CFOA-BASED VOLTAGE CONTROLLED

QUADRATURE OSCILLATOR

A Project Report Submitted

in Partial Fulfilment of the Requirements
for the Degree of

BACHELOR OF TECHNOLOGY
in
Electronics and Communication Engineering

by

Pragati Gupta (Univ. Roll. No. 180010770169)

Samriddhi Shah (Univ. Roll. No. 180010770209)
Diksha Verma (Univ. Roll. No. 180010770091)
Anubhav Kumar (Univ. Roll. No. 180010770300)

Under the Guidance of

Dr. Manoj Kumar Jain

FACULTY OF ENGINEERING AND TECHNOLOGY

UNIVERSITY OF LUCKNOW, LUCKNOW
2020-2021
 DECLARATION

We hereby declare that this submission is our own work and that, to the best of our

knowledge and belief. It contains no material previously published or written by another

person or material which to a substantial extent has been accepted for the award of any other

degree or diploma of the University or other institute of higher education, except where due

acknowledgement has been made in the text.

Pragati Gupta
(180010770169)
Date: 26th July,2021

Samriddhi Shah
(180010770209)
Date: 26th July,2021

Diksha Verma
(180010770091)
Date: 26th July,2021

Anubhav Kumar
(180010770300)
Date: 26th July,2021

ii
 CERTIFICATE

Certified that Pragati Gupta (Univ. Roll No.180010770169), Samriddhi Shah (Univ. Roll

No. 180010770209), Diksha Verma (Univ. Roll No. 180010770091) and Anubhav Kumar

(Univ. Roll No. 180010770300) has carried out the project work presented in this project

report entitled “CFOA based Voltage Controlled Quadrature Oscillator” for the award

of Bachelor of Technology (Electronics and Communication Engineering) from Faculty of

Engineering and Technology, University of Lucknow, Lucknow under my guidance. The

project report embodies results of original work, and studies are carried out by the students

themselves and the contents of the project report do not form the basis for the award of any

other degree to the candidate or to anybody else from this or any other University/Institution.

(Dr. Manoj Kumar Jain)

(Assistant Professor)

iii
 ABSTRACT

Analog circuits are the circuits which are free to deal from zero to full power
supply. Unlike digital which is constrained to specific values, analog circuit takes the con-
tinuous form. These circuits take up the analog signal and manipulate it either by decreasing
or increasing the amplitude, removing noise etc. It is not a single block rather it is a combi-
nation of various circuits elements and building blocks that makeup the analog circuits. The
major circuits like filters and oscillators are in great demand and multiple literatures have
been proposed till now.

In this project we aim to design a new CFOA based Voltage-Controlled Quad-

rature Oscillator circuit. Initially we have done the case study of already proposed CFOA
based Single Resistance Controlled Quadrature Oscillator. We have summarised the results
of various analysis of the mentioned oscillator like Transient, Fourier, THD after verification
of the given waveforms and equations and present all theories related to it. Further we have
the implemented the circuit on breadboard and verified the given theoretical and simulated
results.
After studying multiple literature, we eventually designed a CFOA based voltage
control quadrature oscillator circuit in which the frequency of oscillation is varied through
control voltage of analog multiplier. To verify the designed oscillator, the circuit is simulated
on P-SPICE and various analysis like Transient, Fourier and Monte Carlo are performed.
The results are presented in graphical and tabular manner along with theory which verifies
the newly designed oscillator.

iv
 ACKNOWLEDGEMENT

It is our privilege to express our sincerest regards and respect to our project co-
ordinator, Dr M.K. Jain for his valuable inputs, guidance, encouragement, whole-hearted
cooperation, and constructive criticism throughout the duration of our project. His lectures
on Analog Signal Processing were of great value in designing the circuit and solving and
simulation of this research paper.

We would also like to thank our staff teachers of Lab for their constant support
in providing access to the lab whenever we needed. We are especially grateful to his endless
patience, highly valued advice, and helpfulness in solving our queries in obtaining simula-
tion results and hardware results.
We take this opportunity to thank all our lecturers who have directly or indirectly
helped our project. We express our thanks to our friends for their corporation and verbal
support despite not being the part of this project. Last but not the least we pay our respect
and love to our parents and other family members for their love and encouragement through-
out our career.
Thanking you all.

Pragati Gupta (180010770169)

Samriddhi Shah (180010770209)

Diksha Verma (180010770091)

Anubhav Kumar (180010770300)

v
 TABLE OF CONTENTS

DECLARATION ............................................................................................................. ii
ABSTRACT .................................................................................................................... iv
ACKNOWLEDGEMENT............................................................................................... v
LIST OF FIGURES...................................................................................................... viii
LIST OF ABBREVIATIONS ………………………………………………………..…. ix
CHAPTER 1 : INTRODUCTION .................................................................................. 1
1.1 OSCILLATORS ................................................................................................ 1
1.2 CIRCUIT OPERATION OF OSCILLATOR .................................................. 2
1.3 HISTORY .......................................................................................................... 4
1.4 ROLE OF OSCILLATOR CIRCUITS IN DIGITAL AND ANALOG
CIRCUITS ................................................................................................................... 4
1.5 CLASSIFICATION OF OSCILLATORS ....................................................... 6
1.6 VCO AND ITS APPLICATIONS ................................................................... 12
1.6.1 Types of VCO ........................................................................................... 12
1.6.2 Applications .............................................................................................. 14
CHAPTER 2 : LITERATURE REVIEW .................................................................... 16
INTRODUCTION ........................................................................................... 16
SRCO ............................................................................................................... 16
VCO ................................................................................................................. 18
CHAPTER 3 : ANALYSIS OF SRCQO AND DESIGN OF VCQO ........................... 23
3.1 INTRODUCTION ........................................................................................... 23
3.2. ABOUT CFOA AND AM ............................................................................... 23
3.3. ANALYSIS OF SRC QUADRATURE OSCILLATOR ................................ 25
3.3.1 Verification of Ideal Results..................................................................... 26
3.3.2 Verification of Non-Ideal Results ............................................................ 27
3.4. VERIFICATION OF SIMULATION RESULTS .......................................... 32
3.5. EXPERIMENTAL RESULTS ........................................................................ 34
3.6. DESIGN OF VCQO USING CFOA AND AM .............................................. 36
3.7. THEORETICAL ANALYSIS OF THE CIRCUIT........................................ 36
CHAPTER 4 : SIMULATED RESULT ANALYSIS ................................................... 40
4.1. INTRODUCTION ........................................................................................... 40

vi
 4.2. SIMULATION RESULTS .............................................................................. 42
4.2.1 Transient Results ...................................................................................... 43
4.2.2 Fourier Results ......................................................................................... 44
4.2.3 Total Harmonic Distortion (THD) Results .............................................. 44
4.2.4 Monte Carlo Results................................................................................. 45
4.2.5 Variation of Frequency with Control Voltage......................................... 45
4.3. REMARKS ...................................................................................................... 46
CHAPTER 5 : FINAL CONCLUSION AND FUTURE SCOPE ................................ 47
5.1. INTRODUCTION ........................................................................................... 47
5.2. CONCLUSIONS ............................................................................................. 47
5.3. SCOPE FOR IMPROVEMENT ..................................................................... 48
5.4. FUTURE SCOPE ............................................................................................ 48
REFERENCES .............................................................................................................. 49
Appendix A – Data Sheet of AD844

Appendix B – Data Sheet of AD633

CURRICULUM VITAE

vii
 LIST OF FIGURES

Fig. 1.1 Block diagram of oscillator .................................................................................................1

Fig. 1.2 Digital Oscillator.................................................................................................................5
Fig. 1.3 Analog Oscillator ................................................................................................................6
Fig. 1.4 Classification of oscillator ...................................................................................................6
Fig. 1.5 RC phase shift oscillator .....................................................................................................8
Fig. 1.6 Wein Bridge Oscillator .......................................................................................................8
Fig. 1.7 Tuned LC Oscillator ............................................................................................................9
Fig. 1.8 Hartley Oscillator ............................................................................................................. 10
Fig. 1.9 Colpitts Oscillator ............................................................................................................. 10
Fig. 1.10 Clapp Oscillator .............................................................................................................. 12
Fig. 1.11 Principle of push pull oscillator....................................................................................... 13
Fig. 1.12 Voltage Controlled; emitter coupled multivibrator ......................................................... 13
Fig. 1.13 Basic Voltage Control Ring Oscillator …………………………………………………………………………….14
Fig. 2.1 SRC RC oscillator .............................................................................................................. 16
Fig. 2.2 SRCO using FTFN and OTA. ............................................................................................... 17
Fig. 2.3 SRCO using Current Conveyor. ......................................................................................... 18
Fig. 2.4 Op-amp based VCO using CMOS Technology. ................................................................... 19
Fig. 2.5 OTA based Voltage Controlled Oscillator .......................................................................... 19
Fig. 2.6 VCO using Current Conveyor. ........................................................................................... 20
Fig. 2.7 CFOA based VCO using JFET. ............................................................................................ 21
Fig. 2.8 VCO circuit using Analog Multiplier. ................................................................................. 22
Fig. 3.1 CFOA- building block ........................................................................................................ 23
Fig. 3.2 Matrix form of CFOA ideal conditions............................................................................... 24
Fig. 3.3 CFOA symbol.................................................................................................................... 24
Fig. 3.4 Analog Multiplier ............................................................................................................. 24
Fig. 3.5 CFOA based controlled quadrature oscillator. .................................................................. 25
Fig. 3.6 Transient Analysis of SRCO ............................................................................................... 32
Fig. 3.7 Frequency Spectrum ........................................................................................................ 33
Fig. 3.8 Frequency vs R1 graph ...................................................................................................... 33
Fig. 3.9 Experimental Setup of circuit on breadboard …………………………………….……………………………34
Fig. 3.10 Transient waveform of quadrature outputs.................................................................... 35
Fig. 3.11 Lissajous Pattern of SRCO quadrature outputs ............................................................... 35
Fig. 3.12 Proposed CFOA based VC sinusoidal quadrature oscillator configuration. ...................... 36
Fig. 4.1 Simulated output Waveform of V (28) and V (91) ............................................................. 43
Fig. 4.2 Lissajous Pattern .............................................................................................................. 43
Fig. 4.3 Simulated Frequency Spectrum........................................................................................ 44
Fig. 4.4 Monte Carlo Analysis ....................................................................................................... 45
Fig. 4.5 Frequency (f) vs Control Voltage (Vc) Graph ..................................................................... 45

viii
 LIST OF ABBREVIATIONS

SRCO Single Resistance Controlled Oscillator

SRCQO Single Resistance Controlled Quadrature Oscillator
VCO Voltage Control Oscillator
VCQO Voltage Control Quadrature Oscillator
CFOA Current Feedback Operational Amplifier
AM Analog Multiplier
OTA Operational Transconductance Amplifier
FO Frequency of Oscillation
CO Condition of Oscillation

ix
 CHAPTER 1

INTRODUCTION

1.1 OSCILLATORS

Oscillator is the circuit which produces a continuous, repeated, alternating wave-

form without providing any regular input. Oscillators convert unidirectional current flow
from a DC source into an alternating waveform which is of the desired frequency, as decided
by its passive components of the circuit.
Practically, oscillators are the amplifier circuits which are provided with feed-
back i.e., positive, or regenerative feedback wherein some fraction of the output signal is fed
back to the input (Fig.1.1). In this amplifier there is an amplifying active element that might
be a transistor or an Op-Amp. The back-fed signal which is in phase is responsible to main-
tain the oscillations by making-up for the losses in the circuit due to continuous oscillations.

In general, we call oscillators as generators. Oscillators are energy converters

that convert DC energy to equivalent AC energy. The frequency range of the oscillations lies
in between 1 Hz to 300 GHz.

Block Diagram of Oscillator

Fig. 1.1 Block diagram of oscillator

1
1.2 CIRCUIT OPERATION OF OSCILLATOR

Here we will discuss about the circuit operations involved in the Oscillator. Let
Vi be the input applied at the input terminal of an amplifier having open loop gain A. Feed-
back network with feedback fraction β. The output of amplifier is V o and of feedback net-
work is Vf. β is the part of output which is provided as feedback to input.
1. Vi is applied to the terminal of the amplifier, making the output at the amplifier as
Vo=AVi.
2. Vo voltage is then provided to the feedback network.
3. Output of the feedback amplifier is given as Vf = β Vo=AβVi as Vo = AVi
4. For 0º phase shift, the output signal of the amplifier will be given as,
Vo = A (Vi - βVo)
Vo = AVi - AβVo
AVi = Vo + AβVo
AVi = Vo (1 + Aβ)
We get the closed loop gain of the oscillator with feedback as-
𝑉𝑜 𝐴
𝐺= =
𝑉𝑖 1 + 𝐴β
If we remove the original input signal and continue only with output of the feed-
back circuit at the input of the amplifier, loop gain of the oscillator is responsible for sus-
tained oscillations.

a. If the open loop gain is less than one i.e, Aβ < 1. Then after some period, the output will
fade. As AβVi is input to amplifier, so it is less than Vi and Aβ will be less than unity.
So, it will be reduced after each cycle, resulting in the decaying oscillations as the output.

b. If the open loop gain is greater than one i.e, Aβ > 1. Then after some period, the output
will add to. As AβVi is input to amplifier, so it is greater than Vi and Aβ will be greater
than unity. So, it will be accelerated after each cycle, resulting in the increasing oscilla-
tions as the output.

2
c. If the open loop gain is equal to one i.e, Aβ=1. Then Vf = Vi. Now it is a continuous
sinusoidal waveform, resulting in the constant oscillations as an output.

We always start with the loop gain slight greater than 1 to build up the oscilla-
tions. But once a certain voltage is achieved then loop gain is equal to unity and provides
constant oscillations.

Barkhausen Criteria
Barkhausen Criteria state following two conditions to achieve sustained oscilla-
tions which are mentioned below: -

1. Open loop gain should be slightly greater than or equal to 1 which means Aβ ≥ 1.
2. There should be overall phase shift equal to zero in the circuit. Input and output signal
needs to be in phase with each other.
These conditions provide sustained oscillations at the output.

3
1.3 HISTORY

In September of 1912, Edwin Howard Armstrong was experimenting with Lee DeForest’s
new device the audion (what we now call the triode vacuum tube). These devices had been
successfully used as an AM detector, but no one quite knew how or why the device worked,
or what other applications of the device there might be. By coupling one terminal of the
device to another, Armstrong found that he could achieve large signal gain and thus built the
first electronic amplifier. He called the process “regeneration” which we know it today as
positive feedback. The electronic amplifier would revolutionize radio, but Armstrong has
different plans. He found that as he adjusted his amplifier to achieve maximum gain, the
circuit would suddenly begin to “squeal”. This was disappointing at first, but then Armstrong
realized this “squeal” was a high-frequency signal and the circuit was oscillating. Armstrong
had increased his feedback to the point that the circuit had become unstable, and their poles
were in the right-half plane. Eventually Armstrong had made the first electronic oscillator
which would revolutionize radio. He had created the components necessary to make Contin-
uous Wave (CW) radio practicable. Reminding that radio at that time was primarily wireless
telegraphy (i.e., dots and dashes). CW radio is required to transmit audio information (e.g.,
music and voice). Engineers at that time had already made some CW radio systems, using
electromechanical oscillators, but they could only create signals in the kHz range at their
best. With Armstrong’s oscillator, CW signals at high frequencies could be easily generated.
Along with the amplifier, the electronic oscillator allowed for the creation of reliable, low-
cost radio systems with clear and audible sound. Although these inventions gave a tremen-
dous boost to the radio industry, a major technical problem remained which Armstrong
solved it later.

1.4 ROLE OF OSCILLATOR CIRCUITS IN DIGITAL AND ANALOG

CIRCUITS

1. Digital Oscillators

The circuit of a digital oscillator is an analog oscillator that clips, depending on

the way you look at it. A common 'digital' oscillator is the Pierce oscillator which was in-
vented by George W. Pierce in 1923.

It has been used from an exceptionally long time for microprocessor clock gen-
eration and when we have a microcontroller that requires a crystal and two external capaci-
tors for generating its own clock, the chances are that we are making a Pierce oscillator us-
ing the internal inverter and resistor.

4
 Fig. 1.2 Digital Oscillator

Digital oscillators are complicated than simply generating a single clock signal
and they may generate different signals with a defined phase shift, or they can have a fre-
quency synthesizer that generate one or more alternative frequencies with a fixed frequency
input clock. The output may be square or a clipped sine wave (rarely a true sine for a digital
system). We need to know what accuracy and stability you require. Oscillators based on
quartz crystal will be 10 times better than that, usually more. Similarly, a quartz-based os-
cillator will be having better stability than a ceramic resonator based one. Stability is defined
as temperature, load, or supply stability – all of which can affect the frequency. Digital os-
cillators are more reliable than VCOs, because the oscillators are not generated with the help
of physical components, where physical components can often break down by the time.
A VCXO is a voltage-controlled crystal oscillator which generally allows the
frequency to be “pulled” by a little amount while it still had high stability. Frequency adjust-
ment range is generally limited to approximately 200ppm.
An OCXO is oven controlled. They have the oscillator in an oven or may be in
a double oven where the circuitry and crystal are heated to a constant temperature. Once they
get warmed up, they become very precise and stable. They take a good amount of power as
the heater requires.

2. Analog Oscillator

For an analog oscillator we are more likely to be expecting for a sinusoidal wave.
There were various 'standard' analog oscillator designs which have been around there since
before the transistors existed. Hartley, Colpitts and Clapp for example. They are used as sine
wave oscillators by using inductors and capacitors as their frequency determining compo-
nent and with quartz crystals. They are used as variable frequency oscillators when they are
used with inductors or capacitors as well. Other oscillators such as the Wien bridge oscillator
use resistors and capacitors for determining the frequency, but they are more likely to be
limited to lower frequencies than inductor/capacitor or crystal oscillators.

5
 For example, here is an 10MHz Clapp oscillator in which the output is being
taken from the source of the transistor Q1.

Fig. 1.3 Analog Oscillator

We should have one thing in our mind with all oscillators is that they take time
to start. Having high Q oscillators like crystal oscillators this can be quite significant as the
startup time which is measured in number of clock cycles is proportional to the Q of the
circuit. This will result in a significant delay before anything seems to happen and it will
also result in the frequency being incorrect initially.
In a Resistor Capacitor oscillator circuit, higher input voltages will increase the
rate of charge in the capacitor plates, which decreases the time required for one full oscilla-
tion. Feedback loops are constructed by routing the output signal back into the input of the
amplifier, basically it results in analog distortion favored by synthesizer enthusiasts.

1.5 CLASSIFICATION OF OSCILLATORS

Fig. 1.4 Classification of oscillator

6
Electronic oscillators are classified mainly into the following two categories: -

1. Sinusoidal Oscillators

The oscillators that produce an output having a sine waveform are called sinus-
oidal or harmonic oscillators. Such oscillators can provide output at frequencies ranging
from 20 Hz to 1 GHz.
Sinusoidal oscillators can be classified in the following categories −
a) RC Oscillators

There oscillators use resistors and capacitors and are used to generate low or
audio-frequency signals. Thus, they are also known as audio-frequency (A.F.) oscillators.
Example of such oscillators are Phase –shift and Wein-bridge oscillators.

i) Phase Shift Oscillator

It is a linear electronic oscillator circuit that produces a sine wave output. It con-
sists of an inverting amplifier element such as a transistor or op amp with its output fed back
to its input through a phase-shift network consisting of resistors and capacitors in a ladder
network. The feedback network 'shifts' the phase of the amplifier output by 180 degrees at
the oscillation frequency to give positive feedback. Phase-shift oscillators are often used at
audio frequency as audio oscillators. The filter produces a phase shift that increases with
frequency. It must have a maximum phase shift of more than 180 degrees at high frequencies
so the phase shift at the desired oscillation frequency can be 180 degrees. The most common
phase-shift network cascades three identical resistor-capacitor stages which produce a phase
shift of zero and 270° at low frequencies and high frequencies, respectively.
Frequency of Oscillation should be
1
𝑓0 =
2𝜋𝑅𝐶√6

And Closed Loop Gain should be Rfb = 29R

7
 Fig. 1.5 RC phase shift oscillator

ii) Wien Bridge Oscillator

It is a type of electronic oscillator that generates sine waves. It can generate a

large range of frequencies. The oscillator is based on a bridge circuit originally developed
by Max Wien in 1891 for the measurement of impedances. The bridge comprises four re-
sistors and two capacitors. The oscillator can also be viewed as a positive gain amplifier
combined with a band pass filter that provides positive feedback. Automatic gain control,
intentional nonlinearity and incidental non-linearity limit the output amplitude in various
implementations of the oscillator. The circuit shown below shows a once-common imple-
mentation of the oscillator, with automatic gain control using an incandescent lamp. Under
the condition that R1=R2=R and C1=C2=C, the frequency of oscillation is given by: -
1
𝑓0 =
2𝜋𝑅𝐶
And Closed Loop Gain should be, Rb = Rf/2

Fig. 1.6 Wein Bridge Oscillator

8
b) Tuned Circuit Oscillators / LC Oscillator

In an LC oscillator circuit, the filter is a tuned circuit (often called a tank circuit;
the tuned circuit is a resonator) consisting of an inductor (L) and capacitor (C) connected.
Charge flows back and forth between the capacitor's plates through the inductor, the tuned
circuit can store electrical energy oscillating at its resonant frequency. There are small losses
in the tank circuit, but the amplifier compensates for those losses and supplies the power for
the output signal. LC oscillators are often used at radio frequencies when a tuneable fre-
quency source is necessary, such as in signal generators, tuneable radio transmitters and
the local oscillators in radio receivers. Typical LC oscillator circuits is shown in Fig.1.7

Fig. 1.7 Tuned LC Oscillator

i) Hartley Oscillator

It is an electronic oscillator circuit in which the oscillation frequency is deter-

mined by a tuned circuit consisting of capacitors and inductors, that is, an LC oscillator. The
circuit was invented by American engineer Ralph Hartley in 1915. The distinguishing fea-
ture of the Hartley oscillator is that the tuned circuit consists of a single capacitor in parallel
with two inductors in series (or a single tapped inductor), and the feedback signal needed
for oscillation is taken from the centre connection of the two inductors.
The frequency of oscillation is approximately the resonant frequency of the tank
circuit. If the capacitance of the tank capacitor is C and the total inductance of the tapped
coil is L, then If two uncoupled coils of inductance L1 and L2 are used.

9
 1
𝑓0 =
2𝜋√𝐿. 𝐶
Where L = L1 + L2

Fig. 1.8 Hartley Oscillator

ii) Colpitts Oscillator

The Colpitts Oscillator design uses two centre-tapped capacitors in series with a
parallel inductor to form its resonance tank circuit producing sinusoidal oscillations. In many
ways, the Colpitts oscillator is the exact opposite of the Hartley Oscillator we looked at in
the previous tutorial. Just like the Hartley oscillator, the tuned tank circuit consists of an LC
resonance sub-circuit connected between the collector and the base of a single stage transis-
tor amplifier producing a sinusoidal output waveform. The basic configuration of the Col-
pitts Oscillator resembles that of the Hartley Oscillator but the difference in this is that the
centre tapping of the tank sub-circuit is now made at the junction of a “capacitive voltage
divider” network instead of a tapped auto-transformer type inductor as in the Hartley oscil-
lator.

Fig. 1.9 Colpitts Oscillator

iii) Clapp oscillator

Another oscillator which is an advanced version of Colpitts oscillator is

the Clapp Oscillator. This circuit is designed by making a few changes to the Colpitts os-
cillator. The circuit differs from the Colpitts oscillator only in one respect; it contains one
additional capacitor (C3) connected in series with the inductor. The addition of capacitor (C3)

10
improves the frequency stability and eliminates the effect of transistor parameters and stray
capacitances.
The operation of Clapp oscillator circuit is in the same way as that of Colpitts
oscillator. The frequency of oscillator is given by the relation,

𝑓0 = 12𝜋√𝐿. 𝐶
where
1
𝐶=
(𝐶1 + 𝐶2 + 𝐶3 )

Usually, the value of C3 is much smaller than C1 and C2. As a result of this, C is
approximately equal to C3. Therefore, the frequency of oscillation,
1
𝑓0 =
2𝜋√𝐿. 𝐶3

It is understood that the Clapp oscillator is like the Colpitts oscillator, however
they differ in the way the inductances and capacitances are arranged. The frequency stability
though is good, can be variable in a Clapp oscillator. A Clapp oscillator is sometimes pre-
ferred over a Colpitts oscillator for constructing a variable frequency oscillator. The Clapp
oscillators are used in receiver tuning circuits as a frequency oscillator.
The following circuit diagram (Fig.1.10) shows the arrangement of a transistor
Clapp oscillator.

Fig. 1.10 Clapp Oscillator

11
2. Non-sinusoidal Oscillators / Relaxation Oscillator

The oscillators that produce an output having a square, rectangular or saw-tooth

waveform are called non-sinusoidal or relaxation oscillators. Such oscillators can provide
output at frequencies ranging from 0 Hz to 20MHz. A nonlinear or relaxation oscillator pro-
duces a non-sinusoidal output, such as a square, sawtooth or triangle wave. It consists of an
energy-storing element (a capacitor or rarely, an inductor) and a nonlinear switching device
(a latch, Schmitt trigger, or negative resistance element) connected in a feedback loop. The
switching device periodically charges and discharges the energy stored in the storage ele-
ment thus causing abrupt changes in the output waveform. Square-wave relaxation oscilla-
tors are used to provide the clock signal for sequential logic circuits such as timers and coun-
ters, although crystal oscillators are often preferred for their greater stability. Triangle-wave
or sawtooth oscillators are used in the time base circuits that generate the horizontal deflec-
tion signals for cathode ray tubes in analogue oscilloscopes and television sets. These are
also used in voltage-controlled oscillators (VCOs), inverters and switching power supplies,
dual-slope analog to digital converters (ADCs) and in function generators for the purpose of
generating square and triangle waves for testing equipment. Generally, relaxation oscillators
are used at lower frequencies and have poorer frequency stability in comparison to linear
oscillators.

1.6 VCO AND ITS APPLICATIONS

A Voltage controlled Oscillator is an electronic oscillator whose frequency of

oscillation is dependent on its applied input voltage. These types of circuits are beneficial in
tracking and matching signal frequencies to avoid shifting due to thermal variations, power
supply fluctuations, and other sources of frequency phase-shifts. VCOs are found particu-
larly often in phase-locked loops (PLLs) used for clock generation and synchronization.
PLLs combine the variable frequency characteristics of the VCO with a phase detector cir-
cuit to track a signal as it changes frequency.

1.6.1 Types of VCO

VCOs are basically classified into three types: - push pull oscillators, relaxation
oscillators and ring oscillators.

 Push Pull Oscillator

Push Pull oscillators are electronic circuits used for generating vibrations. Its
uses two electronic switches that alternately conduct electricity. In high application fre-
quency applications, it generates a sinusoidal oscillation with few even harmonics.

12
 Fig. 1.11 Principle of push pull oscillator

Push Pull VCO is a balance circuit that contain two identical and symmetric
circuits. The above diagram is of push pull VCO for wide band applications. Even mode
suppressions are realized by a resistor Res connected to a fundamental virtual-ground node,
therefore no even mode oscillations at fundamental frequency can occur.

 Relaxation Oscillators

Relaxation oscillator (multivibrator) are the types of oscillators which are mostly
used in IC design. The circuit oscillates by continuously charging and discharging a capaci-
tor between two voltage levels.

Fig. 1.12 Voltage Controlled; emitter coupled multivibrator

A voltage-controlled emitter coupled multivibrator is shown in Fig.1.12. Alt-

hough the circuit require a smaller number of devices the oscillation frequency is partially

13
dependent upon the capacitor value and is rather sensitive to thermal effects due to their
dependence upon the device VBE.

 Ring Oscillators

Unlike multivibrator, the basic circuit block of ring oscillator based VCO consist
of variable delay cell that is voltage controlled. Connecting multiple delay elements as a ring
oscillator, the circuit will oscillate with a period equal to the voltage-controlled cell delay
multiplied by twice the number of delay stages. One of the examples of ring oscillator based
VCO is shown in Fig 1.13.

Fig. 1.13 Basic Voltage Control Ring Oscillator

1.6.2 Applications

 Function generator
 Phase Locked Loop
 Tone generator
 Frequency-shift keying
 Frequency modulation

In this chapter brief introduction of Oscillator, its classification and their appli-
cations have been discussed.

In chapter 2 literature review of surveyed results is presented. Using different

building blocks and elements like OP-amp, OTA, Current Conveyor, CFOA etc, multiple
circuits of Single resistance control and Voltage control oscillators are designed. Out of all
some of them have been discussed in this chapter.

In chapter 3 after reviewing the surveyed results, case study of Single resistance-
controlled quadrature oscillator is discussed. Verification of already proposed oscillator re-
sults is done and its experimental analysis is presented. Moreover, a new voltage control
quadrature oscillator is designed, and its theoretical analysis has been performed.

14
 In chapter 4 simulation results of the newly designed oscillator is presented. Var-
ious analysis like transient, fourier and monte carlo is performed and inferences are drawn
from the waveforms obtained.

In chapter 5 conclusion of all the previous chapters are discussed. Also, the scope
of improvement of the designed oscillator and its future work aiming to improve its effi-
ciency is presented.

15
 CHAPTER 2

LITERATURE REVIEW

INTRODUCTION

Single resistance-controlled oscillator (SRCO) refers to a block that generates a

continuous periodic, oscillating electronic signal, whose frequency of oscillation (F.O.) and
condition of oscillation (C.O.) are controllable by a separate individual resistive element. It
finds numerous applications in control systems, signal processing, communication, and in-
strumentation and measurement systems. Moreover, some circuits also find attraction for IC
fabrication. Alike SRCO, Voltage Control Oscillator (VCO) also find the popularity due to
the applications as discussed in Chapter 1. The difference lies in the fact that in VCO the
frequency of oscillation is controlled by the control voltage Vc rather than any single passive
element resistor or capacitor. Multiple literatures of SRCO and VCO have been proposed
till now using different building blocks and active elements. In this chapter literature review
of various oscillator circuits of SRCO and VCO using different blocks have been discussed.

SRCO

Operational Amplifiers are the most used basic building block of analog circuits.
In literature [1] a SRC RC oscillator using a single OP-AMP is proposed as shown in Fig.2.1.
which requires only one OP-AMP and six resistor and three grounded capacitors. The pro-
posed circuit find suitability in low frequency oscillator and seems attractive for IC imple-
mentation.

Fig. 2.1 SRC RC oscillator

16
 The oscillation condition and frequency of oscillation is given by Eqn. (2.1)
and Eqn. (2.2), respectively.
𝐶2 𝑅1 𝑅2 𝐶1 𝑅1 𝑅5
𝐶3 𝑅4 = 𝐶1 𝑅1 + 𝐶2 𝑅2 + 𝐶2 𝑅1 + + (2.1)
𝑅5 𝑅6

𝑅1 𝑅 𝑅 𝑅 𝑅 𝑅
1 + 2+ 1+ 1 2 − 4
𝑓= √𝑅6 𝑅6 𝑅5 𝑅5 𝑅6 𝑅3 (2.2)
2𝜋 𝐶1 𝐶2 𝑅1 𝑅2

From Eq.2.1 and Eq.2.2 it is evident that frequency of oscillation can be varied
by varying the single resistance R3 without affecting the oscillation condition which is inde-
pendent of R3. The circuit presented can readily be employed into voltage control oscillator
by replacing the resistor R3 with field effect transistor voltage variable resistor.

Another SRCO using operational transconductance amplifier (OTA) and four

terminals floating nullor (FTFN) is proposed in literature [2] as shown in Fig. 2.2. The circuit
employs one OTA, one positive FTFN and passive components which are grounded.

Fig. 2.2 SRCO using FTFN and OTA.

The frequency of oscillation and condition oscillation is given by Eqn. (2.3) and
Eqn. (2.4), respectively.

(2.3)

(2.4)

The condition of oscillation is electronically controlled by transconductance of

OTA. From Eqn. (2.4) it is inferred that the frequency of oscillation is independently con-
trolled through resistor R1. This circuit also promises voltage-controlled oscillation if R1 is
replaced by FET or OTA configured as resistor.

17
 Besides these SRCO using current conveyor are also have been widely re-
searched. For instance, the circuit in literature [3] uses CCII+ and CCII- along with minimum
number of passive components i.e., two resistors and two capacitors as shown in Fig.2.3.

Fig. 2.3 SRCO using Current Conveyor.

Considering the ideal conditions of current conveyor, the condition and fre-
quency of oscillation is given by Eqn. (2.5) and Eqn. (2.6), respectively.

(2.5)

(2.6)

From above two equations, it is evident that the condition of oscillation is de-
pendent on grounded capacitors C1 and C2 while the frequency of oscillation is controlled
by grounded resistor R1 or floating resistance R2 without disturbing the condition of oscil-
lation. The circuit also has low passive sensitivities which is evident from Eqn. (2.7).

(2.7)

VCO

As already mentioned above, voltage-controlled oscillators (VCO) find various

applications in instrumentations, electronics, and communication system. Several literatures

18
based on voltage-controlled oscillator has been published till now using different active el-
ements and building blocks. Starting with the basic building block Operational Amplifier,
VCO using CMOS technology is presented in literature [4]. The circuit is shown in Fig.2.4.

Fig. 2.4 Op-amp based VCO using CMOS Technology.

Using only two passive components i.e., resistor and grounded capacitor a sim-
ple sine- wave oscillator is introduced which uses the op-amp compensation poles. The cir-
cuit is design such that it can generate sinusoidal frequencies nearly equal to the geometric
mean of the two 0.18um CMOS technology op-amps used.
The circuit in literature [5] uses OTA as an active building block for implement-
ing VCO using commercially available IC LM13700 as shown in Fig. 2.5. The proposed
oscillator is a third order oscillator which is made by cascading three first order OTA-C
filters (Fig. 3 OTA low pass filter as cited therein [5]).

Fig. 2.5 OTA based Voltage Controlled Oscillator

19
 The expression for frequency oscillation of given oscillator is given by Eqn. (2.8)
which shows that oscillation frequency is controlled by varying the bias voltage V c.

𝑔𝑚 𝑘 (𝑉𝑐 + 13.9)
𝑓𝑛 = √3 𝑘 = √3 19.2 (2.8)
𝐶 2𝜋𝐶 3𝑅𝑏𝑖𝑎𝑠
(Vc is the control voltage common to all three OTAs and R bias is the bias resistance.)
The proposed circuit provide linear relationship between frequency of third order
oscillator and control voltage.

Alike SRCO, current conveyor also finds considerable attention in designing of

VCOs. In literature [6] current conveyor (CCII+) is used as an active element which is built
by replacing the timing capacitance C (Fig.1 as cited therein [6]) by frequency control block
as shown in Fig. 2.6.

Fig. 2.6 VCO using Current Conveyor.

The proposed circuit has wide frequency range with large output frequency pull-
ing coefficient.

Besides this, CFOA also find considerable attention in the repertoire of VCOs
due to their several advantages that will be discussed in the later chapters. In literature [7]
the circuit (Fig.2.E as cited therein [6]) uses two CFOAs and one FET along with six passive
components as shown in Fig 2.7. The frequency of oscillation is given by Eqn. (2.9).

20
 Fig. 2.7 CFOA based VCO using JFET.

1
𝑓0 = (2.9)
2𝜋√𝐶1 𝐶2 𝑅𝑚 𝑅3

2𝑉𝑝2
Where F.O is controlled by 𝑅𝑚 = 𝑟𝐷𝑆 = thus dependent on Vc.
𝐼𝐷𝑆𝑆(𝑉𝐶 −2𝑉𝑝 )

In this literature total seven circuits were proposed using AD844 CFOAs and
BFW10 FETs. All the circuits proposed have following advantageous features such as: -

 Low sensitivity to component tolerance due to absence of difference term in the expres-
sion of frequency.
 Control over frequency of oscillation through single variable resistor
 Availability of explicit current mode output
Besides the method used to realize VCO as in [7] an additional technique is pro-
posed using analog multiplier, commercially available as AD633 IC, in which the condition
of oscillation and frequency of oscillation are independently controlled by control voltage
Vc provided by analog multiplier.
In literature [8], one such oscillator is proposed which employs three CFOAs
along with three analog multipliers including five passive components as shown in Fig.2.8.
The condition and frequency of oscillation is given by Eqn. (2.10) and Eqn. (2.11), respec-
tively.

21
 Fig. 2.8 VCO circuit using Analog Multiplier.

CO: C1R1 + C2R2 ≤ A1C2R1 (2.10)

𝐴 1 (2.11)
𝐹𝑂: 𝑓𝑜 = 2𝜋2 √𝐶
1 𝐶2 𝑅1 𝑅2

From the two equations it is evident that both C.O and F.O are controlled inde-
pendently by the gains of analog multipliers. Also, it is seen that F.O is directly proportional
to A2 which proves that the circuit is a linear VCO.

22
 CHAPTER 3

ANALYSIS OF SRCQO AND DESIGN OF VCQO

3.1 INTRODUCTION

Multiple literatures are published based on SRC oscillator [9-13] among which
the proposed circuit in [13] was the first Single resistance-controlled quadrature1 oscillator.
It was CFOA based single resistance-controlled quadrature oscillation whose oscillation fre-
quency and condition of oscillation depends on two different resistances thus provide inde-
pendent control of both. In this chapter the analysis of SRCO is done and design of voltage
control quadrature oscillator has been presented.

3.2. ABOUT CFOA AND AM

 AD844: Current Feedback Operational Amplifier (CFOA)

The current feedback operational amplifiers (CFOAs) are a very versatile build-
ing block for analog circuit designs. It is essentially a trans linear current conveyor (CCII+)
followed by a trans linear voltage follower (Fig.3.1). It is also known as the transimpedance
operational amplifiers.

Fig. 3.1 CFOA- building block

It provides several advantages over the voltage-mode operational amplifier (VOA), such as:

 Wider and nearly constant bandwidth at low/medium gain

 Relatively much higher slew rate typically 2000V/µS

1
Quadrature outputs are two signals that are 90o out of phase and can be multiplied together to obtain
twice the input frequency.

23
  Requirement of smaller number of external passive components to design various
functional circuits.

The above features implies that CFOA based circuit would generally have rela-
tively higher operational frequency range as compared to the circuits employing traditional
OP-AMP. Also appropriately devised CFOA based structure may not require critical passive
component matching or cancellation constraint to realize the initiated function and therefore
achieve minimum sensitivity to passive component tolerance.

The CFOA are characterised by following hybrid matrix as presented in Fig.3.2.

Fig. 3.3 CFOA symbol

Fig. 3.2 Matrix form of CFOA ideal conditions

Commercially it is available in integrated circuit type AD844.

 AD633: Analog Multiplier (AM)

Analog multiplier is the device consisting of two input ports and one output port.
It is a device that produces an output voltage and current that is proportional to the product
of two or more independent voltages or current.

Fig. 3.4 AM symbol

Besides multiplication it also performs other functions like dividing, squaring,

square rooting and modulation functions.

24
 Eqn. (3.1) is the output voltage equation of four quadrant analog multiplier
where VX1, VX2, VY1, VY2 are the input voltage provided at four input terminals while Vz is
the voltage at compensation node. The output voltage is obtained is V0 which is given by
Eqn. (3.1).
(𝑉𝑋1 − 𝑉𝑋2 )(𝑉𝑌1 − 𝑉𝑌2 )
𝑉𝑜 = + 𝑉𝑧 (3.1)
10

While designing VCOs using AMs one of the terminals is held at steady state
voltage while the other is scaled in proportion to the fixed input. Using the same method, a
voltage-controlled quadrature oscillator is designed as described in Section 3.6.

3.3. ANALYSIS OF SRC QUADRATURE OSCILLATOR

The oscillator to be studied is shown in Fig.3.5. The proposed oscillator config-

uration comprising two CFOAs, three resistors and two capacitors provides two sinusoidal
voltage outputs in phase quadrature.

Fig. 3.5 CFOA based controlled quadrature oscillator.

The circuit has the advantage of independent control of the condition of oscilla-
tion and the oscillation frequency through a single resistor. In addition, the proposed circuit
configurations have good active and passive sensitivity performance and has low impedance
output which can be cascaded to the next stage.

25
 For the verification of presented results the routine circuit analysis is performed
taking ideal and non-ideal conditions of CFOA into consideration as follows: -

3.3.1 Verification of Ideal Results

Considering the ideal conditions of CFOA as:

𝑣𝑧 = 𝑣𝑤

𝑖𝑥 = 𝑖𝑧

𝑣𝑥 = 𝑣𝑦

For CFOA1

𝑣𝑥1
𝑖𝑥 1 =
𝑅1

−𝑣𝑥1
𝑖𝑧1 = −𝑖𝑥1 =
𝑅1

𝑣𝑥1 𝑣𝑧1
(𝑣𝑥1 − 𝑣𝑧1 )𝑠𝐶1 − =
𝑅1 𝑅2

𝑣𝑧1 𝑠𝐶1 𝑅1 𝑅2 − 𝑅2
=
𝑣𝑥1 𝑠𝐶1 𝑅2 𝑅1 + 𝑅1

𝑣𝑧1 = 𝑣01

𝑣01 𝑠𝐶1 𝑅1 𝑅2 − 𝑅2
= (3.2)
𝑣𝑥1 𝑠𝐶1 𝑅2 𝑅1 + 𝑅1

For CFOA2

𝑣01 = 𝑣𝑦2 = 𝑣𝑥2

𝑖𝑥2 = 𝑖𝑧2

𝑣𝑥2
= 𝑣𝑧2 𝑠𝐶2
𝑅3

Now 𝑣𝑧2 = 𝑣02 and 𝑣𝑥2 = 𝑣01

Hence, the relationship between the two outputs voltages 𝑣01 𝑎𝑛𝑑 𝑣02 can be expressed as:

26
𝑣01
= 𝑠𝐶2𝑅3 (3.3)
𝑣02

From Eqn. (3.1) and Eqn. (3.2)

𝑠𝐶1 𝑅1 𝑅2 − 𝑅2
= 𝑠𝐶2 𝑅3
𝑠𝐶1 𝑅2 𝑅1 + 𝑅1

Solving above we get the characteristic equation of the circuit as below: -

1 1 1
𝑠 2 + 𝑠 (𝑅 −𝑅 )+𝑅 =0 (3.4)
2 𝐶1 3 𝐶2 1 𝑅3 𝐶1 𝐶2

Putting s=j𝜔0 and equating imaginary terms to zero in Eqn. (3.3),

we get condition of oscillation and frequency of oscillation respectively as:

𝑅2 𝐶1 = 𝑅3 𝐶2 (3.5)

1
𝜔02 = 𝑅
1 𝑅3 𝐶1 𝐶2

1
 𝜔0 = (3.6)
√𝑅1 𝑅3 𝐶1 𝐶2

3.3.2 Verification of Non-Ideal Results

Considering the non-ideal conditions of CFOA as:

𝑣𝑥 = 𝛽𝑣𝑦

𝑖𝑧 = 𝛼𝑖𝑥

𝑣0 = 𝛾𝑣𝑧

For CFOA1

𝑣𝑥1
𝑖𝑥 1 =
𝑅1

−𝛼1 𝑣𝑥1
𝑖𝑧1 = −𝛼1 𝑖𝑥1 =
𝑅1

𝑣𝑧1
(𝑣𝑥1 − 𝑣𝑧1 )𝑠𝐶1 + 𝑖𝑧1 =
𝑅2

27
 𝛼1 𝑣𝑥1 𝑣𝑧1
(𝑣𝑥1 − 𝑣𝑧1 )𝑠𝐶1 − =
𝑅1 𝑅2

𝑣𝑥1 (𝑠𝐶1 𝑅𝑅2 − 𝛼1 𝑅2 ) = 𝑣𝑧1 (𝑠𝐶1 𝑅1 𝑅2 + 𝑅1 )

𝑣01 = 𝛾1 𝑣𝑧1 and 𝑣02 = 𝑣𝑥1

𝑣01 𝑠𝐶1 𝑅1 𝑅2 𝛾1 −𝑅2 𝛼1 𝛾1

= (3.7)
𝑣02 𝑠𝐶1 𝑅2 𝑅1 +𝑅1

For CFOA2

𝑣01 = 𝑣𝑦2 and 𝑣02 = 𝛾2 𝑣𝑧2

𝑣𝑥2 = 𝛽2 𝑣𝑦2 = 𝛽2 𝑣01

𝑣𝑥2
𝑖𝑥 2 = and 𝑖𝑧2 = 𝑣𝑧2 𝑠𝐶2
𝑅3

𝑖𝑧2 = 𝛼2 𝑖𝑥2

𝛼2 𝑣𝑥2
𝑣𝑧2 𝑠𝐶2 =
𝑅3

𝑣02 𝑠𝐶2 𝛼2 𝛽2 𝑣01

=
𝛾2 𝑅3

𝑣02 𝛼2 𝛽2 𝛾2
= (3.8)
𝑣01 𝑠𝐶2 𝑅3

From Eqn. (3.5) and Eqn. (3.6)

𝑠𝐶2 𝑅3 𝑠𝐶1 𝑅1 𝑅2 𝛾1 − 𝑅2 𝛼1 𝛾1
=
𝛼2 𝛽2 𝛾2 𝑠𝐶1 𝑅2 𝑅1 + 𝑅1

Solving above we get the characteristic equation of the circuit as Eqn. (3.8): -

1 𝛼2 𝛽2 𝛾2 𝛾1 𝛼1 𝛼2 𝛽2 𝛾1 𝛾2
𝑠 2 + 𝑠 (𝑅 − )+ =0 (3.9)
2 𝐶1 𝐶2 𝑅3 𝐶1 𝐶2 𝑅1 𝑅3

Putting s=j𝜔0 and equating imaginary terms to zero in Eqn. (3.8),

we get condition of oscillation as:

𝛽2 𝛼1 𝛼2 𝛾1 𝛾2 𝑅2 𝐶1 = 𝑅3 𝐶2 (3.10)

28
And frequency of oscillation as:

𝛼1 𝑎2 𝛾1 𝛾2
𝜔02 =
𝐶1 𝐶2 𝑅1 𝑅3

𝛼1 𝛼2 𝛽2 𝛾1 𝛾2
 𝜔0 = √ (3.11)
𝐶1 𝐶2 𝑅1 𝑅3

Sensitivity of 𝜔0 with respect to active and passive elements can be obtained as: -
𝜔
𝑆𝛽10 = 0

𝜔 𝜕𝜔0 ∕ 𝜔0
𝑆𝛽20 =
𝜕𝛽2 ∕ 𝛽2

𝜔 1 𝑅1 𝑅3 𝐶1 𝐶2 𝛼1 𝛼2 𝛾1 𝛾2 𝐶1 𝑅3 𝑅1 𝑅3
𝑆𝛽20 = √ ∗ ∗ 𝛽2 ∗ √
2 𝛽2 𝛼1 𝛼2 𝛾1 𝛾2 𝑅1 𝑅3 𝐶1 𝐶2 𝛼1 𝛼2 𝛽2 𝛾1 𝛾2

𝜔 1
𝑆𝛽20 = 2

𝜔 𝜕𝜔0 ∕ 𝜔0
𝑆𝛼10 =
𝜕𝛼1 ∕ 𝛼1

𝜔 1 𝑅1 𝑅3 𝐶1 𝐶2 𝛽2 𝛼2 𝛾1 𝛾2 𝐶1 𝐶2 𝑅1 𝑅3
𝑆𝛼10 = √ ∗ ∗ 𝛼1 ∗ √
2 𝛽2 𝛼1 𝛼2 𝛾1 𝛾2 𝑅1 𝑅3 𝐶1 𝐶2 𝛼1 𝛼2 𝛽2 𝛾1 𝛾2

𝜔 1
𝑆𝛼10 = 2

𝜔 𝜕𝜔0 ∕ 𝜔0
𝑆𝛼20 =
𝜕𝛼2 ∕ 𝛼2

𝜔 1 𝑅1 𝑅3 𝐶1 𝐶2 𝛽2 𝛼1 𝛾1 𝛾2 𝐶1 𝐶2 𝑅1 𝑅3
𝑆𝛼20 = √ ∗ ∗ 𝛼2 ∗ √
2 𝛽2 𝛼1 𝛼2 𝛾1 𝛾2 𝑅1 𝑅3 𝐶1 𝐶2 𝛼1 𝛼2 𝛽2 𝛾1 𝛾2

𝜔 1
𝑆𝛼20 =
2

𝜔 𝜕𝜔0 ∕ 𝜔0
𝑆𝛾10 =
𝜕𝛾1 ∕ 𝛾1

𝜔 1 𝑅1 𝑅3 𝐶1 𝐶2 𝛽2 𝛼1 𝛼2 𝛾2 𝐶1 𝐶2 𝑅1 𝑅3
𝑆𝛾10 = √ ∗ ∗ 𝛾1 ∗ √
2 𝛽2 𝛼1 𝛼2 𝛾1 𝛾2 𝑅1 𝑅3 𝐶1 𝐶2 𝛼1 𝛼2 𝛽2 𝛾1 𝛾2

29
 𝜔 1
𝑆𝛾10 =
2

𝜔 𝜕𝜔0 ∕ 𝜔0
𝑆𝛾20 =
𝜕𝛾2 ∕ 𝛾2

𝜔 1 𝑅1 𝑅3 𝐶1 𝐶2 𝛽2 𝛼1 𝛼2 𝛾1 𝐶1 𝐶2 𝑅1 𝑅3
𝑆𝛾20 = √ ∗ ∗ 𝛾2 ∗ √
2 𝛽2 𝛼1 𝛼2 𝛾1 𝛾2 𝑅1 𝑅3 𝐶1 𝐶2 𝛼1 𝛼2 𝛽2 𝛾1 𝛾2

𝜔 1
𝑆𝛾20 =
2

𝜔 𝜕𝜔0 ∕ 𝜔0
𝑆𝑅10 =
𝜕𝑅1 ∕ 𝑅1

𝜔 1 𝑅1 𝑅3 𝐶1 𝐶2 𝛽2 𝛼1 𝛼2 𝛾1 𝛾2 𝐶1 𝐶2 𝑅1 𝑅3
𝑆𝑅10 = − √ ∗ 2 ∗ 𝑅1 ∗ √
2 𝛽2 𝛼1 𝛼2 𝛾1 𝛾2 𝑅1 𝑅3 𝐶1 𝐶2 𝛼1 𝛼2 𝛽2 𝛾1 𝛾2

𝜔 1
𝑆𝑅10 = −
2

𝜔 𝜕𝜔0 ∕ 𝜔0
𝑆𝑅30 =
𝜕𝑅3 ∕ 𝑅3

𝜔 1 𝑅1 𝑅3 𝐶1 𝐶2 𝛽2 𝛼1 𝛼2 𝛾1 𝛾2 𝐶1 𝐶2 𝑅1 𝑅3
𝑆𝑅30 = − √ ∗ 2 ∗ 𝑅3 ∗ √
2 𝛽2 𝛼1 𝛼2 𝛾1 𝛾2 𝑅3 𝑅1 𝐶1 𝐶2 𝛼1 𝛼2 𝛽2 𝛾1 𝛾2

𝜔 1
𝑆𝑅30 = −
2

𝜔 𝜕𝜔0 ∕ 𝜔0
𝑆𝐶10 =
𝜕𝐶1 ∕ 𝐶1

𝜔 1 𝑅1 𝑅3 𝐶1 𝐶2 𝛽2 𝛼1 𝛼2 𝛾1 𝛾2 𝐶1 𝐶2 𝑅1 𝑅3
𝑆𝐶10 = − √ ∗ 2 ∗ 𝐶1 ∗ √
2 𝛽2 𝛼1 𝛼2 𝛾1 𝛾2 𝐶1 𝑅1 𝑅3 𝐶2 𝛼1 𝛼2 𝛽2 𝛾1 𝛾2

𝜔 1
𝑆𝐶10 = −
2

𝜔 𝜕𝜔0 ∕ 𝜔0
𝑆𝐶20 =
𝜕𝐶2 ∕ 𝐶2

30
 𝜔 1 𝑅1 𝑅3 𝐶1 𝐶2 𝛽2 𝛼1 𝛼2 𝛾1 𝛾2 𝐶1 𝐶2 𝑅1 𝑅3
𝑆𝐶20 = − √ ∗ 2 ∗ 𝐶2 ∗ √
2 𝛽2 𝛼1 𝛼2 𝛾1 𝛾2 𝐶2 𝑅1 𝑅3 𝐶1 𝛼1 𝛼2 𝛽2 𝛾1 𝛾2

𝜔 1
𝑆𝐶20 = −
2
𝜔
𝑆𝑅20 = 0

Summing up all, we get: -

𝜔
𝑆𝛽10 = 0 (3.12)

𝜔 𝜔 𝜔 𝜔 𝜔 1
𝑆𝛽20 = 𝑆𝛼10 = 𝑆𝛼20 = 𝑆𝛾10 = 𝑆𝛾20 = (3.13)
2

𝜔 𝜔 𝜔 𝜔 1
𝑆𝑅10 = 𝑆𝑅30 = 𝑆𝐶10 = 𝑆𝐶20 = − 2 (3.14)

𝜔
𝑆𝑅20 = 0 (3.15)

Frequency Calculation: -

Choosing the following passive components values as:

R1 = R2 = 10KΩ and C1 = C2 = 1nF

The theoretical frequency of oscillation was found to be:

1
𝜔0 =
√𝑅1 𝑅3 𝐶1 𝐶2

1
𝜔0 =
√10 ∗ 103 ∗ 10 ∗ 103 ∗ 1 ∗ 10−9 ∗ 1 ∗ 10−9

𝜔0 = 100000

2π𝑓0 = 100000

Theoretical Frequency of Oscillation, 𝑓0 = 15.91𝐾𝐻𝑧

 It can be seen from Eqn. (3.5) and Eqn. (3.6) that the oscillation condition of the proposed
oscillator can be adjusted by tuning the grounded resistor R2 without affecting the oscil-
lation frequency 𝜔0 , while 𝜔0 can be adjusted by tuning the virtually grounded resistor
R1 without disturbing the oscillation condition. Therefore, the oscillation condition and
the oscillation frequency are independently controllable.

31
 From the relationship between two output voltages in Eqn. (3.3), the phase shift is φ =
90o which guarantees that the proposed oscillator provides the output voltages 𝑣01 and
𝑣02 in phase quadrature.
 From Eqn. (3.12) – Eqn. (3.15) we conclude that the proposed circuit has optimum sen-
sitivity performance in the sense that all values are less than or equal to 0.5 in magnitude.

3.4. VERIFICATION OF SIMULATION RESULTS

Using the Cadence PSPICE simulation software, all the regular simulation
graphs have been obtained to confirm the validity of the proposed SRC oscillator using the
commercially available CFOA IC AD844. With voltage supplies of ±12V, passive compo-
nent values are taken as C1 = C2 = 1nF and R1 = 10 KΩ, while R2 is taken as 10.21365
slightly greater than R1 to start the oscillation. Its Transient and Fourier analysis have been
verified as shown in Fig.3.6. and Fig.3.7.

400mV

200mV

0V

-200mV

-400mV
5.00ms 5.05ms 5.10ms 5.15ms 5.20ms 5.25ms 5.30ms 5.35ms
V(28) V(91)
Time

Fig. 3.6 Transient Analysis of SRCO

V(28) and V(91) are the quadrature outputs of the proposed SRC oscillator circuit whose
transient waveforms are shown in Fig.3.6.

The frequency spectrum i.e., the analysis of the circuit in frequency domain is represented
as shown in Fig.3.7.

32
 200mV

(15.758K,197.563m)

150mV

100mV

50mV

0V
10KHz 12KHz 16KHz 20KHz 24KHz 28KHz 30KHz
V(28) V(91)
Frequency

Fig. 3.7 Frequency Spectrum

After simulating the proposed circuit, it has been verified that the oscillator cir-
cuit provides 90o phase shift outputs. From the simulated waveform the frequency of oscil-
lation is found to be 15.785KHz

Fig. 3.8 Frequency (f) vs R1 graph

Fig.3.8 shows the variation of Frequency with the change in value of resistance
R1. It is observed that theoretical frequency agrees with the simulated values.

33
The THD analysis at this frequency is tabulated below: -
Table 3. 1 THD Results

Harmonic Frequency Fourier Normalized Phase Normalized

No (Hz) Component Component (Degree) Phase (Degree)
1 1.576E+04 2.233E-01 1.000E+00 1.736E+02 0.000E+00
2 3.152E+04 4.996E-04 2.238E-03 1.793E+02 -1.678E+02
3 4.727E+04 2.949E-04 1.321E-03 -1.707E+02 -6.914E+02
4 6.303E+04 1.446E-04 6.479E-04 -1.722E+02 -8.665E+02
5 7.879E+04 1.813E-04 8.122E-04 1.793E+02 -6.885E+02
DC Component = -3.932203E-03
Total Harmonic Distortion = 2.798516E-01 PERCENT

It is evident from the above table that the value of THD is 0.27% which support
the efficient functionality of the designed CFOA based SRC quadrature oscillator.

3.5. EXPERIMENTAL RESULTS

Using the commercially available ICs AD844 and passive components we did
the hardware implementation of the circuit on breadboard as shown in Fig.3.9.

Fig. 3.9 Experimental setup of circuit on breadboard

For practical implementation the value of passive components is taken as C1 =

C2 = 1nF and R1 = R2 = 10KΩ with tolerance of 5% in resistor.
The resultant waveforms are obtained in DSO as shown in Fig.3.10 and
Fig.3.11.

34
 Fig. 3.10 Transient waveform of quadrature outputs

It is observed that the frequency of oscillation is 15.8414KHz.

Fig.3.11 shows the Lissajous pattern which confirms that the two waveforms are
in phase quadrature.

Fig. 3.11 Lissajous Pattern of SRCO quadrature outputs

35
3.6. DESIGN OF VCQO USING CFOA AND AM

The modified form of SRC quadrature oscillator as voltage-controlled quadra-

ture oscillator is designed as shown in Fig. 3.10 which comprises of two CFOAs, three re-
sistors, two capacitors and one analog multiplier.

Fig. 3.12 Proposed CFOA based VC sinusoidal quadrature oscillator configuration.

The CFOA (Current Feedback Operational Amplifier) and analog multiplier

are commercially available as AD8442 and AD6333, respectively which is already discussed
in Section 3.2.
There is a control voltage Vc provided by analog multiplier AD633. This voltage
is responsible for controlling the frequency of oscillation while the condition of oscillation
is controlled by resistance R2. This is proved by the routine analysis of the circuit as pre-
sented in Section 3.7.

3.7. THEORETICAL ANALYSIS OF THE CIRCUIT

Taking ideal conditions of CFOA and multiplier into consideration, the routine
circuit analysis is done as follows.

From given matrix of CFOA in Fig.3.2, the ideal conditions are: -

𝑣𝑧 = 𝑣𝑤

𝑖𝑥 = 𝑖𝑧

𝑣𝑥 = 𝑣𝑦

2
For more details refer to Appendix 1- Datasheet of AD844
3
For more details refer to Appendix 2 - Datasheet of AD633

36
For CFOA1

𝑣𝑥1
𝑖𝑥 1 =
𝑅1

−𝑣𝑥1
𝑖𝑧1 = −𝑖𝑥1 =
𝑅1

𝑣𝑥1 𝑣𝑧1
(𝑣02 − 𝑣𝑧1 )𝑠𝐶1 − =
𝑅1 𝑅2

𝑣02 ∗ 𝑉𝐶
𝑣𝑥1 =
10

𝑣𝑧1 = 𝑣01

𝑣01 𝑠𝐶1 𝑅1 𝑅2 − (𝑉𝐶 𝑅2 )/10

= (3.16)
𝑣02 𝑠𝐶1 𝑅2 𝑅1 + 𝑅1

For CFOA2

𝑣01 = 𝑣𝑦2 = 𝑣𝑥2

𝑖𝑥2 = 𝑖𝑧2

𝑣𝑥2
= 𝑣𝑧2 𝑠𝐶2
𝑅3

Now 𝑣𝑧2 = 𝑣02 and 𝑣𝑥2 = 𝑣01

Hence, the relationship between the two outputs voltages 𝑣01 𝑎𝑛𝑑 𝑣02 can be expressed as:

𝑣01
= 𝑠𝐶2 𝑅3 (3.17)
𝑣02

From eq. 1) and eq. 2)

𝑠𝐶1 𝑅1 𝑅2 − (𝑉𝐶 𝑅2 )/10

= 𝑠𝐶2 𝑅3
𝑠𝐶1 𝑅2 𝑅1 + 𝑅1

Solving above we get the characteristic equation of the circuit as below: -

1 1 𝑉𝐶
𝑠2 + 𝑠 ( − )+ =0 (3.18)
𝑅2 𝐶1 𝑅3 𝐶2 𝑅1 𝑅3 𝐶1 𝐶2 ∗10

Putting s=j𝜔0 and equating imaginary terms to zero,

37
we get condition of oscillation (CO) and frequency of oscillation (FO) respectively as:

CO: 𝑅2 𝐶1 = 𝑅3 𝐶2 (3.19)

𝑉𝐶
𝜔02 =
𝑅1 𝑅3 𝐶1 𝐶2 ∗ 10

𝑉𝐶
FO: 𝜔0 = √ (3.20)
𝑅 1 𝑅3 𝐶1 𝐶2 ∗10

Sensitivity of 𝜔0 with respect to all passive elements can be obtained as: -

𝜔 𝜕𝜔0 ∕ 𝜔0
𝑆𝑅10 =
𝜕𝑅1 ∕ 𝑅1

𝜔 1 1
𝑆𝑅10 = − √𝑅1 𝑅3 𝐶1 𝐶2 ∗ 2 ∗ 𝑅1 ∗ √𝐶1 𝐶2 𝑅1 𝑅3
2 𝑅1 𝑅3 𝐶1 𝐶2

𝜔 1 𝜔 𝜔 𝜔
𝑆𝑅10 = − 2 = 𝑆𝑅30 = 𝑆𝐶10 = 𝑆𝐶20 (3.21)

Frequency Calculation

Choosing the following passive components values as:

R1 = R2 = 10KΩ, C1 = C2 = 1nF and Vc = 10V

The theoretical frequency of oscillation was found to be:

𝑉𝐶
𝜔0 = √
𝑅1 𝑅3 𝐶1 𝐶2 ∗ 10

10
𝜔0 = √
𝑅1 𝑅3 𝐶1 𝐶2 ∗ 10

𝜔0 = 100000

2π𝑓0 = 100000

Theoretical Frequency of Oscillation, 𝑓0 = 15.915𝐾𝐻𝑧

38
 It can be seen from Eqn. (3.19) that the oscillation condition of the proposed oscillator
can be adjusted by tuning the grounded resistor R2. Also, from Eqn. (3.20) it is evident
that the frequency of oscillation can be independently tuned by control voltage (Vc) as
FO being proportional to √𝑉𝑐 thereby allowing fine tuning of oscillator without disturb-
ing the oscillation condition.
 From the relationship between two output voltages in Eqn. (3.17), the phase shift is φ =
90o which guarantees that the proposed oscillator provides the output voltages 𝑣01 and
𝑣02 in phase quadrature.
 From Eqn. (3.21) it is concluded that the designed circuit has low sensitivity performance
as all values are less than unity.

39
 CHAPTER 4

SIMULATED RESULT ANALYSIS

4.1. INTRODUCTION

To confirm the validity of the circuit and check the efficiency of the oscillator
various spice simulation analysis has been done. Before discussing the results, a brief intro-
duction of all the simulations performed are described as follows:

Transient Analysis
Transient analysis is all about determining how a circuit will responds if we
make changes in the driving voltage/current. The real circuit response to the changes in the
driving voltage might be hard to predict due to capacitance and inductance which is the
circuit itself. In few circuits, the parasitic capacitance and inductance can be large enough
so that the response of the circuit deviates from the value that was intended based on the
design.

One can examine the following behaviour using transient analysis:

 The approach to the steady state with time when driven with a constant (DC) voltage.

 The way voltage and current in the circuit change when a DC voltage/current source
changes in magnitude
 How the magnitude and phase of the voltage and current differ from those of the
driver in an AC circuit

 How the circuit responds to the arbitrary driving waveforms in the time-domain

Fourier Analysis

Basically, Fourier analysis is done to calculate the harmonics present in a circuit.

The main aim of Fourier analysis is to extract the harmonics.
It is a type of mathematical analysis which tries to identify patterns or cycles in
a time series data set which has already been normalized. Basically, it seeks to simplify
complex or noisy data by the way of decomposing it into a series of trigonometric or expo-
nential functions, for example sine waves. Each of these sine waves will have a specific
cycle length, amplitude, and phase relationship with the other sine waves, which then can be
added back together to reconstruct the observed data.

40
 By firstly identifying and then removing any effects of spurious trends or any
other complicating factors from the data set taken, the effects of periodic cycles or patterns
can be identified more accurately, which gives the analyst a better estimate of the direction
that the data which is under analysis will take in the future.
The methods of Fourier analysis are generally implemented in algorithmic trad-
ing as a technical analysis tool for forecasting market direction and trends.

Monte Carlo Analysis

Risk analysis is an integral part of every decision or project we make. We always

face uncertainty, ambiguity, and variability with our projects and decisions. In this time of
digital advancement, we have large access to data, but we cannot predict the future with
100% surety. Monte Carlo simulation (also known as the Monte Carlo Method) enables one
to see through all the possible outcomes of one’s decision and analyses the impact of risk,
providing the opportunity for better decision taking capability under uncertainty.

Monte Carlo simulation is a computerized mathematical simulation method that

allows professionals to account for risk and uncertainty in quantitative analysis and gives
more confidence in decision making. The technique is used by researchers, developers, stu-
dents, Project workers in such widely distinct fields as finance, project management, energy,
manufacturing, engineering, research and development, insurance, oil & gas, transportation,
and the environment.

Monte Carlo simulation performs risk analysis by building models of possible

results by substituting a range of values—a probability distribution—for any factor that has
inherent uncertainty. It then calculates results over and over, each time using a different set
of random values from the probability functions. Depending upon the number of uncertain-
ties and the ranges specified for them, a Monte Carlo simulation could involve thousands or
tens of thousands of recalculations before it is complete. Monte Carlo simulation produces
distributions of possible outcome values.

By using probability distributions, variables can have different probabilities of

different outcomes occurring. Probability distributions are a much more realistic way of de-
scribing uncertainty in variables of a risk analysis.
During a Monte Carlo simulation, values are sampled at random from the input
probability distributions. Each set of samples is called an iteration, and the resulting outcome
from that sample is recorded. Monte Carlo simulation does hundreds or thousands of times,
and the result is a probability distribution of possible outcomes. In this way, Monte Carlo
simulation provides a much more comprehensive view of what may happen. It tells you not
only what could happen, but how likely it is to happen.

41
 Monte Carlo simulation provides several advantages over deterministic, or “sin-
gle-point estimate” analysis:

Probabilistic Results
Results show not only what could happen, but how likely each outcome is.

Graphical Results
Because of the data a Monte Carlo simulation generates, it is easy to create
graphs of different outcomes and their chances of occurrence. This is important for com-
municating findings to other stakeholders.
The types of analysis Monte Carlo allows are: -
 Sensitivity Analysis
With just a few cases, deterministic analysis makes it difficult to see which var-
iables impact the outcome the most. In Monte Carlo simulation, it’s easy to see which inputs
had the biggest effect on bottom-line results.

 Scenario Analysis
In deterministic models, it is exceedingly difficult to model different combina-
tions of values for different inputs to see the effects of uniquely different scenarios. Using
Monte Carlo simulation, analysts can see exactly which inputs had which values together
when certain outcomes occurred. This is invaluable for pursuing further analysis.

 Correlation of Inputs
In Monte Carlo simulation, it is possible to model interdependent relationships
between input variables. It is important for accuracy to represent how when some factors go
up, others go up or down accordingly.
An enhancement to Monte Carlo simulation is the use of Latin Hypercube sam-
pling, which samples more accurately from the entire range of distribution functions.

4.2. SIMULATION RESULTS

Using the Cadence PSPICE simulation software, all the regular simulation
graphs have been obtained to confirm the validity of the designed oscillator using the com-
mercially available CFOA and analog multiplier ICs AD844 and AD633, respectively. With
voltage supplies of ±12V, passive component values of C1 = C2 = 1nF, R1 = 10 KΩ, the CO
was set with R2 = 10.21365 KΩ whereas the FO was controlled by input control voltage Vc.
Setting Vc to 10V and keeping remaining values fixed, the above-described analysis has
been performed on the circuit.

42
4.2.1 Transient Results

The simulated quadrature outputs of the designed circuit i.e., V (28) and V (91)
are shown in Fig. 4.1.

Fig. 4.1 Simulated output Waveform of V (28) and V (91)

The simulated waveforms V (28) and V (91) are in phase quadrature is proved
by the obtained Lissajous Pattern4 shown in Fig.4.2. which forms a circle.

Fig. 4.2 Lissajous Pattern

4
Lissajous Pattern or Curve are formed by the intersection of two sinusoidal curves on the axes which are at
right angle. Different curves are forms based on the phase difference between two waveforms.
If phase angle is 0 or 180o straight line is form.
If phase angle is 90o circle is observed on DSO or CRO

43
4.2.2 Fourier Results

Frequency spectrum of quadrature waveform is obtained as shown in 4.3.

Fig. 4.3 Simulated Frequency Spectrum

From the frequency spectrum analysis, the simulated frequency observed is

15.455KHz which agrees quite well the theoretical results.

4.2.3 Total Harmonic Distortion (THD) Results

Presence of harmonics at frequencies other than the oscillating frequency has

been evaluated through THD5 analysis which shows the percentage of distortion present in
the circuit.
Summarizing the THD results, when the designed circuit is employed, Table 4.1
has been prepared.

Table 4.1 THD analysis results

Harmonic Frequency Fourier Normalized Phase Normalized

No (Hz) Component Component (Degree) Phase (Degree)
1 1.580E+04 8.230E+00 1.000E+00 -1.333E+02 0.000E+00
2 3.090E+04 1.236E-02 1.502E-03 1.719E+02 4.385E+02
3 4.635E+04 4.979E-02 6.050E-03 -7.405E+02 3.926E+02
4 6.180E+04 8.009E-03 9.732E-04 -1.275E+02 4.058E+02
5 7.725E+04 2.190E-02 2.661E-03 6.228E+01 7.289E+02
DC Component = 6.372403E-02
Total Harmonic Distortion = 1.272539E+00 PERCENT

It is evident from the above table that the value of THD is 1.27% which lies in
the acceptable range and support the efficient functionality of the designed CFOA based
voltage control quadrature oscillator.

5
Total Harmonic Distortion is the measurement which tells how much distortion is present in the voltage or
current at specific frequency. The acceptable range of THD is less than 5%.

44
4.2.4 Monte Carlo Results

Monte Carlo Analysis is a statistical analysis that shows the behaviour of the
circuit when circuit parameters are varied between specified tolerance levels as discussed
in Section 4.1.
To investigate the stability of the circuit 0.25% Gaussian deviation on resistors
is used. The results of Monte Carlo analysis of the designed circuit is shown in Fig. 4.4.

Fig. 4.4 Monte Carlo Analysis

4.2.5 Variation of Frequency with Control Voltage

By changing the control voltage, frequency is varied, and the following graph
is obtained as shown in Fig. 4.5. The whole simulation is performed in MATLAB.

Fig. 4.5 Frequency (f) vs Control Voltage (Vc) Graph

45
4.3. REMARKS

 After simulating the proposed circuit, it has been verified that the oscillator provides 90o
phase shift outputs which is proved by the Lissajous pattern and thus it is further proved
that the designed oscillator is a quadrature oscillator.
 The simulated frequency observed is 15.445KHz which is almost equal to the theoretical
frequency of oscillation, 𝑓0 = 15.94KHz.
 The percentage of total harmonic distortion is found to be 1.27% which lies in the ac-
ceptable range hence proves that the efficiency of the circuit is good.
 After varying the values of control voltage, it is observed that for the oscillation to start
the value of Vc must be greater than or equal to 1.
 In F vs R1 graph, which is discussed in chapter 3, it is observed that with the increase in
value of R1 the frequency decreases exponentially i.e., a sudden decrease is evident
which on further increasing the value of R1 becomes almost constant. While from Fig.4.8
a noticeable change in value of frequency is observed for every change in value of control
voltage Vc. From this it can be concluded that the newly designed Voltage Controlled
Quadrature Oscillator offers more fine tuning of frequency of oscillation in comparison
to SRCO.

46
 CHAPTER 5

FINAL CONCLUSION AND FUTURE SCOPE

5.1. INTRODUCTION

Active building blocks such as Op-Amps, Current Conveyors, OTA are widely
used for the realization of filters, oscillators impedance convertors, impedance invertors and
gyrators. Its variant has been proven the most widely used active elements and enjoy the
feature of electronic tuning. CFOA is being one of them which has been formed by current
conveyor connected with voltage buffer. It offers several advantages as discussed in Chapter
1 which led to the designing and case study of Single Resistance Controlled Quadrature
Oscillator. Which further led to the idea of the proposed VCO Oscillator using the reduced
no. of analog multiplier as proposed previously by different authors. The advantage of the
voltage-controlled quadrature oscillator is that it is independently tuned over range of volt-
age which provide analysis of the proposed circuit which was the main aim of the project.

5.2. CONCLUSIONS

In chapter 1 we gave the introduction of the basic oscillator circuits, its role in
analog and digital circuits and further classification. In addition to it confine the discussion
giving brief introduction of VCO and its applications.

In chapter 2 the literature review of the SRCO and VCO using different building
blocks has been discussed. Studying different circuits, we observed how the frequency of
oscillation and condition of oscillation is controlled with the variation in resistor and control
voltage.

In chapter 3 we did a full case study of the SRC based Quadrature Oscillator
using CFOA which helped us to reach the idea of the proposed VCO oscillator theoretically
and logically. We verified all the results of the already proposed SRC oscillator theoretically,
by simulating and experimentally. The results of all the three analyses conform to each other
very well. Moreover, we presented the main ideas of the proposed voltage-controlled quad-
rature oscillator and presented the theoretical results of the newly designed circuit.

In chapter 4 we presented the simulation results of VC Quadrature Oscillator.

From the waveforms so obtained we verified theoretical results which agrees quite well with
simulated waveforms.

47
 In comparison to OP-Amp, CFOA has a wide range of operating frequency giv-
ing higher bandwidth with lesser number of passive components. This proves that the effi-
ciency of CFOA based circuit will be more as compared to OP-Amp based. Also requiring
lesser number of components will also lead to cost effectiveness which can prove to be the
major reason to design more and more circuits with CFOA.

5.3. SCOPE FOR IMPROVEMENT

The total harmonic distortion of the designed circuit is 1.27% which can be fur-
ther reduced to improve the efficiency of circuit. This can be done if we can avoid the con-
vergence problem while simulating the circuit.

5.4. FUTURE SCOPE

In the designed circuit fine tuning of oscillator is observed but at the cost of
increase in one active element i.e., analog multiplier. So, we can think to design the same
oscillator with a smaller number of components aiming to attain the same or increased effi-
ciency of the circuit.
Also, after surveying multiple literatures, we have observed that CFOA find the
considerable attention in the repertoire of both SRC and VC oscillators. But still, we can
think of designing the same oscillator with a different building block intending to gain higher
bandwidth and reduced noise effect thus improving its efficiency.

48
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[11] Gupta, S.S. and Senani, R.State., 2008. Variable synthesis of single resistance controlled
grounded capacitor oscillators using only two CFOAs, IEE Proceedings Circuits, Devices and
Systems, 145, pp. 135-138.

[12] Bhaskar, D.R., Gupta, S.S., Senani, R. and Singh, A.K. 2012. New CFOA-based sinusoidal
oscillators retaining independent control of oscillation frequency even under the influence of
parasitic impedances, Analog Integrated Circuits and Signal Processing, 73, pp. 427-437.

[13] P. Mongkolwai, T. Pukkalanun, T. Dumawipata and W. Tangsrirat., 2008. CFOA-based single

resistance-controlled quadrature oscillator, SICE Annual Conference, 2008, pp. 1147-1150.

49
 60 MHz, 2000 V/μs,
Monolithic Op Amp with Quad Low Noise
Data Sheet AD844
FEATURES FUNCTIONAL BLOCK DIAGRAMS
Wide bandwidth NULL 1 AD844 8 NULL
60 MHz at gain of −1 –IN 2 7 +VS
33 MHz at gain of −10 +IN 3 6 OUTPUT

Slew rate: 2000 V/μs –VS 4 5 TZ

00897-001
20 MHz full power bandwidth, 20 V p-p, RL = 500 Ω TOP VIEW
(Not to Scale)
Fast settling: 100 ns to 0.1% (10 V step)
Differential gain error: 0.03% at 4.4 MHz Figure 1. 8-Lead PDIP (N) and 8-Lead CERDIP (Q) Packages
Differential phase error: 0.16° at 4.4 MHz NC 1 16 NC
Low offset voltage: 150 μV maximum (B Grade) OFFSETNULL 2 15 OFFSETNULL
Low quiescent current: 6.5 mA –IN 3 14 V+

Available in tape and reel in accordance with NC 4 13 NC

+IN 5 12 OUTPUT
EIA-481-A standard
NC 6 11 TZ
AD844
APPLICATIONS V– 7
TOP VIEW
10 NC

NC 8 (Not to Scale) 9 NC

00897-002
Flash ADC input amplifiers
NC = NO CONNECT
High speed current DAC interfaces
Video buffers and cable drivers Figure 2. 16-Lead SOIC (R) Package
Pulse amplifiers

GENERAL DESCRIPTION The AD844A and AD844B are specified for the industrial
The AD844 is a high speed monolithic operational amplifier temperature range of −40°C to +85°C and are available in the
fabricated using the Analog Devices, Inc., junction isolated CERDIP (Q) package. The AD844A is also available in an 8-lead
complementary bipolar (CB) process. It combines high band- PDIP (N). The AD844S is specified over the military temperature
width and very fast large signal response with excellent dc range of −55°C to +125°C. It is available in the 8-lead CERDIP
performance. Although optimized for use in current-to-voltage (Q) package. A and S grade chips and devices processed to
applications and as an inverting mode amplifier, it is also suitable MIL-STD-883B, Rev. C are also available.
for use in many noninverting applications. PRODUCT HIGHLIGHTS
The AD844 can be used in place of traditional op amps, but its 1. The AD844 is a versatile, low cost component providing an
current feedback architecture results in much better ac perfor- excellent combination of ac and dc performance.
mance, high linearity, and an exceptionally clean pulse response. 2. It is essentially free from slew rate limitations. Rise and fall
This type of op amp provides a closed-loop bandwidth that is times are essentially independent of output level.
determined primarily by the feedback resistor and is almost 3. The AD844 can be operated from ±4.5 V to ±18 V power
independent of the closed-loop gain. The AD844 is free from supplies and is capable of driving loads down to 50 Ω, as
the slew rate limitations inherent in traditional op amps and well as driving very large capacitive loads using an external
other current-feedback op amps. Peak output rate of change can network.
be over 2000 V/μs for a full 20 V output step. Settling time is 4. The offset voltage and input bias currents of the AD844 are
typically 100 ns to 0.1%, and essentially independent of gain. laser trimmed to minimize dc errors; VOS drift is typically 1
The AD844 can drive 50 Ω loads to ±2.5 V with low distortion μV/°C and bias current drift is typically 9 nA/°C.
and is short-circuit protected to 80 mA. 5. The AD844 exhibits excellent differential gain and
differential phase characteristics, making it suitable for a
The AD844 is available in four performance grades and three variety of video applications with bandwidths up to 60 MHz.
package options. In the 16-lead SOIC (RW) package, the AD844J 6. The AD844 combines low distortion, low noise, and low
is specified for the commercial temperature range of 0°C to 70°C. drift with wide bandwidth, making it outstanding as an
input amplifier for flash analog-to-digital converters (ADCs).

Rev. G Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©1989-2017 Analog Devices, Inc. All rights reserved.
Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
AD844 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1  Response as an Inverting Amplifier ......................................... 12 
Applications ....................................................................................... 1  Response as an I-V Converter .................................................. 13 
Functional Block Diagrams ............................................................. 1  Circuit Description of the AD844 ............................................ 13 
General Description ......................................................................... 1  Response as a Noninverting Amplifier.................................... 14 
Product Highlights ........................................................................... 1  Noninverting Gain of 100 ......................................................... 14 
Revision History ............................................................................... 2  Using the AD844 ............................................................................ 15 
Specifications..................................................................................... 3  Board Layout ............................................................................... 15 
Absolute Maximum Ratings............................................................ 5  Input Impedance ........................................................................ 15 
Metallization Photograph ............................................................ 5  Driving Large Capacitive Loads ............................................... 15 
ESD Caution .................................................................................. 5  Settling Time ............................................................................... 15 
Typical Performance Characteristics ............................................. 6  DC Error Calculation ................................................................ 16 
Inverting Gain-of-1 AC Characteristics .................................... 8  Noise ............................................................................................ 16 
Inverting Gain-of-10 AC Characteristics .................................. 9  Video Cable Driver Using ±5 V Supplies ................................ 16 
Inverting Gain-of-10 Pulse Response ...................................... 10  High Speed DAC Buffer ............................................................ 17 
Noninverting Gain-of-10 AC Characteristics ........................ 11  20 MHz Variable Gain Amplifier ............................................. 17 
Understanding the AD844 ............................................................ 12  Outline Dimensions ....................................................................... 19 
Open-Loop Behavior ................................................................. 12  Ordering Guide .......................................................................... 20 

REVISION HISTORY
5/2017—Rev. F to Rev. G 1/2003—Rev. D to Rev. E
Change to Figure 32 ....................................................................... 14 Updated Features ...............................................................................1
Edit to TPC 18 ...................................................................................7
2/2009—Rev. E to Rev F Edits to Figure 13 and Figure 14................................................... 13
Updated Format .................................................................. Universal Updated Outline Dimensions ....................................................... 15
Changes to Features Section............................................................ 1
Changes to Differential Phase Error Parameter, Table 1 ............. 3 11/2001—Rev. C to Rev. D
Changes to Figure 13 ........................................................................ 8 Edits to Specifications ......................................................................2
Changes to Figure 18 ........................................................................ 9 Edits to Absolute Maximum Ratings ..............................................3
Changes to Figure 23 and Figure 24 ............................................. 11 Edits to Ordering Guide ...................................................................3
Changes to Figure 42 and High Speed DAC Buffer Section ..... 17
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 20

Rev. G | Page 2 of 20
Data Sheet AD844

SPECIFICATIONS
TA = 25°C and VS = ±15 V dc, unless otherwise noted.

Table 1.
AD844J/AD844A AD844B AD844S
Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit
INPUT OFFSET VOLTAGE1 50 300 50 150 50 300 μV
TMIN to TMAX 75 500 75 200 125 500 μV
vs. Temperature 1 1 5 1 5 μV/°C
vs. Supply 5 V to 18 V
Initial 4 20 4 10 4 20 μV/V
TMIN to TMAX 4 4 10 4 20 μV/V
vs. Common Mode VCM = ±10 V
Initial 10 35 10 20 10 35 μV/V
TMIN to TMAX 10 10 20 10 35 μV/V
INPUT BIAS CURRENT
Negative Input Bias Current1 200 450 150 250 200 450 nA
TMIN to TMAX 800 1500 750 1100 1900 2500 nA
vs. Temperature 9 9 15 20 30 nA/°C
vs. Supply 5 V to 18 V
Initial 175 250 175 200 175 250 nA/V
TMIN to TMAX 220 220 240 220 300 nA/V
vs. Common Mode VCM = ±10 V
Initial 90 160 90 110 90 160 nA/V
TMIN to TMAX 110 110 150 120 200 nA/V
Positive Input Bias Current1 150 400 100 200 100 400 nA
TMIN to TMAX 350 700 300 500 800 1300 nA
vs. Temperature 3 3 7 7 15 nA/°C
vs. Supply 5 V to 18 V
Initial 80 150 80 100 80 150 nA/V
TMIN to TMAX 100 100 120 120 200 nA/V
vs. Common Mode VCM = ±10 V
Initial 90 150 90 120 90 150 nA/V
TMIN to TMAX 130 130 190 140 200 nA/V
INPUT CHARACTERISTICS
Input Resistance
Negative Input 50 65 50 65 50 65 Ω
Positive Input 7 10 7 10 7 10 MΩ
Input Capacitance
Negative Input 2 2 2 pF
Positive Input 2 2 2 pF
Input Common-Mode Voltage ±10 ±10 ±10 V
Range
INPUT VOLTAGE NOISE f ≥ 1 kHz 2 2 2 nV/√Hz
INPUT CURRENT NOISE
Negative Input f ≥ 1 kHz 10 10 10 pV/√Hz
Positive Input f ≥ 1 kHz 12 12 12 pV/√Hz
OPEN-LOOP TRANSRESISTANCE VOUT = ±10 V
RL = 500 Ω 2.2 3.0 2.8 3.0 2.2 3.0 MΩ
TMIN to TMAX 1.3 2.0 1.6 2.0 1.3 1.6 MΩ
Transcapacitance 4.5 4.5 4.5 pF
DIFFERENTIAL GAIN ERROR2 f = 4.4 MHz 0.03 0.03 0.03 %
DIFFERENTIAL PHASE ERROR2 f = 4.4 MHz 0.16 0.16 0.16 Degree
Rev. G | Page 3 of 20
AD844 Data Sheet
AD844J/AD844A AD844B AD844S
Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit
FREQUENCY RESPONSE
Small Signal Bandwidth3, 4
Gain = −1 60 60 60 MHz
Gain = −10 33 33 33 MHz
TOTAL HARMONIC DISTORTION f = 100 kHz, 0.005 0.005 0.005 %
2 V rms5
SETTLING TIME
10 V Output Step ±15 V supplies
Gain = −1, to 0.1%5 100 100 100 ns
Gain = −10, to 0.1%6 100 100 100 ns
2 V Output Step ±5 V supplies
Gain = −1, to 0.1%5 110 110 110 ns
Gain = −10, to 0.1%6 100 100 100 ns
OUTPUT SLEW RATE Overdriven 1200 2000 1200 2000 1200 2000 V/μs
input
FULL POWER BANDWIDTH THD = 3%
VOUT = 20 V p-p5 VS = ±15 V 20 20 20 MHz
VOUT = 2 V p-p5 VS = ±5 V 20 20 20 MHz
OUTPUT CHARACTERISTICS
Voltage RL = 500 Ω ±10 ±11 ±10 ±11 ±10 ±11 V
Short-Circuit Current 80 80 80 mA
TMIN to T MAX 60 60 60 mA
Output Resistance Open loop 15 15 15 Ω
POWER SUPPLY
Operating Range ±4.5 ±18 ±4.5 ±18 ±4.5 ±18 V
Quiescent Current 6.5 7.5 6.5 7.5 6.5 7.5 mA
TMIN to TMAX 7.5 8.5 7.5 8.5 7.5 8.5 mA
1
Rated performance after a 5 minute warm-up at TA = 25°C.
2
Input signal 285 mV p-p carrier (40 IRE) riding on 0 mV to 642 mV (90 IRE) ramp. RL = 100 Ω; R1, R2 = 300 Ω.
3
For gain = −1, input signal = 0 dBm, CL = 10 pF, RL = 500 Ω, R1 = 500 Ω, and R2 = 500 Ω in Figure 29.
4
For gain = −10, input signal = 0 dBm, CL =10 pF, RL = 500 Ω, R1 = 500 Ω, and R2 = 50 Ω in Figure 29.
5
CL = 10 pF, RL = 500 Ω, R1 = 1 kΩ, R2 = 1 kΩ in Figure 29.
6
CL = 10 pF, RL = 500 Ω, R1 = 500 Ω, R2 = 50 Ω in Figure 29.

Rev. G | Page 4 of 20
Data Sheet AD844

ABSOLUTE MAXIMUM RATINGS

Table 2.
METALLIZATION PHOTOGRAPH
Parameter Ratings Contact factory for latest dimensions.
Supply Voltage ±18 V Dimensions shown in inches and (millimeters).
Power Dissipation1 1.1 W –IN NULL NULL +VS

Output Short-Circuit Duration Indefinite

Input Common-Mode Voltage ±VS
Differential Input Voltage 6V
Inverting Input Current
Continuous 5 mA
Transient 10 mA 0.076
(1.9)
Storage Temperature Range (Q) −65°C to +150°C
Storage Temperature Range (N, RW) −65°C to +125°C
Lead Temperature (Soldering, 60 sec) 300°C
ESD Rating 1000 V
1
28-lead PDIP package: θJA = 90°C/W.
8-lead CERDIP package: θJA = 110°C/W.
16-lead SOIC package: θJA = 100°C/W. +IN –VS TZ OUTPUT
Stresses at or above those listed under Absolute Maximum 0.095

00897-003
(2.4)
Ratings may cause permanent damage to the product. This is a SUBSTRATE CONNECTED TO +VS
stress rating only; functional operation of the product at these Figure 3. Die Photograph
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond ESD CAUTION
the maximum operating conditions for extended periods may
affect product reliability.

Rev. G | Page 5 of 20
AD844 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C and VS = ±15 V, unless otherwise noted.
70 20
TA = 25°C

60 15
–3dB BANDWIDTH (MHz)

INPUT VOLTAGE (V)

50 10

40 5

30 0
00897-004

00897-007
0 5 10 15 20 0 5 10 15 20
SUPPLY VOLTAGE (±V) SUPPLY VOLTAGE (±V)

Figure 4. −3 dB Bandwidth vs. Supply Voltage, R1 = R2 = 500 Ω Figure 7. Noninverting Input Voltage Swing vs. Supply Voltage

–60 20
1V rms RL = 500Ω
TA = 25°C
–70
HARMONIC DISTORTION (dB)

15
–80
OUTPUT VOLTAGE (V)

–90
10
–100

–110
SECOND HARMONIC 5

–120

THIRD HARMONIC
–130 0

00897-008
0 5 10 15 20
00897-005

100 1k 10k 100k

INPUT FREQUENCY (Hz) SUPPLY VOLTAGE (±V)

Figure 5. Harmonic Distortion vs. Input Frequency, R1 = R2 = 1 kΩ Figure 8. Output Voltage Swing vs. Supply Voltage

5 10
RL = ∞

9
4
TRANSRESISTANCE (MΩ)

SUPPLY CURRENT (mA)

RL = 500Ω
8
3

2 VS = ±15V
6
RL = 50Ω
VS = ±5V
1
5

0 4
00897-009

–60 –40 –20 0 20 40 60 80 100 120 140

00897-006

–50 0 50 100 150

TEMPERATURE (°C) TEMPERATURE (-°C)

Figure 6. Transresistance vs. Temperature Figure 9. Quiescent Supply Current vs. Temperature and Supply Voltage

Rev. G | Page 6 of 20
Data Sheet AD844
2 40

VS = ±15V
35

1
INPUT BIAS CURRENT (µA)

–3dB BANDWIDTH (MHz)

IBP 30

0 25 VS = ±5V

20
–1
IBN
15

–2 10

00897-010

00897-012
–50 0 50 100 150 –60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C) TEMPERATURE (-°C)

Figure 10. Inverting Input Bias Current (IBN) and Noninverting Input Bias Figure 12. –3 dB Bandwidth vs. Temperature, Gain = −1, R1 = R2 = 1 kΩ
Current (IBP) vs. Temperature

100

10
OUTPUT IMPEDANCE (Ω)

±5V SUPPLIES
1

0.1

0.01
00897-011

10k 100k 1M 10M 100M

FREQUENCY (Hz)

Figure 11. Output Impedance vs. Frequency, Gain = −1, R1 = R2 = 1 kΩ

Rev. G | Page 7 of 20
AD844 Data Sheet
INVERTING GAIN-OF-1 AC CHARACTERISTICS
+VS
5V
4.7Ω
0.22µF
100
R1 90

R2
–IN –
AD844 OUTPUT
+

RL CL
10

0.22µF 0

4.7Ω
00897-013

00897-016
20ns
–VS

Figure 13. Inverting Amplifier, Gain of −1 (R1 = R2) Figure 16. Large Signal Pulse Response, Gain = −1, R1 = R2 = 1 kΩ

6
500nV
R1 = R2 = 500Ω
100
0
90

R1 = R2 = 1kΩ
–6
GAIN (dB)

–12

10

–18 0

00897-017
20ns
–24
00897-014

100k 1M 10M 100M

FREQUENCY (Hz)
Figure 17. Small Signal Pulse Response, Gain = −1, R1 = R2 = 1 kΩ

Figure 14. Gain vs. Frequency for Gain = −1, RL = 500 Ω, CL = 0 pF

–180

–210

R1 = R2 = 500Ω
PHASE (Degrees)

–240

–270
R1 = R2 = 1kΩ

–300

–330
00897-015

0 25 50
FREQUENCY (MHz)

Figure 15. Phase vs. Frequency for Gain = −1, RL = 500 Ω, CL = 0 pF

Rev. G | Page 8 of 20
Data Sheet AD844
INVERTING GAIN-OF-10 AC CHARACTERISTICS
+VS 26
4.7Ω
0.22µF RL = 500Ω

500Ω 20

RL = 50Ω
50Ω 14
–

GAIN (dB)
–IN
AD844 OUTPUT
+
8

RL CL

0.22µF 2
4.7Ω

00897-018
–VS
–4

00897-019
100k 1M 10M 100M
FREQUENCY (Hz)

Figure 18. Gain of −10 Amplifier Figure 19. Gain vs. Frequency, Gain = −10
–180

–210
RL = 50Ω RL = 500Ω

PHASE (Degrees)
–240

–270

–300

–330

00897-020
0 25 50
FREQUENCY (MHz)

Figure 20. Phase vs. Frequency, Gain = −10

Rev. G | Page 9 of 20
AD844 Data Sheet
INVERTING GAIN-OF-10 PULSE RESPONSE
5V 500nV

100 100

90 90

10 10

0 0

00897-022
00897-021
20ns 20ns

Figure 21. Large Signal Pulse Response, Gain = –10, RL = 500 Ω Figure 22. Small Signal Pulse Response, Gain = −10, RL = 500 Ω

Rev. G | Page 10 of 20
Data Sheet AD844
NONINVERTING GAIN-OF-10 AC CHARACTERISTICS
4.7Ω
+VS 0.22µF 2V 100ns

100

450Ω 90

50Ω
–
OUTPUT
AD844
–IN +
0.22µF RL
CL

4.7Ω

00897-023
10
–VS
0

00897-026
Figure 23. Noninverting Gain of +10 Amplifier Figure 26. Noninverting Amplifier Large Signal Pulse Response, Gain = +10,
RL = 500 Ω
26

200nV 50ns

20 100
RL = 50Ω RL = 500Ω
90

14
GAIN (dB)

2 10

00897-027
–4
00897-024

100k 1M 10M 100M

FREQUENCY (Hz)

Figure 24. Gain vs. Frequency, Gain = +10 Figure 27. Small Signal Pulse Response, Gain = +10, RL = 500 Ω

–180

–210
RL = 50Ω RL = 500Ω
PHASE (Degrees)

–240

–270

–300

–330
00897-025

0 25 50
FREQUENCY (MHz)

Figure 25. Phase vs. Frequency, Gain = +10

Rev. G | Page 11 of 20
AD844 Data Sheet

UNDERSTANDING THE AD844

The AD844 can be used in ways similar to a conventional op RESPONSE AS AN INVERTING AMPLIFIER
amp while providing performance advantages in wideband Figure 29 shows the connections for an inverting amplifier.
applications. However, there are important differences in the Unlike a conventional amplifier, the transient response and the
internal structure that need to be understood to optimize the small signal bandwidth are determined primarily by the value of
performance of the AD844 op amp. the external feedback resistor, R1, rather than by the ratio of
OPEN-LOOP BEHAVIOR R1/R2 as is customarily the case in an op amp application. This
Figure 28 shows a current feedback amplifier reduced to essen- is a direct result of the low impedance at the inverting input. As
tials. Sources of fixed dc errors, such as the inverting node bias with conventional op amps, the closed-loop gain is −R1/R2.
current and the offset voltage, are excluded from this model. The closed-loop transresistance is the parallel sum of R1 and Rt.
The most important parameter limiting the dc gain is the Because R1 is generally in the range of 500 Ω to 2 kΩ and Rt is
transresistance, Rt, which is ideally infinite. A finite value of Rt about 3 MΩ, the closed-loop transresistance is only 0.02% to
is analogous to the finite open-loop voltage gain in a conventional 0.07% lower than R1. This small error is often less than the
op amp. resistor tolerance.
The current applied to the inverting input node is replicated by When R1 is fairly large (above 5 kΩ) but still much less than Rt,
the current conveyor to flow in Resistor Rt. The voltage developed the closed-loop HF response is dominated by the time constant
across Rt is buffered by the unity gain voltage follower. Voltage R1 Ct. Under such conditions, the AD844 is overdamped and
gain is the ratio Rt/RIN. With typical values of Rt = 3 MΩ and provides only a fraction of its bandwidth potential. Because of
RIN = 50 Ω, the voltage gain is about 60,000. The open-loop the absence of slew rate limitations under these conditions, the
current gain, another measure of gain that is determined by the circuit exhibits a simple single-pole response even under large
beta product of the transistors in the voltage follower stage (see signal conditions.
Figure 31), is typically 40,000. In Figure 29, R3 is used to properly terminate the input if desired.
R3 in parallel with R2 gives the terminated resistance. As R1 is
+1 lowered, the signal bandwidth increases, but the time constant
R1 Ct becomes comparable to higher order poles in the closed-
IIN Rt Ct +1 loop response. Therefore, the closed-loop response becomes
RIN IIN complex, and the pulse response shows overshoot. When R2
00897-028

is much larger than the input resistance, RIN, at Pin 2, most of

Figure 28. Equivalent Schematic the feedback current in R1 is delivered to this input, but as R2
becomes comparable to RIN, less of the feedback is absorbed at
The important parameters defining ac behavior are the
Pin 2, resulting in a more heavily damped response. Consequently,
transcapacitance, Ct, and the external feedback resistor (not
for low values of R2, it is possible to lower R1 without causing
shown). The time constant formed by these components is
instability in the closed-loop response. Table 3 lists combinations
analogous to the dominant pole of a conventional op amp and
of R1 and R2 and the resulting frequency response for the circuit
thus cannot be reduced below a critical value if the closed-loop
of Figure 29. Figure 16 shows the very clean and fast ±10 V
system is to be stable. In practice, Ct is held to as low a value as
pulse response of the AD844.
possible (typically 4.5 pF) so that the feedback resistor can be
R1
maximized while maintaining a fast response. The finite RIN
also affects the closed-loop response in some applications.
R2
The open-loop ac gain is also best understood in terms of the VIN
transimpedance rather than as an open-loop voltage gain. The AD844 VOUT
R3
OPTIONAL
open-loop pole is formed by Rt in parallel with Ct. Because Ct is
typically 4.5 pF, the open-loop corner frequency occurs at about RL CL
00897-029

12 kHz. However, this parameter is of little value in determining

the closed-loop response.
Figure 29. Inverting Amplifier

Rev. G | Page 12 of 20
Data Sheet AD844
R1
Table 3. Gain vs. Bandwidth
ISIG
Gain R1 R2 BW (MHz) GBW (MHz)
−1 1 kΩ 1 kΩ 35 35 AD844 VOUT
CS
−1 500 Ω 500 Ω 60 60
−2 2 kΩ 1 kΩ 15 30
RL CL
−2 1 kΩ 500 Ω 30 60

00897-030
−5 5 kΩ 1 kΩ 5.2 26
−5 500 Ω 100 Ω 49 245 Figure 30. Current-to-Voltage Converter
−10 1 kΩ 100 Ω 23 230
−10 500 Ω 50 Ω 33 330 CIRCUIT DESCRIPTION OF THE AD844
−20 1 kΩ 50 Ω 21 420 A simplified schematic is shown in Figure 31. The AD844 differs
−100 5 kΩ 50 Ω 3.2 320 from a conventional op amp in that the signal inputs have
RESPONSE AS AN I-V CONVERTER radically different impedance. The noninverting input (Pin 3)
presents the usual high impedance. The voltage on this input is
The AD844 works well as the active element in an operational
transferred to the inverting input (Pin 2) with a low offset voltage,
current-to-voltage converter, used in conjunction with an
ensured by the close matching of like polarity transistors operating
external scaling resistor, R1, in Figure 30. This analysis includes
under essentially identical bias conditions. Laser trimming nulls
the stray capacitance, CS, of the current source, which may be a
the residual offset voltage, down to a few tens of microvolts. The
high speed DAC. Using a conventional op amp, this capacitance
inverting input is the common emitter node of a complementary
forms a nuisance pole with R1 that destabilizes the closed-loop
pair of grounded base stages and behaves as a current summing
response of the system. Most op amps are internally compensated
node. In an ideal current feedback op amp, the input resistance
for the fastest response at unity gain, so the pole due to R1 and
is zero. In the AD844, it is about 50 Ω.
CS reduces the already narrow phase margin of the system. For
example, if R1 is 2.5 kΩ, a CS of 15 pF places this pole at a A current applied to the inverting input is transferred to a
frequency of about 4 MHz, well within the response range of even complementary pair of unity-gain current mirrors that deliver
a medium speed operational amplifier. In a current feedback amp, the same current to an internal node (Pin 5) at which the full
this nuisance pole is no longer determined by R1 but by the output voltage is generated. The unity-gain complementary
input resistance, RIN. Because this is about 50 Ω for the AD844, voltage follower then buffers this voltage and provides the load
the same 15 pF forms a pole at 212 MHz and causes little driving power. This buffer is designed to drive low impedance
trouble. It can be shown that the response of this system is: loads, such as terminated cables, and can deliver ±50 mA into a
50 Ω load while maintaining low distortion, even when operating
K R1
VOUT  I sig at supply voltages of only ±6 V. Current limiting (not shown)
1  sTd  1  sTn  ensures safe operation under short-circuited conditions.
where: 7 +VS

K is a factor very close to unity and represents the finite dc gain

of the amplifier. IB

Td is the dominant pole.

Tn is the nuisance pole.
Rt +IN 3 2 –IN TZ 5 6 OUTPUT
K
Rt  R1
Td = KR1Ct
IB
Tn = RINCS (assuming RIN << R1)
00897-031

Using typical values of R1 = 1 kΩ and Rt = 3 MΩ, K = 0.9997; in 4 –VS

other words, the gain error is only 0.03%. This is much less than Figure 31. Simplified Schematic
the scaling error of virtually all DACs and can be absorbed, if
necessary, by the trim needed in a precise system.
In the AD844, Rt is fairly stable with temperature and supply
voltages, and consequently the effect of finite gain is negligible
unless high value feedback resistors are used. Because that
results in slower response times than are possible, the relatively
low value of Rt in the AD844 is rarely a significant source of error.

Rev. G | Page 13 of 20
AD844 Data Sheet
It is important to understand that the low input impedance at NONINVERTING GAIN OF 100
the inverting input is locally generated and does not depend on The AD844 provides very clean pulse response at high
feedback. This is very different from the virtual ground of a noninverting gains. Figure 32 shows a typical configuration
conventional operational amplifier used in the current summing providing a gain of 100 with high input resistance. The feedback
mode, which is essentially an open circuit until the loop settles. resistor is kept as low as practicable to maximize bandwidth,
In the AD844, transient current at the input does not cause and a peaking capacitor (CPK) can optionally be added to
voltage spikes at the summing node while the amplifier is further extend the bandwidth. Figure 33 shows the small signal
settling. Furthermore, all of the transient current is delivered response with CPK = 3 nF, RL = 500 Ω, and supply voltages of
to the slewing (TZ) node (Pin 5) via a short signal path (the either ±5 V or ±15 V. Gain bandwidth products of up to
grounded base stages and the wideband current mirrors). 900 MHz can be achieved in this way.
The current available to charge the capacitance (about 4.5 pF) at The offset voltage of the AD844 is laser trimmed to the 50 μV
the TZ node is always proportional to the input error current, level and exhibits very low drift. In practice, there is an
and the slew rate limitations associated with the large signal additional offset term due to the bias current at the inverting
response of the op amps do not occur. For this reason, the rise input (IBN), which flows in the feedback resistor (R1). This can
and fall times are almost independent of signal level. In practice, optionally be nulled by the trimming potentiometer shown in
the input current eventually causes the mirrors to saturate. Figure 32.
When using ±15 V supplies, this occurs at about 10 mA (or
+VS
±2200 V/μs). Because signal currents are rarely this large,
classical slew rate limitations are absent. 4.7Ω
OFFSET
This inherent advantage is lost if the voltage follower used to TRIM
buffer the output has slew rate limitations. The AD844 is CPK
R1
3nF 20kΩ
designed to avoid this problem, and as a result, the output 499Ω

buffer exhibits a clean large signal transient response, free from 1

anomalous effects arising from internal saturation.
8 0.22µF
2
RESPONSE AS A NONINVERTING AMPLIFIER R2 7
4.99Ω
Because current feedback amplifiers are asymmetrical with AD844 6

regard to their two inputs, performance differs markedly in VIN 3 RL

4
noninverting and inverting modes. In noninverting modes, the 0.22µF
large signal high speed behavior of the AD844 deteriorates at 4.7Ω
low gains because the biasing circuitry for the input system (not

00897-032
shown in Figure 31) is not designed to provide high input –VS
voltage slew rates. Figure 32. Noninverting Amplifier Gain = 100, Optional Offset Trim Is Shown
However, good results can be obtained with some care. The 46

noninverting input does not tolerate a large transient input; it

VS = ±15V
must be kept below ±1 V for best results. Consequently, this 40
mode is better suited to high gain applications (greater than
×10). Figure 23 shows a noninverting amplifier with a gain of 10 VS = ±5V
34
and a bandwidth of 30 MHz. The transient response is shown in
GAIN (dB)

Figure 26 and Figure 27. To increase the bandwidth at higher

gains, a capacitor can be added across R2 whose value is 28
approximately (R1/R2) × Ct.
22

16
00897-040

100k 1M 10M 20M

FREQUENCY (Hz)

Figure 33. AC Response for Gain = 100, Configuration Shown in Figure 32

Rev. G | Page 14 of 20
Data Sheet AD844

USING THE AD844

BOARD LAYOUT
As with all high frequency circuits considerable care must be
AD844 6 VOUT
used in the layout of the components surrounding the AD844.
5
A ground plane, to which the power supply decoupling capaci-
tors are connected by the shortest possible leads, is essential to CL

00897-034
achieving clean pulse response. Even a continuous ground plane 750Ω 22pF
exhibits finite voltage drops between points on the plane, and Figure 34. Feedforward Network for Large Capacitive Loads
this must be kept in mind when selecting the grounding points.
In general, decoupling capacitors should be taken to a point 5V

close to the load (or output connector) because the load 100

currents flow in these capacitors at high frequencies. The +IN 90

and −IN circuits (for example, a termination resistor and Pin 3)

must be taken to a common point on the ground plane close to
the amplifier package.
Use low impedance 0.22 μF capacitors (AVX SR305C224KAA
or equivalent) wherever ac coupling is required. Include either
10
ferrite beads and/or a small series resistance (approximately
0
4.7 Ω) in each supply line.

00897-035
500ns
INPUT IMPEDANCE
At low frequencies, negative feedback keeps the resistance at the Figure 35. Driving 1000 pF CL with Feedforward Network of Figure 34
inverting input close to zero. As the frequency increases, the SETTLING TIME
impedance looking into this input increases from near zero to
Settling time is measured with the circuit of Figure 36. This
the open-loop input resistance, due to bandwidth limitations,
circuit employs a false summing node, clamped by the two
making the input seem inductive. If it is desired to keep the
Schottky diodes, to create the error signal and limit the input
input impedance flatter, a series RC network can be inserted
signal to the oscilloscope. For measuring settling time, the ratio
across the input. The resistor is chosen so that the parallel sum
of R6/R5 is equal to R1/R2. For unity gain, R6 = R5 = 1 kΩ, and
of it and R2 equals the desired termination resistance. The capacit-
RL = 500 Ω. For the gain of −10, R5 = 50 Ω, R6 = 500 Ω, and RL
ance is set so that the pole determined by this RC network is
was not used because the summing network loads the output
about half the bandwidth of the op amp. This network is not
with approximately 275 Ω. Using this network in a unity-gain
important if the input resistor is much larger than the termination
configuration, settling time is 100 ns to 0.1% for a –5 V to +5 V
used, or if frequencies are relatively low. In some cases, the
step with CL = 10 pF.
small peaking that occurs without the network can be of use in
TO SCOPE
extending the −3 dB bandwidth. (TEK 7A11 FET PROBE)

DRIVING LARGE CAPACITIVE LOADS R5 R6

Capacitive drive capability is 100 pF without an external net-
D1 D2
work. With the addition of the network shown in Figure 34,
the capacitive drive can be extended to over 10,000 pF, limited R1
by internal power dissipation. With capacitive loads, the output
speed becomes a function of the overdriven output current limit. VIN
R2 AD844
Because this is roughly ±100 mA, under these conditions, the VOUT

maximum slew rate into a 1000 pF load is ±100 V/μs. Figure 35 R3

shows the transient response of an inverting amplifier (R1 = RL CL

R2 = 1 kΩ) using the feedforward network shown in Figure 34,
driving a load of 1000 pF.
00897-036

NOTES
1. D1, D2 IN6263 OR EQUIVALENT SCHOTTKY DIODE.

Figure 36. Settling Time Test Fixture

Rev. G | Page 15 of 20
AD844 Data Sheet
+5V
DC ERROR CALCULATION 2.2µF

Figure 37 shows a model of the dc error and noise sources for 3 7 ZO = 50Ω
VIN 50Ω
the AD844. The inverting input bias current, IBN, flows in the 6 VOUT
50Ω 2
4 RL
feedback resistor. IBP, the noninverting input bias current, flows 2.2µF 50Ω
300Ω
in the resistance at Pin 3 (RP), and the resulting voltage (plus
–5V
any offset voltage) appears at the inverting input. The total
300Ω

00897-038
error, VO, at the output is:

VO  I BP R P  VOS  I BN R IN 1 
R1 
  I BN R1 Figure 38. The AD844 as a Cable Driver
 R2 
Because IBN and IBP are unrelated both in sign and magnitude, RF OUT IN VIN
OUT
inserting a resistor in series with the noninverting input does HP8753A CIRCUIT
NETWORK HP11850C
SPLITTER VIN UNDER
ANALYZER RF IN OUT TEST VOUT
not necessarily reduce dc error and may actually increase it.
R1 EXT 50Ω OUT
TRIG (TERMINATOR) 470Ω
SYNC OUT

HP3314A OUT

00897-039
STAIRCASE
VN GENERATOR
R2 RIN

VOS
Figure 39. Differential Gain/Phase Test Setup
INN IBN
0.3
IRE = 7.14mV

INP IBP 0.2

DIFFERENTIAL PHASE (Degrees)

RP AD844 0.1
00897-037

0
Figure 37. Offset Voltage and Noise Model for the AD844
–0.1
NOISE
Noise sources can be modeled in a manner similar to the dc bias –0.2
currents, but the noise sources are INN, INP, VN, and the amplifier
induced noise at the output, VON, is: –0.3

00897-040
0 18 36 54 72 90
2
I NP R P  1  R1   I NN R12
VOUT (IRE)
VON  2
 VN 2
 R2  Figure 40. Differential Phase for the Circuit of Figure 38
0.06
Overall noise can be reduced by keeping all resistor values to a IRE = 7.14mV
minimum. With typical numbers, R1 = R2 = 1 kΩ, RP = 0 Ω,
0.04
VN = 2 nV/√Hz, INP = 10 pA/√Hz, INN = 12 pA/√Hz, and VON
DIFFERENTIAL GAIN (%)

calculates to 12 nV/√Hz. The current noise is dominant in this

0.02
case, because it is in most low gain applications.
VIDEO CABLE DRIVER USING ±5 V SUPPLIES 0

The AD844 can be used to drive low impedance cables. Using

±5 V supplies, a 100 Ω load can be driven to ±2.5 V with low –0.02

distortion. Figure 38 shows an illustrative application that

–0.04
provides a noninverting gain of +2, allowing the cable to be
reverse-terminated while delivering an overall gain of +1 to the
–0.06
load. The −3 dB bandwidth of this circuit is typically 30 MHz.
00897-041

0 18 36 54 72 90
Figure 39 shows a differential gain and phase test setup. In video VOUT (IRE)

applications, differential-phase and differential-gain characteris- Figure 41. Differential Gain for the Circuit of Figure 38
tics are often important. Figure 40 shows the variation in phase as
the load voltage varies. Figure 41 shows the gain variation.

Rev. G | Page 16 of 20
Data Sheet AD844

1 MSB +15V (VCC) 24 +15V

0.22µF* 0.22µF*
2 REFCOM 23
0.22µF* 0.22µF*
3 –15V (VEE) 22 –15V
4 IBPO 21
2 7
5 IOUT 20
AD844 6 VOUT
DIGITAL 6 AD568 RL 19
3 4
INPUTS RI
7 ACOM 18
ANALOG
8 LCOM 17 SUPPLY
GROUND
9 SPAN 16
10 SPAN 15
GROUND
11 THCOM 14 DIGITAL
100pF SUPPLY
12 LSB VTH 13
–5V
TOP VIEW

00897-042
(Not to Scale)
*POWER SUPPLY BYPASS CAPACITORS.
Figure 42. High Speed DAC Amplifier

HIGH SPEED DAC BUFFER 20 MHZ VARIABLE GAIN AMPLIFIER

The AD844 performs very well in applications requiring current- The AD844 is an excellent choice as an output amplifier for the
to-voltage conversion. Figure 42 shows connections for use with AD539 multiplier, in all of its connection modes. (See the
the AD568 current output DAC. In this application, the bipolar AD539 data sheet for full details.) Figure 44 shows a simple
offset is used so that the full-scale current is ±5.12 mA, which multiplier providing the output:
generates an output of ±5.12 V using the 1 kΩ application resistor VXVY
on the AD568. Figure 43 shows the full-scale transient response. VW   (1)
2V
Care is needed in power supply decoupling and grounding
techniques to achieve the full 12-bit accuracy and realize the where VX is the gain control input, a positive voltage from 0 V
fast settling capabilities of the system. The AD568 data sheet to 3.2 V (maximum), and VY is the signal voltage, nominally
should be consulted for more complete details about its use. ±2 V full scale but capable of operation up to ±4.2 V.

2V
The peak output in this configuration is thus ±6.7 V. Using all
four of the internal application resistors provided on the AD539
100
in parallel results in a feedback resistance of 1.5 kΩ, at which
90
value the bandwidth of the AD844 is about 22 MHz, and is
essentially independent of VX. The gain at VX = 3.16 V is 4 dB.
+VS
TYP +6V
10Ω 10Ω AT 15µA

0.22µF 0.22µF
INPUTS
10
VX*
0 1 16
0V TO 3V
2 15
00897-043

50ns VY*
3 14 2
±2V FS 7

Figure 43. DAC Amplifier Full-Scale Transient Response 4 AD539 13 AD844 6

3nF TOP VIEW OUTPUT
4
5 (Not to Scale) 12 3 VW

6 11
–VXVY
7 10 VW =
INPUT 0.22µF 2V
GND 8 9
10Ω

–VS
0.22µF TYP –6V
10Ω AT 15µA
00897-044

*VX AND VY INPUTS MAY OPTIONALLY BE TERMINATED;

TYPICALLY BY USING A 50Ω OR 75Ω RESISTOR TO GROUND.

Figure 44. 20 MHz VGA Using the AD539

Rev. G | Page 17 of 20
AD844 Data Sheet
4
Figure 45 shows the small signal response for a 50 dB gain control VX = 3.15V
range (VX = 10 mV to 3.16 V). At small values of VX, capacitive
–6
feedthrough on the PC board becomes troublesome and very VX = 1.0V
careful layout techniques are needed to minimize this problem.
–16
A ground strip between the pins of the AD539 is helpful in this VX = 0.316V

GAIN (dB)
regard. Figure 46 shows the response to a 2 V pulse on VY for
–26
VX = 1 V, 2 V, and 3 V. For these results, a load resistor of 500 Ω VX = 0.10V
was used and the supplies were ±9 V. The multiplier operates
–36
from supplies between ±4.5 V and ±16.5 V. VX = 0.032V

Disconnecting Pin 9 and Pin 16 on the AD539 alters the –46

denominator in Equation 1 to 1 V, and the bandwidth is
approximately 10 MHz, with a maximum gain of 10 dB. –56

00897-045
Using only Pin 9 or Pin 16 results in a denominator of 0.5 V, 100k 1M 10M 60M
FREQUENCY (Hz)
a bandwidth of 5 MHz, and a maximum gain of 16 dB.
Figure 45. VGA AC Response

1V 1V 50ns

100

90

10

00897-046
Figure 46. VGA Transient Response with VX = 1 V, 2 V, and 3 V

Rev. G | Page 18 of 20
Data Sheet AD844

OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)

8 5 0.280 (7.11)
0.250 (6.35)
1 0.240 (6.10)
4
0.325 (8.26)
0.310 (7.87)
0.100 (2.54) 0.300 (7.62)
BSC 0.060 (1.52) 0.195 (4.95)
0.210 (5.33) MAX 0.130 (3.30)
MAX 0.115 (2.92)
0.015
0.150 (3.81) (0.38) 0.015 (0.38)
0.130 (3.30) MIN GAUGE
0.115 (2.92) PLANE 0.014 (0.36)
SEATING
PLANE 0.010 (0.25)
0.022 (0.56) 0.008 (0.20)
0.005 (0.13) 0.430 (10.92)
0.018 (0.46) MIN MAX
0.014 (0.36)

0.070 (1.78)
0.060 (1.52)
0.045 (1.14)

COMPLIANT TO JEDEC STANDARDS MS-001

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

070606-A
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.

Figure 47. 8-Lead Plastic Dual-in-Line Package [PDIP]

(N-8)
Dimensions shown in inches and (millimeters)

0.005 (0.13) 0.055 (1.40)

MIN MAX

8 5
0.310 (7.87)
0.220 (5.59)
1 4

0.100 (2.54) BSC

0.405 (10.29) MAX 0.320 (8.13)

0.290 (7.37)
0.200 (5.08) 0.060 (1.52)
MAX 0.015 (0.38)

0.200 (5.08) 0.150 (3.81)

MIN
0.125 (3.18)
0.015 (0.38)
0.023 (0.58) SEATING 15°
PLANE 0.008 (0.20)
0.014 (0.36) 0.070 (1.78) 0°
0.030 (0.76)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 48. 8-Lead Ceramic Dual In-Line Package [CERDIP]

(Q-8)
Dimensions shown in inches and (millimeters)

Rev. G | Page 19 of 20
AD844 Data Sheet
10.50 (0.4134)
10.10 (0.3976)

16 9
7.60 (0.2992)
7.40 (0.2913)

1 10.65 (0.4193)
8
10.00 (0.3937)

1.27 (0.0500) 0.75 (0.0295)

BSC 45°
2.65 (0.1043) 0.25 (0.0098)
0.30 (0.0118) 2.35 (0.0925)
8°
0.10 (0.0039) 0°
COPLANARITY
0.10 0.51 (0.0201) SEATING 1.27 (0.0500)
PLANE 0.33 (0.0130)
0.31 (0.0122) 0.20 (0.0079) 0.40 (0.0157)

COMPLIANT TO JEDEC STANDARDS MS-013- AA

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

032707-B
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 49. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)

ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD844AN −40°C to +85°C 8-Lead Plastic Dual In-Line Package [PDIP] N-8
AD844ANZ1 −40°C to +85°C 8-Lead Plastic Dual In-Line Package [PDIP] N-8
AD844ACHIPS −40°C to +85°C Die
AD844AQ −40°C to +85°C 8-Lead Ceramic Dual In-Line Package [CERDIP] Q-8
AD844BQ −40°C to +85°C 8-Lead Ceramic Dual In-Line Package [CERDIP] Q-8
AD844JRZ-161 0°C to 70°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
AD844JRZ-16-REEL71 0°C to 70°C 16-Lead SOIC_W, 7” Tape and Reel RW-16
AD844SCHIPS −55°C to +125°C Die
AD844SQ −55°C to +125°C 8-Lead Ceramic Dual In-Line Package [CERDIP] Q-8
AD844SQ/883B −55°C to +125°C 8-Lead Ceramic Dual In-Line Package [CERDIP] Q-8
5962-8964401PA2 −55°C to +125°C 8-Lead Ceramic Dual In-Line Package [CERDIP] Q-8
1
Z = RoHS Compliant Part.
2
Refer to the DESC drawing for tested specifications.

©1989–2017 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D00897-0-5/17(G)

Rev. G | Page 20 of 20
 Low Cost
Analog Multiplier
Data Sheet AD633
FEATURES FUNCTIONAL BLOCK DIAGRAM
4-quadrant multiplication X1
1
Low cost, 8-lead SOIC and PDIP packages X2

Complete—no external components required A W

Laser-trimmed accuracy and stability 1

Total error within 2% of full scale 10V Z
Differential high impedance X and Y inputs Y1
1

00786-023
High impedance unity-gain summing input Y2
Laser-trimmed 10 V scaling reference
Figure 1.
APPLICATIONS
Multiplication, division, squaring
Modulation/demodulation, phase detection
Voltage-controlled amplifiers/attenuators/filters

GENERAL DESCRIPTION
The AD633 is a functionally complete, four-quadrant, analog The AD633 is available in 8-lead PDIP and SOIC packages. It is
multiplier. It includes high impedance, differential X and Y inputs, specified to operate over the 0°C to 70°C commercial temperature
and a high impedance summing input (Z). The low impedance range (J Grade) or the −40°C to +85°C industrial temperature
output voltage is a nominal 10 V full scale provided by a buried range (A Grade).
Zener. The AD633 is the first product to offer these features in
PRODUCT HIGHLIGHTS
modestly priced 8-lead PDIP and SOIC packages.
1. The AD633 is a complete four-quadrant multiplier offered
The AD633 is laser calibrated to a guaranteed total accuracy of in low cost 8-lead SOIC and PDIP packages. The result is a
2% of full scale. Nonlinearity for the Y input is typically less product that is cost effective and easy to apply.
than 0.1% and noise referred to the output is typically less than 2. No external components or expensive user calibration are
100 µV rms in a 10 Hz to 10 kHz bandwidth. A 1 MHz bandwidth, required to apply the AD633.
20 V/µs slew rate, and the ability to drive capacitive loads make 3. Monolithic construction and laser calibration make the
the AD633 useful in a wide variety of applications where device stable and reliable.
simplicity and cost are key concerns. 4. High (10 MΩ) input resistances make signal source
The versatility of the AD633 is not compromised by its simplicity. loading negligible.
The Z input provides access to the output buffer amplifier, enabling 5. Power supply voltages can range from ±8 V to ±18 V. The
the user to sum the outputs of two or more multipliers, increase internal scaling voltage is generated by a stable Zener diode;
the multiplier gain, convert the output voltage to a current, and multiplier accuracy is essentially supply insensitive.
configure a variety of applications. For further information, see
the Multiplier Application Guide.

Rev. K Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved.
Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
AD633 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Squaring and Frequency Doubling .............................................9
Applications ....................................................................................... 1 Generating Inverse Functions .....................................................9
Functional Block Diagram .............................................................. 1 Variable Scale Factor .................................................................. 10
General Description ......................................................................... 1 Current Output ........................................................................... 10
Product Highlights ........................................................................... 1 Linear Amplitude Modulator ................................................... 10
Revision History ............................................................................... 2 Voltage-Controlled, Low-Pass and High-Pass Filters............ 10
Specifications..................................................................................... 3 Voltage-Controlled Quadrature Oscillator................................... 11
Absolute Maximum Ratings ............................................................ 4 Automatic Gain Control (AGC) Amplifiers ........................... 11
Thermal Resistance ...................................................................... 4 Model Results .................................................................................. 13
ESD Caution .................................................................................. 4 Examples of DC, Sin, and Pulse Solutions Using Multisim.. 13
Pin Configurations and Function Descriptions ........................... 5 Examples of DC, Sin, and Pulse Solutions Using PSPICE .... 14
Typical Performance Characteristics ............................................. 6 Examples of DC, Sin, and Pulse Solutions Using SIMetrix .. 14
Functional Description .................................................................... 8 Evaluation Board ............................................................................ 16
Error Sources................................................................................. 8 Outline Dimensions ....................................................................... 19
Applications Information ................................................................ 9 Ordering Guide .......................................................................... 20
Multiplier Connections ............................................................... 9

REVISION HISTORY
3/15—Rev. J to Rev. K Renumbered Sequentially ............................................................. 12
Changes to General Description Section ...................................... 1 Changes to Ordering Guide .......................................................... 15
Changes to Figure 12 Caption and Figure 14 Caption ................ 9
Added Model Results Section, Examples of DC, Sin, and 4/11—Rev. G to Rev. H
Pulse Solutions Using Multisim Section, and Figure 24 Changes to Figure 1, Deleted Figure 2 ............................................1
Through Figure 29, Renumbered Sequentially........................... 13 Added Figure 2, Figure 3, Table 4, Table 5 .....................................5
Added Examples of DC, Sin, and Pulse Solutions Using Deleted Figure 9, Renumbered Subsequent Figures .....................6
PSPICE Section, Examples of DC, Sin, and Pulse Solutions Changes to Figure 15.........................................................................9
Using SIMetrix Section, and Figure 30 Through Figure 37 ...... 14 4/10—Rev. F to Rev. G
Added Figure 38 Through Figure 41 ........................................... 15 Changes to Equation 1 ......................................................................6
Changes to Equation 5 and Figure 14 .............................................7
9/13—Rev. I to Rev. J Changes to Figure 21.........................................................................9
Reorganized Layout ............................................................ Universal
Change to Table 1 ............................................................................. 3 10/09—Rev. E to Rev. F
Changes to Figure 4 .......................................................................... 6 Changes to Format ............................................................. Universal
Added Figure 10, Renumbered Sequentially ................................ 7 Changes to Figure 21.........................................................................9
Changes to Figure 15 ........................................................................ 9 Updated Outline Dimensions ....................................................... 11
Changes to Figure 20 ...................................................................... 10 Changes to Ordering Guide .......................................................... 12
Changes to Figure 31 ...................................................................... 14
Added Figure 32.............................................................................. 15 10/02—Rev. D to Rev. E
Edits to Title of 8-Lead Plastic SOIC Package (RN-8) .................1
2/12—Rev. H to Rev. I Edits to Ordering Guide ...................................................................2
Changes to Figure 1 .......................................................................... 1 Change to Figure 13 ..........................................................................7
Changes to Figure 2 .......................................................................... 5 Updated Outline Dimensions ..........................................................8
Changes to Generating Inverse Functions Section ...................... 8
Changes to Figure 15 ........................................................................ 9
Added Evaluation Board Section and Figure 23 to Figure 29,

Rev. K | Page 2 of 20
Data Sheet AD633

SPECIFICATIONS
TA = 25°C, VS = ±15 V, RL ≥ 2 kΩ.

Table 1.
AD633J, AD633A
Parameter Conditions Min Typ Max Unit
TRANSFER FUNCTION
W=
(X1 − X2 )(Y1 − Y2 ) + Z
10 V
MULTIPLIER PERFORMANCE
Total Error −10 V ≤ X, Y ≤ +10 V ±1 ±21 % full scale
TMIN to TMAX ±3 % full scale
Scale Voltage Error SF = 10.00 V nominal ±0.25% % full scale
Supply Rejection VS = ±14 V to ±16 V ±0.01 % full scale
Nonlinearity, X X = ±10 V, Y = +10 V ±0.4 ±11 % full scale
Nonlinearity, Y Y = ±10 V, X = +10 V ±0.1 ±0.41 % full scale
X Feedthrough Y nulled, X = ±10 V ±0.3 ±11 % full scale
Y Feedthrough X nulled, Y = ±10 V ±0.1 ±0.41 % full scale
Output Offset Voltage2 ±5 ±501 mV
DYNAMICS
Small Signal Bandwidth VO = 0.1 V rms 1 MHz
Slew Rate VO = 20 V p-p 20 V/µs
Settling Time to 1% ΔVO = 20 V 2 µs
OUTPUT NOISE
Spectral Density 0.8 µV/√Hz
Wideband Noise f = 10 Hz to 5 MHz 1 mV rms
f = 10 Hz to 10 kHz 90 µV rms
OUTPUT
Output Voltage Swing ±111 V
Short Circuit Current RL = 0 Ω 30 401 mA
INPUT AMPLIFIERS
Signal Voltage Range Differential ±101 V
Common mode ±101 V
Offset Voltage (X, Y) ±5 ±301 mV
CMRR (X, Y) VCM = ±10 V, f = 50 Hz 60 1
80 dB
Bias Current (X, Y, Z) 0.8 2.01 µA
Differential Resistance 10 MΩ
POWER SUPPLY
Supply Voltage
Rated Performance ±15 V
Operating Range ±81 ±181 V
Supply Current Quiescent 4 61 mA
1
This specification was tested on all production units at electrical test. Results from those tests are used to calculate outgoing quality levels. All minimum and maximum
specifications are guaranteed; however, only this specification was tested on all production units.
2
Allow approximately 0.5 ms for settling following power on.

Rev. K | Page 3 of 20
AD633 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 2. Stresses at or above those listed under Absolute Maximum
Parameter Rating Ratings may cause permanent damage to the product. This is a
Supply Voltage ±18 V stress rating only; functional operation of the product at these
Internal Power Dissipation 500 mW or any other conditions above those indicated in the operational
Input Voltages1 ±18 V section of this specification is not implied. Operation beyond
Output Short-Circuit Duration Indefinite the maximum operating conditions for extended periods may
Storage Temperature Range −65°C to +150°C affect product reliability.
Operating Temperature Range THERMAL RESISTANCE
AD633J 0°C to 70°C
θJA is specified for the worst-case conditions, that is, a device
AD633A −40°C to +85°C
soldered in a circuit board for surface-mount packages.
Lead Temperature (Soldering, 60 sec) 300°C
ESD Rating 1000 V Table 3.
1
For supply voltages less than ±18 V, the absolute maximum input voltage is Package Type θJA Unit
equal to the supply voltage. 8-Lead PDIP 90 °C/W
8-Lead SOIC 155 °C/W

ESD CAUTION

Rev. K | Page 4 of 20
Data Sheet AD633

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

X1 1 8 +VS Y1 1 8 X2
1 1 1

X2 2 A 7 W Y2 2 1 7 X1
10V
1
Y1 3 10V 6 Z –VS 3 6 +VS
A

1
Y2 4 5 –VS Z 4 5 W

AD633JN/AD633AN AD633JR/AD633AR

00786-002
00786-001
(X1 – X2)(Y1 – Y2) (X1 – X2)(Y1 – Y2)
W= +Z W= +Z
10V 10V

Figure 2. 8-Lead PDIP Figure 3. 8-Lead SOIC

Table 4. 8-Lead PDIP Pin Function Descriptions Table 5. 8-Lead SOIC Pin Function Descriptions
Pin No. Mnemonic Description Pin No. Mnemonic Description
1 X1 X Multiplicand Noninverting Input 1 Y1 Y Multiplicand Noninverting Input
2 X2 X Multiplicand Inverting Input 2 Y2 Y Multiplicand Inverting Input
3 Y1 Y Multiplicand Noninverting Input 3 −VS Negative Supply Rail
4 Y2 Y Multiplicand Inverting Input 4 Z Summing Input
5 −VS Negative Supply Rail 5 W Product Output
6 Z Summing Input 6 +VS Positive Supply Rail
7 W Product Output 7 X1 X Multiplicand Noninverting Input
8 +VS Positive Supply Rail 8 X2 X Multiplicand Inverting Input

Rev. K | Page 5 of 20
AD633 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

100
0dB = 0.1V rms, RL = 2kΩ

0 90
CL = 1000pF
OUTPUT RESPONSE (dB)

80

CL = 0.01µF 70

CMRR (dB)
–10 TYPICAL
FOR X, Y
60 INPUTS

50
–20
NORMAL 40
CONNECTION

00786-003
30

00786-006
–30 20
10k 100k 1M 10M 100 1k 10k 100k 1M
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 4. Frequency Response Figure 7. CMRR vs. Frequency

700 1.5

NOISE SPECTRAL DENSITY (µV/ Hz)

600
BIAS CURRENT (nA)

1.0
500

400
0.5

300

00786-007
00786-004

200 0
–60 –40 –20 0 20 40 60 80 100 120 140 10 100 1k 10k 100k
TEMPERATURE (°C) FREQUENCY (Hz)

Figure 5. Input Bias Current vs. Temperature (X, Y, or Z Inputs) Figure 8. Noise Spectral Density vs. Frequency
14 1k
PEAK POSITIVE OR NEGATIVE SIGNAL (V)

PEAK-TO-PEAK FEEDTHROUGH (mV)

12 Y-FEEDTHROUGH
100
OUTPUT, RL ≥ 2kΩ

10 X-FEEDTHROUGH

10
ALL INPUTS
8

1
6
00786-005

00786-008

4 0.1
8 10 12 14 16 18 20 10 100 1k 10k 100k 1M 10M
PEAK POSITIVE OR NEGATIVE SUPPLY (V) FREQUENCY (Hz)

Figure 6. Input and Output Signal Ranges vs. Supply Voltages Figure 9. AC Feedthrough vs. Frequency

Rev. K | Page 6 of 20
Data Sheet AD633
3

1
OUTPUT (±mV)

−1

−2

−3

00786-009
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
TIME (Minutes)

Figure 10. Typical VOS vs. Time, For Five Minutes Following Power Up

Rev. K | Page 7 of 20
AD633 Data Sheet

FUNCTIONAL DESCRIPTION
The AD633 is a low cost multiplier comprising a translinear ERROR SOURCES
core, a buried Zener reference, and a unity-gain connected Multiplier errors consist primarily of input and output offsets,
output amplifier with an accessible summing node. Figure 1 scale factor error, and nonlinearity in the multiplying core. The
shows the functional block diagram. The differential X and Y input and output offsets can be eliminated by using the optional
inputs are converted to differential currents by voltage-to-current trim of Figure 11. This scheme reduces the net error to scale
converters. The product of these currents is generated by the factor errors (gain error) and an irreducible nonlinearity
multiplying core. A buried Zener reference provides an overall component in the multiplying core. The X and Y nonlinearities
scale factor of 10 V. The sum of (X × Y)/10 + Z is then applied are typically 0.4% and 0.1% of full scale, respectively. Scale
to the output amplifier. The amplifier summing Node Z allows factor error is typically 0.25% of full scale. The high impedance
the user to add two or more multiplier outputs, convert the Z input should always reference the ground point of the driven
output voltage to a current, and configure various analog system, particularly if it is remote. Likewise, the differential X
computational functions. and Y inputs should reference their respective grounds to
Inspection of the block diagram shows the overall transfer realize the full accuracy of the AD633.
function is +VS

W=
(X1 − X2 )(Y1 − Y2 ) + Z (1) ±50mV
300kΩ
10 V 50kΩ TO APPROPRIATE
INPUT TERMINAL
1kΩ (FOR EXAMPLE, X2, Y2, Z)

00786-010
–VS

Figure 11. Optional Offset Trim Configuration

Rev. K | Page 8 of 20
Data Sheet AD633

APPLICATIONS INFORMATION
The AD633 is well suited for such applications as modulation +15V

and demodulation, automatic gain control, power measurement, 0.1µF

E X1 +VS 8
voltage-controlled amplifiers, and frequency doublers. These
1

R E2
applications show the pin connections for the AD633JN (8-lead 2 X2 W 7
R1
W=
10V
AD633JN 1kΩ
PDIP), which differs from the AD633JR (8-lead SOIC). 3 Y1 Z 6
C
R2
MULTIPLIER CONNECTIONS 4 Y2 –VS 5 3kΩ

Figure 12 shows the basic connections for multiplication. The X

00786-013
0.1µF
and Y inputs normally have their negative nodes grounded, but –15V
they are fully differential, and in many applications, the grounded Figure 14. Bounceless Frequency Doubler (See the Model Results Section)
inputs may be reversed (to facilitate interfacing with signals of a
particular polarity while achieving some desired output polarity), At ωo = 1/CR, the X input leads the input signal by 45° (and is
or both may be driven. attenuated by √2), and the Y input lags the X input by 45° (and
+15V
is also attenuated by √2). Because the X and Y inputs are 90° out of
phase, the response of the circuit is (satisfying Equation 3)
0.1µF
1 E
( )E( )
+ 1 X1 +VS 8
W=
(10 V ) 2 sin ω0t + 45° 2 sin ω0t + 45°
X
INPUT (X1 – X2)(Y1 – Y2)
– 2 X2 W 7 W= +Z
10V
AD633JN 2
E
( )
+ 3 Y1 Z 6 OPTIONAL SUMMING
=
(40 V ) sin 2 ω t (4)
Y INPUT, Z
INPUT 0
– 4 Y2 –VS 5
0.1µF
00786-011

which has no dc component. Resistor R1 and Resistor R2 are

–15V
included to restore the output amplitude to 10 V for an input
Figure 12. Basic Multiplier Connections (See the Model Results Section)
amplitude of 10 V.
SQUARING AND FREQUENCY DOUBLING The amplitude of the output is only a weak function of frequency;
As is shown in Figure 13, squaring of an input signal, E, is the output amplitude is 0.5% too low at ω = 0.9 ω0 and ω0 = 1.1 ω0.
achieved simply by connecting the X and Y inputs in parallel to GENERATING INVERSE FUNCTIONS
produce an output of E2/10 V. The input can have either polarity,
but the output is positive. However, the output polarity can be Inverse functions of multiplication, such as division and square
reversed by interchanging the X or Y inputs. The Z input can be rooting, can be implemented by placing a multiplier in the feedback
used to add a further signal to the output. loop of an op amp. Figure 15 shows how to implement square
+15V
rooting with the transfer function for the condition E < 0.
0.1µF The 1N4148 diode is required to prevent latchup, which can
E 1 X1 +VS 8 occur in such applications if the input were to change polarity,
2 X2 W 7 W=
E2 even momentarily.
10V
AD633JN
3 Y1 Z 6
W = − (10E )V (5)
4 Y2 –VS 5
10kΩ
0.1µF
00786-012

+15V +15V
–15V 0.01µF 0.1µF
1 X1 +VS 8
Figure 13. Connections for Squaring 0.1µF
10kΩ 7 2 X2 W 7
When the input is a sine wave E sin ωt, this squarer behaves as a E < 0V 2
AD633JN
AD711 Y1 Z 6
frequency doubler, because
6 3
1N4148 –15V
3

(E sin ωt )
4 4 Y2 –VS 5
2 2
=
E
(1 − cos 2 ωt ) (2) 0.1µF
0.1µF

10 V 20 V
000786-014

–15V W = √ –(10V)E
Equation 2 shows a dc term at the output that varies strongly
Figure 15. Connections for Square Rooting
with the amplitude of the input, E. This can be avoided using
the connections shown in Figure 14, where an RC network is
used to generate two signals whose product has no dc term. It
uses the identity

cos θ sin θ =
1
(sin 2 θ ) (3)
2
Rev. K | Page 9 of 20
AD633 Data Sheet
Likewise, Figure 16 shows how to implement a divider using a This arrangement forms the basis of voltage-controlled integrators
multiplier in a feedback loop. The transfer function for the and oscillators as is shown later in this section. The transfer
divider is function of this circuit has the form
1  X1  X2Y1  Y2
W   10 V 
E
(6) IO  (7)
EX R 10 V
R
10kΩ LINEAR AMPLITUDE MODULATOR
+15V +15V The AD633 can be used as a linear amplitude modulator with no
0.1µF 0.1µF external components. Figure 19 shows the circuit. The carrier
EX 1 X1 +VS 8
R and modulation inputs to the AD633 are multiplied to produce
10kΩ X2 W 7
E 2
7 2 a double sideband signal. The carrier signal is fed forward to the
AD633JN
AD711 6 3 Y1 Z 6 Z input of the AD633 where it is summed with the double
0.1µF
3
4 4 Y2 –VS 5
sideband signal to produce a double sideband with the carrier
0.1µF
output.
+15V
–15V
–15V 00786-015
E 0.1µF
W' = –10V MODULATION +
EX 1 X1 +VS 8
INPUT
Figure 16. Connections for Division ±EM – EM
2 X2 W 7 W = 1+ EC sin ωt
10V
AD633JN
VARIABLE SCALE FACTOR CARRIER 3 Y1 Z 6
INPUT
EC sin ωt –VS 5
In some instances, it may be desirable to use a scaling voltage 4 Y2
0.1µF
other than 10 V. The connections shown in Figure 17 increase

00786-018
the gain of the system by the ratio (R1 + R2)/R1. This ratio is –15V

limited to 100 in practical applications. The summing input, S, Figure 19. Linear Amplitude Modulator
can be used to add an additional signal to the output, or it can
VOLTAGE-CONTROLLED, LOW-PASS AND HIGH-
be grounded.
PASS FILTERS
+15V
Figure 20 shows a single multiplier used to build a voltage-
0.1µF
+ 1 X1 +VS 8 controlled, low-pass filter. The voltage at Output A is a result of
X
INPUT
– (X1 – X2)(Y1 – Y2) R1 + R2 filtering ES. The break frequency is modulated by EC, the control
2 X2 W 7 W= +S
AD633JN R1 10V R1 input. The break frequency, f2, equals
+ 3 Y1 Z 6 1kΩ ≤ R1, R2 ≤ 100kΩ
Y
INPUT EC (8)
– 4 Y2 –VS 5 R2 f2 
0.1µF 10 ( 2  RC )
S
00786-016

and the roll-off is 6 dB per octave. This output, which is at a

–15V high impedance point, may need to be buffered.
Figure 17. Connections for Variable Scale Factor dB
f2 f1
CURRENT OUTPUT 0 f
+15V
The voltage output of the AD633 can be converted to a current –6dB/OCTAVE
OUTPUT B
0.1µF OUTPUT A
output by the addition of a resistor, R, between the W and Z pins of
1 X1 +VS 8
the AD633 as shown in Figure 18. CONTROL
INPUT EC 1 + T1P
2 X2 W 7 OUTPUT B =
+15V 1 + T2P
SIGNAL
AD633JN R 1
3 Y1 Z 6 OUTPUT A =
0.1µF INPUT ES 1 + T2P
0.1µF
+ 1 X1 +VS 8 C 1
X 4 Y2 –VS 5
R T1 = = RC
INPUT 1 (X1 – X2)(Y1 – Y2) ω1
– 2 X2 W 7 IO =
00786-019

R 10V 1 10RC
AD633JN –15V T2 = =
+ 3 Y1 Z 6 1kΩ ≤ R ≤ 100kΩ ω2 EC
Y
INPUT Figure 20. Voltage-Controlled, Low-Pass Filter
– 4 Y2 –VS 5
0.1µF
The voltage at Output B, the direct output of the AD633, has the
00786-017

–15V same response up to frequency f1, the natural breakpoint of RC

Figure 18. Current Output Connections
filter, and then levels off to a constant attenuation of f1/f2 = 10/EC
1
f1  (9)
2  RC
Rev. K | Page 10 of 20
Data Sheet AD633
For example, if R = 8 kΩ and C = 0.002 μF, then Output A has a connected to the Y inputs, varies the integrator gains with a
pole at frequencies from 100 Hz to 10 kHz for EC ranging from calibration of 100 Hz/V. The accuracy is limited by the Y input
100 mV to 10 V. Output B has an additional 0 at 10 kHz (and offsets. The practical tuning range of this circuit is 100:1. C2
can be loaded because it is the low impedance output of the (proportional to C1 and C3), R3, and R4 provide regenerative
multiplier). The circuit can be changed to a high-pass filter Z feedback to start and maintain oscillation. The diode bridge, D1
interchanging the resistor and capacitor as shown in Figure 21. through D4 (1N914s), and Zener diode D5 provide economical
dB temperature stabilization and amplitude stabilization at ±8.5 V
f1 f2 by degenerative damping. The output from the second integrator
0 f
+15V (10 V sin ωt) has the lowest distortion.
OUTPUT B
0.1µF +6dB/OCTAVE
OUTPUT A
AUTOMATIC GAIN CONTROL (AGC) AMPLIFIERS
1 X1 +VS 8
CONTROL Figure 23 shows an AGC circuit that uses an rms-to-dc
INPUT EC OUTPUT B
2 X2 W 7
AD633JN C
converter to measure the amplitude of the output waveform.
SIGNAL 3 Y1 Z 6 OUTPUT A The AD633 and A1, half of an AD712 dual op amp, form a
INPUT ES
R voltage-controlled amplifier. The rms-to-dc converter,
4 Y2 –VS 5
0.1µF an AD736, measures the rms value of the output signal. Its
00786-020
–15V output drives A2, an integrator/comparator whose output
Figure 21. Voltage-Controlled, High-Pass Filter
controls the gain of the voltage-controlled amplifier. The
1N4148 diode prevents the output of A2 from going negative.
VOLTAGE-CONTROLLED QUADRATURE OSCILLATOR R8, a 50 kΩ variable resistor, sets the output level of the circuit.
Figure 22 shows two multipliers being used to form integrators Feedback around the loop forces the voltages at the inverting
with controllable time constants in second-order differential and noninverting inputs of A2 to be equal, thus the AGC.
equation feedback loop. R2 and R5 provide controlled current
output operation. The currents are integrated in capacitors C1
and C2, and the resulting voltages at high impedance are applied
to the X inputs of the next AD633. The frequency control input, EC,
D5
1N5236

D1 D3
1N914 1N914
(10V) cos ωt
D2 D4
1N914 1N914 +15V

0.1µF +15V C2 R4
1 X1 +VS 8 0.01µF 16kΩ
R1
1kΩ 0.1µF
2 X2 W 7 1 X1 +VS 8 R3
R2 330kΩ
AD633JN 16kΩ
EC 3 Y1 Z 6 2 X2 W 7 (10V) sin ωt
C1 AD633JN R5
4 Y2 –VS 5 0.01µF 3 Y1 Z 6 16kΩ
0.1µF 0.1µF C3
4 Y2 –VS 5 0.01µF
–15V
00786-021

EC
–15V f= = kHz
10V

Figure 22. Voltage-Controlled Quadrature Oscillator

Rev. K | Page 11 of 20
AD633 Data Sheet
R2 R3 R4
1kΩ 10kΩ 10kΩ

AGC THRESHOLD +15V

ADJUSTMENT
0.1µF
+15V

0.1µF 8 C1
2 1µF
1 X1 +VS 8 1/2 1 EOUT
AD712 R5
2 X2 W 7 3 10kΩ
AD633JN
Y1 Z 6 A1 R6
E 3
1kΩ
4 Y2 –VS 5
+15V
1 CC COMMON 8
0.1µF
0.1µF
2 VIN +VS 7
–15V
AD736
C2 3 CF OUTPUT 6
0.02µF 0.1µF
4 –VS CAV 5
C3 R10
0.2µF 10kΩ
–15V
C4
A2 33µF
R9 1N4148 6
10kΩ 1/2 +15V
7
AD712 OUTPUT
5 R8
4 50kΩ LEVEL
0.1µF ADJUST

00786-022
–15V

Figure 23. Connections for Use in Automatic Gain Control Circuit

Rev. K | Page 12 of 20
Data Sheet AD633

MODEL RESULTS
Circuit simulation using SPICE models embedded in various
application formats such as PSPICE, Multisim, and SIMetrix is a
popular and efficient method of assessing the integrity of a
circuit before creating the printed circuit board in which the
circuits are ultimately used. Although impossible to
demonstrate all of the multiplier functions in every available
program, Figure 24 through Figure 41 demonstrate how the

00786-126
schematic and graph for simple dc, sin(x), and pulse
applications appear in three popular SPICE programs. If a
Figure 26. Frequency Doubler Circuit Schematic Created in Multisim
simulator is not shown here, a good way to progress is to start
with a basic dc circuit to verify that the circuit converges and
then continue with waveforms that are more complex. When
analyzing nonlinear devices such as multipliers, the most
common simulation issue is convergence, the iterative process
by which SPICE seeks the initial dc bias condition before
completely solving the circuit and displaying a graph.

Figure 24 through Figure 41 are arranged schematic first,

followed by the graphic result. If the user has a problem with a
simulator, the most efficient fix is to contact applications
support for the program in use.

00786-127
EXAMPLES OF DC, SIN, AND PULSE SOLUTIONS
USING MULTISIM Figure 27. Frequency Doubler Response Graph Displayed in Multisim
00786-124

00786-128
Figure 24. Circuit to Multiply Two Integers Schematic Created in Multisim
Figure 28. Pulse Circuit Schematic Created in Multisim
00786-125

00786-129

Figure 25. Circuit to Multiply Two Integers Response Graph Displayed in Multisim
(2 V × 4 V)/10 V = 0.8 V
Figure 29. Pulse Circuit Response Graph Displayed in Multisim

Rev. K | Page 13 of 20
AD633 Data Sheet
EXAMPLES OF DC, SIN, AND PULSE SOLUTIONS
USING PSPICE

00786-134
00786-130
Figure 34. Pulse Circuit Schematic Created in PSPICE
Figure 30. Simple Circuit Schematic Created in PSPICE

00786-135
00786-131

Figure 35. Pulse Circuit Response Graph Displayed in PSPICE

Figure 31. Simple Circuit Response Graph Displayed in PSPICE EXAMPLES OF DC, SIN, AND PULSE SOLUTIONS
(2 V × 4 V)/10 V = 0.8 V
USING SIMETRIX
00786-132

00786-136
Figure 32. Frequency Doubler Circuit Schematic Created in PSPICE
Figure 36. Simple Circuit Schematic Created in SIMetrix
00786-133

00786-137

Figure 33. Frequency Doubler Response Graph Displayed in PSPICE

Figure 37.Simple Circuit Response Graph Displayed in SIMetrix
(2 V × 4 V)/10 V = 0.8 V

Rev. K | Page 14 of 20
Data Sheet AD633

00786-138

00786-140
Figure 38. Frequency Doubler Circuit Schematic Created in SIMetrix

Figure 40. Pulse Circuit Schematic Created in SIMetrix

00786-139

Figure 39. Frequency Doubler Response Graph Displayed in SIMetrix

00786-141
Figure 41. Pulse Circuit Response Displayed in SIMetrix

Rev. K | Page 15 of 20
AD633 Data Sheet

EVALUATION BOARD
The evaluation board of the AD633 enables simple bench-top
experimenting to be performed with easy control of the AD633.
Built-in flexibility allows convenient configuration to
accommodate most operating configurations. Figure 42 is a
photograph of the AD633 evaluation board.

00786-026
00786-024 Figure 43. Component Side Copper

Figure 42. AD633 Evaluation Board

Any dual-polarity power supply capable of providing 10 mA or

greater is all that is required to perform the intended tests, in
addition to whatever test equipment the user wants.
Referring to the schematic in Figure 49, inputs to the multiplier are
differential and dc-coupled. Three-position slide switches enhance
flexibility by enabling the multiplier inputs to be connected to

00786-027
an active signal source, to ground, or to a test loop connected
directly to the device pin for direct measurements, such as bias
Figure 44. Circuit Side Copper
current. Inputs may be connected single ended or differentially,
but must have a dc path to ground for bias current. If the
impedance of an input source is non-zero, an equal value
impedance must be connected to the opposite polarity input to
avoid introducing additional offset voltage.
The AD633-EVALZ can be configured for multiplier or divider
operation by switch S1. Refer to Figure 16 for divider circuit
connections.
Figure 43 through Figure 46 are the signal, power, and ground-
plane artworks, and Figure 47 shows the component and circuit
side silkscreen. Figure 48 shows the assembly.
00786-028

Figure 45. Inner Layer Ground Plane

Rev. K | Page 16 of 20
Data Sheet AD633

00786-029

00786-031
Figure 46. Inner Layer Power Plane Figure 48. AD633-EVALZ Assembly

00786-030

Figure 47. Component Side Silk Screen

GND G1 G2 G3 G4 G5 G6
+V −V

C5 + C6
10µF 10µF
25V + 25V
+V −V

Y1_IN
D X2_TP X2_IN
IN FUNCT(1) IN
GND SEL_Y1 SEL_X2 GND
M
TEST Y1_TP TEST
Y2_IN
Y2_TP X1_TP X1_IN
IN AD633ARZ IN (DENOM)
1 8 R1
GND SEL_Y2 Y1 DUT1 X2 SELX1 GND 100Ω
2 7
Y2 X1
TEST TEST
3 6 +V
–VS +VS X2_IN
+V
–VS 4 5
C1 Z W C2 C3
0.1µF 0.1µF 7 0.1µF
3
+
Z_IN R2 Z2 6
Y2_TP
IN D 10kΩ 2 AD711 FUNCTION SWITCH – S1
SEL_Y2 –
GND MULTIPLY:
FUNCT(2) M 4 [(X1-X2)(Y1-Y2)/10V] + Z
TEST R3 C4
NOM_TP 10kΩ 0.1µF DIVIDE:
−V −10V (NUM/DENOM)
NUMERATOR
D
S1
OUT
00786-032

M
OUT_TP

Figure 49. Schematic of the AD633 Evaluation Board

Rev. K | Page 17 of 20
AD633 Data Sheet
POWER SUPPLY

X INPUT DC
VOLTAGE

Y INPUT DC
VOLTAGE OUT – DMM

00786-033
Figure 50. AD633-EVALZ Configured for Bench Experiments

Rev. K | Page 18 of 20
Data Sheet AD633

OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)

8 5 0.280 (7.11)
0.250 (6.35)
1 0.240 (6.10)
4
0.325 (8.26)
0.310 (7.87)
0.100 (2.54) 0.300 (7.62)
BSC 0.060 (1.52) 0.195 (4.95)
0.210 (5.33) MAX 0.130 (3.30)
MAX 0.115 (2.92)
0.015
0.150 (3.81) (0.38) 0.015 (0.38)
0.130 (3.30) MIN GAUGE
0.115 (2.92) PLANE 0.014 (0.36)
SEATING
PLANE 0.010 (0.25)
0.022 (0.56) 0.008 (0.20)
0.005 (0.13) 0.430 (10.92)
0.018 (0.46) MIN MAX
0.014 (0.36)

0.070 (1.78)
0.060 (1.52)
0.045 (1.14)

COMPLIANT TO JEDEC STANDARDS MS-001

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

070606-A
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.

Figure 51. 8-Lead Plastic Dual-in-Line Package [PDIP]

(N-8)
Dimensions shown in inches and (millimeters)
5.00 (0.1968)
4.80 (0.1890)

8 5
4.00 (0.1574) 6.20 (0.2441)
3.80 (0.1497) 1 5.80 (0.2284)
4

1.27 (0.0500) 0.50 (0.0196)

BSC 45°
1.75 (0.0688) 0.25 (0.0099)
0.25 (0.0098) 1.35 (0.0532)
8°
0.10 (0.0040) 0°
COPLANARITY 0.51 (0.0201)
0.10 1.27 (0.0500)
0.31 (0.0122) 0.25 (0.0098)
SEATING 0.40 (0.0157)
PLANE 0.17 (0.0067)

COMPLIANT TO JEDEC STANDARDS MS-012-AA

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
012407-A

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 52. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)

Rev. K | Page 19 of 20
AD633 Data Sheet
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD633ANZ −40°C to +85°C 8-Lead Plastic Dual-in-Line Package [PDIP] N-8
AD633ARZ −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD633ARZ-R7 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel R-8
AD633ARZ-RL −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N], 13" Tape and Reel R-8
AD633JN 0°C to 70°C 8-Lead Plastic Dual-in-Line Package [PDIP] N-8
AD633JNZ 0°C to 70°C 8-Lead Plastic Dual-in-Line Package [PDIP] N-8
AD633JR 0°C to 70°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD633JR-REEL 0°C to 70°C 8-Lead Standard Small Outline Package [SOIC_N], 13" Tape and Reel R-8
AD633JR-REEL7 0°C to 70°C 8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel R-8
AD633JRZ 0°C to 70°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD633JRZ-R7 0°C to 70°C 8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel R-8
AD633JRZ-RL 0°C to 70°C 8-Lead Standard Small Outline Package [SOIC_N], 13" Tape and Reel R-8
AD633-EVALZ Evaluation Board
1
Z = RoHS Compliant Part.

©2015 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D00786-0-3/15(K)

Rev. K | Page 20 of 20
 CURRICULUM VITAE

Pragati Gupta
+917007412069
[email protected]

Pragati Gupta is pursuing B. Tech program in Faculty of Engineering and

Technology, University of Lucknow. She is a 4th year student of Electronics and
Communication Engineering.
She has done a 4-week online training from the company Pie Infocomm in 2020
where she worked on the topic “IOT Technology” under the supervision of Mr.
Lokesh Kumar Singh. She has received online Training of Electronics and
Telecommunication for 4 weeks from BSNL BRBRAITT Jabalpur in 2021.
Pragati Gupta has a keen interest in Analog Signal Processing. Her interest also
includes Analog Circuit Designing, Signal and Image Processing and Internet of
Things.
Samriddhi Shah
+916386328689
[email protected]

Samriddhi Shah is pursuing B. Tech program in Faculty of Engineering and

Technology, University of Lucknow. She is a 4th year student of Electronics and
Communication Engineering.

She has done 6-week project under supervision of Dr. Satyam Agarwal in
Department of Electrical Engineering at IIT ROPAR in 2019 where she worked
on the topic of “Implementation of IOT network for Agriculture”. She has received
online Training of Electronics and Telecommunication for 4 weeks from BSNL
BRBRAITT Jabalpur in 2020.

Samriddhi Shah has deep interest in mathematics. She also likes Signal and
System analysis, Digital Electronics and Analog Designs.
Diksha Verma
+916386035991
[email protected]

Diksha Verma is pursuing B. Tech program in Faculty of Engineering and

Technology, University of Lucknow. She is a 4th year student of Electronics and
Communication Engineering.

She has done 4-week project under supervision of Mr. M. Alam in signal
department at Indian Railways (RDSO). She has received online Training of
“Internet of Things” for 4 weeks from Internshala in 2020.

Diksha Verma has deep interest in Digital Electronics. She also likes Control
System, electromagnetic field theory and Analog electronics.
Anubhav Kumar
+9183185443454.
[email protected]

Anubhav Kumar is pursuing B. Tech program in Faculty of Engineering and

Technology, University of Lucknow. He is a 4th year student of Electronics and
Communication Engineering.
He has done 4-week virtual training program from BSNL BRBRAITT Jabalpur in
2020 in which the main topics were related to telecommunication and networking
and the basics of trending technologies in the IT world.
Anubhav Kumar has his great interest in communication engineering. He also
likes Physics, Optical communication, and Logic circuits as well.