2019design Procedure For Two-Stage CMOS Opamp Using gmID Design Methodology in 16 NM FinFET Technology
2019design Procedure For Two-Stage CMOS Opamp Using gmID Design Methodology in 16 NM FinFET Technology
2019design Procedure For Two-Stage CMOS Opamp Using gmID Design Methodology in 16 NM FinFET Technology
Abstract—This paper proposes a new procedure for the proposed design procedure in comparison with the desired
design of a two-stage (Miller) CMOS operational amplifier in 16 amplifier specifications and followed by a conclusion in
nm FinFET technology based on gm/ID methodology. Unlike the Section IV.
conventional techniques, the proposed design flow allows the
designer to reach the desired Opamp specifications from the II. TWO-STAGE (MILLER) OPAMP DESIGN PROCEDURE
first iteration, using pre-generated gm/ID sizing charts, and
without any need to a compact model equation for the FinFET This section provides a guideline for the design flow of
device. The proposed procedure succeeded in describing the a two-stage (Miller) operational amplifier. It gives the
behavior of the FinFET device not only in strong inversion dimensions of the FinFETs (fin height, fin thickness, and
region but also in the week and moderate inversion regions. The channel length) as well as the value of the compensation
designed Opamp is verified using 16 nm Predictive Technology capacitor that satisfies the amplifier specification. The
Model (PTM-MG) for low-power FinFET (BSIM-CMG, level 72 schematic of the two-stage operational amplifier is shown in
technology). The results show that the proposed design Fig. 1. Table 1 shows the Op-amp targeted specifications. It
methodology fulfills the desired Opamp specifications.
is logical to start the design procedure with the noise
Keywords—FinFET, Opamp design, gm/ID methodology, requirement. At high frequency, the input-referred noise
Moderate inversion, Week inversion. voltage ( ( )) is given by [12]:
2 1 ,
I. INTRODUCTION ( ) = 2 .4 [1 + ] (1)
3 , ,
Nowadays, the great market demands drive the
semiconductor industry toward smaller size and lower power For a lower noise, we can assume , << , . So, the
consumption [1], [2]. System-on-chip designers are in charge transconductance , can be expressed by (2), and then
of covering the required demands. However, by pushing the calculated using the ( ) specification.
manufacture of semiconductors towards sub-20 nm
16 (2)
technology, some effects like short-channel effect (SCE) and , =
gate-dielectric leakage cannot be any more neglected. This 3 ( )
happens due to the lack of gate over channel control. One A. The Compensation Capacitance (CC)
solution is the FinFET technology with a 3D structure in
For a specified value of the gain-bandwidth product, the
which a gate surrounds three sides of a vertical silicon channel
compensation capacitance Cc will be calculated from (3)
(Fin). It leads to enhance the channel control, reduces the
[13], using the gain-bandwidth product (GBW) specification:
leakage current and overcomes the short-channel effect [3],
[4]. Unfortunately, the device downscaling is not the only =
, (3)
problem for the analog designers, but also challenging of the 2 C
conventional square-law MOSFET model that cannot any
more accurately describe the new devices such as FinFET. To B. Input-pair Design (M1 and M2)
overcome this problem, a new design procedure that describes For calculating the aspect ratio of the input pair, first we
FinFET behaviour is highly recommended. The needed have to calculate the drain current ID1 which is calculated
FinFET procedure has to be survived in all inversion regions from the specified slew-rate using equation (4) [12].
(strong, moderate and week inversion regions) in low power
consumption applications [5], [6]. Gm/ID design methodology . (4)
=
[7]–[11] is a promising methodology to overcome the 2
drawbacks of the conventional design that is based on square-
,
law. It gives the analog designer a full control and flexibility = (5)
on the design trade-offs. , + ,
This paper is organized as following. Section II describes Then by choosing a convenient value of the DC-gain for the
a systematic design procedure for the two-stage (Miller) Op- first stage (AV1), and by assuming that gds1,2= gds3,4 for
amp. Section III illustrates the simulation results of the simplicity , the value of the transconductance gds1,2 could be
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85
75 L = 60 nm
65
55
gm/gds
45
35
25
15
L = 20 nm
5
5 10 15 20 25 30 35
gm/Id (S/A)
(a)
Fig. 1. Schematic of the two-stage (Miller) operational amplifier.
18
calculated from (5) [13]. The length (L) of the transistors M1 L = 60 nm
and M2 can be found by finding the intersection point 16
between the pre-calculated values of gm2/ID2 and gm2/gds2
Id/W (μA/μm)
on the first PFET sizing chart shown in Fig. 2(a), then the 14
effective width (W) could be found by finding the
12
intersection point between gm2/ID2 and the choosen length
curve (from the previous step) on the second sizing chart Fig. 10
2(b). thus, we found the aspect ratio (W/L)1,2 for both M1 and
M2. And by using them again on the third sizing chart Fig. 8
2(c) we could found VGS1 that will be used in finding L = 20 nm
(W/L)3,4. 6
C. Current Mirror Load Design (M3 and M4) 12 14 16 18 20
gm/Id (S/A)
To design the active load of the first stage (M3,4), we will
(b)
use the pre-designed values for gds3,4 and ID3,4, and by
assuming an arbitrary but large current efficiency (gm/ID)3,4 0.55
L = 60 nm
(this assumption will be checked soon), we could use
(gm/ID)3,4 and (gm/gds)3,4 on the first NFET sizing chart Fig. 0.53
3(a) on which the length (L3,4) can be picked easily. VGS3,4
will be calculated from the lower common mode input range 0.51
VGS (V)
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In order to achieve the phase margin given in (8), the TABLE 1. SPECIFICATIONS AND SIMULATION RESULTS FOR THE TWO-STAGE
(MILLER) OPAMP
second pole (p2) and the first zero (z1) will be represented in
terms of gm, CL and CC and rewritten in equation (9) [14], so Specification Required Simulation
/ Technology 16 nm FinFET 16 nm FinFET
we can calculate gm6, such that K= ( ). Thus, we have Supply voltage 0.9 V 0.9 V
/
our design knob (gm/ID)6 for designing M6. So, the aspect Load capacitance 5 pF 5 pF
GBW >= 35 MHz 39.1 MHz
ratio (W/L)6 could be found by following the same steps for
DC gain (Ao) >= 60 dB 61.3 dB
achieving (W/L)1,2. Phase margin (PM) >= 60 60.4
CM input range – low <= 0.2 V 0.2 V
° = 90° tan tan (8) CM input range – high >= 0.5 V 0.5 V
2 1 CMRR 70 dB 68 dB
( ) 8 nV/ 8.58 nV/
° = 90° tan tan (9) Slew rate (SR) 15 V/μs 15.4 V/μs
M8 18/40 240 4 9 12
45
CC 1.26 pF
35
25 F. The Second Stage Load (M7) and the copying transistor
15 (M8)
L = 20 nm The output transconductance of M7 (gds7) should have a
5
specific value in order to achieve the required DC voltage
5 10 15 20 25 30 35
gain for the second stage (AV2). Also, for a better mirroring
gm/Id (S/A) accuracy, the length of the transistor M7 should equal the
(a)
length of the transistor M5. Therefore, the effective width of
18 M7 is easily found by following the same way of finding
W3,4,5.
16
The length of the diode-connected transistor M8 has to be
L = 60 nm
Id/W (μA/μm)
0.49 Fig. 5 shows that the DC-gain and the phase margin are
similar to the desired specifications, and the unity gain
0.47 bandwidth is much better than the targeted one. Also fig. 6
L = 20 nm which shows the step response of the designed two-stag
(Miller) Op-amp illustrates a very acceptable slew-rate in
0.45
comparison to the desired specification. Table 1 demonstrates
15 16 17 18 19 20
the accuracy of the proposed design procedure in satisfying
gm/Id (S/A)
the required specifications.
(c)
Fig. 3. Sizing charts 1, a NFIT sizing charts vs gm/ID with length as a
parametric parameter (By a 4 nm step): (a) intrinsic gain (gm/gds), (b)
current density (ID/W), (c) gate-source voltage VGS.
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Read the design specifications (AOL, GBW, CL, PM, SR, CMIR, Sn (f) ...)
Calculate CC
Calculate
,
CMIR, VDSat1
Using L3, 4,
VGS3 in
Calculate VGS3
Sizing
Chart 2(c)
Pick near
ID5, gm3,4, CMRR Yes Check if No
but larger
In Equation (6)
,
,
Calculate gds5
The same flow as (B)
Using gm3/ID3,
L3, 4 in
B Sizing Chart
2(b)
Fig. 4. The proposed design procedure for the two-stage (Miller) opamp.
328
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65.0 200 operational amplifier that confirmed the availability and
60.0 180 simplicity of the proposed procedure have been carried.
55.0 Gain
50.0 Phase 160 REFERENCES
45.0 140
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Fig. 5. Loop gain frequency response of the designed two-stage opamp.
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