Iraudamp 11
Iraudamp 11
CAUTION:
International Rectifier suggests the following guidelines for safe operation and handling of
IRAUDAMP11 Demo board;
Applications
AV receivers
Home theater systems
Mini component stereos
Powered speakers
Sub-woofers
Musical Instrument amplifiers
Automotive after market amplifiers
Features
Specifications
Physical Specifications
Dimensions 3.94”(L) x 2.83”(W) x 0.85”(H)
100 mm (L) x 72 mm (W) x 21.5 mm(H)
Weight 0.130kgm
VR1
IRS2053M
IRF6665
Output Output
CH2 CH1 +B GND -B CH3
250W, 4Ω,
G
Non-inductive Resistors
35 V, 5 A DC supply 35 V, 5 A DC supply
Connector Description
1. Connect 4-200 W dummy loads to 3 output connectors (P2 and P3 as shown on Fig 1)
and an Audio Precision analyzer (AP).
2. Connect the Audio Signal Generator to CN1 for CH1~CH3 respectively (AP).
3. Set up the dual power supply with voltages of ±35V; current limit to 5A.
4. TURN OFF the dual power supply before connecting to On of the unit under test (UUT).
5. Connect the dual power supply to P1. as shown on Fig 1
Power up:
6. Turn ON the dual power supply. The ±B supplies must be applied and removed at the
same time.
7. The Blue LED should turn ON immediately and stay ON
8. Quiescent current for the positive supply should be 75mA 10mA at +35V.
9. Quiescent current for the negative supply should be 95mA 10mA at –35V.
10. With an Oscilloscope, monitor the switching waveform at test points VS1~VS3. Adjust VR1
to set the self oscillating frequency to 400 kHz 25 kHz when DUT in clock synchronize
mode.
2
1
0.5
0.2
% 0.1
0.05
0.02
0.01
0.005
0.002
0.001
100m 200m 500m 1 2 5 10 20 50 100 200
W
.
+4
T
+3
+2
+1
-0
-1
d -2
B
r -3
A -4
-5
-6
-7
-8
-9
-10
20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 200k
Hz
+0
-20
-40
d
B
-60
V
-80
-100
d -50
B
V -75
-100
-125
-150
10 20 50 100 200 500 1k 2k 5k 10k 20k
Hz
.
+0
-1 0
-2 0
-3 0
d -4 0
B
r -5 0
A -6 0
-7 0
-8 0
-9 0
-1 0 0
20 50 100 200 500 1k 2k 5k 10k 20k
Hz
1 1 Cy an S o lid 2 A n lr. A m p l L e ft C H 3 _ o n ; C H 1 _ o ff
3 1 Y e llo w S o lid 2 A n lr. A m p l L e ft C H 1 _ o n ; C H 3 _ o ff
4 1 Red S o lid 2 A n lr. A m p l L e ft C H 2 _ o n ; C H 3 _ o ff
5 1 M agenta S o lid 2 A n lr. A m p l L e ft C H 3 _ o n ; C H 2 _ o ff
6 1 B lu e S o lid 1 A n lr. A m p l L e ft C H 2 _ o n ; C H 1 _ o ff
7 1 Cy an S o lid 1 A n lr. A m p l L e ft C h 1 _ o n ; C H 2 _ o ff
Soft Clipping
IRS2053M has Clipping detection function, it monitors error voltage in COMP pin with a window
comparator and pull an open drain nmos referenced to GND. Threshold to detect is at 10% and
90% of VAA-VSS. Each channel has independent CLIP outputs. Once IRS2053M detects
Clipping, the CLIP pin will generate pulses to trigger soft clipping circuit as Fig 9, which limits
output’s maximum power.
Fig10 shows 20Hz and 20 kHz THD+N versus Power graph in CH3; it shows limitation of output’s
power with different frequency.
R5A
R29A GND
47K
220K
Audio signal INPUT
D3A
C0A 1N4148 R6A
R27A
47K
CLIP Detection
D
10uF,50V 3.3K
G R3A 1K
IN-
Q6
S
C5A
MMBFJ112
10uF, 50V
VSS
GND
10
5
2
1
0.5
0.2
% 0.1
0.05
0.02
0.01
0.005
0.002
0.001
100m 200m 500m 1 2 5 10 20 50 100 300
W
Fig 11 shows efficiency characteristics of the IRAUDAMP11. The high efficiency is achieved by
following major factors:
1) Low conduction loss due to the DirectFETs offering low RDS(ON)
2) Low switching loss due to the DirectFETs offering low input capacitance for fast rise and
fall times
Secure dead-time provided by the IRS2053M, avoiding cross-conduction.
Efficiency (%)
100%
90%
80%
Efficiency (%)
70%
60%
AMP11 35V 4ohms
50%
40%
30%
20%
10%
0%
0 50 100 150
Output power (W)
Thermal Considerations
With this high efficiency, the IRAUDAMP11 design can handle one-eighth of the continuous rated
power, which is generally considered to be a normal operating condition for safety standards,
without additional heatsinks or forced air-cooling.
**DirectFET’s height should be measured from PCB to the top of DirectFET after reflow. The
average height of IRF6665 is 0.6mm.
+0
-10
-20
-30
d -40
B
V -50
-60
-70
-80
-90
20 50 100 200 500 1k 2k 5k 10k 20k 40k
Hz
VS pin VS pin
Load current Load current
The IRAUDAMP11 features a 3CH self-oscillating type PWM modulator for the smallest space,
highest performance and robust design. This topology represents an analog version of a second-
order sigma-delta modulation having a Class D switching stage inside the loop. The benefit of the
sigma-delta modulation, in comparison to the carrier-signal based modulation, is that all the error
in the audible frequency range is shifted to the inaudible upper-frequency range by nature of its
operation. Also, sigma-delta modulation allows a designer to apply a sufficient amount of error
correction.
Integrator
Referring to Fig 17 below, the input operational amplifier of the IRS2053M forms a front-end
second-order integrator with R3x, C2x, C3x, and R2x. The integrator that receives a rectangular
feedback signal from the PWM output via R4x and audio input signal via R3x generates a
quadratic carrier signal at the COMP pin. The analog input signal shifts the average value of the
quadratic waveform such that the duty cycle varies according to the instantaneous voltage of the
analog input signal.
PWM Comparator
The carrier signal at the COMP pin is converted to a PWM signal by an internal comparator that
has a threshold at middle point between VAA and VSS. The comparator has no hysteresis in its
input threshold.
Level Shifters
The internal input level-shifter transfers the PWM signal down to the low-side gate driver section.
The gate driver section has another level-shifter that level shifts up the high-side gate signal to the
high-side gate driver section.
The received PWM signal is sent to the dead-time generation block where a programmable
amount of dead time is added into the PWM signal between the two gate output signals of LO and
HO to prevent potential cross conduction across the output power DirectFETs. The high-side level-
shifter shifts up the high-side gate drive signal out of the dead-time block.
Each channel of the IRS2053M’s drives two DirectFETs, high- and low-sides, in the power stage
providing the amplified PWM waveform.
Output LPF
The amplified PWM output is reconstructed back to an analog signal by the output LC LPF.
Demodulation LC low-pass filter (LPF) formed by L1 and C13, filters out the Class D switching
carrier signal leaving the audio output at the speaker load. A single stage output filter can be used
with switching frequencies of 400 kHz and greater; a design with a lower switching frequency may
require an additional stage of LPF.
The IRAUDAMP11 uses the IRS2053M, a 3 Channel high-voltage (up to 200 V), high-speed
power MOSFET driver with internal dead-time and protection functions specifically designed for
Class D audio amplifier applications. These functions include OCP and UVP. The IRS2053M
integrates bi-directional over current protection for both high-side and low-side MOSFETs. The
dead-time can be selected for optimized performance according to the size of the MOSFET,
minimizing dead-time while preventing shoot-through. As a result, there is no gate-timing
adjustment required externally. Selectable dead-time through the DT pin voltage is an easy and
reliable function which requires only two external resistors, R12 and R13 as shown on Fig 18 or
Fig 24 below.
L1A
CH3 OUTPUT
22uH
R24A 2.2K
2.2K
GND
NC
R14A 4.7R
C16A
0.01uF
C16B
0.01uF
R10
R12
10uF,16V
R12A
IRF6665 N/A
1K
C14A
R32C 10R RpC 95C 22R
R11 8.2K
C13A
C16C
R13
0.01uF
DTA144EKA R4A
100K 1% Q2A
C6A R9A
R7A R5A IRF6665
0.1uF,50V
36
35
34
33
32
31
30
29
28
27
26
25
0.1uF, 63V
0.47uF, 400V
D1A 1N4148
1uF,50V GND
C10A
C19A R19A
0.1uF, 63V
0.47uF, 400V
VCC
COM
NC
OTP2
OTP1
VS3
HO3
OCSET
DT
10K R17A
C12A 220K 10uF, 16V
C14B
C14C
1N4148 47K C2A 2.2nF,50V C3A 2.2nF,50V 37 10K
DS 24
0.1uF,100V
C13C
10R,1W
1nF,50V CSH3 3.9K
MMBFJ112 Q6
3.3K GND
R21B
R21C
D
NC
10K 15K C5A 10uF, 16V
40 D2A 1N4148 4.7R CH2 OUTPUT
G GND 21
LO3 22uH
CN1 C12B IC3 IC1
GND 41
S
CLIP2
CLIP1
CSH2
GND R17C
C10C
HO2
DCP
R23A
VB2
C17C C17A
VS2
VS1
R15C 10K
NC
NC
R14 R15
R19C
R19B
1R
10R 10R
1N4148
R1 R20C Q1C
R22 IRF6665
1
10
11
12
0.1uF,100V
0R0 or N/A
1N4148
C19B
Q2C
10uF, 16V
R26B 10K
R26C 10K
10K
10K
R4 0R0 or N/A D4
C9
3.3k
R41
4 5 P1
120k RTN FB
C61 Q4 C32
D7 +B 3
22uF, 16V
C37
24V
47k 0.1uF, 50V
OVP UVP
R61 10k
C62
0.01uF, 50V
R62 10k
GND GND
For EMI
Self-oscillating frequency is determined by the total delay time along the control loop of the
system; the propagation delay of the IRS2053M, the DirectFETs switching speed, the time-
constant of front-end integrator (R2, R3, R4, C2, C3 ). Variations in +B and –B supply voltages
also affect the self-oscillating frequency.
The self-oscillating frequency changes with the duty ratio. The frequency is highest at idling. It
drops as duty cycle varies away from 50%.
Use R2 to set different self-oscillating frequencies. The PWM switching frequency in this type of
self-oscillating switching scheme greatly impacts the audio performance, both in absolute
frequency and frequency relative to the other channels. In absolute terms, at higher frequencies,
distortion due to switching-time becomes significant, while at lower frequencies, the bandwidth of
the amplifier suffers. In relative terms, interference between channels is most significant if the
relative frequency difference is within the audible range.
Normally, when adjusting the self-oscillating frequency of the different channels, it is suggested to
either match the frequencies accurately, or have them separated by at least 25kHz. Under the
normal operating condition with no audio input signal, the switching-frequency is set around
400kHz in the IRAUDAMP11.
The dead-time of the IRS2053 is set based on the voltage applied to the DT pin. Fig 19 lists the
suggested component value for each programmable dead-time between 45 and 105 ns.
All the IRAUDAMP11 models use DT1 (45ns) dead-time.
Dead- time
45nS
IRS2053M
>0.5mA
65nS Vcc
85nS
R1
DT
105nS
R2
VDT
0.23xVcc 0.36xVcc 0.57xVcc Vcc COM
The external shutdown circuit will disable the output by pulling down CSD pins, (Fig 21). If the
fault condition persists, the protection circuit stays in shutdown until the fault is removed.
R60
SD
15k
GND
Q5
MMBT5551
R54 Z4
10k R57 18V IC6
R51
R56 47k LM26CIM5-XHA
22k
47k 5 1
OS HT
R50 2
Z3 GND
47k R59 4 3
39V R53 VCC VT
22k
OTP
10k
R52
MMBT5551
15k
Q4 D51
MMBT5551 4.7V
Q3
R58
R55 47k
47k
OVP UVP
-B
The low-side current sensing feature protects the low side DirectFET from an overload condition
from negative load current by measuring drain-to-source voltage across RDS(ON) during its on state.
OCP shuts down the switching operation if the drain-to-source voltage exceeds a preset trip level.
The voltage setting on the OCSET pin programs the threshold for low-side over-current sensing.
When the VS voltage becomes higher than the OCSET voltage during low-side conduction, the
IRS2053 turns the outputs off and pulls CSD down to -VSS.
The high-side current sensing protects the high side DirectFET from an overload condition from
positive load current by measuring drain-to-source voltage across RDS(ON) during its on state. OCP
shuts down the switching operation if the drain-to-source voltage exceeds a preset trip level.
High-side over-current sensing monitors drain-to-source voltage of the high-side DirectFET during
the on state through the CSH and VS pins. The CSH pin detects the drain voltage with reference
to the VS pin, which is the source of the high-side DirectFET. In contrast to the low-side current
sensing, the threshold of the CSH pin to trigger OC protection is internally fixed at 1.2V. An
external resistive divider R15, R16 and R17 are used to program a threshold as shown in Fig 20.
An external reverse blocking diode D1 is required to block high voltage feeding into the CSH pin
during low-side conduction. By subtracting a forward voltage drop of 0.6V at D1, the minimum
threshold which can be set for the high-side is 0.6V across the drain-to-source.
OVP is provided externally to the IRS2053M. OVP shuts down the amplifier if the bus voltage
between GND and -B exceeds 39V. The threshold is determined by a Zener diode Z3. OVP
protects the board from harmful excessive supply voltages, such as due to bus pumping at very
low frequency-continuous output in stereo mode.
UVP is provided externally to the IRS2053M. UVP prevents unwanted audible noise output from
unstable PWM operation during power up and down. UVP shuts down the amplifier if the bus
voltage between GND and -B falls below a voltage set by Zener diode Z4.
The IRAUDAMP11 requires no output-offset adjustment. DC offsets are tested to be less than ±20
mV.
A Preset Thermostat IC, IC6 in Fig 19, is placed in close proximity to the heatsink which has 6
DirectFETs under it; and monitors heatsink temperature. If the heatsink temperature rises above
100 C, the OTP shuts down all 3 channels by pulling down the CSD pins of the IRS2053M. OTP
recovers once the temperature has cooled down.
The internally-generated housekeeping power supplies include ±5V for analog signal processing,
and +12V supply (VCC) referred to the negative supply rail -B for DirectFET gate drive. The gate
driver section of the IRS2053M uses VCC to drive gates of the DirectFETs. VCC is referenced to –
B (negative power supply). D2, R18 and C10 form a bootstrap floating supply for the HO gate
driver.
Bus Pumping
When the IRAUDAMP11 is running in stereo mode, the bus pumping effect takes place with low
frequency, high output. Since the energy flowing in the Class D switching stage is bi-directional,
there is a period where the Class D amplifier feeds energy back to the power supply. The majority
of the energy flowing back to the supply is from the energy stored in the inductor in the output LPF.
The OVP protects IRAUDAMP11 from failure in case of excessive bus pumping. One of the
easiest counter measures of bus pumping is to drive both of the channels in a stereo configuration
out-of-phase so that one channel consumes the energy flow from the other and does not return it
to the power supply. Bus voltage detection monitors only +B supply, assuming the bus pumping
on the supplies is symmetric in +B and -B supplies.
The IRAUDAMP11 has an RC network called a Zobel network (R21 and C14) to damp the
resonance and prevent peaking frequency response with light loading impedance. (Fig 23)
Gain Setting
The ratio of resistors R4A~C/R1A~C in Fig 24 sets voltage gain. The IRAUDAMP11 has no on board
volume control. To change the voltage gain, change the input resistor term R1A~C. Changing R4A~C
affects PWM control loop design and may result poor audio performance.
22uH
R24A 2.2K
CH3 OUTPUT
2.2K
GND
NC
R14A 4.7R
C16A
0.01uF
C16B
0.01uF
R10
R12
R32A 10R RpA 95C
R22A
10K
C9A
Q5 R32B 10R RpB 95C R20A Q1A
1K
10uF,16V
R12A
IRF6665 N/A
1K
C14A
R32C 10R RpC 95C 22R
R11 8.2K
C13A
C16C
R13
0.01uF
DTA144EKA R4A
100K 1% Q2A
C6A R9A
R7A R5A IRF6665
0.1uF,50V
36
35
34
33
32
31
30
29
28
27
26
25
470K 47K 22R
0.1uF, 63V
0.47uF, 400V
D1A 1N4148
1uF,50V GND
C10A
C19A R19A
0.1uF, 63V
0.47uF, 400V
GND C15A R15A
1R
R29A D3A R6A
VREF
NC
VCC
NC
COM
OTP3
OTP2
OTP1
VS3
HO3
OCSET
DT
10K R17A
C12A 220K 10uF, 16V
C14B
C14C
1N4148 47K C2A 2.2nF,50V C3A 2.2nF,50V 37 10K
DS 24
0.1uF,100V
R1A 22K VB3 R16A
220pF R31A 10K R30A 10K R27A C4A
CH3 INPUT 38
C13B
C13C
C1A 100pF, 50V R2A 120R COMP3 23
10R,1W
10R,1W
1nF,50V CSH3 3.9K
MMBFJ112 Q6
3.3K GND
R21B
R21C
D
R31B R30B R3A 1K 39 L1B
IN3 22 R18A R24B 2.2K
R22C
10K
NC
10K 15K C5A 10uF, 16V
40 D2A 1N4148 4.7R CH2 OUTPUT
G GND 21
LO3 22uH
CN1 C12B IC3 IC1
GND 41
S
0
GND 4 2IN+ 3IN+ VCC2
GND 4 11 VAA R14B CH1 OUTPUT
CH2 3 VDD GND C7 43 18
3 12 R7 10R VAA LO2 22uH
-B
GND 2 1IN+ 4IN+ R3B 5.6K 4.7uF,10V
2 13 4.7R
CH1 1 1IN- 4IN- CH2 INPUT C2B R2B 44 17
1 14 C5B 10uF, 16V 1nF,50V C4B IN2 LO1
1OUT 4OUT Q1B
GND R1B 22K 120R C3B R20B
45 16 IRF6665
TLC084 COMP2 NC R18C
C1B 100pF, 50V 2.2nF,50V D2C
R31C R30C 15K R3C 5.6K
2.2nF,50V
46 15
22R
IN1 CSH1 4.7R
CH1 INPUT R2C C4C 1nF,50V 1N4148
C12C 10K C5C 10uF, 16V C2C
120R 47 14 Q2B
C10 C11 R1C 22K C3C COMP1 VB1 R9B
D1C
220pF R16C IRF6665
4.7uF,10V 4.7uF,10V 2.2nF,50V
0.1uF,50V
C1C 100pF, 50V 2.2nF,50V 48 13 3.9K +B
FAULT
GND CSD HO1 22R
CLIP3
CLIP2
CLIP1
CSH2
GND R17C
C10C
HO2
DCP
R23A C17A
VB2
C17C
VS2
VS1
R15C 10K
NC
NC
R14 R15
R19C
R19B
10K 0.1uF,50V 100k 1000uF,35V
1R
1R
10R 10R
1N4148
R1 R20C Q1C
R22 IRF6665
10
11
12
10R 22R GND
0.1uF,100V
0.1uF,100V
0R0 or N/A
CSD R12B
1N4148
R4C
100K 1% N/A R23B C17B
C19C
C19B
DSA DSB DSC PROT
D3
R9C Q2C C17D 100k 1000uF,35V
10uF, 16V
100uF,4V
C8
R4B IRF6665 0.1uF,50V
D2B -B
R26A 10K
10K
10K
10K
100K 1% R18B 22R
1N4148 R12C
C10B R15B R17B 4.7R N/A
R26B
R26C
R104
10K
R4 0R0 or N/A D4
C9
0.1uF,50V 10K R16B D1B
1N4148
3.9K P3
1N4148
SD VAA
1
R22B 10K
GND 2
GND 3
CH3 OUTPUT 4
3.3k
R41
4 5 P1
120k RTN FB
C61 Q4 C32
D7 +B 3
MMBT5551 2.2uF, 50V
22uF, 16V
Q3
C37
R58 R32 C36 R38 GND 2
R40 LM5007 Z1
47k 1k 0.01uF, 50V 10R -B 1
0.01uF, 50V R55 DS1 100k C33 24V
47k 0.1uF, 50V
OVP UVP
R61 10k
C62
0.01uF, 50V
R62 10k
GND GND
For EMI
4.5 3 3 4.5
16
10.5
1.6 12 14
12
8 27 27 10
Screw Screw
H343-ND H343-ND
Lock washer Thermal Pad Lock washer
Th l d
Screw Screw
H343-ND Stand Off 3 H343-ND Stand Off 2
1893K-ND
Lock washer Lock washer 1893K-ND
Lock washer
Lock washer
Screw Screw
Screw
Stand Off 4 Lock washers Stand Off 1
1893K-ND H729-ND 1893K-ND
Screws
H343-ND
All Gerber files stored in the attached CD-ROM were generated from Protel Altium Designer
Altium Designer 6. Each file name extension means the following:
Additional files for assembly that may not be related with Gerber files:
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
Data and specifications subject to change without notice. 01/29/2009