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    ECIE 3316 Sem 1 EDA Tool Usage Report

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    Darwish M Sukri
    EDA

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    ECIE 3316 Sem 1 EDA Tool Usage Report

    Uploaded by

    Darwish M Sukri
    15 views2 pages
    EDA

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    PDF, TXT or read online from Scribd

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    EDA

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    15 views2 pages

    ECIE 3316 Sem 1 EDA Tool Usage Report

    Uploaded by

    Darwish M Sukri
    EDA

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 2

    ECIE 3316 Semester 1 2022/23 EDA Tool Usage and Verilog Exercise Report

    (To be submitted by 13 January 2023)


    Please write your Matric Number and your name as the name of the submitted
    file. Please also include the names (and matric numbers) of the members in
    your group project.
    As an exercise in a simple design you are required to do the following:
    1. Use the fulladder Verilog program as given in Laboratory exercise 1 and
    write another short Verilog program to implement an 16-bit ripple carry
    adder. Write your own test bench to illustrate that your 16-bit ripple carry
    adder functions correctly. Use the wave program to illustrate sample
    results.
    2. Use the 4-bit carry lookahead adder Verilog program in Laboratory
    exercise 1 and write another short Verilog to implement a two-level 16-bit
    carry lookahead adder as described in the lectures on carry lookahead
    adder. Write your own test bench to illustrate that your 16-bit carry
    lookahead adder functions correctly. Use the wave program to illustrate
    sample results.

    The report shall include the following:

    1. Introduction to Laboratory Exercise 1 with the objective of designing a


    ripple carry adder including also the carry lookahead adder and
    verifying the behavioral and functional performance using Modelsim-
    Altera simulation tool through a test bench.

    2. A brief explanation of your Verilog programs describing the adder circuits


    i.e. a 16-bit ripple carry adder, and a 16-bit carry lookahead adder.
    For this purpose, you are required to compare the operation of the two
    different adders in terms of logic and time delays.
    3. A discussion on the interpretation of the results obtained for each of the
    2 different circuits in the form of illustrations of the waveforms with
    annotated figures as per the description in the laboratory manuals. A
    screenshot copy of the results is considered incomplete without any
    accompanying interpretation and explanation on the meaning of the
    illustration. Marks will only be given for a clear explanation of the
    illustrations.

    4. A statement on the lesson learned in using Quartus as an EDA tool and


    the purpose of designing using Verilog (including features of the Verilog
    language) and the IP Cores and simulating the circuit using Modelsim
    simulator

    5. This report is worth 10% of the overall assessment for the course. Marks
    will be given for concise and clear explanation of the work done.

    Prof Mashkuri Yaacob


    Date: 15 December 2022

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