NuMicro

Flash Memory Controller (FMC)

A Leading MCU Platform Provider

June 2016
Agenda
• Flash Memory Map
• Flash Memory Features
• User Configuration - Config0
• Boot Selection
- In System Programming (ISP) – Bootloader Code Size limited to LDROM(8KB)
- In Application Programming (IAP) - Bootloader Code Size share with APROM
• Functions and Sample Code in BSP
• Sample Code
2
Flash Memory Map-Physical Address

Reserved

0x0030_0004
0x0030_0000
User Configuration
(8B) Config : chip related settings

Reserved

0x0010_1FFF
Loader ROM
(LDROM 8KB)
LDROM : User’s Bootloader
0x0010_0000

Reserved
APROM : Main Application
0x0001_FFFF
Dataflash
Data Flash is shared with APROM
DFBA
128KB

ApplicationROM
(APROM)

0x0000_0000

APROM 128KB

3
APROM & DataFlash

Data Flash : store application parameters.

Data Flash is shared with APROM and size is configurable.
4
Flash Memory Features – (I)
• 128KB application program memory (APROM)
• 8KB loader program memory (LDROM)
• Data Flash with configurable memory size (DataFlash)
• 4 bytes User Configuration (Config 0)
• 512 bytes flash page erase unit
• 32-bit/64-bit and multi-word flash programming function
• Fast flash programming verification function

5
Flash Memory Features – (2)
• CRC-32 Checksum Calculation Function
• Update embedded flash memory
– In-System-Programming (ISP)
– In-Application-Programming (IAP)

6
Config0 – (1)

31 30 29 28 27 26 25 24
CWDTEN CWDTPDEN Reserved CGPFMFP CFOSC
23 22 21 20 19 18 17 16

CBODEN CBOV CBORST Reserved

15 14 13 12 11 10 9 8

Reserved CIOINI Reserved

7 6 5 4 3 2 1 0

CBS Reserved LOCK DFEN

7
Config0 – (2)
• CWDTEN: Watchdog Enable Bit
- 0 = Watchdog Timer Enabled and force Watchdog Timer clock source as OSC10K after chip powered on.
- 1 = Watchdog Timer Disabled after chip powered on.
• CWDTPDEN: Watchdog Clock Power-down Enable Bit
- 0 = OSC10K Watchdog Timer clock source is forced to be always enabled.
- 1 = OSC10K Watchdog Timer clock source is controlled by OSC10K_EN (PWRCON[3]) when chip enters
Power-down. Note: This bit only works at CWDTEN is set to 0
• CGPFMFP: GPF Multi-function Selection
- 0 = XT1_IN and XT1_OUT pin is configured as GPIO function.
- 1 = XT1_IN and XT1_OUT pin is used as external 4~24MHz crystal oscillator pin.
Note: XT1_IN, XT1_OUT multi-function can only be changed by CGPFMFP.
• CFOSC: CPU Clock Source Selection after Reset
- 000 = External 4~24 MHz high speed crystal oscillator clock.
- 111 = Internal RC 22.1184 MHz high speed oscillator clock.
- Others = Reserved.
The value of CFOSC will be load to HCLK_S (CLKSEL0[2:0]) in system register after any reset occurs.
8
Config0 – (3)
• CBODEN : Brown-out Detector Enable Bit
- 0 = Brown-out detect Enabled after powered on.
- 1 = Brown-out detect Disabled after powered on.

• CBOV : Brown-out Voltage Selection

- 00 = 2.2V.
- 01 = 2.7V.
- 10 = 3.7V.
- 11 = 4.4V.
CBORST : Brown-out Reset Enable Bit
- 0 = Brown-out reset Enabled after powered on.
- 1 = Brown-out reset Disabled after powered on.

CIOINI : I/O Initial State Select

- 0 = All GPIO default to be input tri-state mode after powered on
9
Config0 – (4)
• CBS : Chip Boot Selection
- 00 = Boot from LDROM with IAP function
- 01 = Boot from LDROM without IAP function
- 10 = Boot from APROM with IAP function
- 11 = Boot from APROM without IAP function
- IAP function means APROM and LDROM can be executed and access by CPU without reset. When IAP
function enabled, APROM base address is 0x0 and LDROM base address is 0x100000.

LOCK : Security Lock

- 0 = Flash data is locked.
- 1 = Flash data is not locked
When flash data is locked, only device ID, CONFIG0 and CONFIG1 can be read by writer and ICP through serial
debug interface. Others data is locked as 0xFFFFFFFF. ISP can read data anywhere regardless of LOCK bit
value.User need to erase whole chip by ICP/Writer tool or erase user configuration by ISP to unlock.
10
Config0 – (5)
• DFEN : Data Flash Enable Bit
- 0 = Data Flash Enabled.
- 1 = Data Flash Disabled.
Note: This bit only for 128 KB APROM Device

11
 In System Programming (ISP)
• The purpose of ISP provides a facility way to update
application and data in APROM.
• ISP program resides in LDROM. User program runs in APROM.
• ISP Master (PC or NuMicro board) control ISP program
through UART/USB/I2C/SPI.

12
ISP Command

13
ISP Control Flow: 32-bit Programming Example
Start

Enable ISPEN FMC_ISPCMD = 0x21

Write FMC_ISPADDR
Write FMC_ISPCMD End of Flash Operation
Write FMC_ISPDAT

Set ISPGO = 1
Check ISPFF = 1?
Add ISB instruction

End of ISP NO
NO Operation
Check ISPGO = 0 ?
?
YES
YES
Stop

32-bit Programming
14
Boot selection without IAP mode (Logical address)

Reserved

Boot from APROM Reserved

without IAP
Boot from LDROM
0x0003_FFFF
(0x0001_FFFF)
Data Flash without IAP
DFBA

ApplicationROM
(APROM)

0x0000_0FFF
Loader ROM
(LDROM)
0x0000_0000

APROM without IAP mode LDROM without IAP mode

15
 In Application Programming (IAP)
• The purpose of IAP function for user to switch the code executing
between APROM and LDROM without a reset.
• User can enable the IAP function by re-booting chip and setting the chip
boot selection bits in CONFIG0 (CBS[1:0]) as 10b or 00b.
• Chip boots from APROM with the IAP function enabled (CBS[1:0] = 10b),
the executable range of code includes all of APROM and LDROM. The
address space of APROM is kept as the original size but the address space
of the 8 KB LDROM is mapped to 0x0010_0000~ 0x0010_1FFF.

16
 In Application Programming (IAP)
• Chip boots from LDROM with the IAP function enabled (CBS[1:0] = 00b),
the executable range of code includes all of LDROM and almost all of
APROM except for its first page. User cannot access the first page of
APROM by CPU because the first page of executable code range becomes
the mirror of the first page of LDROM as set by default. Meanwhile, the
address space of 8 KB LDROM is mapped to 0x0010_0000~0x0010_1FFF.
• When chip boots with the IAP function enabled, any other page within
the executable range of code can be mirrored to the first page of
executable code (0x0000_0000~0x0000_01FF) any time. User can change
the remap address of the first executing page by filling the target remap
address to ISPADR and then go through ISP procedure with the Vector
Page Re-map command. After changing the remap address, user can
check if the change is successful by reading the VECMAP field in the 17
ISPSTA register
In-Application-Program (IAP)
• System memory map
0x0000_0000 to 0x0000_01FF

• 3 kinds of system memory map

Reserved

with IAP mode when chip

booting 0x0010_0FFF

0x0010_0000
Loader ROM
(LDROM 4KB)

- LDROM with IAP

VECMAP = 0x100000

0x0003_FFFF
Reserved

Data Flash

-
(0x0001_FFFF)

APROM with IAP DFBA

• Vector Page Mapping address

ApplicationROM
VECMAP = 0x0xxx00 (APROM)

0x0000_0200
VECMAP (FMC_ISPSTS[20:9]) 0x0000_01FF
System Memory Vector
0x0000_0000

18
Sample Code Path

NUC029xEEBSPv3.00.001

NuMicro NUC029 Series

Document Driver Reference Guide

SampleCode

FMC_IAP

Fmc_ap_main.uvproj
KEIL

19
Functions and Sample Code in BSP
• \SampleCode\StdDriver
- FMC_ExeInSRAM
- FMC_IAP
- FMC_RW

20
Functions and Sample Code in BSP
• fmc.h
- static __INLINE void FMC_Write (uint32_t u32addr, uint32_t u32data)
 Program 32-bit data into specified address of flash
- static __INLINE uint32_t FMC_Read(uint32_t u32Addr)
 Read 32-bit Data from specified address of flash
- static __INLINE int32_t FMC_Erase(uint32_t u32Addr)
 Flash page erase
- static __INLINE void FMC_SetVectorPageAddr(uint32_t u32PageAddr)
 Set vector mapping address

21
Functions and Sample Code in BSP
• fmc.c
- void FMC_Open(void)
 Enable FMC ISP function
- void FMC_SetBootSource(int32_t i32BootSrc)
 Set boot source from LDROM or APROM after next software reset
- void FMC_EnableAPUpdate(void)
 Enable APROM update function

22
Fmc_ap_main
int main() {
/* Unlock protected registers */
SYS_UnlockReg();
……
/* Enable FMC ISP function */
FMC_Open();
/* Enable IAP function */
if(SetIAPBoot() < 0) {
printf("Failed to set IAP boot mode!\n");
goto lexit;
}
/*Boot mode APROM+IAP/
printf(" Boot Mode ............................. ");
u32CBS = (FMC->ISPSTA & FMC_ISPSTA_CBS_Msk) >> FMC_ISPSTA_CBS_Pos;
printf("[%s]\n", acBootMode[u32CBS]);

/* Enable LDROM update function*/

void FMC_EnableLDUpdate(void) 23
Fmc_ap_main
/*IAP code to LDROM - address 0x00100000*/
if(LoadImage((uint32_t)&loaderImage1Base, (uint32_t)&loaderImage1Limit,
FMC_LDROM_BASE, FMC_LDROM_SIZE) != 0)
/* Disable LDROM update function*/
FMC_DisableLDUpdate();
/*Run IAP program in LDROM*/
/* Mask all interrupt before changing VECMAP to avoid wrong interrupt handler fetched */
__set_PRIMASK(1);

/* Set VECMAP to LDROM for booting from LDROM */

FMC_SetVectorPageAddr(FMC_LDROM_BASE);

/* Software reset to boot to LDROM */

NVIC_SystemReset();
}

24
Flash Page Erase Flow – 512 bytes
• The data changes from 0 to 1 (One way)
Start

Enable ISPEN

FMC_ISPCMD = 0x22 Write FMC_ISPADDR

Write FMC_ISPCMD End of Flash Operation

Set ISPGO = 1
Check ISPFF = 1?
Add ISB instruction

End of ISP NO
NO Operation
Check ISPGO = 0 ?
?
YES
YES
Stop 25
Flowchart – FMC R/W
Sample Code Path

NUC029xEEBSPv3.00.001

NuMicro NUC029 Series

Document Driver Reference Guide

SampleCode

FMC_RW

fmc_rw.uvproj
KEIL

28
fmc_rw
int main()
{
uint32_t i, u32Data;
/* Enable FMC ISP function */
FMC_Open();

if(SetDataFlashBase(DATA_FLASH_TEST_BASE) < 0) {
printf("Failed to set Data Flash base address!\n");
goto lexit;
}

/* Read BS */
printf(" Boot Mode ............................. ");
if(FMC_GetBootSource() == 0)
printf("[APROM]\n");
else {
printf("[LDROM]\n");
printf(" WARNING: The driver sample code must execute in AP mode!\n");
goto lexit;
29
}
fmc_rw
/* Read User Configuration */
printf(" User Config 0 ......................... [0x%08x]\n", FMC_Read(FMC_CONFIG_BASE));
printf(" User Config 1 ......................... [0x%08x]\n", FMC_Read(FMC_CONFIG_BASE + 4));
/* Read Data Flash base address */
u32Data = FMC_ReadDataFlashBaseAddr();
printf(" Data Flash Base Address ............... [0x%08x]\n", u32Data);
FMC_EnableAPUpdate();
if(FlashTest(APROM_TEST_BASE, DATA_FLASH_TEST_BASE, TEST_PATTERN) < 0) {
printf("\n\nAPROM test failed!\n");
goto lexit;
}
FMC_DisableAPUpdate();
printf("\n\nData Flash test =>\n");
if(FlashTest(DATA_FLASH_TEST_BASE, DATA_FLASH_TEST_END, TEST_PATTERN) < 0) {
printf("\n\nUHB test failed!\n");
}

30
Thank you!