DLC Unit 1

St.
JOSEPH'S COLLEGE OF ENGINEERING Department of Electrical and Electronics Engineering III - Sem
UNIT - I
Number System:
 A numeral system (or system of numeration) is a writing system for expressing numbers,
that is, a mathematical notation for representing numbers of a given set, using digits or
other symbols in a consistent manner.
 The values of each digit is determined by the digit, the position of the digit in the number
and the base or radix of the number system.
 The number system will be of 4 types.
 Decimal
 Binary
 Octal
 Hexadecimal
Decimal:
 Decimal is said to be Base Ten.
 When we count in Base Ten, we count starting with zero and going to nine in the order.
 It is a human language one.
0, 1, 2, 3, 4, 5, 6, 7, 8, 9
 Each additional digit represents a higher and higher quantity.
 This is applicable for base 10 as well as to other bases.
Binary:
 In a Binary number system, there are only two symbols used to represent numbers: 0 and
1.
 When we count up from zero in binary, we run out of symbols much more frequently.
 It is a circuit language one.
0, 1
Applications:
 The binary system is useful in computer science and electrical engineering.
 Transistors operate from the binary system and transistors are found in practically all
electronic devices.
Octal:
 Octal is Base Eight meaning eight symbols are used to represent all the quantities.
 When we count up one from the 7, we need a new placement to represent what we call 8
since an 8 does not exist in Octal. So after 7 is 10.
 It is a machine language one.
0, 1, 2, 3, 4, 5, 6, 7
Hexadecimal:
 The hexadecimal system is Base Sixteen; this number system uses sixteen symbols to
represent numbers.
 Unlike binary and octal, hexadecimal has six additional symbols that it uses beyond the
conventional ones found in decimal.
 It is a machine language one.
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F
EE8351 - DLC UNIT I - Number Systems and Digital Logic Families 11

St.JOSEPH'S COLLEGE OF ENGINEERING Department of Electrical and Electronics Engineering III - Sem
Decimal (10) Binary (2) Octal (8) Hexadecimal (16)

0 0000 0 0
1 0001 1 1
2 0010 2 2
3 0011 3 3
4 0100 4 4
5 0101 5 5
6 0110 6 6
7 0111 7 7
8 1000 10 8
9 1001 11 9
10 1010 12 A
11 1011 13 B
12 1100 14 C
13 1101 15 D
14 1110 16 E
15 1111 17 F
Convert the following decimal to binary/ Octal/ Hexadecimal.

i). 26710 ii).1476810 iii). 34.4510
i). (267)10
Binary: Octal: Hexadecimal:
(267)10 = (10001011)2(267)10 = (413)8(267)10 = 1011 = (10B) 16

ii). (14768)10
(14768)10 = (1111110000)2(14768)10 = (2760)8(14768)10 = (39B0)16

iii). (34.45)10
3410 =10001023410 = 4283410 = 2216
0.45 x 2 = 0.90 0 (LSB) 0.45 x 8 = 3.6 3 0.45 x 16 = 7.2 7

0.90 x 2 = 1.80 1 0.60 x 8 = 4.8 4 0.2 x 16 = 3.2 3
0.80 x 2 = 1.60 1 0.80 x 8 = 6.4 6 0.2 x 16 = 3.2 3
0.60 x 2 = 1.20 1 0.40 x 8 = 3.2 3
0.20 x 2 = 0.40 0 (MSB) 0.20 x 8 = 1.6 1
(0.45)10 = (0. 01110)2(0.45)10= (0.34631)8(0.45)10= (0.733)16

(34.45)10 = (100010.01110)2(34.45)10 = (42.34631)8(34.45)10 = (22.733)16
Convert the Binary number 11100101 to its decimal, octal and hexadecimal equivalent.
Decimal:
1 × 27 + 1 × 26 + 1 × 25 + 0 × 24 + 0 × 23 + 1 × 22 + 0 × 21 + 1 × 20
= 128+ 64 + 32 + 0 + 0 + 4 + 0 + 1
= [229]10
Octal: 011 100 101
3 4 5 = [345]8
Hexadecimal: 1110 0101
E 5 = [E5]16
Convert the Octal number 2436 to its decimal, binary and hexadecimal equivalent.
Decimal:2 × 83 + 4 × 82 + 3 × 81 + 6 × 80
= 1024 + 256 + 24 + 6
= [1310]10
Binary: 2 4 3 6
010 100 011 110
= [10100011110]2
Hexadecimal: 2 4 3 6
010 100 011 110
= 0101 0001 1110
5 1 E = [51E] 16

Convert the hexadecimal number 28D to its decimal, binary and octal equivalent.
Decimal: 2 8 D
= 2 8 13
= 2 × 162 + 8 × 161 + 13 × 160
= 512 + 128+ 13
= [653]10
Binary: 2 8 D
= 2 8 13
= 0010 1000 1101
= [1010001101]2
Octal: 2 8 D
= 2 8 13
= 0010 1000 1101
= 001 010 001 101
1 2 1 5
= [1215]8
Convert FACE into its binary, octal and decimal equivalent.[May’17]

(i) Hexadecimal to binary:
FACE16 = F A C E
15 10 12 14
1111 1010 1100 1110
= (1111101011001110)2
(ii) Hexadecimal to octal:

FACE16 = F A C E
15 10 12 14
1111 1010 1100 1110
001 111 101 011 001 110
1 7 5 3 1 6
= 17 5 3168
(iii) Hexadecimal to decimal

FACE16 = F A C E
15 10 12 14
1111 1010 1100 1110
= 11111010110011102
=
1x215+1x214+1x213+1x212+1x211+0x210+1x29+0x28+1x27+1x26+0x25+0x24+1x23
+1x22+1x21+0x20
= 6420610

Convert 23.625 to octal (base 8). [Nov’16]
2310 = 278
0.625 x 8 = 5.0 5 (LSB)

5.0 x 8 = 40.0 40 (MSB)
(0.625)10= (0.540)8
(23.625)10 = (27.540)8
Convert 1010111011101100 into its octal, decimal and hexadecimal equivalent. [Apr’16]
(i) Binary to octal:
1 010 111 011 101 1002
001 010 111 011 101 100
1 2 7 3 5 4
=1273548
(ii) Binary to decimal:

10101110111011002
= 1x215 + 0x214 + 1x213 + 0x212 + 1x211 + 1x210 + 1x29 + 0x28 + 1x27 + 1x26 + 1x25 + 0x24 +
1x23+1x22+0x21+0x20
= 4478010
(iii)Binary to hexadecimal:
1010 1110 1110 1100
1010 1110 1110 1100
10 14 14 12
A E E C = AEEC16
Perform the following addition using BCD and Excess-3 addition (205+569)[Apr’15]
BCD:
205 - 0 0 1 0 0 0 0 0 0 1 0 1
569 - 0 1 0 1 0 1 1 0 1 0 0 1
0111 0110 1110
+ 0110
0111 0111 0100
(205+569)= (0 1 1 1 0 1 1 1 0 1 0 0)2
Excess-3:
205 - 0010 0000 0101
0011 0011 0011
Excess-3 of 205 - 0 1 0 1 0 0 1 1 1 0 0 0
569 - 0101 0110 1001

0011 0011 0011
Excess-3 of 569 - 1 0 0 0 1 0 0 1 1 1 0 0

Excess-3 addition:
0101 0011 1000
1000 1001 1100
1101 1101 0100
- 0 0 1 1 - 0 0 1 1 +0 0 1 1
1010 1010 0111
(205+569) = (1 0 1 0 1 0 1 0 0 1 1 1)2
Perform the following operation (756) – (437) 8 + (725) 16. Express the answer in octal
form.[Nov’15]
(756)8 - 1 1 1 101 110
(437)8 - 100 011 111
(725) 16 - 0 1 1 1 0010 0101
Since (437) 8 is in negative, taking 2’s complement,
(437)8 - 100 011 111
011 100 0 01
Adding: (756)8 - 111 101 110

011 100 001
1011 001 111
Converting octal value to hexa value:
10 1100 1111
Adding: 10 1100 1111
(725) 16 - 0111 0010 0101
1001 1111 0100
Hexadecimal to Octal conversion:
100 111 110 100
4 7 6 4
(756)8 – (437) 8 + (725) 16 = (4764) 8
Given the two binary numbers X=1010100 and Y= 1000011, perform the subtraction Y-X by
using 2’s complements.
a) X = 1010100
2's complement of Y = + 0111101
Sum = 10010001
Discard end carry
X -Y = 0010001

b) Y = 1000011
2's complement of X = + 0101100
Sum = 1101111
There is no end carry,
Therefore the answer is Y-X = - (2's complement of 1101111)
= -0010001
Classification of binary code
Weighted codes:
 In weighted codes, each digit is assigned a specific weight according to its position.
 For example, in 8421 BCD code, 1001 the weights of 1, 0, 0, 1 (from left to right) are 8, 4,
2 and 1 respectively.
 Suppose W1 W2 W3 and W4 are the weights of binary digits and Xl X2 X3 and X4 are the
corresponding digit values then decimal digit.
 N = W1 Xl + W2 X2 + W3 X3 + W4 X4 is represented by binary sequence X4 X3 X2 X4.
 The codes 8421 BCD, 2421 BCD, 5211 BCD are all weighted codes.
Non-weighted codes:
 The non-weighted codes are not positional weighted.
 In other words, each digit position within the number is not assigned a fixed value (or
weight).
 Excess-3 and gray code are non-weighted codes.
Reflective codes:
 A code is reflective when the code is self-complementing.
 In other words, when the code for 9 is the complement of 0, 8 for 1, 7 for 2, 6 for 3 and 5 for
4.
 2421BCD, 5421BCD and Excess-3 code are reflective codes.

Sequential codes:
 In sequential codes, each succeeding code is one binary number greater than its preceding
code.
 This property helps in manipulation of data.
 8421 BCD and Excess-3 are sequential codes.
Alphanumeric codes:
 Codes used to represent numbers, alphabetic characters, symbols and various instructions
necessary for conveying intelligible information.
 ASCII, EBCDIC, UNICODE are the most-commonly used alphanumeric codes.
Error detecting and correcting codes:

 Codes which allow error detection and correction are called error detecting and correcting
codes.
 Hamming code is the mostly commonly used error detecting and correcting code.
Error detection and Error correction:

 Error detection is the ability to detect errors.
 Error correction has an additional feature that enables identification and correction of the
errors.
 Error detection always precedes error correction. Both can be achieved by having
extra/redundant/check bits in addition to data deduce that there is anerror.
Binary
Decimal Excess - 3 Gray Code
8421
0 0000 0011 0000
1 0001 0100 0001
2 0010 0101 0011
3 0011 0110 0010
4 0100 0111 0110
5 0101 1000 0111
6 0110 1001 1010
7 0111 1010 0100
8 1000 1011 1100
9 1001 1100 1101
10 1010 1101 1111
11 1011 1110
12 1100 1111
13 1101
14 1110
15 1111

Binary
Decimal BCD 2421 3321 8 4 -2 -1 5421
8421
0 0000 0000 0000 0000 0000 0000
1 0001 0001 0001 0001 0111 0001
2 0010 0010 0010 0010 0110 0010
3 0011 0011 0011 0100 0101 0011
4 0100 0100 0100 0101 0100 0100
5 0101 0101 1011 0110 1011 1000
6 0110 0110 1100 0111 1010 1001
7 0111 0111 1101 1101 1001 1010
8 1000 1000 1110 1110 1000 1011
9 1001 1001 1111 1111 1111 1100
10 1010 0 0 0 10 0 0 0
11 1011 0001 0001
12 1100 0001 0010
13 1101 0001 0011
14 1110 00010100
15 1111 00010101
Hamming code:
 Hamming code is a code to detect error and also to correct it.

 It detects a single bit error and also identifies the bit that is in error.
 This code uses a number of parity bits located at certain positions in the code group.
 Let us consider an example for Hamming Code, Determine which bit, is in error in the odd
parity, Hamming coded information 00110102 and decode the correct message.
Step1: Construct the bit location table

Bit destination D7 D6 D5 P4 D3 P2 P1
Bit location 7 6 5 4 3 2 1
Bit location number 111 110 101 100 011 010 001
Received Code 0 0 1 1 0 1 0
Step 2: Check for parity bits

For P1: P1 checks locations 1, 3, 5 and 7
There is only one in the group
Hence Parity check for odd parity is correct……………………….0 (LSB)
Hence Parity check for odd parity is correct……………………….0
There are two 1s in the group
Hence Parity check for odd parity is wrong ……………………….1 (MSB)
 The resultant word is C = 1 0 0. This says that the bit in the number 4 location is in error.
 It is 1 and should be 0. Therefore, the correct code is 0 0 1 0 0 1 02

Advantages:
 By using Hamming code we can detect and correct the errors in the information in single
or double bit information.
 But in parity codes, it can only use to detect the error in the information.
Determine which bit, if any, is in error in the even parity, Hamming coded information
11001112. Decode the correct message.

There are three 1’s in the group
Hence Parity check for even parity is wrong……………………….1 (LSB)
There are four 1s in the group
Hence Parity check for even parity is correct……………………….0
Hence Parity check for even parity is correct……………………….0 (MSB)
 The resultant word is C =0 0 1. This says that the bit in the number 1 location is in error.
 It is 1 and should be 0. Therefore, the correct code is 1 1 0 0 1 1 02 and the message is
1 1 0 12
Assume that the even parity Hamming code in example (0 1 1 0 0 1 1) is transmitted and
that (0 1 0 0 0 1 1)2 is received. The receiver does not know what was transmitted. Determine
bit location where error has occurred using received code.
Hence Parity check for even parity is wrong……………………….1 (LSB)
Hence Parity check for even parity is correct……………………….0


Hence Parity check for even parity is wrong ……………………….1 (MSB)
 The resultant word is C = 1 0 1. This says that the bit in the number 5 location is in error.
 It is 0 and should a 1. Therefore, the correct code is (0 1 1 0 0 1 1)2, which agrees with the
transmitted code.
Given that a frame with bit sequence 1101011011 is transmitted, it has been received as
11010110102. Determine the method of detecting the error using any one error detecting
code. [Nov’14]
Bit destination D10 D9 P8 D7 D6 D5 P4 D3 P2 P1
Bit location 10 9 8 7 6 5 4 3 2 1
Bit location number 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001
Received Code 1 1 0 1 0 1 1 0 1 0
For P1: P1 checks locations 1, 3, 5, 7 and 9
There arethree ones in the group
For P8: P8 checks locations 8, 9 and 10
There aretwo ones in the group
Hence Parity check for odd parity is wrong……………………….1 (MSB)
 The resultant word is C = 1 0 0 0. This says that the bit in the number 8 location is in error.
 It is 0 and should be 1. Therefore, the correct code is (1111011010)2, which agrees with the
transmitted code.
The Hamming code 1 0 1 1 0 1 1 0 1 is received. Correct it if any errors. There are four parity
bits and odd parity is used.
Bit destination D9 p8 D7 D6 D5 P4 D3 P2 P1
Bit location 9 8 7 6 5 4 3 2 1
Bit location number 1001 1000 0111 0110 0101 0100 0011 0010 0001
Received Code 1 0 1 1 0 1 1 0 1
Hence Parity check for odd parity is wrong……………………….1 (LSB)


There are three 1s in the group
Hence Parity check for odd parity is correct ………………………0
For P8: P8 checks locations 8 and 9
Hence Parity check for odd parity is correct ……………………….0 (MSB)
 The resultant word is C = 0 0 0 1. This says that the bit in the number 1 location is in error.
 It is 1 and should a 0. Therefore, the correct code is 1011011002.
A 12-bit Hamming code word containing 8 bits of data and 4 parity bits is read from memory.
What was the original 8-bit data word that was written into memory if the 12-bit word read
out is as (1) 101110010100 and (2) 111111110100? [Nov’15]
(1) 101110010100 (using Even parity)
Bit
destination
D12 D11 D10 D9 P8 D7 D6 D5 P4 D3 P2 P1
Bit location 12 11 10 9 8 7 6 5 4 3 2 1
Bit location 110 100 010
number
1011 1010 1000 0111 0110 0101 0011 0010 0001
0 1 0
Received
Code
1 0 1 1 1 0 0 1 0 1 0 0
For P1: P1 checks locations 1, 3, 5, 7, 9, 11
Hence Parity check for even parity is wrong…………………….….….1 (LSB)
Hence Parity check for even parity is correct…………………….…….0
For P4: P4 checks locations 4, 5, 6, 7, 12
Hence Parity check for even parity is correct…….…………………….0
There are four 1sin the group
Hence Parity check for even parity is correct …………...……….…….0 (MSB)
Check bits: C = 1 0 0 0, i.e. Erroris in bit 8= 1011000101002
Actual 8 bit data stored in memory is 101100112
(2) 111111110100 (using odd parity)


Bit
destinatio D12 D11 D10 D9 P8 D7 D6 D5 P4 D3 P2 P1
n
Bit
location
12 11 10 9 8 7 6 5 4 3 2 1
Bit
location 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001
number
Received
Code
1 1 1 1 1 1 1 1 0 1 0 0
There are five 1s in the group
Hence Parity check for odd parity is correct ……………………….0
Hence Parity check for odd parity is wrong…….………………….1
Hence Parity check for odd parity is correct………….…………….0 (MSB)
 Check bits: C = 0100, i.e. Error is in bit 4 = 1111111111002
 Actual 8 bit data stored in memory is 111111112
The message below has been coded in the even parity Hamming code and transmitted
through a noisy channel. Decode the message that at most a single error has occurred in each
word code. i). 1001001 ii) 0111001 iii) 1110110 iv) 00110011
Bit destination D7 D6 D5 P4 D3 P2 P1 Error code
Hamming coded message 1 0 0 1 0 0 1
1, 3, 5 and 7 check for P1 1 0 0 1 0
2, 3, 6 and 7 check for P2 1 0 0 0 1
4, 5, 6 and 7 check for P4 1 0 0 1 0
Error in bit position 2. Therefore, hamming code should be 10010112 and message is 10002.
ii)
Error
code
1, 3, 5 and 7 check for P1 0 1 0 1 0
2, 3, 6 and 7 check for P2 0 1 0 0 1
4, 5, 6 and 7 check for P4 0 1 1 1 1

iii)
Error
code
1, 3, 5 and 7 check for P1 1 1 1 0 1
2, 3, 6 and 7 check for P2 1 1 1 1 0
4, 5, 6 and 7 check for P4 1 1 1 0 1
iv)
Error
code
1, 3, 5 and 7 check for P1 0 1 0 1 0
2, 3, 6 and 7 check for P2 0 0 0 1 1
4, 5, 6 and 7 check for P4 0 0 1 1 1 0
Encode the information character 01101110101 according to the 15-bit hamming code.
 In this the message bits are 11 and parity bits are 4.
 We know that the parity bits are located in the positions that are numbered corresponding
to ascending powers of two (1, 2, 4, 8…).
 Therefore, we have following, format for 15-bit hamming code. We also know that parity
bits are assigned by checking message bits having 1 in the same location as parity bit in
their binary location numbers.
Bit
D12 D11 D10 D9 P8 D7 D6 D5 P4 D3 P2 P1
destination D15 D14 D13
Bit location 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Bit location 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001
number
Information
0 1 1 0 1 1 1 0 1 0 1
bits
Check for
P1: 3, 5, 7, 0 1 0
1 1 0 0 1 0
9, 11, 13,
15
Check for
P2: 3, 6, 7, 0 1
1 1 0 1 1 1
10, 11, 14,
15

Check for
P4: 5, 6, 7, 0 1 1
0 0 1 0 1
12, 13, 14,
15
Check for
P8: 9, 10, 0 1 1
0 1 1 1 1
11, 12, 13,
14, 15
Hamming
coded 0 1 1 0 1 1 1 1 0 1 0 1 1 1 0
message
The 15 – bit hamming code is 0110111101011102
Encode the binary word 1011 into seven bit even parity Hamming code.[Apr’15]
Information Bit 1 0 1 1
3, 5 and 7 check for P1 1 1 1 1
3, 6 and 7 check for P2 1 0 1
0
4, 5, 6 and 7 check for P4 1 0 1 0
Thus the encoded seven bit parity Hamming code is 10101012
Explain in detail the usage of Hamming codes for error detection and error correction with
an example considering the data bits as 0101.
Let us assume a odd parity
3, 5 and 7 check for P1 0 0 1 0
1
4, 5, 6 and 7 check for P4 0 1 0 0
The 7 – bit hamming code is 01001102
Deduce the odd parity hamming code for the data: 10102. Introduce an error in the LSB of
the hamming code and deduce the steps to detect the error. [Apr’16] [OR] Design a odd
parity hamming code generator and detector for 4 bit data and explain their logic.

3, 5 and 7 check for P1 1 1 0 1

0
4, 5, 6 and 7 check for P4 1 0 1 1
Digital logic families.

A digital logic family is a group of compatible devices with the same logic levels and
supply voltages. According to components used in the logic family, digital logic families are
classified as shown in the figure.
Of the above the most widely used Logic families are TTL, CMOS and ECL, due to their
characteristics matching the hardware requirements.
Transistor Transistor Logic (TTL)
 Transistor Transistor logic, TTL, is named for its dependence on transistor alone to basic
operations.
 The first version, which is now known as standard TTL, was developed in 1965 and is rarely
used in today’s system.
 Through the years, the basic design has been modified to improve its performance in several
aspects and as a consequence, a number of subfamilies have evolved.
CMOS Logic:
Digital circuit with MOSFETs can be grouped into three categories:
 PMOS - Uses only P-channel enhancement MOSFETs,
 NMOS - Uses only N-channel enhancement MOSFETs, and
 CMOS (Complementary MOS) – Uses both P and N-channel devices.
 PMOS and NMOS digital ICs are economical than CMOS ICs because they have greater
packing density than CMOS.
 NMOS has twice the packing density than PMOS.

NMOS can operate at about three times faster than their PMOS counterparts. This is because
NMOS has faster moving current carriers (holes).
 CMOS has the greatest complexity and lowest packaging density
 CMOS has advantages of high speed and much lower dissipation.
 NMOS and CMOS are widely used in the digital ICs, but PMOS are no longer part of new
designs.
 CMOS circuit contains both NMOS and PMOS devices to speed the switching of capacitive
loads. It consumes low power and can operate at high voltages, resulting in improved noise
immunity.
ECL Family
 The TTL family uses transistors operating in the saturation mode.
 As a result, their switching speed is limited by the storage delay time associated with transistor
that is driven into saturation.
 Another logic family has been developed that prevents transistor saturation, thereby increasing
overall switching speed by using radically different circuit structure, called current mode logic
(CML).
 This logic family is also called emitter-coupled logic (ECL).
 Unlike TTL and CMOS families, ECL does not produce a large voltage swing between the
LOW and HIGH levels.
 It has a small voltage swing, less than a volt, and it internally switches current between two
possible paths, depending on the output state
Working of RTL logic families.

 In this logic family of ICs, the series of resistors are added to each transistor.
 By reducing the current – hogging effect with resistors, a larger fan-out is achieved.
 But due to the resistor’s presence, the speed of the circuit will be always slow.
Fig. RTL NOR gate circuit
RTL working:
 When inputs A, B are ‘0’, the transistors Q1 and Q2 are OFF. Thus the node C is not
connected to ground and the Vcc will appear at node C s output which is logic ‘1’.
 When any one inputs either A or B is ‘1’ or if both A and B are ‘1’ Q1 or Q2 or both the
transistors will be in saturated mode. Thus the node C will be connected to ground making
the output C as 0V or Logic LOW for all the remaining three conditions.

 If more number of resistors are included in the logic circuit, then the input resistance gets
increased and switching speed will decrease. An alternate approach to increase the
switching speed in RTL is to add a capacitor parallel to the resistor in the input of the
transistor’s base.
 Another problem is the transistors go to saturation causing longer turn off delay (i.e.,) it
takes more time for the output to become 1 to 0. Integrated Injection Logic (IIL) can
eliminate all the problems of the RTL circuit.
Characteristics of RTL logic circuit:

1. Speed of operation is low. The propagation delay is in the order of 500ns. It cannot operate
at speeds above 4MHz.
2. Fan out is 4 or 5 with a switching delay of 50ns and fan in is 4.
3. Poor noise immunity.
4. High average power dissipation due to resistors.
5. The noise margin from zero to the threshold voltage is about 0.5V and from one to the
threshold voltage is 0.2V.
6. Sensitive to temperature.
The RTL family of ICs includes NOR gates, flip flops and 4 bit shift registers.
Explain the working of DTL logic families.

 The formation of NOT gate using Diode Logic is difficult and requires two voltage levels
to represent logic HIGH and LOW. To avoid this, transistor inverter is combined with diodes
to form NAND and NOR gates.
 The DTL circuit combines the diode AND gate and the bipolar transistor inverter into a
NAND gate. The AND function is performed by two diodes with a resistor for pull up and
NOT function is formed by the transistor inverter circuit.
 When A=0, B=0, the node X has 0V. This 0V is given as an input to the transistor Q1. The
transistor will be in cut off condition only. Node C will have +5V (HIGH).
 Similarly if any one input is 0, A=0, B=0 or both A and B are 0, then the node X will be
grounded. Thus there is no base current. The transistor will be in cut off condition. Therefore
the node C will have +5V (HIGH).
 But for the inputs A=1, B=1, A and B are give +5V. Now the node X will have +5V (since
both diodes do not conduct). This voltage is given to the transistor’s base with a drop by R2.
 Now the transistor conducts. The output of the NAND gate is LOW. The node C is grounded.
In this way we can generate NOR using DTL circuits.

Transistor -Transistor Logic (TTL):

 Transistor Transistor logic, TTL, is named for its dependence on transistor alone to
basic operations.
 The first version, which is now known as standard TTL, was developed in 1965 and is
rarely used in today’s system.
 The subfamily circuits along with their characteristics of TTL are discussed below.
They are
 TTL inverter
 TTL 2-input NAND gate
 TTL 3-input NAND gate
 Totem-pole output
 Open collector output
TTL Inverter
 We have seen that when the input voltage is low, the output voltage is HIGH and vice
versa.
 Therefore, we can make a logic inverter from an NPN transistor in the common emitter
configuration.
 The operation of transistor inverter for both the input (HIGH and LOW) using switching
analogy is shown below.
2-Input TTL NAND Gates

 The circuit diagram of 2-input TTL NAND Gate is as shown in figure.
 Its input structure consists of multiple-emitter transistor and output structure consists of
totem-pole output.
 Here, Q1 is an NPN transistor having two emitters, one for each input to the gate.
 Although this circuits looks complex, we can simplify its analysis by using the diode
equivalent of the multiple-emitter transistor Q1.

2-input TTL NAND gate Diode equivalent for Q1
 The diodes D2 and D3 represents the two E-B junction of Q1 and D4 is the collector-base(C-
B) junction.
 The input voltages A and B are either LOW (ideally grounded) or HIGH (ideally +5 volts).
 If either A and B or both are low, the corresponding diode conducts and the base of Q1 is
pulled to approximately 0.7V. This reduces the base voltage of Q2 to atmost zero. Therefore,
Q2 cuts off. With Q2 open, Q4 goes into cut-off and the Q3 Base is pulled HIGH. Since Q3
acts as an emitter follower, the Y output is pulled up to a HIGH voltage.
 On the other hand, when A and B both are HIGH, the emitter diode of Q1 is reverse biased
making them off. This causes the collector diode D4 to get in to forward conduction. This
forces Q2 base to go HIGH. In turn, Q4 goes into saturation, producing a low output in all
input and output conditions.
 Without diode D1 in the circuit, Q3 will conduct slightly when the output is low.
 To prevent this, the diode is inserted. Its voltage drops keeps the base-emitter diode of Q3
reverse biased.
 In this way, only Q4 conducts when the output is low.
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
Truth table for 2-input NAND gate
3-Input TTL NAND Gate:
 The three inputs TTL NAND Gate is same as that of two input TTL NAND Gate except
that its Q1 (NPN) transistor has three emitters instead of two. Rest of the circuit is same.
 For three input NAND gate if all the inputs are logic 1 then only output is logic 0; otherwise
output is logic 1. The operation is similar to the 2-input NAND gate.

A B C Y
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
Three input TTL NAND gate Truth table of 3 input NAND gate
Two input TTL NAND gate with totem-pole ouput:
 In the TTL circuit, transistors Q3 and Q4 form a totem-pole. Such a configuration is known
as active pull-up or totem pole output.
 The active pull-up formed by Q3 and Q4 has a specific advantage. Totem-pole transistors are
used because they produce LOW output impedance.
 Either Q3 acts an emitter follower (HIGH output) or Q4 is saturated (LOW output).
 When Q3 is conducting, the output impedance is approximately 70Ω. When Q4 is saturated,
the output impedance is only 12Ω. Either way, the output impedance is low.
 This means that the output voltage can change quickly from one state to another because
any stray output capacitance is rapidly charged or discharged through the low output
impedance.
 Thus the propagation delay is low in totem-pole TTL logic.
TTL with open collector output configuration.

 One problem with totem-pole output is that two outputs cannot be tied together, as shown in
below figure, where the totem pole outputs of two separate gates are connected together at
point X.

 Suppose that the output of gate A is high (Q3A ON and OFF) and the output of gate B is
LOW (Q3B OFF and Q4B ON). In this situation transistor Q4B act as a load for Q3A.
 Since Q4B is a low resistance load, it draws high current around 55mA.
 This current might not damage Q3A or Q4B immediately, but over a period of time can cause
overheating and deterioration in performance and eventually device failure.
 Some TTL devices provide another type of output called open collector output.
 The output of two different gates with open collector output can be tied together.
 This is known as wired logic.
 A 2-input NAND gate with an open-collector output eliminates the pull-up transistor Q3,
D1 and R4.
 The output is taken from the open collector terminal of transistor Q4.
 Totem pole o/p tied together can produce harmful current.
 Because the collector of Q4 is open, a gate like this will not work properly until you connect
an pull-up resistor.
 When Q4 is OFF output is tied to Vcc through an external pull up resistor.

 As mentioned earlier, the open collector output of two or more gates can be connected
together, as connection is called a wired-AND and represented schematically by the special
AND gate symbol.
Compare the Totem pole and open collector outputs. [Apr’15][May’17]

Sl.No. Totem Pole Open Collector
Output stage consists of pull up
Output stage consists of only pull down
1. transistor (Q4), diode resistor and pull
transistor.
down transistor (Q5).
External pull up resistor is not External pull up resistor is not required for
2.
required. proper operation of gate.
Output of two gates cannot be tied Output of two gates can be tied together
3.
together. using Wired AND technique.
4. Operating speed is high. Operating speed is low.
CMOS logic circuit configuration and characteristics
CMOS Logic:
Digital circuit with MOSFETs can be grouped into three categories:

 PMOS - Uses only P-channel enhancement MOSFETs,
 NMOS - Uses only N-channel enhancement MOSFETs, and
 CMOS (Complementary MOS) – Uses both P and N-channel devices.
 PMOS and NMOS digital ICs are economical than CMOS ICs because they have greater
packing density than CMOS.
 NMOS has twice the packing density than PMOS. Furthermore, NMOS can operate at
about three times faster than their PMOS counterparts.
 This is because NMOS has faster moving current carriers

(holes). CMOS has the greatest complexity and lowest
packaging density.
 However, it has advantages of high speed and much lower

dissipation. NMOS and CMOS are widely used in the digital
ICs, but PMOS are no longer part of new designs.
 CMOS circuit contains both NMOS and PMOS devices to

speed the switching of capacitive loads. It consumes low
power and can operate at high voltages, resulting in improved
noise immunity.

CMOS Inverter:
 It consists of two MOSFET’s in series in such a way that the p-channel device has its source
connected to +VDD and the n-channel device has its source connected to ground.
 The gates of the two devices are connected together as the common input and the drains
are connected together as the common output.
1. When input is HIGH, the gate of Q1 (p=channel) is at 0 V relative to the source of Q1 i.e. Vgs1 = 0
V. Thus Q1 is OFF. On the other hand, the gate of Q2 (n-channel) as at +VDD relative to its source
i.e. Vgs2 = +VDD. Thus, Q2 is ON. This will produce VOUT = 0 V as in figure.
2. When input is LOW, the gate of Q1 (p=channel) is at negative potential relative to its source while
Q2 has Vgs = 0 V. Thus Q1 is ON and Q2 is OFF. This produces output voltage approximately +VDD
in figure.
Truth Table
A Q1 Q2 Output
0 ON OFF 1
1 OFF ON 0
CMOS NAND Gate :

 It consists of two p-channel MOSFET’s Q1 and Q2, connected in parallel and two n-channel
MOSFET’s Q3 and Q4 connected in series.
1. When both the inputs are low, the gates of both p-channel MOSFET’s are negative with respect to
their source, since the sources are connected to +VDD. Thus Q1 and Q2 are both ON. Since the gate-
to-source voltages of Q3 and Q4 (n-channel MOSFETs) are both 0 V, those MOSFET’s are OFF.
The output is therefore connected to +VDD (HIGH) through Q1 and Q2 and is disconnected from
ground, as shown in fig(b).
2. When A=0 and B=+VDD, Q1 is ON because Vgs1=-VDD and Q4 is ON because Vgs4=+VDD.
MOSFET’s Q2 and Q3 are OFF because their gate-to-source voltages are 0 V. Since Q1 is ON and
Q3 is OFF, the output is connected to +VDD and it is disconnected from ground. Output is HIGH.
3. When A=+VDD and B=0, Q1 is OFF because Vgs1=+VDD and Q4 is OFF because Vgs4=-VDD.
MOSFET’s Q2 and Q3 are ON because their gate-to-source voltage is +VDD. Since Q2 and Q3 are
ON, the output is connected to +VDD and it is disconnected from ground. Output is HIGH.
4. Finally, when both inputs are HIGH, Q1 and Q2 are both OFF and Q3 and Q4 are both ON, therefore
the output is connected to ground and is LOW.
Note:
 P-channel MOSFET is ON when its gate voltage is negative with respect to its source
 N-channel MOSFET is ON when its gate voltage is positive with respect to its source.

A B Q1 Q2 Q3 Q4 Output
0 0 ON ON OFF OFF 1
0 1 ON OFF OFF ON 1
1 0 OFF ON ON OFF 1
1 1 OFF OFF ON ON 0
Truth table for CMOS NAND gate
CMOS NOR Gate:

 Below figure shows 2-input CMOS NOR gate. Here, p-channel MOSFET’s Q1 and Q2 are
connected in series and n-channel MOSFET’s Q3 and Q4 are connected in parallel.
 Like NAND circuit, this circuit can be analyzed by realizing that a LOW at any input turns ON
its corresponding p-channel MOSFET and turns OFF its corresponding n-channel MOSFET,
and vice versa for a HIGH input.

A B Q1 Q2 Q3 Q4 Output
0 0 ON ON OFF OFF 1
0 1 ON OFF OFF ON 0
1 0 OFF ON ON OFF 0
1 1 OFF OFF ON ON 0
Truth table for CMOS NOR gate
Characteristics of CMOS family.

Characteristics of CMOS family:
 Operating Speed: Slower than TTL series. Approximately 25 to 100ns depending on the
subfamily of CMOS. It also depends on the power supply voltage.
 Voltage levels and noise margins: The voltage level for CMOS varies according to their
subfamilies. Noise margin are calculated as follow.
VNH = VOH (MIN) – VIH (MIN)
VNL = VIL (MAX) – VOL (MAX)
 Fan-out: The CMOS inputs have an extremely large resistance

(1012Ω) that draws essentially no current from the signal source. Each
CMOS input, however, typically present a 5 pF load to ground as
shown in the fig. This input capacitance limits the number of CMOS
inputs that one CMOS output can drive.
 The CMOS output has to charge and discharge the parallel

combination of all the input capacitances.

 This charging and discharging time increases as we increase number of loads.

 Typically, each CMOS load increases the driving circuit’s propagation delay by 3ns.
 Thus, fan-out for CMOS depends on the permissible maximum propagation delay.
 Typically, CMOS outputs are limited to a fan-out of 50 for low-frequency operation (<1
MHz).
 Of course, for high-frequency operation the fan-out would have to be less.
One CMOS O/P driving Several CMOS I/P
 Power Dissipation (PD):
The power dissipation of a CMOS IC is very low as long as it is in a d.c condition.
Unfortunately, power dissipation of CMOS IC increases in propagation to the frequency at which
the circuits are switching states. For example, a CMOS NAND gate that has P D=10 nW under d.c
conditions will have PD=0.1 mW at a frequency of 100 kHz and 1 mW at 1 MHz.
When CMOS output switches from LOW to HIGH, a transient charging current has to
be supplied to the load capacitance. Therefore, as the switching frequency increases, the average
current drawn from VDD also increases, resulting increase in power dissipation.
 Propagation Delay:
 The propagation delay in CMOS is the sum of delay due to internal capacitance and due to load
capacitance. The delay due to internal capacitance is called the intrinsic propagation delay.
 The delay due to load capacitance can be approximated as follows.
 Tp(CL)=0.5 RO CL seconds
o Where Tp(CL) is either tpLH or tpHL.
 Ro is the output resistance of the gate and CLis the total load capacitance. The Ro depends on
the supply voltage and it can be approximated as
 Ro=VCC/IOS
o Where IOS is the short circuit output current.
 Unused Inputs: CMOS inputs should never be left disconnected. All CMOS inputs have to be
tied either to a fixed voltage level (0 V or VDD) or to another input. This rule applies even to the
inputs of extra unused logic gates on a chip. An unused CMOS input is susceptible to noise and
static charges that could easily bias both the P and N-channel MOSFETs in the conductive state,
resulting in increased power dissipation and possible overheating.
 Static- charge susceptibility (CMOS Hazards): Every CMOS device is vulnerable to the
building up of electrical charge on its insulated gate. Recall that the relationship between charge
Q and voltage V on a capacitor having capacitance C is
V=Q/C
Since the input capacitance at the gate is usually quite small (a few picofarads), a relatively
small amount of charge can create a large voltage which may be greater than the breakdown
voltage of a MOS gate (typically 100 V).
The primary source of charge is “static” electricity, usually produced by handling and the
plastics and textiles. The CMOS devices are protected against this static charge by on chip
diode-resistor network, as shown in the fig. these diodes are designed to turn ON and limit the
size of the input voltages to well below any damaged value.
 Latch-up: CMOS integrated circuits contain parasitic PNP and NPN transistors: transistors that
exist because of the proximity of P and N materials embedded in the substrate. Their existence
is not intentional but is unavoidable. Because of conducting paths between a pair of such
transistors, a device can be triggered into a heavy conducting mode, known as latch-up. This

heavy conduction mode, results large current flow which can destroy IC. Most CMOS circuits
contain protective measures to prevent latch-up, but it can still occur if the manufactures
specified maximum ratings are exceeded.
Typical network used to protect CMOS from static charges
Basic ECL Circuit:
 The basic inverter/buffer circuit in ECL family consists of two transistor connected in
differential single ended input mode with a common emitter resistance.
 The circuit has two outputs: inverting output (OUT1) and non-inverting output (OUT2). For
this circuit, the input LOW and HIGH voltage levels are defined as 3.6 V and 4.4 V, and it
produces output LOW and HIGH levels as 4.2 V and 5.0 V.
 When VIN is HIGH (4.4V), transistor Q1 is ON, but not saturated and transistor Q2 is OFF.
Thus VOUT2 is pulled to 5.0V (HIGH) through R2 and drop across R1 is 0.8 V so that VOUT1.
 When VIN is LOW (3.6V), transistor Q2 is ON, but not saturated and transistor Q1 is OFF. Thus,
VOUT1 is pulled to 5.0V (HIGH) through R1 and drop across R2 is 0.8 V so that VOUT2 is 4.2 V
(LOW).
ECL OR/NOR Gate

 The 2-input ECL OR/NOR gate and it
logic symbol. There has an additional
transistor in parallel with Q1 as
compared to ECL inverter.
 If any input is HIGH corresponding
transistor is active, and VOUT1 is LOW
(NOR output).At the same time Q3 is
off producing VOUT2 HIGH
(OR output).

Compare the characteristics of TTL, ECL and CMOS logic families.[Apr’10]

S.No: Parameter CMOS TTL ECL
n-channel and p- Bipolar junction Bipolar junction
1 Device used
channel MOSFET transistor transistor
2 VIH(min) 3.5 V 2V -1.2 V
3 VIl(max) 1.5 V 0.8 V -1.4 V
4 VOH(min) 4.95 V 2.7 V -0.9 V
5 VOL(max) 0.005 V 0.4 V -1.7 V
High level noise
6 VNH=1.45 V 0.4 V 0.3 V
margin
Low level noise
7 VNL=1.45 V 0.4 V 0.3 V
margin
More vulnerable to
8 Noise immunity Better than TTL Less than CMOS
noise
9 Propagation delay 70 ns 10 ns 500 ps
10 Switching speed Less than TTL Faster than CMOS Fastest
Power dissipation
11 0.1 mW 10 mW 25 mW
per gate
Speed power
12 0.7 pJ 100 pJ 0.5 pJ
product
13 Fan-out 50 10 25
Power supply
14 3-15 V Fixed 5 V -4.5 to 5.2 V
voltage
Increase with Increase with Constant with
15 Power dissipation
frequency frequency frequency
Portable instrument
Laboratory High speed
16 Application where battery
instruments instruments.
supply is used.

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EE8351 - DLC UNIT I - Number Systems and Digital Logic Families 11

Decimal (10) Binary (2) Octal (8) Hexadecimal (16)

Convert the following decimal to binary/ Octal/ Hexadecimal.

(267)10 = (10001011)2(267)10 = (413)8(267)10 = 1011 = (10B) 16

(14768)10 = (1111110000)2(14768)10 = (2760)8(14768)10 = (39B0)16

EE8351 - DLC UNIT I - Number Systems and Digital Logic Families 12

3410 =10001023410 = 4283410 = 2216

0.45 x 2 = 0.90 0 (LSB) 0.45 x 8 = 3.6 3 0.45 x 16 = 7.2 7

(0.45)10 = (0. 01110)2(0.45)10= (0.34631)8(0.45)10= (0.733)16

Hexadecimal: 1110 0101

010 100 011 110

EE8351 - DLC UNIT I - Number Systems and Digital Logic Families 13

Convert FACE into its binary, octal and decimal equivalent.[May’17]

(ii) Hexadecimal to octal:

(iii) Hexadecimal to decimal

EE8351 - DLC UNIT I - Number Systems and Digital Logic Families 14

Convert 23.625 to octal (base 8). [Nov’16]

0.625 x 8 = 5.0 5 (LSB)

(ii) Binary to decimal:

569 - 0101 0110 1001

EE8351 - DLC UNIT I - Number Systems and Digital Logic Families 15

Adding: (756)8 - 111 101 110

EE8351 - DLC UNIT I - Number Systems and Digital Logic Families 16

Classification of binary code

EE8351 - DLC UNIT I - Number Systems and Digital Logic Families 17

Error detecting and correcting codes:

Error detection and Error correction:

EE8351 - DLC UNIT I - Number Systems and Digital Logic Families 18

 Hamming code is a code to detect error and also to correct it.

Step1: Construct the bit location table

Step 2: Check for parity bits

EE8351 - DLC UNIT I - Number Systems and Digital Logic Families 19

Step 2: Check for parity bits

EE8351 - DLC UNIT I - Number Systems and Digital Logic Families 20

There is only one in the group

EE8351 - DLC UNIT I - Number Systems and Digital Logic Families 21

For P2: P2 checks locations 2, 3, 6 and 7

(1) 101110010100 (using Even parity)

Step1: Construct the bit location table

Check bits: C = 1 0 0 0, i.e. Erroris in bit 8= 1011000101002

Actual 8 bit data stored in memory is 101100112

(2) 111111110100 (using odd parity)

EE8351 - DLC UNIT I - Number Systems and Digital Logic Families 22

EE8351 - DLC UNIT I - Number Systems and Digital Logic Families 23

EE8351 - DLC UNIT I - Number Systems and Digital Logic Families 24

EE8351 - DLC UNIT I - Number Systems and Digital Logic Families 25

3, 5 and 7 check for P1 1 1 0 1

Digital logic families.

EE8351 - DLC UNIT I - Number Systems and Digital Logic Families 26

Working of RTL logic families.

Fig. RTL NOR gate circuit

EE8351 - DLC UNIT I - Number Systems and Digital Logic Families 27

Characteristics of RTL logic circuit:

Explain the working of DTL logic families.

EE8351 - DLC UNIT I - Number Systems and Digital Logic Families 28

Transistor -Transistor Logic (TTL):

2-Input TTL NAND Gates

EE8351 - DLC UNIT I - Number Systems and Digital Logic Families 29