Features

• Fast Read Access Time - 90 ns

• 5-Volt-Only Reprogramming
• Sector Program Operation
Single Cycle Reprogram (Erase and Program)
1024 Sectors (256 bytes/sector)
Internal Address and Data Latches for 256-Bytes
• Internal Program Control and Timer
• Hardware and Software Data Protection
• Two 8 KB Boot Blocks with Lockout 2-Megabit
• Fast Sector Program Cycle Time - 10 ms
• DATA Polling for End of Program Detection
(256K x 8)
• Low Power Dissipation
40 mA Active Current
100 µA CMOS Standby Current 5-volt Only
• Typical Endurance > 10,000 Cycles
• Single 5V ±10% Supply CMOS Flash
• CMOS and TTL Compatible Inputs and Outputs
• Commercial and Industrial Temperature Ranges Memory
Description
The AT29C020 is a 5-volt-only in-system Flash programmable and erasable read only
memory (PEROM). Its 2 megabits of memory is organized as 262,144 bytes. Manu- AT29C020
factured with Atmel’s advanced nonvolatile CMOS technology, the device offers ac-
cess times to 90 ns with power dissipation of just 220 mW over the commercial tem-
perature range. When the device is deselected, the CMOS standby current is less
than 100 µA. Device endurance is such that any sector can typically be written to in
excess of 10,000 times.
(continued)

AT29C020
DIP Top View
Pin Configurations
Pin Name Function
A0 - A17 Addresses
CE Chip Enable
OE Output Enable
WE Write Enable
I/O0 - I/O7 Data Inputs/Outputs
NC No Connect

PLCC Top View

TSOP Top View

Type 1

0291I/G20-I–6/97
Description (Continued)
To allow for simple in-system reprogrammability, the During a reprogram cycle, the address locations and 256-
AT29C020 does not require high input voltages for pro- bytes of data are internally latched, freeing the address
gramming. Five-volt-only commands determine the opera- and data bus for other operations. Following the initiation
tion of the device. Reading data out of the device is similar of a program cycle, the device will automatically erase the
to reading from an EPROM. Reprogramming the sector and then program the latched data using an internal
AT29C020 is performed on a sector basis; 256-bytes of control timer. The end of a program cycle can be detected
data are loaded into the device and then simultaneously by DATA polling of I/O7. Once the end of a program cycle
programmed. has been detected, a new access for a read or program
can begin.
Block Diagram

Device Operation
READ: The AT29C020 is accessed like an EPROM. period will start. A8 to A17 specify the sector address. The
When CE and OE are low and WE is high, the data stored sector address must be valid during each high to low tran-
at the memory location determined by the address pins is sition of WE (or CE). A0 to A7 specify the byte address
asserted on the outputs. The outputs are put in the high within the sector. The bytes may be loaded in any order;
impedance state whenever CE or OE is high. This dual- sequential loading is not required. Once a programming
line control gives designers flexibility in preventing bus operation has been initiated, and for the duration of tWC, a
contention. read operation will effectively be a polling operation.
BYTE LOAD: Byte loads are used to enter the 256- SOFTWARE DATA PROTECTION: A software control-
bytes of a sector to be programmed or the software codes led data protection feature is available on the AT29C020.
for data protection. A byte load is performed by applying a Once the software protection is enabled a software algo-
low pulse on the WE or CE input with CE or WE low (re- rithm must be issued to the device before a program may
spectively) and OE high. The address is latched on the be performed. The software protection feature may be en-
falling edge of CE or WE, whichever occurs last. The data abled or disabled by the user; when shipped from Atmel,
is latched by the first rising edge of CE or WE. the software data protection feature is disabled. To enable
PROGRAM: The device is reprogrammed on a sector the software data protection, a series of three program
basis. If a byte of data within a sector is to be changed, commands to specific addresses with specific data must
data for the entire sector must be loaded into the device. be performed. After the software data protection is en-
Any byte that is not loaded during the programming of its abled the same three program commands must begin
sector will be indeterminate. Once the bytes of a sector each program cycle in order for the programs to occur. All
are loaded into the device, they are simultaneously pro- software program commands must obey the sector pro-
grammed during the internal programming period. After gram timing specifications. Once set, the software data
the first data byte has been loaded into the device, suc- protection feature remains active unless its disable com-
cessive bytes are entered in the same manner. Each new mand is issued. Power transitions will not reset the soft-
byte to be programmed must have its high to low transition ware data protection feature, however the software fea-
on WE (or CE) within 150 µs of the low to high transition of ture will guard against inadvertent program cycles during
WE (or CE) of the preceding byte. If a high to low transition power transitions.
is not detected within 150 µs of the last low to high transi- After setting SDP, any attempt to write to the device with-
tion, the load period will end and the internal programming out the 3-byte command sequence will start the internal
(continued)
2 AT29C020
 AT29C020

Device Operation (Continued)

write timers. No data will be written to the device; however, the program cycle has been completed, true data is valid
for the duration of tWC, a read operation will effectively be on all outputs and the next cycle may begin. DATA polling
a polling operation. may begin at any time during the program cycle.
After the software data protection’s 3-byte command code TOGGLE BIT: I n a d d i t i o n t o DATA p o l l i n g t h e
is given, a sector of data is loaded into the device using the AT29C020 provides another method for determining the
sector program timing specifications. end of a program or erase cycle. During a program or
HARDWARE DATA PROTECTION: Hardware features erase operation, successive attempts to read data from
protect against inadvertent programs to the AT29C020 in the device will result in I/O6 toggling between one and
the following ways: (a) VCC sense— if VCC is below 3.8V zero. Once the program cycle has completed, I/O6 will
(typical), the program function is inhibited. (b) VCC power stop toggling and valid data will be read. Examining the
on delay— once VCC has reached the VCC sense level, toggle bit may begin at any time during a program cycle.
the device will automatically time out 5 ms (typical) before OPTIONAL CHIP ERASE MODE: The entire device
programming. (c) Program inhibit— holding any one of OE can be erased by using a 6-byte software code. Please
low, CE high or WE high inhibits program cycles. (d) Noise see Software Chip Erase application note for details.
filter— pulses of less than 15 ns (typical) on the WE or CE BOOT BLOCK PROGRAMMING LOCKOUT: The
inputs will not initiate a program cycle. AT29C020 has two designated memory blocks that have
PRODUCT IDENTIFICATION: The product identifica- a programming lockout feature. This feature prevents pro-
tion mode identifies the device and manufacturer as At- gramming of data in the designated block once the feature
mel. It may be accessed by hardware or software opera- has been enabled. Each of these blocks consists of 8K
tion. The hardware operation mode can be used by an ex- bytes; the programming lockout feature can be set inde-
ternal programmer to identify the correct programming al- pendently for either block. While the lockout feature does
gorithm for the Atmel product. In addition, users may wish not have to be activated, it can be activated for either or
to use the software product identification mode to identify both blocks.
the part (i.e. using the device code), and have the system These two 8K memory sections are referred to as boot
software use the appropriate sector size for program op- blocks. Secure code which will bring up a system can be
erations. In this manner, the user can have a common contained in a boot block. The AT29C020 blocks are lo-
board design for 256K to 4-megabit densities and, with cated in the first 8K bytes of memory and the last 8K bytes
each density’s sector size in a memory map, have the sys- of memory. The boot block programming lockout feature
tem software apply the appropriate sector size. can therefore support systems that boot from the lower
For details, see Operating Modes (for hardware operation) addresses of memory or the higher addresses. Once the
or Software Product Identification. The manufacturer and programming lockout feature has been activated, the data
device code is the same for both modes. in that block can no longer be erased or programmed;
DATA POLLING: The AT29C020 features DATA poll- data in other memory locations can still be changed
ing to indicate the end of a program cycle. During a pro- through the regular programming methods. To activate the
gram cycle an attempted read of the last byte loaded will lockout feature, a series of seven program commands to
result in the complement of the loaded data on I/O7. Once specific addresses with specific data must be performed.
Please see Boot Block Lockout Feature Enable Algorithm.
Absolute Maximum Ratings* If the boot block lockout feature has been activated on
either block, the chip erase function will be disabled.
Temperature Under Bias................. -55°C to +125°C BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine whether programming of
Storage Temperature...................... -65°C to +150°C
(continued)
All Input Voltages
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
*NOTICE: Stresses beyond those listed under “Absolute Maxi-
All Output Voltages mum Ratings” may cause permanent damage to the device.
with Respect to Ground .............-0.6V to V CC + 0.6V This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indi-
Voltage on OE cated in the operational sections of this specification is not
with Respect to Ground ................... -0.6V to +13.5V implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

3
Device Operation (Continued)
either boot block section is locked out. See Software Prod- FE, the corresponding block can be programmed; if the
uct Identification Entry and Exit sections. When the device data is FF, the program lockout feature has been activated
is in the software product identification mode, a read from and the corresponding block cannot be programmed. The
location 00002H will show if programming the lower ad- software product identification exit mode should be used
dress boot block is locked out while reading location to return to standard operation.
FFFF2H will do so for the upper boot block. If the data is
DC and AC Operating Range
AT29C020-90 AT29C020-10 AT29C020-12 AT29C020-15
Operating Com. 0°C - 70°C 0°C - 70°C 0°C - 70°C 0°C - 70°C
Temperature (Case) Ind. -40°C - 85°C -40°C - 85°C -40°C - 85°C
VCC Power Supply 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10%

Operating Modes
Mode CE OE WE Ai I/O
Read VIL VIL VIH Ai DOUT
Program (2) VIL VIH VIL Ai DIN
5V Chip Erase VIL VIH VIL Ai
Standby/Write Inhibit VIH X (1) X X High Z
Program Inhibit X X VIH
Program Inhibit X VIL X
Output Disable X VIH X High Z
Product Identification
A1 - A17 = VIL, A9 = VH, (3)
A0 = VIL Manufacturer Code (4)
Hardware VIL VIL VIH
A1 - A17 = VIL, A9 = VH,
A0 = VIH Device Code (4)
A0 = VIL Manufacturer Code (4)
Software (5)
A0 = VIH Device Code (4)
Notes: 1. X can be VIL or VIH. 4. Manufacturer Code: 1F, Device Code: DA
2. Refer to AC Programming Waveforms. 5. See details under Software Product Identification Entry/Exit.
3. VH = 12.0V ± 0.5V.
DC Characteristics
Symbol Parameter Condition Min Max Units
ILI Input Load Current VIN = 0V to VCC 10 µA
ILO Output Leakage Current VI/O = 0V to VCC 10 µA
Com. 100 µA
ISB1 VCC Standby Current CMOS CE = VCC - 0.3V to VCC
Ind. 300 µA
ISB2 VCC Standby Current TTL CE = 2.0V to VCC 3 mA
ICC VCC Active Current f = 5 MHz; IOUT = 0 mA 40 mA
VIL Input Low Voltage 0.8 V
VIH Input High Voltage 2.0 V
VOL Output Low Voltage IOL = 2.1 mA .45 V
VOH1 Output High Voltage IOH = -400 µA 2.4 V
VOH2 Output High Voltage CMOS IOH = -100 µA; VCC = 4.5V 4.2 V

4 AT29C020
 AT29C020

AC Read Characteristics
AT29C020-90 AT29C020-10 AT29C020-12 AT29C020-15
Symbol Parameter Min Max Min Max Min Max Min Max Units
tACC Address to Output Delay 0 90 100 120 150 ns
tCE (1) CE to Output Delay 90 100 120 150 ns
tOE (2) OE to Output Delay 0 40 0 50 0 50 0 70 ns
tDF (3, 4) CE or OE to Output Float 0 25 0 25 0 30 0 40 ns
Output Hold from OE, CE or
tOH Address, whichever 0 0 0 0 ns
occurred first

AC Read Waveforms (1, 2, 3, 4)

Notes: 1. CE may be delayed up to tACC - tCE after the address 3. tDF is specified from OE or CE whichever occurs first
transition without impact on tACC . (CL = 5 pF).
2. OE may be delayed up to tCE - tOE after the falling 4. This parameter is characterized and is not 100% tested.
edge of CE without impact on tCE or by tACC - tOE
after an address change without impact on tACC .

Input Test Waveforms and Measurement Level Output Test Load

tR, tF < 5 ns
Note: While CE is active, any address inputs that cause VIH to drop
below 2.0V or VIL to rise above 0.8V for a duration of up to 15 ns
may cause the device to read incorrectly.

Pin Capacitance (f = 1 MHz, T = 25°C) (1)

Typ Max Units Conditions
CIN 4 6 pF VIN = 0V
COUT 8 12 pF VOUT = 0V
Note: 1. This parameter is characterized and is not 100% tested.

5
AC Byte Load Characteristics
Symbol Parameter Min Max Units
tAS, tOES Address, OE Set-up Time 0 ns
tAH Address Hold Time 50 ns
tCS Chip Select Set-up Time 0 ns
tCH Chip Select Hold Time 0 ns
tWP Write Pulse Width (WE or CE) 90 ns
tDS Data Set-up Time 50 ns
tDH, tOEH Data, OE Hold Time 0 ns
tWPH Write Pulse Width High 100 ns

AC Byte Load Waveforms

WE Controlled

CE Controlled

6 AT29C020
 AT29C020

Program Cycle Characteristics

Symbol Parameter Min Max Units
tWC Write Cycle Time 10 ms
tAS Address Set-up Time 0 ns
tAH Address Hold Time 50 ns
tDS Data Set-up Time 50 ns
tDH Data Hold Time 0 ns
tWP Write Pulse Width 90 ns
tBLC Byte Load Cycle Time 150 µs
tWPH Write Pulse Width High 100 ns

Program Cycle Waveforms (1, 2, 3)

Notes: 1. A8 through A17 must specify the sector address 3. All bytes that are not loaded within the sector being
during each high to low transition of WE (or CE). programmed will be indeterminate.
2. OE must be high when WE and CE are both low.

7
Software Data (1) Software Data (1)
Protection Enable Algorithm Protection Disable Algorithm
LOAD DATA AA LOAD DATA AA
TO TO
ADDRESS 5555 ADDRESS 5555

LOAD DATA 55 LOAD DATA 55

TO TO
ADDRESS 2AAA ADDRESS 2AAA

LOAD DATA A0 LOAD DATA 80

TO TO
ADDRESS 5555 WRITES ENABLED ADDRESS 5555

LOAD DATA LOAD DATA AA

TO (4) ENTER DATA TO
SECTOR (256 BYTES) (2) ADDRESS 5555
PROTECT STATE

LOAD DATA 55
Notes for software program code: TO
ADDRESS 2AAA
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
LOAD DATA 20
2. Data Protect state will be activated at end of program cycle. TO
3. Data Protect state will be deactivated at end of program ADDRESS 5555 EXIT DATA
(3)
period. PROTECT STATE
4. 256-bytes of data MUST BE loaded. LOAD DATA
TO (4)
SECTOR (256 BYTES)

Software Protected Program Cycle Waveform (1, 2, 3)

Notes: 1. A8 through A17 must specify the sector address 3. All bytes that are not loaded within the sector being
during each high to low transition of WE (or CE) programmed will be indeterminate.
after the software code has been entered.
2. OE must be high when WE and CE are both low.

8 AT29C020
 AT29C020
(1)
Data Polling Characteristics
Symbol Parameter Min Typ Max Units
tDH Data Hold Time 10 ns
tOEH OE Hold Time 10 ns
tOE OE to Output Delay (2) ns
tWR Write Recovery Time 0 ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.

Data Polling Waveforms

(1)
Toggle Bit Characteristics
Symbol Parameter Min Typ Max Units
tDH Data Hold Time 10 ns
tOEH OE Hold Time 10 ns
tOE OE to Output Delay (2) ns
tOEHP OE High Pulse 150 ns
tWR Write Recovery Time 0 ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.

Toggle Bit Waveforms (1, 2, 3)

Notes: 1. Toggling either OE or CE or both OE and CE will 3. Any address location may be used but the address
operate toggle bit. should not vary.
2. Beginning and ending state of I/O6 will vary.

9
Software Product (1) Boot Block Lockout (1)
Identification Entry Feature Enable Algorithm
LOAD DATA AA LOAD DATA AA
TO TO
ADDRESS 5555 ADDRESS 5555

LOAD DATA 55 LOAD DATA 55

TO TO
ADDRESS 2AAA ADDRESS 2AAA

LOAD DATA 90 LOAD DATA 80

TO TO
ADDRESS 5555 ADDRESS 5555

LOAD DATA AA
PAUSE 10 mS ENTER PRODUCT TO
IDENTIFICATION ADDRESS 5555
MODE (2, 3, 5)
LOAD DATA 55
TO
ADDRESS 2AAA

Software Product (1) LOAD DATA 40

TO
Identification Exit ADDRESS 5555

LOAD DATA AA
TO
ADDRESS 5555 LOAD DATA 00 LOAD DATA FF
TO TO
LOAD DATA 55 ADDRESS 00000H (2) ADDRESS FFFFFH (3)
TO
ADDRESS 2AAA
PAUSE 10 mS PAUSE 10 mS
LOAD DATA F0
TO
ADDRESS 5555
Notes for boot block lockout feature enable:
1. Data Format: I/O7 - I/O0 (Hex);
PAUSE 10 mS EXIT PRODUCT Address Format: A14 - A0 (Hex).
IDENTIFICATION 2. Lockout feature set on lower address boot block.
(4) 3. Lockout feature set on higher address boot block.
MODE

Notes for software product identification:

1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. A1 - A17 = VIL.
Manufacture Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 1F
Device Code: DA

10 AT29C020
 AT29C020

Ordering Information
tACC ICC (mA)
(ns) Ordering Code Package Operation Range
Active Standby
90 40 0.1 AT29C020-90JC 32J Commercial
AT29C020-90PC 32P6 (0° to 70°C)
AT29C020-90TC 32T
100 40 0.1 AT29C020-10JC 32J Commercial
AT29C020-10PC 32P6 (0° to 70°C)
AT29C020-10TC 32T
40 0.3 AT29C020-10JI 32J Industrial
AT29C020-10PI 32P6 (-40° to 85°C)
AT29C020-10TI 32T
120 40 0.1 AT29C020-12JC 32J Commercial
AT29C020-12PC 32P6 (0° to 70°C)
AT29C020-12TC 32T
40 0.3 AT29C020-12JI 32J Industrial
AT29C020-12PI 32P6 (-40° to 85°C)
AT29C020-12TI 32T
150 40 0.1 AT29C020-15JC 32J Commercial
AT29C020-15PC 32P6 (0° to 70°C)
AT29C020-15TC 32T
40 0.3 AT29C020-15JI 32J Industrial
AT29C020-15PI 32P6 (-40° to 85°C)
AT29C020-15TI 32T

Package Type
32J 32 Lead, Plastic J-Leaded Chip Carrier (PLCC)
32P6 32 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
32T 32 Lead, Thin Small Outline Package (TSOP)

11