ACTS, Pune

Suggested Teaching Guidelines for

Evaluation method: CCEE Theory exam– 40% weightage

Courseware:

No specific courseware for modules, faculty may share some course materials.

Reference:
1. System Verilog for Design by Sutherland, Davidmann and Flake / Springer
2. System Verilog for Verification by Chris Spear / Springer
3. Writing Testbenches using System Verilog by Janick Bergeron
4. System Verilog Language Reference Manual 3.1a

Session 1 & 2
Lecture: Introduction to System Verilog
 System Verilog: Origins, Overview, Need and Importance
 System Verilog Declaration Spaces
 Data types
o 4-state and 2-state data type
o String
o Event
o Type casting
o User defined date types (typedef)
o Enumerated data types (enum)
 Data Declaration
 Operators and Expression
Assignment – Lab:
Review Exercises – Handling variables, types, basic operations in System Verilog (SV)

Session 3 & 4
Lecture: Introduction to System Verilog
 Arrays
o Packed and unpacked arrays
o Array initialization at declaration
o Multiple dimensions
o Array Handling
o Dynamic Array
o Associative Array
o Synthesis guidelines
 Overview of Structures

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Suggested Teaching Guidelines for
System Verilog PG-DVLSI September 2022
o Declarations, assigning values to structures
o Types: Packed and unpacked structures
o Passing structures through ports, Passing structures as arguments to tasks and functions
o Synthesis guidelines
 Overview of Unions
o Types: Unpacked unions, Tagged unions, Packed unions
o Synthesis guidelines
 An example of using structures and unions

Assignment – Lab:
Review Exercises – Array declaration, Array Handling exercises

Session 5
Lecture: Procedural Blocks and Statements
 Procedural Statements
o Initial, final and always block
o Loop
 Process
o Combinational
o Latched and sequential
o Continuous assignment
o Fork-join and its variant
 Clocking Domains

Assignment – Lab:
Review Exercises – Using procedural statements in SV coding

Session 6
Lecture: Tasks and Functions
 Introduction to Task and function
 Scope and life time of Task and function
 Argument passing in Task and function
o Pass by value
o Pass by reference
o Default argument value
o Argument passing by name
o Optional argument list

Assignment – Lab:
Review Exercises – Lab assignments of SV coding using tasks and functions

Session 7 & 8
Lecture: Case Studies – Design
 Design of combinational circuit, sequential circuit and Finite State Machine using System
Verilog.
 Case study of Traffic Light Controller / ATM Design / AHB Peripheral using System Verilog

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Suggested Teaching Guidelines for
System Verilog PG-DVLSI September 2022
Session 9
Lecture: Review of OOP Concepts
 OOP terminology
 Data hiding and encapsulation
 Introduction to inheritance
 Introduction to polymorphism
o Compile time polymorphism
o Run time polymorphism
 Introduction to Class
 Objects and properties
 Object methods
 Constructor
 Static Properties and methods
 This
 Assignment and re-naming and copying

Assignment – Lab:
 Review Exercises – OOPs practice codes in C++/SV

Session 10
Lecture: OOP in System Verilog
 Inheritance in System Verilog
 Overridden member
 Constant properties
 Abstract class and virtual methods
 Polymorphism
 Scope resolution operator
 Difference between classes, structures and unions
 Memory management

Assignment – Lab:
Review Exercises – Practice codes for using OOPs in SV.
Note: More lab practice should be taken for this session.

Session 11
Lecture: Introduction to Verification
 The Verification Process
 Importance of Verification
 Types of Verification
o Formal Verification
o Equivalence Checking
o Model Checking
o Functional Verification
 Functional Verification approach
o Black-box
o White –box
o Grey-box
 Comparison between testing and Verification
 Verification reuse
o Costing behind the verification

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Suggested Teaching Guidelines for
System Verilog PG-DVLSI September 2022

Session 12
Lecture: Coverage
 Understanding Coverage
 Methodology
 Code Coverage
o Statement Coverage
o Path Coverage
o Expression Coverage
o FSM Coverage
 Functional Coverage
o Item Coverage
o Cross Coverage
o Transition Coverage
 Case Study

Assignment – Lab:
Review Exercises - some lab assignments which taking care of code coverage

Session 13
Lecture: Randomization - I
 Introduction
 Randomization in real world
 Randomization in System Verilog
 Random variables
 Constraint blocks
o Inside
o Weighted distribution
o ‘dist’
o Array constraints
o Conditional constraints
o Bidirectional constraints
Assignments:
Review Exercises –
 Create a System Verilog program class to prove that variables declared with rand keyword
are standard random variables.
 Create and run a SV project to check status of randomization return value.
 Write SV program in which if an extended object is casted to base object, all the constraints
in extended object are solved along with the constraints in base object.
 Write SV program in array of objects are created before calling randomize.
 Write a SV program to implicit the weighted distribution in constraint expression.

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Suggested Teaching Guidelines for
System Verilog PG-DVLSI September 2022

Session 14
Lecture: Randomization - II
 Controlling multiple randomization
o Solve-before
o Constraint_mode()
o If-else constraining
 Pre and post randomize functions
 Random Number function
 Tips and techniques of handling the randomization
Assignments:
Review Exercises –
 Create a project to add a new process without disturbing the random number generator state.
 Write a SV program on pre_randomize and post_randomize methods that can be used as
hooks for the user to perform operations such as setting initial values and performing
functions after assigning random variables.
 Create a project in which the constraint blocks are defined externally in the same file or other
files.
 Specification: Create a test_1 file which requires Var between 0 to 100 and tets_2 file
requires Var between 50 to 100.
 Declare the constraint block as empty and define them in other files.
 Write a SV program to randomize the class instances using global constraints.
 A simple testbench may use a data class with just a few constraints. Write SV program on
how to have two tests with very different flavors of data.
 Create a project which implies that the constraints can be on or off with Constraint mode.

Session 15 & 16
Lecture: Case Studies – Randomization
 In general, randomization does not depend on life time of variable.
 Even if a variable is static, randomization is specfic to object.
 So rand_mode() on static variable, only switches off the randomization on the variable of that
object.
 Implement it with the following:
o Initialize Var1 as static and Var2 as automatic.
o Var1 and Var2 in obj_2 should be nonrandomized
o Var1 and Var2 in obj_1 are getting randomized.
o Show that the only difference between Var1 and Var2 is that new random value for Var1
is appears on both objects.

Session 17 & 18
Lecture: Case Studies – Verification
 Case studies of Verification Environments in SystemVerilog for combinational designs,
sequential designs and finite state machines

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Suggested Teaching Guidelines for
System Verilog PG-DVLSI September 2022

Session 19
Lecture: Assertions Property
 Definition and concept
 Implication
 Immediate assertions
 Concurrent assertions

Session 20
Lecture: Assertions timing
 Assertion sampling
 Multiple clock support
 Clock resolution

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