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    Microprogrammed Sequencer in CSA

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    Deepak kumar
    The microprogram sequencer determines the next address to present to the control memory to read and execute a micro-instruction. It contains two multiplexers - one selects an address source for the control address register and the other tests a status bit and routes the result to input logic. The input logic circuit contains the address selection logic and determines the type of operations for the specific sequencer. It has three inputs and three outputs that select the source addresses and enable loading of the subroutine register.

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    Microprogrammed Sequencer in CSA

    Uploaded by

    Deepak kumar
    38 views3 pages
    The microprogram sequencer determines the next address to present to the control memory to read and execute a micro-instruction. It contains two multiplexers - one selects an address source for the control address register and the other tests a status bit and routes the result to input logic. The input logic circuit contains the address selection logic and determines the type of operations for the specific sequencer. It has three inputs and three outputs that select the source addresses and enable loading of the subroutine register.

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    Microprogrammed Sequence in Computer system architecture

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    The microprogram sequencer determines the next address to present to the control memory to read and execute a micro-instruction. It contains two multiplexers - one selects an address source for the control address register and the other tests a status bit and routes the result to input logic. The input logic circuit contains the address selection logic and determines the type of operations for the specific sequencer. It has three inputs and three outputs that select the source addresses and enable loading of the subroutine register.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    38 views3 pages

    Microprogrammed Sequencer in CSA

    Uploaded by

    Deepak kumar
    The microprogram sequencer determines the next address to present to the control memory to read and execute a micro-instruction. It contains two multiplexers - one selects an address source for the control address register and the other tests a status bit and routes the result to input logic. The input logic circuit contains the address selection logic and determines the type of operations for the specific sequencer. It has three inputs and three outputs that select the source addresses and enable loading of the subroutine register.

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    Roll No 2001006 Paper Code 11061/NI Page No_ 5 .

    Ans: 2MiGrobrogram Sequen.cer

    he basiG Combonents of a micyogrammed Control unit are fhe


    Control m.emary and the circnit thot Select the next address.
    Iheaddress selecion bart is calleda mitrabrog ram 5equen.cer.
    he burboSe of a. microbrogram Sequenc.e.r is to hresent A.n
    Address fo the Control mem.oru So that a micra-instrochOn_mau-
    beread and execute.
    henext addresslogic at the Sequencer dekermines the Shecipic-
    address Source to be Joaded inta the Control address register
    he block diagram of the microbrogram Seq11encer is as:

    External
    (MAP)

    Io Logic 2 10
    ILTnbu S13
    T S MUXL SBR

    Increment
    MUX2
    CAR
    Select CLK

    Contto Memory
    Micco-opS CD BR AD

    Signature
    Dedoak kumar
    Roll No 2001006 Paper Code 11061/N1 Page No 6,

    The Conhol memory is included in the diagram to Show iheinterac-


    tion between the Sequencerand the memory ata.ched to i
    here are tuo multiblexers in the circuit.
    The first muliblexers (Mux1) Selects an_address from_one af
    four Source.S and routes it into conttol_address_register CAR)
    Lii The Second multHplexer (Mux2) tests Hhe value afa selected
    Status hit and the restult of test is abblied to an Tnhut lagic
    J
    Circuit.
    The outhut from_CAR LContral Address Register brovides the
    Control memory.
    The Content of CAR iS inc.re.mented and abplied to one or ihe
    muliblexer inbuts and to the Suhrauine legister [SRR)-
    The other three inhuts o the_muliblexer comes tram
    The address tield of the þresent miccoinStruction.
    Lii From the out of SBR.
    LGtn From an ExBernal Source that mabs the InStruschion.
    TheCD Cconditio.n)feld at the miom-instruction selects aneat
    fhe status bits in the second multäblexer
    f the bit Select iS equal n i the T yariable iS equal o 1, ather
    -uiSe it 1s equal to 0.
    The T value together Luith tuo bits from the BRCbroanch) fteld
    gnes to the Inbut logic circuif
    The inbut logic ina barkitular Sequencer uwill deter mine the
    type0 operations that are Available_in the unit
    The Tnbut Logio circuit has three_inhufs Inl andI and three
    outtbuts Sn, Si and L
    Variables So_and Si Sel ect one of the Source addresSes for CAR.
    VariableL enables he load inbut in SBR.
    The binary value of the Seleciom Vartables determines the
    hathin the multiblexer.
    Deepak lkumar
    Signature
    Roll No 12.001006 Paper Code iD61/N1 Page No

    he Truth Table for the inbut Logíc Circuit is 9iven heloLu


    BR Inbuts MUX1 Load SBR
    Field I Ia S1 So
    000
    0 O1
    1 0 10
    0 1 O 1 1_ O1 1
    1 0 10X 10
    1 1 1 1 XK 11

    Tnbuts Iand T ate identical to the bit values in theBR Reld


    The bit value.s for Si and Sp are dekermined from the Sifated
    tunction and the bath in the multislexer that establish the
    the
    required Transfer.
    The Subrouine fegister ts loaded uith the Tncremented
    Valve of CAR_cduring a call micro-inshuction LBR=o1) proÍ-
    -ded that the Stratus bit Condilion is satiStied (T=1)._
    K-mab SimbliPication:

    T1IT o 1 ITT o IIT 0


    00 00 0 I
    O0
    11I IL
    01
    O 01 o1
    11 11/1 11(1 1
    O 10 I
    1o
    kmab tor L_ I K-mah tor SA k-mab tor S
    Hence
    S1 I
    S -Ti La tTT
    L= IL.T
    Signature
    Deebak kUmar

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