Birla Institute of Technology and Science, Pilani

II semester 2022-2023
EEE F341/INSTR F341 Analog Electronics
Time: 50 min TUT-1 Date: 02-02-2023

Q1. A voltage amplifier is required to amplify the output signal from a communication receiver
(microphone) that produce a voltage signal of VS=20 mV with an internal resistance of RS=1.5 k. The
load resistance is RL=15 k. The desired output voltage is VO ≥ 10 V. The amplifier must not draw more
than 1 µA from the receiver. The variation in output voltage when the load is disconnected should be less
than 0.5%. Determine the required input resistance, output resistance and actual voltage gain of the voltage
amplifier.

Q2. A amplifier shown below is fed by a transducer providing a voltage of 1 V with internal resistance of
1 M and delivers its output to a load of 200  (RL). The op-amp has open loop gain 80 dB, Ri=20 M,
Ro=75 . Also consider R1=1 k and R2=9 k. Draw an equivalent circuit of the amplifier and find the
following items
(a) Input resistance of the amplifier (Rif)
(b) Output resistance of the amplifier (Rof)
Vo
(c) Source to load voltage gain (Vo/Vs).
VS
(d) Specify the type of feedback.

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Q3. Consider the op-amp have open-loop gain
104 (V/V), Ri=1 M and Ro=100 . Also,
consider the source voltage have 1 k internal resistance (Rs). Draw the equivalent circuit model for the
amplifier and calculate the followings
(a) Closed loop voltage gain (Af)
(b) Input resistance (Rif)
(c) Output resistance (Rof)
(d) Source to load voltage gain (Vo/Vs).
(e) Specify the type of feedback.

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 Birla Institute of Technology and Science, Pilani
II semester 2022-2023
EEE F341/INSTR F341 Analog Electronics
Time: 50 min TUT-2 Date: 09-02-2023

Q1. To obtain a high-gain, high-input-resistance

difference amplifier the circuit in the Figure below
employs positive feedback, in addition to the negative
feedback provided by the resistor R connected from the
output to the negative input of the op amp. Specifically,
a voltage divider (R5, R6) connected across the output
feeds a fraction β of the output, that is, a voltage βv0,
back to the positive-input terminal of the op amp
through a resistor R. Assume that R5 and R6 are much
smaller than R so that the current through R is much
lower than the current in the voltage divider, with the
result that β≈R6/(R5 + R6). Show that the differential
gain is given by

Design the circuit to obtain a differential gain of 10 V/V and differential input resistance of 2 MΩ. Select
values for R, R5, and R6 such that (R5 + R6) ≤ R/100.

Q2. The circuit shown in the following figure use an

op-amp having a ±4 mV offset. What is the output
offset voltage? What does the output offset become
with the input ac coupled through a capacitor C? If,
instead, the 1-k resistor is capacitively coupled to
ground, what does the output offset becomes?

Q3. Sketch and label the frequency response of the

given circuit.

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 ---- Unit should be 'V'

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 Birla Institute of Technology and Science, Pilani
II semester 2022-2023
EEE F341/INSTR F341 Analog Electronics
Time: 50 min TUT-3 Date: 16-02-2023

Q1. Problems on Instrumentation amplifier

(a) Fig. 1 represents a vaiable gain instrumentation aplifier circuit using two op-apms. If all the op-
amps are ideal, derive the expression of output voltage.

(b) Derive the expression of output voltage of the instrumentation amplifier shown in Fig.2.

Fig. 1 Fig. 2

Q2. Problems on Miller Integrator

(a) A Miller integrator whose input and output voltages are initially zero and whose time constant is
1 ms is driven by the signal shown in Fig. 3 below. Sketch and label the output waveform.

(b) Consider a Miller integrator having a time constant of 1 ms, and whose output is initially zero,
when fed with a string of pulses of 10-µs duration and 1-V amplitude rising from 0 V (see Fig. 4
below). Sketch and label the output waveform resulting. How many pulses are required for an
output voltage change of 1 V?

Fig. 3 Fig. 4

(c) Design a Miller integrator that has a unity-gain frequency of 1 krad/s and an input resistance of
100 kΩ. Sketch the output you would expect for the situation in which 2-V 2-ms pulse is applied
to the input. Consider 0 V output initially.
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 Birla Institute of Technology and Science, Pilani
II semester 2022-2023
EEE F341/INSTR F341 Analog Electronics
Time: 50 min TUT-4 Date: 23-02-2023

Q1. A differentiator utilizes an ideal op-amp, a 10-k resistor, and a 0.01-µF capacitor. What is the
frequency f0 (in Hz) at which its input and output sine-wave signals have equal magnitude? What is the
output signal for a 1-V peak-to peak sine-wave input with frequency equal to 10f0 ?

Q2. Design the following differential equation using the capacitance of 0.1 µF only.
d2 v dv
2
+ 20 + 100v = 5
dt dt

Q3. Find the input impedance of the following circuit. Also, replace the Z1 to Z5 with resistors and capacitors
to realize a simulated inductance at the input of the circuit.

Q4. A third-order low-pass filter has transmission zeros at ω = 2 rad/s and ω = α . Its natural modes are at
s = - 1 and s = -0.5 ± j0.8. The dc gain is unity. Find the filter transfer function [T(s)].

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 Birla Institute of Technology and Science, Pilani
II semester 2022-2023
EEE F341/INSTR F341 Analog Electronics
Time: 50 min TUT-5 Date: 02-03-2023

Q1. Find the transfer function T(s) = VO(s)/Vi(s) for the following circuit and comment on the type of filter.
Find R1 and R3 of the circuit for Butterworth approximation when fo = 1 kHz and C2=C4=0.1 µF.

Q2. Q5. Draw the Bode magnitude plot for the given circuit below including the magnitude, 3 dB cut off
frequency and fO. Also, find a suitable value for Rcomp. Comment the type of the circuit below.

Q3. Determine the order N of the Butterworth filter for which Amax=1 dB, Amin ≥ 20 dB, selectivity ratio
ωs/ωp=1.3. What is the actual value of minimum stopband attenuation realized? If A min is to be exactly 20
dB, to what value can Amax be reduced.

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 Birla Institute of Technology and Science, Pilani
II semester 2022-2023
EEE F341/INSTR F341 Analog Electronics
Time: 50 min TUT-6 Date: 09-03-2023

Q1. A third order Butterworth low pass active filter is to be designed by cascading a first order and second
order stages as shown in the following figure (a) and figure (b) with 3 dB cutoff frequency of the filter to
be 30 kHz. What would be the cut off frequency of individual stage? (Consider 1.5 dB for each stage and
ɛ=1)
(a) Design a third order filter with unity gain and R2=R3=R4= 1 kΩ
(b) If R3=R4 and C2=C3, what would be the gain expected from the second stage.

Q2. Design a KHN circuit to realize a bandpass filter with center frequency of 1 kHz and 3-dB bandwidth
of 100 Hz. Use, 22 nF capacitor only. Draw the complete KHN circuit, specifying all the component values.
Find the center frequency gain. Given R1 = R2 = RF = 10 kΩ.

Q3. Design a non-inverting and inverting switch-capacitor integrator using a clock of 10 kHz signal to
obtain a 1 ms time constant.

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