Dante Experiment#2

UNIVERSITY OF THE EAST
College of Engineering
Computer Engineering Department
EXPERIMENT NO. 2
Half Adder and Full Adder
Course Code: NCP 3201 Program:

Course Title: Introduction to HDL Date Performed: 08/30/2022
Date Submitted: 09/04/2022
Name: DANTE, CHRISTIAN JOIE C. Professor: ENGR. NELSON
RODELAS
Learning Outcomes:
At the end of the experiment, the student should be able to:
1. Develop VHDL programs for Combinational Circuit Half Adder and Full Adder.
2. Construct an EPWave of Half Adder and Full Adder.
Discussion:
 Half adder is the simplest of all adder circuits. Half adder is a combinational
arithmetic circuit that adds two numbers and produces a sum bit (s) and carry bit
(c) both as output. The addition of 2 bits is done using a combination circuit
called a Half adder. The input variables are augend and addend bits, and the
output variables are sum & carry bits. A and B are the two input bits.
 Let us consider two input bits A and B, then sum bit (s) is the X-OR of A and B. it
is evident from the function of a half adder that it requires one X-OR gate and
one AND gate for its construction.
 Truth Table
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
 Here we perform two operations Sum and Carry, thus we need two K-maps one
for each to derive the expression.
 Logical Expression
Sum = A XOR B
Carry = A AND B
 Schematic Diagram
A
B SUM
CARRY
 Copy and paste the given code below on the testbench area and save.
library IEEE;
use IEEE.std_logic_1164.all;
entity Experiment_2 IS
end Experiment_2;
architecture Experiment_2TB OF Experiment_2 IS
-- Component Declaration for the Unit Under Test (UUT)
component Half_Adder
port(
a : in std_logic;
b : in std_logic;
sum : out std_logic;
cy : out std_logic);
end component;
--Inputs
signal a : std_logic := '0';
signal b : std_logic := '0';
--Outputs
signal sum : std_logic;
signal cy : std_logic;
begin
-- Instantiate the Unit Under Test (UUT)

UUT: Half_Adder port map (
a => a,
b => b,
sum => sum,
cy => cy
);
-- Stimulus process
stim_proc: process
begin
a <= '0';
b <= '0';
wait for 100 ns;
a <= '1';
b <= '0';
wait for 100 ns;
a <= '0';
b <= '1';
wait for 100 ns;
a <= '1';
b <= '1';
wait for 100 ns;
wait;
end process;
end Experiment_2TB;
 Copy and paste the following code to the design area.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Half_Adder is
port (
a : in std_logic;
b : in std_logic;
sum : out std_logic;
cy : out std_logic);
end Half_Adder;
architecture Half_AdderRTL of Half_Adder is
begin
sum<= a xor b;
cy<= a and b;
end Half_AdderRTL;
 Save and Run the Program.
Take note of the following coding errors:
• One possible mistake is incorrect spacing.
• Always log out of your EDAPlayground account after completing a program.
• Always alter the top entity's and title's names because the top entity's and title's
names must be the same. Furthermore, testbench names like SampleCode1 must
be the same as the top entity name.
• The design's name must be the same as the design's name after beginning
architecture (for example, Design or_
• There must be no spaces in the design's name.
• You must input all the codes, or an error will occur.
Activity:
1. Create the VHDL Module of the Full Adder.
2. Produce the EPWave of the Full Adder in the space provided.
3. Write the design code. (Separate page)
4. Screenshot of EPWave for Full Adder. (Separate page)
Question:
1. What are your observations from using EDA Playground in describing the code
for Half Adder and Full Adder?
One EX-OR gate and one AND gate are connected to create the combinational
logic circuit known as the half adder. A and B, the half adder circuit's two inputs,
add the two input numbers and produce a carry and a sum. The output of the
AND gate is the carry, but the output of the EX-OR gate is the sum of the two
values. Since there is no logic gate to handle it, carry addition cannot be
forwarded. So, the Half Adder circuit is what this is known as.
Two EX-OR gates, two AND gates, and one OR gate make up a full adder circuit.
Two EX-OR gates, two AND gates, and one OR gate are the two outputs that are
produced by the full adder, which adds the three inputs. A and B make up the
first two inputs, and C-IN is the third input. The normal output is denoted as S,
which represents SUM, while the output carry is designated as C-OUT. The
binary digit sum is the equation that the EX-OR gate produces. While the carry
obtained by addition is the output of the AND gate.
SCREENSHOS AND CODES:

CODES:
-- Code your testbench here signal sum : std_logic;
LIBRARY IEEE; signal cy : std_logic;
USE IEEE.std_logic_1164.ALL; -- No clocks detected in port list.
Replace <clock> below with
entity Experiment_2 IS
-- appropriate port name
end Experiment_2;
BEGIN
-- Instantiate the Unit Under Test
architecture Experiment_2TB OF
(UUT)
Experiment_2 IS
uut: Full_Adder PORT MAP (
a => a,
-- Component Declaration for the Unit
Under Test (UUT) b => b,
c => c,
COMPONENT Full_Adder sum => sum,
PORT( cy => cy
a : IN std_logic; );
b : IN std_logic; -- Stimulus process
c : IN std_logic; stim_proc: process
sum : OUT std_logic; begin
cy : OUT std_logic
); a <= '0';
END COMPONENT; b <= '0';
--Inputs c <= '0';
signal a : std_logic := '0'; wait for 100 ns;
signal b : std_logic := '0'; a <= '0';
signal c : std_logic := '0'; b <= '0';
--Outputs c <= '1';
wait for 100 ns; c <= '1';
a <= '0'; wait for 100 ns;
b <= '1'; a <= '1';
c <= '0'; b <= '1';
wait for 100 ns; c <= '0';
a <= '0'; wait for 100 ns;
b <= '1'; a <= '1';
c <= '1'; b <= '1';
wait for 100 ns; c <= '1';
a <= '1'; wait for 100 ns;
b <= '0';
c <= '0'; wait;
wait for 100 ns; end process;
a <= '1'; END Experiment_2TB;
b <= '0';
DESIGN:
-- Code your design here cy : out STD_LOGIC);
library IEEE; end Full_Adder;
use IEEE.STD_LOGIC_1164.ALL; architecture Behavioral of Full_Adder is
entity Full_Adder is
Port ( begin
a : in STD_LOGIC; sum<= a xor b xor c;
b : in STD_LOGIC; cy<= (a and b) or (b and c) or (c and a);
c : in STD_LOGIC; end Behavioral;
sum : out STD_LOGIC;

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UNIVERSITY OF THE EAST

Course Code: NCP 3201 Program:

architecture Experiment_2TB OF Experiment_2 IS

-- Component Declaration for the Unit Under Test (UUT)

-- Instantiate the Unit Under Test (UUT)

SCREENSHOS AND CODES:

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