ELECTRICAL ENGINEERING DEPARTMENT

ACADEMIC SESSION: JUN 2020

DEC50143 - CMOS IC DESIGN & FABRICATION
PRACTICAL WORK 3 : Layout Design and Simulation of Basic Logic Gates.
PRACTICAL WORK
DATE :
LECTURER’S NAME:
GROUP NO. :
TOTAL
STUDENT ID & NAME : MARKS
(100%)
(1)

(2)

(3)

(4)

(5)

DATE SUBMIT : DATE RETURN :

1 LEARNING OUTCOMES (LO):

1. : Design the basic logic gates, digital circuits from Boolean function and integrated
circuit layout based on the knowledge of integrated circuit design methodology

2. : Construct the layout design of CMOS circuits using layout design software based on
specific CMOS layout design rules

3. : Demonstrate elements of environmental sustainability in implementing reduce and

reuse techniques in design parameters and design consideration through practical
work

2 OBJECTIVE

At the end of this practical work session, the student should be able to:
a. to design the layout of the following logic gates:
i. 2-input NAND gate and 2-input AND gate
ii. 2-input NOR gate and 2-input OR gate
b. to simulate the layout of each gate in (a)
c. to design the layout of IC 4011/ IC 4081/ IC 4001 / IC 4071

3 THEORY

1. Steps to construct CMOS logic circuit:

i. Identify the function f to determine

PMOS network.
ii. Identify the function f to determine
NMOS network.
iii. AND function is obtained when the
transistors are in series.
iv. OR function is obtained when the
transistors are in parallel.

Example : 2 input NAND gate

 2. Steps to construct stick diagram using Euler-Path method:
i. Label all the transistor terminals.
ii. Draw Euler path for PUN and PDN (both path must go through transistors in the same order).
iii. Transfer all the transistor terminals onto the stick diagram according to Euler path.
iv. Make a connection using metal layer.

Example : Stick diagram for 2 input NAND gate

4 EQUIPMENT / TOOLS

PC Set & Microwind 2.6a software.

5 PROCEDURE

Part A: Designing and simulating the layout of 2 input NAND gate.

Figure 4.1: Symbol of 2-input NAND gate Figure 4.2: CMOS static logic diagram of
2-input NAND gate

1. Based on figure 4.2, draw the stick diagram of 2 input NAND gate using Euler’s path method.

Figure 4.3: Stick diagram of 2-input NAND gate

2. Open the Microwind Editor window.

3. Select the Foundry file from File menu. Select “cmos012.rul” file.
4. Draw the layout of 2-input NAND gate based on the stick diagram in Figure 4.3.
Use: NMOS size - W=6λ, L=2λ
PMOS size - W=12λ, L=2λ

Figure 4.4: Layout of 2 input NAND gate

5. Make sure that your layout conforms to all the design rules.
Run DRC by selecting:
>Analysis>Design Rule Checker
6. Add clock to input A and input B of the layout. To observe the output, place a Visible Node
icon at the output.
7. Let’s set the value for of the pulse at input A as the following:
Time low = 0.2 ns
Time high = 0.2 ns
Rise time = Fall time = 0.001 ns
8. Click OK.
9. Let’s set the value for of the pulse at input B as the following:
Time low = 0.4 ns
Time high = 0.4 ns
Rise time = Fall time = 0.001 ns
10. Click OK.
11. Save your layout.
12. Simulate the inverter layout by selecting:
>Simulate> Run Simulation>Voltage vs Time (default) on the main menu.
The timing diagram of the 2 input NAND gate appear, as shown in figure 4.5.

Figure 4.5: Timing diagram of 2-input NAND gate

13. Produce the truth table for 2-input NAND gate based on the timing diagram produced in
step 8. The truth table for 2-input NAND gate is shown in figure 4.6.

Figure 4.6: Truth table of 2-input NAND gate

14. Measure the optimized area of the layout (the unit is λ 2).
Part B: Designing and simulating the layout of 2-input AND gate .

Figure 4.7: Symbol of 2-input AND gate Figure 4.8: CMOS static logic diagram
of 2-input AND gate

1. Based on figure 4.8, draw the stick diagram for 2-input AND gate using Euler’s path method.

Figure 4.9: Stick diagram of 2-input AND gate

2. Open the Microwind Editor window.

3. Select the Foundry file from File menu. Select “cmos012.rul” file.
4. Draw the layout of 2-input AND gate based on the stick diagram in figure 4.9.
Use: NMOS size - W=6λ, L=2λ
PMOS size - W=12λ, L=2λ

Figure 4.10: Layout of 2-input AND gate

 5. Make sure that your layout conforms to all the design rules.
Run DRC by selecting:
>Analysis>Design Rule Checker
6. Add clock to input A and input B of the layout. To observe the output, add Visible Node icon
at the output. (The settings of the clock pulses are the same as in Part A)
7. Save your layout.
8. Simulate the inverter layout by selecting:
>Simulate> Run Simulation>Voltage vs Time (default) on the main menu.
The timing diagram of the 2-input AND gate appear, as shown in figure 4.11.

Figure 4.11: Timing diagram of 2-input AND gate

9. Produce the truth table for 2-input AND gate based on the timing diagram produced in step
8. The truth table for 2-input AND gate is shown in figure 4.12.

Figure 4.12: Truth table of 2 input AND gate

10. Measure the optimized area of the layout (the unit is λ 2).

Part C: Designing and simulating the layout of 2 input NOR gate.

1. Draw the CMOS static logic diagram of 2-input NOR gate.

2. From the static logic diagram, draw the stick diagram of 2-input NOR gate using Euler’s path
method.
3. Repeat Step 2 until Step 10 in Part B for 2-input NOR gate.
 Part D: Designing and simulating the layout of 2 input OR gate.

1. Draw the CMOS static logic diagram of 2-input OR gate.

2. From the static logic diagram, draw the stick diagram of 2-input OR gate using Euler’s path
method.
3. Repeat Step 2 until Step 10 in Part B for 2-input OR gate.

6 RESULT

In your report, include the results of the following:

1. 2-input NOR gate:
a) CMOS static logic diagram (1 mark)
b) Stick diagram (1 mark)
c) Layout (1 mark)
d) Timing diagram (1 mark)
e) Truth table (1 mark)
f) Optimized layout area = _________ λ x _________ λ
= _________ λ 2 (1.5 marks)

2. 2-input OR gate:
a) CMOS static logic diagram (1 mark)
b) Stick diagram (1 mark)
c) Layout (1 mark)
d) Timing diagram (1 mark)
e) Truth table (1 mark)
f) Optimized layout area = _________ λ x _________ λ
= _________ λ 2 (1.5 marks)

7 DISCUSSION

1. What is the function of stick diagram in integrated circuit layout design?

(2 marks)
2. State the color codes for stick diagram.
(3 marks)
3. Explain the use of metal2 layer in designing the layout of CMOS IC.
(2 marks)

8 CONCLUSION

Write TWO (2) conclusions for the practical work that you have done.
(4 marks)
Appendix

CMOS Logic Gates

IC 4011 – 2 input NAND IC 4081 – 2 input AND

gate gate

IC 4001 – 2 input NOR gate IC 4071 – 2 input OR gate

 PRACTICAL SKILL ASSESSMENT RUBRIC
DEC50143 CMOS IC DESIGN & FABRICATION
PRACTICAL WORK 3
Student Name : Class :
Date :
Student ID# :

SCORE DESCRIPTION
ASPECTS EXCELLENT MODERATE POOR SCALE SCORE
4-5 2-3 1
Use correct technology feature Use correct technology feature
A. Technology feature Use other technology feature. x1
for ALL parts of the layout. for parts of the layout.
Follow lambda design rule for
Follow lambda design rule for Follow lambda design rule for
B. Design rule minimum width and spacing for x1
MANY of the polygons. ONLY a few of the polygons.
ALL polygons.
Use correct PMOS and NMOS Use acceptable PMOS and NMOS Use incorrect PMOS and
C. Transistor size x2
transistor size. transistor size. NMOS transistor size.
Use correct number of metal Use correct metal layers but Use incorrect metal layers and
D. Metal layers x2
layers and width. incorrect width. width.
‘No DRC error’ Able to produce ‘No DRC error’ Able to produce ‘No DRC error’ Not able to produce ‘No DRC
E. x2
display display for ALL layouts. display for some of the layouts. error’ display at ALL.
Layout Design Produce acceptable floorplan
Produce good floorplan and Produce appropriate floorplan
F. – input / output / and input / output layout x2
input / output layout design. and input / output layout design.
floorplan design.
Not able to produce any
Able to produce the simulation Able to produce the simulation
G Layout simulation simulation for ALL of the x2
of ALL layouts correctly. for some of the layouts correctly.
layouts.
Layout size (end Produce small layout size (end Produce acceptable layout size Produce large layout size (end
H. x2
product) product). (end product). product).
TOTAL / 70

… …………….…………………….
Supervisor Name & Signature