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    International Islamic University, Islamabad: FPGA Based Design LAB

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    Muhammad Saud
    This document provides instructions for interfacing a PS/2 keyboard with an FPGA. It describes connecting the keyboard to the FPGA board and implementing a design with Verilog modules to deserialize, decode, and display the scanned keyboard codes. The design takes the keyboard clock and data signals as inputs and outputs the pressed key value. It also lists the pin mappings for connecting the design to the Spartan 3E and Virtex 2 Pro FPGA boards.

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    International Islamic University, Islamabad: FPGA Based Design LAB

    Uploaded by

    Muhammad Saud
    28 views5 pages
    This document provides instructions for interfacing a PS/2 keyboard with an FPGA. It describes connecting the keyboard to the FPGA board and implementing a design with Verilog modules to deserialize, decode, and display the scanned keyboard codes. The design takes the keyboard clock and data signals as inputs and outputs the pressed key value. It also lists the pin mappings for connecting the design to the Spartan 3E and Virtex 2 Pro FPGA boards.

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    This document provides instructions for interfacing a PS/2 keyboard with an FPGA. It describes connecting the keyboard to the FPGA board and implementing a design with Verilog modules to deserialize, decode, and display the scanned keyboard codes. The design takes the keyboard clock and data signals as inputs and outputs the pressed key value. It also lists the pin mappings for connecting the design to the Spartan 3E and Virtex 2 Pro FPGA boards.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    28 views5 pages

    International Islamic University, Islamabad: FPGA Based Design LAB

    Uploaded by

    Muhammad Saud
    This document provides instructions for interfacing a PS/2 keyboard with an FPGA. It describes connecting the keyboard to the FPGA board and implementing a design with Verilog modules to deserialize, decode, and display the scanned keyboard codes. The design takes the keyboard clock and data signals as inputs and outputs the pressed key value. It also lists the pin mappings for connecting the design to the Spartan 3E and Virtex 2 Pro FPGA boards.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 5

    International Islamic University,

    Islamabad
    FPGA Based Design LAB

    EXPERIMENT # 10: Keyboard Interfacing with FPGA

    Name of Student:

    Roll No.:

    Date of Experiment:

    Report submitted on:

    Marks obtained:

    Remarks:

    Instructor’s Signature:

    FPGA Based Design Lab (EE-406L) Page 73


    Keyboard Interfacing with FPGA
    1. Objective
    This lab exercise is designed to understand the design and then implement the PS/2
    Keyboard interfacing with FPGA on Spartan 3E or Spartan 2 kit.

    2. Resources Required
    • A Computer
    • Xilinx ISE
    • Spartan 2 or Spartan 3E board
    • PS2 Keyboard

    3. Introduction
    The PS/2 connector is a 6-pin mini-DIN connector used for connecting some keyboards and mice
    to a PC compatible computer system. Its name comes from the IBM Personal System/2 series of
    personal computers, with which it was introduced in 1987. The PS/2 mouse connector generally
    replaced the older DE-9 RS-232 "serial mouse" connector, while the PS/2 keyboard connector
    replaced the larger 5-pin/180° DIN connector used in the IBM PC/AT design. The PS/2 designs
    on keyboard and mouse interfaces are electrically similar and employ the same communication
    protocol.

    Keyboard with Hex Scan Codes

    1- Keyboard Data 2- Reserved

    3- Ground 4- Power Supply (+5V)

    5- Keyboard Clk 6- Reserved

    PS2 Keyboard Connector Pin Diagram

    FPGA Based Design Lab (EE-406L) Page 74


    The Spartan3E FPGA Kit includes PS/2 port for mouse/keyboard interface and it is the standard
    6-pin mini-DIN connector, labeled J8 on the board. Table shows the signals on the connector. Only
    pins 1 and 5 of the connector is attached to the FPGA I/O lines

    PS/2 XC3S500E-Pins

    PS2_CLk P174
    PS2_DATA P175

    4. Verilog Codes (to be utilized in this lab)

    Top Module
    module top_keyboard(out,kbrd_clk,kbrd_data,rst);

    input kbrd_clk,kbrd_data,rst;
    output [3:0]out;

    wire [7:0] data;

    deserialize des(.in(kbrd_data),.clk(kbrd_clk),.out(data),.rst(rst));
    decoder dec(.out(out),.in(data));

    endmodule

    Deserialize Module
    module deserialize(in,clk,out,ready,rst);

    input in,clk,rst;
    output [7:0] out;
    output ready;

    reg start_bit,r0,r1,r2,r3,r4,r5,r6,r7,parity,stop;

    reg [3:0]counter;
    reg ready;
    reg [7:0] out;

    always@(negedge clk or negedge rst)


    begin
    if(!rst)
    begin
    start_bit <= 0;

    FPGA Based Design Lab (EE-406L) Page 75


    r0<= 0;
    r1<= 0;
    r2<= 0;
    r3<= 0;
    r4<= 0;
    r5<= 0;
    r6<= 0;
    r7<= 0;
    parity<= 0;
    stop<= 0;
    end
    else
    begin
    stop <= in;
    parity <= stop;
    r7 <= parity;
    r6 <= r7;
    r5 <= r6;
    r4 <= r5;
    r3 <= r4;
    r2 <= r3;
    r1 <= r2;
    r0 <= r1;
    //start_bit <= r0;
    end
    end
    always@(negedge clk or negedge rst)
    begin
    if(!rst)
    begin counter <= 0; ready <= 0; end
    else if(counter == 4'd10)
    begin counter <= 0; ready <= 1; end
    else
    begin counter <= counter + 1; ready <= 0; end
    end

    always@(posedge clk)
    begin
    if(ready)
    out <= {r7,r6,r5,r4,r3,r2,r1,r0};
    else
    out <= out;

    end

    endmodule

    FPGA Based Design Lab (EE-406L) Page 76


    Decoder Module
    module decoder(out,in);

    output [3:0] out;


    input [7:0]in;

    reg [3:0] out;


    always@(in)
    begin
    case(in)
    8'h16: out <= 4'd1;
    8'h1E: out <= 4'd2;
    8'h26: out <= 4'd3;
    8'h25: out <= 4'd4;
    8'h2E: out <= 4'd5;
    8'h36: out <= 4'd6;
    8'h3D: out <= 4'd7;
    8'h3E: out <= 4'd8;
    8'h46: out <= 4'd9;
    8'h45: out <= 4'd0;
    default : out<= 4'd0;
    endcase
    end

    endmodule

    Implementation on Spartan 3E Board Implementation on Virtex 2 Pro Board

    NET "kbrd_clk" LOC = "P174" ; NET "kbrd_clk" LOC = "AG2" ;


    NET "kbrd_data" LOC = "P175" ; NET "kbrd_data" LOC = "AG1" ;
    NET "out[0]" LOC = "F11" ; NET "out[0]" LOC = "AC4" ;
    NET "out[1]" LOC = "E11" ; NET "out[1]" LOC = "AC3" ;
    NET "out[2]" LOC = "E12" ; NET "out[2]" LOC = "AA6" ;
    NET "out[3]" LOC = "F12" ; NET "out[3]" LOC = "AA5" ;
    NET "rst" LOC = "L13" ; NET "rst" LOC = "AC11" ;

    FPGA Based Design Lab (EE-406L) Page 77

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