TESTABILITY FOR VLSI (MELZG531)

Assignment -1 : Analog and Mixed Signal Testing

Submitted By - Rahul Agarwal (2022ht80055)

Introduction :
The cost of integrated circuits increases with the complexity and integration density. This has led designers
to consider testing from the design phase; that's what we call DFT (Design For Testability).
DFT includes all design techniques that aim to facilitate testing of integrated circuits at the last stage of
manufacturing as well as in the use of these devices in their applications. Such task is especially difficult in
the case of analog and mixed signal integrated circuits. Indeed, techniques applied on analog and mixed
circuits are not as developed and mastered as digital ones.
The ways for reduction of a test cost Design-For-Testability (DFT) investigation of possibilities and
preparation of the recommendations for electronic device testing during early stages of its designing
Automated Test Pattern Generation (ATPG) automation of test development process and testing
realization, development and improvement of modern computer aided test generation systems.

The complexity of IC testing :

• The changes in the technological process;

• The growing scale of integration
• The rise of functional complexity
• Absence of access to internal components and nodes of the circuit, etc.

The current practice for testing the analog and mixed-signal (AMS) functions of ICs is specification based
testing. It involves direct measurement of the performances that are promised in the specification data sheet
one by one. However, despite the ease of interpreting the test result, specification-based testing incurs a
very high cost since it relies on specialized Automatic Test Equipment (ATE) with advanced capabilities and
running the tests takes a long time. In fact, testing the AMS functions of modern Systems-on-Chip (SoC) is
responsible for the largest fraction of the test cost despite the fact that AMS circuits occupy a much smaller
area on the die compared to their digital counterparts. With the ever-increasing levels of integration of SoC
designs, more and more of which include AMS circuits, ATE cost, test development and test execution times
are being increasingly impacted and will keep increasing as we move towards more advanced technology
nodes. AMS testing is nowadays an area of focus and innovation for the microelectronics industry.
Characteristics of Analog Circuit Testability for internal nodes:
➢ Controllability is understood as relative difficulty of setting a node to a specific value.
▪ This measure is normalized to range between 0.0 and 1.0, with 1.0 being totally controllable
and 0.0 being totally uncontrollable.
▪ Primary inputs are by definition totally controllable.

➢ Observability is understood as relative difficulty of propagating an error from an internal node to a

primary output.
▪ This measure is normalized to range between 0.0 and 1.0, with 1.0 being totally observable
and 0.0 being totally unobservable. Primary outputs are by definition totally observable.

➢ Testability Transfer Factor (TTF) allows to determine how controllability and observability influence
on passing of test information, which is propagated through one components to other components
or to primary outputs.
▪ It represents easiness of achieving an arbitrary signal on its outputs by exercising its inputs.
▪ It helps in determining whether a specific signal occurred on its inputs by examining the values
on its outputs.

Testability Measuring:

➢ Controllability Calculation
The input controllability of a component represents the easiness of achieving an arbitrary signal value at the
component's inputs.
The output controllability of a component represents the easiness of producing an arbitrary signal value on
the outputs of the component. It depends on the input controllability and the testability transfer factor of
the component.

Cout = Tf Cin
Where Cin – input controllability of the component;
Cout – output controllability of the component;
Tf – Testability Transfer Factor of the component.

The controllability for any node i (or any vertex i in the signal flow graph) can
be expressed as :

Where Ci – controllability of node i;

Fin – fan-in of node i;
Cm – controllability at source node of fan-in m;
(Tf )m - Testability Transfer Factor of fan-in m
➢ Observability Calculation
The output observability of a component represents the easiness of determining whether or not the
expected signal value occurs at the inputs of the component by observing the signal values at the primary
outputs of the circuit.

The input observability of a component represents the easiness of determining whether or not the expected
signal value occurs there, by observing the signal values at the primary outputs of the circuit.

Since the testability transfer factor represents the easiness of propagating a signal through the component,
then input observability can be expressed as

Oin = Tf Oout
Where Oin – input observability of the component;
Oout – output observability of the component;
Tf – Testability Transfer Factor of the component.

The observability for any node i (or any vertex i in the signal flow graph) can be expressed as :

Where Oi – observability of node i;

Fout – fan-out of node i;
Om – observability at source node of fan-out m;
(Tf)m - Testability Transfer Factor of fan-out m.

➢ Testability Calculation
For testability measure of circuit node i the geometric mean of two characteristics (controllability and
observability) are proposed to use:

Where Ti is the testability of node i;

Ci is the controllability of node i;
Oi is the observability of node i.

The common testability measure of a whole circuit can be expressed as simple mean value of testability
measures of all circuit nodes:

Where T is the testability of a circuit;

Ti is the testability of node i;
N is a number of circuit nodes.
Advantages of Design-For-Testability
➢ Reduction of testing time and as consequence decrease of IC’s total cost;
➢ Increasing of the fault coverage;
➢ Increasing of the circuit reliability;
➢ Verification of the output characteristics in real-time mode.

DFT solutions for Analog Circuits

➢ Reconfiguration-based test
▪ Division on functional blocks;
▪ Rearranging of circuit internal structure.
➢ Code-based test
▪ The methods of Code-based approach are used for on-line testing and allow to decide task of
measuring the values of on-chip signals in real time mode. A redundant data code is used to
encode on-chip data.

The groups of DFT techniques for Analog Circuits :

➢ Support for External Test and Evaluation;
▪ IDDQ testing
▪ Transient Response Testing
▪ Residual Multiple Frequency Testing
➢ Access to Embedded Blocks
➢ On-chip Test Evaluation
➢ Built-In Self-Test
➢ On-chip Multi-Module System Test

Built-In Self-Test:
The strategies of Built-In Testing :
▪ On-line (working mode) : Faults are detected during execution by the circuit of intended for it
function.
▪ Off-line (dedicated mode) : Tested circuit is switched to the dedicated mode, at which the usual
operation of the device is impossible.
For many decades, mixed-signal integrated circuits (ICs) have been tested successfully through conventional
testing approaches. But with more and more mixed-signal functions being integrated into complex
application-specific IC, companies no longer can afford to rely on conventional methods for testing mixed-
signal ICs. Faced with more complex testing challenges, many designers and test engineers are looking for a
mixed-signal design-for-test (DFT) solution to help them reap the advantages that their digital counterparts
enjoy today.

Testing is applied to detect faults after several operations: design, manufacturing, packaging, as illustrated
in below figure:

Typical IC production flow

If a test strategy is considered at IC level, the fault can be detected at early system design stages, located
and eliminated at a very low cost (The rule of ten).
Fault Model
A fault is a model that represents the effect of a failure by means of the change that is produced in the
system signal. As a model, the fault does not have to be an exact representation of the defects, but rather,
to be useful in detecting the defects. The most common fault model assumes single stuck-at (SSF) lines even
though it is clear that this model does not accurately represent all actual physical failures. However, test sets
that have been generated for this fault type have been effective in detecting other types of faults. Figure
illustrates a possible origin for a node stuck at 0 voltage: the implementation is close to a VSS node (here
situated close, same layer), and a faulty metal bridge makes a robust connection to the ground.

Physical origin of node fault stuck at 0

However, the manufacturing of interconnects may result in interruptions or short-cuts, which may have
catastrophic consequences on the behavior of the integrated circuit.

TABLE I. MOST COMMONLY USED FAULT MODELS

Fault Model Description

Single stuck-at One line takes the value 0 or 1.
faults (SSF)
Multiple stuck-at One, two or more lines have fixed values, not necessarily the same.
faults (MSF)
Bridging faults Two or more lines that are normally independent become electrically connected.
Delay faults A fault is caused by delays in one or more paths in the circuit.
Intermittent faults Caused by internal parameter degradation. Incorrect signal values occur for some but
not all states of the circuit. Degradation is progressive until permanent failure occurs.
Transient faults Incorrect signal values caused by coupled disturbances. Coupling may be via power
bus capacitive or inductive coupling. Includes internal and external sources as well as
particle irradiation.

In the digital world, many years of DFT development are paying off. Digital built-in self-test (BIST) now is
economical and, in many cases, the only practical way to get a product to market quickly and cost effectively.
As semiconductor technology enables larger gate counts, more mixed-signal functions are being integrated
into ICs. These ICs contain hundreds of thousands of logic gates that are designed using a high-level hardware
description language such as Verilog or VHDL.
The lack of automation for design and test development for mixed-signal functions contrasts starkly with
DFT for digital functions. For this reason, test development for mixed-signal functions has been a major
bottleneck in improving time- to-market, decreasing test costs, and increasing test performance. New
breakthroughs in mixed-signal BIST, however, provide the opportunity to remove this bottleneck and
streamline the test-development process.

Designing mixed-signal ICs for testability can simplify and accelerate design debug and characterization. It
can enable more economical testing through the use of lower-cost testers or faster tests. And by providing
less intrusive monitoring of performance and better diagnostics, DFT can improve quality, yield, and yield
management.

Many issues, however, have prevented the widespread adoption of any single mixed-signal DFT style. New
digital BIST solutions are emerging that address these issues.

Mixed-Signal DFT History

Today, the most common approach to mixed-signal DFT is ad hoc. Many companies have developed their
own application-specific ways to improve testability, including adding special function modes and
instructions, increasing the number of output and input pins, and providing internal loops. These methods
exploit the peculiarities of each design and are used because they occupy a small area on the IC and have
minimal impact on performance. However, the design- and process-specific nature of these methods makes
them very difficult to automate or teach to new engineers.

A notable ad hoc method is loop-around which has been used in telecommunications ICs for many years,
both at the IC and board level. The loop-around method exploits the presence of a transmitter or analog-to-
digital converter (ADC) together with the complementary receiver or digital-to-analog converter (DAC). The
limitations to this approach — gain and noise masking, crosstalk issues, and lack of diagnostic capability —
result in a test that is not thorough.

On-chip analog buses are common and were discussed in publications in the mid-1980s. Typically, only an
output bus that drives a multiplexed high-performance function output amplifier or a low-performance
dedicated amplifier and test pin is implemented. With the latter case, you can see signals while the rest of
the IC is functioning normally. Analog buses are still somewhat ad hoc in nature. The choice of signals to
monitor requires understanding the impact of loading on the monitored signals, the diagnostic value of the
signals, crosstalk, and the impact of the limited bandwidth of the bus.

Off-chip monitoring of the internal analog signals of an IC almost always impacts its performance. The off-
chip version of the signals inevitably has more noise and distortion, leading to a reduction in fault coverage
or yield. Nevertheless, the approach has potential for being a methodical test access, especially if it becomes
a standard.
The IEEE P1149.4 Standard for a Mixed-Signal Test Bus, which received 93% acceptance on its first ballot in
September 1997, uses an input and output analog bus to access analog pins (and optionally, internal nodes)
of an IC. The standard primarily is aimed at improving board testability by facilitating measurement of simple
passive and active components on the board without a bed-of-nails tester.

IEEE 1149.4 Architecture

Many other analog DFT approaches have been proposed, but most require reconfiguration of the function
under test. Some approaches propose that internal operational amplifiers be converted into unity gain
amplifiers and cascaded for testing all amplifiers at once or reconfiguring selected op-amps to provide serial
access.

Other approaches suggest connecting the output of a function to its own input via an accurate analog
feedback network so that the function becomes an oscillator. Connections to carefully selected internal
nodes of op-amps or filters are advocated by other approaches. All these approaches have not been
implemented in industry. They require significant changes to handcrafted designs, jeopardize performance,
and significantly increase the simulation time, which are not issues in digital design because gate-level design
is automated.

The urgent need to reduce the mixed-signal test-development effort that occurs after an IC is manufactured
led to virtual test. Virtual Test is simulation of the IC being tested, the interface board, and the test program
running on the tester. Because simulation times are longer than those for the IC alone, behavioral models
for all functions in the IC, interface board, and tester are essential. This approach can help test engineers
better understand the IC and debug the test program, but relies on accurate behavioral models and does
not automate test program creation. In other words, virtual test is a test simulation strategy but does not
improve testability.
Mixed-Signal BIST
The most promising approach to improving mixed-signal DFT is BIST. In the past, many proposals for mixed-
signal BIST have been published, but almost none have been used in industry. Most of the proposals have
the same drawbacks including area, impact on performance, and lack of automation. For BIST to supplant
conventional mixed-signal test, it must be accurate in the presence of normal parametric variations, noise
tolerant to achieve test repeatability, and diagnostic to enable measurement of the key data-sheet
parameters that ensure quality and yield.

New mixed-signal BIST solutions must avoid the problems of previous DFT and BIST approaches. The BIST
circuits must be digital, synthesizable from Verilog/VHDL RTL descriptions, and suitable for automatic layout.
The only connections to the functions being tested must be to the normal inputs and outputs, with no
internal analog changes needed. The algorithms must tolerate typical noise and process variations and
output key data-sheet parameter values (digitally encoded) and pass/fail bits.

Key mixed-signal functions that need solutions are ADCs and DACs and phase-locked loops (PLLs).
LogicVision recently patented a digital method that finds the third-order polynomial that fits the time-
domain transfer function of ADCs. The algorithm derives values for offset, gain, and second and third
harmonic distortion. The company also has developed other digital techniques to measure the loop gain,
lock range, lock time, and jitter of PLLs at full speed, using approximately 1k gates.

The Future of Mixed-Signal Test

When complete BIST for an IC is possible, a tester will only need to provide a few high-speed signals, such as
a master clock, a few low-speed test-control signals (five 1149.1 digital pins and two 1149.4 analog pins),
and power. The development of a mixed-signal BIST is a significant step in making this scenario possible.

However, BIST will not cause conventional testers to become obsolete. Mixed-signal BIST can enable better
use of mainframe testers by facilitating testing of more functions in parallel or more devices in parallel with
a small number of high-performance channels allocated to each tested device.

Because each type of mixed-signal function needs a unique test, it is likely that industry will only develop
BIST for the most common functions, such as ADCs and DACs, PLLs, and filters. Companies will continue to
create ad hoc solutions for other specialized functions, but will benefit from the emergence of the 1149.4
mixed-signal test bus as a standard way to convey continuous variables to and from the functions under test.

A continuum of solutions will be available, ranging from BIST for generic functions to embedded
measurement for generic parameters, to parameter translation (which is a form of data compression), and
to conventional automatic test pattern generation (ATPG) and conventional test. The most efficient ATPG
for mixed-signal testing is for circuits with BIST—the test pattern is digital, simple, and tester independent.
IDDQ TESTING

IDDQ testing can be incorporated into a specific DFT testing technique. Indeed I DDQ testing is a technique
based on measuring level of current in an integrated circuit, a functional circuit consumes a well-defined
current. A defect is likely to increase the consumption of current in an integrated circuit. This
overconsumption is detected by the BICS, which indicate the appearance of a defect. The technique is
considered as a valuable complement to other methods for testing circuits, in the interest that it allows the
detection of certain types of defects that could not be found by using the basic techniques. Some defects
can cause an excess of current without affecting the performance of the circuit, the IDDQ test can detect
these defects, like the appearance of resistive circuits between two terminals of the transistor quad.

This testing method is based on the principle that there is no static current path between the power supply
and the ground in a correctly operating quiescent CMOS digital circuit – except for a small amount of leakage.
It then detects the leak by picking up on any increased magnitude of the current, which is easily shown due
to semiconductor manufacturing faults. It then has the upper hand of being able to check the chip for as
many possible faults with only one measurement. It also works much better than conventional stuck-at fault
test vectors in the sense that it picks up faults that usually go by these measurements undetected.

Even though this method is quite popular and simple, its inner workings are very complex. It goes beyond
just measuring the supply current. To use an example, if a line is shortened to Vdd it will still be unable to
draw extra current if the gate driving the signal is set to ‘1’. But a different input attempting to set the signal
at ‘0’ will show an increase in quiescent current that will indicate a bad part in the electrical stream. A typical
Iddq test will use about 20 inputs. These test inputs need only controllability and not necessarily
observability. The reason for this is that observability takes place through the shared power connection.

Faults detected by IDDQ tests:

• Bridging Faults: Shorts between two nodes causing a voltage contention because they are being driven
by two conflicting voltages. Sometimes also referred to as stuck-on faults.
• Punch-through: Short between Drain and the source.
• Resistive Shorts
• Line and Gate Break Faults
• Source or Drain Break Faults
• Even some Delay Faults
• Latch-Up
• Stuck-open Faults
Comparison with other testing methodologies:

• While other testing methodologies like scan and atspeed rely on detecting the voltage level at the node
in question which is being tested for a desired fault, IDDQ testing senses current levels.
• Traditional testing methodologies rely on the two pillars of DFT namely: controlability and observability
as the sensitized fault (controlability) needs to be propagated to the output (observability), in order to
detect a fault. In IDDQ testing, all faults are propagated to the power supply which is much easier to do
so.
• Hence, typically, only 2-3 test vectors are sufficient to achieve a 50% fault coverage for IDDQ testing.
• Scan and atspeed testing require ATE (Automatic Test Equipment) to apply test patterns and receive the
output of the DUT (Device Under Test). lopa tests require an off-chip current monitoring device, in
addition to the ATE.

The advantages of Iddq are far greater than anyone could have ever imagined. Firstly, it is a simple and direct
test that can identify physical defects more effectively than standardised equipment or methods. Secondly,
the time period attached to it isn’t very demanding. What this means is that the design time and area
overhead are relatively low. The test generation is fast, the test application time is fast due to the small sets
in vectors, and it catches underlying effects that other tests can’t pick up on immediately.

One disadvantage of Iddq testing is that it can be time consuming if compared to methods like scan testing.
It is also a more expensive option, comparatively speaking. The reason for this is because it is achieved by
current measurements that take much more time than reading digital pins in mass production.