IEEE SOLID-STATE CIRCUITS SOCIETY

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2023 IEEE

SAN FRANCISCO
FEBRUARY

CIRCUIT DESIGN
SOLID-STATE

DRAFT 2-8-2023
INTERNATIONAL

19, 20, 21, 22, 23

CONFERENCE THEME:

MARRIOTT MARQUIS HOTEL

BUILDING ON 70 YEARS OF
INNOVATION IN SOLID-STATE
ADVANCE PROGRAM

CIRCUITS CONFERENCE
SUNDAY ALL-DAY THURSDAY ALL-DAY
3 FORUMS: TRANSCEIVERS FOR EXASCALE; FUTURE OF AUTOMOTIVE TECHNOLOGY; WIRELESS POWER AMPLIFICATION 4 FORUMS:
5 - D AY 12 TUTORIALS: ADVANCING TECHNOLOGIES FOR XR; EXTREME DATA CONVERTERS;
FUNDAMENTALS OF FREQUENCY REFERENCES; BRIDGING RF AND POWER; FUNDAMENTALS OF DATA CONVERTERS; AUTOMOTIVE SYSTEM DESIGN; HETEROGENEOUS MULTI-CORE ARCHITECTURES FOR AI;
PROGRAM FUNDAMENTAL CONCEPTS TO FUTURE TRENDS; SOLID-STATE CMOS LIDAR; FUNDAMENTALS OF UL VOLTAGE; CURRENT-MODE PASSIVE MIXERS & N-PATH IN RF RECEIVERS; WEARABLE & IMPLANTABLE DEVICES
PHYSICAL-LAYER SECURITY FOR LATENCY; ART OF MM-WAVE; DIGITAL EQUALIZATION & TIMING RECOVERY; EXTENDING PROCESSOR CORES FOR ML
SHORT-COURSE:
2 EVENING EVENTS: GRADUATE STUDENT RESEARCH IN PROGRESS; MENTORING SESSION/NETWORKING BINGO QUANTUM COMPUTING & THE APPLICATION OF CRYOELECTRONICS
 ISSCC VISION STATEMENT
The International Solid-State Circuits Conference is the foremost global forum for presentation of advances
in solid-state circuits and systems-on-a-chip. The Conference offers a unique opportunity for engineers
working at the cutting edge of IC design and application to maintain technical currency, and to network with
leading experts.

CONFERENCE TECHNICAL HIGHLIGHTS

On Sunday, February 19th, the day before the official opening of the Conference, ISSCC 2023 offers:
• A choice of 12 Tutorials, or
• A choice of 1 of 3 all-day Advanced-Circuit-Design Forums:
“Transceivers for Exascale: Towards Tbps/mm and sub-pJ/bit”
  “The Power Behind Electrical Vehicles – Accelerating the Future of Automotive Technology
“Efficient Wireless Power Amplification and Linearization”

The 90-minute tutorials offer background information and a review of the basics in specific circuit- and
system-design topics. In the all-day Advanced-Circuit-Design Forums, leading experts present state-of-the-
art design strategies in a workshop-like format. The Forums are targeted at designers experienced in the
technical field.

On Sunday, February 19th, there are two events: “Mentoring Session/Networking Bingo” will be offered
starting at 3:00 pm. In addition, the Student-Research Preview, featuring ninety-second introductory
presentations followed by a poster session from selected graduate-student researchers from around the
world will begin at 8:00 pm. The SRP will start with an inspirational lecture by Professor Mark Horowitz
(Stanford University).

On Monday, February 20th, ISSCC 2023 at 8:30 am offers four plenary papers on the theme: “Building on
70 Years of Innovation in Solid-State Circuit Design”. On Monday at 1:30 pm, there are five parallel technical
sessions, followed by a Social Hour at 5:15 pm open to all ISSCC attendees. The Social Hour, held in
conjunction with Book Displays and Author Interviews, will also include a Demonstration Session, featuring
posters and live demonstrations of selected papers from industry and academia. Monday evening includes
two events, entitled, “Integrated Circuits in an Interconnected World” and “The Path to Sustainable IC
Ecosystems”

On Tuesday, February 21st, there are five parallel technical sessions, both morning and afternoon. Book
Displays and Author Interviews, will also include a second Demonstration Session. Tuesday evening includes
two events, entitled: “The Smartest Designer in The Universe, Post-Pandemic!” and “What will be the
Essential Skills for IC Designers in the Next Decade?”

On Wednesday, February 22nd, there will be five parallel technical sessions, both morning and afternoon,
followed by Author Interviews.

On Thursday, February 23rd, ISSCC offers a choice of five all-day events:

• A Short Course entitled:
“Principles of Quantum Computing and the Application of Cryoelectronics
to Qubit Control and Readout ”
• Four Advanced-Circuit-Design Forums entitled:
“Advancing Technologies for Extended Reality (XR) to Make the “Metaverse” Possible”
“Extreme Data Converters and Their Peripherals ”
“The Future of Heterogeneous Multi-Core Architectures for AI and Other Specialized Processing”
“Advanced Circuits and Technologies for Wearable and Implantable Devices”

This year, again, there is an option which allows an attendee to sample parts of all 5 Thursday offerings.
Registration for educational events on Sunday and Thursday will be filled on a first-come first-served basis.
Use of the ISSCC Web-Registration Site (http://www.isscc.org) is strongly encouraged. Registrants will be
provided with immediate confirmation on registration for the Conference, Tutorials, Forums, and the Short
Course.

Need Additional Information? Go to: www.isscc.org

 Table of Contents
Tutorials....................................................................................................................................5-10
FORUMS
F1 Transceivers for Exascale: Towards Tbps/mm and sub-pJ/bit.............................................................11
F2 The Power Behind Electrical Vehicles –Accelerating the Future of Automotive Technology.............12

F3 Efficient Wireless Power Amplification and Linearization....................................................................13

EVENING EVENTS
EE Mentoring Session/Networking Bingo Event.......................................................................................14
EE1 Student Research Preview: Short Presentations with Poster Session.................................................14
PAPER SESSIONS
1 Plenary..........................................................................................................................................15-16
2 Digital Processors..............................................................................................................................17
3 Amplifiers and Oscillators..................................................................................................................18
4 Frequency Synthesizers......................................................................................................................19
5 Image Sensors...................................................................................................................................20
6 Advanced Wireline Links and Techniques......................................................................................21
Demonstration Session 1.......................................................................................................................22
EVENING EVENTS
EE2 Integrated Circuits in an Interconnected World......................................................................................23
EE3 The Path to Sustainable IC Ecosystems....................................................................................................24
PAPER SESSIONS
7 SRAM Compute-In-Memory.....................................................................................................................25
8 GHz-to-Millimeter Wave Frequency Generation.......................................................................................26
9 Highlighted Chip Releases: Digital and Machine Learning Processors.....................................................26
10 Pipelined and Noise-Shaping ADCs..........................................................................................................27
11 USB and Compute Power Delivery............................................................................................................28
12 High Performance Optical Receivers........................................................................................................29
13 Ideas for the Future...........................................................................................................................29
14 Digital Techniques for Clocking and Power Management......................................................................30
15 IOT & Security.....................................................................................................................................30
16 Efficient Compute-In-Memory Based Processors for ML.........................................................................31
17 High-Speed Data Converters................................................................................................................32
18 mm-Wave & sub-THz for Wireless and Sensing.......................................................................................33
19 5G and Satcom: Receivers and Transmitters........................................................................................33
20 GaN Power Conversion...........................................................................................................................34
21 Emerging Sensing Systems and IOT.........................................................................................................35
Conference Timetable....................................................................................................................36-37
Demonstration Session 2........................................................................................................................38
EVENING EVENTS
EE4 The Smartest Designer in The Universe, Post-Pandemic!........................................................................39
EE5 What will be the Essential Skills for IC Designers in the Next Decade?....................................................39
PAPER SESSIONS
22 Heterogenous ML Accelerators................................................................................................................40
23 Analog Sensor Interfaces..........................................................................................................................41
24 THz Signal Generation..............................................................................................................................42
25 RF Transceiver Building Blocks.................................................................................................................42
26 Display and User Interaction Technologies..................................................................................43
27 Innovations from Outside the (ISSCC) Box..............................................................................................43
28 High-Density Memories and High-Speed Interface..................................................................................44
29 Digital Accelerators and Circuit Techniques..............................................................................................45
30 Power Management Techniques...............................................................................................................46
31 Energy-Efficient Radios for UWB, BMI, and IoT Systems.........................................................................47
32 Intelligent Biomedical Circuits and Systems.............................................................................................48
33 Non-Volatile Memory and Compute-In-Memory......................................................................................49
34 Cryo-CMOS for Quantum Computing.......................................................................................................50
SHORT COURSE
SC Principles of Quantum Computing and the Application...................................................................51-52
of Cryoelectronics to Qubit Control and Readout
FORUMS
F4 Advancing Technologies for Extended Reality (XR) to Make the “Metaverse” Possible............................53
F5 Extreme Data Converters and Their Peripherals.......................................................................................54
F6 The Future of Heterogeneous Multi-Core Architectures for AI and Other Specialized Processing......55
F7 Advanced Circuits and Technologies for Wearable and Implantable Devices........................................56
Committees.............................................................................................................57-65
Conference Information..............................................................................................................66-69
Conference Space Layout......................................................................................................................70

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CIRCUIT INSIGHTS Saturday February 18th, 7:30 AM

ISSCC 2023 Circuit Insights

Organizer/Moderator: Ali Sheikholeslami, University of Toronto, Toronto, Canada

ISSCC Education Chair

ISSCC 2023 offers the second edition of its Circuit Insights on Saturday, Feb. 18, 2023,
7:30am -12:00pm PST. Like its initial debut in 2022, this event is targeting third-year undergraduate
students and starting graduate students in the area of circuit design, but may be of interest to new
circuit design engineers as well. The event will be held in person for a small audience of 50 students
(by invitation only) at the ISSCC venue at the Marriott Hotel in San Francisco, and will be broadcast
live via YouTube/Zoom worldwide. This event is free of charge but requires registration through
isscc.org/insights.

The event consists of four 45-minute talks on fundamentals of Circuit Design, each to be followed
by a 15-minute Q&A Session, with a 30-minute break after the second talk. The Q&A session will
be interactive, entertaining questions from the in-person as well as the online attendees.

Agenda
Time Topic
7:00 AM Light Breakfast
7:30 AM Opening Remarks
Ali Sheikholeslami, Circuit Insights Organizer/Moderator
7:35 AM Welcoming Remarks
Eugenio Cantatore, ISSCC Conference Chair
John Long, SSCS President
7:40 AM The CMOS Latch
Asad Abidi, University of California, Los Angeles, CA
8:25 AM Interactive Q & A
8:40 AM The Art of Linear Analysis for Analog Circuits
Jaeha Kim, Seoul National University, Korea
9:25 AM Interactive Q & A
9:40 AM Break
10:10 AM The Basics of Low Noise Amplifiers
Rabia Yazicigil Kirby, Boston University, MA
10:55 AM Interactive Q & A
11:10 AM The Basics of Analog-to-Digital Converters
Maurits Ortmanns, University of Ulm, Germany
11:55 AM Interactive Q & A
12:10 PM Attendees Feedback
12:20 PM Networking Lunch
1:30 PM Conclusion

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TUTORIALS Sunday February 19th
There are a total of 12 tutorials this year on 12 different topics. Each tutorial, selected through a competitive
process within each subcommittee of the ISSCC, presents the basic concepts and working principles of a
single topic of broad interest. The tutorials are intended for non-experts, graduate students, and practicing
engineers who wish to explore and understand a new topic. Tutorial registration bundles access to all 12 of
the tutorials. Participants are asked to select between the option for only on-demand access to the tutorials
(provided ahead of the conference) or the option to additionally attend a full-day live Q&A and networking
session with the presenters during the conference, at no additional charge. The coordinators for the 2023
ISSCC Tutorials are (in the same order as the tutorials): Jens Anders (T1), Yan Lu (T2), Shahrzad Naraghi
(T3), Chia-Hsiang Yang (T4), Eric J.-W. Fang (T5), Leonardo Gasparini (T6), Yih Wang (T7), Jeff Walling
(T8), Noriyuki Miura (T9), Bodhisatwa Sadhu (T10), Byungsub Kim (T11), Jae-Sun Seo (T12).
Naveen Verma
ISSCC Tutorials Chair

The presentations of all 12 tutorials will be available online, on-demand, as of:

Friday, Feb. 10, 2023, 5:00pm, PST
Live Q&A in person for the tutorials:
Sunday Feb. 19, 2023

10:00 AM - Live Q&A in person - February 19

T1: Fundamentals of Frequency References
Danielle Griffith, Texas Instruments, Dallas, TX

Frequency references are a fundamental building block in a vast array of electronic systems. This tutorial
will introduce several types of oscillators commonly used as frequency references, including crystal and
MEMS oscillators as well as fully-integrated oscillators. Classical circuit architectures and recent advances
will be shown. The tutorial will focus on how system-level requirements influence the circuit-level
architecture, the required frequency accuracy, power consumption, and other design targets. Design
tradeoffs will be described for each oscillator type. At the end of this tutorial, attendees will have a solid
understanding of frequency reference specifications, common oscillator architectures, tradeoffs, and recent
innovations in the field.

Danielle Griffith received the B.S.E.E. and M.Eng. degrees from the Massachusetts Institute of Technology.
She is currently a Fellow at Texas Instruments in Dallas, Texas. Her areas of expertise are circuits and
architectures for efficient wireless systems, low power oscillators, and MEMS circuitry. She has published
a book chapter and >50 papers, and holds 22 issued US patents. Danielle has presented at numerous
conference tutorial and workshop sessions.  She has been a TPC member for the RFIC, ISSCC, and VLSI
conferences.  She is a senior member of the IEEE, an associate editor of the IEEE JSSC, and a Distinguished
Lecturer of the SSCS.

10:20 AM - Live Q&A in person - February 19

T2: Bridging RF and Power: An Introduction to Envelope Tracking Systems
and Building Blocks
Ji-Seon Paek, Pusan National University, Pusan, Korea

Envelope tracking (ET) is a well-established power-management technique to improve the power efficiency
of RF power amplifiers. This tutorial covers the principles of envelope-tracking operation, and the design of
building blocks under ET-system link budget considerations. It develops the understanding of standard-
specific system specifications, required by 3GPP and IEEE standards, to enable optimal design of each
building block. Based on the understanding, various supply-modulator (SM) structures and power-
management circuit techniques will be reviewed, which can efficiently power RF power amplifiers while
meeting the requirements of wireless communication standards.

Jiseon Paek received the B.S., M.S., and Ph.D. degrees in electrical engineering from the Korea Advanced
Institute of Science and Technology (KAIST), Daejeon, Korea, in 2004, 2006, and 2011, respectively. Since
2011, he has been with Samsung Electronics, where he leads various projects developing wireless RF
transceivers, envelope tracking (ET) ICs, and fully integrated power ICs for mobile handset applications.
Since 2022, he has been an Associate Professor in the Department of Electronics Engineering at Pusan
National University (PNU), Korea. He is now serving on the power management sub-committee of ISSCC.

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TUTORIALS Sunday February 19th
10:40 AM - Live Q&A in person - February 19
T3: Fundamentals of Data Converters
Yun Chiu, University of Texas at Dallas, Richardson, TX

A refreshing review of fundamental data-conversion principles and circuit techniques, ranging from the
concepts of sampling and quantization, to flash, pipeline and SAR architectures, to common circuit building
blocks, to time- and frequency-domain measurement techniques of converters, will be presented in this
tutorial. An emphasis will be placed on performance robustness, digital correctability, and calibration in
advanced process nodes. The tutorial will wrap up with a historic remark on and a future perspective of the
ADC Figure-of-Merits.

Yun Chiu is an Erik Jonsson Distinguished Professor of the ECE Department of the University of Texas at
Dallas, where he directs the Analog and Mixed-Signal Lab at the Texas Analog Center of Excellence. His
industry experience includes working as a Senior Staff Member in a Silicon Valley startup in the late 90s
and co-founding Formula Microelectronics in 2015 during his sabbatical leave. He has served on the
technical program committees of VLSI-C, CICC, and A-SSCC. He is now serving on the data converter
subcommittee of ISSCC. He received his Ph.D. from UC Berkeley.

11:00 AM - Live Q&A in person - February 19

T4: Automotive System Design
Sugako Otani, Renesas Electronics, Tokyo, Japan

The automotive industry is in the midst of a significant transformation. “CASE: Connected, Autonomous,
Shared & Service, Electric” has been advocated as a trend. Along with this trend, automotive E/E
(Electrical/Electronic) architecture has rapidly progressed toward ECU (Electronic Control Unit ) integration
and centralization in the autonomous driving era. The tutorial introduces automotive system design and key
technologies of LSI devices, including processors for advanced vehicle control and cognitive/judgment
processing. Multiple safety mechanisms for automotive functional safety are also covered.

Sugako Otani is a system and processor architect at Renesas Electronics Corporation. Her current research
focuses on application-specific architectures, ranging from IoT devices to automotive. She joined Mitsubishi
Electric Corporation, Japan, in 1995 after receiving an M.S. in physics from Waseda University, Tokyo. She
received a Ph.D. in Electrical Engineering and Computer Science from Kanazawa University in 2015. From
2005 to 2006, she was a Visiting Scholar at Stanford University. She is a committee member of ISSCC,
VLSI Symposium, ESSCIRC, and Cool Chips. Since 2019, she has been a Visiting Associate Professor at
Nagoya University, Japan.

11:20 AM - Live Q&A in person - February 19

T5: All-Digital PLLs:
From Fundamental Concepts to Future Trends
Akihide Sai, Toshiba, Kawasaki, Japan

Frequency synthesis has become ubiquitous in chip designs for clocking, RF, and data sampling. Traditional
analog PLLs have moved to digital implementations, for area, power, and technology portability. This tutorial
describes the evolution of all-digital PLLs, from the basic digitization of oscillator control at integer ratios,
to low-noise flexible fractional-N frequency synthesis with digital-to-time converters (DTCs). The evolution
of two noise-critical blocks is described: time-to-digital converters (TDCs) and fractional dividers. This
includes voltage-based TDCs, such as time amplifiers and successive-approximation-register (SAR)
architectures, and various DTCs for fractional-divider noise reduction. It concludes with architectures at the
limits of noise and size, namely bang-bang TDCs, and looks at future digital PLL trends. The presentation
emphasizes key considerations for digital systems, including fast dynamic frequency scaling (DFS), fine
resolution, and noise mitigation.

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TUTORIALS Sunday February 19th
Akihide Sai received the B.E. and M.E. degrees from Waseda University, Tokyo, Japan, in 2002 and 2004,
respectively. In 2004, he joined the Corporate Research and Development Center, Toshiba Corporation,
Kawasaki, Japan. From 2004 to 2015, he has been engaged in the research and development of low-power
transceivers and digital/analog phase-locked loops (PLLs). Since 2016, he has been a senior research
scientist and a team leader of mixed-signal circuits for automobile LiDAR SoCs. He contributed to high-
performance mixed-signal circuit and LiDAR system projects and co-authored more than 20 technical papers
and patents.

11:40 AM - Live Q&A in person - February 19

T6: Solid-State CMOS LiDAR Sensors
Seong-Jin Kim, Ulsan National Institute of Science and Technology, Ulsan, Korea

This tutorial will present the technologies behind single-photon avalanche-diode (SPAD)-based solid-state
CMOS LiDAR sensors that have emerged to realize level-5 automotive vehicles and the metaverse AR/VR in
mobile devices. It will begin with the fundamentals of direct and indirect time-of-flight (ToF) techniques,
followed by structures and operating principles of three key building blocks: SPAD devices, time-to-digital
converters (TDCs), and signal-processing units for histogram derivation. The tutorial will finally introduce
the recent development of on-chip histogramming TDCs with some state-of-the-art examples.

Seong-Jin Kim received a Ph.D. degree from KAIST, Daejeon, South Korea, in 2008 and joined the Samsung
Advanced Institute of Technology to develop 3D imagers. From 2012 to 2015, he was with the Institute of
Microelectronics, A*STAR, Singapore, where he was involved in designing various sensing systems. He is
currently an associate professor at Ulsan National Institute of Science and Technology, Ulsan, South Korea,
and a co-founder of SolidVUE, a LiDAR startup company in South Korea. His current research interests
include high-performance imaging devices, LiDAR systems, and biomedical interface circuits and systems.

1:00 PM - Live Q&A in person - February 19

T7: Fundamentals of Ultra-Low Voltage
Embedded Memory Design
Eric Karl, Intel, Portland, OR

To meet the energy efficiency demands of future applications, system-on-chip (SoC) designs continue to
march towards ultra-low-voltage operation. This tutorial will address the fundamental challenges for
embedded memory operation at low voltages in advanced process technologies, and cover single and multi-
port SRAM, logic flip-flop, logic latch arrays, and eFuse technologies, prevalent in embedded design use.
Memory assist circuits, repair, error correction, multi-VCC array design, clocking and min-delay design
strategies relevant to enabling ultra-low and near-threshold system operation will be explored. System
designers will walk away with a stronger understanding of how to better navigate embedded memory usage
in ultra-low-voltage designs.

Eric Karl is an Intel Fellow, Director of Advanced Design and Director of Embedded Memory Technology
and Circuits. Karl leads the Advanced Design group in Intel’s Technology Development organization, where
he is responsible for standard-cell library architecture, memory and analog circuit technologies employed
by all designers on Intel technology. Karl leads teams at Intel responsible for design technology co-
optimization and develops a wide-range of circuits for early development test vehicles to enable technology
development. Karl played a lead role in Intel’s embedded memory technology development and the transition
to FinFET technology in 2012. Karl holds doctoral, master’s and bachelor’s degrees in electrical engineering
from the University of Michigan, Ann Arbor. He has published over 30 peer-reviewed technical papers, holds
numerous patents and is currently serving on the memory subcommittee of the International Solid-State
Circuits Conference (ISSCC).

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TUTORIALS Sunday February 19th
1:20 PM - Live Q&A in person - February 19
T8: Role of Current-Mode Passive Mixers
and N-Path Filters in RF Receivers
Masoud Babaie, Delft University of Technology, Delft, The Netherlands

Modern multimode sub-6GHz receivers heavily employ current-mode passive mixers and N-path filters to
simultaneously satisfy the noise requirements and deal with large in-band and out-of-band interferences.
After a brief description of a typical receiver structure and its performance matrix, the operation of current-
mode receivers and N-path filters will be explained in detail. In particular, this tutorial will focus on the
impedance transformation property and reciprocal mixing of those structures. The tutorial will then cover
architectures and applications exploiting N-path filters, such as high-order programmable bandpass filters,
magnetic-free circulators, mixer-first, and low-noise trans-impedance amplifier (LNTA)-based receivers.

Masoud Babaie is a associate professor at the Delft University of Technology, The Netherlands. His research
interests include RF/millimeter-wave integrated circuits and systems for wireless communications. He has
authored or co-authored one book, three book chapters, 11 patents, and over 80 technical articles. Dr.
Babaie serves on the technical program committee of the IEEE ISSCC and is the co-chair for the emerging
computing devices and circuits subcommittee of IEEE ESSCIRC. He was a co-recipient of the 2019 IEEE
ISSCC demonstration-session certificate of recognition and the 2020 IEEE ISSCC Jan Van Vessem Award
for outstanding European paper. He also received the Veni grant from the Netherlands Organization for
Scientific Research (NWO) in 2019.

1:40 PM - Live Q&A in person - February 19

T9: Physical-Layer Security for Latency- and Energy-Constrained
Integrated Systems
Rabia Tugce Yazicigil, Boston University, Boston, MA
The boom of connected IoT nodes and ubiquity of wireless communications are projected to increase
wireless data traffic by several orders of magnitude in the near future. While these future scalable networks
support increasing numbers of wireless devices utilizing the EM spectrum, ensuring the security of wireless
communications and sensing is also a critical requirement under tight resource constraints. The physical
layer has increasingly become the target of attacks by exploiting hardware weaknesses, e.g., side-channel
attacks/fault injection/direct probing, and signal properties, e.g., time, frequency, and modulation
characteristics. This tutorial introduces common security vulnerabilities within wireless systems such as
jamming, eavesdropping, counterfeiting and spoofing, followed by physical-layer countermeasures, while
assessing the trade-offs between performance and security. It examines recent research directions, e.g.,
secure spatio-temporal modulated arrays, temporal swapping of decomposed constellations, RF
fingerprinting, bit-level frequency hopping, and integrated physical-attack-detection (anomaly-detection)
sensors, and reaction circuits, and finally discusses research opportunities looking forward.

Rabia Yazicigil is an Assistant Professor in the ECE Department at Boston University and a Visiting Scholar
at MIT. She was a Postdoctoral Associate at MIT and received her PhD degree from Columbia University in
2016. Her research interests lie at the interface of integrated circuits, signal processing, security, bio-sensing,
and wireless communications to innovate system-level solutions for future energy-constrained applications.
She has received numerous awards, including the “Electrical Engineering Collaborative Research Award”
for her PhD research (2016), second place at the Bell Labs Future X Days Student Research Competition
(2015), and 2014 Millman Teaching Assistant Award of Columbia University. She served as the Vice Chair
of the Rising Stars 2020 workshop at the ISSCC. She is a member of the ISSCC and ESSCIRC TPCs and
2015 MIT EECS Rising Stars cohort.

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TUTORIALS Sunday February 19th
2:00 PM - Live Q&A in person - February 19
T10: The Art of mm-Wave Design and Layout
Shahriar Shahramian, Nokia – Bell Labs, New Providence, NJ
We live in the golden age of mm-wave ASIC design! With the rise of 5G networks & 6G research, a massive
push for commercialization of mm-wave integrated circuits is underway. This tutorial explores the hidden
impairments that are often overlooked or difficult to locate in mm-wave layouts and interconnects. Using
real-life fabricated circuit blocks operating up to and beyond D-band (170GHz), as well as optical circuits
operating beyond 100Gb/s, the tutorial will explore layout challenges and impairments that can adversely
affect the circuit performance. After modeling these elements, simulations demonstrate the impact of the
parasitics on bandwidth, center frequency, stability, and noise figure. Using simple and quick modeling
techniques, the designers can incorporate effects of various layout parasitics. Furthermore, mm-wave
techniques at the chip level are explored from ground planes to flip-chip bumps. Finally, going beyond the
boundaries of integrated circuits, co-design techniques will be explored to carry mm-wave signals into
packages, printed circuit boards, and antennas.

Shahriar Shahramian received the Ph.D. degree from University of Toronto in 2010 where he focused on
the design of mm-wave data converters and transceivers. Dr. Shahramian has been with Bell Laboratories
– Nokia since 2009 and is currently the Director of the Communication & Sensing ASICs Research Group.
His research focus includes the design of mm-wave wireless and wireline integrated circuits and systems.
Dr. Shahramian is a Bell Labs Fellow and leads the design and architecture of several state-of-the-art ASICs
for optical coherent and wireless backhaul products. Shahriar serves as the chair of the mm-Wave & THz
subcommittee of IEEE BCICTS, as well as chair of mm-Wave SoCs at IEEE RFIC, and is a member of the
technical program committee of IEEE ISSCC. He has also served as the Guest Editor of the IEEE Journal of
Solid-State Circuits (JSSC). Dr. Shahramian has been the recipient of an Ontario Graduate Scholarship and
a University of Toronto Fellowship. He also received the best paper awards at the CSICS Symposium in
2005 and 2015, the RFIC Symposium in 2015 and 2020 and ISSCC in 2018. He was the recipient of the
IEEE MTT Young Engineer Award in 2020. He holds an Adjunct Associate Professor position at Columbia
University, has received several teaching awards and is the founder and host of The Signal Path educational
video series. Dr. Shahramian has presented short courses and workshops at the IEEE CSICS, BCTM, BCICTS,
RFIC/IMS and ISSCC conferences.

2:20 PM - Live Q&A in person - February 19

T11: Digital Equalization and Timing Recovery Techniques for ADC-DSP
Based High-Speed Links
Masum Hossain, University of Alberta, Edmonton, Canada
As we move beyond 200Gb/s, equalization and timing-recovery techniques have evolved drastically, with
ISI and latency playing a significant role in DSP-based receivers, especially with multi-level signaling. This
tutorial aims at bridging the gap between well-understood analog/mixed-signal solutions and today’s DSP-
based solutions. Starting from traditional analog architectures, the tutorial will walk through the evolution
toward today’s DSP-based equalization and timing recovery. The tutorial will include digital equalization,
timing recovery, their interaction, and interdependency. MLSD, a recent trend in DSP-based equalization
will also be covered.

Masum Hossain received the B.Sc. degree from the Bangladesh University of Engineering and Technology,
Dhaka, Bangladesh, in 2002, the M.Sc. degree from Queen’s University, Kingston, ON, Canada, in 2005, and
the Ph.D. degree from the University of Toronto, Toronto, ON, in 2010. From 2008 to 2010, he was with the
Analog and Mixed-Signal Division, Gennum Corporation, Burlington, ON. From 2010 to 2012 he was with
Rambus Laboratory, Sunnyvale, CA, USA, as a Senior Member of Technical Staff. In 2013, he joined the
Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada. Dr.
Hossain was a recipient of the Best Student Paper Award at the 2008 IEEE Custom Integrated Circuits
Conference and the Analog Device’s Outstanding Student Designer Award in 2010. In 2021 he received EPS
society nominated best paper award in IEEE Transaction in Components, Packaging and Manufacturing.

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TUTORIALS Sunday February 19th
2:40 PM - Live Q&A in person - February 19
T12: Extending Processor Cores for Machine Learning
Luca Benini, ETH Zürich and UNIBO, Zurich, Switzerland
Many low-cost, ultra-low-power applications require flexibility and cannot afford the large silicon budget of
a specialized machine-learning/artificial-intelligence (ML/AI) accelerator. The tutorial will review the key
ideas and approaches to extend the instruction-set architecture (ISA) and microarchitecture, as well as the
digital design of processor cores to achieve high efficiency for ML. ISA extension examples (e.g. ARM’s
Helium and RISC-V extensions) will be analyzed, along with implementation challenges and solutions,
drawing insights from various silicon-proven RISC-V cores.

Luca Benini holds the Chair of Digital Circuits and Systems at ETH Zürich and is a Full Professor at Università
di Bologna. He served as chief architect in STmicroelectronics, France, from 2009-2012. He received a PhD
from Stanford University. His research interests are in energy-efficient parallel computing systems, smart
sensing micro-systems and machine learning hardware. He is a Fellow of the IEEE, Fellow of the ACM, and
a member of the Academia Europaea. He is the recipient of the 2016 IEEE CAS Mac Van Valkenburg award,
the 2019 IEEE TCAD Donald O. Pederson Best Paper Award and the ACM/IEEE A. Richard Newton Award
2020.

10
FORUM 1 Sunday February 19th, 8:00 AM
Transceivers for Exascale: Towards Tbps/mm and sub-pJ/bit
Organizers: Tamer Ali, Mediatek, Irvine, CA
Didem Turker Melek, Cadence Design Systems, San Jose, CA

Committee: Munehiko Nagatani, NTT, Atsugi, Japan

Thomas Toifl, Cisco Systems, Wallisellen, Switzerland

Champions: Franz Dielacher, Villach, Austria

Bill Redman-White, HiLight Semiconductor, Southampton, United Kingdom
Connectivity is a key enabler of exascale computing systems. The forum covers electrical and optical
transceivers used throughout these systems, from short die-to-die interconnect to long-distance network
interfaces. In addition to state-of-the-art standard and proprietary interfaces, the forum also covers emerging
and future works that will significantly increase interface bandwidth and power efficiency, and the design
challenges of building high-performance connectivity chips.

Agenda

Time Topic
8:00 AM Breakfast
8:15 AM Introduction
Tamer Ali, Mediatek, Irvine, CA
8:25 AM High-Density, Energy-Efficient Interconnect Technologies Inside
Supercomputers
Yuichiro Ajima, Fujitsu, Kawasaki, Japan
9:10 AM Bandwidth-Density- and Energy-Optimized Die-to-Die Interfaces
Elad Alon, Blue Cheetah, Sunnyvale, CA
9:55 AM Break
10:10 AM Advanced Packaging and 3D-IC Interconnections
Shenggao Li, TSMC, San Jose, CA
10:55 AM PCIe Rising: The Journey to 64Gb/s and 128Gb/s
Marc Loinaz, Cadence, San Jose, CA
11:40 AM Circuit Designs for 200+Gb/s Transceivers
Jihwan Kim, Intel, Hillsboro, OR
12:25 PM Lunch
1:40 PM Electronics and Photonics for Beyond 200G Capable Transceivers
Peter Ossieur, imec, Ghent, Belgium
2:25 PM Direct-drive Optical I/O using Monolithic Silicon Photonics Integration
Christoph Schulien, Ranovus, Nuremberg, Germany
3:10 PM Break
3:25 PM Advancements in High-Speed Electrical Terahertz Waveguide
Interconnects
Hyeon-Min Bae, KAIST/Point2-technology, Daejeon, Korea
4:10 PM Realizing Petabit/s IO and sub-pJ/bit System-Wide Communication
with Silicon Photonics
Keren Bergman, Columbia University, New York, NY
4:55 PM Closing Remarks

11
FORUM 2 Sunday February 19th, 8:00 AM
The Power Behind Electrical Vehicles –
Accelerating the Future of Automotive Technology
Organizer: Min Chen, Innoscience America, Santa Clara, CA

Committee: Kousuke Miyaji, Shinshu University, Nagano, Japan

Frank Praemassing, Infineon Technologies, Villach, Austria
Marco Berkhout, Goodix Technology, Nijmegen, The Netherlands

Champion: Bruce Rae, STMicroelectronics, Edinburgh, United Kingdom

Vehicle electrification in EV/HEV is demanding unprecedented power electronic devices, circuits, and
systems. This forum provides a comprehensive overview of the mega trend and design challenges on all
levels, specifically related to battery protection and management systems, drivetrain topologies & systems,
power semiconductor devices and modules, supplemental power electronics, automotive sensors, PMIC,
and LED drivers.

Agenda

Time Topic
8:00 AM Breakfast
8:15 AM Introduction
Min Chen, Innoscience America, Santa Clara, CA
8:25 AM Mega Trends in Vehicle Electrification and Future EV Technology
Francesco Gennaro, STMicroelectronics, Catania, Italy
9:15 AM The Battery System is the Core of Future Mobility
Patrick Leteinturier, Infineon Technologies, Neubiberg, Germany
10:05 AM Break
10:20 AM Trends and Research Cases of 800V Motor Drive Circuits for Battery
Electric Vehicle
Tomonori Kimura, MIRISE Technologies, Nisshin, Japan
11:10 AM The Opportunity from GaN and for GaN in Cars
Alex Lidow, EPC, El Segundo, CA
12:00 PM Lunch
1:20 PM Power Electronics Components: MCU, Isolated Gate Driver,
Isolated Power Supply, and Sensors
Shunichi Kaeriyama, Renesas Electronics, Kodaira, Japan
2:10 PM Long-Range High-Resolution LiDAR Technology
Katsuyuki Kimura, Toshiba, Kawasaki, Japan
3:00 PM Break
3:15 PM Smart Power ASICs: System Definer and Not Just Components
Tamer Sinanoglu, Bosch, Reutlingen, Germany
4:05 PM High-Efficiency LED Drivers for Automotive Applications
Hoi Lee, University of Texas at Dallas, Dallas, Texas
4:55 PM Closing Remarks

12
FORUM 3 Sunday February 19th, 8:00 AM
Efficient Wireless Power Amplification and Linearization
Organizers: James Buckwalter, University of California, Santa Barbara, Santa Barbara, CA
Jeff Walling, Virginia Tech, Blacksburg, VA

Committee: Hongtao Xu, Fudan University, Shanghai, China

Byung-Wook Min, Yonsei University, Seoul, Korea
Giuseppe Gramegna, imec, Leuven, Belgium
Wu-Hsin Chen, Qualcomm, San Diego, CA

Champion: Andreia Cathelin, STMicroelectronics, Crolles Cedex, France

This forum reviews the state-of-the-art for power amplification and digital predistortion technologies from
RF to mm-wave frequencies with applications to cellular, wifi, and satellite communications. Speakers are
chosen to cover advances in CMOS/BiCMOS as well as GaAs/GaN process technologies that
comprehensively connect underlying devices, circuits, and system architectures. The forum will also cover
the emerging capabilities of digital signal processing for analog and digital PAs in RF bands and mm-wave
arrays.

Agenda
Time Topic
8:00 AM Breakfast
8:15 AM Introduction
James Buckwalter, University of California, Santa Barbara,
Santa Barbara, CA
8:25 AM Emerging Device Technologies for RF/mm-Wave FEM
Nicholas Comfoltey, GlobalFoundries, San Diego, CA
9:15 AM Linear GaAs Technologies for Mobile Power Amplifiers
David Danzilio, WIN Semiconductors, Taoyuan, Taiwan
10:05 AM Break
10:20 AM Sub-8GHz Base Station Power Amplifiers and Linearization
Rui Hou, Ericsson, Stockholm, Sweden
11:10 AM Advances in Highly Efficient All-Digital CMOS Transmitters for
Wide Bandwidth Wireless Application
Ofir Degani, Intel, Haifa, Israel
12:15 PM Lunch
1:20 PM Single Transformer-Based Compact Doherty PA for 5G RFICs and
Base-Stations
Hyun-Chul Park, Samsung, Hwaseong, Korea
2:10 PM Digital Predistortion (DPD) for High-Efficiency 5G Radio Units
Zohaib Mahmood, Maxlinear, Waltham, MA
3:00 PM Break
3:15 PM Digital Pre-Distortion for Large-Scale mm-Wave Arrays
Harish Krishnaswamy, Sivers Semiconductors, Chatham, NJ
4:05 PM Machine-Learning-Assisted Approaches for Wideband DPD
Anding Zhu, University College Dublin, Dublin, Ireland
4:55 PM Closing Remarks

13
SPECIAL EVENTS Sunday February 19th
Mentoring Session/Networking Bingo Event
(Open to all Attendees)
3:00 - 5:00 PM

Women in Circuits (WiC) together with ISSCC will be holding a networking and mentoring session on
Sunday afternoon. Distinguished panelists from the “Integrated Circuits in an Interconnected World”
panel, WiC members, and other participants will play getting-to-know-you bingo to promote
engagement between various members of the community. This will give participants the chance to
network and mingle with people across a spectrum of seniority in the field in a casual setting. This
event is open to all ISSCC attendees and the public.

EE1: Student Research Preview (SRP)

8:00 PM
The Student Research Preview (SRP) will highlight selected student research projects in progress. The
SRP consists a number of ninety-second presentations followed by a Poster Session, by graduate
students from around the world, which have been selected on the basis of a short submission
concerning their on-going research. Selection is based on the technical quality and innovation of the
work. This year, the SRP will be presented in three theme sections: 1) RF and Analog, 2) Energy-
Efficient Circuits and Systems, and 3) Compute-in-Memory (CIM), Artificial Intelligence (AI) and
Security.

The SRP will include an inspirational lecture by Professor Mark Horowitz (Stanford University). SRP
begins at 8:00 pm on Sunday, February 19th. It is open to all ISSCC registrants.

SRP ORGANIZING COMMITTEE

Co-Chair: Jerald Yoo, National University of Singapore, Singapore
Co-Chair: Mondira (Mandy) Pant, Intel, MA
Advisor: Anantha Chandrakasan, MIT, MA
Advisor: Jan Van der Spiegel, University of Pennsylvania, Philadelphia, PA
Media/Publications: Laura Fujino, University of Toronto, Toronto, Canada
A/V: Trudy Stetzler, Halliburton, Houston, TX

COMMITTEE MEMBERS
Utsav Banerjee, IISC, India Noriyuki Miura, Osaka University, Japan
Hsin-Shu Chen, National Taiwan University, Taiwan Phillip Nadeau, Analog Devices, MA
Po-Hung Chen, National Chiao Tung University,Taiwan Mondira Pant, Intel, MA
Zeynep Deniz, IBM, NY Negar Reiskarimian, Massachusetts Institute
Sijun Du, Delft University of Technology, of Technology, MA
The Netherlands Atsushi Shirane, Tokyo Institute of Technology, Japan
Antoine Frappe, University of Lille, France Mahsa Shoaran, EPFL, Switzerland
Hao Gao, Eindhoven University of Technology, Yildiz Sinangil, Apple, CA
The Netherlands Mahmut Sinangil, Nvidia, CA
Preet Garcha, Texas Instruments, TX Filip Tavernier, KU Leuven, Belgium
Minkyu Je, KAIST, Korea Chia-Hsiang Yang, National Taiwan University, Taiwan
Matthias Kuhl, University of Freiburg, Germany Lita Yang, Meta, CA
Jaydeep Kulkarni, University of Texas at Austin, TX Rabia Tugce Yazicigil, Boston University, MA
Jiamin Li, Southern University of Science Jerald Yoo, National University of Singapore,
and Technology, China Singapore
Carolina Mora Lopez, imec, Belgium Milin Zhang, Tsinghua University, China

14
SESSION 1 Monday February 20th, 8:30 AM
Plenary Session — Invited Papers
Chair: Eugenio Cantatore, Eindhoven University of Technology, Eindhoven,
The Netherlands
ISSCC Conference Chair

Associate Chair: Piet Wambacq, imec, Heverlee, Belgium

ISSCC International Technical Program Chair

FORMAL OPENING OF THE CONFERENCE 8:30 AM

1.1 Innovation For the Next Decade of Compute Efficiency 8:45 AM

Lisa Su, Chair and Chief Executive Officer, AMD,
Austin, TX

Although traditional scaling has slowed over the past decade, we have made tremendous progress as an
industry with new approaches including chiplet-based architectures, domain-specific accelerators, and
advanced packaging technologies which have enabled major milestones including the first exascale
supercomputers. As we look into the future, we need to accelerate the pace of innovation to drive the next
decade of advancement in high-performance computing. By far, the largest limiting factor to delivering
continued compounded growth in computation power is energy efficiency. In this paper, we highlight a
holistic strategy for accelerating innovation in energy efficiency required for next-generation high-
performance computing and ultimately achieving zettascale performance. These approaches will be built
on continued innovation in process technologies, modular chiplet architectures, and advanced packaging.
Fully meeting the challenge will require new dimensions of improvement through extending domain-specific
architectures to accelerate core algorithms in combination with wide-scale deployment of AI across all
aspects of the system from transistors to software.

1.2 Shape the World with Mixed-Signal Integrated 9:20 AM

Circuits - Past, Present, and Future
Akira Matsuzawa, Professor Emeritus of Tokyo Institute of Technology
and CEO of Tech Idea, Kawasaki, Japan

The past 50 years has been an era in which analog equipment has been replaced by digital counterparts.
Audio, TV, video, camcorder, camera, recording, wired connection, and wireless communication have been
subject to digitization. The digitization of these devices and systems was due to the technological shift from
bipolar to CMOS, and to the development of logic and memory circuits supported by scaling laws. In
addition, design innovation in mixed-signal integrated circuits such as ADCs and DACs has shown to be
indispensable. This talk will look back on the digitization of equipment and the mixed-signal integrated circuit
technology that contributed to it. Further, we will look forward to future applications and developments.

ISSCC, SSCS, IEEE AWARD PRESENTATIONS 9:55 AM

BREAK 10:20 AM

15
SESSION 1 Monday February 20th, 10:40 AM
1.3 EU Chips Act Drives Pan-European Full-Stack 10:40 AM
Innovation Partnerships
Jo De Boeck, Executive Vice President and Chief Strategy Officer,
imec & KU Leuven, Leuven, Belgium

In every aspect of our life and society, semiconductors play a major role. The pandemic in conjunction with
supply chain hiccups and geopolitical tensions made all regions realize that they need to revisit their presence
in the semiconductor value chain. The European Commission projected the ambition of achieving a 20%
share of the global semiconductor production by 2030.

Europe can leverage existing strengths such as, among others, the unique position of equipment companies
and leadership positions in 300mm semiconductor technology R&D. The Chips-for-Europe initiative will
invest in pilot lines and ecosystems for chip manufacturing, embracing leading-edge and first-of-a-kind
technologies. The pilot lines will allow early exploration of the potential impact of new technology features
in advanced chip and system architectures. This will trigger increased demand and accelerate industrial
uptake of the novel technologies. This type of innovation loop is also essential for deep-tech start-ups
building their unique value proposition. The full-stack, networked model of industry collaboration is at the
core of the EU Chips Act ambition and will impact different application domains such as heterogeneous
cloud and distributed computing, connectivity, automotive, and health.

It is crucial for all this innovation potential that we, as an industry, consider that semiconductor
manufacturing is resource-intensive with respect to energy, water, chemicals, and raw materials. Design-
technology co-optimization (DTCO) and System-Technology co-optimization (STCO) methodologies can
develop a framework for early sustainability assessments of logic technologies. Finally, we urgently need to
get the message across that climate, health, safety, and human connectedness all require complex digital
backbones, if we want to stand a chance of attracting the right talent.

1.4 5G Drives Exponential Increase in Processing 11:15 AM

Needs Across all Industries
Erik Ekudden, Senior Vice President & Chief Technology Officer, Ericsson,
Kista, Sweden

Across essentially all industrial sectors, advanced semiconductor technology is the key enabler for
innovations in customer offerings and internal efficiencies. The increase in the value of data and the related
push for AI are examples of forces that increase the demand for compute power, which translates to more
complex and powerful silicon. Moore’s Law, supported by rapidly evolving semiconductor technology and
ever more advanced building practices and assembly technologies, has met the need for decades.

But what is driving 5G today? If we look at the processing requirements, it is the digital front-end, physical
layer processing, and beam forming. Back in 2010, LTE/4G was a 20MHz carrier with two receive and two
transmit branches, and there was a transmission time interval of one millisecond. Fast forward to where
we are today on 5G with massive MIMO, we typically have 100MHz carrier bandwidth. That is a factor of
five increase. We have 64 transmitter and 64 receiver radios, which is an increase by a factor of 32, and the
transmission time is down to 0.5 milliseconds. In other words, there is only half the time to do 160 times
more processing. This is driving an exponential increase in processing needs across the telecom business
today, and will continue to do so as we race towards 6G. This talk will address whether the semiconductor
industry is ready to tackle these challenges.

PRESENTATION TO PLENARY SPEAKERS 11:50 AM

CONCLUSION 11:55 AM

16
SESSION 2 Monday February 20th, 1:30 PM
Digital Processors
Session Chair: Shidhartha Das, AMD, Cambridge, United Kingdom
Session Co-Chair: Ji-Hoon Kim, Ewha Womans University, Seoul, Korea

1:30 PM
2.1 “Zen 4”: The AMD 5nm 5.7GHz x86-64 Microprocessor Core
B. Munger1, K. Wilcox1, J. Sniderman1, C. Tung1, B. Johnson2, R. Schreiber3, C. Henrion2, K. Gillespie1,
T.  Burd4, H.  Fair1, D.  Johnson2, J.  White1, S.  McLelland1, S.  Bakke1, J.  Olson1, R.  McCracken1,
M. Pickett2, A. Horiuchi2, H. Nguyen1, T. H. Jackson2
1AMD, Boxborough, MA; 2AMD, Fort Collins, CO; 3AMD, Austin, TX; 4AMD, Santa Clara, CA

2:00 PM
2.2 A 5G Mobile Gaming-Centric SoC with High-Performance Thermal Management in
4nm FinFET
B-J. Huang, A. Tsai, L. Hsieh, K. Chang, C-J. Tsai, J-M. Chen, E-W. Fang, S-Y. Hsueh, J. Ciao, B. Chen,
C. Chang, P. Kao, E. Wang, H. H. Chen, H. Mair, S-A. Hwang
MediaTek, Hsinchu, Taiwan

2:30 PM
2.3 Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with
Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip
Extension
K. Kawamura*1, J. Yu*1, D. Okonogi1, S. Jimbo1, G. Inoue1, A. Hyodo1, Á. L. García-Arias1, K. Ando2,
B. H. Fukushima-Kimura2, R. Yasudo3, T. V. Chu1, M. Motomura1
1Tokyo Institute of Technology, Yokohama, Japan

2Hokkaido University, Sapporo, Japan

3Kyoto University, Kyoto, Japan

*Equally Credited Authors (ECAs)

Break 3:00 PM

3:15 PM
2.4 A Fully Integrated End-to-End Genome Analysis Accelerator for Next-Generation
Sequencing
Y-L. Chen*1, C-H. Yang*1, Y-C. Wu*1, C-H. Lee2, W-C. Chen3, L-Y. Lin3, N-S. Chang3, C-P. Lin3,
C-S. Chen3, J-H. Hung2,4, C-H. Yang1,2
1National Taiwan University, Taipei, Taiwan; 2GeneASIC Technologies, Hsinchu, Taiwan

3Taiwan Semiconductor Research Institute, Hsinchu, Taiwan

4National Yang Ming Chiao Tung University, Hsinchu, Taiwan

*Equally Credited Authors (ECAs)

3:45 PM
2.5 A 28nm 142mW Motion-Control SoC for Autonomous Mobile Robots
I-T. Lin1, Z-S. Fu1, W-C. Chen2, L-Y. Lin2, N-S. Chang2, C-P. Lin2, C-S. Chen2, C-H. Yang1
1National Taiwan University, Taipei, Taiwan

2Taiwan Semiconductor Research Institute, Hsinchu, Taiwan

4:15 PM
2.6 VISTA: A 704mW 4K-UHD CNN Processor for Video and Image Spatial/Temporal
Interpolation Acceleration
K-P. Lin, J-H. Liu, J-Y. Wu, H-C. Liao, C-T. Huang
National Tsing Hua University, Hsinchu, Taiwan

4:45 PM
2.7 MetaVRain: A 133mW Real-Time Hyper-Realistic 3D-NeRF Processor with 1D-2D
Hybrid-Neural Engines for Metaverse on Mobile Devices
D. Han, J. Ryu, S. Kim, S. Kim, H-J. Yoo
Korea Advanced Institute of Science and Technology, Daejeon, Korea

Conclusion 5:15 PM

17
SESSION 3 Monday February 20th, 1:30 PM
Amplifiers and Oscillators
Session Chair: Jens Anders, University of Stuttgart, Stuttgart, Germany
Session Co-Chair: Shon-Hang Wen, MediaTek, Hsinchu, Taiwan
1:30 PM
3.1 A 120.9dB DR, -111.2dB THD+N Digital-Input Capacitively-Coupled Chopper Class-D
Audio Amplifier
H. Zhang1, M. Berkhout2, K. A. A. Makinwa1, Q. Fan1
1Delft University of Technology, Delft, The Netherlands
2Goodix Technology, Nijmegen, The Netherlands

2:00 PM
3.2 A Chopper-Stabilized Amplifier with a Relaxed Fill-In Technique and 22.6pA Input
Current
T. Rooijers1,2, J. H. Huijsing1, K. A. A. Makinwa1
1Delft University of Technology, Delft, The Netherlands; 2now at Broadcom, Bunnik, The Netherlands

2:15 PM
3.3 Bandpass Filter and Oscillator ICs with THD < -140dBc at 10Vppd for Testing
High-Resolution ADCs
S. Sarkar1,2, R. Agarwal1, N. Krishnapura2
1Texas Instruments, Bangalore, India; 2Indian Institute of Technology Madras, Chennai, India

2:30 PM
3.4 A 0.01mm2 10MHz RC Frequency Reference with a 1-Point On-Chip-Trimmed
Inaccuracy of ±0.28% from −45°C to 125°C in 0.18μm CMOS
X. An*1,2, S. Pan*1,3, H. Jiang2, K. A. A. Makinwa1
1Delft University of Technology, Delft, The Netherlands
2Silicon Integrated, Eindhoven, The Netherlands; 3Tsinghua University, Beijing, China

*Equally Credited Authors (ECAs)

Break 3:00 PM
3:15 PM
3.5 A 1.4μW/MHz 100MHz RC Oscillator with ±1030ppm Inaccuracy from -40°C to 85°C
After Accelerated Aging for 500 Hours at 125°C
K-S. Park, N. Pal, Y. Li, R. Xia, T. Wang, A. Abdelrahman, P. K. Hanumolu
University of Illinois, Urbana, IL
3:45 PM
3.6 A 12/13.56MHz Crystal Oscillator with Binary-Search-Assisted Two-Step Injection
Achieving 5.0nJ Startup Energy and 45.8μs Startup Time
H. Li1, K-M. Lei1, P-I. Mak1, R. P. Martins1,2
1University of Macau, Macau, China; 2Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal

4:15 PM
3.7 A 16MHz XO with 17.5μs Startup Time Under 104ppm-ΔF Injection Using Automatic
Phase-Error Correction Technique
Z. Cai1, X. Wang1, Z. Wang1, Y. Yin1, W. Zhang1, T. Xu2, Y. Guo1
1Nanjing University of Posts and Telecommunications, Nanjing, China; 2Hefei University, Hefei, China

4:30 PM
3.8 A 0.954nW 32kHz Crystal Oscillator in 22nm CMOS with Gm-C-Based Current Injection
Control
Y. Zhang1, Y. You1, W. Ren1, X. Xu1, L. Shen1, J. Ru1, R. Huang1, L. Ye1,2
1Peking University, Beijing, China
2Advanced Institute of Information Technology of Peking University, Hangzhou, China

4:45 PM
3.9 A 0.5-to-400MHz Programmable BAW Oscillator with Fractional Output Divider
Achieving 4ppm Frequency Stability over Temperature and <95fs Jitter
S.  Mukherjee1, Y.  Darwhekar1, J.  Janardhanan1, P.  Mirajkar1, R.  Reddy1, H.  Ramesh1, B.  Bahr2,
J.  Chand1, U.  Meda1, B.  Haroun2, S.  Karantha1, E.  Yen3, K.  Martin2, D.  Gan4, A.  Sijelmassi2,
S. Aniruddhan5, 1Texas Instruments, Bangalore, India; 2Texas Instruments, Dallas, TX
3Texas Instruments, Santa Clara, CA; 4Texas Instruments, Melaka, Malaysia
5Indian Institute of Technology Madras, Chennai, India

Conclusion 5:15 PM

18
SESSION 4 Monday February 20th, 1:30 PM
Frequency Synthesizers
Session Chair: Dmytro Cherniak, Infineon Technologies, Villach, Austria
Session Co-Chair: Wanghua Wu, Samsung Semiconductor, Santa Clara, CA

1:30 PM
4.1 A 16GHz, 41kHzrms Frequency Error, Background-Calibrated, Duty-Cycled FMCW
Charge-Pump PLL
P. T. Renukaswamy1,2, K. Vaesen1, N. Markulic1, V. Derudder1, D-W. Park 1, P. Wambacq1,2,
J. Craninckx1
1imec, Heverlee, Belgium

2Vrije Universiteit Brussel, Brussels, Belgium

2:00 PM
4.2 A 135fsrms-Jitter 0.6-to-7.7GHz LO Generator Using a Single LC-VCO-Based
Subsampling PLL and a Ring-Oscillator-Based Sub-Integer-N Frequency Multiplier
Y. Jo*, J. Kim*, Y. Shin, C. Hwang, H. Park, J. Choi
Korea Advanced Institute of Science and Technology, Daejeon, Korea
*Equally Credited Authors (ECAs)

2:30 PM
4.3 A 76.7fs-Integrated-Jitter and -71.9dBc In-Band Fractional-Spur Bang-Bang Digital
PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering
S.  M.  Dartizio1, F.  Tesolin1, G.  Castoro1, F.  Buccoleri1, L.  Lanzoni1, M.  Rossoni1, D.  Cherniak2,
L. Bertulessi1, C. Samori1, A. L. Lacaita1, S. Levantino1
1Politecnico di Milano, Milano, Italy

2Infineon Technologies, Villach, Austria

Break 3:00 PM

3:15 PM
4.4 A 32kHz-Reference 2.4GHz Fractional-N Nonuniform Oversampling PLL with
Gain-Boosted PD and Loop-Gain Calibration 
J. Qiu, W. Wang, Z. Sun, B. Liu, Y. Zhang, D. Xu, H. Huang, A. A. Fadila, Z. Liu, W. Madany, Y. Xiong,
A. Shirane, K. Okada
Tokyo Institute of Technology, Tokyo, Japan

3:45 PM
4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC
Topology
G. Castoro*1, S. M. Dartizio*1, F. Tesolin1, F. Buccoleri1, M. Rossoni1, D. Cherniak2, L. Bertulessi1,
C. Samori1, A. L. Lacaita1, S. Levantino1
1Politecnico di Milano, Milan, Italy

2Infineon Technologies, Villach, Austria

*Equally Credited Authors (ECAs)

4:15 PM
4.6 A 47fsrms-Jitter and 26.6mW 103.5GHz PLL with Power-Gating Injection-Locked
Frequency-Multiplier-Based Phase Detector and Extended Loop Bandwidth 
J. Bang, J. Kim, S. Jung, S. Park, J. Choi
Korea Advanced Institute of Science and Technology, Daejeon, Korea

4:45 PM
4.7 A 0.4V-VDD 2.25-to-2.75GHz ULV-SS-PLL Achieving 236.6fsrms Jitter, -253.8dB
Jitter-Power FoM, and -76.1dBc Reference Spur
Z. Zhang1, X. Shen1, Z. Zhang1, G. Li1, N. Qi1, J. Liu1, Y. Chen2, N. Wu1, L. Liu1
1Chinese Academy of Sciences, Beijing, China

2University of Macau, Macau, China

Conclusion 5:15 PM

19
SESSION 5 Monday February 20th, 1:30 PM
Image Sensors
Session Chair: Kazuko Nishimura, Panasonic Holdings, Moriguchi, Japan
Session Co-Chair: Masaki Sakakibara, Sony Semiconductor Solutions, Atsugi-shi, Japan
1:30 PM
5.1 A 3-Wafer-Stacked Hybrid 15MPixel CIS + 1MPixel EVS with 4.6GEvent/s Readout,
In-Pixel TDC and On-Chip ISP and ESP Function
M. Guo1, S. Chen1, Z. Gao2, W. Yang1, P. Bartkovjak2, Q. Qin2, X. Hu1, D. Zhou1, M. Uchiyama2, Y. Kudo3,
S. Fukuoka3, C. Xu2, H. Ebihara2, A. Wang2, P. Jiang2, B. Jiang2, B. Mu2, H. Chen1, J. Yang2, T. Dai2,
A. Suess2
1OmniVision Technologies, Shanghai, China; 2OmniVision Technologies, Santa Clara, CA

3OmniVision Technologies, Yokohama, Japan

2:00 PM
5.2 1.22μm 35.6Mpixel RGB Hybrid Event-Based Vision Sensor with 4.88μm-Pitch Event
Pixels and up to 10K Event Frame Rate by Adaptive Control on Event Sparsity
K. Kodama1, Y. Sato1, Y. Yorikado1, R. Berner2, K. Mizoguchi1, T. Miyazaki1, M. Tsukamoto1, Y. Matoba1,
H. Shinozaki1, A. Niwa1, T. Yamaguchi1, C. Brandli2, H. Wakabayashi1, Y. Oike1
1Sony Semiconductor Solutions, Atsugi, Japan

2Sony Advanced Visual Sensing, Schlieren, Switzerland

2:30 PM
5.3 A 2.97μm-Pitch Event-Based Vision Sensor with Shared Pixel Front-End Circuitry and
Low-Noise Intensity Readout Mode
A. Niwa1, F. Mochizuki1, R. Berner2, T. Maruyama1, T. Terano1, K. Takamiya1, Y. Kimura1, K. Mizoguchi1,
T. Miyazaki1, S. Kaizu1, H. Takahashi1, A. Suzuki1, C. Brandli2, H. Wakabayashi1, Y. Oike1
1Sony Semiconductor Solutions, Kanagawa, Japan

2Sony Advanced Visual Sensing, Zurich, Switzerland

Break 3:00 PM
3:15 PM
5.4 A 0.64μm 4-Photodiode 1.28μm 50Mpixel CMOS Image Sensor with 0.98e- Temporal
Noise and 20Ke- Full-Well Capacity Employing Quarter-Ring Source-Follower
H. Kim, Y. H. Kim, S. Moon, H. Kim, B. Yoo, J. Park, S. Kim, J-M. Koo, S. Seo, H. J. Shin, Y. Choi,
J. Kim, K. Kim, J-H. Seo, S. Lim, T. Jung, H. Park, S. Jung, J. Ko, K. Lee, J. Ahn, J. Yim
Samsung Electronics, Hwasung, Korea
3:30 PM
5.5 A 16.4kPixel 3.08-to-3.86THz Digital Real-Time CMOS  Image Sensor with 73dB
Dynamic Range
M. Liu1, Z. Cai1, S. Zhou2, M-K. Law3, J. Liu1, J. Ma4, N. Wu1, L. Liu1
1Chinese Academy of Sciences, Beijing, China; 2Tianjin University, Tianjin, China

3University of Macau, Macau, China: 4Zhejiang University, Hangzhou, China

3:45 PM
5.6 A 400×200 600fps 117.7dB-DR SPAD X-Ray Detector with Seamless Global Shutter
and Time-Encoded Extrapolation Counter
B. Park1, B. Ahn1, H-S. Choi2, J. Jeong3, K. Hwang3, T. Kim3, M-J. Lee2, Y. Chae1
1Yonsei University, Seoul, Korea; 2Korea Institute of Science and Technology, Seoul, Korea

3Rayence, Hwaseong, Korea

4:15 PM
5.7 55pW/pixel Peak Power Imager with Near-Sensor Novelty/Edge Detection and DC-DC
Converter-Less MPPT for Purely Harvested Sensor Nodes
K. A. Ahmed*, H. Okuhara*, M. Alioto, National University of Singapore, Singapore, Singapore
*Equally Credited Authors (ECAs)
4:45 PM
5.8 Dual-Port CMOS Image Sensor with Regression-Based HDR Flux-to-Digital Conversion
and 80ns Rapid-Update Pixel-Wise Exposure Coding
R. Gulve, R. Rangel, A. Barman, D. Nguyen, M. Wei, M. A. Sakr, X. Sun, D. B. Lindell, K. N. Kutulakos,
R. Genov, University of Toronto, Toronto, Canada
Conclusion 5:15 PM

20
SESSION 6 Monday February 20th, 1:30 PM
Advanced Wireline Links and Techniques
Session Chair: Friedel Gerfers, Technische Universität Berlin, Berlin, Germany
Session Co-Chair: Takashi Takemoto, Hitachi, Sapporo, Japan

1:30 PM
6.1 A 112Gb/s Serial Link Transceiver With 3-tap FFE and 18-tap DFE Receiver for up to
43dB Insertion Loss Channel in 7nm FinFET Technology
B. Zhang1, A. Vasani1, A. Sinha2, A. Nilchi1, H. Tong1, L. Rao1, K. Khanoyan1, H. Hatamkhani1, X. Yang1,
X. Meng1, A. Wong2, J. Kim2, P. Jing2, Y. Sun2, A. Nazemi1, D. Liu2, A. Brewster1, J. Cao1, A. Momtaz1
1Broadcom, Irvine, CA

2Broadcom, San Jose, CA

2:00 PM
6.2 A 4.63pJ/b 112Gb/s DSP-Based PAM-4 Transceiver for a Large-Scale Switch in 5nm
FinFET
H. Park*1, M. Abdullatif*1, E. Chen1, A. Elmallah1, Q. Nehal1, M. Gandara1, T-B. Liu2, A. Khashaba1,
J. Lee1, C-Y. Kuan2, D. Ramachandran1, R-B. Sun2, A. Atharav1, Y. Chun1, M. Zhang1, D-F. Weng2,
C-H. Tsai2, C-H. Chang2, C-S. Peng2, S-T. Hsu2, T. Ali1
1MediaTek, Irvine, CA

2MediaTek, Hsinchu, Taiwan

*Equally Credited Authors (ECAs)

2:30 PM
6.3 A 0.43pJ/b 200Gb/s 5-Tap Delay-Line-Based Receiver FFE with Low-Frequency
Equalization in 28nm CMOS
B. Ye, G. Wu, W. Gai, K. Sheng, Y. He, Peking University, Beijing, China

Break 3:00 PM

3:15 PM
6.4 A 4nm 32Gb/s 8Tb/s/mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver With
Equalization Schemes And Training Techniques 
K. Seong, D. Park, G. Bae, H. Lee, Y. Suh, W. Oh, H. Lee, J. Kim, T. Lee, G. Mo, S. Jung, D. Choi,
B-J. Yoo, S. Park, H-G. Rhew, J. Shin
Samsung Electronics, Hwasung, Korea

3:45 PM
6.5 A 37.8dB Channel Loss 0.6μs Lock Time CDR with Flash Frequency Acquisition in 5nm
FinFET
C-K. Kao, S-C. Hung, T-H. Yeh, C-Y. Hsiao, MediaTek, Hsinchu, Taiwan

4:15 PM
6.6 A 0.83pJ/b 52Gb/s PAM-4 Baud-Rate CDR with Pattern-Based Phase Detector for
Short-Reach Applications
S. Park, Y. Choi, J. Sim, J. Choi, H. Park, Y. Kwon, C. Kim, Korea University, Seoul, Korea

4:45 PM
6.7 A 128Gb/s PAM-4 Transmitter with Programmable-Width Pulse Generator and
Pattern-Dependent Pre-Emphasis in 28nm CMOS
K. Sheng, W. Gai, Z. Feng, H. Niu, B. Ye, H. Zhou, Peking University, Beijing, China

5:00 PM
6.8 A 100Gb/s 1.6Vppd PAM-8 Transmitter with High-Swing 3+1 Hybrid FFE Taps in 40nm
J. Yang*, E. Song*, S. Hong, D. Lee, S. Lee, H. Im, T. Shin, J. Han
Hanyang University, Seoul, Korea
*Equally Credited Authors (ECAs)

Conclusion 5:15 PM

21
 Demonstration Session 1, Monday February 20th, 5:00-7:00 PM
This year, the Demonstration Session extending in selected regular papers, both Academic and Industrial, will take place
on Monday February 20th, and Tuesday February 21st, from 5 pm until 7 pm in the Golden Gate Hall. These demonstrations
will feature real-life applications made possible by new ICs presented at ISSCC 2023, as noted by the symbol DS1

ISSCC 2022 Demo Award Winners Presenting at ISSCC 2023

6.1 A 1.41pJ/b 224Gb/s PAM-4 SerDes Receiver with 31dB Loss Compensation
32.1 BatDrone: A 9.83M-focal-points/s 7.76μs-Latency Ultrasound Imaging System with On-Chip
Per-Voxel RX Beamfocusing for 7m-Range Drone Applications 

2.1 “Zen 4”: The AMD 5nm 5.7GHz x86-64 Microprocessor Core
2.3 Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with
Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension
2.7 MetaVRain: A 133mW Real-Time Hyper-Realistic 3D-NeRF Processor with 1D-2D Hybrid-Neural
Engines for Metaverse on Mobile Devices
3.6 A 12/13.56MHz Crystal Oscillator with Binary-Search-Assisted Two-Step Injection Achieving 5.0nJ
Startup Energy and 45.8μs Startup Time
3.7 A 16MHz XO with 17.5μs Startup Time Under 104ppm-ΔF Injection Using Automatic Phase-Error
Correction Technique
4.1 A 16GHz, 41kHzrms Frequency Error, Background-Calibrated, Duty-Cycled FMCW Charge-Pump
PLL
5.1 A 3-Wafer-Stacked Hybrid 15MPixel CIS + 1MPixel EVS with 4.6GEvent/s Readout, In-Pixel TDC
and On-Chip ISP and ESP Function
5.2 1.22μm 35.6Mpixel RGB Hybrid Event-Based Vision Sensor with 4.88μm-Pitch Event Pixels and
up to 10K Event Frame Rate by Adaptive Control on Event Sparsity
5.3 A 2.97μm-Pitch Event-Based Vision Sensor with Shared Pixel Front-End Circuitry and Low-Noise
Intensity Readout Mode
5.6 A 400×200 600fps 117.7dB-DR SPAD X-Ray Detector with Seamless Global Shutter and Time-
Encoded Extrapolation Counter
5.8 Dual-Port CMOS Image Sensor with Regression-Based HDR Flux-to-Digital Conversion and 80ns
Rapid-Update Pixel-Wise Exposure Coding
11.1 A Scalable Heterogeneous Integrated Two-Stage Vertical Power Delivery Architecture
for High Performance Computing
11.5 A 21W 94.8%-Efficient Reconfigurable Single Inductor Multi-Stage Hybrid DC-DC
Converter
11.6 A 42W Reconfigurable Bidirectional Power Delivery Voltage-Regulating Cable
16.2 A 28nm 53.8TOPS/W 8b Sparse Transformer Accelerator with In-Memory Butterfly Zero Skipper
for Unstructured-Pruned NN and CIM-Based Local-Attention-Reusable Engine
18.1 A W-Band Transceiver Array with 2.4GHz LO Synchronization Enabling Full Scalability for FMCW
Radar
21.3 A CMOS Multi-Functional Biosensor Array for Rapid Low-Concentration Analyte Detection with
On-Chip DEP-Assisted Active Enrichment and Manipulation with No External Electrodes
21.4 A 263 GHz 32-channel EPR-on-a-chip injection-locked VCO-array
21.5 An LTE-Harvesting BLE-to-WiFi Backscattering Chip for Single-Device RFID-Like Interrogation
22.2 A 28nm 2D/3D Unified Sparse Convolution Accelerator with Block-Wise Neighbor Searcher for
Large-Scaled Voxel-Based Point Cloud Network
22.5 C-DNN: A 24.5-85.8TOPS/W Complementary-Deep-Neural-Network Processor with
Heterogeneous CNN/SNN Core Architecture and Forward-Gradient-Based Sparsity Generation

22
EVENING EVENT Monday February 20th, 8:00 PM
EE2:
Integrated Circuits in an Interconnected World

Organizers: Alicia Klinefelter, NVIDIA, Durham, NC

Deeksha Lal, pSemi, Raleigh, NC

Co-Organizers: Elnaz Ansari, Meta, Menlo Park, CA

Zeynep Deniz, IBM, Yorktown Heights, NY
Najme Ebrahimi, University of Florida, Gainesville, FL
Dina El-Damak, German University in Cairo, Cairo, Egypt
Preet Garcha, TI, Dallas, TX
Ulkuhan Guler, WPI, Worcester, MA
Awani Khodkumbhe, UC Berkeley, Berkeley, CA
Kwantae Kim, University/ETH Zürich, Zürich, Switzerland
Shalini Lal, pSemi, Raleigh, NC
Jiamin Li, SUSTech, Shenzhen, China
Kazuko Nishimura, Panasonic, Moriguchi, Japan
Michella Rustom, USC, Los Angeles, CA
Trudy Stetzler, Halliburton, Houston, TX
Rabia Yazicigil Kirby, Boston University, Boston, MA
Farhana Sheikh, Intel, Hillsboro, OR
Kathy Wilcox, AMD, Boxborough, MA
Alice Wang, Everactive, Plano, TX

Moderator: Maryam Rofougaran, Movandi, Irvine, CA

Data-centric applications such as automotive, IoT, and machine learning primarily depend on IC connectivity
to meet the demands of high-bandwidth and energy-efficient communication. Product requirement diversity
continues to grow, and IC components now face a bottleneck in system performance and power, particularly
due to their interconnects. To ensure communication capabilities that meet the demands of emerging
applications with ever-increasing features, additional research and focus is needed. This panel focuses on
connectivity for the next generation of communication systems and brings together expert panelists to share
their perspectives on topics in IC connectivity across wireless, wireline, chip-to-chip, and optical link
communications.

Panelists: Kyeongha Kwon, KAIST, Daejeon, South Korea

Angad Rekhi, NVIDIA, Santa Clara, CA
Asako Toda, Intel, San Jose, CA
Hua Wang, ETH Zürich, Zürich, Switzerland

23
EVENING EVENT Monday February 20th, 8:00 PM
EE3:
The Path to Sustainable IC Ecosystems

Organizers: Yvain Thonnart, CEA-List, Grenoble, France

Rahul Rao, IBM India, Bangalore, India

Co-Organizers: Mutsumi Hamaguchi, Sharp, Tenri, Japan

Renzhi Liu, Intel, Hillsboro, OR
Yongpan Liu, Tsinghua University, Beijing, China

Champion: Alicia Klinefelter, Nvidia, Durham, NC

Moderator: Massimo Alioto, National University of Singapore, Singapore

Sustainability has become a major concern in our lives in general, and all the way to IC design. It widened
from energy management to include greenhouse gas emissions and pressure on natural resources all along
the product lifecycle. These challenges must be taken into account early in product design phases, to rethink
system architecture and circuit techniques to favor frugality and reuse and minimize the impact of
manufacturing. A deep restructuration of the IC ecosystem to integrate eco-design and reuse will need to
arise, either from top-down political intervention or company-driven initiatives. How do we facilitate an
economically viable path to sustainable IC ecosystem? Will this come from market incentives or are
government regulations required? With a growing awareness of this challenge, several initiatives have
already emerged for sustainable electronics, coming from research labs, companies, citizens, or
governments. This panel confronts these approaches and explores their potential to create this economy
viable path via market incentive or government regulation, for a sustainable value chain all over the product
lifecycle.

Panelists: Carole-Jean Wu, Meta, Cambridge, MA

Yogesh Ramadass, Texas Instruments, Santa Clara, CA
Marcus Pan, SRC, Durham, NC
Todd Brady, Intel, Chandler, AZ
Jo De Boeck, imec, Leuven, Belgium
Andreia Cathelin, STMicroelectronics, Crolles, France

24
SESSION 7 Tuesday February 21st, 8:30 AM
SRAM Compute-In-Memory
Session Chair: Kyu-Hyoun (KH) Kim, IBM T. J. Watson, Yorktown Heights, NY
Session Co-Chair: Violante Moschiano, Intel, Avezzano, Italy
8:30 AM
7.1 A 22nm 832kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with
16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices
P-C. Wu*1, J-W. Su*1,2, L-Y. Hong1, J-S. Ren1, C-H. Chien1, H-Y. Chen1, C-E. Ke1, H-M. Hsiao2,
S-H. Li2, S-S. Sheu2, W-C. Lo2, S-C. Chang2, C-C. Lo1, R-S. Liu1, C-C. Hsieh1, K-T. Tang1, M-F. Chang1
1National Tsing Hua University, Hsinchu, Taiwan
2Industrial Technology Research Institute, Hsinchu, Taiwan, *Equally Credited Authors (ECAs)

9:00 AM
7.2 A 28nm 64kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and
Double-bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs
A. Guo, X. Si, X. Chen, F. Dong, X. Pu, D. Li, Y. Zhou, L. Ren, Y. Xue, X. Dong, H. Gao, Y. Zhang,
J. Zhang, Y. Kong, T. Xiong, B. Wang, H. Cai, W. Shan, J. Yang, Southeast University, Nanjing, China
9:30 AM
7.3 A 28nm 38-to-102-TOPS/W 8b Multiply-Less Approximate Digital SRAM
Compute-In-Memory Macro for Neural-Network Inference
Y. He1, H. Diao2, C. Tang1, W. Jia1, X. Tang2, Y. Wang2, J. Yue3, X. Li1, H. Yang1, H. Jia1, Y. Liu1
1Tsinghua University, Beijing, China; 2Peking University, Beijing, China
3Chinese Academy of Sciences, Beijing, China

Break 10:00 AM
10:15 AM
7.4 A 4nm 6163-TOPS/W/b 4790-TOPS/mm2/b SRAM Based Digital-Computing-in-Memory
Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update
H. Mori1, W-C. Zhao1, C-E. Lee1, C-F. Lee1, Y-H. Hsu1, C-K. Chuang1, T. Hashizume2, H-C. Tung1,
Y-Y. Liu1, S-R. Wu1, K. Akarvardar3, T-L. Chou1, H. Fujiwara1, Y. Wang1, Y-D. Chih1, Y-H. Chen1,
H-J. Liao1, T-Y. J. Chang1, 1TSMC, Hsinchu, Taiwan; 2TSMC, Yokohama, Japan
3TSMC, San Jose, CA

10:45 AM
7.5 A 28nm Horizontal-Weight-Shift and Vertical-Feature-Shift-Based Separate-Wordline
6T-SRAM Computation-in-Memory Unit-Macro for Edge Depthwise Neural-Networks
B. Wang, C. Xue, Z. Feng, Z. Zhang, H. Liu, L. Ren, X. Li, A. Yin, T. Xiong, Y. Xue, S. He, Y. Kong,
Y. Zhou, A. Guo, X. Si, J. Yang, Southeast University, Nanjing, China
11:00 AM
7.6 A 70.85-86.27-TOPS/W PVT-Insensitive 8b Word-Wise ACIM with Post Processing
Relaxation
S-E. Hsieh1, C-H. Wei1, C-X. Xue1, H-W. Lin1, W-H. Tu1, E-J. Chang1, K-T. Yang1, P-H. Chen1,
W-N. Liao1, L. L. Low2, C-D. Lee1, A-C. Lu1, J. Liang1, C-C. Cheng1, T-H. Kang1
1MediaTek, Hsinchu, Taiwan; 2MediaTek, Singapore, Singapore

11:15 AM
7.7 CV-CIM: A 28nm XOR-derived Similarity-aware Computation-In-Memory For Cost
Volume Construction
Z. Yue, Y. Wang, H. Wang, Y. Wang, R. Guo, L. Tang, L. Liu, S. Wei, Y. Hu, S. Yin
Tsinghua University, Beijing, China
11:30 AM
7.8 A 22nm Delta-Sigma Computing-In-Memory (ΔΣCIM) SRAM Macro with Near-Zero-
Mean Outputs and LSB-First ADCs Achieving 21.38TOPS/W for 8b-MAC Edge AI
Processing
P. Chen*1, M. Wu*1, W. Zhao1, J. Cui1, Z. Wang1,2, Y. Zhang3, Q. Wang3, J. Ru1, L. Shen1, T. Jia1,
Y. Ma1, L. Ye1,2, R. Huang1, 1Peking University, Beijing, China
2Advanced Institute of Information Technology of Peking University, Hangzhou, China
3Nano Core Chip Electronic Technology, Hangzhou, China, *Equally Credited Authors (ECAs)

11:45 AM
7.9 CTLE-Ising: A 1440-Spin Continuous-Time Latch-Based Ising Machine with One-Shot
Fully-Parallel Spin Updates Featuring Equalization of Spin States
J. Bae*, W. Oh*, J. Koo, B. Kim
University of California, Santa Barbara, CA, *Equally Credited Authors (ECAs
Conclusion 12:15 PM

25
SESSIONS 8 & 9 Tuesday February 21st, 8:30 AM
GHz-to-millimeter Wave Frequency Generation
Session Chair: Swaminathan Sankaran, Texas Instruments, Dallas, TX
Session Co-Chair: Mona Hella, Rensselaer Polytechnic Institute, Troy, NY
8:30 AM
8.1 A 11.5-to-14.3GHz 192.8dBc/Hz FoM at 1MHz Offset Dual-Core Enhanced Class-F VCO
with Common-Mode-Noise Self-Cancellation and Isolation Technique
Q. Wu, W. Deng, H. Jia, H. Liu, S. Zhang, Z. Wang, B. Chi
Tsinghua University, Beijing, China
8:45 AM
8.2 A 22.4-to-26.8GHz Dual-Path-Synchronized Quad-Core Oscillator Achieving
−138dBc/Hz PN and 193.3dBc/Hz FoM at 10MHz Offset from 25.8GHz
X. Zhan1, J. Yin1, P-I. Mak1, R. P. Martins1,2
1University of Macau, Macau, China
2Instituto Superior Tecnico/University of Lisboa, Lisboa, Portugal

9:00 AM
8.3 A 28GHz Scalable Inter-Core-Shaping Multi-Core Oscillator with DM/CM-Configured
Coupling Achieving 193.3dBc/Hz FoM and 205.5dBc/Hz FoMA at 1MHz Offset
Y. Shu, Z. Deng, X. Luo
University of Electronic Science and Technology of China, Chengdu, China
9:30 AM
8.4 An 83.3-to-104.7GHz Harmonic-Extraction VCO Incorporating Multi-Resonance,
Multi-Core, and Multi-Mode (3M) Techniques Achieving -124dBc/Hz Absolute PN
and 190.7dBc/Hz FoMT
H. Guo1, Y. Chen1, Y. Huang1, P-I. Mak1, R. P. Martins1,2
1University of Macau, Macau, China
2Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal

Break 10:00 AM

Highlighted Chip Releases: Digital and Machine Learning Processors

Session Chair: Alicia Klinefelter, NVIDIA, Durham, NC
Session Co-Chair: Vivek De, Intel, Beaverton, OR
10:15 AM
9.1 A 7nm ML Training Processor with Wave Clock Distribution
T. C. Fischer1, A. K. Nivarti1, R. Ramachandran1, R. Bharti1, D. Carson1, A. Lawrendra1, V. Mudgal1,
V. Santhosh1, S. Shukla2, T-C. Tsai1
1Tesla, Palo Alto, CA
2Tesla, Austin, TX

10:45 AM
9.2 A 1mW Always-on Computer Vision Deep Learning Neural Decision Processor
D. Garrett, Y-S. Park, S. Kim, J. Sharma, W. Huang, M. Shaghaghi, V. Parthasarathy, S. Gibellini,
S. Bailey, M. Moturi, P. Vorenkamp, K. Busch, J. Holleman, B. Javid, A. Yousefi, M. Judy, A. Gupta
Syntiant, Irving, CA
11:15 AM
9.3 NVLink-C2C: A Coherent Off Package Chip-to-Chip Interconnect with 40Gbps/pin
Single-ended Signaling
Y. Wei1, Y. C. Huang2, H. Tang1, N. Sankaran1, I. Chadha1, D. Dai1, O. Oluwole1, V. Balan1, E. Lee1
1Nvidia, Santa Clara, CA
2Nvidia, Hsinchu, Taiwan

11:45 AM
9.4 An In-Depth Look at the Intel IPU E2000
B. Burres*1, N. Sundar*2, Y. Li*3
1Intel, Hudson, MA
2Intel, Santa Clara, CA
3Intel, Portland, OR

*Equally Credited Authors (ECAs)

Conclusion 12:15 PM

26
SESSION 10 Tuesday February 21st, 8:30 AM
Pipelined and Noise-Shaping ADCs
Session Chair: Nima Maghari, University of Florida, Gainesville, FL
Session Co-Chair: Ping Gui, Southern Methodist University, Dallas, TX

8:30 AM
10.1 A 1.8GHz 12b Pre-Sampling Pipelined ADC with Reference Buffer and OP Power
Relaxations
S-E. Hsieh, T-C. Wu, C-C. Hou
MediaTek, Hsinchu, Taiwan

9:00 AM
10.2 A Single-Channel 2.6GS/s 10b Dynamic Pipelined ADC with Time-Assisted Residue
Generation Scheme Achieving Intrinsic PVT Robustness
J. Hao1,2, M. Zhang1, Y. Zhang1,2, S. Liu2, Z. Zhu2, Y. Zhu1, C-H. Chan1, R. P. Martins1,3
1University of Macau, Macau, China

2Xidian University, Xi’an, China

3Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal

9:30 AM
10.3 A Single-Channel 12b 2GS/s PVT-Robust Pipelined ADC with Critically Damped Ring
Amplifier and Time-Domain Quantizer
Y. Cao1, M. Zhang1, Y. Zhu1, C-H. Chan1, R. P. Martins1,2
1University of Macau, Macau, China

2Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal

Break 10:00 AM

10:15 AM
10.4 A Rail-to-Rail 12MS/s 91.3dB SNDR 94.1dB DR Two-Step SAR ADC with Integrated
Input Buffer Using Predictive Level-Shifting
M. Li1, C. Y. Lee1, A. ElShater1, Y. Miyahara2, K. Sobue2, K. Tomioka2, U-K. Moon1
1Oregon State University, Corvallis, OR

2Asahi Kasei Microdevices, Atsugi, Japan

10:45 AM
10.5 A 25MHz-BW 77.2dB-SNDR 2nd-Order Gain-Error-Shaping and NS Pipelined SAR ADC
Based on a Quantization-Prediction-Unrolled Scheme
H. Zhang1, Y. Zhu1, C-H. Chan1, R. P. Martins1,2
1University of Macau, Macau, China

2Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal

11:15 AM
10.6 A 150kHz-BW 15-ENOB Incremental Zoom ADC with Skipped Sampling and Single
Buffer Embedded Noise-Shaping SAR Quantizer
Z. Wang1, L. Jie2, Z. Kong1, M. Zhan2, Y. Zhong2, Y. Wang1, X. Tang1
1Peking University, Beijing, China

2Tsinghua University, Beijing, China

11:45 AM
10.7 A Single-Channel 70dB-SNDR 100MHz-BW 4th-Order Noise-Shaping Pipeline SAR ADC
with Residue Amplifier Error Shaping 
Y. Zhang*1,2, J. Hao1,2, S. Liu2, Z. Zhu2, Y. Zhu1, C-H. Chan*1, R. P. Martins1,3
1University of Macau, Macau, China

2Xidian University, Xi’an, China

3Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal

*Equally Credited Authors (ECAs)

Conclusion 12:15 PM

27
SESSION 11 Tuesday February 21st, 8:30 AM
USB and Compute Power Delivery
Session Chair: Harish Krishnamurthy, Intel, Hillsboro, OR
Session Co-Chair: Chan-Hong Chern, TSMC, Hsinchu, Taiwan
8:30 AM
11.1 A Scalable Heterogeneous Integrated Two-Stage Vertical Power Delivery Architecture
for High Performance Computing
C. Hardy1, H. Pham1, M. M. Jatlaoui2, F. Voiron2, T. Xie1, P-H. Chen1, S. Jha1, P. Mercier1, H-P. Le1
1University of California, San Diego, CA; 2Murata, Caen, France

9:00 AM
11.2 A 12-1 Quad-Output Switched-Capacitor Buck Converter with Shared DC Capacitors
Achieving 90.4% Peak Efficiency and 48mA/mm3 Power Density at 85% Efficiency
T. Hu1, M. Huang1, Y. Lu1, R. P. Martins1,2
1University of Macau, Macau, China; 2Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal

9:30 AM
11.3 A 1.8W High-Frequency SIMO Converter Featuring Digital Sensor-Less Computational
Zero-Current Operation and Non-Linear Duty-Boost
S. Kim1, H. K. Krishnamurthy1, S. Sofer2, S. Weng1, S. Wolf2, A. Ravi1, K. Ravichandran1, O. Degani2,
J. W. Tschanz1, V. De1, 1Intel, Hillsboro, OR; 2Intel, Haifa, Israel
9:45 AM
11.4 A Double Step-down Dual-output Converter with Cross Regulation of 0.025mV/mA and
Improved Current Balance
W-C. Hung1, C-W. Chen1, Y-W. Huang1, A. Chen1, Z-Y. Yang1, K-H. Chen1, K-L. Zheng1,2, Y-H. Lin3,
S-R. Lin3, T-Y. Tsai3, W-C. Huang1
1National Yang Ming Chiao Tung University, Hsinchu, Taiwan

2Chip-GaN Power Semiconductor, Hsinchu, Taiwan; 3Realtek Semiconductor, Hsinchu, Taiwan

Break 10:00 AM
10:15 AM
11.5 A 21W 94.8%-Efficient Reconfigurable Single Inductor Multi-Stage Hybrid DC-DC
Converter
C. Hardy, H-P. Le, University of California, San Diego, CA
10:45 AM
11.6 A 42W Reconfigurable Bidirectional Power Delivery Voltage-Regulating Cable
Z. Tong1, J. Huang1, Y. Lu1, R. P. Martins1,2
1University of Macau, Macau, China; 2Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal

11:15 AM
11.7 A Wide 0.1-10 Conversion-Ratio Symmetric Hybrid Buck-Boost Converter for USB PD
Bidirectional Conversion
C. Lin1, C-S. Hung1, S-Y. Li1, Y-T. Hsu1, K-H. Chen1, K-L. Zheng1,2, Y-H. Lin3, S-R. Lin3, T-Y. Tsai3
1National Yang Ming Chiao Tung University, Hsinchu, Taiwan

2Chip-GaN Power Semiconductor, Hsinchu, Taiwan; 3Realtek Semiconductor, Hsinchu, Taiwan

11:30 AM
11.8 A 5A 94.5% Peak Efficiency 9~16V-to-1V Dual-Path Series-Capacitor Converter with
Full Duty Range and Low V·A Metric
X. Yang, L. Zhao, M. Zhao, Z. Tan, Y. Ding, W. Li, W. Qu, Zhejiang University, Hangzhou, China
11:45 AM
11.9 A Compact 12V-to-1V 91.8% Peak Efficiency Hybrid Resonant Switched-Capacitor
Parallel Inductor (ReSC-PL) Buck Converter
G. Cai1, Y. Lu1, R. P. Martins1,2
1University of Macau, Macau, China; 2Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal

12:00 PM
11.10 A 12V-Input 1V-1.8V-Output 93.7% Peak Efficiency Dual-Inductor Quad-Path Hybrid
DC-DC Converter
W-L. Zeng1,2, G. Cai1, C-F. Lee1, C-S. Lam1, Y. Lu1, S-W. Sin1, R. P. Martins1,3
1University of Macau, Macau, China

2Zhuhai UM Science & Technology Research Institute, Zhuhai, China

3Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal

Conclusion 12:15 PM

28
SESSIONS 12 & 13 Tuesday February 21st, 8:30 AM
High Performance Optical Receivers
Session Chair: Byungsub Kim, POSTECH, Pohang, Korea
Session Co-Chair: Thomas Toifl, Cisco Systems, Gattikon, Switzerland
8:30 AM
12.1 A 0.96pJ/b 7×50Gb/s-per-Fiber WDM Receiver with Stacked 7nm CMOS and 45nm
Silicon Photonic Dies
M. Raj1, C. Xie1, A. Bekele1, A. Chou1, W. Zhang1, Y. Cao1, J. W. Kim1, N. Narang2, H. Zhao2, Y. Wang2,
K. H. Tan2, W. Lin1, J. Im1, D. Mahashin1, S. Asuncion1, P. Upadhyaya1, Y. Frans1
1AMD, San Jose, CA; 2AMD, Singapore, Singapore

9:00 AM
12.2 A 7 pA/√Hz Asymmetric Differential TIA for 100Gb/s PAM-4 Links with -14dBm Optical
Sensitivity in 16nm CMOS
K. Lakshmikumar*1, A. Kurylak*1, R. K. Nandwana*1, B. Das1, J. Pampanin1, M. Brubaker1,
P. K. Hanumolu2, 1CISCO Systems, Allentown, PA; 2University of Illinois, Urbana, IL
*Equally Credited Authors (ECAs)
9:30 AM
12.3 A Carrier Phase Recovery Loop for a 3.2pJ/bit 24Gb/s QPSK Coherent Optical Receiver
A. Abdelrahman1, M. G. Ahmed1,2, M. A. Khalil1, M. B. Younis1, K-S. Park1, P. K. Hanumolu1
1University of Illinois, Urbana, IL; 2now at Ain Shams University, Cairo, Egypt

Break 10:00 AM

Ideas for the Future

Session Chair: Sudip Shekhar, University of British Columbia, Vancouver, Canada
Session Co-Chair: Daniel Morris, Meta, Menlo Park, CA
10:15 AM
13.1 Crystalline Oxide Semiconductor-Based 3D Bank Memory System for Endpoint Artificial
Intelligence with Multiple Neural Networks Facilitating Context Switching and Power
Gating
Y. Yakubo1, K. Furutani1, K. Toyotaka1, H. Katagiri1, M. Fujita1, M. Kozuma1, Y. Ando1, Y. Kurokawa 1,
T. Nakura2, S. Yamazaki1
1Semiconductor Energy Laboratory, Atsugi, Japan; 2Fukuoka University, Fukuoka, Japan

10:45 AM
13.2 A 47nW Mixed-Signal Voice Activity Detector (VAD) Featuring a Non-Volatile
Capacitor-ROM, a Short-Time CNN Feature Extractor and an RNN Classifier
J. Lin1, K-F. Un1, W-H. Yu1, P-I. Mak1, R. P. Martins1,2
1University of Macau, Macau, China
2Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal

11:15 AM
13.3 A Triturated Sensing System
N. Miura1, K. Naruse1, J. Shiomi1, Y. Midoh1, T. Hirose1, T. Okidono2, T. Miki2, M. Nagata2
1Osaka University, Suita, Japan; 2Kobe University, Kobe, Japan

11:30 AM
13.4 A Self-Programming PUF Harvesting the High-Energy Plasma During Fabrication
K. Naruse, T. Ueda, J. Shiomi, Y. Midoh, N. Miura
Osaka University, Suita, Japan
11:45 AM
13.5 Subtractive Photonic Waveguide-Coupled Photodetectors in 180nm Bulk CMOS
C. Ives, A. Hajimiri
California Institute of Technology, Pasadena, CA
12:00 PM
13.6 A Silicon Photonic Reconfigurable Optical Analog Processor (SiROAP) with a 4×4
Optical Mesh
M. J. Shawon, V. Saxena
University of Delaware, Newark, DE
Conclusion 12:15 PM

29
SESSIONS 14 & 15 Tuesday February 21st, 1:30 PM
Digital Techniques for Clocking and Power Management
Session Chair: Arijit Raychowdhury, Georgia Institute of Technology, Atlanta, GA
Session Co-Chair: Eric Fang, Mediatek, Hsinchu City, Taiwan
1:30 PM
14.1 A Fractional-N Digital MDLL with Injection Error Scrambling and Background
Third-Order DTC Delay Equalizer Achieving –67dBc Fractional Spur
Q. Zhang1, H-C. Cheng1, S. Su1,2, M. S-W. Chen1
1University of Southern California, Los Angeles, CA; 2University of Waterloo, Waterloo, Canada

2:00 PM
14.2 A 10-to-300MHz Fractional Output Divider with -80dBc Worst-Case Fractional Spurs
Using Auxiliary-PLL-Based Background 0th/1st/2nd-Order DTC INL Calibration
Y. Yang, W. Deng, A. Yan, H. Jia, J. Gong, Z. Wang, B. Chi, Tsinghua University, Beijing, China
2:15 PM
14.3 A Digital Low-Dropout (LDO) Linear Regulator with Adaptive Transfer Function
Featuring 125A/mm2 Power Density and Autonomous Bypass Mode
M. Zelikson, K. Luria, L. Gil, Y. Brown, V. Goldenbeg, D. Kasif, E. Hlees, A. Vinichuk
Intel, Haifa, Israel
2:45 PM
14.4 A Monolithic 26A/mm2 Imax, 88.5% Peak-Efficiency Continuously Scalable
Conversion-Ratio Switched-Capacitor DC-DC Converter
N. Butzen1, H. Krishnamurthy1, Z. Ahmed1, S. Weng1, K. Ravichandran1, M. Zelikson2, J. Tschanz1,
J. Douglas3, 1Intel, Hillsboro, OR; 2Intel, Haifa, Israel; 3Intel, Chandler, AZ
Break 3:00 PM

IOT & Security

Session Chair: Chiraag Juvekar, Apple, Mountain View, CA
Session Co-Chair: Ingrid Verbauwhede, KU Leuven, Leuven, Belgium
3:15 PM
15.1 A Self-Powered SoC with Distributed Cooperative Energy Harvesting and Multi-Chip
Power Management for System-in-Fiber
X. Liu1, D. S. Truesdell1, O. Faruqe1, L. Parameswaran2, M. Rickley2, A. Kopanski2, L. Cantley2,
A. Coon2, M. Bernasconi2, T. Wang2, B. H. Calhoun1
1University of Virginia, Charlottesville, VA; 2MIT Lincoln Laboratory, Lexington, MA

3:45 PM
15.2 A 2.19μW Self-Powered SoC with Integrated Multimodal Energy Harvesting,
Dual-Channel up to -92dBm WRX and Energy-Aware Subsystem
C. J. Lukas1, F. B. Yahya1, K-K. Huang2, J. Boley2, D. S. Truesdell1, J. Breiholz1, A. Wokhlu2, K. Craig1,
J. K. Brown3, A. Fitting2, W. Moore2, A. Shih2, A. Wang2, A. Gravel2, D. D. Wentzloff3, B. H. Calhoun1
1Everactive, Charlottesville, VA; 2Everactive, Santa Clara, CA; 3Everactive, Ann Arbor, MI

4:15 PM
15.3 A 33kDMIPS 6.4W Vehicle Communication Gateway Processor Achieving 10Gbps/W
Network Routing, 40ms CAN Bus Start-Up and 1.4mW Standby Power
K. Shimada, K. Sano, K. Fukuoka, H. Morita, M. Daito, T. Kamei, H. Hamasaki, Y. Shimazaki
Renesas Electronics, Tokyo, Japan
4:45 PM
15.4 A 28nm 68MOPS 0.18μJ/Op Paillier Homomorphic Encryption Processor with Bit-Serial
Sparse Ciphertext Computing
G. Shi1, Z. Tan1, D. Cao2, J. Cai1, W. Zhang3, Y. Wu3, K. Ma1
1Tsinghua University, Beijing, China; 2Xi’an JiaoTong University, Xi’an, China

3Polar Bear Tech, Xi’an, China

5:15 PM
15.5 A 100Gbps Fault-Injection Attack Resistant AES-256 Engine with 99.1-to-99.99% Error
Coverage in Intel 4 CMOS
R. Kumar1, A. Varna2, C. Tokunaga1, S. Taneja1, V. De1, S. Mathew1
1Intel, Hillsboro, OR; 2Intel, Chandler, AZ

Conclusion 5:30 PM

30
SESSION 16 Tuesday February 21st, 1:30 PM
Efficient Compute-In-Memory-Based Processors for ML
Session Chair: Jae-sun Seo, Arizona State University, Tempe, AZ
Session Co-Chair: Yongpan Liu, Tsinghua University, Beijing, China

1:30 PM
16.1 MulTCIM: A 28nm 2.24μJ/Token Attention-Token-Bit Hybrid Sparse Digital CIM-Based
Accelerator for Multimodal Transformers
F. Tu, Z. Wu, Y. Wang, W. Wu, L. Liu, Y. Hu, S. Wei, S. Yin
Tsinghua University, Beijing, China

2:00 PM
16.2 A 28nm 53.8TOPS/W 8b Sparse Transformer Accelerator with In-Memory Butterfly Zero
Skipper for Unstructured-Pruned NN and CIM-Based Local-Attention-Reusable Engine
S. Liu1, P. Li1, J. Zhang1, Y. Wang1, H. Zhu1, W. Jiang1, S. Tang2, C. Chen1,3, Q. Liu1, M. Liu1
1Fudan University, Shanghai, China

2BIRENTECH, Shanghai, China; 3Peng Cheng Laboratory, Shenzhen, China

2:30 PM
16.3 A 28nm 16.9-300TOPS/W Computing-in-Memory Processor Supporting Floating-Point
NN Inference/Training with Intensive-CIM Sparse-Digital Architecture
J. Yue1, C. He1, Z. Wang1, Z. Cong1, Y. He2, M. Zhou2, W. Sun2, X. Li2, C. Dou1, F. Zhang1, H. Yang2,
Y. Liu2, M. Liu1
1Institute of Microelectronics of the Chinese Academy of Sciences, Beijing, China

2Tsinghua University, Beijing, China

Break 3:00 PM

3:15 PM
16.4 TensorCIM: A 28nm 3.7nJ/Gather and 8.3TFLOPS/W FP32 Digital-CIM Tensor
Processor for MCM-CIM-Based Beyond-NN Acceleration
F. Tu, Y. Wang, Z. Wu, W. Wu, L. Liu, Y. Hu, S. Wei, S. Yin
Tsinghua University, Beijing, China

3:45 PM
16.5 DynaPlasia: An eDRAM In-Memory-Computing-Based Reconfigurable Spatial
Accelerator with Triple-Mode Cell for Dynamic Resource Switching
S. Kim, Z. Li, S. Um, W. Jo, S. Ha, J. Lee, S. Kim, D. Han, H-J. Yoo
Korea Advanced Institute of Science and Technology, Daejeon, Korea

4:15 PM
16.6 A Nonvolatile AI-Edge Processor with 4MB SLC-MLC Hybrid-Mode ReRAM
Compute-in-Memory Macro and 51.4-251TOPS/W
W-H. Huang*1, T-H. Wen*1,2, J-M. Hung*1, W-S. Khwa*2, Y-C. Lo1, C-J. Jhang1,2, H-H. Hsu1,
Y-H. Chin1, Y-C. Chen1, C-C. Lo1, R-S. Liu1, K-T. Tang1, C-C. Hsieh1, Y-D. Chih3, T-Y. Chang3,
M-F. Chang1,2
1National Tsing Hua University, Hsinchu, Taiwan; 2TSMC Corporate Research, Hsinchu, Taiwan

3TSMC, Hsinchu, Taiwan; *Equally Credited Authors (ECAs)

4:45 PM
16.7 A 40-310TOPS/W SRAM-Based All-Digital Up to 4b In-Memory Computing Multi-Tiled
NN Accelerator in FD-SOI 18nm for Deep-Learning Edge Applications
G. Desoli*1, N. Chawla*2, T. Boesch*3, M. Ayodhyawasi*2, H. Rawat2, H. Chawla2, A. VS2, P. Zambotti4,
A. Sharma2, C. Cappetta1, M. Rossi1, A. De Vita1, F. Girardi1
1STMicroelectronics, Cornaredo, Italy; 2STMicroelectronics, Noida, India

3STMicroelectronics, Geneva, Switzerland; 4STMicroelectronics, Agrate, Italy

*Equally Credited Authors (ECAs)

Conclusion 5:15 PM

31
SESSION 17 Tuesday February 21st, 1:30 PM
High-Speed Data Converters
Session Chair: John Keane, Keysight Technologies, Santa Clara, CA
Session Co-Chair: Ying-Zu Lin, Mediatek, HsinChu, Taiwan

1:30 PM
17.1 A 2×-Interleaved 9b 2.8GS/s 5b/cycle SAR ADC with Linearized Configurable V2T Buffer
Achieving >50dB SNDR at 3GHz Input
H. Zhao1, M. Zhang1, Y. Zhu1, C-H. Chan1, R. P. Martins1,2
1University of Macau, Macao, China

2Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal

2:00 PM
17.2 An 8b 1.0-to-1.25GS/s 0.7-to-0.8V Single-Stage Time-Based Gated-Ring-Oscillator
ADC with 2× Interpolating Sense-Amplifier-Latches
A. S. Yonar1,2, P. A. Francese1, M. Brändli1, M. Kossel1, M. Prathapan1, T. Morf1, A. Ruffino1, T. Jang2
1IBM Zurich Research Laboratory, Zurich, Switzerland

2ETH Zürich, Zurich, Switzerland

2:30 PM
17.3 A 14b 16GS/s Time-Interleaving Direct-RF Synthesis DAC with T-DEM Achieving -70dBc
IM3 up to 7.8GHz in 7nm
W-H. Tseng*1, W. Lin*1, C-W. Hsu1, C-Y. Huang1, Y-S. Lin1, H-Y. Huang1, H. Chen1, S-H. Liao1,
K-D. Chen1, J. Strange2, G. Manganaro3
1MediaTek, HsinChu, Taiwan; 2MediaTek, Kent, United Kingdom; 3MediaTek, Woburn, MA

*Equally Credited Authors (ECAs)

Break 3:00 PM

3:15 PM
17.4 A 750mW 24GS/s 12b Time-Interleaved ADC for Direct RF Sampling in Modern
Wireless Systems
S. Santhosh Kumar1, M. Kudo1, V. Cretu1, A. Morineau1, A. Matsuda2, M. Yoshida2, M. Marutani2,
A. H. Maniyar1, J. Kumar1
1Socionext Europe, Maidenhead, United Kingdom

2Socionext, Yokohama, Japan

3:45 PM
17.5 A 10mW 10-ENOB 1GS/s Ring-Amp-Based Pipelined TI-SAR ADC with Split MDAC and
Switched Reference Decoupling Capacitor
M. Zhan, L. Jie, N. Sun
Tsinghua University, Beijing, China

4:15 PM
17.6 A 7b 4.5GS/s 4× Interleaved SAR ADC with Fully On-Chip Background Timing Skew
Calibration
Y-H. Wang, S-J. Chang
National Cheng Kung University, Tainan, Taiwan

4:45 PM
17.7 A 3mW 2.7GS/s 8b Subranging ADC with Multiple-Reference-Embedded Comparators
J-C. Wang, T-H. Kuo
National Cheng Kung University, Tainan, Taiwan

5:00 PM
17.8 A Single-Channel 10GS/s 8b >36.4dB SNDR Time-Domain ADC Featuring
Loop-Unrolled Asynchronous Successive Approximation in 28nm CMOS
Q. Chen1, Y. Liang*1, C. C. Boon1, Q. Liu2
1Nanyang Technological University, Singapore, Singapore

2Kun Gao Xinxin Technologies, Singapore, Singapore

*Equally Credited Authors (ECAs)

Conclusion 5:15 PM

32
SESSIONS 18 & 19 Tuesday February 21st, 1:30 PM
mm-Wave & sub-THz for Wireless and Sensing
Session Chair: Jane Gu, University of California, Davis, Davis, CA
Session Co-Chair: Giuseppe Gramegna, imec, Leuven, Belgium
1:30 PM
18.1 A W-Band Transceiver Array with 2.4GHz LO Synchronization Enabling Full Scalability
for FMCW Radar
J. Zhang, A. Singhvi, S. S. Ahmed, A. Arbabian, Stanford University, Stanford, CA
2:00 PM
18.2 A 128Gb/s 1.95pJ/b D-Band Receiver with Integrated PLL and ADC in 22nm FinFET
A. Agrawal1, A. Whitcombe2, W. Shin3, R. Bhat1, S. Kundu1, P. Sagazio1, H. Chandrakumar1, T. Brown1,
B. Carlton1, C. Hull4, S. Callender1, S. Pellerano1
1Intel, Hillsboro, OR; 2Intel, Santa Clara, CA; 3now with Apple, Sunnyvale, CA

4now with Amazon, Redmond, WA

2:30 PM
18.3 71-to-89GHz 12Gb/s Double-Edge-Triggered Quadrature RFDAC with LO Leakage
Suppression Achieving 20.5dBm Peak Output Power and 20.4% System Efficiency
B. Yang, Z. Deng, H. J. Qian, X. Luo
University of Electronic Science and Technology of China, Chengdu, China
2:45 PM
18.4 A 4×4 607GHz Harmonic Injection-Locked Receiver Array Achieving 4.4pW/√Hz NEP
in 28nm CMOS
A. De Vroede, P. Reynaert, KU Leuven ESAT-MICAS, Heverlee, Belgium
Break 3:00 PM

5G and Satcom: Receivers and Transmitters

Session Chair: Venumadhav Bhagavatula, Samsung Semiconductor , San Jose, CA
Session Co-Chair: Alireza Zolfaghari, Broadcom, Irvine, CA
3:15 PM
19.1 A 300MHz-BW, 27-to-38dBm In-Band OIP3 sub-7GHz Receiver for 5G Local Area Base
Station Applications
M. A. Montazerolghaem, L. C. N. de Vreede, M. Babaie
Delft University of Technology, Delft, The Netherlands
3:45 PM
19.2 An Interferer-Tolerant Harmonic-Resilient Receiver with >+10dBm 3rd-Harmonic
Blocker P1dB for 5G NR Applications
S. Araei, S. Mohin, N. Reiskarimian, Massachusetts Institute of Technology, Cambridge, MA
4:15 PM
19.3 A 2.95mW/element Ka-band CMOS Phased-Array Receiver Utilizing On-Chip
Distributed Radiation Sensors in Low-Earth-Orbit Small Satellite Constellation 
X. Fu1, D. You1, X. Wang1, M. Ide1, Y. Zhang1, J. Sakamaki1, A. A. Fadila1, Z. Li1, Y. Wang1, J. Sudo2,
M. Higaki2, S. Inoue2, T. Eishima2, T. Tomura1, J. Pang1, H. Sakai1, K. Okada1, A. Shirane1
1Tokyo Institute of Technology, Tokyo, Japan; 2Axelspace, Tokyo, Japan

4:45 PM
19.4 A Small-Satellite-Mounted 256-Element Ka-Band CMOS Phased-Array Transmitter
Achieving 63.8dBm EIRP Under 26.6W Power Consumption Using Single/Dual Circular
Polarization Active Coupler
D. You1, X. Fu1, X. Wang1, Y. Gao1, W. Wang1, J. Sakamaki1, H. Herdian1, S. Kato1, M. Ide1, Y. Zhang1,
A. A. Fadila1, Z. Li1, C. Wang1, Y. Wang1, J. Sudo2, M. Higaki2, N. Kawaguchi2, M. Nitta2, S. Inoue2,
T. Eishima2, T. Tomura1, J. Pang1, H. Sakai1, K. Okada1, A. Shirane1
1Tokyo Institute of Technology, Tokyo, Japan; 2Axelspace, Tokyo, Japan

Conclusion 5:15 PM

33
SESSION 20 Tuesday February 21st, 1:30 PM
GaN Power Conversion
Session Chair: Patrik Arno, ST Microelectronics, Grenoble, France
Session Co-Chair: Saurav Bandyopadhyay, Texas Instruments, Dallas, TX
1:30 PM
20.1 A High Common-Mode Transient Immunity GaN-on-SOI Gate Driver for High dV/dt SiC
Power Switch
S-Y. Li1, W-C. Hung1, T-W. Wang1, Y-T. Hsu1, K-H. Chen1, K-L. Zheng1,2, Y-H. Lin3, S-R. Lin3, T-Y. Tsai3
1National Yang Ming Chiao Tung University, Hsinchu, Taiwan
2Chip-GaN Power Semiconductor, Hsinchu, Taiwan
3Realtek Semiconductor, Hsinchu, Taiwan

2:00 PM
20.2 A Condition-Adaptive Δf3-EMI Control GaN Switching Regulator With Modulation
Frequency Envelope Tracking For Full-Spectrum Automotive CISPR 25 Compliance
L. Du1, D. Yan1,2, D. B. Ma1
1University of Texas at Dallas, Richardson, TX
2Texas Instruments, Dallas, TX

2:30 PM
20.3 A GaN Gate Driver with On-Chip Adaptive On-time Controller and Negative Current
Slope Detector
S-Y. Lin1, S-Y. Lin1, S-H. Hung1, T-W. Wang1, C-H. Li1, C-L. Go1, S-C. Huang1, K-H. Chen1,
K-L. Zheng1,2, Y-H. Lin3, S-R. Lin3, T-Y. Tsai3
1National Yang Ming Chiao Tung University, Hsinchu, Taiwan
2Chip-GaN Power Semiconductor, Hsinchu, Taiwan
3Realtek Semiconductor, Hsinchu, Taiwan

2:45 PM
20.4 Multiple-Phase Accelerated Current Control in Bidirectional Energy Transfer of
Automotive High-Voltage and Low-Voltage Batteries
T-W. Wang1, S-Y. Li1, S-H. Hung1, T-Y. Wu1, C-Y. Chen1, P-J. Chiu1, K-H. Chen1, K-L. Zheng1,2,
Y-H. Lin3, T-Y. Tsai3, S-R. Lin3
1National Yang Ming Chiao Tung University, Hsinchu, Taiwan
2Chip-GaN Power Semiconductor, Hsinchu, Taiwan
3Realtek Semiconductor, Hsinchu, Taiwan

Break 3:00 PM

34
SESSION 21 Tuesday February 21st, 3:15 PM
Emerging Sensing Systems and IOT
Session Chair: Kaushik Sengupta, Princeton University, Princeton, NJ
Session Co-Chair: Milin Zhang, Tsinghua University, beijing, China
3:15 PM
21.1 A 65nm CMOS Living-Cell Dynamic Fluorescence Sensor with 1.05fA Sensitivity at
600/700nm Wavelengths
F. Aghlmand1, C. Hu1,2, S. Sharma1, K. K. Pochana1, R. M. Murray1, A. Emami1
1California Institute of Technology, Pasadena, CA
2Texas A&M University, College Station, TX

3:45 PM
21.2 A 22μW Peak Power Multimodal Electrochemical Sensor Interface IC for Bioreactor
Monitoring
Q. Lin1, W. Sijbers1, C. Avdikou1, D. Gomez1,2, D. Biswas1, S. Sneha3, A. Malissovas3, B. Tacca3,
N. V. Helleputte1
1imec, Leuven, Belgium
2Now with MPS Spain, Barcelona, Spain
3imec - Holst Centre, Eindhoven, The Netherlands

4:00 PM
21.3 A CMOS Multi-Functional Biosensor Array for Rapid Low-Concentration Analyte
Detection with On-Chip DEP-Assisted Active Enrichment and Manipulation with No
External Electrodes
D. Lee1, D. Jung2, F. Jiang1, G. V. Junek3, J. Park4, H. Liu1, Y. Kong1, Y. Kim1, J. Wang1, H. Wang1,3
1ETH Zürich, Zurich, Switzerland
2Qualcomm, San Jose
3Georgia Institute of Technology, Atlanta, GA
4Apple, San Diego, CA

4:15 PM
21.4 A 263GHz 32-Channel EPR-on-a-Chip Injection-Locked VCO-Array
A. Chu*1, M. Kern*1, K. Khan1, K. Lips2, J. Anders1,3
1University of Stuttgart, Stuttgart, Germany
2Helmholtz-Zentrum Berlin für Materialien und Energie, Berlin, Germany
3Institute for Microelectronics Stuttgart (IMS CHIPS), Stuttgart, Germany

*Equally Credited Authors (ECAs)

4:30 PM
21.5 An LTE-Harvesting BLE-to-WiFi Backscattering Chip for Single-Device RFID-Like
Interrogation
S-K. Kuo*, M. Dunna*, H. Lu, A. Agarwal, D. Bharadia, P. P. Mercier
University of California, San Diego, CA
*Equally Credited Authors (ECAs)
5:00 PM
21.6 ASIL-D Compliant Battery Monitoring IC with High Measurement Accuracy and Robust
Communication
J-K. Lee1,2, S. Woo2, W. Jeong2, K-S. Oh2, D. Kim2, Y. Ko2, J-Y. Jeon2, J. Lee2, Y-S. Son2, S-G. Lee1,
K. Kwon1
1Korea Advanced Institute of Science and Technology, Daejeon, Korea
2Autosilicon, Daejeon, Korea

Conclusion 5:30 PM

35
 TIMETABLE OF ISSCC 2023 SESSIONS
ISSCC 2023 • SUNDAY FEBRUARY 19TH • Q&A IN-PERSON TUTORIALS
Tutorials
10:20 AM - T2: Bridging RF and Power:
10:00 AM - T1: Fundamentals of Frequency References 10:40 AM - T3: Fundamentals of Data Converters
An Introduction to Envelope Tracking Systems and Building Blocks
11:00 AM - T4: Automotive System Design 11:20 AM - T5: All-Digital PLLs: From Fundamental Concepts to Future Trends 11:40 AM - T6: Solid-State CMOS LiDAR Sensors

1:20 PM - T8: Role of Current-Mode Passive Mixers and N-Path Filters 1:40 PM - T9: Physical-Layer Security for Latency- and Energy-Constrained
1:00 PM - T7: Fundamentals of Ultra-Low Voltage Embedded Memory Design
in RF Receivers Integrated Systems
2:20 PM - T11: Digital Equalization and Timing Recovery Techniques for ADC-DSP
2:00 PM - T10: The Art of mm-Wave Design and Layout 2:40 PM - T12: Extending Processor Cores for Machine Learning
Based Highspeed Links
ISSCC 2023 • SUNDAY FEBRUARY 19TH
Forums
F2: The Power Behind Electrical Vehicles – Accelerating the Future
8:00 AM F1: Transceivers for Exascale: Towards Tbps/mm and Sub-pJ/bit of Automotive Technology F3: Efficient Wireless Power Amplification and Linearization
Events Below in Bold Box are Included with your Conference Registration
Evening Events
3:00 - 5:00 PM: Mentoring Session / Networking Bingo Event 8:00 PM – EE1: Student Research Preview: Short Presentations with Poster Session

ISSCC 2023 • MONDAY FEBRUARY 20 TH

• PAPER SESSIONS
8:30 AM Session 1: Plenary Session
Session 6:
Session 2: Session 3: Session 4: Session 5:
1:30 PM Advanced Wireline Links and
Digital Processors Amplifiers and Oscillators Frequency Synthesizers Image Sensors
Techniques
12noon to 7:00 PM – Book Displays • 5:00 PM to 7:00 PM – Demonstration Session • 5:15 PM – Author Interviews • Social Hour
Evening Events
8:00 PM EE2: Integrated Circuits in an Interconnected World EE3: The Path to Sustainable IC Ecosystems
ISSCC 2023 • TUESDAY FEBRUARY 21 ST
• PAPER SESSIONS
Session 8: Session 12:
GHz-to-Millimeter Wave Frequency Generation
Session 10: Session 11: High Performance Optical Receivers
Session 7:
8:30 AM
SRAM Compute-In-Memory Session 9: Pipelined and Noise-Shaping ADCs USB and Compute Power Delivery
Highlighted Chip Releases: Session 13:
Digital and Machine Learning Processors Ideas for the Future
Session 14: Session 18:
mm-Wave & sub-THz for Wireless Session 20:
Digital Techniques for Clocking and Session 16: GaN Power Conversion
Session 17: and Sensing
1:30 PM Power Management Efficient Compute-In-Memory
High-Speed Data Converters Session 19: Session 21:
Session 15: Based Processors for ML 5G and Satcom:
IOT & Security Emerging Sensing Systems and IOT
Receivers and Transmitters
10:00 AM to 7:00 PM – Book Displays • 5:00 PM to 7:00 PM – Demonstration Session • 5:15 PM – Author Interviews
Evening Events
8:00 PM EE4: The Smartest Designer in The Universe, Post-Pandemic! EE5: What will be the Essential Skills for IC Designers in the Next Decade?
ISSCC 2023 • WEDNESDAY FEBRUARY 22ND • PAPER SESSIONS
Session 24: Session 26:
Session 22: Session 23: THz Signal Generation Display and User Interaction Technologies Session 28:
8:30 AM High-Density Memories
Heterogenous ML Accelerators Analog Sensor Interfaces Session 25: Session 27:
Innovations from Outside the (ISSCC) Box and High-Speed Interface
RF Transceiver Building Blocks
Session 33:
Session 29: Session 31: Session 32: Non-Volatile Memory
Session 30: and Compute-In-Memory
1:30 PM Digital Accelerators and Circuit Energy-Efficient Radios for UWB, Intelligent Biomedical Circuits and
Power Management Techniques
Techniques BMI, and IoT Systems Systems Session 34:
Cryo-CMOS for Quantum Computing
10:00 AM to 3:00 PM – Book Displays • 5:15 PM – Author Interviews
ISSCC 2023 • THURSDAY FEBRUARY 23RD
Short Course: F4: F5: F6: F7:
Principles of Quantum Computing and Advancing Technologies for Extreme Data Converters The Future of Heterogeneous Advanced Circuits and Technologies
8:00 AM
the Application of Cryoelectronics to Extended Reality (XR) to Make the and Their Peripherals Multi-Core Architectures for AI for Wearable and Implantable
Qubit Control and Readout “Metaverse” Possible and Other Specialized Processing Devices

36 37
 Demonstration Session 2, Tuesday, February 21st, 5:00-7:00 PM
This year, the Demonstration Session extending in selected regular papers, both Academic and Industrial, will take place
on Monday February 20th, and Tuesday February 21st, from 5 pm until 7 pm in the Golden Gate Hall. These demonstrations
will feature real-life applications made possible by new ICs presented at ISSCC 2023, as noted by the symbol DS2

6.2 A 4.63pJ/b 112Gb/s DSP-Based PAM-4 Transceiver for a Large-Scale Switch in 5nm FinFET
15.2 A 2.19μW Self-Powered SoC with Integrated Multimodal Energy Harvesting,Dual-Channel up to
-92dBm WRX and Energy-Aware Subsystem
15.5 A 100Gbps Fault-Injection Attack Resistant AES-256 Engine with 99.1-to-99.99% Error Coverage
in Intel 4 CMOS
17.1 A 2×-Interleaved 9b 2.8GS/s 5b/cycle SAR ADC with Linearized Configurable V2T Buffer Achieving
>50dB SNDR at 3GHz Input
17.6 A 7b 4.5GS/s 4× Interleaved SAR ADC with Fully On-Chip Background Timing Skew Calibration

19.4 A Small-Satellite-Mounted 256-Element Ka-Band CMOS Phased-Array Transmitter Achieving

63.8dBm EIRP Under 26.6W Power Consumption Using Single/Dual Circular Polarization Active
Coupler

20.1 A High Common-Mode Transient Immunity GaN-on-SOI Gate Driver for High dV/dt SiC Power
Switch
22.6 ANP-I: A 28nm 1.5pJ/SOP Asynchronous Spiking Neural Network Processor Enabling
Sub-0.1μJ/Sample On-Chip Learning for Edge-AI Applications
22.7 DL-VOPU: An Energy-Efficient Domain-Specific Deep-Learning-Based Visual Object Processing
Unit Supporting Multi-Scale Semantic Feature Extraction for Mobile Object Detection/Tracking
Applications
22.8 A 0.81mm2 740μW Real-Time Speech Enhancement Processor Using Multiplier-Less PE Arrays
for Hearing Aids in 28nm CMOS
23.6 A 2.98pJ/Conversion 0.0023mm2 Dynamic Temperature Sensor with Fully On-Chip Corrections
25.5 A 1-to-5GHz All-Passive Frequency-Translational 4th-Order N-path Filter with Low-Power Clock
Boosting for High Linearity and Relaxed Pdc-Frequency Trade-Off
29.1 A 32.5mW Mixed-Signal Processing-in-Memory-Based k-SAT Solver in 65nm CMOS with 74.0%
Solvability for 30-Variable 126-Clause 3-SAT Problems
29.2 Snap-SAT: A One-Shot Energy-Performance-Aware All-Digital Compute-in-Memory Solver for
Large-Scale Hard Boolean Satisfiability Problems
29.5 A 73.53TOPS/W 14.74TOPS Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for
Hybrid Frame and Event-Based Target Tracking
29.8 A Sub-0.8pJ/b 16.3Gbps/mm2 Universal Soft-Detection Decoder Using ORBGRAND in 40nm CMOS
30.4 A 3.7V-to-1kV Chip-Cascaded Switched-Capacitor Converter with Auxiliary Boost Achieving >96%
Reactive Power Efficiency for Electrostatic Drive Applications
30.10 Single Chip, Qi Compliant, 40W Wireless Power Transmission Controller using RMS Coil
Current Sensing and Adaptive ZVS for 4dB EMI and up to 1.7% Efficiency Improvements
31.5 A Passive Bidirectional BLE Tag Demonstrating Battery-Free Communication in
Tablet/Smartphone-to-Tag, Tag-to-Tablet/Smartphone, and Tag-to-Tag Modes
32.1 A Behind-The-Ear Patch-Type Mental Healthcare Integrated Interface with 275-Fold Input
Impedance Boosting and Adaptive Multimodal Compensation Capabilities
32.2 A Stimulus-Scattering-Free Pixel-Sharing Sub-Retinal Prosthesis SoC with 35.8dB Dynamic
Range Time-Based Photodiode Sensing and Per-Pixel Dynamic Voltage Scaling
32.6 SciCNN: A 0-Shot-Retraining Patient-Independent Epilepsy-Tracking SoC
33.3 A 9Mb HZO-based Embedded FeRAM Macro with a 1012-Cycle Endurance, a 5ns Read and a
7ns Write Time using ECC-Assisted Data Refresh and an Offset-Canceled Sense Amplifier
34.1 THz Cryo-CMOS Backscatter Transceiver: A Contactless 4 Kelvin-300 Kelvin Data Interface

38
EVENING EVENTS Tuesday February 21st, 8:00 PM
EE4:
The Smartest Designer in the Universe, Post-Pandemic!
Organizer: Denis Daly, Apple, Cambridge, MA
Co-Organizers: Shuhei Amakawa, Hiroshima University, Higashihiroshima, Japan
Negar Reiskarimian, MIT, Cambridge, MA
Vito Giannini, Uhnder, Austin, TX
Champion: Tim Piessens, ICsense, Leuven, Belgium
Moderator: Bram Nauta, University of Twente, Enschede, The Netherlands
At ISSCC 2020 there was a battle of epic proportions between industry, academia and students to determine
who was the smartest designer in the universe. Industry came out victorious. Now, at ISSCC 2023, as we
return to an in-person conference, academia and students have their chance to get their revenge and set
the record straight. In this interactive quiz show, three teams representing industry, academia and students
will compete for the honor and the prestigious title: “The Smartest Designer in the Universe”. In several
rounds, the contestants will solve questions and puzzles covering all parts of electrical engineering. They
will baffle you with their knowledge, surprise you with their wit and entertain you with their to the point
remarks. This all topped with a gentle sauce of irony since the smartest designer in the universe should be
smart enough to appreciate the special relativity of it all. Join this session not only to support your own
team but enroll in the game. Everybody will be able to actively participate using an app.
Team Academia:
Kofi Makinwa, Delft University of Technology, Delft, The Netherlands
Azita Emami, Caltech, Pasadena, CA
Howard Luong, HKUST, Hong Kong, China
Team Industry:
Farhana Sheikh, Intel, Hillsboro, OR
Rozi Roufoogaran, NXP, Irvine, CA
Subhashish Mukherjee, Texas Instruments, Bangalore, Karnataka, India

EE5:
What will be the Essential Skills for IC Designers in the Next Decade?
Organizer: Mozhgan Mansuri, Intel, Hillsboro, OR
Co-Organizers: Wei-Zen Chen, National Yang Ming Chiao Tung University,
Hsinchu, Taiwan
Byungsub Kim, Pohang University of Science and Technology,
Pohang, Korea
Visvesh Sathe, Georgia Institute of Technology, Atlanta, GA
Giuseppe Gramegna, imec, Leuven, Belgium
Moderator: Mozhgan Mansuri, Intel, Hillsboro, OR

Based on emerging trends in design methodology such as AI for IC design and verification, this session of
academic and industry leaders will predict and discuss how future design automation will change the way
IC designers work in the next decade. Will more and more of IC design be automated by then? Is our field
shrinking? Are we attracting and training enough students to learn IC design to meet potential industry
needs? Join this special evening topic session to get the perspective of industry and academic leaders in
IC design.
Panelists: Mike Flynn, University of Michigan, Ann Arbor, MI
Hoi-Jun Yoo, KAIST, Daejeon, Korea
Alvin Loke, NXP Semiconductors, San Diego, CA
Laura Smith, AMD, Austin, TX

39
SESSION 22 Wednesday February 22nd, 8:30 AM
Heterogeneous ML Accelerator
Session Chair: Rangharajan Venkatesan, NVIDIA, Santa Clara, CA
Session Co-Chair: Sophia Shao, UC Berkeley, Berkeley, CA
8:30 AM
22.1 A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-
Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing
F. Conti1, D. Rossi1, G. Paulin2, A. Garofalo1, A. Di Mauro2, G. Rutishauer2, G. Ottavi1, M. Eggimann2,
H.  Okuhara1, V.  Huard3, O.  Montfort3, L.  Jure3, N.  Exibard3, P.  Gouedo3, M.  Louvat3, E.  Botte3,
L. Benini1,2, 1University of Bologna, Bologna, Italy; 2ETH Zürich, Zürich, Switzerland
3Dolphin Design, Meylan, France

9:00 AM
22.2 A 28nm 2D/3D Unified Sparse Convolution Accelerator with Block-Wise Neighbor
Searcher for Large-Scaled Voxel-Based Point Cloud Network
W. Sun1, X. Feng2, C. Tang2, S. Fan2, Y. Yang2, J. Yue3, Z. Du4, W. Zhao4, H. Yang2, Y. Liu2
1
Tsinghua Shenzhen International Graduate School, Shenzhen, China
2
Tsinghua University, Beijing, China; 3Chinese Academy of Sciences, Beijing, China
4
Pi2star Technology, Beijing, China
9:30 AM
22.3 A 127.8TOPS/W Arbitrarily Quantized 1-to-8b Scalable-Precision Accelerator for
General-Purpose Deep Learning with Reduction of Storage, Logic and Latency Waste
S. Moon1, H-G. Mun1, H. Son2, J-Y. Sim1
1Pohang University of Science and Technology, Pohang, Korea
2Gyeongsang National University, Jinju, Korea

Break 10:00 AM
10:15 AM
22.4 A 28nm 11.2TOPS/W Hardware-Utilization-Aware Neural-Network Accelerator with
Dynamic Dataflow
C-Y. Du1, C-F. Tsai2, W-C. Chen3, L-Y. Lin3, N-S. Chang3, C-P. Lin3, C-S. Chen3, C-H. Yang1
1National Taiwan University, Taipei, Taiwan; 2Delta Electronics, Taipei, Taiwan
3Taiwan Semiconductor Research Institute, Hsinchu, Taiwan

10:45 AM
22.5 C-DNN: A 24.5-85.8TOPS/W Complementary-Deep-Neural-Network Processor with
Heterogeneous CNN/SNN Core Architecture and Forward-Gradient-Based Sparsity
Generation
S. Kim, S. Kim, S. Hong, S. Kim, D. Han, H-J. Yoo
Korea Advanced Institute of Science and Technology, Daejeon, Korea
11:15 AM
22.6 ANP-I: A 28nm 1.5pJ/SOP Asynchronous Spiking Neural Network Processor Enabling
Sub-0.1μJ/Sample On-Chip Learning for Edge-AI Applications
J. Zhang1, D. Huo1, J. Zhang1, C. Qian1, Q. Liu1, L. Pan1, Z. Wang1, N. Qiao2, K-T. Tang3, H. Chen1
1Tsinghua University, Beijing, China; 2SynSense, Chengdu, China
3National Tsing Hua University, Hsinchu, Taiwan

11:30 AM
22.7 DL-VOPU: An Energy-Efficient Domain-Specific Deep-Learning-based Visual Object
Processing Unit Supporting Multi-Scale Semantic Feature Extraction for Mobile Object
Detection/Tracking Applications
Y. Gong, T. Zhang, H. Guo, X. Liu, J. Zheng, H. Wu, C. Jia, L. Que, L. Zhou, L. Chang, J. Zhou
University of Electronic Science and Technology of China, Chengdu, China
11:45 AM
22.8 A 0.81mm2 740μW Real-Time Speech Enhancement Processor Using Multiplier-Less
PE Arrays for Hearing Aids in 28nm CMOS
S. Park, S. Lee, J. Park, H-S. Choi, D. Jeon, Seoul National University, Seoul, Korea
12:00 PM
22.9 A 12nm 18.1TFLOPs/W Sparse Transformer Processor with Entropy-Based Early Exit,
Mixed-Precision Predication and Fine-Grained Power Management
T. Tambe1, J. Zhang1, C. Hooper1, T. Jia2, P. N. Whatmough1,3, J. Zuckerman4, M. Cassel Dos Santos4,
E. J. Loscalzo4, D. Giri4, K. Shepard4, L. Carloni4, A. Rush5, D. Brooks1, G-Y. Wei1
1Harvard University, Cambridge, MA; 2Peking University, Beijing, China; 3ARM, Boston, MA
4Columbia University, New York, NY; 5Cornell University, New York, NY

Conclusion 12:15 PM

40
SESSION 23 Wednesday February 22nd, 8:30 AM
Analog Sensor Interfaces
Session Chair: Chinwuba Ezekwe, Robert Bosch, Sunnyvale, CA
Session Co-Chair: Minkyu Je, KAIST, Daejeon, Korea
8:30 AM
23.1 A 7.9fJ/Conversion-Step and 37.12aFrms Pipelined-SAR Capacitance-to-Digital
Converter with kT/C Noise Cancellation and Incomplete-Settling-Based
Correlated Level Shifting
J. Gao1, L. Shen1, H. Li1, S. Ye1, J. Li1, X. Xu1, J. Cui1, Y. Gao1, R. Huang1, L. Ye1,2
1Peking University, Beijing, China
2Advanced Institute of Information Technology of Peking University, Hangzhou, China

9:00 AM
23.2 A 40A Shunt-Based Current Sensor with ±0.2% Gain Error from -40°C to 125°C
and Self-Calibration 
Z. Tang1, N. G. Toth1, R. Zamparette1, T. Nezuka2, Y. Furuta2, K. A. A. Makinwa1
1Delft University of Technology, Delft, The Netherlands
2MIRISE Technologies, Aichi, Japan

9:30 AM
23.3 A 51A Hybrid Magnetic Current Sensor with a Dual Differential DC Servo Loop
and 43mArms Resolution in a 5MHz Bandwidth
A. Jouyaeian1, Q. Fan1, M. Motz2, U. Ausserlechner2, K. A. A. Makinwa1
1Delft University of Technology, Delft, The Netherlands
2Infineon Technologies, Villach, Austria

Break 10:00 AM

10:15 AM
23.4 A Closed-Loop 12bit CMOS-Integrated Stress Sensor System with 4bit Adjustable
Sensitivity from 178 to 11kPa/LSB at up to 22.5kS/s and 5bit Dynamic Range
Adjustment
K. Allinger1, M. Kuhl2
1Hamburg University of Technology, Hamburg, Germany
2University of Freiburg - IMTEK, Freiburg, Germany

10:45 AM
23.5 A Sub-1V 810nW Capacitively-Biased BJT-Based Temperature Sensor with
an Inaccuracy of ±0.15°C (3σ) from -55°C to 125°C 
Z. Tang1, S. Pan1,2, K. A. A. Makinwa1
1Delft University of Technology, Delft, The Netherlands
2Tsinghua University, Beijing, China

11:15 AM
23.6 A 2.98pJ/conversion 0.0023mm2 Dynamic Temperature Sensor with Fully
On-Chip Corrections
Y. Shen, H. Li, E. Cantatore, P. Harpe
Eindhoven University of Technology, Eindhoven, The Netherlands
11:45 AM
23.7 A BJT-Based Temperature Sensor with ±0.1°C (3σ) Inaccuracy from –55°C to 125°C
and a 0.85pJ∙K2 Resolution FoM Using Continuous-Time Readout
N. G. Toth*1, Z. Tang1, T. Someya1,3, S. Pan*1,2, K. A. A. Makinwa1
1Delft University of Technology, Delft, The Netherlands
2Tsinghua University, Beijing, China
3now with SiTime, Tokyo, Japan

*Equally Credited Authors (ECAs)

Conclusion 12:15 PM

41
SESSIONS 24 & 25 Wednesday February 22nd, 8:30 AM
THz Signal Generation
Session Chair: Ruonan Han, Massachusetts Institute of Technology, Cambridge, MA
Session Co-Chair: Yves Baeyens, Nokia - Bell Labs, Murray Hill, NJ

8:30 AM
24.1 A 0.64-to-0.69THz Beam-Steerable Coherent Source with 9.1dBm Radiated Power
and 30.8dBm Lensless EIRP in 65nm CMOS
L. Gao, C. H. Chan, City University of Hong Kong, Hong Kong, China

9:00 AM
24.2 A 264-to-287GHz, −2.5dBm Output Power, and −92dBc/Hz 1MHz-Phase-Noise CMOS
Signal Source Adopting a 75fsrms Jitter D-Band Cascaded Sub-Sampling PLL
B-T. Moon, S-G. Lee, J. Choi
Korea Advanced Institute of Science and Technology, Daejeon, Korea

9:30 AM
24.3 A 200-to-350GHz SiGe BiCMOS Frequency Doubler with Slotline-Based
Mode-Decoupling Harmonic Tuning Technique Achieving 1.1-to-4.7dBm Output Power
S. Li1, X. Li1,2, H. Wu1, W. Chen1
1Tsinghua University, Beijing, China; 2Sanechips Technology, Shenzhen, China

Break 10:00 AM

RF Transceiver Building Blocks

Session Chair: Jeffrey Walling, Virgina Tech, Blacksburg, VA
Session Co-Chair: Hongtao Xu, Fudan University, Shanghai, China

10:15 AM
25.1 A 4.1W Quadrature Doherty Digital Power Amplifier with 33.6% Peak PAE in
28nm Bulk CMOS
J. Li1, Y. Yin1, H. Chen2, J. Lin1, Y. Li1, X. Jia1, Z. Hu1, X. Zhang2, H. Xu1
1Fudan University, Shanghai, China; 2South China University of Technology, Guangzhou, China

10:45 AM
25.2 A 19.7-to-43.8GHz Power Amplifier with Broadband Linearization Technique
in 28nm Bulk CMOS
W. Zeng1, L. Gao1, N. Sun1, H. Xu2, Q. Xue1, X. Zhang1
1South China University of Technology, Guangzhou, China; 2Fudan University, Shanghai, China

11:15 AM
25.3 A 4.8dB NF, 70-to-86GHz Deep-Noise-Canceling LNA Using Asymmetric
Compensation Transformer and 4-to-1 Hybrid-Phase Combiner in 40nm CMOS
C. Han*, J. Zhou*, Z. Deng, Y. Shu, X. Luo
University of Electronic Science and Technology of China, Chengdu, China
*Equally Credited Authors (ECAs)

11:45 AM
25.4 A 4b RFDAC at 8GS/s for FMCW Chirps with 4GHz Bandwidth in 10μs
S. K. Sireesh1,2, S. H. Abkenar1,2, N. Christoffers1, C. Wagner1, T. Brandt1, A. Stelzer2
1Infineon Technologies, Linz, Austria; 2Johannes Kepler University, Linz, Austria

12:00 PM
25.5 A 1-to-5GHz All-Passive Frequency-Translational 4th-Order N-path Filter
with Low-Power Clock Boosting for High Linearity and Relaxed Pdc-Frequency
Trade-Off
A. Nagulu1, M. Yi 1, Y. Zhuang1, S. Garikapati2, H. Krishnaswamy2
1Washington University in St. Louis, St. Louis, MO; 2Columbia University, New York, NY

Conclusion 12:15 PM

42
SESSIONS 26 & 27 Wednesday February 22nd, 8:30 AM
Display and User Interaction Technologies
Session Chair: Joonsung Bae, Kangwon National University, Chuncheon, Korea
Session Co-Chair: Johan Vanderhaegen, Google, Cupertino, CA

8:30 AM
26.1 A Source-Driver IC Including Power-Switching Fast-Slew-Rate Buffer and 8Gb/s
Effective 3-Tap DFE Receiver Achieving 4.9mV DVRMS and 17V/μs Slew Rate for 8K
Displays and Beyond
K. Ryu*, J-Y. Jeong*, J-P. Lim, K-H. Lee, K. Kim, Y. Kwon, S. Yoo, S. Kim, H-W. Lim, J-Y. Lee
Samsung Electronics, Hwaseong, Korea
*Equally Credited Authors (ECAs)

9:00 AM
26.2 Virtual Rotating Gesture Recognizable Touch Readout IC for 1.26” Circular Touch
Screen Panel
S. Ko1, J. Lee1, J. Ham1, B. So2, D. Cho2, H. Kim2, B. Kim2, W. Sim2, G. Youm2
1Kwangwoon University, Seoul, Korea

2Zinitix, Suwon, Korea

9:30 AM
26.3 A 45.8dB-SNR 120fps 100pF-Load Self-Capacitance Touch-Screen Controller with
Enhanced In-Band Common Noise Immunity Using Noise Antenna Reference
S. Byun, H. Lee, T.-G.Song, J.Lee, J. Baek, G. Ha, S. Baek, Y. Kim, W. Jung, H.-W. Lim, S. Kim,
J.-Y. Lee
Samsung Electronics, Hwaseong, Korea

Break 10:00 AM

Innovations from Outside the (ISSCC) Box

Session Chair: Ali Hajimiri, Caltech, Pasadena, CA
Session Co-Chair: Firooz Aflatouni, University of Pennsylvania, Philadelphia, PA

10:15 AM
27.1 Some Recent Progress in Bioelectronics
J. Rogers
Northwestern University, Evanston, IL

10:45 AM
27.2 The Tall Thin Molecular Programmer
E. Winfree
California Institute of Technology, Pasadena, CA

11:15 AM
27.3 The Promise of 2-D Materials for Scaled Digital and Analog Applications
D. Verreck, P. Wambacq, M. Van de Put, Z. Ahmed, Q. Smets, A. Afzalian, R. Duflou, X. Wu,
G. Mirabelli, R. Chen, I. Asselberghs, G. Sankar Kar
imec, Leuven, Belgium

11:45 AM
27.4 Inverse Designed, Densely Integrated Classical and Quantum Photonics
J. Vuckovic1, G. H. Ahn2, K. Van Gasse1, M. Guidry1, H. Kwon1, J. Lu1, D. Lukin1, A. Piggott1, N. Sapra1,
L. Su1, J. Skarda1, R. Trivedi1, D. Vercruysse1, A. White1, J. Yang1, K. Yang1
1Stanford University, Stanford, CA

2Stanford University, stanford, CA

Conclusion 12:15 PM

43
SESSION 28 Wednesday February 22nd, 8:30 AM
High-Density Memories and High-Speed Interfaces
Session Chair: Seung-Jae Lee, Samsung, Hwaseong, Korea
Session Co-Chair: Dongkyun Kim, SK hynix, Icheon, Korea
8:30 AM
28.1 A 1.67Tb 5b/Cell Flash Memory Fabricated in a 192-Layer Floating-Gate 3D-NAND
Technology and Featuring a 23.3Gb/mm2 Bit Density
A.  Khakifirooz1, E.  Anaya2, S.  Balasubrahmanyam2, G.  Bennett1, D.  Castro2, J.  Egler2, K.  Fan2,
R.  Ferdous1, K.  Ganapathi1, O.  Guzman2, C.  W.  Ha1, R.  Haque2, V.  Harish2, M.  Jalalifar2,
O. W. Jungroth2, S-T. Kang1, G. Karbasian1, J-Y. Kim1, S. Li2, A. S. Madraswala2, S. Maddukuri2,
A. Mohammed1, S. Mookiah2, S. Nagabhushan2, B. Ngo2, D. Patel2, S. K. Poosarla2, N. V. Prabhu2,
C. Quiroga2, S. Rajwade1, A. Rahman2, J. Shah2, R. S. Shenoy1, E. Tachie Menson2, A. Tankasala1,
S. K. Thirumala1, S. Upadhyay2, K. Upadhyayula2, A. Velasco2, N. K. B. Vemula2, B. Venkataramaiah2,
J. Zhou1, B. M. Pathak2, P. Kalavade1, 1Intel, Santa Clara, CA; Intel, Folsom, CA
9:00 AM
28.2 A High Performance 1Tb 3b/Cell 3D-NAND Flash with 194MB/s Write Throughput on
over 300 Layers
B. Kim, S. Lee, B. Hah, K. Park, Y. Park, K. Jo, Y. Noh, H. Seol, H. Lee, J. Shin, S. Choi, Y. Jung,
S. Ahn, Y. Park, S. Oh, M. Kim, S. Kim, H. Park, T. Lee, H. Won, M. Kim, C. Koo, Y. Choi, S. Choi,
S. Park, D. Youn, J. Lim, W. Park, H. Hur, K. Kwean, H. Choi, W. Jeong, S. Chung, J. Choi, S. Cha
SK hynix Semiconductor, Icheon, Korea
9:30 AM
28.3 A 4nm 16Gb/s/pin Single-Ended PAM4 Parallel Transceiver with Switching-Jitter
Compensation and Transmitter Optimization
J. Jin, S-M. Lee, K. Min, S. Ju, J. Lim, H. Chae, K. Kang, Y. Hong, Y. Jeong, S-H. Kim, J. Lee, J. Kim
Samsung Electronics, Hwaseong, Korea
Break 10:00 AM
10:15 AM
28.4 A 4nm 1.15TB/s HBM3 Interface with Resistor-Tuned Offset-Calibration and In-Situ
Margin-Detection
K. Chae, J. Park, J. Song, B. Koo, J. Oh, S. Yi, W. Lee, D. Kim, T. Yeo, K. Kang, S. Park, E. Kim,
S. Jung, S. Park, S. Park, M. Noh, H. Rhew, J. Shin, Samsung Electronics, Hwaseung, Korea
10:45 AM
28.5 A 900μW, 1–4GHz Input-Jitter-Filtering Digital-PLL-Based 25%-Duty-Cycle Quadrature-
Clock Generator for Ultra-Low-Power Clock Distribution in High-Speed DRAM
Interfaces
Y. Shin*, Y. Jo*, J. Kim, J. Lee, J. Kim, J. Choi
Korea Advanced Institute of Science and Technology, Daejeon, Korea
*Equally Credited Authors (ECAs)
11:00 AM
28.6 A 32Gb/s/pin 0.51pJ/b Single-Ended Resistor-Less Impedance-Matched Transmitter
with T-Coil-Based Edge-Boosting Equalizer in 40nm CMOS
J-H. Park1, H. Lee1, H. Cho1, S. Lee1, K-H. Lee1, H-G. Ko2, D-K. Jeong1
1Seoul National University, Seoul, Korea; 2ONEsemiconductor, Gyeonggi, Korea

11:15 AM
28.7 A 1.1V 6.4Gb/s/pin 24Gb DDR5 SDRAM with Highly Accurate Duty Corrector and NBTI
Tolerant DLL
D. Kwon, H. S. Jeong, J. Choi, W. Kim, J. W. Kim, J. Yoon, J. Choi, S. Lee, H. N. Rie, J-I. Lee, J. Lee,
T. Jang, J. Kim, S. Kang, J. Shin, Y. Loh, C. Y. Lee, J. Woo, H. Yu, C. Bae, R. Oh, Y-S. Sohn, C. Yoo,
J. Lee, Samsung Electronics, Hwaseong, Korea
11:45 AM
28.8 A 1.1V 16Gb DDR5 DRAM with Probabilistic-Aggressor Tracking, a Refresh
Management Function, Per-Row Hammer Tracking, a Multi-Step Precharge,
and Core-Bias-Voltage Modulation for Security and Reliability Enhancement
W. Kim, C. Jung, S. Yoo, D. Hong, J. Hwang, J. Yoon, O. Jung, J. Choi, S. Hyun, M. Kang, S. Lee,
D. Kim, S. Ku, D. Choi, N. Joo, S. Yoon, J. Noh, B. Go, C. Kim, S. Hwang, M. Hwang, S-M. Yi, H. Kim,
S. Heo, Y. Jang, K. Jang, S. Chu, Y. Oh , K. Kim, J. Kim, S. Kim, J. Hwang, S. Park, J. Lee, I. Jeong,
J. Cho, J. Kim, SK hynix Semiconductor, Icheon, Korea
Conclusion 12:15 PM

44
SESSION 29 Wednesday February 22nd, 1:30 PM
Digital Accelerators and Circuit Techniques
Session Chair: Mingoo Seok, Columbia University, New York, NY
Session Co-Chair: Kazuki Fukuoka, Renesas Electronics, Tokyo, Japan

1:30 PM
29.1 A 32.5mW Mixed-Signal Processing-in-Memory-Based k-SAT Solver in 65nm CMOS
with 74.0% Solvability for 30-Variable 126-Clause 3-SAT Problems
D. Kim, N. Mizanur Rahman, S. Mukhopadhyay, Georgia Institute of Technology, Atlanta, GA

2:00 PM
29.2 Snap-SAT: A One-Shot Energy-Performance-Aware All-Digital Compute-in-Memory
Solver for Large-Scale Hard Boolean Satisfiability Problems
S. Xie, M. Yang, S. A. Lanham, Y. Wang, M. Wang, S. Oruganti, J. P. Kulkarni
University of Texas, Austin, TX

2:30 PM
29.3 A 8.09TOPS/W Neural Engine Leveraging Bit-Sparsified Sign-Magnitude
Multiplications and Dual Adder Trees
H. An, Y. Chen, Z. Fan, Q. Zhang, P. Abilllama, H-S. Kim, D. Blaauw, D. Sylvester
University of Michigan, Ann Arbor, MI

2:45 PM
29.4 Wafer-Level Stacking of High-Density Capacitors to Enhance the Performance of a
Large Multicore Processor for Machine Learning Applications
S. Felix1, S. Morton2, S. Stacey1, J. Walsh1
1Graphcore, Bristol, United Kingdom; 2Graphcore, Adelaide, Australia

Break 3:00 PM

3:15 PM
29.5 A 73.53TOPS/W 14.74TOPS Heterogeneous RRAM In-Memory and SRAM
Near-Memory SoC for Hybrid Frame and Event-Based Target Tracking
M. Chang*1, A. S. Lele*1, S. D. Spetalnick1, B. Crafton1, S. Konno1, Z. Wan1, A. Bhat1, W-S. Khwa2,
Y-D. Chih3, M-F. Chang2, A. Raychowdhury1
1Georgia Institute of Technology, Atlanta, GA; 2TSMC Corporate Research, Hsinchu, Taiwan

3TSMC Design Technology, Hsinchu, Taiwan; *Equally Credited Authors (ECAs)

3:45 PM
29.6 A 1.5μW End-to-End Keyword Spotting SoC with Content-Adaptive Frame Sub-Sampling
and Fast-Settling Analog Frontend
J-H. Seol1,2, H. Yang1, R. Rothe1, Z. Fan1, Q. Zhang1, H-S. Kim1, D. Blaauw1, D. Sylvester1
1University of Michigan, Ann Arbor, MI; 2Samsung Electronics, Hwasung, Korea

4:15 PM
29.7 CCSA: A 394TOPS/W Mixed-Signal GPS Accelerator with Charge-Based Correlation
Computing for Signal Acquisition
J. Li1, W. He1, B. Zhang2, L. Qi1, G. He1, M. Seok2
1Shanghai Jiao Tong University, Shanghai, China; 2Columbia University, New York, NY

4:45 PM
29.8 A Sub-0.8pJ/b 16.3Gbps/mm2 Universal Soft-Detection Decoder Using ORBGRAND in
40nm CMOS
A. Riaz1, A. Yasar1, F. Ercan1, W. An2, J. Ngo1, K. Galligan3, M. Medard2, K. R. Duffy3, R. T. Yazicigil1
1Boston University, Boston, MA; 2Massachusetts Institute of Technology, Cambridge, MA

3Maynooth University, Maynooth, Ireland

5:15 PM
29.9 An 8T eNVSRAM Macro in 22nm FDSOI Standard Logic with Simultaneous Full-Array
Data Restore for Secure IoT Devices
S. Nouri, S. S. Iyer; University of California, Los Angeles, CA

Conclusion 5:30 PM

45
SESSION 30 Wednesday February 22nd, 1:30 PM
Power Management Techniques
Session Chair: Xun Liu, The Chinese University of Hong Kong, Shenzhen, China
Session Co-Chair: Gael Pillonnet, CEA-Leti, Grenoble, France
1:30 PM
30.1 A Scalable N-Step Equal Split SSHI Piezoelectric Energy Harvesting Circuit Achieving
1170% Power Extraction Improvement and 22nA Quiescent Current with a 1μH-to-10μH Low
Q Inductor 
Y-W. Jeong, S-J. Lee, J-H. Kim, M-J. Cho, H-S. Kim, S-U. Shin
Ulsan National Institute of Science and Technology, Ulsan, Korea
2:00 PM
30.2 A 93.2%-Efficiency Multi-Input Bipolar Energy Harvester with 17.9X MPPT Loss Reduction
Z-Y. Yang1, A. Chen1, C-W. Chen1, W-C. Hung1, K-H. Chen1, K-L. Zheng1,2, Y-H. Lin3, S-R. Lin3, T-Y. Tsai3
1National Yang Ming Chiao Tung University, Hsinchu, Taiwan
2Chip-GaN Power Semiconductor, Hsinchu, Taiwan; 3Realtek Semiconductor, Hsinchu, Taiwan

2:30 PM
30.3 A Bias-Flip Rectifier with a Duty-Cycle-Based MPPT Algorithm for Piezoelectric Energy
Harvesting with 98% Peak MPPT Efficiency and 738% Energy-Extraction Enhancement
X. Yue, S. Javvaji, Z. Tang, K. A. Makinwa, S. Du; Delft University of Technology, Delft, The Netherlands
2:45 PM
30.4 A 3.7V-to-1kV Chip-Cascaded Switched-Capacitor Converter with Auxiliary Boost Achieving
>96% Reactive Power Efficiency for Electrostatic Drive Applications
Y. Li, B. Mabetha, J. T. Stauth; Dartmouth College, Hanover, NH
Break 3:00 PM
3:15 PM
30.5 A 95.3% 5V-to-32V Wide Range 3-Level Current Mode Boost Converter with Fully
State-based Phase Selection Achieving Simultaneous High-Speed VCF Balancing
and Smooth Transition
S-J. Lee1, Y-W. Jeong1, M-J. Cho1, J-H. Kim1, H-S. Kim1, J-S. Bang2, S-U. Shin1
1Ulsan National Institute of Science and Technology, Ulsan, Korea; 2Samsung Electronics, Hwaseong, Korea

3:45 PM
30.6 A 98.6%-Peak-Efficiency 1.47A/mm2-Current-Density Buck-Boost Converter with Always
Reduced Conduction Loss
J. Jin1, Y. Zhou1, C. Chen1, X. Han1, W. Xu2, L. Cheng1,2
1University of Science and Technology of China, Hefei, China; 2Hefei CLT Microelectronics, Hefei, China

4:00 PM
30.7 A Continuously Scalable-Conversion-Ratio SC Converter with Reconfigurable VCF Step for
High Efficiency over an Extended VCR Range 
Y. Wang1,2, M. Huang1, Y. Lu1, R. P. Martins1,3
1University of Macau, Macau, China; 2Zhuhai UM Science & Technology Research Institute, Zhuhai, China
3Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal

4:15 PM
30.8 3D Wireless Power Transfer with Noise Cancellation Technique for -62dB Noise Suppression
and 90.1%-Efficiency
F. Huang1, H-Y. Tsai1, C-Y. Huang1, Y-C. Luo1, C-H. Li1, S-C. Huang1, Y-H. Kao1, K-H. Chen1, K-L. Zheng1,2,
Y-H. Lin3, S-R. Lin3, T-Y. Tsai3
1National Yang Ming Chiao Tung University, Hsinchu, Taiwan
2Chip-GaN Power Semiconductor, Hsinchu, Taiwan; 3Realtek Semiconductor, Hsinchu, Taiwan

4:45 PM
30.9 A 90%-Efficiency 40.68MHz Single-Stage Dual-Output Regulating Rectifier with ZVS
and Synchronous PFM Control for Wireless Powering
Z. Luo, J. Liu, H. Lee, University of Texas at Dallas, Richardson, TX
5:00 PM
30.10 Single Chip, Qi Compliant, 40W Wireless Power Transmission Controller using RMS Coil
Current Sensing and Adaptive ZVS for 4dB EMI and up to 1.7% Efficiency Improvements
F. Neri1, G. Mehas2, F. Di Fazio1, G. Figliozzi1, J. Menart1, M. Augustyniak1, T. Acar2, A. Bavisi2
1Renesas Electronics, Zürich, Switzerland; 2Renesas Electronics, San Jose, CA

Conclusion 5:15 PM

46
SESSION 31 Wednesday February 22nd, 1:30 PM
Energy-Efficient Radios for UWB, BMI, and IoT Systems
Session Chair: Negar Reiskarimian, Massachusetts Institute of Technology, Cambridge, MA
Session Co-Chair: Jan Prummel, Renesas Electronics, s-Hertogenbosch, The Netherlands

1:30 PM
31.1 A Quadrature Uncertain-IF IR-UWB Transceiver with Twin-OOK Modulation
B. Wang, W. Rhee, Z. Wang
Tsinghua University, Beijing, China

2:00 PM
31.2 A Fully Integrated IEEE 802.15.4/4z-Compliant 6.5-to-8GHz UWB System-on-Chip RF
Transceiver Supporting Precision Positioning in a CMOS 28nm Process
W. Kim1, H-G. Seok1, G. Lee1, S. Kim1, J-K. Lee1, C. Kim1, W. Kim1, W. Jung1, Y. Cho1, S. Bae1, J. Cho1,
H. Na1, B. Kang1, H. Han1, H. Son1, C. Ahn1, H. Kang1, S. Jung1, H. Sung1, Y. Kim1, D. Kim1, D. Kim1,
J-S. Paek1,2, S. Oh1, J. Lee1, S. Kwak1, J. Kim1
1Samsung Electronics, Hwaseong, Korea

2now at Pusan National University, Pusan, Korea

2:30 PM
31.3 A 1.8Gb/s, 2.3pJ/bit, Crystal-Less IR-UWB Transmitter for Neural Implants
J. Lei1, X. Liu2, W. Song1, H. Huang1, X. Ma2, J. Wei2, M. Zhang1
1Tsinghua University, Beijing, China
2Beijing Ningju Technology, Beijing, China

Break 3:00 PM

3:15 PM
31.4 A 128-Channel 2mm×2mm Battery-Free Neural Dielet Merging Simultaneous
Multi-Channel Transmission Through Multi-Carrier Orthogonal Backscatter
C. Yang, Z. Zhang, L. Zhang, Y. Zhang, Z. Li, Y. Luo, G. Pan, B. Zhao
Zhejiang University, Hangzhou, China

3:45 PM
31.5 A Passive Bidirectional BLE Tag Demonstrating Battery-Free Communication in
Tablet/Smartphone-to-Tag, Tag-to-Tablet/Smartphone, and Tag-to-Tag Modes
Z. Chang*1, Q. Xiao*1,2, W. Wang1,2, Y. Luo1, B. Zhao1
1Zhejiang University, Hangzhou, China

2Microaiot, Hangzhou, China

*Equally Credited Authors (ECAs)

4:15 PM
31.6 A ULP Long-Range Active-RF Tag with Automatic Antenna-Interface Calibration
Achieving 20.5% TX Efficiency at -22dBm EIRP, and -60.4dBm Sensitivity at 17.8nW
RX Power
Z. Yang1, J. Yin1, W-H. Yu1, H. Zhang1, P-I. Mak1, R. P. Martins1,2
1University of Macau, Macau, China

2Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal

4:30 PM
31.7 A 0.7-to-2.5GHz Sliding Digital-IF Quadrature Digital Transmitter Achieving >40%
System Efficiency for Multi-Mode NB-IoT/BLE Applications
C. Hu, D. Zheng, Y. Yin, J. Lin, Y. Li, W. Li, H. Xu
Fudan University, Shanghai, China

4:45 PM
31.8 A 0.4-to-0.95GHz Distributed N-Path Noise-Cancelling Ultra-Low-Power RX with
Integrated Passives Achieving –85dBm/100kb/s Sensitivity, -41dB SIR and 174dB RX
FoM in 22nm CMOS
H. Bialek, M. Johnston, A. Natarajan
Oregon State University, Corvallis, OR

Conclusion 5:15 PM

47
SESSION 32 Wednesday February 22nd, 1:30 PM
Intelligent Biomedical Circuits and Systems
Session Chair: Jun-Chau Chien, National Taiwan University, Taipei, Taiwan
Session Co-Chair: Mahsa Shoaran, EPFL, Geneva, Switzerland

1:30 PM
32.1 A Behind-The-Ear Patch-Type Mental Healthcare Integrated Interface with 275-Fold
Input Impedance Boosting and Adaptive Multimodal Compensation Capabilities
H. Kim1, M. Kim1, K. Lee2, S. Cho1, C. S. Park1, S. Song3, D. S. Keum4, D. P. Jang3, J. J. Kim1
1Ulsan National Institute of Science and Technology, Ulsan, Korea

2Samsung Electronics, Hwaseong, Korea

3Hanyang University, Seoul, Korea

4SOSO H&C, Daegu, Korea

2:00 PM
32.2 A Stimulus-Scattering-Free Pixel-Sharing Sub-Retinal Prosthesis SoC with 35.8dB
Dynamic Range Time-Based Photodiode Sensing and Per-Pixel Dynamic Voltage
Scaling
K. Eom1, M. Park1, H-S. Lee1, S-B. Ku1, N. Kim2, S. Cha3, Y. S. Goo3, S. Kim2, S-W. Kim4, H-M. Lee1
1Korea University, Seoul, Korea

2Daegu Gyeongbuk Institute of Science and Technology, Daegu, Korea

3Chungbuk National University, Cheongju, Korea

4Korea University Guro Hospital, Seoul, Korea

2:30 PM
32.3 A 1V 136.6dB-DR 4kHz-BW ΔΣ Current-to-Digital Converter with a
Truncation-Noise-Shaped Baseline-Servo-Loop in 0.18μm CMOS 
T. Seol, S. Lee, G. Kim, S. Kim, E. Kim, S. Baik, J. Kung, J-W. Choi, A. K. George, J. Lee
Daegu Gyeongbuk Institute of Science and Technology, Daegu, Korea

Break 3:00 PM

3:15 PM
32.4 A 1V-Supply 1.85VPP-Input-Range 1kHz-BW 181.9dB-FOMDR 179.4dB-FOMSNDR 2nd-Order
Noise-Shaping SAR-ADC with Enhanced Input Impedance in 0.18μm CMOS
G. Kim, S. Lee, T. Seol, S. Baik, Y. Shin, G. Kim, J-H. Yoon, A. K. George, J. Lee
Daegu Gyeongbuk Institute of Science and Technology, Daegu, Korea

3:45 PM
32.5 A 384-Channel Online-Spike-Sorting IC Using Unsupervised Geo-OSort Clustering and
Achieving 0.0013mm2/Ch and 1.78μW/Ch
Y. Chen1,2, B. Tacca1, Y. Chen1, D. Biswas1, G. Gielen1,3, F. Catthoor1,3, M. Verhelst1,3, C. Mora Lopez1
1imec, Leuven, Belgium

2Fudan University, Shanghai, China

3KU Leuven, Leuven, Belgium

4:15 PM
32.6 SciCNN: A 0-Shot-Retraining Patient-Independent Epilepsy-Tracking SoC
C-W. Tsai1,2, R. Jiang1, L. Zhang1,3, M. Zhang1,4, L. Wu1, J. Guo1, Z. Yan1, J. Yoo1,2
1National University of Singapore, Singapore, Singapore

2The N.1 Institute for Health, Singapore, Singapore

3Apple, Cupertino, CA

4Huawei Technologies, Chengdu, China

4:45 PM
32.7 Fascicle-Selective Bidirectional Peripheral Nerve Interface IC with 173dB FOM
Noise-Shaping SAR ADCs and 1.38pJ/b Frequency-Multiplying Current-Ripple Radio
Transmitter
J. Xu, J. Sales Filho, S. Nag, L. Long, C. Tejeiro, E. Hwang, G. O'Leary, Y. Huang, M. Kanchwala,
M. Abdolrazzaghi, C. Tang, P. Liu, Y. Sui, X. Liu, G. Eleftheriades, J. Zariffa, R. Genov
University of Toronto, Toronto, Canada

Conclusion 5:15 PM

48
SESSION 33 Wednesday February 22nd, 1:30 PM
Non-Volatile Memory and Compute-In-Memory
Session Chair: Hidehiro Shiga, KIOXIA, Yokohama, Japan
Session Co-Chair: Takashi Ito, Renesas, Kodaira-shi, Tokyo, Japan
1:30 PM
33.1 A 16nm 32Mb Embedded STT-MRAM with a 6ns Read Access Time, 1M-Cycle Write
Endurance, 20-Year Retention at 150°C and MTJ-OTP Solutions for Magnetic Immunity
P-H. Lee, C-F. Lee, Y-C. Shih, H-J. Lin, Y-A. Chang, C-H. Lu, Y-L. Chen, C-P. Lo, C-C. Chen, C-H. Kuo,
T-L. Chou, C-Y. Wang, J. Wu, R. Wang, H. Chuang, Y. Wang, Y-D. Chih, T-Y. J. Chang
TSMC, Hsinchu, Taiwan
2:00 PM
33.2 A 22nm 8Mb 46.4-160.1-TOPS/W STT-MRAM Near-Memory-Computing Macro with
8b Precision for AI-Edge Devices
Y-C. Chiu*1, W-S. Khwa*2, C-Y. Li1, F-L. Hsieh1, Y-A. Chien1, G-Y. Lin1, P-J. Chen1, T-H. Pan1,
D-Q. You1, F-Y. Chen1, A. Lee1, C-C. Lo1, R-S. Liu1, C-C. Hsieh1, K-T. Tang1, Y-D. Chih3, T-Y. Chang3,
M-F. Chang1,2
1National Tsing Hua University, Hsinchu, Taiwan
2TSMC Corporate Research, Hsinchu, Taiwan
3TSMC, Hsinchu, Taiwan

*Equally Credited Authors (ECAs)

2:30 PM
33.3 A 9Mb HZO-Based Embedded FeRAM Macro with a 1012-Cycle Endurance, a 5ns Read
and a 7ns Write Time using ECC-Assisted Data Refresh and an Offset-Canceled Sense
Amplifier
J. Yang1, Q. Luo1, X. Xue2, H. Jiang3, Q. Wu2, Z. Han1, Y. Cao3, Y. Han3, C. Dou1, H. Lv1, Q. Liu2, M. Liu1,2
1Institute of Microelectronics of the Chinese Academy of Sciences, Beijing, China
2Fudan University, Shanghai, China
3Zhejiang Lab, Hangzhou, China

2:45 PM
33.4 A 28nm 2Mb 22.4-41.5TOPS/W STT-MRAM Computing-in-Memory Macro with a
Refined Bit Cell for AI Inference
H. Cai1, Z. Bian1, Y. Hou1, Y. Zhou1, J-L. Cui1, Y. Guo1, X. Tian1, B. Liu1, X. Si1, Z. Wang2, J. Yang1,
W. Shan1
1Southeast University, Nanjing, China
2Nanjing Prochip Electronic Technology, Nanjing, China

Break 3:00 PM

49
SESSION 34 Wednesday February 22nd, 3:15 PM
Cryo-CMOS for Quantum Computing
Session Chair: Fabio Sebastiano, Delft University of Technology, Delft, The Netherlands
Session Co-Chair: Giorgio Ferrari, Politecnico di Milano, Milano, Italy
3:15 PM
34.1 THz Cryo-CMOS Backscatter Transceiver: A Contactless 4 Kelvin-300 Kelvin Data
Interface
J. Wang, M. I. Ibrahim, I. B. Harris, N. M. Monroe, M. I. W. Khan, X. Yi, D. R. Englund, R. Han
Massachusetts Institute of Technology, Cambridge, MA
3:45 PM
34.2 A 28nm Bulk-CMOS IC for Full Control of a Superconducting Quantum Processor
Unit-Cell
J.  Yoo1, Z.  Chen1, F.  Arute1, S.  Montazeri1, M.  Szalay1, C.  Erickson1, E.  Jeffrey1, R.  Fatemi1,
M. Giustina1, M. Ansmann1, E. Lucero1, J. Kelly1, J. C. Bardin1,2
1Google Quantum AI, Goleta, CA; 2University of Massachusetts, Amherst, MA

4:15 PM
34.3 A Polar-Modulation Based Cryogenic Qubit State Controller in 28nm Bulk CMOS
Y. Guo1,2, Y. Li1, W. Huang1, S. Tan1, Q. Liu3, T. Li1,3, N. Deng1, Z. Wang1, Y. Zheng2, H. Jiang1
1Tsinghua University, Beijing, China
2Nanyang Technological University, Singapore, Singapore
3Beijing Academy of Quantum Information Sciences, Beijing, China

4:45 PM
34.4 A Cryogenic Controller IC for Superconducting Qubits with DRAG Pulse Generation by
Direct Synthesis without Using Memory
K. Kang, D. Minn, J. Lee, H-J. Song, M. Lee, J-Y. Sim
Pohang University of Science and Technology, Pohang, Korea
5:00 PM
34.5 A Calibration-Free 12.8-16.5GHz Cryogenic CMOS VCO with 202dBc/Hz FoM for
Classic-Quantum Interface
G. Zhang1, H. Lin2, C. Wang1
1University of Electronic Science and Technology of China, Chengdu, China
2Chengdu Data Automation System Technologies, Chengdu, China

Conclusion 5:15 PM

50
SHORT COURSE Thursday, February 23rd, 8:00 AM
Principles of Quantum Computing and the Application
of Cryoelectronics to Qubit Control and Readout
Time: Topic:
8:00 AM Breakfast
8:25 AM Introduction by Chair, Daniel Friedman
IBM Thomas J. Watson Research Center, Yorktown Heights, NY
8:30 AM Introduction to Quantum Computing: Qubits, Gates, and Algorithms
William Oliver, Massachusetts Institute of Technology, Cambridge, MA
10:00 AM Break
10:30 AM Spin Qubits: Principles, Control/Readout Architectures, and Cryoelectronic Solutions
Sushil Subramanian, Intel, Hillsboro, OR
12:15 PM Lunch
1:20 PM Superconducting Qubits: Principles, Control/Readout Architectures,
and Cryoelectronic Solutions
David Frank, IBM, Yorktown Heights, NY
2:50 PM Break
3:20 PM Cryoelectronics for Quantum Computing: Technology, Circuit Design,
and Future Directions
Joseph Bardin, University of Massachusetts Amherst, Amherst, MA
& Google Quantum AI, Goleta, CA
4:50 PM Conclusion

Introduction
Quantum computing is a paradigm that has the potential to transform problems that are computationally
intractable today into solvable problems in the future. Significant advances in the last decade have
demonstrated that quantum computers can be implemented, and further that the goal of demonstrating
true performance advantages over traditional computing techniques on one or more problems with
commercial value may be achieved in the not-so-distant future. Yet there remain many fundamental
questions to be answered on the road to realizing a broad class of quantum computing systems, questions
that span the entire range from devices to control electronics to systems design to algorithms. In this short
course, we will first provide an introduction to quantum computing, including fundamentals of qubits,
quantum gates, quantum circuits, and quantum algorithms. In the second and third talks, we will present
approaches to using CMOS circuits at cryogenic temperatures to interact with spin qubits and
superconducting qubits, respectively. In the final talk, we will describe approaches to technology/circuit
co-design and co-optimization in the design of cryogenic circuits for quantum computing applications, and
will then look forward toward future directions and challenges for quantum computing scaled system
implementations.
SC1:
Introduction to Quantum Computing: Qubits, Gates, and Algorithms
William Oliver, Massachusetts Institute of Technology, Cambridge, MA

Quantum computers are fundamentally different from conventional computers. They promise to address
problems that are practically prohibitive and even impossible to solve using today’s supercomputers. The
challenge is building one that is large enough to be useful. In this short course, we will introduce quantum
computing with a focus on the qubit modalities, single-qubit and two-qubit gates, and their use in quantum
algorithms and error mitigation.

William D. Oliver is appointed Henry Ellis Warren (1894) Professor of Electrical Engineering and Computer
Science, Professor of Physics, and Lincoln Laboratory Fellow at the Massachusetts Institute of Technology.
He serves as the inaugural Director of the MIT Center for Quantum Engineering and as Associate Director
of the MIT Research Laboratory of Electronics. Will’s research interests and expertise include the materials,
fabrication, design, and implementation of superconducting qubit processors, as well as the development
of cryogenic packaging and control electronics for extensible quantum computing applications. He received
his PhD in Electrical Engineering from Stanford University in 2003.

51
SHORT COURSE Thursday, February 23rd, 10:30 AM
SC2:
Spin Qubits:
Principles, Control/Readout Architectures,and Cryoelectronic Solutions
Sushil Subramanian, Intel, Hillsboro, OR

Quantum computing offers a potential solution for problems intractable by classical computing. A large
number of qubits, the fundamental units of quantum information, have to be controlled precisely for
implementing practical applications, thereby posing challenging scalability requirements on all layers of the
quantum computing stack. Spin qubits present a scalable solution at the device level due to their ease of
integration and compatibility with standard semiconductor manufacturing. In this talk, we will explore spin-
qubit physics and operation and discuss methods for spin-qubit control and readout. We will then introduce
integrated cryo-CMOS for scalable control and present details of recent advances in qubit-controller SOCs.

Sushil Subramanian received the B.Tech. degree in electronics and electrical communication engineering
from Indian Institute of Technology, Kharagpur, India, in 2009, and the M.S. and Ph.D. degrees in electrical
engineering from the University of Southern California, Los Angeles, CA, in 2017, where he worked on fast-
hopping frequency synthesizers and interference tolerant receivers. He is currently with Intel Labs, Intel
Corporation, Hillsboro, OR, where he works on integrated circuits and systems for qubit control in quantum
computers.

SC3:
Superconducting Qubits:
Principles, Control/Readout Architectures, and Cryoelectronic Solutions
David Frank, IBM, Yorktown Heights, NY

Superconducting qubits such as transmons are one of the most well-developed classes of quantum devices
for building a quantum computer. We will describe the fabrication and operating principles of such qubits
and discuss the requirements for their control and read-out electronics. In particular, the use of cryogenic
CMOS circuits operating at 4 K is a promising approach to obtaining high-quality qubit control with reduced
system complexity, and we will discuss the design and operation of such circuits.

David Frank received his B.S. from Caltech in 1977 and a Ph.D. in physics from Harvard University in 1983.
He is a Research Staff Member at the IBM T. J. Watson Research Center. His studies have included III-V
FETs, exploring the limits of scaling of silicon technology, and quantum computing. His recent work includes
exploring uses of CMOS in quantum computing and concepts in quantum error correction. He has also
worked on telegraph noise in nanoscale FETs, the modeling of innovative Si devices, low-power circuit
design, and the analysis of CMOS scaling. Dr. Frank is an IEEE Fellow and was a co-recipient of the 2011
IEEE Cledo Brunetti award. He has authored or co-authored over 130 technical publications and holds 23
U.S. patents.

SC4:
Cryoelectronics for Quantum Computing:
Technology, Circuit Design, and Future Directions
Joseph Bardin, University of Massachusetts Amherst, Amherst, MA & Google Quantum AI, Goleta, CA

In this talk, we give an overview of emerging IC technology for the readout and control of superconducting
quantum processors. After a brief introduction, the talk will describe the prospect of using SiGe HBT-based
LNAs for qubit readout, including a discussion of technology optimization for reducing noise. We then will
discuss control ICs, including experimental challenges and characterization techniques using quantum
control experiments. The talk will end with a discussion of open challenges.

Joseph Bardin is a Professor of ECE at UMass Amherst and a Research Scientist with the Google Quantum
AI team. At UMass, he leads research in the area of low-temperature integrated circuits, with applications
in radio astronomy and the quantum information sciences. At Google, he leads the team working on the
development of integrated circuits for large-scale quantum computers.

52
FORUM 4 Thursday February 23rd, 8:00 AM
Advancing Technologies for Extended Reality (XR)
to Make the “Metaverse” Possible
Organizers: Huichu Liu, Meta Agile Silicon Team, Menlo Park, CA
Visvesh Sathe, Georgia Institute of Technology, Atlanta, GA

Committee: Kaushik Sengupta, Princeton University, Princeton, NJ

Firooz Aflatouni, University of Pennsylvania, Philadelphia, PA
Matteo Bassi, Infineon Technologies, Villach, Austria
Sugako Otani, Renesas Electronics, Tokyo, Japan
Champions: Vivek De, Intel, Hillsboro, OR
Makoto Nagata, Kobe University, Kobe, Japan

Devices for “eXtended Reality” (XR), consisting of augmented (AR), virtual (VR) and mixed realities
(MR), represent the next leap in human-computer interactions. Since XR systems include complex
interactions between many sensors, processing and display while maintaining weight, form factor
and battery constraints, advancing these technologies requires overcoming formidable barriers in
multiple areas: computing, display technologies, low-power sensor, camera and telemetry for gesture
recognition, thermal management, and packaging. In addition, these XR devices implement advanced
machine-learning algorithms and rely on circuit, system, and software co-design to enable the desired
immersive experience. This forum provides an overview of the key challenges and opportunities in
the hardware design for XR devices and explores the necessary technology advancements to make
the “Metaverse” possible.
Agenda
Time Topic
8:00 AM Breakfast
8:15 AM Introduction
Huichu Liu, Meta Agile Silicon Team, Menlo Park, CA
8:25 AM Overview of Augmented Reality and Virtual Reality Applications,
Silicon Challenges and Research Directions
Edith Beigné, Meta Platforms, Menlo Park, CA
9:15 AM Extended Reality: An End-to-End Systems View
Sarita Adve, University of Illinois at Urbana-Champaign, IL
10:05 AM Break
10:20 AM XR SoC Design and Implementation
Sungcheol Park, Samsung Electronics, Hwaseong, Korea
11:10 AM Silicon Photonics: Augmented Reality and Beyond
Jelena Notaros, MIT, Boston, MA
12:00 PM Lunch
1:20 PM mm-Wave Integrated Systems for High-Precision Sensing
and Recognition in XR Devices
Vadim Issakov, Technische Universität Braunschweig,
Braunschweig, Germany & Infineon Technologies, Munich, Germany
2:10 PM TinyML: Why it is Essential for Metaverse
Evgeni Gousev, Qualcomm, San Diego, CA
3:00 PM Break
3:15 PM XR Challenges and Success Factors
Johan Johansson, MediaTek, Stockholm, Sweden
4:05 PM Compact and Energy Efficient Packaging for XR Hardware
Kuo-Chung Yee, TSMC, Hsinchu, Taiwan
4:55 PM Closing Remarks

53
FORUM 5 Thursday February 23rd, 8:00 AM
Extreme Data Converters and Their Peripherals
Organizer: Jongwoo Lee, Samsung Electronics, Hwasung, Korea

Committee: Nan Sun, Tsinghua University, Beijing, China

Nima Maghari, University of Florida, Gainesville, FL
Dominique Morche, Département Architecture Conception et
Logiciel Embarqué (DACLE), CEA-Leti, Grenoble, France
Man-Kay Law, University of Macau, Taipa, Macau, China

Champion: Kostas Doris, NXP, Eindhoven, The Netherlands

Moderator: Kostas Doris, NXP, Eindhoven, The Netherlands

Data converters have undergone significant advances over the past decade. Their performance and
application spaces have been greatly expanded. Nowadays, data converters can sample beyond
100GS/s, consume only several nW of power, and achieve an energy-efficiency approaching the
theoretical limit. This forum will discuss design techniques that are pushing the data-converter
applications into previously uncharted territories, including extremely high speed, high precision,
and energy efficiency. In addition to the converters, the peripheral circuits, such as time and voltage
references and driving amplifiers, are taking the spotlight in this forum.

Agenda
Time Topic
8:00 AM Breakfast

8:15 AM Introduction
Jongwoo Lee, Samsung Electronics, Hwasung, Korea

8:25 AM The Post-FoM Era of ADC: What Else Matters When Quantization is
‘Free’?
Matt Straayer, AMD, Boxborough, MA

9:15 AM Design Techniques for Energy-Efficient Analog-to-Digital

Converters
Youngchel Chae, Yonsei University, Seoul, Korea

10:05 AM Break

10:20 AM Continuous-Time Pipelined ADC: A Breed of Continuous-Time ADCs

for Ultra-Wideband Conversion
Hajime Shibata, ADI, Toronto, Canada

11:10 AM Precision High Speed Converters

Sandeep Oswal, TI, Bengaluru, India

12:00 PM Lunch

1:20 PM High-Speed and High-Performance Continuous-Time Delta-Sigma

ADCs
Lucien Breems, NXP, Eindhoven, The Netherlands

2:10 PM High Performance ADC Design in High-Speed Wireline

Transceivers and 5G Wireless Transceivers
Ben Rhew, Samsung Electronics, Hwaseong, Korea

3:00 PM Break

3:15 PM Extremely Compact Data Converters for Future 3D Sensing

Satoshi Kondo, Toshiba, Kawasaki, Japan

4:05 PM Panel Discussion

Moderator: Kostas Doris, NXP, Eindhoven, The Netherlands

4:55 PM Closing Remarks

54
FORUM 6 Thursday February 23rd, 8:00 AM
The Future of Heterogeneous Multi-Core Architectures for AI and
Other Specialized Processing
Organizer: Jun Deguchi, Kioxia, Kawasaki, Japan

Committee: Soojung Ryu, Sapeon, Seongnam, Korea

Marian Verhelst, KU Leuven, Heverlee, Belgium
Eric Wang, TSMC, Hsinchu, Taiwan
Ru Huang, Peking University, Beijing, China
Harish Krishnamurthy, Intel, Hillsboro, OR
Ingrid Verbauwhede, KU Leuven, Leuven, Belgium

Champions: Fatih Hamzaoglu, Intel, Hillsboro, OR

Yan Li, Western Digital, Milpitas, CA
The field of processor SoC design is increasingly moving to heterogeneous architectures, in which
different processor types are combined in the same processing system. These processors range
from various CPUs (power-efficient and high-performance cores) to GPUs, NPUs and ISPs. The trend
towards increased heterogeneity is not yet saturated. Will we see even more heterogeneous systems
in the future? What processor combinations are optimal for different target devices? What
accelerators will we see added in the future? And how can such heterogeneous processing cores
efficiently share data when the number of cores keeps going up, and still ensure coherency? With
the introduction of chiplets, how can the benefits of heterogeneous multi-core architectures be
expanded? This forum will bring together experts on multi-core processing systems and processor
specialization to consider the future of heterogeneous many-core compute systems.

Agenda
Time Topic
8:00 AM Breakfast
8:15 AM Introduction
Jun Deguchi, Kioxia, Kawasaki, Japan
8:25 AM Scaling AI Computing Sustainably
Carole-Jean Wu, Meta, Cambridge, MA
9:15 AM AI Accelerators: A Trade-off in Performance, Energy Efficiency,
Flexibility, and Design Complexity
Michaela Blott, AMD, Dublin, Ireland
10:05 AM Break
10:20 AM The Era of Domain-Specific Architecture: Heterogeneous NPU
Cores in a Mobile SoC
Jun-Seok Park, Samsung Electronics, Hwaseong, Korea
11:10 AM Is an AI Accelerator All You Need? Overcoming Amdahl’s Law with
Tightly-Coupled Heterogeneous Accelerators
Angelo Garofalo, ETH Zurich, Zurich, Switzerland
12:00 PM Lunch
1:20 PM Meeting Future Performance Demands Through Packaging
Bryan Black, Chipletz, Austin, TX
2:10 PM Co-Design of Programmable Hardware Accelerators and Compilers
for Future Heterogeneous Computing Systems
Priyanka Raina, Stanford University, Stanford, CA
3:00 PM Break
3:15 PM Universal Chiplet Interconnect Express (UCIe)TM: An Open Industry-
Standard Chiplet Interconnect for Next-Generation Systems on a
Package
Debendra Das Sharma, Intel, Santa Clara, CA
4:05 PM Memory Systems for AI Computers
Simon Knowles, Graphcore, Bristol, United Kingdom
4:55 PM Closing Remarks

55
FORUM 7 Thursday February 23rd, 8:00 AM
Advanced Circuits and Technologies
for Wearable and Implantable Devices
Organizer: Sohmyung Ha, New York University Abu Dhabi,
United Arab Emirates
Committee: Jiawei Xu, Fudan University, Shanghai, China
Qinwen Fan, Delft University of Technology, Delft, The Netherlands
Yan Lu, University of Macau, Taipa, Macao, China
Mehdi Kiani, The Pennsylvania State University, University Park, PA

Champions: Makoto Ikeda, University of Tokyo, Tokyo, Japan

Arun Natarajan, Oregon State University, Corvallis, OR
Over the past decades, we have witnessed remarkable advances in wearable and implantable
devices for diagnosing and treating a wide range of diseases and for vigilant healthcare
monitoring. This forum will be a great venue to learn and discuss recent advances in system-
level architectures, circuit techniques, and emerging technologies for various wearable and
implantable applications. Presentations will include discussions of sensors, interface circuits,
on-chip signal processing, powering, and communication for wearable and implantable
devices.

Agenda

Time Topic
8:00 AM Breakfast
8:15 AM Introduction
Sohmyung Ha, New York University Abu Dhabi,
United Arab Emirates
8:25 AM Biopotential Sensing in Consumer Wearables
Yun-Shiang Shu, MediaTek, Hsinchu, Taiwan
9:15 AM Skin-Interfaced Wearable Electrochemical Biosensors
Wei Gao, California Institute of Technology, Pasadena, CA
10:05 AM Break
10:20 AM Flexible and Integrated Power Sources for Wearable Devices
Ana Arias, University of California, Berkeley, CA
11:10 AM Secure and Efficient Internet of Bodies (IoB) using Body as a ‘Wire’
Shreyas Sen, Purdue University, West Lafayette, IN
12:00 PM Lunch
1:20 PM Hybrid Implantable Neural Systems: From Soft, Biomimetic
Devices to Translational Interfaces
Stéphanie Lacour, EPFL, Lausanne, Switzerland
2:10 PM Bioelectronics - Where Technology Meets Biology
Refet Firat Yazicioglu, Galvani Bioelectronics, London,
United Kingdom
3:00 PM Break
3:15 PM Towards Battery-Free Millimeter-Sized Bioelectronic Implants
Kaiyuan Yang, Rice University, Houston, TX
4:05 PM Neuron-Inspired Wireless Telemetry for Implantable Neural
Interfaces
Yao-Hong Liu, imec, Eindhoven, The Netherlands
4:55 PM Closing Remarks

56
 EXECUTIVE COMMITTEE
CONFERENCE CHAIR ADCOM REPRESENTATIVE
Eugenio Cantatore Jan van der Spiegel
Eindhoven University of Technology, University of Pennsylvania,
Eindhoven, The Netherlands Philadelphia, PA

PAST CONFERENCE CHAIR

DIRECTOR OF PUBLICATIONS
Kevin Zhang
Laura Fujino
Taiwan Semiconductor Manufacturing Company,
Hsinchu, Taiwan University of Toronto,
Toronto, Canada
SENIOR TECHNICAL ADVISOR
Anantha Chandrakasan PRESS LIAISON AND ARC CHAIR
Massachusetts Institute of Technology, Kenneth C. Smith
Cambridge, MA University of Toronto,
Toronto, Canada
EXECUTIVE COMMITTEE SECRETARY
Makoto Nagata PRESS COORDINATOR
Kobe University,
Shahriar Mirabbasi
Kobe, Japan
University of British Columbia,
PROGRAM CHAIR Vancouver, Canada
Piet Wambacq
imec, EDUCATION CHAIR
Heverlee, Belgium Ali Sheikholeslami
University of Toronto,
PROGRAM VICE-CHAIR Toronto, Canada
Frank O’Mahony
Intel, DIRECTOR OF OPERATIONS
Hillsboro, OR Melissa Widerkehr
Widerkehr and Associates,
ITPC FAR-EAST REGIONAL CHAIR
Jun Deguchi Lewes, DE
Kioxia,
Kawasaki, Japan DIRECTOR OF FINANCE
John Weinmann
ITPC FAR-EAST REGIONAL VICE CHAIR Rochester, NY
Man-Kay Law
University of Macau, Taipa, WEB SITE AND A/V CHAIR
Macau, China Trudy Stetzler
Halliburton,
ITPC EUROPEAN REGIONAL CHAIR
Houston, TX
Bruce Rae
ST Microelectronics,
Edinburgh, United Kingdom STRATEGY ADVISORY GROUP CHAIR
Bram Nauta
ITPC EUROPEAN REGIONAL VICE CHAIR University of Twente,
Matteo Bassi Enschede, The Netherlands
Infineon Technologies,
Villach, Austria SOCIAL MEDIA CHAIR
Carolina Mora-Lopez
DEMO SESSION CHAIR imec,
Patrick Mercier Leuven, Belgium
University of California, San Diego,
La Jolla, CA
WIC REPRESENTATIVE
SRP CHAIR Kathy Wilcox
Jerald Yoo AMD,
National University of Singapore, Boxborough, MA
Singapore

57
 INTERNATIONAL TECHNICAL PROGRAM COMMITTEE
Technical Editors & Multi-Media Coordinator
Jason H. Anderson James W. Haslett
University of Toronto, Toronto, Canada The University of Calgary, Calgary, Canada
Leonid Belostotski Shahriar Mirabbasi
The University of Calgary, Calgary, Canada University of British Columbia,
Dustin Dunwell Vancouver, Canada
Alphawave IP, Toronto, Canada
Vincent Gaudet MULTI-MEDIA COORDINATOR
University of Waterloo, Waterloo, Canada AND DIGEST EDITOR
Glenn Gulak David Halupka
University of Toronto, Toronto, Canada StarIC, Toronto, Canada

Analog Subcommittee
Chair: Maurits Ortmanns
Institute of Microelectronics University of Ulm, Ulm, Germany

Ippei Akita Drew Hall

AIST, Tsukuba, Japan University of California, San Diego,
La Jolla, CA
Jens Anders
University of Stuttgart, Stuttgart, Germany Minkyu Je
Marco Berkhout KAIST, Daejeon, Korea
Goodix Technology,
Man-Kay Law
Nijmegen, The Netherlands
University of Macau, Taipa, Macau, China
Chinwuba Ezekwe
Viola Schaffer
Robert Bosch, Sunnyvale, CA
Texas Instruments, Freising, Germany
Qinwen Fan
Delft University of Technology, Shon-Hang Wen
Delft, The Netherlands MediaTek, Hsinchu, Taiwan

Danielle Grifith Jiawei Xu

Texas Instruments, Dallas, TX Fudan University, Shanghai, China

Data Converters Subcommittee

Chair: Jan Westra
Broadcom, Bunnik, The Netherlands

Ahmed Ali Nima Maghari

Apple, Oak Ridge, NC University of Florida, Gainesville, FL

Yun Chiu Dominique Morche

University of Texas at Dallas, Ricardson, TX Département Architecture Conception et
Logiciel Embarqué (DACLE), CEA-Leti,
Ping Gui Grenoble, France
Southern Methodist University, Dallas, TX
Shahrzad Naraghi
John Keane Legato Logic, San Jose, CA
Keysight Technologies, Santa Clara, CA
Nan Sun
Jongwoo Lee Tsinghua University, Beijing, China
Samsung Electronics, Hwasung, Korea
Yan Zhu
Ying-Zu Lin University of Macau Avenida da Universidade,
Mediatek, Hsinchu, Taiwan Taipa, Macau, China

58
 INTERNATIONAL TECHNICAL PROGRAM COMMITTEE
Digital Architectures & Systems (DAS) Subcommittee
Chair: Thomas Burd
Advanced Micro Devices, Santa Clara, CA

Massimo Alioto Sanu Mathew

National University of Singapore, Singapore Intel, Hillsboro, OR
Shidhartha Das Sugako Otani
Advanced Micro Devices, Renesas Electronics, Tokyo, Japan
Cambridge, United Kingdom
Rahul Rao
Chiraag Juvekar
IBM India, Bangalore, India
Apple, Mountain View, CA
Ji-Hoon Kim Ingrid Verbauwhede
Ewha Womans University, Seoul, Korea KU Leuven, Leuven, Belgium
Hugh Mair Chia-Hsiang Yang
MediaTek, Austin, TX National Taiwan University, Taipei, Taiwan

Digital Circuits (DCT) Subcommittee

Chair: Keith Bowman
Qualcomm, Raleigh, NC

Eric Jia-Wei Fang Arijit Raychowdhury

Mediatek, Hsinchu, Taiwan Georgia Institute of Technology, Atlanta, GA
Kazuki Fukuoka Akihide Sai
Renesas Electronics, Tokyo, Japan Toshiba, Kawasaki, Japan
Tanay Karnik Visvesh Sathe
Intel, Hillsboro, OR Georgia Institute of Technology, Atlanta, GA
Huichu Liu Mingoo Seok
Meta Agile Silicon Team, Menlo Park, CA Columbia University, New York, NY
Mijung Noh Yvain Thonnart
Samsung Electronics, Hwaseong, Korea CEA-List, Grenoble, France

IMMD Subcommittee
Chair: Rikky Muller
University of California, Berkeley, Berkeley, CA
Joonsung Bae Seong-Jin Kim
Kangwon National University, Ulsan National Institute of Science and Technology,
Chuncheon, Korea Ulsan, Korea
Behnam Behroozpour Junghyup Lee
SiLC Technologies, South San Francisco, CA DGIST, Daegu, Korea
Jun-Chau Chien Kazuko Nishimura
National Taiwan University, Taipei, Taiwan Panasonic Holdings, Moriguchi, Japan
Leonardo Gasparini
Bruce Rae
Fondazione Bruno Kessler, Trento, Italy
ST Microelectronics,
Sohmyung Ha Edinburgh, United Kingdom
New York University,
Abu Dhabi, United Arab Emirates Masaki Sakakibara
Sony Semiconductor Solutions, Atsugi, Japan
Mutsumi Hamaguchi
Sharp Corporation, Tenri, Japan Mahsa Shoaran
EPFL, Geneva, Switzerland
Taekwang Jang
ETH Zurich, Zurich, Switzerland Johan Vanderhaegen
Google, Mountain View, CA
Mehdi Kiani
The Pennsylvania State University, Jerald Yoo
University Park, PA National University of Singapore, Singapore

59
 INTERNATIONAL TECHNICAL PROGRAM COMMITTEE
Machine Learning Subcommittee
Chair: SukHwan Lim
Samsung Electronics, Hwaseong, Korea
Luca Benini Sophia Shao
ETHZ and UNIBO, Zurich, Switzerland UC Berkeley, Berkeley, CA
Jun Deguchi Kea-Tiong (Samuel) Tang
Kioxia Corporation, Kawasaki, Japan
National Tsing Hua University,
Yongpan Liu Hsinchu, Taiwan
Tsinghua University, Beijing, China
Rangharajan Venkatesan
Soojung Ryu
NVIDIA Corporation, Santa Clara, CA
SAPEON Korea, Seongnam, Korea
Jae-sun Seo Marian Verhelst
Arizona State University, Tempe, AZ KU Leuven, Heverlee, Belgium

Memory Subcommittee
Chair: Meng-Fan Chang
National Tsing Hua University, Hsinchu, Taiwan
Ru Huang Seung-Jae Lee
Peking University, Beijing, China Samsung, Hwaseong, Korea
Takashi Ito
Renesas, Tokyo, Japan Violante Moschiano
Intel Italia SPA, Rome, Italy
Eric Karl
Intel, Portland, OR Bor-Doou Rong
Dongkyun Kim Etron, Hsinchu, Taiwan
SK hynix, Icheon, Korea
Hidehiro Shiga
Hye-Ran Kim KIOXIA, Yokohama, Japan
Samsung Electronics, Hwaseong, Korea
Kyu-Hyoun (KH) Kim Eric Wang
IBM T. J. Watson, Yorktown Heights, NY TSMC, Hsinchu, Taiwan

Power Management Subcommittee

Chair: Bernhard Wicht
University of Hannover, Hannover, Germany
Patrik Arno Yan Lu
ST Microelectronics, Sassenage, France University of Macau, Taipa, Macao, China
Saurav Bandyopadhyay Kousuke Miyaji
Texas Instruments, Dallas, TX Shinshu University, Nagano, Japan
Ke-Horng Chen Jiseon Paek
National Chiao Tung University, Pusan National University, Pusan, Korea
Hsinchu, Taiwan
Robert Pilawa
Min Chen University of California, Berkeley,
Innoscience America, Santa Clara, CA Berkeley, CA
Chan-Hong Chern Gael Pillonnet
TSMC, Hsinchu, Taiwan CEA-Leti, Grenoble, France
Li Geng Frank Prämaßing
Xi'an Jiaotong University, Xi'an, China Infineon Technologies Austria, Villach, Austria
Kuo-Chun Hsu Jason Stauth
MediaTek, Hsinchu, Taiwan Dartmouth College, Hanover, NH
Harish Krishnamurthy Chen-Kong Teh
Intel, Hillsboro, OR Toshiba, Kawasaki, Japan
Xun Liu Xin Zhang
The Chinese University of Hong Kong, IBM T. J. Watson Research Center,
Shenzhen, China Yorktown Heights, NY

60
 INTERNATIONAL TECHNICAL PROGRAM COMMITTEE
RF Subcommittee
Chair: Jan Craninckx
imec, Leuven, Belgium

Shuhei Amakawa Mona Hella

Hiroshima University, Rensselaer Polytechnic Institute, Troy, NY
Higashihiroshima, Japan
Shuya Kishimoto
Masoud Babaie NEC, Kawasaki, Japan
Delft University of Technology,
Delft,The Netherlands Salvatore Levantino
Politecnico di Milano, Milano, Italy
Yves Baeyens
Nokia - Bell Labs, Murray Hill, NJ Swaminathan Sankaran
James Buckwalter Texas Instruments, Dallas, TX
University of California, Santa Barbara,
Jeff Walling
Santa Barbara, CA
Virginia Tech., Blacksburg, VA
Dmytro Cherniak
Infineon Technologies, Villach, Austria Wanghua Wu
Samsung Semiconductor, San Jose, CA
Jaehyouk Choi
KAIST, Daejeon, Korea Hongtao Xu
Fudan University, Shanghai, China
Wei Deng
Tsinghua University, Beijing, China Jun Yin
Jeremy Dunworth University of Macau, Taipa, Macau, China
Qualcomm Technologies, San Diego, CA Conan Zhan
Ruonan Han MediaTek, Hsinchu, Taiwan
Massachusetts Institute of Technology,
Cambridge, MA

TD Subcommittee
Chair: Ali Hajimiri
Caltech, Pasadena, CA

Firooz Aflatouni Munehiko Nagatani

University of Pennsylvania, Philadelphia, PA NTT Corporation, Atsugi, Japan
Joseph Bardin Fabio Sebastiano
Google & UMass Amherst, Goleta, CA Delft University of Technology,
Denis Daly Delft, The Netherlands
Apple, Wellesley, MA Kaushik Sengupta
Giorgio Ferrari Princeton University, Princeton, NJ
Politecnico di Milano, Milano, Italy Sudip Shekhar
Shawn Shuo-Hung Hsu University of British Columbia,
National Tsing Hua University, Vancouver, Canada
Hsinchu, Taiwan Guy Torfs
Noriyuki Miura Ghent University, Gent, Belgium
Osaka University, Osaka, Japan
Rabia Tugce Yazicigil
Carolina Mora-Lopez Boston University, Boston, MA
imec, Leuven, Belgium
Milin Zhang
Daniel H. Morris Tsinghua University, Beijing, China
Meta, Sunnyvale, CA

61
 INTERNATIONAL TECHNICAL PROGRAM COMMITTEE
Wireless Subcommittee
Chair: Chih-Ming Hung
MediaTek, Taipei, Taiwan

Matteo Bassi Byung-Wook Min

Infineon Technologies, Villach, Austria Yonsei University, Seoul, Korea

Venumadhav Bhagavatula Jan Prummel

Samsung Semiconductor, San Jose, CA Renesas Electronics,
‘s-Hertogenbosch, The Netherlands
Wu-Hsin Chen
Qualcomm, San Diego, CA Negar Reiskarimian
Massachusetts Institute of Technology,
Vito Giannini Cambridge, MA
Uhnder, Austin, TX
Bodhisatwa Sadhu
Giuseppe Gramegna IBM T. J. Watson Research Center,
imec, Leuven, Belgium Yorktown Heights, NY

Jane Gu Shahriar Shahramian

University of California, Davis, Davis, CA Nokia – Bell Labs, New Providence, NJ

Hiroyuki Ito Ho-Jin Song

Tokyo Institute of Technology, Pohang University of Science and Technology,
Yokohama, Japan Pohang, Korea

Nagendra Krishnapura David Wentzloff

Indian Institute of Technology Madras, University of Michigan, Everactive,
Chennai, India Ann Arbor, MI

Renzhi Liu Alireza Zolfaghari

Intel, Hillsboro, OR Broadcom, Irvine, CA

Wireline Subcommittee
Chair: Yohan Frans
AMD, San Jose, CA

Tamer Ali Byungsub Kim

Mediatek, Pohang University of Science and Technology,
Irvine, CA Pohang, Korea
Mike Shuo-Wei Chen
University of Southern California, Mozhgan Mansuri
Los Angeles, CA Intel, Hillsboro, OR

Wei-Zen Chen Takashi Takemoto

National Yang Ming Chiao Tung University, Hitachi, Hokkaido University,
Hsinchu, Taiwan
Sapporo, Japan
Friedel Gerfers
Technische Universität Berlin, Thomas Toifl
Berlin, Germany Cisco Systems,
Wallisellen, Switzerland
Masum Hossain
University of Alberta,
Didem Turker Melek
Edmonton, Canada
Cadence Design Systems,
Kenny Hsieh San Jose, CA
TSMC, Hsinchu, Taiwan

62
 EUROPEAN REGIONAL SUBCOMMITTEE
ITPC EUROPEAN REGIONAL CHAIR
Bruce Rae
ST Microelectronics, Edinburgh, United Kingdom

ITPC EUROPEAN REGIONAL VICE CHAIR

Matteo Bassi
Infineon Technologies, Villach, Austria

ITPC EUROPEAN REGIONAL SECRETARY

Viola Schaffer
Texas Instruments, Freising, Germany
Jens Anders Carolina Mora-Lopez
University of Stuttgart, Stuttgart, Germany imec, Leuven, Belgium

Patrik Arno Dominique Morche

ST Microelectronics, Sassenage, France Département Architecture Conception et
Logiciel Embarqué (DACLE), CEA-Leti,
Masoud Babaie Grenoble, France
Delft University of Technology,
Delft, The Netherlands Violante Moschiano
Intel Italia SPA, Rome, Italy
Luca Benini
ETHZ and UNIBO, Zurich, Switzerland Maurits Ortmanns
University of Ulm, Ulm, Germany
Marco Berkhout
Goodix Technology, Gael Pillonnet
Nijmegen, The Netherlands CEA-Leti, Grenoble, France

Dmytro Cherniak Frank Prämaßing

Infineon Technologies, Villach, Austria Infineon Technologies Austria,
Villach, Austria
Jan Craninckx
imec, Leuven, Belgium Jan Prummel
Renesas Electronics,
Shidhartha Das s-Hertogenbosch, The Netherlands
Advanced Micro Devices,
Cambridge, United Kingdom
Fabio Sebastiano
Qinwen Fan Delft University of Technology,
Delft University of Technology, Delft, The Netherlands
Delft, The Netherlands
Mahsa Shoaran
Giorgio Ferrari EPFL, Geneva, Switzerland
Politecnico di Milano, Milano, Italy
Thomas Toifl
Leonardo Gasparini Cisco Systems, Wallisellen, Switzerland
Fondazione Bruno Kessler, Trento, Italy
Yvain Thonnart
Friedel Gerfers CEA-List, Grenoble, France
Technische Universität, Berlin,
Berlin, Germany Guy Torfs
Ghent University, Gent, Belgium
Giuseppe Gramegna
imec, Leuven, Belgium Ingrid Verbauwhede
KU Leuven, Leuven, Belgium
Sohmyung Ha
New York University, Marian Verhelst
New York University Abu Dhabi KU Leuven, Heverlee, Belgium
Abu Dhabi, United Arab Emirates
Jan Westra
Taekwang Jang Broadcom, Bunnik, The Netherlands
ETH Zurich, Zurich, Switzerland
Bernhard Wicht
Salvatore Levantino University of Hannover, Hannover, Germany
Politecnico di Milano, Milano, Italy

63
 FAR EAST REGIONAL SUBCOMMITTEE
ITPC FAR-EAST REGIONAL CHAIR
Jun Deguchi
Kioxia Corporation, Kawasaki, Japan

ITPC FAR-EAST REGIONAL VICE CHAIR

Man-Kay Law
University of Macau, Taipa, Macau, China

ITPC FAR-EAST REGIONAL SECRETARY

Jaehyouk Choi
KAIST, Daejeon, Korea

ITPC FAR-EAST REGIONAL ASSOCIATE SECRETARY

Wei-Zen Chen
National Yang Ming Chiao Tung University, Hsinchu, Taiwan

Ippei Akita Kuo-Chun Hsu

AIST, Tsukuba, Japan MediaTek, Hsinchu, Taiwan

Massimo Alioto Shawn Shuo-Hung Hsu

National University of Singapore, Singapore National Tsing Hua University,
Hsinchu, Taiwan
Shuhei Amakawa
Hiroshima University, Ru Huang
Higashihiroshima, Japan Peking University, Beijing, China

Joonsung Bae Chih-Ming Hung

Kangwon National University, MediaTek, Taipei, Taiwan
Chuncheon, Korea
Hiroyuki Ito
Meng-Fan Chang Tokyo Institute of Technology,
National Tsing Hua University, Yokohama, Japan
Hsinchu, Taiwan Takashi Ito
Renesas, Tokyo, Japan
Ke-Horng Chen
National Chiao Tung University, Minkyu Je
Hsinchu, Taiwan KAIST, Daejeon, Korea
Chan-Hong Chern Byungsub Kim
TSMC, Hsinchu, Taiwan Pohang University of Science
and Technology, Pohang, Korea
Jun-Chau Chien
National Taiwan University, Taipei, Taiwan Dongkyun Kim
SK hynix, Icheon, Korea
Wei Deng
Tsinghua University, Beijing, China Hye-Ran Kim
Samsung Electronics, Hwaseong, Korea
Eric Jia-Wei Fang
Mediatek, Hsinchu, Taiwan Ji-Hoon Kim
Ewha Womans University, Seoul, Korea
Kazuki Fukuoka
Renesas Electronics, Tokyo, Japan Seong-Jin Kim
Ulsan National Institute of Science
Li Geng and Technology, Ulsan, Korea
Xi'an Jiaotong University, Xi'an, China
Shuya Kishimoto
Mutsumi Hamaguchi NEC, Kawasaki, Japan
Sharp Corporation, Tenri, Nara, Japan
Nagendra Krishnapura
Kenny Hsieh Indian Institute of Technology Madras,
TSMC, Hsinchu, Taiwan Chennai, India

64
 FAR EAST REGIONAL SUBCOMMITTEE
Jongwoo Lee Masaki Sakakibara
Samsung Electronics, Hwasung, Korea Sony Semiconductor Solutions,
Atsugi, Japan
Junghyup Lee
DGIST, Daegu, Korea Hidehiro Shiga
KIOXIA, Yokohama, Japan
Seung-Jae Lee
Samsung, Hwaseong, Korea Ho-Jin Song
Pohang University of Science and Technology,
Ying-Zu Lin Pohang, Korea
Mediatek, Hsinchu, Taiwan
Nan Sun
Xun Liu Tsinghua University, Beijing, China
The Chinese University of Hong Kong,
Shenzhen, Shenzhen, China Takashi Takemoto
Hitachi, Hokkaido University,
Yongpan Liu Sapporo, Japan
Tsinghua University, Beijing, China
Kea-Tiong (Samuel) Tang
Yan Lu National Tsing Hua University,
University of Macau, Taipa, Macao Hsinchu, Taiwan

Chen-Kong Teh
Byung-Wook Min
Yonsei University, Seoul, Korea Toshiba, Kawasaki, Japan

Eric Wang
Noriyuki Miura
TSMC, Hsinchu, Taiwan
Osaka University, Osaka, Japan
Shon-Hang Wen
Kousuke Miyaji
MediaTek, Hsinchu, Taiwan
Shinshu University, Nagano, Japan
Hongtao Xu
Munehiko Nagatani Fudan University, Shanghai, China
NTT Corporation, Atsugi, Japan
Jiawei Xu
Kazuko Nishimura Fudan University, Shanghai, China
Panasonic Holdings, Moriguchi, Japan
Chia-Hsiang Yang
Mijung Noh National Taiwan University,
Samsung Electronics, Hwaseong, Korea Taipei, Taiwan

Sugako Otani Jerald Yoo

Renesas Electronics, Tokyo, Japan National University of Singapore,
Singapore
Jiseon Paek
Samsung Electronics, Cheonan, Korea Jun Yin
University of Macau, Taipa,
Rahul Rao Macau, China
IBM India, Bangalore, India
Conan Zhan
Bor-Doou Rong MediaTek, Hsinchu, Taiwan
Etron, Hsinchu, Taiwan
Yan Zhu
Soojung Ryu University of Macau Avenida
SAPEON Korea, Seongnam, Korea da Universidade, Taipa, Macau, China

Akihide Sai Milin Zhang

Toshiba, Kawasaki, Japan Tsinghua University, Beijing, China

65
 CONFERENCE INFORMATION
HOW TO REGISTER FOR ISSCC
Online: This is the only way to register and will give you immediate email confirmation of your events. Go
to the ISSCC website at www.isscc.org and select the link to the Registration website.
Payment Options: Immediate payment can be made online via credit card. Alternative payment options are
available including payment by check. Payment must be made within 10 days to hold your registration.
Registrations received without full payment will not be processed until payment is received at YesEvents.
Please read the instructions on the Registration website.

COVID 19 PROTOCOLS
The health and safety of our conference attendees is our top priority. The ISSCC 2023 conference Organizing
Committee remains vigilant in monitoring the COVID-19 pandemic. The conference will follow CDC and
State of California guidelines. ISSCC is planned as an in-person event but it also has an online offering. We
look forward to you joining us in San Francisco, CA. If you don’t feel comfortable participating in large
gatherings, if your organization has travel restrictions, we encourage you to join us online.

MASKS, VACCINATION, SANITIZERS

All participants are encouraged to wear an approved face covering at all times while inside the venue and
while attending ISSCC. Face coverings may be removed when actively eating, drinking, or giving a
presentation during a session.

Currently, proof of vaccination is no longer required in meetings in San Francisco. We will be monitoring
that regulation and the ISSCC website will be updated as regulations change.

Hand sanitizing lotion will be available throughout the hotel and at the Registration desk.

REGISTRATION DESK HOURS:

Saturday, February 18: 4:00 pm to 7:00 pm
Sunday, February 19: 7:00 am to 8:30 pm
Monday, February 20: 6:30 am to 3:00 pm
Tuesday, February 21: 8:00 am to 3:00 pm
Wednesday, February 22: 8:00 am to 3:00 pm
Thursday, February 23: 7:00 am to 2:00 pm

Students must present their Student ID at the Registration Desk to receive the student rates.
Those registering at the IEEE Member rate must provide their IEEE Membership number.

Deadlines: The deadline for registering at the Early Registration rates is 12:00 Midnight EST Sunday January
8, 2023. After January 8th, and before 12:00 Midnight EST Monday January 23, 2023, registrations will
be processed at the Late Registration rates. After January 23rd, you must register at the on-site rates.
You are urged to register early to obtain the lowest rates and ensure your participation in all aspects of
ISSCC.
Cancellations/Adjustments: Prior to 12:00 Midnight EST Monday January 23, 2023, conference registration
can be cancelled. Fees paid will be refunded (less a processing fee of $75). Send an email to the registration
contractor at [email protected] to cancel or make other adjustments.
No refunds will be made after 12:00 Midnight EST January 23, 2023. Paid registrants who do not attend
the conference will have access to the on-demand material.

IEEE MEMBERSHIP SAVES ON ISSCC REGISTRATION

Take advantage of reduced ISSCC fees by joining the Solid-State Circuits Society today, or by using your
IEEE membership number. If you’re an IEEE member and have forgotten your member number, simply
phone IEEE at 1(800) 678-4333 and ask. IEEE membership staff will take about two minutes to look up your
number for you. If you come to register on site without your membership card, you can phone IEEE then,
too. Or you can request a membership number look-up by email by using the online form at:
www.ieee.org/abouUhelp/member_support.html. If you’re not an IEEE member, consider joining before you
register to save on your fees. Join online at www.ieee.org/join any time and you’ll receive your member
number by email. If you join IEEE at the conference, you can also select a free Society membership. This
offer is not available to existing IEEE members.

66
 CONFERENCE INFORMATION
SSCS MEMBERSHIP -
A VALUABLE PROFESSIONAL RESOURCE FOR YOUR CAREER GROWTH
Get Connected! Stay Current! Invest in your Career! Membership in the Solid-State Circuits Society offers
you the chance to explore solutions within a global community of colleagues in our field. Membership
extends to you the opportunity to grow and share your knowledge, hone your expertise, expand or specialize
your network of colleagues, advance your career, and give back to the profession and your local community.

SSCS MEMBERSHIP DELIVERS:

Networking with peers - Educational development - Leadership opportunities
Tools for career growth - Recognition for your achievements
We invite you to join or renew today to participate in exclusive educational events, access to leading research
and best practice literature, and start your own career legacy by mentoring students and young professionals
entering our field. It all starts with becoming a member of the Solid-State Circuits Society where you can:
-Connect with your Peers - valuable networking opportunities through our world-class conferences,
publication offerings, social media extensions, and interactive educational opportunities.
-Keep up with the latest trends and cutting-edge developments in our industry - through our electronic
newsletters, member magazine “Solid-State Circuits Magazine”, and our award winning “Journal of Solid
State Circuits”.
-Access valuable career and educational tools - saving you both time and money with 24/7 access to our
website and members-only professional development and educational material; Distinguished Lecturer
Tours, Tutorials, and webinars by subject matter experts.
-Access exclusive SSCS Conference Digests for ISSCC, CICC, A-SSCC, ESSCIRC, and Symposium on VLSI
Circuits.
-Access publications and EBooks - discounted access to vast online document libraries of journals,
standards, and conference papers offer you one-third of the world’s technical research to keep your
knowledge current. Publications included in your SSCS membership are the “RFIC Virtual Journal” (RFVJ)
and the “Journal on Exploratory Solid-State Computational Devices and Circuits” (JxCDC), Solid State
Letters, and our newest Journal, the “Open Journal of Solid State Circuits” (OJ-SSC) an open access
publication.

SSCS MEMBERSHIP SAVES EVEN MORE ON ISSCC REGISTRATION

This year, SSCS members will again receive an exclusive benefit of a $30 discount on the registration fee
for ISSCC in addition to the IEEE discount. Also, the SSCS will again reward our members with a $10
Starbucks gift card when they attend the Conference as an SSCS member in good standing.

Join or renew your membership with IEEE’s Solid-State Circuits Society today at sscs.ieee.org - you will
not want to miss out on the opportunities and benefits your membership will provide now and throughout
your career.
ITEMS INCLUDED IN REGISTRATION
Technical Sessions: Registration includes admission to all technical and evening sessions starting Sunday
evening and continuing throughout Monday, Tuesday and Wednesday. ISSCC does not offer partial
conference registrations.
Technical Book Display: Several technical publishers will have collections of professional books and
textbooks for sale during the Conference. The Book Display will be open on Monday from Noon to 7:00 pm;
on Tuesday from 10:00 am to 7:00 pm; and on Wednesday from 10:00 am to 3:00 pm.
Demonstration Sessions: Hardware demonstrations will support selected papers on Monday and Tuesday
evenings.
Author Interviews: Author Interviews will be held Monday, Tuesday and Wednesday evenings. Authors from
each day’s papers will be available to discuss their work.
Monday Social Hour: Refreshments will be available starting at 5:15 pm.
University Events: Several universities are planning social events during the Conference. Check the
University Events display at the conference for the list of universities, locations and times of these events.
Publications: Conference registration includes:
-Papers Visuals: The visuals from all papers presented will be available by download.
-Demonstration Session Guidebook: A descriptive guide to the Demonstration Session will be available by
download.
-Note: Instructions will be provided for access to all downloads. Downloads will be available both during
the Conference and for a limited time afterwards.

67
 CONFERENCE INFORMATION
OPTIONAL EVENTS
Educational Events: Many educational events are available at ISSCC for an additional fee. There are twelve
90-minute Tutorials that will be available virtually, not in person at the conference, there is an in-person
Q&A. The forums and Short Course will be live, in-person. There will be three all-day Forums on Sunday.
There are four additional all-day Forums on Thursday as well as an all-day Short Course. The Forums and
Short Course include breakfast, lunch and break refreshments. See the schedule for details of the topics
and times.

OPTIONAL PUBLICATIONS
ISSCC 2023 Publications: The following ISSCC 2023 digital publications can be purchased in advance or
on site:
2023 ISSCC Download USB: All of the downloads included in conference registration, (regular papers and
presentations) (mailed in March)
2023 Tutorials USB: All of the 90 minute Tutorials (mailed in June).
2023 Short Course USB: (mailed in June).
The Short Course and Tutorial USBs contain audio and written English transcripts synchronized with the
presentation visuals. In addition, the USBs contain a pdf file of the presentations and pdf files of key reference
material.
Earlier ISSCC Publications: Selected publications from earlier conferences can be purchased. There are
several ways to purchase this material:
-Items listed on the registration website can be purchased with registration and picked up at the
conference.
-Visit the ISSCC Publications Desk. This desk is located in the registration area and has the same hours
as conference registration. With payment by cash, check or credit card, you can purchase materials at this
desk. See the posted list at the Conference for titles and prices.
-Visit the ISSCC website at www.isscc.org and click on the link “SHOP/Shop ISSCC/Shop Now” where you
can order online or download an order form to mail, email or fax. For a small shipping fee, this material will
be sent to you immediately and you will not have to wait until you attend the Conference to get it.

HOW TO MAKE HOTEL RESERVATIONS

Online: ISSCC participants are urged to make their hotel reservations at the San Francisco Marriott Marquis
online. Go to the conference website and click on the Hotel Reservation link. Conference room rates are
$306 for a single/double (per night plus tax). In addition, ISSCC attendees booked in the ISSCC group
receive in-room Internet access for free. All online reservations require the use of a credit card. Online
reservations are confirmed immediately. You should print the page containing your confirmation number
and reservation details and bring it with you when you travel to ISSCC. Telephone: Call 877- 622-3056 (US)
or 415-896-1600 and ask for “Reservations.” When making your reservation, identify the group as ISSCC
2022 to get the group rate.
Hotel Deadline: Reservations must be received at the San Francisco Marriott Marquis no later than 5 pm
Pacific Time January 29, 2023 to obtain the special ISSCC rates. A limited number of rooms are available
at these rates. Once this limit is reached or after January 29th, the group rates may no longer be available
and reservations will be filled at the best available rate. Changes: Before the hotel deadline, your
reservation can be changed by calling the telephone numbers above. After the hotel deadline, call the Marriott
Marquis at 415-896-1600 (ask for “Reservations”). Have your hotel confirmation number ready.

IEEE NON-DISCRIMINATION POLICY

IEEE is committed to the principle that all persons shall have equal access to programs, facilities, services,
and employment without regard to personal characteristics not related to ability, performance, or
qualifications as determined by IEEE policy and/or applicable laws.

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 CONFERENCE INFORMATION
EVENT PHOTOGRAPHY
Attendance at, or participation in, this conference constitutes consent to the use and distribution by IEEE of
the attendee’s image or voice for informational, publicity, promotional and/or reporting purposes in print or
electronic communications media. Video or audio recording by participants or other attendees during any
portion of the conference is not allowed without special prior written permission of IEEE.

TAKING PICTURES, VIDEOS OR AUDIO RECORDINGS

DURING ANY OF THE SESSIONS IS NOT PERMITTED

REFERENCE INFORMATION
Conference Website: www.isscc.org
ISSCC Email: [email protected]

Registration questions: [email protected]

Hotel Information: San Francisco Marriott Marquis Phone: 415-896-1600
780 Mission Street
San Francisco, CA 94103
Press Information: Kenneth C. Smith Phone: 416-418-3034
University of Toronto
Email: [email protected]
Registration: YesEvents Phone: 800-937-8728
PO Box 3024 Fax: 410-559-2236
Westminster, MD 21158
Email: [email protected]

Hotel Transportation
Visit the ISSCC website “Registration/Transportation from Airport” page for helpful travel
information and links. You can get a map and driving directions from the hotel website at:
www.marriott.com/hotels/travel/sfodt-san-francisco-marriott-marquis/

Next ISSCC Dates and Location:

ISSCC 2024 will be held on February 18-22, 2024
at the San Francisco Marriott Marquis Hotel.

SUBCOMMITTEE CHAIRS
Analog: Maurits Ortmanns
Data Converters: Jan Westra
Digital Architectures & Systems: Thomas Burd
Digital Circuits: Keith Bowman
Imagers, MEMS, Medical & Displays: Rikky Muller
Machine Learning & AI SukHwan Lim
Memory: Meng-Fan Chang
Power Management: Bernhard Wicht
RF: Jan Craninckx
Technology Directions: Ali Hajimiri
Wireless: Chih-Ming Hung
Wireline: Yohan Frans
Program-Committee Chair: Piet Wambacq
Program-Committee Vice-Chair: Frank O’Mahony
Conference Chair: Eugenio Cantatore

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 CONFERENCE SPACE LAYOUT

LOWER B2 LEVEL - YERBA BUENA BALLROOM

SALON 10

SALON 9

SALON 8

SALON 7

SALON 6

B2 LEVEL - GOLDEN GATE HALL

70
 445 Hoes Lane
P.O. Box 1331
Piscataway, NJ 08855-1331
USA
ISSCC.org
sscs.ieee.org
ISSCC 2023 ADVANCE PROGRAM