Chapter 3: Analysis of Redundant Signed Digit in

Pipelined ADC

One bit per Stage

The pipelined ADC architecture is a combination of n different stages organized in a

cascaded way. Different blocks of each stage of Pipelined ADC are S/H, m bit DAC,

analog subtractor, Analog to Digital Converter of m-bit, and a 2𝑚 gain amplifier. All

blocks are performing their own jobs to complete the function of an ADC [41-43]. The

block diagram of N-bit pipelined ADC which includes single stage architecture in Figure

3.1 (for m=1). At every clock cycle, the S/H takes the input voltage 𝑉𝑖𝑛 to sample and

the sampled value could be held for an extra time for hold period of S/H. The sub-ADC

converters the sampled input into equivalent digital signal and the purpose of sub DAC

is to generate the analog signal again from the generated digital output signal which

would be subtracted from 𝑉𝑖𝑛 to generate the new input signal also known as residue

signal for the following stage. Residue voltage generated is defined by following

equation

𝑉𝑟𝑒𝑠 = (𝑉𝑖𝑛 − 𝑉𝑑𝑎𝑐 )2𝑚

To find out the resolution of complete ADC, number of stages and resolution of each

stage should be considered. Suppose m number of stages are there and every stage is

capable to produce n bits, so m x n bits will be produced by complete ADC. The topology

or resolution of each stage defines the resolution of complete Pipelined ADC. By

considering each stage of 1-bit resolution and the time required to complete the process
34
by each stage is ‘k’ seconds, then the latency would be k.m seconds for ‘m’ number of

stages and 1/k samples/sec would be considered as throughput of ADC.

Figure 3.1: Pipelined ADC Architecture

The Multiplying Digital to Analog Converter

The MDAC (Multiplying Digital to Analog Converter) includes a sampler, a sub-DAC

block, a subtractor and a multiplier. The Output generated from MDAC is called residue

voltage (Vres). The MDAC (Multiplying Digital to Analog Converter) includes a

sampler, a sub-DAC block, a subtractor and a multiplier. The Output generated from

MDAC is called residue voltage (Vres) which treats as the input voltage for the following

stage. MDAC’s working is really simple and explained here. To produce the digital

output, firstly the sub-ADC quantizes the sampled input and then the sub-DAC converts

the output digital code into an equivalent analog signal. The converted analog signal has

been subtracted from the input sampled voltage for that stage and the difference

35
amplified to full scale voltage through inter-stage amplifier to produce the residue

voltage. This process continues till the last stage. If a pipelined ADC has ‘m’ no. of

stages, the first stage takes n number of clock to go through all the stages and the system

having latency of n-clock cycles. The next signal comes out after that and have the

latency of n-l clock cycles and so on. So, after n clock cycles, a complete digital output

comes out at every clock cycle. So, for 12-bit ADC, 12 clock cycles are required to

propagate up to the output of the last stage. Some shift registers as a delay elements are

used to store the output bit generated by sub-ADC. For ADC operation, pipelined

architecture uses a two-phase, non-overlapping clock signal as depicted in Figure 3.2

where S1 indicates stage 1 and S2 indicates stage 2 and so on. Practically all the stages

are working concurrently but performing different operations at different phases (φ1 and

φ2). During the first phase, φ1, each stage samples the input signal and generates a digital

output which would store in shift registers. During the hold phase, φ2, the generated

analog signal i.e the residue voltage passes to next stage.

S1 samples
Φ1 S1 samples S2 DAC+RA
S3 samples

S1 DAC+RA S1 DAC+RA
Φ2 S2 samples
S2 samples
S3 DAC+RA

S1 CMP
S1 CMP S2 CMP
S3 CMP

Figure 3.2: Timing Diagram of Pipelined ADC

36
In the duration of the hold phase i.e. under high valued φ1, MDAC samples the output

of S&H amplifier, converts into digital output and pass to delay element. During the

sample phase i.e. under high valued φ2, MDAC amplifies the subtracted signal and S/H

amplifier samples the next input. But, all the stages are working simultaneously just in

pipelining.

One bit per stage operation

Figure 3.3: One bit/Stage Implementation [41]

As shown in Figure 3.3 [41] one bit per stage consists of one comparator with latch inside

and a 2-input multiplexer (MUX2) at the output. Comparator output (C1P) is ready when

37
clock φ1 is high. Value of C1P is either 0 or logic 1 depends on value of Vin as compared

to Vref (reference value). If Vin<Vref, C1P would be logic 0 otherwise logic 1. C1P also

works as a select line for MUX2 which gives DAC output as Vdac. If C1P=0, Vdac

would be Vref– otherwise it would be Vref+. Here NMOS switches has been used for

simplicity. Practically CMOS transmission gate switches are more preferable than MOS

switches due to their low resistance and wide signal swing.

During the sampling mode when φ1=1, switch Ml and M2 are closed and M4, M5 are

open so both capacitors Cs and Cf are available to charge to the Input signal Vin. Here,

transistor M3 is also connected to common mode voltage Vcm (virtual short) as shown

in Figure. 3.4. Comparator is active now and comparing the input voltage Vin with Vref

and gives output C1P so that Vdac from MUX2. The output of sub-DAC, Vdac is stored

in the parasitic capacitor Cp at that node which would be used in φ2 phase. Here,

capacitor CL is shown at the output of OPAMP X1 which is the parasitic load capacitor

due to various parasitic capacitors present at that node.

38
 Figure 3.4: Sampling phase (during φ1 is high)

Ref. to Figure. 3.5, in the duration of staying high φ2 i.e. amplification phase duration,

switch Ml, M2 and M3 are open and switch M4, M5 are closed by which capacitor Cf

made a link to the output of OP-AMP X1 and multiplexer’s output (Vdac) is connected

to the capacitor CS. Switch M6 is also turned ON during this phase. NMOS switch M6,

capacitor Ch and OPAMP X2 in unity gain configuration work altogether as sample and

hold amplifier. During this phase, output of Xl is stored in Ch and therefore in CL, works

as Vout.

39
 Figure 3.5: Amplification phase (Φ2 high)

Again, when φ1 phase becomes high, the value stored in Ch acts as input for next stage.

To stabilize the output Vout i.e the input of next stage, sample and hold amplifier is used

for that. In absence of S/H amplifier (consists of M6, Ch and X2), the output of OPAMP

Xl decreases because of NMOS, in the output stage of OPAMP, is always ON. So, it’s

required to stabilize the output of MDAC, Vout. During φ1, in ref. to Figure. 3.4,

capacitor Cs and Cf are charged to Vcm-Vin. So, the charge stored in both capacitors is

given by

Qs= (Vcm-Vin)(Cs+Cf) 3.1

Where Vcm is the dc bias voltage just to keep input MOS transistor of OPAMP in the

saturation region only which is usually in the mid of ICMR of OPAMP. Because the

ideal OPAMP with very high gain is assumed here, inverting terminal is virtually

40
connected to non-inverting terminal of OPAMP and Vin is the input signal in the range

of Vref- and Vref+.

During φ2, in ref. to Figure. 3.5, charge stored in both the capacitors is

Qa = (Vcm-Vdac) Cs + (Vcm-Vout) Cf 3.2

where Vdac is the output voltage from sub-DAC.

By applying charge conservation at inverting terminal of OPAMP, we get Qs=Qa

By solving equations 3.1 and 3.2 for Vcm,

𝐶𝑓 𝐶𝑓
𝑉𝑜𝑢𝑡 = (1 + 𝐶𝑠 )𝑉𝑖𝑛 − ( 𝐶𝑠 )𝑉𝑑𝑎𝑐 3.3

If Cs=Cf 𝑉𝑜𝑢𝑡 = 2𝑉𝑖𝑛 − 𝑉𝑑𝑎𝑐 3.4

Thus, when Vin < Vref,

Vdac = Vref- and Vout = 2Vin-(Vref-) 3.5

When Vin > Vref,

Vdac = Vref+ and Vout = 2Vin-(Vref+) 3.6

where Vref is the threshold voltage of comparator comp1

For Vin = Vref and depending upon the offset voltage of comparator, Vout could be

followed by either equation (3.5) or (3.6). The residue graph of stage 1 for ideal stage is

shown in Figure. 3.6.

41
 Figure 3.6: Residue Transfer function of stage 1

For the next stage the input voltage generates from last stage’s residue voltage. For 1 bit/

stage architecture, each stage will go through a gain of 2 to make their transitions at faster

rate and to the full scale voltage.

Figure 3.7: Ideal output if 0.7V is given at first stage.

42
Here, 4-bit Pipelined ADC has been taken to explain the process of generation of residue

voltages for various stages as shown in Figure 3.7. Consider the input for first stage is

0.7V, + 𝑉𝑟𝑒𝑓 is 1V, – 𝑉𝑟𝑒𝑓 is 0V, 𝑉𝑚𝑖𝑑 is 0.5V, so, the residue voltage generated by stage

1 is 2x0.7- 1=0.4 V and the output 𝐷𝑜𝑢𝑡 is logic 1. Now for the stage 2 the input voltage

is 0.4 V which is less than 𝑉𝑚𝑖𝑑 , the residue voltage 𝑉𝑟𝑒𝑠 for the next stage is

0.4x2+0=0.8V, and the digital bit for this stage is 𝐷𝑜𝑢𝑡 is ‘0’. Because the input voltage

for this stage is 0.8V which is more than 𝑉𝑚𝑖𝑑 , 0.5V so the residue voltage for the third

stage is 0.8x2-1=0.6V and digital o/p is ‘1’. At the fourth stage, the input voltage is

greater than 𝑉𝑚𝑖𝑑 so digital bit for this stage is ‘1’. Now the overall digital output as the

combination of all four stages would be 1011.

Figure 3.8: Residue Transfer function with comparator offset

43
Figure 3.8 demonstrates the comparator offset error at single stage due to which the

residue voltage could shift to other point other than the ideal.

To explain the problem of 1-bit stage assuming the residue voltage of first stage shifts

from 0.4 V to 0.5 V due to comparator offset error. In Pipelined ADC, this error will

propagate through all stages [44-45]. The digital output corresponding to second stage

would be ‘1’ instead of ‘0’ and 𝑉𝑟𝑒𝑠 is 0.5x2-1=0V for next stage which makes all other

stages erroneous. The complete digital output would be 1100 instead of 1011 as shown

in Figure 3.9. But this error could be removed using 1.5 bit per stage Pipelined ADC.

Figure 3.9: Comparator error at one stage propagates through all stages

44
 1.5-bit Stage

The 1.5-bit per stage is the most common topology in Pipelined ADCs. As shown in

Figure 3.10, each stage is generating two bits because two comparators are used here for

each stage which compares with reference value as (+Vref/4 and -Vref/4) to convert

analog value into digital value. There is a way to relax the accuracy requirements of the

ADCs by lowering the inter stage amplifier gain. By using this configuration of Pipelined

ADC, high speed and high resolution could be achieved because each stage is generating

more no. of bits with high tolerance of error and inter stage gain amplifier [46-48]. The

MDAC used in real circuits is most commonly fully differential circuits to overwhelm

common-mode noise but the MDAC considered here is single ended for simplicity only.

Figure 3.10: 1.5 bit Stage

45
 Figure 3.11: MDAC during sampling phase

Figure 3.12: MDAC during amplification phase

46
The DAC has three different operating modes for 1.5 bit/stage architecture to generate

digital outputs. The functionality of 1.5 bit/stage could be clear with the help of following

equations.

𝐶𝑠 𝐶𝑠
(1 + 𝐶𝑓) 𝑉𝑖 + 𝐶𝑓 𝑉𝑟𝑒𝑓 𝑖𝑓 𝑉𝑖 < −𝑉𝑟𝑒𝑓/4
𝐶𝑠 𝑉𝑟𝑒𝑓
Vo= (1 + 𝐶𝑓) 𝑉𝑖 𝑖𝑓 − ≤ 𝑉𝑖 ≤ +𝑉𝑟𝑒𝑓/4
4
𝐶𝑠 𝐶𝑠
{ (1 + 𝐶𝑓) 𝑉𝑖 − 𝐶𝑓 𝑉𝑟𝑒𝑓 𝑖𝑓 𝑉𝑖 > +𝑉𝑟𝑒𝑓/4

In reference to Figure 3.13 and based on above equations, three different operating

regions are

Region 1: = 00: Vi< -Vref/4

During sampling phase ref. to Figure. 3.11

QC1=C1Vi, and QC2=C2Vi

During amplification phase ref. to Figure 3.12

C1 can achieve the value as -Vref,

And using the theory of charge conservation,

C1Vi+C2Vi=C1(-Vref) +C2 Vout

Therefore, the output would be

𝐶1+𝐶2 𝐶1
𝑉𝑜𝑢𝑡 = 𝑉𝑖 + 𝐶2 𝑉𝑟𝑒𝑓
𝐶2

47
By considering capacitor matching, C1=C2, then Vout=2Vi+Vref

𝑽𝒓𝒆𝒇
𝑽𝒐𝒖𝒕 = 𝟐(𝑽𝒊 + )
𝟐

Region 2: 01: when Vref/4 <Vin >- Vref/4

For sampling phase ( ), charge QC1=C1Vin and charge QC2=C2Vin

For Amplification phase ( ), C1 has discharged, thus by charge conservation theory by

considering virtual ground concept,

C1Vin + C2Vin = C2Vout

𝐶1+𝐶2
And 𝑉𝑜𝑢𝑡 = 𝑉𝑖
𝐶2

If both capacitors are of same value, C1=C2, then

Vout=2Vin

Region 3: 10: Vi> Vref/4, over range error so required a subtraction factor of Vref/2

from Vi input voltage

For sampling phase :

charge QC1=C1Vi and charge QC2=C2Vi

For Amplification phase :

capacitor C1 has charged to Vref

by using charge conservation theory

48
C1Vin + C2Vin = C1Vref +C2Vout and

𝐶1+𝐶2 𝐶1
Vout = 𝑉𝑖 − 𝐶2 𝑉𝑟𝑒𝑓
𝐶2

By considering both capacitors C1 and C2 are of same value,

𝑉𝑟𝑒𝑓
So, Vout = 2Vin-Vref = 2(𝑉𝑖 − )
2

The residue graph of 1.5-bit stage Pipelined ADC is depicted in Figure 3.13. The DAC

is performing the function of a multiplex who decides the value of 𝑉𝑟𝑒𝑓 modified with

input voltage.

00 01 10
Vout

Vref

1/2Vref

-1/2Vref

-Vref
-Vref -1/4Vref 0 +1/4Vref Vref Vin

Figure 3.13: Ideal Residue Voltage for 1.5-bit Stage

𝑉𝑟𝑒𝑓 could be subtracted, added or pass the input without any modifications. The

different imperfections and errors generated by the comparators could be removed by

this added 0.5-bit redundancy. With the help of extra digital block for error correction,

the cancelation of redundancy is possible. The amplification value remains same as 1-

bit/stage as 2 to maintain the full scale range of all stages. So, the bandwidth could be

49
 maximized as the product of gain bandwidth remains constant. Afterwards the speed of

the converter could be increased. Figure 3.14 shows the digital output and residues for

succeeding stages again by taking an example of specific input voltage [49].

Figure 3.114: 1.5 bit per stage Pipelined ADC with digital output at different stages

The 1.5-bit pipelined ADC removes the effect of non-ideal components on ADC without

making any change in digital output as shown in Figure 3.15 [50] when the residue

voltage of first stage shifts from its original value due to comparator offset error. This

happened due to three different operating regions for output and the output stays in the

same region even after small amount of offset error. So, this change in residue voltage

50
 doesn’t make any change in final output and this error will not propagate through all

stages as shown in Figure 3.14 and 3.15.

Figure 3.15: The capability of 1.5 bit per stage ADC to remove comparator error

Redundant Signed Digit to Binary Conversion

The redundant signed digit, RSD is shown in Figure 3.16 which clearly shows that the

process of redundancy could be achieved by the architecture itself with the help of two

digital outputs.

51
 Figure 3.16: The trend to achieve final digital output through RSD [50].

The final digital conversion starts from the binary bits generated by the last stage. Each

stage uses delay units or registers to store the digital bits, 2 different registers for two

bits per stage [50]. Stage 1 uses n-1 delay units for single bit if there are n number of

stages. The second stage again has to save its generated bits to registers, so it requires n-

2 number of delta units for single bit. At every clock cycle all bits stored in registers shift

to next registers and new generated bits comes in those delay units. Figure 3.17 shows

the role of digital correction unit or redundant signed digit (RSD) block where half adders

and full adders are used to find out the final digital output. The process of binary

conversion starts from the two bits generated by the last stage to generate LSBs first. The

sum generated from each adder is used as the final bit of digital output and carry

generated from each adder has been promoted to next adder to finalize next higher bit of

digital output. The sum bit generated from the last adder towards left side will act as a

52
most significant bit (MSB) of the final digital generated code and the carry output of the

same adder will act as sign digit, D0.

Figure 3.17: 14-bit Digital Correction Logic

53
 The Proposed RSD for 1.5 bit per stage ADC

In the present architecture of 1.5bit/stage Pipelined ADC architecture, the first stage uses

n-1 delay units or registers to store outputs at different clock intervals [51-52]. Stage 1

uses 4 delay units if there are 4 different stages. At every clock cycle, the new output bit

comes from the stage saves in the register and other outputs shift by to the next register.

Similarly stage 2 uses n-2 delay units and all other stages got a shift register having

registers one less than previous stage’s delay units. In this process, all the bits from all

stages could be stored and used all together in digital correction block, RSD. All stages

are able to produce 2 bits and one bit is redundant bit out of those. Starting from last

stage all bits are fed to full adders. In this proposed method, instead of using full adders,

only half adders are used. In the process of generation of final digital output, wait time

for carry generation from the previous adder is zero. Addition of bits is fast and quick

process because it performs in only two steps as shown in Figure 3.17. For this 4-bit

Pipelined ADC, the circuit is no longer require to store initial bits. The adder starts

producing results in the first step by taking one bit from the current stage and one bit

generated from the previous stage. Now, to find out the actual result this adder result also

requires a carry bit generated from LSBs addition. For this purpose, an exclusive-or gate

along with a half adder is used. Half adder used in second step could generate two bits

as usual. The sum output from LSB will work as first least significant bit and the carry

bit forwarded to exclusive gate where it will work with other bit and generate the second

LSB. By using this method, a large reduction of logic gates from the last design and at

the same time faster than the previous design. So this design is quite reasonable in all

aspects of time and area. The RSD shown in Figure 3.18 is only for 4-bit ADC for
54
simplification and clear explanation. The same logic has been applied for 14-bit ADC

and achieve fast and quick results. The proposed technique of 4-bit Pipelined ADC was

simulated using MATLAB simulation tool.

Figure 3.18: Proposed Redundant Signed Digit (RSD) logic

Results and Measurements

Here a high speed 14-bit pipelined ADC with proposed RSD circuit is modelled and

simulated in MATLAB and VHDL. In addition of reduced number of gate count and

increased processing speed, SNR, SFDR and SNDR also increased. To realize the

proposed architecture of ADC model, different simulations has been done in MATLAB

55
as well as in Xilinx in an effective way. With this ADC model, the complexity has been

transferred from analog domain to digital domain. This design is also a FPGA supportive.

For this proposed Pipelined ADC of 14 bits with 100MSample/s, improved results are

achieved. To verify the proposed model of Pipelined ADC with different active sources

of errors, the operation of a pipelined ADC analysed in the form of several simulations

with analog input voltage. Because the assumption for the capacitor mismatch error is

in between 0.1% to 0.5%, the operation of 14-bit Pipelined ADC has been applied 1024

point FFT to find out SNR, SNDR and SFDR with the proposed technique. Here the

SNR is 85.9 dB, SNDR (Signal to noise and distortion ratio) is 85.89 dB and SFDR

(Spurious free dynamic range) is 102.8 dB. We have done static performance of both

designs of Digital error correction Logic. There is very less hardware utilization for

proposed method with high processing speed comparatively. Post-processing results

obtained after applying FFT on ADC model, SNDR became 85.89 dB, SNR became

85.9dBand SFDR became 102.8 dB as shown in Figure 3.19. The reconstruction of the

analog voltage has been validated also.

56
 Figure 3.19: 1024 point FFT

2.5 Bit Stage Operation

Here, in each stage with the help of high speed flash ADCs, the input voltage is converted

to 3 binary digits and with the help of DAC, digital raw bits reconstructed back to analog.

Same as other types of Pipelined ADC, the reconstructed analog signal is deducted from

original input signal and the result of difference of two signals is multiplied by a factor

to produce the residue signal which works as input signal for next stage [51]. As the

pipelined ADC produces latency to the digitally converted data firstly, but there is only

one conversion per clock cycle after that. Due to this concurrency, the conversion rate of

the Pipelined ADC is independent to the number of stages. In Figure 3.20, the 2.5-bit

stage MDAC is represented and in Figure 3.21 its respective residue signal is shown. For

2.5-bit flash ADC, the reference voltages for 6 different comparators are 3/16 Vref, 5/16

Vref, 7/16 Vref, 9/16 Vref,11/16 Vref and 13/16 Vref along with the sampled and hold

57
signal. The correction range of the ADC is 1/4 Vref. Amplifier gain is required as 4x. If

the gain and offset errors comes within this range, by digital correction, it could be

resolved and other stages would not be saturated due to error. The required DAC is 7

level DAC and the max tolerance with 2.5 bit on comparator offset is ±VR/8. The output

voltage of 2.5 bit per stage is defined by

Vout =4 Vin – Dout.Vref

Φ2

Φ1 C1
Vi
Φ1 C2

VR1
Φ1 C3
...

6
VR
6 CMP’s b Φ1 C4
A Vo
-VR Φ2
Φ1e
Φ2
0 Decoder
Φ2
VR

Figure 3.20: 2.5 bit MDAC

58
 Figure 3.21: Residue Transfer Function of 2.5-bit stage

Multi-bit Pipelined ADC

Although the most popular type is 1.5 bit per stage implementation. But that is good for

low resolution ADCs only. For high resolution and low power applications, Multi-Bit

Pipelined ADCs are used where sub-ADC resolution is greater than 2 bits per stage, so

named as multi-bit stage. The selection of stage-bit-size also decides the linearity, power

dissipation, noise performance and circuit complexity. ADC architecture should be

capable to provide solutions to correct flash and offset errors, comparator offset errors,

non-linearity errors etc. Low power dissipation and long battery life is the most

demanding feature in today’s era. Minimal power dissipation depends on circuit

59
components, power amplifiers and number of comparators used for ADC and also on

how these components are situated after layout. One bit per stage pipeline ADC requires

less power comparatively i.e. power required for multiplications and number of

comparators used per stage. Single stage Residue amplifiers requires low gain-

bandwidth amplifiers to draw less current than the higher gain-bandwidth amplifiers,

which are required by multibit per stage pipeline ADCs. Also, a single comparator per

stage dissipates much less power than larger multibit comparator arrays required by

multibit per stage ADCs. For low speed applications, multibit per stage ADCs could be

designed to dissipate same amount of power as the single bit per stage ADC does.

Although the area required by multibit per stage is more than a single bit per stage. To

achieve maximum dynamic range, a better noise performance is required for most of the

applications. SHA and first few stages are major noise contributors in ADCs. To decrease

the noise level, the input capacitance of a stage should be increased. So, by keeping the

input capacitances of the first few stages large, the noise performance of a single bit per

stage ADC could be improved. But large capacitor sizes carry out a large power to run

the ADC properly. In a multibit per stage ADC, the SHA and the first stage contributes

in noise performance mainly. To ensure noise performance, large capacitors are still

needed by the SHA and first stage, but for the second and subsequent stages smaller input

capacitors can work well. The multi-bit per stage are more relaxed for power constraints

on the residue amplifiers comparative to single-bit per stage ADC. As a result, multibit

per stage ADCs, the power could be reduced with better noise performance. Another

advantage of multibit per stage ADC is its ability to relax residue amplifier offsets and

flash decision errors reducing the chances of over-range conditions. On the other hand,

60
single bit per stage ADCs cannot relax from these errors without specific design

considerations. For total error correction, multibit per stage ADCs requires fewer design

considerations. Multi-bit 1st stage is more preferable than single bit per stage due to (1)

As soon as the first stage comes into settling mode from sample mode, a step voltage

(Vm) may appear. As per Ref. [52-54] if 1st stage has higher in resolution, the step

voltage amplitude is lower in proportion. The small-signal band width is always

desirable in comparison to the large-signal slew rate because the Vgs-Vt has limitation

for the op-amp design in the advanced CMOS process. So, a multi-bit structure is really

a good option for this case. (2) Multi-bit first stage is recommended due to Capacitor

mismatching error relaxation to achieve higher resolution sometimes without calibration

also (3) More power efficient structure as compared to single bit/stage ADC only at the

cost of circuit complexity.

SHA-less Pipelined ADCs

Both the sub-ADC and the S/H in the first stage samples same input signal (dynamic in

nature) simultaneously in SHA-less Pipelined architecture because of the absence of held

signal. If there is a bandwidth mismatch between their input networks, the problem of

different sampled values for the same event can appear i.e sampling clock skew.

Sometimes this mismatch error passes uncorrected when it doesn’t come in digital error-

correction range and becomes a gross conversion error. In that case SHA-less design is

more critical than a traditional front-end SHA design. In the classic model of Pipelined

ADC implementation, a dedicated sample and hold amplifier (SHA) is used before the

61
first stage for improving the dynamic performance of Pipelined ADC as shown in Figure

3.22 [55]. The purpose of the front-end SHA is to ensure the sub-ADC path and the S/H

both will attain the same sample value of the input signal irrespective to sampling clock

skew between the sub-ADC and the S/H.

Figure 3.22: SHA holds the signal when the first stage samples.

The sample and hold Amplifier (SHA) consists of an operational amplifier based

switched capacitor circuit for tracking/sampling the analog input signal and holding the

same value. In Pipelined ADCs, most widely used SHA is a flip-around SHA because of

simplicity and large closed loop bandwidth, is shown in Figure 3.23(a) [56]. This SHA

works on a non-overlapping clock scheme as shown in Figure 3.23(b).

62
 Figure 3.23: Flip-around SHA (a) and timing diagram (b).

At phase Ф1, the sampling capacitor Cs samples to the input Vin and the op-amp resets

in the same time; at phase Ф2, the lower capacitor side of Cs is associated to the output

of Op-amp, to make it same as Vin. In the phase Ф2, the op-amp output should swing

from 0 to Vin. In differential circuits, the output common mode of the flip-around SHA

is determined by the common mode input signal because the SHA output is duplication

of the input. Because the linearity of SHA is directly dependent on the characteristics of

op-amp so hard to achieve a high gain op-amp with a large swing.

Other type of SHA is Pre-charge SHA as shown in Figure 3.24. This SHA is capable to

reduce the op-amp swing requirement [57]. Both the capacitors Cs and Co are sampled

at phase Ф1 and charged to Vin. At the same time the op-amp resets to ground. On other

phase, the op-amp has to supply a voltage at ground to maintain SHA output at Vin only.

In this SHA, op-amp requires almost zero swing. But the common mode output of a Pre-

charged SHA should be same as the common mode input.

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 Figure 3.24: Pre-Charge SHA

For the applications requiring different input and output common modes, a charge

redistribution SHA can be used instead which is shown in Figure 3.25. At Ф1, the

capacitor Cs charged to the input voltage Vin and at Ф2, Cf will charge the value of Cs

which pushes the SHA output to Vin. Only the differential charge is transferred to the

differential circuits during Ф2, so the input and output common modes are decoupled.

Therefore, a large input common mode range is available for a charge redistribution

SHA. There is no scope for signal dependent disturbance to the input because the

sampling capacitor is always reset before connecting to the input again.

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 Figure 3.25: Charge redistribution SHA.

There are some points to be noted down for all types of SHAs are

 Requires an op-amp with optimized DC gain, bandwidth, noise, and power.

 The front-end SHA contributes to noise of the ADC.

 Front-end SHA consumes substantial power and leads to increase the total power

consumption of the ADC.

 To achieve the same SNR performance as the SHA-less, the value of sampling

capacitance has to be increased.

 The design of front-end SHA is a thought-provoking task for high-speed and

high-resolution ADCs.

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 A comparison of with SHA and without SHA Pipelined
ADC

A comparison of the power consumption and the input capacitance without any parasitic

capacitance of a Pipelined ADCs with dedicated front-end SHA and a SHA-less

Pipelined ADC is shown in Figure. 3.26 [58-60]. The comparison of with dedicated

front-end SHA and a SHA-less Pipelined ADC at medium speed and resolution is shown

in Figure 3.27 and the comparison at high speed and high resolution is shown in Figure

3.28. As per the noise analysis, assumes the stages in a Pipelined ADC has the same

bandwidth, resolution, and scaling factor of 1/2n of all stages, op-amps in folded cascode

structure, have the same overdrive voltage; and considered the front-end SHA is a flip-

around SHA. The comparison results of the ADC total input capacitance (Cinw SHA/Cin

SHAless ) and the ADC power consumption of dedicated front-end SHA and SHA-less

Pipelined ADC (PwSHA/PSHAless) are plotted w.r.t the ratio between the sampling

capacitance of SHA and the full sampling capacitance of the ADC’s first stage. These

plots are concluded that Pipelined ADC with dedicated front-end SHA results in at least

50% increase in power consumption and ADC input capacitance after wards. But at high

frequencies, low power consumption is required along with a low input capacitance and

can achieve good input linearity at high input frequencies. Apart of that, the dedicated

front-end SHA induces distortion and the designing of front end SHA is hard at high-

speed and high-resolution ADCs. So, elimination of the front-end SHA is a good choice

to save power, sampling capacitance, and complexity. But SHA-less Pipelined ADC’s

requires a special clock circuit to avoid any kind of sampling clock skew at high input

frequencies.
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Figure 3.26: Comparison between pipeline ADCs with SHA and without SHA with no parasitic

(ηo= ηg=0).

Figure 3.27: Power and input capacitance comparison between pipeline ADCs with SHA and

without SHA at medium speed and resolution (ηo= ηg=0.5).

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Figure 3.128: Power and input capacitance comparison between pipeline ADCs with SHA and

without SHA at high speed and resolution (ηo= ηg=1).

68