Low Power VLSI Design

Observation on switching power reduction

(i) reduction of the power supply voltage VDD.

(ii) reduction of the voltage swing in all nodes.

(iii) reduction of the switching probability (transition factor).

(iv) reduction of the load capacitance.

The switching power dissipation is also a linear function of the clock frequency, yet
simply reducing the frequency would significantly diminish the overall system
performance. Thus, the reduction of clock frequency would be a viable option only in
cases where the overall throughput of the system can be maintained by other means.
Occurs due to finite delay of gates, output is becoming high some small time
 Leakage current
The reverse diode leakage occurs when the pn-junction between the drain and the bulk
of the transistor is reverse biased.

The reverse biased drain junction then conducts a reverse saturation current which is
drawn from the power supply.

Consider a CMOS inverter with a high input voltage, where the nMOS transistor is
turned on and the output node voltage is discharged to zero. Although the pMOS
transistor is turned off, there will be a reverse potential difference of VDD between its
drain and the n-well, causing a diode leakage through the drain junction.

The n-well region of the pMOS transistor is also reverse- biased with VDD, with respect
to the p-type substrate. Therefore, another significant leakage current component exists
because of the n-well junction
Leakage Power Dissipation
 Subthreshold Leakage current
It is due to carrier diffusion between the source and the drain regions of the transistor
in weak inversion.

The behavior of an MOS transistor in the subthreshold operating region is similar to a

The amount of the subthreshold current may become significant when the gate-to-
source voltage is smaller than, but very close to, the threshold voltage of the device.

In this case, the power dissipation due to subthreshold leakage can become comparable
in magnitude to the switching power dissipation of the circuit.
Subthreshold Leakage current
Low power design through voltage scaling
Average switching power dissipation is proportional to the square of the power
supply voltage, hence, reduction of VDD will significantly reduce the power
consumption.

The propagation delay expressions for the CMOS inverter circuit is shown below
If the power supply voltage is scaled down while all other parameters are kept constant, the
propagation delay time would increase.

If the circuit is always operated at the maximum frequency allowed by its propagation delay,
the number of switching events per unit time (i.e., the operating frequency) will drop as the
propagation delay becomes larger with the reduction of the power supply voltage. The net
result is that the dependence of switching power dissipation on the power supply voltage
becomes stronger than a simple quadratic relationship,

The propagation delay expressions show the negative effect of reducing the power supply
voltage upon delay can be compensated for, if the threshold voltage of the transistors (V T) is
scaled down accordingly.

When scaled linearly, reduced threshold voltages allow the circuit to produce the same
speed-performance at a lower VDD.

Following figure shows the variation of the propagation delay of a CMOS inverter as a
function of the power supply voltage, and for different threshold voltage values.
Smaller threshold voltages lead to smaller noise margins for the CMOS logic gates.

The subthreshold conduction current also sets a severe limitation against reducing
the threshold voltage.

For threshold voltages smaller than 0.2 V, leakage due to subthreshold conduction
power dissipation increases.

we will see two circuit design techniques which can be used to overcome the
difficulties (such as leakage and high stand-by power dissipation) associated with
the low- V T circuits. These techniques are called Variable-Threshold CMOS
(VTCMOS) and Multiple-Threshold CMOS (MTCMOS).
Variable threshold CMOS(VTCMOS) Circuits
We have seen that using a low supply voltage (VDD) and a low threshold voltage (V T) in CMOS
logic circuits is an efficient method for reducing the overall power dissipation, while
maintaining high speed performance.

CMOS logic gate entirely with low-V T transistors will inevitably lead to increased subthreshold
leakage, and consequently, to higher stand-by power dissipation when the output is not
switching.

One possible way to overcome this problem is to adjust the threshold voltages of the transistors
in order to avoid leakage in the stand-by mode, by changing the substrate bias.

In VTCMOS circuit technique, the transistors are designed inherently with a low threshold
voltage, and the substrate bias voltages of nMOS and pMOS transistors are generated by a
variable substrate bias control circuit.
When the inverter circuit is operating in its active mode, the substrate bias voltage of the
nMOS transistor is VBn = 0 and the the substrate bias voltage of the pMOS transistor is VBp =
VDD.
Thus, the inverter transistors do not experience any backgate-bias effect and circuit operates
with low VDD and low V T, benefiting from both low power dissipation (due to low VDD) and
high switching speed (due to low V T).

When the inverter circuit is in the stand-by mode, however, the substrate bias control circuit
generates a lower substrate bias voltage for the nMOS transistor and a higher substrate bias
voltage for the pMOS transistor.

As a result, the magnitudes of the threshold voltages V Tn and V Tp, both increase in the stand-
by mode, due to the backgate-bias effect. Since the subthreshold leakage current drops
exponentially with increasing threshold voltage, the leakage power dissipation in the stand-by
mode can be significantly reduced with this technique.
The VTCMOS technique can also be used to automatically control the threshold
voltages of the transistors in order to reduce leakage currents, and to compensate for
process-related fluctuations of the threshold voltages. This approach is also called the
Self-Adjusting Threshold-Voltage Scheme (SATS).

The variable-threshold CMOS circuit design techniques are very effective for reducing
the subthreshold leakage currents and for controlling threshold voltage values in low
VDD - low V T applications.

However, this technique usually requires twin-well or triple-well CMOS technology in

Separate power pins may be required if the substrate bias voltage levels are not
generated on-chip. The additional area occupied by the substrate bias control circuitry
is usually negligible compared to the overall chip area.
Multiple-Threshold CMOS (MTCMOS) Circuits
Another technique which can be applied for reducing leakage currents in low voltage
circuits in the stand-by mode is based on using two different types of transistors (both
nMOS and pMOS) with two different threshold voltages in the circuit.
Here, low-V T transistors are typically used to design the logic gates where switching
speed is essential, whereas high- V T transistors are used to effectively isolate the logic
gates in stand-by and to prevent leakage dissipation.
In the active mode, the high-V T transistors are turned on and the logic gates consisting
of low-V T transistors can operate with low switching power dissipation and small
propagation delay.
When the circuit is driven into stand-by mode, on the other hand, the high-V T
transistors are turned off and the conduction paths for any subthreshold leakage
currents that may originate from the internal low-V T circuitry are effectively cut off.