ISSCC 2003 / SESSION 25 / RF INFOTAINMENT / PAPER 25.

25.7 A 2GHz 16dBm IIP3 Low Noise Amplifier range where the phase difference is below 30O, which is also con-
in 0.25µm CMOS Technology firmed by transient and harmonic simulations. This wide oper-
ating range comes from its inherent small path delay of Io- deter-
mined directly by the input signal.
Yong-Sik Youn, Jae-Hong Chang1, Kwang-Jin Koh, Young-Jae Lee2,
Hyun-Kyu Yu Figure 25.7.4 shows the proposed LNA circuit operating in a bal-
Electronics and Telecommunications Research Institute (ETRI), Daejeon, Republic of anced differential mode to satisfy the design architecture for
Korea IMT-2000 and Bluetooth. The inductively degenerated LNA is
1
KAIST, Daejeon, Republic of Korea the most suitable because of its superior noise performance,
2
Hynix Semiconductor, Cheongju, Republic of Korea which comes from the signal swing boost across Cgs resonating
with Lg [4]. But, the linearity is degraded as the signal swing
The primary goal of LNAs is to keep the overall noise figure of increases. Thus, the linearity improvement technique is more
the receiver low enough by suppressing the relatively large noise advantageous especially in inductive degeneration LNAs. All
of the mixer by the high gain of the LNAs. Another important components are integrated to reduce cost and complexity of on-
characteristic is linearity to prevent the incoming signal from wafer measurements, and all input inductors have a patterned
being corrupted with large intermodulating signals from adja- ground shield to screen substrate noise.
cent channels. Most linearization techniques focus on power
amplifiers and are not applicable for ICs in handsets. A few sim- The typical (without M5~M8 in Fig. 25.7.4) and the proposed LNAs
ple methods have been proposed to improve the linearity of are fabricated using a standard 0.25µm CMOS technology. Several
amplifiers [1~3]. However, they consume too much power and measurements are performed from 2.0GHz to 2.4GHz. Two balun
reduce gain. transformers are used for differential signals and the in/out sur-
rounding losses are considered deliberately. The losses including
Third order intermodulation mainly originates from the nonlin- cables are from 2.9dB at 2.0GHz to 3.3dB at 2.4GHz per port. The
earity of FET I-V characteristic which can be expressed around losses must be taken into account separately to extract the real
the quiescent bias point by a Taylor series expansion as id = in/out power of the LNAs and hence to obtain exact values of IIP3
g1vgs+g2vgs2+g3vgs3. Figure 25.7.1a shows a simple common-source and NF.
FET cascode (M1=M2=200µm/250nm), and its derivative dc I-V
characteristics are shown in Fig. 25.7.2. The cascode topology is Figure 25.7.5 shows on-wafer measured third-order intermodula-
widely used in LNAs to obtain better reverse isolation. For high- tion characteristics of both the LNAs at the two-tone frequencies
er linearity, a simple solution is to increase Vgs in saturation. of 2199MHz and 2200MHz, and the overall performance are sum-
However, Vgs is limited to the vicinity of 0.7V by considering marized in Fig. 25.7.6. With 17% bias current increase and 0.8dB
power consumption and gain increase. Around this voltage, the maximum gain reduction, the proposed (+16dBm) has 13dB high-
third-order coefficient G3 has a negative hump and its worst er IIP3 than the typical (+3dBm). The improved linearity degrades
value. Thus, it is hard to obtain a high linearity using this topol- and vanishes as input power increases over -20dBm per one tone.
ogy alone. To cancel the negative G3 hump, its positive hump This is caused by the limited operating range shown in Fig. 25.7.3
with similiar shape must be superposed. and presents no real problem because the normal input signal
does not exceed the value above. The measurements also show the
In this work, the G3 curve in the triode region is used for compen- IIP3 of the proposed circuit is insensitive to the bias current, espe-
sation. This idea originates from the observation of the waveforms cially with increased current. The proposed circuit keeps the IIP3
in Fig. 25.7.2 which have even-odd symmetries between the bound- at least +10dBm to half the bias current. In noise measurements,
ary of saturation and triode region. It is realized by inserting a tri- the losses were de-embedded by using the extended Friis equation
ode FET (M3) and a stacked FET (M4) connected in parallel with for differential circuits in [5]. Note also that the NF difference of
M1 as shown in Fig. 25.7.1b. Simulations show that the positive G3 the LNAs is under 0.1dB due to the minimal noise contribution of
hump in triode has nearly constant magnitude independent of its the proposed structure. The estimated in/out return losses are the
bias current. Despite this advantage, its magnitude is not sufficient same in both the LNAs about -10/-15dB at 2.2GHz, where the val-
(about half the G3 in saturation) and requires a double-sized triode ues are obtained from another single mode LNAs to compare the
FET which degrades the LNA performance. performance between single and differential mode. Finally, the
proposed differential LNA chip microphotograph is shown in Fig.
The key idea of this work is to drive M3 and M4 by two opposite 25.7.7.
polarity signals, which results in driving M3 gate and drain with
a positive and a negative signal, respectively. In a deep triode Acknowledgements
FET, the current depends on the drain voltage rather than the The authors wish to acknowledge the support and assistance of the Hynix
gate voltage, and there is a turning point where the current Semiconductor Inc., Dr. Chung-Hwan Kim of Teltron, and Jang-Hong Choi
starts to decrease as the gate voltage increases. Thus, the of ETRI.
G1(gm) of M3 is a negative value after that point. However, sim-
References
ulations also show that the combined signals boost the G3 of M3 [1] Yongwang Ding et al., “A +18dBm IIP3 LNA in 0.35µm CMOS,” IEEE
5~10 times due to the large variation rate of M3 current around ISSCC Digest of Technical Papers, pp. 162–163, 2001.
the point. This means that M3 is smaller by the amount of the [2] S. Tanaka et al., “A Linearization Technique for CMOS RF Power
G3 boosting. In spite of using a small M3 (50µm/250nm), the G3 Amplifiers,” IEEE VLSI Circuits Digest of Technical Papers, pp. 93–94,
of M3 is sufficient to cancel the G3 of M1. 1997.
[3] Min-Gun Kim et al., “An FET-Level Linearization Method using a
As the above nonlinearity cancellation is based on dc analysis, Predistortion Branch FET,” IEEE Microwave Guided Wave Letters, pp.
233–235, 1999.
the phase difference of the unequal two paths (Io+ and Io-) must
[4] Yong-Sik Youn et al., “A 2GHz RF Front-End Transceiver Chipset in
be considered to obtain good performance to a few GHz. The pro- CMOS Technology for PCS and IMT-2000 Applications,” IEEE RFIC
posed structure is verified by ac simulations as well as dc simu- Digest of Papers, pp. 271–274, 2002.
lations. Figure 25.7.3 shows about 20dB G3 cancellation at [5] A. A. Abidi et al., “De-Embedding the Noise Figure of Differential
2.5GHz. Moreover, it operates well at least to a 6GHz WLAN Amplifiers,” IEEE J. Solid-State Circuits, pp. 882–885, 1999.

• 2003 IEEE International Solid-State Circuits Conference 0-7803-7707-9/03/$17.00 ©2003 IEEE

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Figure 25.7.5: Measured IIP3 of typical and proposed LNA. Figure 25.7.6: Measured performance summary.

• 2003 IEEE International Solid-State Circuits Conference 0-7803-7707-9/03/$17.00 ©2003 IEEE

Figure 25.7.7: Chip micrograph. (Proposed LNA is only shown)

25

• 2003 IEEE International Solid-State Circuits Conference 0-7803-7707-9/03/$17.00 ©2003 IEEE

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• 2003 IEEE International Solid-State Circuits Conference 0-7803-7707-9/03/$17.00 ©2003 IEEE

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• 2003 IEEE International Solid-State Circuits Conference 0-7803-7707-9/03/$17.00 ©2003 IEEE

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• 2003 IEEE International Solid-State Circuits Conference 0-7803-7707-9/03/$17.00 ©2003 IEEE

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• 2003 IEEE International Solid-State Circuits Conference 0-7803-7707-9/03/$17.00 ©2003 IEEE

 




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• 2003 IEEE International Solid-State Circuits Conference 0-7803-7707-9/03/$17.00 ©2003 IEEE

 
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• 2003 IEEE International Solid-State Circuits Conference 0-7803-7707-9/03/$17.00 ©2003 IEEE

Figure 25.7.7: Chip micrograph. (Proposed LNA is only shown)

• 2003 IEEE International Solid-State Circuits Conference 0-7803-7707-9/03/$17.00 ©2003 IEEE