RX220 Group User's Manual - Hardware
RX220 Group User's Manual - Hardware
RX220 Group User's Manual - Hardware
User’s Manual
RX220 Group
32 User’s Manual: Hardware
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
(2012.4)
NOTES FOR CMOS DEVICES
(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a
reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise
from entering the device when the input level is fixed, and also in the transition period when the input level
passes through the area between VIL (MAX) and VIH (MIN).
(2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction.
If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc.,
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be
connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling
related to unused pins must be judged separately for each device and according to related specifications
governing the device.
(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause
destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it when it has occurred.
Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended
to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work benches and floors should be grounded. The operator should be grounded using a
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be
taken for PW boards with mounted semiconductor devices.
(4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS
device. Immediately after the power source is turned ON, devices with reset functions have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A
device is not initialized until the reset signal is received. A reset operation must be executed immediately
after power-on for devices with reset functions.
(5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal
operation and external interface, as a rule, switch on the external power supply after switching on the internal
power supply. When switching the power supply off, as a rule, switch off the external power supply and then
the internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements
due to the passage of an abnormal current. The correct power on/off sequence must be judged separately
for each device and according to related specifications governing the device.
(6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply
while the device is not powered. The current injection that results from input of such a signal or I/O pull-up
power supply may cause malfunction and the abnormal current that passes in the device at this time may
cause degradation of internal elements. Input of signals during the power off state must be judged
separately for each device and according to related specifications governing the device.
How to Use This Manual
1. Objective and Target Users
This manual was written to explain the hardware functions and electrical characteristics of this LSI to the target
users, i.e. those who will be using this LSI in the design of application systems. Target users are expected to
understand the fundamentals of electrical circuits, logic circuits, and microcomputers.
This manual is organized in the following items: an overview of the product, descriptions of the CPU, system
control functions, and peripheral functions, electrical characteristics of the device, and usage notes.
When designing an application system that includes this LSI, take all points to note into account.
Points to note are given in their contexts and at the final part of each section, and in the section giving usage notes.
The list of revisions is a summary of major points of revision or addition for earlier versions. It does not cover all
revised items. For details on the revised points, see the actual locations in the manual.
The following documents have been prepared for the RX220 Group. Before using any of the documents, please visit
our web site to verify that you have the most up-to-date available version of the document.
b7 b6 b5 b4 b3 b2 b1 b0
All trademarks and registered trademarks are the property of their respective owners.
Contents
Features ................................................................................................................................................... 35
1. Overview ........................................................................................................................................ 36
1.1 Outline of Specifications ...................................................................................................... 36
1.2 List of Products .................................................................................................................... 40
1.3 Block Diagram ..................................................................................................................... 42
1.4 Pin Functions ....................................................................................................................... 43
1.5 Pin Assignments .................................................................................................................. 46
2. CPU ............................................................................................................................................... 55
2.1 Features ............................................................................................................................... 55
2.2 Register Set of the CPU ...................................................................................................... 56
2.2.1 General-Purpose Registers (R0 to R15) ..................................................................................... 57
2.2.2 Control Registers ........................................................................................................................ 57
2.2.2.1 Interrupt Stack Pointer (ISP)/User Stack Pointer (USP) ................................................... 58
2.2.2.2 Interrupt Table Register (INTB) ........................................................................................ 58
2.2.2.3 Program Counter (PC) ....................................................................................................... 58
2.2.2.4 Processor Status Word (PSW) ........................................................................................... 59
2.2.2.5 Backup PC (BPC) .............................................................................................................. 60
2.2.2.6 Backup PSW (BPSW) ....................................................................................................... 61
2.2.2.7 Fast Interrupt Vector Register (FINTV) ............................................................................ 61
2.2.3 Register Associated with DSP Instructions ................................................................................ 61
2.2.3.1 Accumulator (ACC) .......................................................................................................... 61
2.3 Processor Mode ................................................................................................................... 62
2.3.1 Supervisor Mode ......................................................................................................................... 62
2.3.2 User Mode .................................................................................................................................. 62
2.3.3 Privileged Instruction ................................................................................................................. 62
2.3.4 Switching between Processor Modes ......................................................................................... 62
2.4 Data Types .......................................................................................................................... 63
2.5 Endian .................................................................................................................................. 63
2.5.1 Switching the Endian .................................................................................................................. 63
2.5.2 Access to I/O Registers ............................................................................................................... 66
2.5.3 Notes on Access to I/O Registers ............................................................................................... 67
2.5.4 Data Arrangement ....................................................................................................................... 68
2.5.4.1 Data Arrangement in Registers ......................................................................................... 68
2.5.4.2 Data Arrangement in Memory ........................................................................................... 68
2.5.5 Notes on the Allocation of Instruction Codes ............................................................................ 68
2.6 Vector Table ........................................................................................................................ 69
2.6.1 Fixed Vector Table ..................................................................................................................... 69
2.6.2 Relocatable Vector Table ........................................................................................................... 70
2.7 Operation of Instructions ...................................................................................................... 71
2.7.1 Data Prefetching by the RMPA Instruction and the String-Manipulation Instructions ............. 71
2.8 Pipeline ................................................................................................................................ 72
2.8.1 Overview .................................................................................................................................... 72
2.8.2 Instructions and Pipeline Processing .......................................................................................... 74
2.8.2.1 Instructions Converted into Single Micro-Operation and Pipeline Processing ................. 74
2.8.2.2 Instructions Converted into Multiple Micro-Operations and Pipeline Processing ............ 76
2.8.2.3 Pipeline Basic Operation ................................................................................................... 79
2.8.3 Calculation of the Instruction Processing Time ......................................................................... 81
2.8.4 Numbers of Cycles for Response to Interrupts ........................................................................... 82
Features
■ 32-bit RX CPU core
Max. operating frequency: 32 MHz
Capable of 49 DMIPS in operation at 32 MHz PLQP0100KB-A 14 × 14 mm, 0.5-mm pitch
Accumulator handles 64-bit results (for a single PLQP0064KB-A
PLQP0048KB-A
10 × 10 mm, 0.5-mm pitch
7 × 7 mm, 0.5-mm pitch
instruction) from 32- × 32-bit operations PLQP0064GA-A 14 × 14 mm, 0.8-mm pitch
Multiplication and division unit handles 32- × 32-bit
operations (multiplication instructions take one CPU
clock cycle) ■ Independent watchdog timer
Fast interrupt 125-kHz on-chip oscillator produces a dedicated clock
CISC Harvard architecture with 5-stage pipeline signal to drive IWDT operation.
Variable-length instructions, ultra-compact code ■ Useful functions for IEC60730 compliance
On-chip debugging circuit Self-diagnostic and disconnection-detection assistance
■ Low-power design and architecture functions for the A/D converter, clock-frequency
Operation from a single 1.62-V to 5.5-V supply accuracy-measurement circuit, independent watchdog
1.62-V operation available (at up to 8 MHz) timer, functions to assist in RAM testing, etc.
Three low-power modes ■ Up to seven communications channels
■ On-chip flash memory for code, no wait states SCI with many useful functions (up to five channels)
32-MHz operation, 31.25-ns read cycle Asynchronous mode, clock synchronous mode, smart
No wait states for reading at full CPU speed card interface mode
Up to 256-Kbyte capacity IrDA Interface (one channel, in cooperation with the
User code programmable via the SCI SCI5)
Programmable at 1.62 V I2C bus interface: Transfer at up to 400 kbps, capable of
For instructions and operands SMBus operation (one channel)
RSPI (one channel)
■ On-chip data flash memory
8 Kbytes (Number of times of reprogramming: 100,000) ■ Up to 14 extended-function timers
Erasing and programming impose no load on the CPU. 16-bit MTU: input capture, output capture,
complementary PWM output, phase counting mode
■ On-chip SRAM, no wait states
(six channels)
Up to 16-Kbyte size capacity
8-bit TMR (four channels)
■ DMA 16-bit compare-match timers (four channels)
DMAC: Incorporates four channels
■ 12-bit A/D converter
DTC: Four transfer modes
Capable of conversion within 1.56 μs
■ ELC Self-diagnostic function and analog input disconnection
Module operation can be initiated by event signals detection assistance function
without going through interrupts.
■ Analog comparator
Modules can operate while the CPU is sleeping.
■ General I/O ports
■ Reset and supply management
5-V tolerant, open drain, input pull-up, switching of
Seven types of reset, including the power-on reset (POR)
driving ability
Low voltage detection (LVD) with voltage settings
■ MPC
■ Clock functions
Multiple locations are selectable for I/O pins of
Frequency of external clock: Up to 20 MHz
peripheral functions
Frequency of the oscillator for sub-clock generation:
32.768 kHz ■ Operating temp. range
On-chip low- and high-speed oscillators, dedicated on- 40C to +85C
chip low-speed oscillator for the IWDT 40C to +105C
Generation of a dedicated 32.768-kHz clock for the RTC
Clock frequency accuracy measurement circuit (CAC)
■ Real-time clock
Adjustment functions (30 seconds, leap year, and error)
Year and month display or 32-bit second display (binary
counter) is selectable
1. Overview
1.1 Outline of Specifications
Table 1.1 lists the specifications in outline, and Table 1.2 gives a comparison of the functions of products in different
packages.
Table 1.1 is for products with the greatest number of functions, so numbers of peripheral modules and channels will
differ in accord with the package. For details, see Table 1.2, Comparison of Functions for Different Packages.
Note: • Please contact Renesas Electronics sales office for derating of operation under Ta = +85°C to +105°C. Derating is the
systematic reduction of load for the sake of improved reliability.
R 5 F 5 2 2 0 6 B D F P
Package type, number of pins, and pin pitch
FP: LQFP/100/0.50
FM: LQFP/64/0.50
FK: LQFP/64/0.80
FL: LQFP/48/0.50
Group name
20: RX220 Group
Series name
RX200 Series
Type of memory
F: Flash memory version
Renesas MCU
Figure 1.1 How to Read the Product Part No., Memory Capacity, and Package Type
E2 DataFlash
IWDTa
ELC
CRC
SCIe × 4 channels
(including one channel for IrDA)
SCIf × 1 channel
RSPI × 1 channel
RIIC × 1 channel
Internal peripheral buses 1 to 6
MTU2a × 6 channels
POE2a
Port 0
TMR × 2 channels (unit 0)
Port 1
TMR × 2 channels (unit 1)
Port 2
CMT × 2 channels (unit 0)
CMT × 2 channels (unit 1) Port 3
ICUb
ROM
RTCc Port 4
DOC Port A
Instruction bus
RAM DMACA × 4
channels Comparator A × 2 channels Port B
CAC Port C
Port D
RX CPU
Internal main bus 1
Port E
Port H
Clock
generation Port J
circuit
BSC
VCC
VSS
PC0
PC1
PE3
PE4
PE5
PE6
PE7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PE2 76 50 PC2
PE1 77 49 PC3
PE0 78 48 PC4
PD7 79 47 PC5
PD6 80 46 PC6
PD5 81 45 PC7
PD4 82 44 P50
PD3 83 43 P51
PD2 84 42 P52
PD1
PD0
85
86
RX220 Group 41
40
P53
P54
P47 87
88
PLQP0100KB-A 39 P55
P46 38 PH0
P45 89 (100-pin LQFP) 37 PH1
P44 90 36 PH2
P43 91 (Top view) 35 PH3
P42 92 34 P12
P41 93 33 P13
VREFL0 94 32 P14
P40 95 31 P15
VREFH0 96 30 P16
AVCC0 97 29 P17
P07 98 28 P20
AVSS0 99 27 P21
P05 100 26 P22
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
NC
NC
MD
XCIN
VCC
P03
PJ3
VCL
PJ1
RES#
VSS
P35
P34
P33
P32
P31
P30
P27
P26
P25
P37/XTAL
P36/EXTAL
P24
P23
XCOUT
Note: • This figure indicates the power supply pins and I/O port pins. For the pin configuration, see the
table “List of Pins and Pin Functions (100-Pin LQFP)”.
PB6/PC0
PB7/PC1
VCC
VSS
PA4
PE3
PE4
PE5
PA0
PA1
PA3
PA6
PB0
PB1
PB3
PB5
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PE2 49 32 PC2
PE1 50 31 PC3
PE0 51 30 PC4
NC 52 29 PC5
P46
NC
53
54
RX220 Group 28
27
PC6
PC7
P44 55 PLQP0064KB-A 26 P54
P43 56 25 P55
P42 57 PLQP0064GA-A 24 PH0
P41
VREFL0
58
59
(64-pin LQFP) 23
22
PH1
PH2
P40 60 (Top view) 21 PH3
VREFH0 61 20 P14
AVCC0 62 19 P15
P05 63 18 P16
AVSS0 64 17 P17
16
10
11
12
13
14
15
1
2
3
4
5
6
7
8
9
VSS
XCIN
MD
XCOUT
VCC
P37/XTAL
P03
VCL
RES#
P36/EXTAL
P35
P32
P31
P30
P27
P26
Note: • This figure indicates the power supply pins and I/O port pins. For the pin configuration,
see the table “List of Pins and Pin Functions (64-Pin LQFP)”.
PB1/PC1
PB3/PC2
PB5/PC3
VCC
VSS
PA4
PE3
PE4
PA1
PA3
PA6
36
35
34
33
32
31
30
29
28
27
26
25
PE2 37 24 PC4
PE1 38 23 PC5
NC 39 22 PC6
P46 40
41
RX220 Group 21 PC7
NC 20 PH0
P42 42 PLQP0048KB-A 19 PH1
P41 43
VREFL0 44
(48-pin LQFP) 18
17
PH2
PH3
P40 45
(Top view) 16 P14
VREFH0 46 15 P15
AVCC0 47 14 P16
AVSS0 48 13 P17
10
11
12
1
2
3
4
5
6
7
8
9
MD
VCC
VSS
VCL
P37/XTAL
P36/EXTAL
P35
P31
P30
P27
P26
RES#
Note: • This figure indicates the power supply pins and I/O port pins. For the pin
configuration, see the table “List of Pins and Pin Functions (48-Pin LQFP)”.
2. CPU
The RX220 Group is an MCU with the high-speed, high-performance RX CPU as its core.
A variable-length instruction format has been adopted for the RX CPU. Allocating the more frequently used instructions
to the shorter instruction lengths facilitates the development of efficient programs that take up less memory.
The CPU has 73 basic instructions and nine DSP instructions, for a total of 82 instructions. It has 10 addressing modes
and caters to register–register operations, register–memory operations, immediate–register operations, immediate–
memory operations, memory–memory transfer, and bitwise operations. High-speed operation was realized by achieving
execution in a single cycle not only for register–register operations, but also for other types of multiple instructions. The
CPU includes an internal multiplier and an internal divider for high-speed multiplication and division.
The RX CPU has a five-stage pipeline for processing instructions. The stages are instruction fetching, instruction
decoding, execution, memory access, and write-back. In cases where pipeline processing is drawn-out by memory
access, subsequent operations may in fact be executed earlier. By adopting “out-of-order completion” of this kind, the
execution of instructions is controlled to optimize numbers of clock cycles.
2.1 Features
High instruction execution rate: One instruction in one clock cycle
Address space: 4-Gbyte linear
Register set of the CPU
General purpose: Sixteen 32-bit registers
Control: Eight 32-bit registers
Accumulator: One 64-bit register
Basic instructions: 73 (arithmetic/logic instructions, data-transfer instructions, branch instructions, bit-manipulation
instructions, string-manipulation instructions, and system-manipulation instructions)
Relative branch instructions to suit branch distances
Variable-length instruction format (lengths from one to eight bytes)
Short formats for frequently used instructions
DSP instructions: 9
Supports 16-bit 16-bit multiplication and multiply-and-accumulate operations.
Rounds the data in the accumulator.
Addressing modes: 10
Five-stage pipeline
Adoption of “out-of-order completion”
Processor modes
A supervisor mode and a user mode are supported.
Data arrangement
Selectable as little endian or big endian
General-purpose register
b31 b0
*1
R0 (SP)
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
Control register
b31 b0
ISP (Interrupt stack pointer)
USP (User stack pointer)
PC (Program counter)
Note 1. The stack pointer (SP) can be the interrupt stack pointer (ISP) or user stack pointer (USP), according to
the value of the U bit in the PSW register.
b31 b0
ISP
b31 b0
USP
The stack pointer (SP) can be either of two types, the interrupt stack pointer (ISP) or the user stack pointer (USP).
Whether the stack pointer operates as the ISP or USP depends on the value of the stack pointer select bit (U) in the
processor status word (PSW).
Set the ISP or USP to a multiple of four, as this reduces the numbers of cycles required to execute interrupt sequences
and instructions entailing stack manipulation.
b31 b0
The interrupt table register (INTB) specifies the address where the relocatable vector table starts.
b31 b0
The program counter (PC) indicates the address of the instruction being executed.
b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16
— — — — IPL[3:0] — — — PM — — U I
— — — — — — — — — — — — O S Z C
Note 1. In user mode, writing to the IPL[3:0], PM, U, and I bits by an MVTC or a POPC instruction is ignored. Writing to the IPL[3:0] bits
by an MVTIPL instruction generates a privileged instruction exception.
Note 2. In supervisor mode, writing to the PM bit by an MVTC or a POPC instruction is ignored, but writing to the other bits is possible.
Note 3. Switching from supervisor mode to user mode requires execution of an RTE instruction after having set the PSW.PM bit saved on
the stack to 1 or executing an RTFI instruction after having set the BPSW.PM bit to 1.
The processor status word (PSW) indicates the results of instruction execution or the state of the CPU.
b31 b0
b31 b0
b31 b0
The fast interrupt vector register (FINTV) is provided to speed up response to interrupts.
The FINTV register specifies a branch destination address when a fast interrupt has been generated.
The accumulator (ACC) is a 64-bit register used for DSP instructions. The accumulator is also used for the multiply and
multiply-and-accumulate instructions; EMUL, EMULU, MUL, and RMPA, in which case the prior value in the
accumulator is modified by execution of the instruction.
Use the MVTACHI and MVTACLO instructions for writing to the accumulator. The MVTACHI and MVTACLO
instructions write data to the higher-order 32 bits (bits 63 to 32) and the lower-order 32 bits (bits 31 to 0), respectively.
Use the MVFACHI and MVFACMI instructions for reading data from the accumulator. The MVFACHI and MVFACMI
instructions read data from the higher-order 32 bits (bits 63 to 32) and the middle 32 bits (bits 47 to 16), respectively.
2.5 Endian
For the RX CPU, instructions are little endian, but the data arrangement is selectable as little or big endian.
Table 2.1 32-Bit Read Operations when Little Endian has been Selected
Operation
Reading a 32-bit unit Reading a 32-bit unit Reading a 32-bit unit Reading a 32-bit unit Reading a 32-bit unit
Address of src from address 0 from address 1 from address 2 from address 3 from address 4
Address 0 Transfer to LL — — — —
Address 1 Transfer to LH Transfer to LL — — —
Address 2 Transfer to HL Transfer to LH Transfer to LL — —
Address 3 Transfer to HH Transfer to HL Transfer to LH Transfer to LL —
Address 4 — Transfer to HH Transfer to HL Transfer to LH Transfer to LL
Address 5 — — Transfer to HH Transfer to HL Transfer to LH
Address 6 — — — Transfer to HH Transfer to HL
Address 7 — — — — Transfer to HH
Table 2.2 32-Bit Read Operations when Big Endian has been Selected
Operation
Reading a 32-bit unit Reading a 32-bit unit Reading a 32-bit unit Reading a 32-bit unit Reading a 32-bit unit
Address of src from address 0 from address 1 from address 2 from address 3 from address 4
Address 0 Transfer to HH — — — —
Address 1 Transfer to HL Transfer to HH — — —
Address 2 Transfer to LH Transfer to HL Transfer to HH — —
Address 3 Transfer to LL Transfer to LH Transfer to HL Transfer to HH —
Address 4 — Transfer to LL Transfer to LH Transfer to HL Transfer to HH
Address 5 — — Transfer to LL Transfer to LH Transfer to HL
Address 6 — — — Transfer to LL Transfer to LH
Address 7 — — — — Transfer to LL
Table 2.3 32-Bit Write Operations when Little Endian has been Selected
Operation
Address Writing a 32-bit unit Writing a 32-bit unit Writing a 32-bit unit Writing a 32-bit unit Writing a 32-bit unit
of dest to address 0 to address 1 to address 2 to address 3 to address 4
Address 0 Transfer from LL — — — —
Address 1 Transfer from LH Transfer from LL — — —
Address 2 Transfer from HL Transfer from LH Transfer from LL — —
Address 3 Transfer from HH Transfer from HL Transfer from LH Transfer from LL —
Address 4 — Transfer from HH Transfer from HL Transfer from LH Transfer from LL
Address 5 — — Transfer from HH Transfer from HL Transfer from LH
Address 6 — — — Transfer from HH Transfer from HL
Address 7 — — — — Transfer from HH
Table 2.4 32-Bit Write Operations when Big Endian has been Selected
Operation
Address Writing a 32-bit unit Writing a 32-bit unit Writing a 32-bit unit Writing a 32-bit unit Writing a 32-bit unit
of dest to address 0 to address 1 to address 2 to address 3 to address 4
Address 0 Transfer from HH — — — —
Address 1 Transfer from HL Transfer from HH — — —
Address 2 Transfer from LH Transfer from HL Transfer from HH — —
Address 3 Transfer from LL Transfer from LH Transfer from HL Transfer from HH —
Address 4 — Transfer from LL Transfer from LH Transfer from HL Transfer from HH
Address 5 — — Transfer from LL Transfer from LH Transfer from HL
Address 6 — — — Transfer from LL Transfer from LH
Address 7 — — — — Transfer from LL
Table 2.5 16-Bit Read Operations when Little Endian has been Selected
Operation
Reading Reading Reading Reading Reading Reading Reading
Address a 16-bit unit from a 16-bit unit from a 16-bit unit from a 16-bit unit from a 16-bit unit from a 16-bit unit from a 16-bit unit from
of src address 0 address 1 address 2 address 3 address 4 address 5 address 6
Address 0 Transfer to LL — — — — — —
Address 1 Transfer to LH Transfer to LL — — — — —
Address 2 — Transfer to LH Transfer to LL — — — —
Address 3 — — Transfer to LH Transfer to LL — — —
Address 4 — — — Transfer to LH Transfer to LL — —
Address 5 — — — — Transfer to LH Transfer to LL —
Address 6 — — — — — Transfer to LH Transfer to LL
Address 7 — — — — — — Transfer to LH
Table 2.6 16-Bit Read Operations when Big Endian has been Selected
Operation Reading Reading Reading Reading Reading Reading Reading
a 16-bit unit a 16-bit unit a 16-bit unit a 16-bit unit a 16-bit unit a 16-bit unit a 16-bit unit
Address from address from address from address from address from address from address from address
of src 0 1 2 3 4 5 6
Address 0 Transfer to LH — — — — — —
Address 1 Transfer to LL Transfer to LH — — — — —
Address 2 — Transfer to LL Transfer to LH — — — —
Address 3 — — Transfer to LL Transfer to LH — — —
Address 4 — — — Transfer to LL Transfer to LH — —
Address 5 — — — — Transfer to LL Transfer to LH —
Address 6 — — — — — Transfer to LL Transfer to LH
Address 7 — — — — — — Transfer to LL
Table 2.7 16-Bit Write Operations when Little Endian has been Selected
Operation
Writing Writing Writing Writing Writing Writing Writing
Address a 16-bit unit to a 16-bit unit to a 16-bit unit to a 16-bit unit to a 16-bit unit to a 16-bit unit to a 16-bit unit to
of dest address 0 address 1 address 2 address 3 address 4 address 5 address 6
Address 0 Transfer from LL — — — — — —
Address 1 Transfer from LH Transfer from LL — — — — —
Address 2 — Transfer from LH Transfer from LL — — — —
Address 3 — — Transfer from LH Transfer from LL — — —
Address 4 — — — Transfer from LH Transfer from LL — —
Address 5 — — — — Transfer from LH Transfer from LL —
Address 6 — — — — — Transfer from LH Transfer from LL
Address 7 — — — — — — Transfer from LH
Table 2.8 16-Bit Write Operations when Big Endian has been Selected
Operation
Writing Writing Writing Writing Writing Writing Writing
Address a 16-bit unit to a 16-bit unit to a 16-bit unit to a 16-bit unit to a 16-bit unit to a 16-bit unit to a 16-bit unit to
of dest address 0 address 1 address 2 address 3 address 4 address 5 address 6
Address 0 Transfer from LH — — — — — —
Address 1 Transfer from LL Transfer from LH — — — — —
Address 2 — Transfer from LL Transfer from LH — — — —
Address 3 — — Transfer from LL Transfer from LH — — —
Address 4 — — — Transfer from LL Transfer from LH — —
Address 5 — — — — Transfer from LL Transfer from LH —
Address 6 — — — — — Transfer from LL Transfer from LH
Address 7 — — — — — — Transfer from LL
Table 2.9 8-Bit Read Operations when Little Endian has been Selected
Operation Reading an 8-bit unit Reading an 8-bit unit Reading an 8-bit unit Reading an 8-bit unit
Address of src from address 0 from address 1 from address 2 from address 3
Address 0 Transfer to LL — — —
Address 1 — Transfer to LL — —
Address 2 — — Transfer to LL —
Address 3 — — — Transfer to LL
Table 2.10 8-Bit Read Operations when Big Endian has been Selected
Operation Reading an 8-bit unit Reading an 8-bit unit Reading an 8-bit unit Reading an 8-bit unit
Address of src from address 0 from address 1 from address 2 from address 3
Address 0 Transfer to LL — — —
Address 1 — Transfer to LL — —
Address 2 — — Transfer to LL —
Address 3 — — — Transfer to LL
Table 2.11 8-Bit Write Operations when Little Endian has been Selected
Operation Writing an 8-bit unit to Writing an 8-bit unit to Writing an 8-bit unit to Writing an 8-bit unit to
Address of dest address 0 address 1 address 2 address 3
Address 0 Transfer from LL — — —
Address 1 — Transfer from LL — —
Address 2 — — Transfer from LL —
Address 3 — — — Transfer from LL
Table 2.12 8-Bit Write Operations when Big Endian has been Selected
Operation Writing an 8-bit unit to Writing an 8-bit unit to Writing an 8-bit unit to Writing an 8-bit unit to
Address of dest address 0 address 1 address 2 address 3
Address 0 Transfer from LL — — —
Address 1 — Transfer from LL — —
Address 2 — — Transfer from LL —
Address 3 — — — Transfer from LL
b7 b0
Byte (8-bit) data
b15 b0
Word (16-bit) data
b31 b0
Longword (32-bit) data
MSB LSB
b7 b0 b7 b0
1-bit data Address L 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Address N+2
MSB LSB
FFFFFF80h (Reserved)
FFFFFFCCh (Reserved)
FFFFFFD4h (Reserved)
FFFFFFD8h (Reserved)
FFFFFFE0h (Reserved)
FFFFFFE4h (Reserved)
FFFFFFE8h (Reserved)
FFFFFFECh (Reserved)
FFFFFFF0h (Reserved)
FFFFFFF4h (Reserved)
FFFFFFFCh Reset
b31 b0
INTB IntBase
0
IntBase+4
1
IntBase+8
2
IntBase+1020
255
2.8 Pipeline
2.8.1 Overview
The RX CPU has 5-stage pipeline structure. The RX CPU instruction is converted into one or more micro-operations,
which are then executed in pipeline processing. In the pipeline stage, the IF stage is executed in the unit of instructions,
while the D and subsequent stages are executed in the unit of micro-operations.
The operation of pipeline and respective stages is described below.
One cycle
M stage
Pipeline stage IF stage D stage E stage M1 stage M2 stage WB stage
BYP
Execution processing IF DEC OP RW
OA1
RF OA2
Note 1. The number of cycles for the dividing instruction varies according to the divisor and dividend.
Note 2. For the number of cycles for throughput and latency, see section 2.8.3, Calculation of the Instruction Processing Time.
Figure 2.7 to Figure 2.9 show the operation of instructions that are converted into a basic single micro-operation.
4 stages
ADD R1, R2 IF D E WB
Note: • Multi-cycle instructions (DIV, DIVU) are executed in multiple cycles in the E stage.
DIV R3, R4 IF D E E WB
5 stages
MOV [R1], R2 IF D E M1 WB
Note: • When the load operation is executed to the no-wait memory, the M1 stage is executed in
one cycle. In other cases, the M stage (M1 or M2) is executed in multiple cycles.
MOV [R1], R2 IF D E M1 M1 M2 WB
4 stages
Note: • The M1 stage is executed until a write request is received during the store operation.
(If the store operation is executed to the no-wait memory, the M1 stage is executed in
one cycle.)
IF D E M1 M1 M1
Table 2.14 Instructions that are Converted into Multiple Micro-Operations (1/2)
Mnemonic (indicates the common operation when Reference
Instruction the size is omitted) Figure Number of Cycles
Arithmetic/logic instructions {ADC, ADD, AND, MAX, MIN, MUL, OR, SBB, SUB, Figure 2.10 3
(memory source operand) XOR} “[Rs], Rd”/“dsp[Rs], Rd”
{CMP, TST} “[Rs], Rs2”/“dsp[Rs], Rs2”
Arithmetic/logic instructions DIV “[Rs],Rd / dsp[Rs],Rd” — 5 to 22
(division) DIVU“[Rs],Rd / dsp[Rs],Rd” — 4 to 20
Arithmetic/logic instruction {EMUL, EMULU} “#IMM, Rd”/“Rs, Rd” Figure 2.12 2
(multiplier: 32 × 32 64 bits)
(register-register, register-
immediate)
Arithmetic/logic instruction {EMUL, EMULU} “[Rs], Rd”/“dsp[Rs], Rd” — 4
(multiplier: 32 × 32 64 bits)
(memory source operand)
Arithmetic/logic instructions RMPA.B — 6+7×floor(n/4)+4×(n%4)
(multiply-and-accumulate n: Number of processing
operation) bytes*1
RMPA.W — 6+5×floor(n/2)+4×(n%2)
n: Number of processing
words*1
RMPA.L — 6+4n
n: Number of processing
longwords*1
Arithmetic/logic instruction (64-bit SATR — 3
signed saturation processing for
the RMPA instruction)
Data transfer instructions MOV “[Rs], [Rd]”/“dsp[Rs], [Rd]”/“[Rs], dsp[Rd]”/ Figure 2.11 3
(memory-memory transfer) “dsp[Rs], dsp[Rd]”
PUSH “[Rs]”/“dsp[Rs]”
Bit manipulation instructions {BCLR, BNOT, BSET} “#IMM, [Rd]”/“#IMM, dsp[Rd]”/ Figure 2.11 3
(memory source operand) “Rs, [Rd]”/“Rs, dsp[Rd]”
BMCnd “#IMM, [Rd]”/“#IMM, dsp[Rd]”
BTST “#IMM, [Rs]”/“#IMM, dsp[Rs]”/“Rs, [Rs2]”/“Rs,
dsp[Rs2]
Transfer instruction POPC “CR” — Throughput: 3
(load operation) Latency: 4*2
Transfer instruction (save PUSHM “Rs-Rs2” — n
operation of multiple registers) n: Number of registers*3
Transfer instruction (restore POPM “Rs-Rs2” — Throughput: n
operation of multiple registers) Latency: n+1
n: Number of
registers*2,*4
Transfer instruction XCHG “Rs, Rd” Figure 2.13 2
(register-register)
Transfer instruction XCHG “[Rs], Rd”/“dsp[Rs], Rd” Figure 2.14 2
(memory-register)
Branch instructions RTS — 5
RTSD “#IMM” — 5
RTSD “#IMM, Rd-Rd2” — Throughput: n<5?5:1+n
Latency: n<4?5:2+n
n: Number of registers*2
Table 2.14 Instructions that are Converted into Multiple Micro-Operations (2/2)
Mnemonic (indicates the common operation when Reference
Instruction the size is omitted) Figure Number of Cycles
String manipulation instructions*5 SCMPU — 2+4×floor(n/4)+4×(n%4)
n: Number of comparison
bytes*1
SMOVB — n>3?
6+3×floor(n/4)+3×(n%4):
2+3n
n: Number of transfer
bytes*1
SMOVF, SMOVU — 2+3×floor(n/4)+3×(n%4)
n: Number of transfer
bytes*1
SSTR.B — 2+floor(n/4)+n%4
n: Number of transfer
bytes*1
SSTR.W — 2+floor(n/2)+n%2
n: Number of transfer
words*1
SSTR.L — 2+n
n: Number of transfer
longwords
SUNTIL.B, SWHILE.B — 3+3×floor(n/4)+3×(n%4)
n: Number of comparison
bytes*1
SUNTIL.W, SWHILE.W — 3+3×floor(n/2)+3×(n%2)
n: Number of comparison
words*1
SUNTIL.L, SWHILE.L — 3+3×n
n: Number of comparison
longwords
System manipulation instructions RTE — 6
RTFI — 3
?: Conditional operator
Figure 2.10 to Figure 2.14 show the operation of instructions that are converted into basic multiple micro-operations.
Note: • mop: Micro-operation, stall: Pipeline stall
Load data
Bit manipulation,
store operation
MOV [R1], [R2] IF D E M1 (mop1) load
D E M1 M1 (mop2) bit manipulation, store
Figure 2.11 MOV Instruction (Memory-Memory), Bit Manipulation Instruction (Memory Source Operand)
Figure 2.15 When an Instruction which Requires Multiple Cycles is Executed in the E Stage
Figure 2.16 When an Instruction which Requires more than One Cycle for its Operand Access is Executed
Branch
IF D E (mop) jump
instruction
Branch penalty
Two cycles
IF D E WB
Figure 2.17 When a Branch Instruction is Executed (an Unconditional Branch Instruction is Executed or
the Condition is Satisfied for a Conditional Branch Instruction)
Bypass process
ADD R2, R1 IF D stall E WB (mop) add
Figure 2.18 When the Subsequent Instruction Uses an Operand Read from the Memory
Bypass process
SUB R3, R2 IF D E WB (mop) sub
(b) When WB stages for the memory load and for the operation are overlapped
Even when the WB stages for the memory load and for the operation are overlapped, the operation processing is
pipelined in, because the load data and the operation result can be written to the register at the same timing.
Figure 2.20 When WB Stages for the Memory Load and for the Operation are Overlapped
(c) When subsequent instruction writes to the same register before the end of memory load
Even when the subsequent instruction writes to the same register before the end of memory load, the operation
processing is pipelined in, because the WB stage for the memory load is canceled.
IF D E WB
IF D E WB
Figure 2.21 When Subsequent Instruction Writes to the Same Register before the End of Memory Load
(d) When the load data is not used by the subsequent instruction
When the load data is not used by the subsequent instruction, the subsequent operations are in fact executed earlier and
the operation processing ends (out-of-order completion).
Figure 2.22 When Load Data is not Used by the Subsequent Instruction
Times calculated from the values in Table 2.15 will be applicable when access to memory from the CPU is processed
with no waiting. The RAM and ROM in products of the RX220 Groups allow such access. Numbers of cycles for
response to interrupts can be minimized by placing program code (and vectors) in ROM and the stack in RAM.
Furthermore, place the addresses where the exception handling routine start on eight-byte boundaries.
For information on the number of cycles from notification to acceptance of the interrupt request, indicated by N in the
table above, see Table 2.13, Instructions that are Converted into a Single Micro-Operation, and Table 2.14,
Instructions that are Converted into Multiple Micro-Operations.
The timing of interrupt acceptance depends on the state of the pipelines. For more information on this, see section
13.3.1, Acceptance Timing and Saved PC Value.
3. Operating Modes
3.1 Operating Mode Types and Selection
There are two types of operating-mode selection: one is be selected by the level on pins at the time of release from the
reset state, and the other is selected by software after release from the reset state.
Table 3.1 shows the relationship between levels on the mode-setting pins (MD, PC7) on release from the reset state and
the operating mode selected at that time. For details on each of the operating modes, see section 3.3, Details of
Operating Modes.
Note 1. Do not change the level on the MD pin while the MCU is operating.
Note 2. The PC7 pin can also be used as a general port pin.
Note 3. The on-chip ROM is classified into two types: ROM and E2 DataFlash.
The endian is selectable in single-chip mode and user boot mode. Endian is set in the given operating mode by using the
endian select bits (MDE[2:0]) in the register indicated in Table 3.2. For the correspondence between the setting and
endian, see Table 3.3.
— — — — — — — — — — — — — — — MD
Note 1. This affects the level on the MD pin at the time of release from the reset state.
— — — — — — — — — — UBTS — — — — —
— — — — — — — — — — — — — — — RAME
Note: • Set the PRCR.PRC1 bit to 1 (write enabled) before rewriting this register.
Reset
MD = High
RES# = High
RES# = Low
MD = Low
RES# = Low PC7 = High
RES# = High
Boot mode
Note 1. To start the chip in user boot mode, settings for UB code A and UB code B in the option-setting memory are
required along with the levels set on the mode-setting pins.
4. Address Space
4.1 Address Space
This LSI has a 4-Gbyte address space, consisting of the range of addresses from 0000 0000h to FFFF FFFFh. That is,
linear access to an address space of up to 4 Gbytes is possible, and this contains both program and data areas.
Figure 4.1 shows the memory map.
Single-chip mode*1
Reserved area*3
00FC 0000h
On-chip ROM (program ROM)
(write only) (256 KB)
0100 0000h
Reserved area*3
Note 1. The address space in boot mode and user boot mode is the same as the address space in single-chip mode.
Note 2. The capacity of ROM/RAM differs depending on the products.
ROM (bytes) RAM (bytes)
Capacity Address Capacity Address
256 K FFFC 0000h to FFFF FFFFh 16 K 0000 0000h to 0000 3FFFh
128 K FFFE 0000h to FFFF FFFFh 8K 0000 0000h to 0000 1FFFh
64K FFFF 0000h to FFFF FFFFh
32 K FFFF 8000h to FFFF FFFFh 4K 0000 0000h to 0000 0FFFh
Note:•See Table 1.3, List of Products, for the product type name.
5. I/O Registers
This section provides information on the on-chip I/O register addresses and bit configuration. The information is given as
shown below. Notes on writing to registers are also given below.
In the above cases, after writing to an I/O register, wait until the write operation is completed using the following
procedure and then execute the subsequent instruction.
[Instruction examples]
Byte-size I/O registers
MOV.L #SFR_ADDR, R1
MOV.B #SFR_DATA, [R1]
CMP [R1].UB, R1
;; Next process
MOV.L #SFR_ADDR, R1
MOV.W #SFR_DATA, [R1]
CMP [R1].W, R1
;; Next process
MOV.L #SFR_ADDR, R1
MOV.L #SFR_DATA, [R1]
CMP [R1].L, R1
;; Next process
If multiple registers are written to and a subsequent instruction should be executed after the write operations are entirely
completed, only read the I/O register that was last written to and execute the operation using the value; it is not necessary
to read or execute operation for all the registers that were written to.
Number of access cycles to I/O registers = Number of bus cycles for internal main bus 1 +
Number of divided clock synchronization cycles +
Number of bus cycles for internal peripheral bus 1 to 6
The number of bus cycles of internal peripheral bus 1 to 6 differs according to the register to be accessed.
When peripheral functions connected to internal peripheral bus 2 to 6 are accessed, the number of divided clock
synchronization cycles is added.
The number of divided clock synchronization cycles differs depending on the frequency ratio between ICLK and PCLK
(or FCLK) or bus access timing.
In the peripheral function unit, when the frequency ratio of ICLK is equal to or greater than that of PCLK (or FCLK), the
sum of the number of bus cycles for internal main bus 1 and the number of the divided clock synchronization cycles will
be one cycle of PCLK (or FCLK) at a maximum. Therefore, one PCLK (or FCLK) has been added to the number of
access cycles shown in Table 5.1.
When the frequency ratio of ICLK is lower than that of PCLK (or FCLK), the subsequent bus access is started from the
ICLK cycle following the completion of the access to the peripheral functions. Therefore, the access cycles are described
on an ICLK basis.
Note 1. This applies to the number of cycles when the access from the CPU does not conflict with the instruction bus
access from the different bus master (DMAC or DTC).
0008 000Ch SYSTEM Standby control register SBYCR 16 16 3 ICLK section 11.
0008 0010h SYSTEM Module stop control register A MSTPCRA 32 32 3 ICLK section 11.
0008 0014h SYSTEM Module stop control register B MSTPCRB 32 32 3 ICLK section 11.
0008 0018h SYSTEM Module stop control register C MSTPCRC 32 32 3 ICLK section 11.
0008 0020h SYSTEM System clock control register SCKCR 32 32 3 ICLK section 9.
0008 0026h SYSTEM System clock control register 3 SCKCR3 16 16 3 ICLK section 9.
0008 0032h SYSTEM Main clock oscillator control register MOSCCR 8 8 3 ICLK section 9.
0008 0033h SYSTEM Sub-clock oscillator control register SOSCCR 8 8 3 ICLK section 9.
0008 0035h SYSTEM IWDT-dedicated on-chip oscillator control register ILOCOCR 8 8 3 ICLK section 9.
0008 0036h SYSTEM High-speed on-chip oscillator control register HOCOCR 8 8 3 ICLK section 9.
0008 0037h SYSTEM High-speed on-chip oscillator control register 2 HOCOCR2 8 8 3 ICLK section 9.
0008 0040h SYSTEM Oscillation stop detection control register OSTDCR 8 8 3 ICLK section 9.
0008 0041h SYSTEM Oscillation stop detection status register OSTDSR 8 8 3 ICLK section 9.
0008 00A0h SYSTEM Operating power control register OPCCR 8 8 3 ICLK section 11.
0008 00A1h SYSTEM Sleep mode return clock source switching register RSTCKCR 8 8 3 ICLK section 11.
0008 00A2h SYSTEM Main clock oscillator wait control register MOSCWTCR 8 8 3 ICLK section 11.
0008 00A3h SYSTEM Sub-clock oscillator wait control register SOSCWTCR 8 8 3 ICLK section 11.
0008 00A9h SYSTEM HOCO wait control register 2 HOCOWTCR2 8 8 3 ICLK section 11.
0008 00E0h SYSTEM Voltage monitoring 1 circuit/comparator A1 control register 1 LVD1CR1 8 8 3 ICLK section 8.,
section 33.
0008 00E1h SYSTEM Voltage monitoring 1 circuit/comparator A1 status register LVD1SR 8 8 3 ICLK section 8.,
section 33.
0008 00E2h SYSTEM Voltage monitoring 2 circuit/comparator A2 control register 1 LVD2CR1 8 8 3 ICLK section 8.,
section 33.
0008 00E3h SYSTEM Voltage monitoring 2 circuit/comparator A2 status register LVD2SR 8 8 3 ICLK section 8.,
section 33.
0008 1300h BSC Bus error status clear register BERCLR 8 8 2 ICLK section 15.
0008 1304h BSC Bus error monitoring enable register BEREN 8 8 2 ICLK section 15.
0008 1308h BSC Bus error status register 1 BERSR1 8 8 2 ICLK section 15.
0008 130Ah BSC Bus error status register 2 BERSR2 16 16 2 ICLK section 15.
0008 1310h BSC Bus priority control register BUSPRI 16 16 2 ICLK section 15.
0008 2000h DMAC0 DMA source address register DMSAR 32 32 2 ICLK section 16.
0008 2004h DMAC0 DMA destination address register DMDAR 32 32 2 ICLK section 16.
0008 2008h DMAC0 DMA transfer count register DMCRA 32 32 2 ICLK section 16.
0008 200Ch DMAC0 DMA block transfer count register DMCRB 16 16 2 ICLK section 16.
0008 2010h DMAC0 DMA transfer mode register DMTMD 16 16 2 ICLK section 16.
0008 2013h DMAC0 DMA interrupt setting register DMINT 8 8 2 ICLK section 16.
0008 2014h DMAC0 DMA address mode register DMAMD 16 16 2 ICLK section 16.
0008 2018h DMAC0 DMA offset register DMOFR 32 32 2 ICLK section 16.
0008 201Ch DMAC0 DMA transfer enable register DMCNT 8 8 2 ICLK section 16.
0008 201Dh DMAC0 DMA software start register DMREQ 8 8 2 ICLK section 16.
0008 201Eh DMAC0 DMA status register DMSTS 8 8 2 ICLK section 16.
0008 201Fh DMAC0 DMA activation source flag control register DMCSL 8 8 2 ICLK section 16.
0008 2040h DMAC1 DMA source address register DMSAR 32 32 2 ICLK section 16.
0008 2044h DMAC1 DMA destination address register DMDAR 32 32 2 ICLK section 16.
0008 2048h DMAC1 DMA transfer count register DMCRA 32 32 2 ICLK section 16.
0008 204Ch DMAC1 DMA block transfer count register DMCRB 16 16 2 ICLK section 16.
0008 2050h DMAC1 DMA transfer mode register DMTMD 16 16 2 ICLK section 16.
0008 2053h DMAC1 DMA interrupt setting register DMINT 8 8 2 ICLK section 16.
0008 2054h DMAC1 DMA address mode register DMAMD 16 16 2 ICLK section 16.
0008 205Ch DMAC1 DMA transfer enable register DMCNT 8 8 2 ICLK section 16.
0008 205Dh DMAC1 DMA software start register DMREQ 8 8 2 ICLK section 16.
0008 205Eh DMAC1 DMA status register DMSTS 8 8 2 ICLK section 16.
0008 205Fh DMAC1 DMA activation source flag control register DMCSL 8 8 2 ICLK section 16.
0008 2080h DMAC2 DMA source address register DMSAR 32 32 2 ICLK section 16.
0008 2084h DMAC2 DMA destination address register DMDAR 32 32 2 ICLK section 16.
0008 2088h DMAC2 DMA transfer count register DMCRA 32 32 2 ICLK section 16.
0008 208Ch DMAC2 DMA block transfer count register DMCRB 16 16 2 ICLK section 16.
0008 2090h DMAC2 DMA transfer mode register DMTMD 16 16 2 ICLK section 16.
0008 2093h DMAC2 DMA interrupt setting register DMINT 8 8 2 ICLK section 16.
0008 2094h DMAC2 DMA address mode register DMAMD 16 16 2 ICLK section 16.
0008 209Ch DMAC2 DMA transfer enable register DMCNT 8 8 2 ICLK section 16.
0008 209Dh DMAC2 DMA software start register DMREQ 8 8 2 ICLK section 16.
0008 209Eh DMAC2 DMA status register DMSTS 8 8 2 ICLK section 16.
0008 209Fh DMAC2 DMA activation source flag control register DMCSL 8 8 2 ICLK section 16.
0008 20C0h DMAC3 DMA source address register DMSAR 32 32 2 ICLK section 16.
0008 20C4h DMAC3 DMA destination address register DMDAR 32 32 2 ICLK section 16.
0008 20C8h DMAC3 DMA transfer count register DMCRA 32 32 2 ICLK section 16.
0008 20CCh DMAC3 DMA block transfer count register DMCRB 16 16 2 ICLK section 16.
0008 20D0h DMAC3 DMA transfer mode register DMTMD 16 16 2 ICLK section 16.
0008 20D3h DMAC3 DMA interrupt setting register DMINT 8 8 2 ICLK section 16.
0008 20D4h DMAC3 DMA address mode register DMAMD 16 16 2 ICLK section 16.
0008 20DCh DMAC3 DMA transfer enable register DMCNT 8 8 2 ICLK section 16.
0008 20DDh DMAC3 DMA software start register DMREQ 8 8 2 ICLK section 16.
0008 20DEh DMAC3 DMA status register DMSTS 8 8 2 ICLK section 16.
0008 20DFh DMAC3 DMA activation source flag control register DMCSL 8 8 2 ICLK section 16.
0008 2200h DMAC DMA module activation register DMAST 8 8 2 ICLK section 16.
0008 2400h DTC DTC control register DTCCR 8 8 2 ICLK section 17.
0008 2404h DTC DTC vector base register DTCVBR 32 32 2 ICLK section 17.
0008 2408h DTC DTC address mode register DTCADMOD 8 8 2 ICLK section 17.
0008 240Ch DTC DTC module start register DTCST 8 8 2 ICLK section 17.
0008 240Eh DTC DTC status register DTCSTS 16 16 2 ICLK section 17.
0008 7010h ICU Interrupt request register 016 IR016 8 8 2 ICLK section 14.
0008 7015h ICU Interrupt request register 021 IR021 8 8 2 ICLK section 14.
0008 7017h ICU Interrupt request register 023 IR023 8 8 2 ICLK section 14.
0008 701Bh ICU Interrupt request register 027 IR027 8 8 2 ICLK section 14.
0008 701Ch ICU Interrupt request register 028 IR028 8 8 2 ICLK section 14.
0008 701Dh ICU Interrupt request register 029 IR029 8 8 2 ICLK section 14.
0008 701Eh ICU Interrupt request register 030 IR030 8 8 2 ICLK section 14.
0008 701Fh ICU Interrupt request register 031 IR031 8 8 2 ICLK section 14.
0008 7020h ICU Interrupt request register 032 IR032 8 8 2 ICLK section 14.
0008 7021h ICU Interrupt request register 033 IR033 8 8 2 ICLK section 14.
0008 7022h ICU Interrupt request register 034 IR034 8 8 2 ICLK section 14.
0008 702Ch ICU Interrupt request register 044 IR044 8 8 2 ICLK section 14.
0008 702Dh ICU Interrupt request register 045 IR045 8 8 2 ICLK section 14.
0008 702Eh ICU Interrupt request register 046 IR046 8 8 2 ICLK section 14.
0008 702Fh ICU Interrupt request register 047 IR047 8 8 2 ICLK section 14.
0008 7039h ICU Interrupt request register 057 IR057 8 8 2 ICLK section 14.
0008 703Fh ICU Interrupt request register 063 IR063 8 8 2 ICLK section 14.
0008 7040h ICU Interrupt request register 064 IR064 8 8 2 ICLK section 14.
0008 7041h ICU Interrupt request register 065 IR065 8 8 2 ICLK section 14.
0008 7042h ICU Interrupt request register 066 IR066 8 8 2 ICLK section 14.
0008 7043h ICU Interrupt request register 067 IR067 8 8 2 ICLK section 14.
0008 7044h ICU Interrupt request register 068 IR068 8 8 2 ICLK section 14.
0008 7045h ICU Interrupt request register 069 IR069 8 8 2 ICLK section 14.
0008 7046h ICU Interrupt request register 070 IR070 8 8 2 ICLK section 14.
0008 7047h ICU Interrupt request register 071 IR071 8 8 2 ICLK section 14.
0008 7058h ICU Interrupt request register 088 IR088 8 8 2 ICLK section 14.
0008 7059h ICU Interrupt request register 089 IR089 8 8 2 ICLK section 14.
0008 705Ch ICU Interrupt request register 092 IR092 8 8 2 ICLK section 14.
0008 705Dh ICU Interrupt request register 093 IR093 8 8 2 ICLK section 14.
0008 7066h ICU Interrupt request register 102 IR102 8 8 2 ICLK section 14.
0008 7067h ICU Interrupt request register 103 IR103 8 8 2 ICLK section 14.
0008 706Ah ICU Interrupt request register 106 IR106 8 8 2 ICLK section 14.
0008 7072h ICU Interrupt request register 114 IR114 8 8 2 ICLK section 14.
0008 7073h ICU Interrupt request register 115 IR115 8 8 2 ICLK section 14.
0008 7074h ICU Interrupt request register 116 IR116 8 8 2 ICLK section 14.
0008 7075h ICU Interrupt request register 117 IR117 8 8 2 ICLK section 14.
0008 7076h ICU Interrupt request register 118 IR118 8 8 2 ICLK section 14.
0008 7077h ICU Interrupt request register 119 IR119 8 8 2 ICLK section 14.
0008 7078h ICU Interrupt request register 120 IR120 8 8 2 ICLK section 14.
0008 7079h ICU Interrupt request register 121 IR121 8 8 2 ICLK section 14.
0008 707Ah ICU Interrupt request register 122 IR122 8 8 2 ICLK section 14.
0008 707Bh ICU Interrupt request register 123 IR123 8 8 2 ICLK section 14.
0008 707Ch ICU Interrupt request register 124 IR124 8 8 2 ICLK section 14.
0008 707Dh ICU Interrupt request register 125 IR125 8 8 2 ICLK section 14.
0008 707Eh ICU Interrupt request register 126 IR126 8 8 2 ICLK section 14.
0008 707Fh ICU Interrupt request register 127 IR127 8 8 2 ICLK section 14.
0008 7080h ICU Interrupt request register 128 IR128 8 8 2 ICLK section 14.
0008 7081h ICU Interrupt request register 129 IR129 8 8 2 ICLK section 14.
0008 7082h ICU Interrupt request register 130 IR130 8 8 2 ICLK section 14.
0008 7083h ICU Interrupt request register 131 IR131 8 8 2 ICLK section 14.
0008 7084h ICU Interrupt request register 132 IR132 8 8 2 ICLK section 14.
0008 7085h ICU Interrupt request register 133 IR133 8 8 2 ICLK section 14.
0008 7086h ICU Interrupt request register 134 IR134 8 8 2 ICLK section 14.
0008 7087h ICU Interrupt request register 135 IR135 8 8 2 ICLK section 14.
0008 7088h ICU Interrupt request register 136 IR136 8 8 2 ICLK section 14.
0008 7089h ICU Interrupt request register 137 IR137 8 8 2 ICLK section 14.
0008 708Ah ICU Interrupt request register 138 IR138 8 8 2 ICLK section 14.
0008 708Bh ICU Interrupt request register 139 IR139 8 8 2 ICLK section 14.
0008 708Ch ICU Interrupt request register 140 IR140 8 8 2 ICLK section 14.
0008 708Dh ICU Interrupt request register 141 IR141 8 8 2 ICLK section 14.
0008 70AAh ICU Interrupt request register 170 IR170 8 8 2 ICLK section 14.
0008 70ABh ICU Interrupt request register 171 IR171 8 8 2 ICLK section 14.
0008 70AEh ICU Interrupt request register 174 IR174 8 8 2 ICLK section 14.
0008 70AFh ICU Interrupt request register 175 IR175 8 8 2 ICLK section 14.
0008 70B0h ICU Interrupt request register 176 IR176 8 8 2 ICLK section 14.
0008 70B1h ICU Interrupt request register 177 IR177 8 8 2 ICLK section 14.
0008 70B2h ICU Interrupt request register 178 IR178 8 8 2 ICLK section 14.
0008 70B3h ICU Interrupt request register 179 IR179 8 8 2 ICLK section 14.
0008 70B4h ICU Interrupt request register 180 IR180 8 8 2 ICLK section 14.
0008 70B5h ICU Interrupt request register 181 IR181 8 8 2 ICLK section 14.
0008 70B6h ICU Interrupt request register 182 IR182 8 8 2 ICLK section 14.
0008 70B7h ICU Interrupt request register 183 IR183 8 8 2 ICLK section 14.
0008 70B8h ICU Interrupt request register 184 IR184 8 8 2 ICLK section 14.
0008 70B9h ICU Interrupt request register 185 IR185 8 8 2 ICLK section 14.
0008 70C6h ICU Interrupt request register 198 IR198 8 8 2 ICLK section 14.
0008 70C7h ICU Interrupt request register 199 IR199 8 8 2 ICLK section 14.
0008 70C8h ICU Interrupt request register 200 IR200 8 8 2 ICLK section 14.
0008 70C9h ICU Interrupt request register 201 IR201 8 8 2 ICLK section 14.
0008 70DAh ICU Interrupt request register 218 IR218 8 8 2 ICLK section 14.
0008 70DBh ICU Interrupt request register 219 IR219 8 8 2 ICLK section 14.
0008 70DCh ICU Interrupt request register 220 IR220 8 8 2 ICLK section 14.
0008 70DDh ICU Interrupt request register 221 IR221 8 8 2 ICLK section 14.
0008 70DEh ICU Interrupt request register 222 IR222 8 8 2 ICLK section 14.
0008 70DFh ICU Interrupt request register 223 IR223 8 8 2 ICLK section 14.
0008 70E0h ICU Interrupt request register 224 IR224 8 8 2 ICLK section 14.
0008 70E1h ICU Interrupt request register 225 IR225 8 8 2 ICLK section 14.
0008 70E2h ICU Interrupt request register 226 IR226 8 8 2 ICLK section 14.
0008 70E3h ICU Interrupt request register 227 IR227 8 8 2 ICLK section 14.
0008 70E4h ICU Interrupt request register 228 IR228 8 8 2 ICLK section 14.
0008 70E5h ICU Interrupt request register 229 IR229 8 8 2 ICLK section 14.
0008 70EAh ICU Interrupt request register 234 IR234 8 8 2 ICLK section 14.
0008 70EBh ICU Interrupt request register 235 IR235 8 8 2 ICLK section 14.
0008 70ECh ICU Interrupt request register 236 IR236 8 8 2 ICLK section 14.
0008 70EDh ICU Interrupt request register 237 IR237 8 8 2 ICLK section 14.
0008 70EEh ICU Interrupt request register 238 IR238 8 8 2 ICLK section 14.
0008 70EFh ICU Interrupt request register 239 IR239 8 8 2 ICLK section 14.
0008 70F0h ICU Interrupt request register 240 IR240 8 8 2 ICLK section 14.
0008 70F1h ICU Interrupt request register 241 IR241 8 8 2 ICLK section 14.
0008 70F2h ICU Interrupt request register 242 IR242 8 8 2 ICLK section 14.
0008 70F3h ICU Interrupt request register 243 IR243 8 8 2 ICLK section 14.
0008 70F4h ICU Interrupt request register 244 IR244 8 8 2 ICLK section 14.
0008 70F5h ICU Interrupt request register 245 IR245 8 8 2 ICLK section 14.
0008 70F6h ICU Interrupt request register 246 IR246 8 8 2 ICLK section 14.
0008 70F7h ICU Interrupt request register 247 IR247 8 8 2 ICLK section 14.
0008 70F8h ICU Interrupt request register 248 IR248 8 8 2 ICLK section 14.
0008 70F9h ICU Interrupt request register 249 IR249 8 8 2 ICLK section 14.
0008 711Bh ICU DTC activation enable register 027 DTCER027 8 8 2 ICLK section 14.
0008 711Ch ICU DTC activation enable register 028 DTCER028 8 8 2 ICLK section 14.
0008 711Dh ICU DTC activation enable register 029 DTCER029 8 8 2 ICLK section 14.
0008 711Eh ICU DTC activation enable register 030 DTCER030 8 8 2 ICLK section 14.
0008 711Fh ICU DTC activation enable register 031 DTCER031 8 8 2 ICLK section 14.
0008 712Dh ICU DTC activation enable register 045 DTCER045 8 8 2 ICLK section 14.
0008 712Eh ICU DTC activation enable register 046 DTCER046 8 8 2 ICLK section 14.
0008 7140h ICU DTC activation enable register 064 DTCER064 8 8 2 ICLK section 14.
0008 7141h ICU DTC activation enable register 065 DTCER065 8 8 2 ICLK section 14.
0008 7142h ICU DTC activation enable register 066 DTCER066 8 8 2 ICLK section 14.
0008 7143h ICU DTC activation enable register 067 DTCER067 8 8 2 ICLK section 14.
0008 7144h ICU DTC activation enable register 068 DTCER068 8 8 2 ICLK section 14.
0008 7145h ICU DTC activation enable register 069 DTCER069 8 8 2 ICLK section 14.
0008 7146h ICU DTC activation enable register 070 DTCER070 8 8 2 ICLK section 14.
0008 7147h ICU DTC activation enable register 071 DTCER071 8 8 2 ICLK section 14.
0008 7166h ICU DTC activation enable register 102 DTCER102 8 8 2 ICLK section 14.
0008 7167h ICU DTC activation enable register 103 DTCER103 8 8 2 ICLK section 14.
0008 716Ah ICU DTC activation enable register 106 DTCER106 8 8 2 ICLK section 14.
0008 7172h ICU DTC activation enable register 114 DTCER114 8 8 2 ICLK section 14.
0008 7173h ICU DTC activation enable register 115 DTCER115 8 8 2 ICLK section 14.
0008 7174h ICU DTC activation enable register 116 DTCER116 8 8 2 ICLK section 14.
0008 7175h ICU DTC activation enable register 117 DTCER117 8 8 2 ICLK section 14.
0008 7179h ICU DTC activation enable register 121 DTCER121 8 8 2 ICLK section 14.
0008 717Ah ICU DTC activation enable register 122 DTCER122 8 8 2 ICLK section 14.
0008 717Dh ICU DTC activation enable register 125 DTCER125 8 8 2 ICLK section 14.
0008 717Eh ICU DTC activation enable register 126 DTCER126 8 8 2 ICLK section 14.
0008 7181h ICU DTC activation enable register 129 DTCER129 8 8 2 ICLK section 14.
0008 7182h ICU DTC activation enable register 130 DTCER130 8 8 2 ICLK section 14.
0008 7183h ICU DTC activation enable register 131 DTCER131 8 8 2 ICLK section 14.
0008 7184h ICU DTC activation enable register 132 DTCER132 8 8 2 ICLK section 14.
0008 7186h ICU DTC activation enable register 134 DTCER134 8 8 2 ICLK section 14.
0008 7187h ICU DTC activation enable register 135 DTCER135 8 8 2 ICLK section 14.
0008 7188h ICU DTC activation enable register 136 DTCER136 8 8 2 ICLK section 14.
0008 7189h ICU DTC activation enable register 137 DTCER137 8 8 2 ICLK section 14.
0008 718Ah ICU DTC activation enable register 138 DTCER138 8 8 2 ICLK section 14.
0008 718Bh ICU DTC activation enable register 139 DTCER139 8 8 2 ICLK section 14.
0008 718Ch ICU DTC activation enable register 140 DTCER140 8 8 2 ICLK section 14.
0008 718Dh ICU DTC activation enable register 141 DTCER141 8 8 2 ICLK section 14.
0008 71AEh ICU DTC activation enable register 174 DTCER174 8 8 2 ICLK section 14.
0008 71AFh ICU DTC activation enable register 175 DTCER175 8 8 2 ICLK section 14.
0008 71B1h ICU DTC activation enable register 177 DTCER177 8 8 2 ICLK section 14.
0008 71B2h ICU DTC activation enable register 178 DTCER178 8 8 2 ICLK section 14.
0008 71B4h ICU DTC activation enable register 180 DTCER180 8 8 2 ICLK section 14.
0008 71B5h ICU DTC activation enable register 181 DTCER181 8 8 2 ICLK section 14.
0008 71B7h ICU DTC activation enable register 183 DTCER183 8 8 2 ICLK section 14.
0008 71B8h ICU DTC activation enable register 184 DTCER184 8 8 2 ICLK section 14.
0008 71C6h ICU DTC activation enable register 198 DTCER198 8 8 2 ICLK section 14.
0008 71C7h ICU DTC activation enable register 199 DTCER199 8 8 2 ICLK section 14.
0008 71C8h ICU DTC activation enable register 200 DTCER200 8 8 2 ICLK section 14.
0008 71C9h ICU DTC activation enable register 201 DTCER201 8 8 2 ICLK section 14.
0008 71DBh ICU DTC activation enable register 219 DTCER219 8 8 2 ICLK section 14.
0008 71DCh ICU DTC activation enable register 220 DTCER220 8 8 2 ICLK section 14.
0008 71DFh ICU DTC activation enable register 223 DTCER223 8 8 2 ICLK section 14.
0008 71E0h ICU DTC activation enable register 224 DTCER224 8 8 2 ICLK section 14.
0008 71E3h ICU DTC activation enable register 227 DTCER227 8 8 2 ICLK section 14.
0008 71E4h ICU DTC activation enable register 228 DTCER228 8 8 2 ICLK section 14.
0008 71EBh ICU DTC activation enable register 235 DTCER235 8 8 2 ICLK section 14.
0008 71ECh ICU DTC activation enable register 236 DTCER236 8 8 2 ICLK section 14.
0008 71EFh ICU DTC activation enable register 239 DTCER239 8 8 2 ICLK section 14.
0008 71F0h ICU DTC activation enable register 240 DTCER240 8 8 2 ICLK section 14.
0008 71F7h ICU DTC activation enable register 247 DTCER247 8 8 2 ICLK section 14.
0008 71F8h ICU DTC activation enable register 248 DTCER248 8 8 2 ICLK section 14.
0008 7202h ICU Interrupt request enable register 02 IER02 8 8 2 ICLK section 14.
0008 7203h ICU Interrupt request enable register 03 IER03 8 8 2 ICLK section 14.
0008 7204h ICU Interrupt request enable register 04 IER04 8 8 2 ICLK section 14.
0008 7205h ICU Interrupt request enable register 05 IER05 8 8 2 ICLK section 14.
0008 7207h ICU Interrupt request enable register 07 IER07 8 8 2 ICLK section 14.
0008 7208h ICU Interrupt request enable register 08 IER08 8 8 2 ICLK section 14.
0008 720Bh ICU Interrupt request enable register 0B IER0B 8 8 2 ICLK section 14.
0008 720Ch ICU Interrupt request enable register 0C IER0C 8 8 2 ICLK section 14.
0008 720Dh ICU Interrupt request enable register 0D IER0D 8 8 2 ICLK section 14.
0008 720Eh ICU Interrupt request enable register 0E IER0E 8 8 2 ICLK section 14.
0008 720Fh ICU Interrupt request enable register 0F IER0F 8 8 2 ICLK section 14.
0008 7210h ICU Interrupt request enable register 10 IER10 8 8 2 ICLK section 14.
0008 7211h ICU Interrupt request enable register 11 IER11 8 8 2 ICLK section 14.
0008 7215h ICU Interrupt request enable register 15 IER15 8 8 2 ICLK section 14.
0008 7216h ICU Interrupt request enable register 16 IER16 8 8 2 ICLK section 14.
0008 7217h ICU Interrupt request enable register 17 IER17 8 8 2 ICLK section 14.
0008 7218h ICU Interrupt request enable register 18 IER18 8 8 2 ICLK section 14.
0008 7219h ICU Interrupt request enable register 19 IER19 8 8 2 ICLK section 14.
0008 721Bh ICU Interrupt request enable register 1B IER1B 8 8 2 ICLK section 14.
0008 721Ch ICU Interrupt request enable register 1C IER1C 8 8 2 ICLK section 14.
0008 721Dh ICU Interrupt request enable register 1D IER1D 8 8 2 ICLK section 14.
0008 721Eh ICU Interrupt request enable register 1E IER1E 8 8 2 ICLK section 14.
0008 721Fh ICU Interrupt request enable register 1F IER1F 8 8 2 ICLK section 14.
0008 72E0h ICU Software interrupt activation register SWINTR 8 8 2 ICLK section 14.
0008 72F0h ICU Fast interrupt set register FIR 16 16 2 ICLK section 14.
0008 7300h ICU Interrupt source priority register 000 IPR000 8 8 2 ICLK section 14.
0008 7301h ICU Interrupt source priority register 001 IPR001 8 8 2 ICLK section 14.
0008 7302h ICU Interrupt source priority register 002 IPR002 8 8 2 ICLK section 14.
0008 7303h ICU Interrupt source priority register 003 IPR003 8 8 2 ICLK section 14.
0008 7304h ICU Interrupt source priority register 004 IPR004 8 8 2 ICLK section 14.
0008 7305h ICU Interrupt source priority register 005 IPR005 8 8 2 ICLK section 14.
0008 7306h ICU Interrupt source priority register 006 IPR006 8 8 2 ICLK section 14.
0008 7307h ICU Interrupt source priority register 007 IPR007 8 8 2 ICLK section 14.
0008 7320h ICU Interrupt source priority register 032 IPR032 8 8 2 ICLK section 14.
0008 7321h ICU Interrupt source priority register 033 IPR033 8 8 2 ICLK section 14.
0008 7322h ICU Interrupt source priority register 034 IPR034 8 8 2 ICLK section 14.
0008 732Ch ICU Interrupt source priority register 044 IPR044 8 8 2 ICLK section 14.
0008 7339h ICU Interrupt source priority register 057 IPR057 8 8 2 ICLK section 14.
0008 733Fh ICU Interrupt source priority register 063 IPR063 8 8 2 ICLK section 14.
0008 7340h ICU Interrupt source priority register 064 IPR064 8 8 2 ICLK section 14.
0008 7341h ICU Interrupt source priority register 065 IPR065 8 8 2 ICLK section 14.
0008 7342h ICU Interrupt source priority register 066 IPR066 8 8 2 ICLK section 14.
0008 7343h ICU Interrupt source priority register 067 IPR067 8 8 2 ICLK section 14.
0008 7344h ICU Interrupt source priority register 068 IPR068 8 8 2 ICLK section 14.
0008 7345h ICU Interrupt source priority register 069 IPR069 8 8 2 ICLK section 14.
0008 7346h ICU Interrupt source priority register 070 IPR070 8 8 2 ICLK section 14.
0008 7347h ICU Interrupt source priority register 071 IPR071 8 8 2 ICLK section 14.
0008 7358h ICU Interrupt source priority register 088 IPR088 8 8 2 ICLK section 14.
0008 7359h ICU Interrupt source priority register 089 IPR089 8 8 2 ICLK section 14.
0008 735Ch ICU Interrupt source priority register 092 IPR092 8 8 2 ICLK section 14.
0008 735Dh ICU Interrupt source priority register 093 IPR093 8 8 2 ICLK section 14.
0008 7366h ICU Interrupt source priority register 102 IPR102 8 8 2 ICLK section 14.
0008 7367h ICU Interrupt source priority register 103 IPR103 8 8 2 ICLK section 14.
0008 736Ah ICU Interrupt source priority register 106 IPR106 8 8 2 ICLK section 14.
0008 7372h ICU Interrupt source priority register 114 IPR114 8 8 2 ICLK section 14.
0008 7376h ICU Interrupt source priority register 118 IPR118 8 8 2 ICLK section 14.
0008 7379h ICU Interrupt source priority register 121 IPR121 8 8 2 ICLK section 14.
0008 737Bh ICU Interrupt source priority register 123 IPR123 8 8 2 ICLK section 14.
0008 737Dh ICU Interrupt source priority register 125 IPR125 8 8 2 ICLK section 14.
0008 737Fh ICU Interrupt source priority register 127 IPR127 8 8 2 ICLK section 14.
0008 7381h ICU Interrupt source priority register 129 IPR129 8 8 2 ICLK section 14.
0008 7385h ICU Interrupt source priority register 133 IPR133 8 8 2 ICLK section 14.
0008 7386h ICU Interrupt source priority register 134 IPR134 8 8 2 ICLK section 14.
0008 738Ah ICU Interrupt source priority register 138 IPR138 8 8 2 ICLK section 14.
0008 738Bh ICU Interrupt source priority register 139 IPR139 8 8 2 ICLK section 14.
0008 73AAh ICU Interrupt source priority register 170 IPR170 8 8 2 ICLK section 14.
0008 73ABh ICU Interrupt source priority register 171 IPR171 8 8 2 ICLK section 14.
0008 73AEh ICU Interrupt source priority register 174 IPR174 8 8 2 ICLK section 14.
0008 73B1h ICU Interrupt source priority register 177 IPR177 8 8 2 ICLK section 14.
0008 73B4h ICU Interrupt source priority register 180 IPR180 8 8 2 ICLK section 14.
0008 73B7h ICU Interrupt source priority register 183 IPR183 8 8 2 ICLK section 14.
0008 73C6h ICU Interrupt source priority register 198 IPR198 8 8 2 ICLK section 14.
0008 73C7h ICU Interrupt source priority register 199 IPR199 8 8 2 ICLK section 14.
0008 73C8h ICU Interrupt source priority register 200 IPR200 8 8 2 ICLK section 14.
0008 73C9h ICU Interrupt source priority register 201 IPR201 8 8 2 ICLK section 14.
0008 73DAh ICU Interrupt source priority register 218 IPR218 8 8 2 ICLK section 14.
0008 73DEh ICU Interrupt source priority register 222 IPR222 8 8 2 ICLK section 14.
0008 73E2h ICU Interrupt source priority register 226 IPR226 8 8 2 ICLK section 14.
0008 73EAh ICU Interrupt source priority register 234 IPR234 8 8 2 ICLK section 14.
0008 73EEh ICU Interrupt source priority register 238 IPR238 8 8 2 ICLK section 14.
0008 73F2h ICU Interrupt source priority register 242 IPR242 8 8 2 ICLK section 14.
0008 73F3h ICU Interrupt source priority register 243 IPR243 8 8 2 ICLK section 14.
0008 73F4h ICU Interrupt source priority register 244 IPR244 8 8 2 ICLK section 14.
0008 73F5h ICU Interrupt source priority register 245 IPR245 8 8 2 ICLK section 14.
0008 73F6h ICU Interrupt source priority register 246 IPR246 8 8 2 ICLK section 14.
0008 73F7h ICU Interrupt source priority register 247 IPR247 8 8 2 ICLK section 14.
0008 73F8h ICU Interrupt source priority register 248 IPR248 8 8 2 ICLK section 14.
0008 73F9h ICU Interrupt source priority register 249 IPR249 8 8 2 ICLK section 14.
0008 7400h ICU DMAC activation request select register 0 DMRSR0 8 8 2 ICLK section 14.
0008 7404h ICU DMAC activation request select register 1 DMRSR1 8 8 2 ICLK section 14.
0008 7408h ICU DMAC activation request select register 2 DMRSR2 8 8 2 ICLK section 14.
0008 740Ch ICU DMAC activation request select register 3 DMRSR3 8 8 2 ICLK section 14.
0008 7500h ICU IRQ control register 0 IRQCR0 8 8 2 ICLK section 14.
0008 7501h ICU IRQ control register 1 IRQCR1 8 8 2 ICLK section 14.
0008 7502h ICU IRQ control register 2 IRQCR2 8 8 2 ICLK section 14.
0008 7503h ICU IRQ control register 3 IRQCR3 8 8 2 ICLK section 14.
0008 7504h ICU IRQ control register 4 IRQCR4 8 8 2 ICLK section 14.
0008 7505h ICU IRQ control register 5 IRQCR5 8 8 2 ICLK section 14.
0008 7506h ICU IRQ control register 6 IRQCR6 8 8 2 ICLK section 14.
0008 7507h ICU IRQ control register 7 IRQCR7 8 8 2 ICLK section 14.
0008 7510h ICU IRQ pin digital filter enable register 0 IRQFLTE0 8 8 2 ICLK section 14.
0008 7514h ICU IRQ pin digital filter setting register 0 IRQFLTC0 16 16 2 ICLK section 14.
0008 7580h ICU Non-maskable interrupt status register NMISR 8 8 2 ICLK section 14.
0008 7581h ICU Non-maskable interrupt enable register NMIER 8 8 2 ICLK section 14.
0008 7582h ICU Non-maskable interrupt clear register NMICLR 8 8 2 ICLK section 14.
0008 7583h ICU NMI pin interrupt control register NMICR 8 8 2 ICLK section 14.
0008 7590h ICU NMI pin digital filter enable register NMIFLTE 8 8 2 ICLK section 14.
0008 7594h ICU NMI pin digital filter setting register NMIFLTC 8 8 2 ICLK section 14.
0008 8000h CMT Compare match timer start register 0 CMSTR0 16 16 2, 3 PCLKB 2 ICLK section 24.
0008 8002h CMT0 Compare match timer control register CMCR 16 16 2, 3 PCLKB 2 ICLK section 24.
0008 8004h CMT0 Compare match timer counter CMCNT 16 16 2, 3 PCLKB 2 ICLK section 24.
0008 8006h CMT0 Compare match timer constant register CMCOR 16 16 2, 3 PCLKB 2 ICLK section 24.
0008 8008h CMT1 Compare match timer control register CMCR 16 16 2, 3 PCLKB 2 ICLK section 24.
0008 800Ah CMT1 Compare match timer counter CMCNT 16 16 2, 3 PCLKB 2 ICLK section 24.
0008 800Ch CMT1 Compare match timer constant register CMCOR 16 16 2, 3 PCLKB 2 ICLK section 24.
0008 8010h CMT Compare match timer start register 1 CMSTR1 16 16 2, 3 PCLKB 2 ICLK section 24.
0008 8012h CMT2 Compare match timer control register CMCR 16 16 2, 3 PCLKB 2 ICLK section 24.
0008 8014h CMT2 Compare match timer counter CMCNT 16 16 2, 3 PCLKB 2 ICLK section 24.
0008 8016h CMT2 Compare match timer constant register CMCOR 16 16 2, 3 PCLKB 2 ICLK section 24.
0008 8018h CMT3 Compare match timer control register CMCR 16 16 2, 3 PCLKB 2 ICLK section 24.
0008 801Ah CMT3 Compare match timer counter CMCNT 16 16 2, 3 PCLKB 2 ICLK section 24.
0008 801Ch CMT3 Compare match timer constant register CMCOR 16 16 2, 3 PCLKB 2 ICLK section 24.
0008 8030h IWDT IWDT refresh register IWDTRR 8 8 2, 3 PCLKB 2 ICLK section 26.
0008 8032h IWDT IWDT control register IWDTCR 16 16 2, 3 PCLKB 2 ICLK section 26.
0008 8034h IWDT IWDT status register IWDTSR 16 16 2, 3 PCLKB 2 ICLK section 26.
0008 8036h IWDT IWDT reset control register IWDTRCR 8 8 2, 3 PCLKB 2 ICLK section 26.
0008 8038h IWDT IWDT count stop control register IWDTCSTPR 8 8 2, 3 PCLKB 2 ICLK section 26.
0008 8200h TMR0 Timer control register TCR 8 8 2, 3 PCLKB 2 ICLK section 23.
0008 8201h TMR1 Timer counter control register TCR 8 8 2, 3 PCLKB 2 ICLK section 23.
0008 8202h TMR0 Timer control/status register TCSR 8 8 2, 3 PCLKB 2 ICLK section 23.
0008 8203h TMR1 Timer control/status register TCSR 8 8 2, 3 PCLKB 2 ICLK section 23.
0008 8204h TMR0 Time constant register A TCORA 8 8 2, 3 PCLKB 2 ICLK section 23.
0008 8205h TMR1 Time constant register A TCORA 8 8*1 2, 3 PCLKB 2 ICLK section 23.
0008 8206h TMR0 Time constant register B TCORB 8 8 2, 3 PCLKB 2 ICLK section 23.
0008 8207h TMR1 Time constant register B TCORB 8 8*1 2, 3 PCLKB 2 ICLK section 23.
0008 8208h TMR0 Timer counter TCNT 8 8 2, 3 PCLKB 2 ICLK section 23.
0008 8209h TMR1 Timer counter TCNT 8 8*1 2, 3 PCLKB 2 ICLK section 23.
0008 820Ah TMR0 Timer counter control register TCCR 8 8 2, 3 PCLKB 2 ICLK section 23.
0008 820Bh TMR1 Timer counter control register TCCR 8 8*1 2, 3 PCLKB 2 ICLK section 23.
0008 820Ch TMR0 Time count start register TCSTR 8 8 2, 3 PCLKB 2 ICLK section 23.
0008 8210h TMR2 Timer control register TCR 8 8 2, 3 PCLKB 2 ICLK section 23.
0008 8211h TMR3 Timer control register TCR 8 8 2, 3 PCLKB 2 ICLK section 23.
0008 8212h TMR2 Timer control/status register TCSR 8 8 2, 3 PCLKB 2 ICLK section 23.
0008 8213h TMR3 Timer control/status register TCSR 8 8 2, 3 PCLKB 2 ICLK section 23.
0008 8214h TMR2 Time constant register A TCORA 8 8 2, 3 PCLKB 2 ICLK section 23.
0008 8215h TMR3 Time constant register A TCORA 8 8*1 2, 3 PCLKB 2 ICLK section 23.
0008 8216h TMR2 Time constant register B TCORB 8 8 2, 3 PCLKB 2 ICLK section 23.
0008 8217h TMR3 Time constant register B TCORB 8 8*1 2, 3 PCLKB 2 ICLK section 23.
0008 8218h TMR2 Timer counter TCNT 8 8 2, 3 PCLKB 2 ICLK section 23.
0008 8219h TMR3 Timer counter TCNT 8 8*1 2, 3 PCLKB 2 ICLK section 23.
0008 821Ah TMR2 Timer counter control register TCCR 8 8 2, 3 PCLKB 2 ICLK section 23.
0008 821Bh TMR3 Timer counter control register TCCR 8 8*1 2, 3 PCLKB 2 ICLK section 23.
0008 821Ch TMR2 Time count start register TCSTR 8 8 2, 3 PCLKB 2 ICLK section 23.
0008 8280h CRC CRC control register CRCCR 8 8 2, 3 PCLKB 2 ICLK section 31.
0008 8281h CRC CRC data input register CRCDIR 8 8 2, 3 PCLKB 2 ICLK section 31.
0008 8282h CRC CRC data output register CRCDOR 16 16 2, 3 PCLKB 2 ICLK section 31.
0008 8300h RIIC0 I2C bus control register 1 ICCR1 8 8 2, 3 PCLKB 2 ICLK section 29.
0008 8301h RIIC0 I2C bus control register 2 ICCR2 8 8 2, 3 PCLKB 2 ICLK section 29.
0008 8302h RIIC0 I2C bus mode register 1 ICMR1 8 8 2, 3 PCLKB 2 ICLK section 29.
0008 8303h RIIC0 I2C bus mode register 2 ICMR2 8 8 2, 3 PCLKB 2 ICLK section 29.
0008 8304h RIIC0 I2C bus mode register 3 ICMR3 8 8 2, 3 PCLKB 2 ICLK section 29.
0008 8305h RIIC0 I2 C bus function enable register ICFER 8 8 2, 3 PCLKB 2 ICLK section 29.
0008 8306h RIIC0 I2C bus status enable register ICSER 8 8 2, 3 PCLKB 2 ICLK section 29.
0008 8307h RIIC0 I2C bus interrupt enable register ICIER 8 8 2, 3 PCLKB 2 ICLK section 29.
0008 8308h RIIC0 I2C bus status register 1 ICSR1 8 8 2, 3 PCLKB 2 ICLK section 29.
0008 8309h RIIC0 I2C bus status register 2 ICSR2 8 8 2, 3 PCLKB 2 ICLK section 29.
0008 830Ah RIIC0 Slave address register L0 SARL0 8 8 2, 3 PCLKB 2 ICLK section 29.
0008 830Ah RIIC0 Timeout internal counter L TMOCNTL 8 8 2, 3 PCLKB 2 ICLK section 29.
0008 830Bh RIIC0 Slave address register U0 SARU0 8 8 2, 3 PCLKB 2 ICLK section 29.
0008 830Bh RIIC0 Timeout internal counter U TMOCNTU 8 8*2 2, 3 PCLKB 2 ICLK section 29.
0008 830Ch RIIC0 Slave address register L1 SARL1 8 8 2, 3 PCLKB 2 ICLK section 29.
0008 830Dh RIIC0 Slave address register U1 SARU1 8 8 2, 3 PCLKB 2 ICLK section 29.
0008 830Eh RIIC0 Slave address register L2 SARL2 8 8 2, 3 PCLKB 2 ICLK section 29.
0008 830Fh RIIC0 Slave address register U2 SARU2 8 8 2, 3 PCLKB 2 ICLK section 29.
0008 8310h RIIC0 I2 C bus bit rate low-level register ICBRL 8 8 2, 3 PCLKB 2 ICLK section 29.
0008 8311h RIIC0 I2C bus bit rate high-level register ICBRH 8 8 2, 3 PCLKB 2 ICLK section 29.
0008 8312h RIIC0 I2C bus transmit data register ICDRT 8 8 2, 3 PCLKB 2 ICLK section 29.
0008 8313h RIIC0 I2C bus receive data register ICDRR 8 8 2, 3 PCLKB 2 ICLK section 29.
0008 8380h RSPI0 RSPI control register SPCR 8 8 2, 3 PCLKB 2 ICLK section 30.
0008 8381h RSPI0 RSPI slave select polarity register SSLP 8 8 2, 3 PCLKB 2 ICLK section 30.
0008 8382h RSPI0 RSPI pin control register SPPCR 8 8 2, 3 PCLKB 2 ICLK section 30.
0008 8383h RSPI0 RSPI status register SPSR 8 8 2, 3 PCLKB 2 ICLK section 30.
0008 8384h RSPI0 RSPI data register SPDR 32 16, 32 2, 3 PCLKB 2 ICLK section 30.
0008 8388h RSPI0 RSPI sequence control register SPSCR 8 8 2, 3 PCLKB 2 ICLK section 30.
0008 8389h RSPI0 RSPI sequence status register SPSSR 8 8 2, 3 PCLKB 2 ICLK section 30.
0008 838Ah RSPI0 RSPI bit rate register SPBR 8 8 2, 3 PCLKB 2 ICLK section 30.
0008 838Bh RSPI0 RSPI data control register SPDCR 8 8 2, 3 PCLKB 2 ICLK section 30.
0008 838Ch RSPI0 RSPI clock delay register SPCKD 8 8 2, 3 PCLKB 2 ICLK section 30.
0008 838Dh RSPI0 RSPI slave select negation delay register SSLND 8 8 2, 3 PCLKB 2 ICLK section 30.
0008 838Eh RSPI0 RSPI next-access delay register SPND 8 8 2, 3 PCLKB 2 ICLK section 30.
0008 838Fh RSPI0 RSPI control register 2 SPCR2 8 8 2, 3 PCLKB 2 ICLK section 30.
0008 8390h RSPI0 RSPI command register 0 SPCMD0 16 16 2, 3 PCLKB 2 ICLK section 30.
0008 8392h RSPI0 RSPI command register 1 SPCMD1 16 16 2, 3 PCLKB 2 ICLK section 30.
0008 8394h RSPI0 RSPI command register 2 SPCMD2 16 16 2, 3 PCLKB 2 ICLK section 30.
0008 8396h RSPI0 RSPI command register 3 SPCMD3 16 16 2, 3 PCLKB 2 ICLK section 30.
0008 8398h RSPI0 RSPI command register 4 SPCMD4 16 16 2, 3 PCLKB 2 ICLK section 30.
0008 839Ah RSPI0 RSPI command register 5 SPCMD5 16 16 2, 3 PCLKB 2 ICLK section 30.
0008 839Ch RSPI0 RSPI command register 6 SPCMD6 16 16 2, 3 PCLKB 2 ICLK section 30.
0008 839Eh RSPI0 RSPI command register 7 SPCMD7 16 16 2, 3 PCLKB 2 ICLK section 30.
0008 8410h IRDA IrDA control register IRCR 8 8 2, 3 PCLKB 2 ICLK section 28.
0008 8600h MTU3 Timer control register TCR 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8601h MTU4 Timer control register TCR 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8602h MTU3 Timer mode register TMDR 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8603h MTU4 Timer mode register TMDR 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8604h MTU3 Timer I/O control register H TIORH 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8605h MTU3 Timer I/O control register L TIORL 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8606h MTU4 Timer I/O control register H TIORH 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8607h MTU4 Timer I/O control register L TIORL 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8608h MTU3 Timer interrupt enable register TIER 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8609h MTU4 Timer interrupt enable register TIER 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 860Ah MTU Timer output master enable register TOER 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 860Dh MTU Timer gate control register TGCR 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 860Eh MTU Timer output control register 1 TOCR1 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 860Fh MTU Timer output control register 2 TOCR2 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8610h MTU3 Timer counter TCNT 16 16 2, 3 PCLKB 2 ICLK section 21.
0008 8612h MTU4 Timer counter TCNT 16 16 2, 3 PCLKB 2 ICLK section 21.
0008 8614h MTU Timer cycle data register TCDR 16 16 2, 3 PCLKB 2 ICLK section 21.
0008 8616h MTU Timer dead time data register TDDR 16 16 2, 3 PCLKB 2 ICLK section 21.
0008 8618h MTU3 Timer general register A TGRA 16 16 2, 3 PCLKB 2 ICLK section 21.
0008 861Ah MTU3 Timer general register B TGRB 16 16 2, 3 PCLKB 2 ICLK section 21.
0008 861Ch MTU4 Timer general register A TGRA 16 16 2, 3 PCLKB 2 ICLK section 21.
0008 861Eh MTU4 Timer general register B TGRB 16 16 2, 3 PCLKB 2 ICLK section 21.
0008 8620h MTU Timer subcounter TCNTS 16 16 2, 3 PCLKB 2 ICLK section 21.
0008 8622h MTU Timer cycle buffer register TCBR 16 16 2, 3 PCLKB 2 ICLK section 21.
0008 8624h MTU3 Timer general register C TGRC 16 16 2, 3 PCLKB 2 ICLK section 21.
0008 8626h MTU3 Timer general register D TGRD 16 16 2, 3 PCLKB 2 ICLK section 21.
0008 8628h MTU4 Timer general register C TGRC 16 16 2, 3 PCLKB 2 ICLK section 21.
0008 862Ah MTU4 Timer general register D TGRD 16 16 2, 3 PCLKB 2 ICLK section 21.
0008 862Ch MTU3 Timer status register TSR 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 862Dh MTU4 Timer status register TSR 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8630h MTU Timer interrupt skipping set register TITCR 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8631h MTU Timer interrupt skipping counter TITCNT 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8632h MTU Timer buffer transfer set register TBTER 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8634h MTU Timer dead time enable register TDER 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8636h MTU Timer output level buffer register TOLBR 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8638h MTU3 Timer buffer operation transfer mode register TBTM 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8639h MTU4 Timer buffer operation transfer mode register TBTM 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8640h MTU4 Timer A/D converter start request control register TADCR 16 16 2, 3 PCLKB 2 ICLK section 21.
0008 8644h MTU4 Timer A/D converter start request cycle set register A TADCORA 16 16 2, 3 PCLKB 2 ICLK section 21.
0008 8646h MTU4 Timer A/D converter start request cycle set register B TADCORB 16 16 2, 3 PCLKB 2 ICLK section 21.
0008 8648h MTU4 Timer A/D converter start request cycle set buffer register A TADCOBRA 16 16 2, 3 PCLKB 2 ICLK section 21.
0008 864Ah MTU4 Timer A/D converter start request cycle set buffer register B TADCOBRB 16 16 2, 3 PCLKB 2 ICLK section 21.
0008 8660h MTU Timer waveform control register TWCR 8 8, 16 2, 3 PCLKB 2 ICLK section 21.
0008 8680h MTU Timer start register TSTR 8 8, 16 2, 3 PCLKB 2 ICLK section 21.
0008 8681h MTU Timer synchronous register TSYR 8 8, 16 2, 3 PCLKB 2 ICLK section 21.
0008 8684h MTU Timer read/write enable register TRWER 8 8, 16 2, 3 PCLKB 2 ICLK section 21.
0008 8690h MTU0 Noise filter control register NFCR 8 8, 16 2, 3 PCLKB 2 ICLK section 21.
0008 8691h MTU1 Noise filter control register NFCR 8 8, 16 2, 3 PCLKB 2 ICLK section 21.
0008 8692h MTU2 Noise filter control register NFCR 8 8, 16 2, 3 PCLKB 2 ICLK section 21.
0008 8693h MTU3 Noise filter control register NFCR 8 8, 16 2, 3 PCLKB 2 ICLK section 21.
0008 8694h MTU4 Noise filter control register NFCR 8 8, 16 2, 3 PCLKB 2 ICLK section 21.
0008 8695h MTU5 Noise filter control register NFCR 8 8, 16 2, 3 PCLKB 2 ICLK section 21.
0008 8700h MTU0 Timer control register TCR 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8701h MTU0 Timer mode register TMDR 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8702h MTU0 Timer I/O control register H TIORH 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8703h MTU0 Timer I/O control register L TIORL 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8704h MTU0 Timer interrupt enable register TIER 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8705h MTU0 Timer status register TSR 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8706h MTU0 Timer counter TCNT 16 16 2, 3 PCLKB 2 ICLK section 21.
0008 8708h MTU0 Timer general register A TGRA 16 16 2, 3 PCLKB 2 ICLK section 21.
0008 870Ah MTU0 Timer general register B TGRB 16 16 2, 3 PCLKB 2 ICLK section 21.
0008 870Ch MTU0 Timer general register C TGRC 16 16 2, 3 PCLKB 2 ICLK section 21.
0008 870Eh MTU0 Timer general register D TGRD 16 16 2, 3 PCLKB 2 ICLK section 21.
0008 8720h MTU0 Timer general register E TGRE 16 16 2, 3 PCLKB 2 ICLK section 21.
0008 8722h MTU0 Timer general register F TGRF 16 16 2, 3 PCLKB 2 ICLK section 21.
0008 8724h MTU0 Timer interrupt enable register 2 TIER2 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8726h MTU0 Timer buffer operation transfer mode register TBTM 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8780h MTU1 Timer control register TCR 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8781h MTU1 Timer mode register TMDR 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8782h MTU1 Timer I/O control register TIOR 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8784h MTU1 Timer interrupt enable register TIER 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8785h MTU1 Timer status register TSR 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8786h MTU1 Timer counter TCNT 16 16 2, 3 PCLKB 2 ICLK section 21.
0008 8788h MTU1 Timer general register A TGRA 16 16 2, 3 PCLKB 2 ICLK section 21.
0008 878Ah MTU1 Timer general register B TGRB 16 16 2, 3 PCLKB 2 ICLK section 21.
0008 8790h MTU1 Timer input capture control register TICCR 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8800h MTU2 Timer control register TCR 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8801h MTU2 Timer mode register TMDR 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8802h MTU2 Timer I/O control register TIOR 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8804h MTU2 Timer interrupt enable register TIER 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8805h MTU2 Timer status register TSR 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8806h MTU2 Timer counter TCNT 16 16 2, 3 PCLKB 2 ICLK section 21.
0008 8808h MTU2 Timer general register A TGRA 16 16 2, 3 PCLKB 2 ICLK section 21.
0008 880Ah MTU2 Timer general register B TGRB 16 16 2, 3 PCLKB 2 ICLK section 21.
0008 8880h MTU5 Timer counter U TCNTU 16 16 2, 3 PCLKB 2 ICLK section 21.
0008 8882h MTU5 Timer general register U TGRU 16 16 2, 3 PCLKB 2 ICLK section 21.
0008 8884h MTU5 Timer control register U TCRU 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8886h MTU5 Timer I/O control register U TIORU 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8890h MTU5 Timer counter V TCNTV 16 16 2, 3 PCLKB 2 ICLK section 21.
0008 8892h MTU5 Timer general register V TGRV 16 16 2, 3 PCLKB 2 ICLK section 21.
0008 8894h MTU5 Timer control register V TCRV 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8896h MTU5 Timer I/O control register V TIORV 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 88A0h MTU5 Timer counter W TCNTW 16 16 2, 3 PCLKB 2 ICLK section 21.
0008 88A2h MTU5 Timer general register W TGRW 16 16 2, 3 PCLKB 2 ICLK section 21.
0008 88A4h MTU5 Timer control register W TCRW 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 88A6h MTU5 Timer I/O control register W TIORW 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 88B2h MTU5 Timer interrupt enable register TIER 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 88B4h MTU5 Timer start register TSTR 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 88B6h MTU5 Timer compare match clear register TCNTCMPCLR 8 8 2, 3 PCLKB 2 ICLK section 21.
0008 8900h POE Input level control/status register 1 ICSR1 16 8, 16 2, 3 PCLKB 2 ICLK section 22.
0008 8902h POE Output level control/status register 1 OCSR1 16 8, 16 2, 3 PCLKB 2 ICLK section 22.
0008 8908h POE Input level control/status register 2 ICSR2 16 8, 16 2, 3 PCLKB 2 ICLK section 22.
0008 890Ah POE Software port output enable register SPOER 8 8 2, 3 PCLKB 2 ICLK section 22.
0008 890Bh POE Port output enable control register 1 POECR1 8 8 2, 3 PCLKB 2 ICLK section 22.
0008 890Ch POE Port output enable control register 2 POECR2 8 8 2, 3 PCLKB 2 ICLK section 22.
0008 890Eh POE Input level control/status register 3 ICSR3 16 8, 16 2, 3 PCLKB 2 ICLK section 22.
0008 9000h S12AD A/D control register ADCSR 16 16 2, 3 PCLKB 2 ICLK section 32.
0008 9004h S12AD A/D channel select register A ADANSA 16 16 2, 3 PCLKB 2 ICLK section 32.
0008 9008h S12AD A/D-converted value addition mode select register ADADS 16 16 2, 3 PCLKB 2 ICLK section 32.
0008 900Ch S12AD A/D-converted value addition count select register ADADC 8 8 2, 3 PCLKB 2 ICLK section 32.
0008 900Eh S12AD A/D control extended register ADCER 16 16 2, 3 PCLKB 2 ICLK section 32.
0008 9010h S12AD A/D start trigger select register ADSTRGR 16 16 2, 3 PCLKB 2 ICLK section 32.
0008 9012h S12AD A/D converted extended input control register ADEXICR 16 16 2, 3 PCLKB 2 ICLK section 32.
0008 9014h S12AD A/D channel select register B ADANSB 16 16 2, 3 PCLKB 2 ICLK section 32.
0008 9018h S12AD A/D double register ADDBLDR 16 16 2, 3 PCLKB 2 ICLK section 32.
0008 901Ch S12AD A/D internal reference voltage data register ADOCDR 16 16 2, 3 PCLKB 2 ICLK section 32.
0008 901Eh S12AD A/D self-diagnosis data register ADRD 16 16 2, 3 PCLKB 2 ICLK section 32.
0008 9020h S12AD A/D data register 0 ADDR0 16 16 2, 3 PCLKB 2 ICLK section 32.
0008 9022h S12AD A/D data register 1 ADDR1 16 16 2, 3 PCLKB 2 ICLK section 32.
0008 9024h S12AD A/D data register 2 ADDR2 16 16 2, 3 PCLKB 2 ICLK section 32.
0008 9026h S12AD A/D data register 3 ADDR3 16 16 2, 3 PCLKB 2 ICLK section 32.
0008 9028h S12AD A/D data register 4 ADDR4 16 16 2, 3 PCLKB 2 ICLK section 32.
0008 902Ah S12AD A/D data register 5 ADDR5 16 16 2, 3 PCLKB 2 ICLK section 32.
0008 902Ch S12AD A/D data register 6 ADDR6 16 16 2, 3 PCLKB 2 ICLK section 32.
0008 902Eh S12AD A/D data register 7 ADDR7 16 16 2, 3 PCLKB 2 ICLK section 32.
0008 9030h S12AD A/D data register 8 ADDR8 16 16 2, 3 PCLKB 2 ICLK section 32.
0008 9032h S12AD A/D data register 9 ADDR9 16 16 2, 3 PCLKB 2 ICLK section 32.
0008 9034h S12AD A/D data register 10 ADDR10 16 16 2, 3 PCLKB 2 ICLK section 32.
0008 9036h S12AD A/D data register 11 ADDR11 16 16 2, 3 PCLKB 2 ICLK section 32.
0008 9038h S12AD A/D data register 12 ADDR12 16 16 2, 3 PCLKB 2 ICLK section 32.
0008 903Ah S12AD A/D data register 13 ADDR13 16 16 2, 3 PCLKB 2 ICLK section 32.
0008 903Ch S12AD A/D data register 14 ADDR14 16 16 2, 3 PCLKB 2 ICLK section 32.
0008 903Eh S12AD A/D data register 15 ADDR15 16 16 2, 3 PCLKB 2 ICLK section 32.
0008 9060h S12AD A/D sampling state register 0 ADSSTR0 8 8 2, 3 PCLKB 2 ICLK section 32.
0008 9061h S12AD A/D sampling state register L ADSSTRL 8 8 2, 3 PCLKB 2 ICLK section 32.
0008 9071h S12AD A/D sampling state register O ADSSTRO 8 8 2, 3 PCLKB 2 ICLK section 32.
0008 9073h S12AD A/D sampling state register 1 ADSSTR1 8 8 2, 3 PCLKB 2 ICLK section 32.
0008 9074h S12AD A/D sampling state register 2 ADSSTR2 8 8 2, 3 PCLKB 2 ICLK section 32.
0008 9075h S12AD A/D sampling state register 3 ADSSTR3 8 8 2, 3 PCLKB 2 ICLK section 32.
0008 9076h S12AD A/D sampling state register 4 ADSSTR4 8 8 2, 3 PCLKB 2 ICLK section 32.
0008 9077h S12AD A/D sampling state register 5 ADSSTR5 8 8 2, 3 PCLKB 2 ICLK section 32.
0008 9078h S12AD A/D sampling state register 6 ADSSTR6 8 8 2, 3 PCLKB 2 ICLK section 32.
0008 9079h S12AD A/D sampling state register 7 ADSSTR7 8 8 2, 3 PCLKB 2 ICLK section 32.
0008 907Ah S12AD A/D disconnecting detection control register ADDISCR 8 8 2, 3 PCLKB 2 ICLK section 32.
0008 A020h SCI1 Serial mode register SMR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A021h SCI1 Bit rate register BRR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A022h SCI1 Serial control register SCR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A023h SCI1 Transmit data register TDR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A024h SCI1 Serial status register SSR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A025h SCI1 Receive data register RDR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A026h SCI1 Smart card mode register SCMR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A027h SCI1 Serial extended mode register SEMR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A028h SCI1 Noise filter setting register SNFR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A029h SCI1 I2C mode register 1 SIMR1 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A02Ah SCI1 I2 C mode register 2 SIMR2 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A02Bh SCI1 I2C mode register 3 SIMR3 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A02Ch SCI1 I2C status register SISR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A02Dh SCI1 SPI mode register SPMR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A0A0h SCI5 Serial mode register SMR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A0A1h SCI5 Bit rate register BRR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A0A2h SCI5 Serial control register SCR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A0A3h SCI5 Transmit data register TDR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A0A4h SCI5 Serial status register SSR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A0A5h SCI5 Receive data register RDR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A0A6h SCI5 Smart card mode register SCMR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A0A7h SCI5 Serial extended mode register SEMR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A0A8h SCI5 Noise filter setting register SNFR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A0A9h SCI5 I2C mode register 1 SIMR1 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A0AAh SCI5 I2C mode register 2 SIMR2 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A0ABh SCI5 I2C mode register 3 SIMR3 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A0ACh SCI5 I2C status register SISR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A0ADh SCI5 SPI mode register SPMR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A0C0h SCI6 Serial mode register SMR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A0C1h SCI6 Bit rate register BRR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A0C2h SCI6 Serial control register SCR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A0C3h SCI6 Transmit data register TDR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A0C4h SCI6 Serial status register SSR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A0C5h SCI6 Receive data register RDR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A0C6h SCI6 Smart card mode register SCMR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A0C7h SCI6 Serial extended mode register SEMR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A0C8h SCI6 Noise filter setting register SNFR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A0C9h SCI6 I2C mode register 1 SIMR1 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A0CAh SCI6 I2C mode register 2 SIMR2 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A0CBh SCI6 I2C mode register 3 SIMR3 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A0CCh SCI6 I2C status register SISR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A0CDh SCI6 SPI mode register SPMR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A120h SCI9 Serial mode register SMR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A121h SCI9 Bit rate register BRR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A122h SCI9 Serial control register SCR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A123h SCI9 Transmit data register TDR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A124h SCI9 Serial status register SSR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A125h SCI9 Receive data register RDR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A126h SCI9 Smart card mode register SCMR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A127h SCI9 Serial extended mode register SEMR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A128h SCI9 Noise filter setting register SNFR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A129h SCI9 I2C mode register 1 SIMR1 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A12Ah SCI9 I2C mode register 2 SIMR2 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A12Bh SCI9 I2C mode register 3 SIMR3 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A12Ch SCI9 I2 C status register SISR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 A12Dh SCI9 SPI mode register SPMR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 B000h CAC CAC control register 0 CACR0 8 8 2, 3 PCLKB 2 ICLK section 10.
0008 B001h CAC CAC control register 1 CACR1 8 8 2, 3 PCLKB 2 ICLK section 10.
0008 B002h CAC CAC control register 2 CACR2 8 8 2, 3 PCLKB 2 ICLK section 10.
0008 B003h CAC CAC interrupt control register CAICR 8 8 2, 3 PCLKB 2 ICLK section 10.
0008 B004h CAC CAC status register CASTR 8 8 2, 3 PCLKB 2 ICLK section 10.
0008 B006h CAC CAC upper-limit value setting register CAULVR 16 16 2, 3 PCLKB 2 ICLK section 10.
0008 B008h CAC CAC lower-limit value setting register CALLVR 16 16 2, 3 PCLKB 2 ICLK section 10.
0008 B00Ah CAC CAC counter buffer register CACNTBR 16 16 2, 3 PCLKB 2 ICLK section 10.
0008 B080h DOC DOC control register DOCR 8 8 2, 3 PCLKB 2 ICLK section 34.
0008 B082h DOC DOC data input register DODIR 16 16 2, 3 PCLKB 2 ICLK section 34.
0008 B084h DOC DOC data setting register DODSR 16 16 2, 3 PCLKB 2 ICLK section 34.
0008 B100h ELC Event link control register ELCR 8 8 2, 3 PCLKB 2 ICLK section 18.
0008 B102h ELC Event link setting register 1 ELSR1 8 8 2, 3 PCLKB 2 ICLK section 18.
0008 B103h ELC Event link setting register 2 ELSR2 8 8 2, 3 PCLKB 2 ICLK section 18.
0008 B104h ELC Event link setting register 3 ELSR3 8 8 2, 3 PCLKB 2 ICLK section 18.
0008 B105h ELC Event link setting register 4 ELSR4 8 8 2, 3 PCLKB 2 ICLK section 18.
0008 B10Bh ELC Event link setting register 10 ELSR10 8 8 2, 3 PCLKB 2 ICLK section 18.
0008 B10Dh ELC Event link setting register 12 ELSR12 8 8 2, 3 PCLKB 2 ICLK section 18.
0008 B110h ELC Event link setting register 15 ELSR15 8 8 2, 3 PCLKB 2 ICLK section 18.
0008 B113h ELC Event link setting register 18 ELSR18 8 8 2, 3 PCLKB 2 ICLK section 18.
0008 B115h ELC Event link setting register 20 ELSR20 8 8 2, 3 PCLKB 2 ICLK section 18.
0008 B117h ELC Event link setting register 22 ELSR22 8 8 2, 3 PCLKB 2 ICLK section 18.
0008 B119h ELC Event link setting register 24 ELSR24 8 8 2, 3 PCLKB 2 ICLK section 18.
0008 B11Ah ELC Event link setting register 25 ELSR25 8 8 2, 3 PCLKB 2 ICLK section 18.
0008 B11Fh ELC Event link option setting register A ELOPA 8 8 2, 3 PCLKB 2 ICLK section 18.
0008 B120h ELC Event link option setting register B ELOPB 8 8 2, 3 PCLKB 2 ICLK section 18.
0008 B122h ELC Event link option setting register D ELOPD 8 8 2, 3 PCLKB 2 ICLK section 18.
0008 B123h ELC Port group setting register 1 PGR1 8 8 2, 3 PCLKB 2 ICLK section 18.
0008 B125h ELC Port group control register 1 PGC1 8 8 2, 3 PCLKB 2 ICLK section 18.
0008 B127h ELC Port buffer register 1 PDBF1 8 8 2, 3 PCLKB 2 ICLK section 18.
0008 B129h ELC Event link port setting register 0 PEL0 8 8 2, 3 PCLKB 2 ICLK section 18.
0008 B12Ah ELC Event link port setting register 1 PEL1 8 8 2, 3 PCLKB 2 ICLK section 18.
0008 B12Dh ELC Event link software event generation register ELSEGR 8 8 2, 3 PCLKB 2 ICLK section 18.
0008 B300h SCI12 Serial mode register SMR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 B301h SCI12 Bit rate register BRR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 B302h SCI12 Serial control register SCR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 B303h SCI12 Transmit data register TDR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 B304h SCI12 Serial status register SSR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 B305h SCI12 Receive data register RDR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 B306h SCI12 Smart card mode register SCMR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 B307h SCI12 Serial extended mode register SEMR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 B308h SCI12 Noise filter setting register SNFR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 B309h SCI12 I2C mode register 1 SIMR1 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 B30Ah SCI12 I2 C mode register 2 SIMR2 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 B30Bh SCI12 I2C mode register 3 SIMR3 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 B30Ch SCI12 I2C status register SISR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 B30Dh SCI12 SPI mode register SPMR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 B320h SCI12 Extended serial mode enable register ESMER 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 B321h SCI12 Control register 0 CR0 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 B322h SCI12 Control register 1 CR1 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 B323h SCI12 Control register 2 CR2 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 B324h SCI12 Control register 3 CR3 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 B325h SCI12 Port control register PCR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 B326h SCI12 Interrupt control register ICR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 B327h SCI12 Status register STR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 B328h SCI12 Status clear register STCR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 B329h SCI12 Control Field 0 data register CF0DR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 B32Ah SCI12 Control Field 0 compare enable register CF0CR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 B32Bh SCI12 Control Field 0 receive data register CF0RR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 B32Ch SCI12 Primary control field 1 data register PCF1DR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 B32Dh SCI12 Secondary control field 1 data register SCF1DR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 B32Eh SCI12 Control field 1 compare enable register CF1CR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 B32Fh SCI12 Control field 1 receive data register CF1RR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 B330h SCI12 Timer control register TCR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 B331h SCI12 Timer mode register TMR 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 B332h SCI12 Timer prescaler register TPRE 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 B333h SCI12 Timer count register TCNT 8 8 2, 3 PCLKB 2 ICLK section 27.
0008 C000h PORT0 Port direction register PDR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C001h PORT1 Port direction register PDR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C002h PORT2 Port direction register PDR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C003h PORT3 Port direction register PDR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C004h PORT4 Port direction register PDR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C005h PORT5 Port direction register PDR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C00Ah PORTA Port direction register PDR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C00Bh PORTB Port direction register PDR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C00Ch PORTC Port direction register PDR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C00Dh PORTD Port direction register PDR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C00Eh PORTE Port direction register PDR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C011h PORTH Port direction register PDR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C012h PORTJ Port direction register PDR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C020h PORT0 Port output data register PODR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C021h PORT1 Port output data register PODR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C022h PORT2 Port output data register PODR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C023h PORT3 Port output data register PODR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C024h PORT4 Port output data register PODR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C025h PORT5 Port output data register PODR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C02Ah PORTA Port output data register PODR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C02Bh PORTB Port output data register PODR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C02Ch PORTC Port output data register PODR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C02Dh PORTD Port output data register PODR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C02Eh PORTE Port output data register PODR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C031h PORTH Port output data register PODR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C032h PORTJ Port output data register PODR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C040h PORT0 Port input data register PIDR 8 8 3 or 4 3 ICLK section 19.
PCLKB cycles when
cycles when reading,
reading, 2 ICLK
2 or 3 cycles when
PCLKB writing
cycles when
writing
0008 C041h PORT1 Port input data register PIDR 8 8 3 or 4 3 ICLK section 19.
PCLKB cycles when
cycles when reading,
reading, 2 ICLK
2 or 3 cycles when
PCLKB writing
cycles when
writing
0008 C042h PORT2 Port input data register PIDR 8 8 3 or 4 3 ICLK section 19.
PCLKB cycles when
cycles when reading,
reading, 2 ICLK
2 or 3 cycles when
PCLKB writing
cycles when
writing
0008 C043h PORT3 Port input data register PIDR 8 8 3 or 4 3 ICLK section 19.
PCLKB cycles when
cycles when reading,
reading, 2 ICLK
2 or 3 cycles when
PCLKB writing
cycles when
writing
0008 C044h PORT4 Port input data register PIDR 8 8 3 or 4 3 ICLK section 19.
PCLKB cycles when
cycles when reading,
reading, 2 ICLK
2 or 3 cycles when
PCLKB writing
cycles when
writing
0008 C045h PORT5 Port input data register PIDR 8 8 3 or 4 3 ICLK section 19.
PCLKB cycles when
cycles when reading,
reading, 2 ICLK
2 or 3 cycles when
PCLKB writing
cycles when
writing
0008 C04Ah PORTA Port input data register PIDR 8 8 3 or 4 3 ICLK section 19.
PCLKB cycles when
cycles when reading,
reading, 2 ICLK
2 or 3 cycles when
PCLKB writing
cycles when
writing
0008 C04Bh PORTB Port input data register PIDR 8 8 3 or 4 3 ICLK section 19.
PCLKB cycles when
cycles when reading,
reading, 2 ICLK
2 or 3 cycles when
PCLKB writing
cycles when
writing
0008 C04Ch PORTC Port input data register PIDR 8 8 3 or 4 3 ICLK section 19.
PCLKB cycles when
cycles when reading,
reading, 2 ICLK
2 or 3 cycles when
PCLKB writing
cycles when
writing
0008 C04Dh PORTD Port input data register PIDR 8 8 3 or 4 3 ICLK section 19.
PCLKB cycles when
cycles when reading,
reading, 2 ICLK
2 or 3 cycles when
PCLKB writing
cycles when
writing
0008 C04Eh PORTE Port input data register PIDR 8 8 3 or 4 3 ICLK section 19.
PCLKB cycles when
cycles when reading,
reading, 2 ICLK
2 or 3 cycles when
PCLKB writing
cycles when
writing
0008 C051h PORTH Port input data register PIDR 8 8 3 or 4 3 ICLK section 19.
PCLKB cycles when
cycles when reading,
reading, 2 ICLK
2 or 3 cycles when
PCLKB writing
cycles when
writing
0008 C052h PORTJ Port input data register PIDR 8 8 3 or 4 3 ICLK section 19.
PCLKB cycles when
cycles when reading,
reading, 2 ICLK
2 or 3 cycles when
PCLKB writing
cycles when
writing
0008 C060h PORT0 Port mode register PMR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C061h PORT1 Port mode register PMR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C062h PORT2 Port mode register PMR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C063h PORT3 Port mode register PMR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C064h PORT4 Port mode register PMR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C065h PORT5 Port mode register PMR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C06Ah PORTA Port mode register PMR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C06Bh PORTB Port mode register PMR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C06Ch PORTC Port mode register PMR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C06Dh PORTD Port mode register PMR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C06Eh PORTE Port mode register PMR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C071h PORTH Port mode register PMR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C072h PORTJ Port mode register PMR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C082h PORT1 Open drain control register 0 ODR0 8 8, 16 2, 3 PCLKB 2 ICLK section 19.
0008 C083h PORT1 Open drain control register 1 ODR1 8 8, 16 2, 3 PCLKB 2 ICLK section 19.
0008 C085h PORT2 Open drain control register 1 ODR1 8 8, 16 2, 3 PCLKB 2 ICLK section 19.
0008 C086h PORT3 Open drain control register 0 ODR0 8 8, 16 2, 3 PCLKB 2 ICLK section 19.
0008 C087h PORT3 Open drain control register 1 ODR1 8 8, 16 2, 3 PCLKB 2 ICLK section 19.
0008 C094h PORTA Open drain control register 0 ODR0 8 8, 16 2, 3 PCLKB 2 ICLK section 19.
0008 C095h PORTA Open drain control register 1 ODR1 8 8, 16 2, 3 PCLKB 2 ICLK section 19.
0008 C096h PORTB Open drain control register 0 ODR0 8 8, 16 2, 3 PCLKB 2 ICLK section 19.
0008 C097h PORTB Open drain control register 1 ODR1 8 8, 16 2, 3 PCLKB 2 ICLK section 19.
0008 C098h PORTC Open drain control register 0 ODR0 8 8, 16 2, 3 PCLKB 2 ICLK section 19.
0008 C099h PORTC Open drain control register 1 ODR1 8 8, 16 2, 3 PCLKB 2 ICLK section 19.
0008 C09Ch PORTE Open drain control register 0 ODR0 8 8, 16 2, 3 PCLKB 2 ICLK section 19.
0008 C0C0h PORT0 Pull-up control register PCR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C0C1h PORT1 Pull-up control register PCR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C0C2h PORT2 Pull-up control register PCR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C0C3h PORT3 Pull-up control register PCR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C0C4h PORT4 Pull-up control register PCR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C0C5h PORT5 Pull-up control register PCR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C0CAh PORTA Pull-up control register PCR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C0CBh PORTB Pull-up control register PCR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C0CCh PORTC Pull-up control register PCR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C0CDh PORTD Pull-up control register PCR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C0CEh PORTE Pull-up control register PCR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C0D1h PORTH Pull-up control register PCR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C0D2h PORTJ Pull-up control register PCR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C0E1h PORT1 Drive capacity control register DSCR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C0EBh PORTB Drive capacity control register DSCR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C0ECh PORTC Drive capacity control register DSCR 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C11Fh MPC Write-protect register PWPR 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C120h PORT Port switching register B PSRB 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C121h PORT Port switching register A PSRA 8 8 2, 3 PCLKB 2 ICLK section 19.
0008 C147h MPC P07 pin function control register P07PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C14Ah MPC P12 pin function control register P12PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C14Bh MPC P13 pin function control register P13PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C14Ch MPC P14 pin function control register P14PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C14Dh MPC P15 pin function control register P15PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C14Eh MPC P16 pin function control register P16PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C14Fh MPC P17 pin function control register P17PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C150h MPC P20 pin function control register P20PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C151h MPC P21 pin function control register P21PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C152h MPC P22 pin function control register P22PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C153h MPC P23 pin function control register P23PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C154h MPC P24 pin function control register P24PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C155h MPC P25 pin function control register P25PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C156h MPC P26 pin function control register P26PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C157h MPC P27 pin function control register P27PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C158h MPC P30 pin function control register P30PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C159h MPC P31 pin function control register P31PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C15Ah MPC P32 pin function control register P32PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C15Bh MPC P33 pin function control register P33PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C15Ch MPC P34 pin function control register P34PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C160h MPC P40 pin function control register P40PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C161h MPC P41 pin function control register P41PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C162h MPC P42 pin function control register P42PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C163h MPC P43 pin function control register P43PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C164h MPC P44 pin function control register P44PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C165h MPC P45 pin function control register P45PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C166h MPC P46 pin function control register P46PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C167h MPC P47 pin function control register P47PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C16Ch MPC P54 pin function control register P54PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C16Dh MPC P55 pin function control register P55PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C190h MPC PA0 pin function control register PA0PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C191h MPC PA1 pin function control register PA1PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C192h MPC PA2 pin function control register PA2PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C193h MPC PA3 pin function control register PA3PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C194h MPC PA4 pin function control register PA4PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C195h MPC PA5 pin function control register PA5PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C196h MPC PA6 pin function control register PA6PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C197h MPC PA7 pin function control register PA7PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C198h MPC PB0 pin function control register PB0PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C199h MPC PB1 pin function control register PB1PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C19Ah MPC PB2 pin function control register PB2PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C19Bh MPC PB3 pin function control register PB3PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C19Ch MPC PB4 pin function control register PB4PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C19Dh MPC PB5 pin function control register PB5PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C19Eh MPC PB6 pin function control register PB6PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C19Fh MPC PB7 pin function control register PB7PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C1A0h MPC PC0 pin function control register PC0PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C1A1h MPC PC1 pin function control register PC1PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C1A2h MPC PC2 pin function control register PC2PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C1A3h MPC PC3 pin function control register PC3PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C1A4h MPC PC4 pin function control register PC4PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C1A5h MPC PC5 pin function control register PC5PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C1A6h MPC PC6 pin function control register PC6PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C1A7h MPC PC7 pin function control register PC7PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C1A8h MPC PD0 pin function control register PD0PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C1A9h MPC PD1 pin function control register PD1PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C1AAh MPC PD2 pin function control register PD2PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C1ABh MPC PD3 pin function control register PD3PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C1ACh MPC PD4 pin function control register PD4PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C1ADh MPC PD5 pin function control register PD5PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C1AEh MPC PD6 pin function control register PD6PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C1AFh MPC PD7 pin function control register PD7PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C1B0h MPC PE0 pin function control register PE0PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C1B1h MPC PE1 pin function control register PE1PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C1B2h MPC PE2 pin function control register PE2PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C1B3h MPC PE3 pin function control register PE3PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C1B4h MPC PE4 pin function control register PE4PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C1B5h MPC PE5 pin function control register PE5PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C1B6h MPC PE6 pin function control register PE6PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C1B7h MPC PE7 pin function control register PE7PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C1C8h MPC PH0 pin function control register PH0PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C1C9h MPC PH1 pin function control register PH1PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C1CAh MPC PH2 pin function control register PH2PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C1CBh MPC PH3 pin function control register PH3PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C1D1h MPC PJ1 pin function control register PJ1PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C1D3h MPC PJ3 pin function control register PJ3PFS 8 8 2, 3 PCLKB 2 ICLK section 20.
0008 C28Fh SYSTEM Flash HOCO software standby control register FHSSBYCR 8 8 4, 5 PCLKB 2, 3 ICLK section 11.
0008 C290h SYSTEM Reset status register 0 RSTSR0 8 8 4, 5 PCLKB 2, 3 ICLK section 6.
0008 C291h SYSTEM Reset status register 1 RSTSR1 8 8 4, 5 PCLKB 2, 3 ICLK section 6.
0008 C293h SYSTEM Main clock oscillator forced oscillation control register MOFCR 8 8 4, 5 PCLKB 2, 3 ICLK section 9.
0008 C294h SYSTEM High-speed clock oscillator power supply control register HOCOPCR 8 8 4, 5 PCLKB 2, 3 ICLK section 9.
0008 C296h FLASH Flash write erase protection register FWEPROR 8 8 4, 5 PCLKB 2, 3 ICLK section 36.,
section 37.
0008 C297h SYSTEM Voltage monitoring circuit/comparator A control register LVCMPCR 8 8 4, 5 PCLKB 2, 3 ICLK section 8.,
section 33.
0008 C298h SYSTEM Voltage detection level select register LVDLVLR 8 8 4, 5 PCLKB 2, 3 ICLK section 8.,
section 33.
0008 C29Ah SYSTEM Voltage monitoring 1 circuit/comparator A1 control register 0 LVD1CR0 8 8 4, 5 PCLKB 2, 3 ICLK section 8.,
section 33.
0008 C29Bh SYSTEM Voltage monitoring 2 circuit/comparator A2 control register 0 LVD2CR0 8 8 4, 5 PCLKB 2, 3 ICLK section 8.,
section 33.
0008 C400h RTC 64-Hz counter R64CNT 8 8 2, 3 PCLKB 2 ICLK section 25.
0008 C402h RTC Second counter/Binary counter 0 RSECCNT/ 8 8 2, 3 PCLKB 2 ICLK section 25.
BCNT0
0008 C404h RTC Minute counter/Binary counter 1 RMINCNT/ 8 8 2, 3 PCLKB 2 ICLK section 25.
BCNT1
0008 C406h RTC Hour counter/Binary counter 2 RHRCNT/ 8 8 2, 3 PCLKB 2 ICLK section 25.
BCNT2
0008 C408h RTC Day-of-week counter/Binary counter 3 RWKCNT/ 8 8 2, 3 PCLKB 2 ICLK section 25.
BCNT3
0008 C40Ah RTC Date counter RDAYCNT 8 8 2, 3 PCLKB 2 ICLK section 25.
0008 C40Ch RTC Month counter RMONCNT 8 8 2, 3 PCLKB 2 ICLK section 25.
0008 C40Eh RTC Year counter RYRCNT 16 16 2, 3 PCLKB 2 ICLK section 25.
0008 C410h RTC Second alarm register/Binary counter 0 alarm register RSECAR/ 8 8 2, 3 PCLKB 2 ICLK section 25.
BCNT0AR
0008 C412h RTC Minute alarm register/Binary counter 1 alarm register RMINAR/ 8 8 2, 3 PCLKB 2 ICLK section 25.
BCNT1AR
0008 C414h RTC Hour alarm register/Binary counter 2 alarm register RHRAR/ 8 8 2, 3 PCLKB 2 ICLK section 25.
BCNT2AR
0008 C416h RTC Day-of-week alarm register/Binary counter 3 alarm register RWKAR/ 8 8 2, 3 PCLKB 2 ICLK section 25.
BCNT3AR
0008 C418h RTC Date alarm register/Binary counter 0 alarm enable register RDAYAR/ 8 8 2, 3 PCLKB 2 ICLK section 25.
BCNT0AER
0008 C41Ah RTC Month alarm register/Binary counter 1 alarm enable register RMONAR/ 8 8 2, 3 PCLKB 2 ICLK section 25.
BCNT1AER
0008 C41Ch RTC Year alarm register/Binary counter 2 alarm enable register RYRAR/ 16 16 2, 3 PCLKB 2 ICLK section 25.
BCNT2AER
0008 C41Eh RTC Year alarm enable register/Binary counter 3 alarm enable RYRAREN/ 8 8 2, 3 PCLKB 2 ICLK section 25.
register BCNT3AER
0008 C422h RTC RTC control register 1 RCR1 8 8 2, 3 PCLKB 2 ICLK section 25.
0008 C424h RTC RTC control register 2 RCR2 8 8 2, 3 PCLKB 2 ICLK section 25.
0008 C426h RTC RTC control register 3 RCR3 8 8 2, 3 PCLKB 2 ICLK section 25.
0008 C42Eh RTC Time error adjustment register RADJ 8 8 2, 3 PCLKB 2 ICLK section 25.
007F C402h FLASH Flash mode register FMODR 8 8 2, 3 FCLK 2 ICLK section 36.,
section 37.
007F C410h FLASH Flash access status register FASTAT 8 8 2, 3 FCLK 2 ICLK section 36.,
section 37.
007F C411h FLASH Flash access error interrupt enable register FAEINT 8 8 2, 3 FCLK 2 ICLK section 36.,
section 37.
007F C412h FLASH Flash ready interrupt enable register FRDYIE 8 8 2, 3 FCLK 2 ICLK section 36.,
section 37.
007F C440h FLASH E2 DataFlash read enable register 0 DFLRE0 16 16 2, 3 FCLK 2 ICLK section 37.
007F C450h FLASH E2 DataFlash programming/erasure enable register 0 DFLWE0 16 16 2, 3 FCLK 2 ICLK section 37.
007F FFB0h FLASH Flash status register 0 FSTATR0 8 8 2, 3 FCLK 2 ICLK section 36.,
section 37.
007F FFB1h FLASH Flash status register 1 FSTATR1 8 8 2, 3 FCLK 2 ICLK section 36.,
section 37.
007F FFB2h FLASH Flash P/E mode entry register FENTRYR 16 16 2, 3 FCLK 2 ICLK section 36.,
section 37.
007F FFB4h FLASH Flash protection register FPROTR 16 16 2, 3 FCLK 2 ICLK section 36.
007F FFB6h FLASH Flash reset register FRESETR 16 16 2, 3 FCLK 2 ICLK section 36.
007F FFBAh FLASH FCU command register FCMDR 16 16 2, 3 FCLK 2 ICLK section 36.
007F FFC8h FLASH FCU processing switching register FCPSR 16 16 2, 3 FCLK 2 ICLK section 36.
007F FFCAh FLASH E2 DataFlash blank check control register DFLBCCNT 16 16 2, 3 FCLK 2 ICLK section 37.
007F FFCCh FLASH Flash P/E status register FPESTAT 16 16 2, 3 FCLK 2 ICLK section 36.,
section 37.
007F FFCEh FLASH E2 DataFlash blank check status register DFLBCSTAT 16 16 2, 3 FCLK 2 ICLK section 37.
007F FFE8h FLASH Peripheral clock notification register PCKAR 16 16 2, 3 FCLK 2 ICLK section 36.,
section 37.
Note 1. Odd addresses cannot be accessed in 16-bit units. When accessing a register in 16-bit units, access the address of the TMR0 or TMR2 register. Table 23.4 lists register
allocation for 16-bit access.
Note 2. Odd addresses cannot be accessed in 16-bit units. When accessing a register in 16-bit units, access the address of the TMOCNTL register. Table 29.3 lists register
allocation for 16-bit access.
6. Resets
6.1 Overview
There are seven types of resets: RES# pin reset, power-on reset, voltage monitoring 0 reset, voltage monitoring 1 reset,
voltage monitoring 2 reset, independent watchdog timer reset, and software reset.
Table 6.1 lists the reset names and sources.
Note 1. For the voltages to be monitored (VPOR, Vdet0, Vdet1, and Vdet2), see section 8, Voltage Detection Circuit (LVDAa) and
section 38, Electrical Characteristics.
When a reset is canceled, the reset exception handling starts. For the reset exception handling, see section 13,
Exception Handling.
Table 6.3 lists the pin related to the reset.
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — — CWSF
RSTSR1 determines whether a power-on reset has caused the reset processing (cold start) or a reset signal input during
operation has caused the reset processing (warm start).
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — SWRF — IWDTR
F
Value after reset: 0 0 0 0 0 0*1 0 0*1
SWRR[15:0]
Note: • Set the PRCR.PRC1 bit to 1 (write enabled) before rewriting this register.
6.3 Operation
*3
Vdet0*1
VPOR*1
RES# pin
Voltage detection 0
signal (Low is valid)
tPOR*2 tLVD0*2
Internal reset signal
RSTSR0.LVD0RF
Note: • For details on the electrical characteristics, see section 38, Electrical Characteristics.
Note 1. Vdet0 indicates the detection level for a voltage monitoring 0 reset and VPOR indicates the detection level for a
power-on reset.
Note 2. tPOR indicates the period of a power-on reset and tLVD0 indicates the period of a voltage monitoring 0 reset.
Note 3. At the time the power-supply voltage rises, VCC must rise to at least the minimum guaranteed voltage before release
from the POR reset state.
Figure 6.1 Operation Examples During a Power-On Reset and Voltage Monitoring 0 Reset
select bit (LVD1RN) in the LVD1CR0 register. When the LVD1CR0.LVD1RN bit is 0 and VCC has fallen to or below
Vdet1, the CPU is released from the internal reset state and starts reset exception handling once the voltage monitoring 1
reset time (tLVD1) has elapsed after VCC has risen above Vdet1. When the LVD1CR0.LVD1RN bit is 1 and VCC has
fallen to or below Vdet1, the CPU is released from the internal reset state and starts reset exception handling once the
voltage monitoring 1 reset time (tLVD1) has elapsed.
Likewise, timing for release from the voltage monitoring 2 reset state is selectable by setting the voltage monitoring 2/
comparator A2 reset negation select bit (LVD2RN) in the LVD2CR0 register. Detection levels Vdet1 and Vdet2 can be
changed by settings in the voltage detection level select register (LVDLVLR).
Figure 6.2 shows examples of operations during voltage monitoring 1 and 2 resets.
For details on the voltage monitoring 1 reset and voltage monitoring 2 reset, refer to section 8, Voltage Detection
Circuit (LVDAa).
Vdeti*1
External voltage
VCC
RES# pin
LVDi valid setting
LVCMPCR.LVDiE
LVDiCR0.LVDiRN = 0
Voltage detection i
signal (Low is valid)
RES# pin reset
RSTSR0.LVDiRF
tLVDi*2
Internal reset signal
LVDiCR0.LVDiRN = 1
Voltage detection i
signal (Low is valid)
RES# pin reset
RSTSR0.LVDiRF
tLVDi*2
Internal reset signal
Note: • For details on the electrical characteristics, see section 38, Electrical Characteristics.
Note 1. Vdeti shows a detection level of voltage monitoring 1 reset and voltage monitoring 2 reset.
Note 2. tLVDi shows a time for voltage monitoring 1 reset and voltage monitoring 2 reset.
(i = 1, 2)
Figure 6.2 Operation Examples During Voltage Monitoring 1 Reset and Voltage Monitoring 2 Reset
VPOR
RES# pin
Reset exception
handling
RSTSR2. No
SWRF=1
Yes RSTSR0. No
LVD2RF=1
Yes RSTSR0. No
LVD1RF=1
Yes RSTSR2. No
IWDTRF=1
Yes RSTSR0. No
LVD0RF=1
Yes RSTSR0. No
PORF=1
Yes
7. Option-Setting Memory
7.1 Overview
Option-setting memory refers to a set of registers that are provided for selecting the state of the microcontroller after a
reset. The option-setting memory is allocated in the ROM.
Figure 7.1 shows the option-setting memory area.
Addresses
4 bytes
b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16
— — — — — — — — — — — — — — — —
Note 1. The value of the blank product is FFFF FFFFh. It is set to the written value after written by the user.
The OFS0 register selects the operations of the independent watchdog timer (IWDT) after a reset.
The OFS0 register is allocated in the ROM. Set this register at the same time as writing the program. After writing to the
OFS0 register once, do not write to it again.
When erasing the block including the OFS0 register, the OFS0 register value becomes FFFF FFFFh.
The setting in the OFS0 register is ineffective in user boot mode, and the value becomes FFFF FFFFh.
b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16
— — — — — — — — — — — — — — — —
Note 1. The value of the blank product is FFFF FFFFh. It is set to the written value after written by the user.
The OFS1 register is allocated in the ROM. Set this register at the same time as writing the program. After writing, do
not write additions to this register.
When erasing the block including the OFS1 register, the setting in the OFS1 register is ineffective, and the OFS1 register
value becomes FFFF FFFFh.
The setting in the OFS1 register is ineffective in user boot mode, and the value becomes FFFF FFFFh.
b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16
— — — — — — — — — — — — — — — —
— — — — — — — — — — — — — MDE[2:0]
Note 1. The value of the blank product is FFFF FFFFh. It is set to the written value after written by the user.
The MDEn (n = B, S) register selects the endian for the CPU. In user boot mode, the endian select register B (MDEB) at
address FF7F FFF8h is used to select the endian. In single-ship mode, the endian select register S (MDES) at address
FFFF FF80h is used.
MDEn is allocated in the ROM. Set the register at the same time as writing the program. After writing to the register
once, do not write to it again.
When erasing the block including the MDEn register, the MDEn register value becomes FFFF FFFFh.
7.3 UB Code
UB codes A and B are required if user boot mode is to be employed.The MCU will start up in user boot mode on release
from the reset state if the four conditions below are satisfied.
UB code A is 55736572h and 426F6F74h.
UB code B is FFFFFF07h and 0008C04Ch.
The low level is being input on the MD pin.
The high level is being input on the PC7 pin.
7.3.1 UB code A
UB code A consists of two 32-bit words. Set UB code A to 55736572h and 426F6F74h. Do not set other values for the
code.
Figure 7.2 shows the configuration of UB code A. Set UB code A in 32-bit units.
7.3.2 UB Code B
UB code B consists of two 32-bit words. Set UB code B to FFFFFF07h and 0008C04Ch. Do not set other values for the
code.
Figure 7.3 shows the configuration of UB code B. Set UB code B in 32-bit units.
8.1 Overview
In voltage detection 0, the detection voltage can be selected from four levels by using option function select register 1
(OFS1).
In voltage detection 1 and voltage detection 2, the detection voltage can be selected from sixteen levels using the voltage
detection level select register (LVDLVLR).
Voltage detection 2 can be switched between input voltages to VCC and the CMPA2 pin.
Reset of voltage monitoring 0, reset/interrupt of voltage monitoring 1, and reset/interrupt of voltage monitoring 2 can be
used.
However, voltage monitoring 1 and comparator A1 cannot be used at the same time because they share the voltage
detection circuit. Similarly, voltage monitoring 2 and comparator A2 cannot be used at the same time because they share
the voltage detection circuit.
Table 8.1 lists the specifications of the voltage detection circuit. Figure 8.1 is a block diagram of the voltage detection
circuit. Figure 8.2 is a block diagram of the voltage monitoring 1 interrupt/reset circuit. Figure 8.3 is a block diagram of
the voltage monitoring 2 interrupt/reset circuit.
LVDAS
VCC
-
Internal reference Level selection Vdet0
voltage circuit
(for detecting Vdet0) (4 levels) Shared use with comparator A1
VDSEL[1:0]
LVD1E
LVD1CMPE
EXVCCINP1=0
-
Vdet1
Internal reference Level selection
voltage circuit
(for detecting Vdet1) (16 levels) EXVREFINP1=0
LVD1LVL[3:0]
Shared use with comparator A2
CMPA2
LVD2E
LVD2CMPE
EXVCCINP2=1
+
Voltage detection 2 signal
EXVCCINP2=0
-
Vdet2
Internal reference Level selection
voltage circuit
(for detecting Vdet2) (16 levels)
EXVREFINP2=0
LVD2LVL[3:0]
LVD1FSAMP[1:0]
The setting of the LVD1DET bit will be 0 if 0 (undetected) is written in the program.
=00b
=01b
=10b
Voltage detection 1 circuit =11b
LOCO 1/2 1/2 1/2
LVD1SR
VCC
LVD1E b1
LVD2FSAMP[1:0]
The setting of the LVD2DET bit will be 0 if 0 (undetected) is written by the program.
=00b
=01b
=10b
Voltage detection 2 circuit =11b
LOCO 1/2 1/2 1/2
VCC
LVD2SR
LVD2E
LVD2CMPE b1 LVD2RIE
EXVCCINP2=0 LVD2RI
LVD2DFDIS=0 LVD2MON
+ Digital LVD2RN=0
filter
CMPA2 EXVCCINP2=1 Voltage Voltage
- detection 2 Fixed monitoring 2
LVD2DFDIS=1 period
signal LVD2RN=1 reset signal
Internal reference negation (Low is valid)
voltage Level selection
(for detection of EXVREFINP2=0 LVD2DET
Vdet2)
LVD2LVL[3:0] Edge
selection b0
circuit Voltage
monitoring 2
non-maskable
interrupt signal
Voltage detection 2 signal will be high when the setting of
the LVD2E bit is 0 (disabled) LVD2IDTSEL[1:0]
LVD2IRQSEL Voltage
monitoring 2
maskable
interrupt signal
Table 8.2 lists the input/output pins relevant to the voltage detection circuit.
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — LVD1IR LVD1IDTSEL
QSEL [1:0]
Value after reset: 0 0 0 0 0 0 0 1
Note: • Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — LVD1M LVD1D
ON ET
Value after reset: 0 0 0 0 0 0 1 0
Note: • Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
Note 1. Only 0 can be written to this bit. After writing 0 to this bit, it takes 2 system clock cycles for the bit to be read as 0.
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — LVD2IR LVD2IDTSEL
QSEL [1:0]
Value after reset: 0 0 0 0 0 0 0 1
Note: • Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — LVD2M LVD2D
ON ET
Value after reset: 0 0 0 0 0 0 1 0
Note: • Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
Note 1. Only 0 can be written to this bit. After writing 0 to this bit, it takes 2 system clock cycles for the bit to be read as 0.
b7 b6 b5 b4 b3 b2 b1 b0
Note: • Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
Note 1. The LVDLVLR.LVD2LVL[3:0] bits must be set to 0001b when the EXVCCINP2 bit is to be set to 1 (CMPA2 pin input voltage).
b7 b6 b5 b4 b3 b2 b1 b0
LVD2LVL[3:0] LVD1LVL[3:0]
Note: • Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
When changing the LVDLVLR register, first set the LVCMPCR.LVD1E and LVCMPCR.LVD2E bits to 0 (voltage
detection n circuit disabled) (n = 1, 2).
Do not use the voltage detection 1 and 2 circuits at the same detection voltage level. When setting the detection voltage
level of the voltage detection 0 circuit to 1.90 V, do not set the detection voltage level of the voltage detection 1 and 2
circuits to 1.90 V. When setting the detection voltage level of the voltage detection 0 circuit to 2.80 V, do not set the
detection voltage level of the voltage detection 1 and 2 circuits to 2.80 V.
b7 b6 b5 b4 b3 b2 b1 b0
x: Undefined
Note: • Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
LVD1DFDIS Bit (Voltage Monitoring 1/Comparator A1 Digital Filter Disable Mode Select)
Set the LOCOCR.LCSTP bit to 0 (the LOCO operates) if the LVD1DFDIS bit is 0 (digital filter enabled).
Set the LVD1DFDIS bit to 1 (digital filter disabled) when using voltage monitoring 1 circuit in software standby mode.
b7 b6 b5 b4 b3 b2 b1 b0
x: Undefined
Note: • Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
LVD2DFDIS Bit (Voltage Monitoring 2/Comparator A2 Digital Filter Disable Mode Select)
Set the LOCOCR.LCSTP bit to 0 (the LOCO operates) if the LVD1DFDIS bit is 0 (digital filter enabled).
Set the LVD2DFDIS bit to 1 (digital filter disabled) when using voltage monitoring 2 circuit in software standby mode.
*3
Vdet0*1
VPOR*1
RES# pin
Voltage detection 0
signal (Low is valid)
tPOR*2 tLVD0*2
Internal reset signal
RSTSR0.LVD0RF
Note: • For details on the electrical characteristics, see section 38, Electrical Characteristics.
Note 1. Vdet0 indicates the detection level for a voltage monitoring 0 reset and VPOR indicates the detection level for a
power-on reset.
Note 2. tPOR indicates the period of a power-on reset and tLVD0 indicates the period of a voltage monitoring 0 reset.
Note 3. At the time the power-supply voltage rises, VCC must rise to at least the minimum guaranteed voltage before release
from the POR reset state.
Table 8.5 Procedures for Setting Bits Related to the Voltage Monitoring 1 Interrupt and Voltage Monitoring 1
Reset
When the Digital Filter is in Use When the Digital Filter is Not in Use
Voltage Monitoring 1 Voltage Monitoring 1
Interrupt, Voltage Interrupt, Voltage
Monitoring 1 ELC Event Monitoring 1 ELC Event
Step Output Voltage Monitoring 1 Reset Output Voltage Monitoring 1 Reset
1*2 Select the detection voltage by setting the LVDLVLR.LVD1LVL[3:0] bits.
2*2 Set the LVCMPCR.EXVREFINP1 bit to 0 (internal reference voltage).
Set the LVCMPCR.EXVCCINP1 bit to 0 (VCC voltage).
3*1 Select the sampling clock for the digital filter by setting the Set the LVD1CR0.LVD1DFDIS bit to 1 (disabling the digital
LVD1CR0.LVD1FSAMP[1:0] bits. filter).
4 Clear the LVD1CR0.LVD1RI Set the LVD1CR0.LVD1RI bit Clear the LVD1CR0.LVD1RI Set the LVD1CR0.LVD1RI bit
*1, *2 bit to 0 (to select the voltage to 1 (to select the voltage bit to 0 (to select the voltage to 1 (to select the voltage
monitoring 1 interrupt). monitoring 1 reset). monitoring 1 interrupt). monitoring 1 reset).
Select the type of reset nega- Select the type of reset nega-
tion by setting the tion by setting the
LVD1CR0.LVD1RN bit. LVD1CR0.LVD1RN bit.
5 Select the timing of interrupt — Select the timing of interrupt —
requests by setting the requests by setting the
LVD1CR1.LVD1IDTSEL[1:0] LVD1CR1.LVD1IDTSEL[1:0]
bits. bits.
Select the type of interrupt by Select the type of interrupt by
setting the setting the
LVD1CR1.LVD1IRQSEL bit. LVD1CR1.LVD1IRQSEL bit.
6 — Set the LVD1CR0.LVD1RIE — Set the LVD1CR0.LVD1RIE
bit to 1 (enabling voltage bit to 1 (enabling voltage
monitoring 1 interrupt/reset) monitoring 1 interrupt/reset)
7*2 Set the LVCMPCR.LVD1E bit to 1 (enabling the circuit for voltage detection 1).
8*2 Wait for at least td(E-A) or longer.
9 Set the LVD1CR0.LVD1CMPE bit to 1 (enabling output of the results of comparison by the voltage monitoring 1 circuit).
10 Wait for at least one cycle of the LOCO. —
11 Clear the LVD1CR0.LVD1DFDIS bit to 0 (enabling the digital —
filter).
12 Wait for at least 2n + 3 cycles of the LOCO (where n = 1, 2, 4, — (No waiting is required.)
8, and the sampling clock for the digital filter is the LOCO
frequency-divided by n).
13 Clear the LVD1SR.LVD1DET — Clear the LVD1SR.LVD1DET —
bit to 0. bit to 0.
14 Set the LVD1CR0.LVD1RIE — Set the LVD1CR0.LVD1RIE —
bit to 1 (enabling voltage bit to 1 (enabling voltage
monitoring 1 interrupt/reset) monitoring 1 interrupt/reset)
Note 1. Executing steps 3 and 4 at the same time (with a single instruction) creates no problems.
Note 2. Steps 1, 2, 4, 7, and 8 are not required if operation is with the setting to select the voltage monitoring 1 interrupt
(LVD1CR0.LVD1RI = 0) and operation can be restarted by simply changing the settings of the LVD1CR0.LVD1DFDIS and
LVD1FSAMP bits or LVD1CR1.LVD1IRQSEL and LVD1IDTSEL bits after monitoring is stopped or if restarting is in a case
where the settings related to the voltage-detection circuit were not changed after monitoring was stopped. When changes are to
be made and operation is with the setting to select the voltage monitoring 1 reset (LVD1CR0.LVD1RI = 1), proceed through all
steps from 1 to 14.
Table 8.6 Procedures for Stopping Bits Related to the Voltage Monitoring 1 Interrupt and Voltage Monitoring
1 Reset
Voltage Monitoring 1 Interrupt, Voltage Monitoring 1 ELC
Step Event Output Voltage Monitoring 1 Reset
1 Clear the LVD1CR0.LVD1RIE bit to 0 (disabling voltage —
monitoring 1 interrupt/reset).
2 Clear the LVD1CR0.LVD1CMPE bit to 0 (disabling output of the results of comparison by the voltage monitoring 1 circuit).
3*1 Clear the LVCMPCR.LVD1E bit to 0 (disable the voltage monitoring 1 circuit).
4 — Clear the LVD1CR0.LVD1RIE bit to 0 (disabling voltage
monitoring 1 interrupt/reset).
5 Modify settings of bits related to the voltage detection circuit registers other than LVCMPCR.LVD1E, LVD1CR0.LVD1RIE, and
LVD1CR0.LVD1CMPE.
Note 1. Step 3 is not required if operation is with the setting to select the voltage monitoring 1 interrupt (LVD1CR0.LVD1RI = 0) and
operation can be restarted by simply changing the settings of the LVD1CR0.LVD1DFDIS and LVD1FSAMP bits or
LVD1CR1.LVD1IRQSEL and LVD1IDTSEL bits after monitoring is stopped or if restarting is in a case where the settings related
to the voltage-detection circuit were not changed after monitoring was stopped. When changes are to be made and operation is
with the setting to select the voltage monitoring 1 reset (LVD1CR0.LVD1RI = 1), proceed through all steps from 1 to 5.
VCC
Vdet1
1n + 2 to 2n + 3 cycles 1n + 2 to 2n + 3 cycles
of the LOCO of the LOCO
LVD1DFDIS bit is set to 0 (digital filter LVD1DET bit
enabled) and LVD1IDTSEL[1:0] bits
are set to 10b (when drop and rise are Set to 0 by a program
detected)
Voltage monitoring 1
interrupt request
Set to 0 by a program
Set to 0 by a program
LVD1DFDIS bit is set to 0 (digital LVD1DET bit
filter enabled), LVD1IDTSEL[1:0]
bits are set to 01b (when drop is
detected).
Voltage monitoring 1
interrupt request
Set to 0 by a program
LVD1DFDIS bit is set to 1 (digital LVD1DET bit
filter disabled), LVD1IDTSEL[1:0]
bits are set to 01b (when drop is
detected). Voltage monitoring 1
interrupt request
n: the frequency of the sampling clock for the digital filter is the LOCO frequency divided by n
Note 1. When the voltage monitoring 0 reset is not in use, VCC VCCmin.
Table 8.7 Procedures for Setting Bits Related to the Voltage Monitoring 2 Interrupt and Voltage Monitoring 2
Reset
When the Digital Filter is in Use When the Digital Filter is Not in Use
Voltage Monitoring 2 Voltage Monitoring 2
Step Interrupt Voltage Monitoring 2 Reset Interrupt Voltage Monitoring 2 Reset
1*2 Select the detection voltage by setting the LVDLVLR.LVD2LVL[3:0] bits.
2*2 Set the LVCMPCR.EXVREFINP2 bit to 0 (internal reference voltage).
Set the LVCMPCR.EXVCCINP2 bit to 0 (VCC voltage) or set it to 1 (selecting the input voltage on the CMPA2 pin).
3*1 Select the sampling clock for the digital filter by setting the Set the LVD2CR0.LVD2DFDIS bit to 1 (disabling the digital
LVD2CR0.LVD2FSAMP[1:0] bits. filter).
4 Clear the LVD2CR0.LVD2RI Set the LVD2CR0.LVD2RI bit Clear the LVD2CR0.LVD2RI Set the LVD2CR0.LVD2RI bit
*1, *2 bit to 0 (to select the voltage to 1 (to select the voltage bit to 0 (to select the voltage to 1 (to select the voltage
monitoring 2 interrupt). monitoring 2 reset). monitoring 2 interrupt). monitoring 2 reset).
Select the type of reset nega- Select the type of reset nega-
tion by setting the tion by setting the
LVD2CR0.LVD2RN bit. LVD2CR0.LVD2RN bit.
5 Select the timing of interrupt — Select the timing of interrupt —
requests by setting the requests by setting the
LVD2CR1.LVD2IDTSEL[1:0] LVD2CR1.LVD2IDTSEL[1:0]
bits. bits.
Select the type of interrupt by Select the type of interrupt by
setting the setting the
LVD2CR1.LVD2IRQSEL bit. LVD2CR1.LVD2IRQSEL bit.
6 — Set the LVD2CR0.LVD2RIE — Set the LVD2CR0.LVD2RIE
bit to 1 (enabling voltage bit to 1 (enabling voltage
monitoring 2 interrupt/reset) monitoring 2 interrupt/reset)
7*2 Set the LVCMPCR.LVD2E bit to 1 (enabling the circuit for voltage detection 2).
8*2 Wait for at least td(E-A) or longer.
9 Set the LVD2CR0.LVD2CMPE bit to 1 (enabling output of the results of comparison by the voltage monitoring 2 circuit).
10 Wait for at least one cycle of the LOCO. —
11 Clear the LVD2CR0.LVD2DFDIS bit to 0 (enabling the digital —
filter).
12 Wait for at least 2n + 3 cycles of the LOCO (where n = 1, 2, 4, — (No waiting is required.)
8, and the sampling clock for the digital filter is the LOCO
frequency-divided by n).
13 Clear the LVD2SR.LVD2DET — Clear the LVD2SR.LVD2DET —
bit to 0. bit to 0.
14 Set the LVD2CR0.LVD2RIE — Set the LVD2CR0.LVD2RIE —
bit to 1 (enabling voltage bit to 1 (enabling voltage
monitoring 2 interrupt/reset) monitoring 2 interrupt/reset)
Note 1. Executing steps 3 and 4 at the same time (with a single instruction) creates no problems.
Note 2. Steps 1, 2, 4, 7, and 8 are not required if operation is with the setting to select the voltage monitoring 2 interrupt
(LVD2CR0.LVD2RI = 0) and operation can be restarted by simply changing the settings of the LVD2CR0.LVD2DFDIS and
LVD2FSAMP bits or LVD2CR1.LVD2IRQSEL and LVD2IDTSEL bits after monitoring is stopped or if restarting is in a case
where the settings related to the voltage-detection circuit were not changed after monitoring was stopped. When changes are to
be made and operation is with the setting to select the voltage monitoring 2 reset (LVD2CR0.LVD2RI = 1), proceed through all
steps from 1 to 14.
Table 8.8 Procedures for Stopping Bits Related to the Voltage Monitoring 2 Interrupt and Voltage Monitoring
2 Reset
Step Voltage Monitoring 2 Interrupt Voltage Monitoring 2 Reset
1 Clear the LVD2CR0.LVD2RIE bit to 0 (disabling voltage —
monitoring 2 interrupt/reset).
2 Clear the LVD2CR0.LVD2CMPE bit to 0 (disabling output of the results of comparison by the voltage monitoring 2 circuit).
3*1 Clear the LVCMPCR.LVD2E bit to 0 (disable the voltage monitoring 2 circuit).
4 — Clear the LVD2CR0.LVD2RIE bit to 0 (disabling voltage
monitoring 2 interrupt/reset).
5 Modify settings of bits related to the voltage detection circuit registers other than LVCMPCR.LVD2E, LVD2CR0.LVD2RIE, and
LVD2CR0.LVD2CMPE.
Note 1. Step 3 is not required if operation is with the setting to select the voltage monitoring 2 interrupt (LVD2CR0.LVD2RI = 0) and
operation can be restarted by simply changing the settings of the LVD2CR0.LVD2DFDIS and LVD2FSAMP bits or
LVD2CR1.LVD2IRQSEL and LVD2IDTSEL bits after monitoring is stopped or if restarting is in a case where the settings related
to the voltage-detection circuit were not changed after monitoring was stopped. When changes are to be made and operation is
with the setting to select the voltage monitoring 2 reset (LVD2CR0.LVD2RI = 1), proceed through all steps from 1 to 5.
VCC
Vdet2
1n + 2 to 2n + 3 cycles 1n + 2 to 2n + 3 cycles
of the LOCO of the LOCO
Voltage monitoring 2
interrupt request
Set to 0 by a program
Set to 0 by a program
LVD2DFDIS bit is set to 0 (digital LVD2DET bit
filter enabled), LVD2IDTSEL[1:0]
bits are set to 01b (when drop is
detected).
Voltage monitoring 2
interrupt request
Set to 0 by a program
Set to 0 by a program
LVD2DFDIS bit is set to 1 (digital LVD2DET bit
filter disabled), LVD2IDTSEL[1:0]
bits are set to 01b (when drop is
detected). Voltage monitoring 2
interrupt request
n: the frequency of the sampling clock for the digital filter is the LOCO frequency divided by n
Note 1. When the voltage monitoring 0 reset is not in use, VCC VCCmin.
When enabling the LVD's event link output function, be sure to make settings for enabling the LVD before enabling the
LVD event link function of the ELC. To stop the LVD's event link output function, be sure to make settings for stopping
the LVD after disabling the LVD event link function of the ELC.
Note 1. The maximum operating frequency in middle-speed operating mode A1. For the maximum operating frequency in the other
operating modes, see section 11.2.5, Operating Power Control Register (OPCCR).
SCKCR FCK[3:0]
Selector
FlashIF clock (FCLK)
To FlashIF
SCKCR ICK[3:0]
Selector
System clock (ICLK)
To CPU, DTC, DMAC, ROM,
and RAM
Frequency
CKSEL[2:0] divider SCKCR PCKB[3:0], PCKD[3:0]
SCKCR3 1/1
Selector
Oscillation 1/4
Selector
(PCLKB, PCLKD)
stop 1/8
detection 1/16 To peripheral module
circuit 1/32
1/64
XTAL
Main clock
Selector
oscillator
EXTAL Main clock
XCIN
Sub-clock Sub-clock
oscillator
XCOUT
(CACILCLK)
(CACLCLK)
CAC clock
To CAC (CACHCLK)
(CACSCLK)
To RTC-dedicated clock (RTCSCLK)
(CACMCLK)
To RTC
Table 9.2 lists the input/output pins of the clock generation circuit.
b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16
— — — — PCKB[3:0] — — — — PCKD[3:0]
When an instruction for writing to SCKCR, or SCKCR3 is to follow writing to the SCKCR register, do so in accord with
the procedure below.
1. Write to the SCKCR register.
2. Confirm that the value has actually been written to the SCKCR register.
3. Proceed to the next step.
— — — — — CKSEL[2:0] — — — — — — — —
Note: • Set the PRCR.PRC0 bit to 1 (write enabled) before rewriting this register.
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — — MOSTP
Note: • Set the PRCR.PRC0 bit to 1 (write enabled) before rewriting this register.
Set up this register after setting up the main clock oscillator wait control register described in section 11, Low Power
Consumption.
Do not set the MOSTP bit to 1 when one of the following conditions is met.
When the main clock is selected as the clock source for the system clock (SCKCR3.CKSEL[2:0] = 010b)
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — — SOSTP
Note: • Set the PRCR.PRC0 bit to 1 (write enabled) before rewriting this register.
Set up this register after setting up the sub-clock oscillator wait control register described in section 11, Low Power
Consumption.
Writing 1 to the SOSTP bit (stopping the sub-clock oscillator) is prohibited while the sub-clock oscillator is selected by
the clock source select bits in system clock control register 3 (SCKCR3.CKSEL[2:0]).
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — — LCSTP
Note: • Set the PRCR.PRC0 bit to 1 (write enabled) before rewriting this register.
Writing 1 to the LCSTP bit (stopping the LOCO) is prohibited while the LOCO is selected by the clock source select bits
in system clock control register 3 (SCKCR3.CKSEL[2:0]).
Writing 1 to the LCSTP bit (stopping the LOCO) is prohibited if detection of oscillation stopping is enabled by the
oscillation-stop detection-enable bit in the oscillation stop detection control register (OSTDCR.OSTDE).
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — — ILCSTP
Note: • Set the PRCR.PRC0 bit to 1 (write enabled) before rewriting this register.
When the IWDT start mode select bit in option function select register 0 (OFS0.IWDTSTRT) is 0 (IWDT operating), the
setting of this register is invalid; it is valid only when the OFS0.IWDTSTRT bit is set to 1 (IWDT stopped). The ILCSTP
bit cannot be changed from 0 (IWDT-dedicated on-chip oscillator operating) to 1 (IWDT-dedicated on-chip oscillator
stopped) while ILOCOCR is valid.
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — — HCSTP
Note: • Set the PRCR.PRC0 bit to 1 (write enabled) before rewriting this register.
Set up this register after setting up the HOCO wait control register 2 described in section 11, Low Power
Consumption.
Writing 1 to the HCSTP bit (stopping the HOCO) is prohibited while the HOCO is selected by the clock source select
bits (CKSEL[2:0]) in system clock control register 3 (SCKCR3).
Writing 0 to the HCSTP bit (making the HOCO operate) is prohibited when the setting of the operating power control
mode select bits in the operating power control register (OPCCR.OPCM[2:0]) is for low-speed operating mode 2.
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — HCFRQ[1:0]
Note: • Set the PRCR.PRC0 bit to 1 (write enabled) before rewriting this register.
Writing to the HOCOCR2 register is prohibited while the HOCOCR.HCSTP bit is 0 (the setting for the HOCO to
operate).
b7 b6 b5 b4 b3 b2 b1 b0
OSTDE — — — — — — OSTDI
E
Value after reset: 0 0 0 0 0 0 0 0
Note: • Set the PRCR.PRC0 bit to 1 (write enabled) before rewriting this register.
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — — OSTDF
Note: • Set the PRCR.PRC0 bit to 1 (write enabled) before rewriting this register.
Note 1. This bit can only be set to 0.
[Setting condition]
The main clock oscillation is stopped with the OSTDCR.OSTDE bit being 1 (oscillation stop detection function
enabled).
[Clearing condition]
1 is read and then 0 is written when the SCKCR3.CKSEL[2:0] bits are neither 010b.
b7 b6 b5 b4 b3 b2 b1 b0
Note: • Set the PRCR.PRC1 bit to 1 (write enabled) before rewriting this register.
The EXTAL/XTAL pin is also used as a port. In the initial setting state, the pin is set as a port.
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — — HOCO
PCNT
Value after reset: 0 0 0 0 0 0 0 0
Note: • Set the PRCR.PRC1 bit to 1 (write enabled) before rewriting this register.
CL1
EXTAL
Rf
XTAL
Figure 9.3 shows an equivalent circuit of the crystal resonator. Use a crystal resonator that has the characteristics shown
in Table 9.4.
CL
L RS
XTAL EXTAL
C0
XTAL Hi-Z
C1
XCIN
Rf
XCOUT
Rd
C2 C1 = 8 pF, C2 = 5 pF (reference values)
Figure 9.6 shows an equivalent circuit for the 32.768-kHz crystal resonator. Use a crystal resonator that has the
characteristics listed in Table 9.5.
CS
LS RS
XCIN XCOUT
C0
XCIN
XCOUT Open
Switching between the main clock and LOCO clock is controlled by the oscillation stop detection flag
(OSTDSR.OSTDF). The clock source is switched to the low-speed clock when the OSTDF flag is 1, and is switched to
the main clock again when the OSTDF flag is cleared to 0. At this time, if the main clock is selected with the
CKSEL[2:0] bits, the OSTDF flag cannot be cleared to 0. To switch the clock source to the main clock again after the
oscillation stop detection, set the CKSEL[2:0] bits to a clock source other than the main clock and clear the OSTDF flag
to 0. After that, check that the OSTDF flag is not 1, and then set the CKSEL[2:0] bits to the main clock after the specified
oscillation stabilization time has elapsed.
After a reset is released, the main clock oscillator is stopped and the oscillation stop detection function is disabled. To
enable the oscillation stop detection function, activate the main clock oscillator and write 1 to the oscillation stop
detection function enable bit (OSTDCR.OSTDE) after a specified oscillation stabilization time has elapsed.
The oscillation stop detection function is provided against the main clock stop by an external cause. Therefore, the
oscillation stop detection function should be disabled before the main clock oscillator is stopped by the software or a
transition is made to software standby mode.
The clocks that are switched to the LOCO clock by the oscillation stop detection are: the main clock, and CAC main
clock (CACMCLK), which are provided as the system clock sources.
The system clock (ICLK) frequency during the LOCO clock operation is specified by the LOCO oscillation frequency
and the division ratio set by the system clock select bits (SCKCR.ICK[3:0])
Start
Setting OSTDCR.OSTDIE = 0
Reading OSTDSR.OSTDF = 1
Yes
Setting OSTDSR.OSTDF = 0
No
OSTDSR.OSTDF = 0 Try again?
Yes
No
End
Note: • On return from the oscillation-stopped state, the factor responsible for stopping the main clock oscillation
circuit must be removed on the user system to allow the return of oscillation.
(1) Operating clock of the CPU, DMAC, DTC, ROM, and RAM: System clock (ICLK)
(2) Operating clock of peripheral modules: Peripheral module clock (PCLKB and PCLKD)
(3) Operating clock of the FlashIF: FlashIF clock (FCLK)
(4) Operating clock for the CAC: CAC clock (CACCLK)
(5) Operating clock for the RTC: RTC-dedicated sub-clock (RTCSCLK)
(6) Operating clock for the IWDT: IWDT-dedicated clock (IWDTCLK)
Frequencies of the internal clocks are set by the combination of the division ratios selected by the FCK[3:0], ICK[3:0],
PCKB[3:0], and PCKD[3:0] bits in SCKCR, and the clock source selected by the CKSEL[2:0] bits in SCKCR3. If the
value of any of these bits is changed, subsequent operation will be at the frequency determined by the new value.
LSI
C L2
XTAL
EXTAL
C L1
Figure 9.9 Notes on Board Design for Oscillation Circuit (Applies to the Sub-Clock Oscillator, in Case of the
Main Clock Oscillator)
Note 1. For details on the oscillation stabilization wait time of the sub-clock, see section 11.2.8, Sub-Clock Oscillator Wait
Control Register (SOSCWTCR).
Regardless of the RCR3.RTCEN bit setting, wait until the oscillator stabilization wait time elapses before rewriting
the SOSCCR.SOSTP bit to 0 (sub-clock oscillator is operating).
Since the sub-clock control circuit is in an unstable state after a cold start, it must be initialized regardless of
whether or not the sub-clock is in use. The sub-clock is initialized by setting the SOSCCR.SOSTP bit to 1 and the
RCR3.RTCEN bit to 0 (sub-clock oscillator is stopped). See section 25.2.19, RTC Control Register 3 (RCR3),
for instructions to initialize the RCR3.RTCEN bit.
Although the sub-clock oscillator pins are not available in 48-pin LQFP packages, initialize the sub-clock control
circuit in the same way.
The RCR3.RTCDV[2:0] bits must also be set when operating the sub-clock oscillator. Set these bits while the sub-
clock oscillator is stopped. Do not rewrite these bits while the sub-clock oscillator is operating.
When successively rewriting the SOSCCR.SOSTP bit followed by the RCR3.RTCEN bit or vice versa, confirm that
the first bit rewrite was completed successfully before rewriting the second bit.
10.1 Overview
Table 10.1 shows the specifications of the CAC and Figure 10.1 shows a block diagram of the CAC.
CACREFE DFS[1:0]
DFS[1:0]
CACREF Pin
Digital filter
RSCS[2:0] RCDS[1:0]
EDGES[1:0]
1/32
dividing circuit
Reference
Frequency
FMCS[2:0] TCSS[1:0]
Frequency
measurement
clock CFME
Main clock
Sub-clock Frequency 1/4 Count source
dividing circuit
Frequency
Comparator
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — — CFME
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
RCDS[1:0] Bits (Reference Signal Generation Clock Frequency Division Ratio Select)
These bits select the frequency division ratio of the reference signal generation clock.
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
CAULVR is a 16-bit readable/writable register that stores the upper-limit value of the frequency.
This register should be set when the CFME bit in CACR0 is 0.
The counter value held in CACNTBR can vary with the difference between the phases of the digital filter and edge-
detection circuit on the one hand and the signal on the CACREF pin on the other, so ensure that this setting allows an
adequate margin.
CALLVR is a 16-bit readable/writable register that stores the lower-limit value of the frequency.
This register should be set when the CFME bit in CACR0 is 0.
The counter value held in CACNTBR can vary with the difference between the phases of the digital filter and edge-
detection circuit on the one hand and the signal on the CACREF pin on the other, so ensure that this setting allows an
adequate margin.
CACNTBR is a 16-bit read-only register that retains the counter value at the time a valid reference signal edge is input.
10.3 Operation
(1) Writing 1 to the CFME bit in CACR0 while the RPS bit in CACR2 is 0 and the CACREFE bit in CACR1 is 1
enables clock-frequency measurement based on the CACREF pin input.
(2) After 1 is written to the CFME bit, the timer starts up-counting when the valid edge selected by the EDGES[1:0]
bits in CACR1 is input from the CACREF pin.
(3) When the next valid edge is input, the counter value is retained in CACNTBR and compared with the values of
CAULVR and CALLVR. If both CACNTBR CAULVR and CACNTBR CALLVR are satisfied, only the
MENDF flag in CASTR is set to 1 because the clock frequency is correct. If the MENDIE bit in CAICR is 1, a
measurement end interrupt will occur.
(4) When the next valid edge is input, the counter value is retained in CACNTBR and compared with the values of
CAULVR and CALLVR. In the case of CACNTBR > CAULVR, the FERRF flag in CASTR is set to 1 because the
clock frequency is erroneous. If the FERRIE bit in CAICR is 1, a frequency error interrupt will occur. Also, the
MENDF flag in CASTR is set to 1. If the MENDIE bit in CAICR is 1, a measurement end interrupt will occur.
(5) When the next valid edge is input, the counter value is retained in CACNTBR and compared with the values of
CAULVR and CALLVR. In the case of CACNTBR < CALLVR, the FERRF flag in CASTR is set to 1 because the
clock frequency is erroneous. If the FERRIE bit in CAICR is 1, a frequency error interrupt will occur. Also, the
MENDF flag in CASTR is set to 1. If the MENDIE bit in CAICR is 1, a measurement end interrupt will occur.
(6) While the CFME bit in CACR0 is 1, the counter value is retained in CACNTBR and compared with the values of
CAULVR and CALLVR every time a valid edge is input. Writing 0 to the CFME bit in CACR0 clears the counter
and stops up-counting.
CACREF pin 1
0
FFFFh
Counter is
After 1 is written to CFME bit, counting cleared by writing
starts at the first valid edge. 0 to CFME bit.
CAULVR
CALLVR
0000h
Time
Figure 10.2 Operating Example of Clock Frequency Accuracy Measurement Circuit Based on CACREF Pin
Input
(1) When 1 is written to the CFME bit in CACR0 with the RPS bit in CACR2 set to 1, clock frequency measurement
based on another clock source is enabled.
(2) After 1 is written to the CFME bit, the timer starts up-counting when the valid edge selected by the EDGES[1:0]
bits in CACR1 is input based on the clock source selected by the RSCS[2:0] bits in CACR2.
(3) When the next valid edge is input, the counter value is retained in CACNTBR and compared with the values of
CAULVR and CALLVR. If both CACNTBR CAULVR and CACNTBR CALLVR are satisfied, only the
MENDF flag in CASTR is set to 1 because the clock frequency is correct. If the MENDIE bit in CAICR is 1, a
measurement end interrupt will occur.
(4) When the next valid edge is input, the counter value is retained in CACNTBR and compared with the values of
CAULVR and CALLVR. In the case of CACNTBR > CAULVR, the FERRF flag in CASTR is set to 1 because the
clock frequency is erroneous. If the FERRIE bit in CAICR is 1, a frequency error interrupt will occur. Also, the
MENDF flag in CASTR is set to 1. If the MENDIE bit in CAICR is 1, a measurement end interrupt will occur.
(5) When the next valid edge is input, the counter value is retained in CACNTBR and compared with the values of
CAULVR and CALLVR. In the case of CACNTBR < CALLVR, the FERRF flag in CASTR is set to 1 because the
clock frequency is erroneous. If the FERRIE bit in CAICR is 1, a frequency error interrupt will occur. Also, the
MENDF flag in CASTR is set to 1. If the MENDIE bit in CAICR is 1, a measurement end interrupt will occur.
(6) While the CFME bit in CACR0 is 1, the counter value is retained in CACNTBR and compared with the values of
CAULVR and CALLVR every time a valid edge is input. Writing 0 to the CFME bit in CACR0 clears the counter
and stops up-counting.
FFFFh
After 1 is written to CFME bit, counting Counter is
starts at the first valid edge. cleared by writing
0 to CFME bit.
CAULVR
CALLVR
0000h
Time
Figure 10.3 Operating Example of Clock Frequency Accuracy Measurement Circuit Based on Another Clock
Source
Table 11.2 Entering and Exiting Low Power Consumption Modes and Operating States in Each Mode
Entering and Exiting Low Power Consumption
Modes and Operating States Sleep Mode All-Module Clock Stop Mode Software Standby Mode
Transition condition Control register + instruction Control register + instruction Control register + instruction
Canceling method other than reset Interrupt Interrupt*1 Interrupt*2
State after cancellation*3 Program execution state Program execution state Program execution state
(interrupt processing) (interrupt processing) (interrupt processing)
Main clock oscillator Operating possible Operating possible Stopped
Sub-clock oscillator Operating possible Operating possible Operating possible*4
High-speed on-chip oscillator Operating possible Operating possible Stopped
Low-speed on-chip oscillator Operating possible Operating possible Stopped
IWDT-dedicated on-chip oscillator Operating possible*5 Operating possible*5 Operating possible*5
CPU Stopped (Retained) Stopped (Retained) Stopped (Retained)
RAM0 Operating possible (Retained) Stopped (Retained) Stopped (Retained)
(0000 0000h to 0000 3FFFh)
Flash memory Operating Stopped (Retained) Stopped (Retained)
Independent watchdog timer (IWDT) Operating possible*5 Operating possible*5 Operating possible*5
Realtime clock (RTC) Operating possible Operating possible Operating possible
8-bit timer (unit 0, unit 1) (TMR) Operating possible Operating possible*6 Stopped (Retained)
Voltage detection circuit (LVD) Operating possible Operating possible Operating possible*7
Power-on reset circuit Operating Operating Operating*7
Peripheral modules Operating possible Stopped (Retained) Stopped (Retained)
I/O ports Operating Retained*8 Retained
“Operating possible” means that operating or stopped can be controlled by the control register setting.
“Stopped (Retained)” means that internal register values are retained and internal operations are suspended.
“Stopped (Undefined)” means that internal register values are undefined and power is not supplied to the internal circuit.
Note 1. “Interrupts” here indicates an external pin interrupt (the NMI or IRQ0 to IRQ7) or any of peripheral interrupts (the 8-bit timer, RTC
alarm, RTC periodic, IWDT, voltage monitoring 1, voltage monitoring 2, and oscillator-stopped detection interrupts).
Note 2. “Interrupts” here indicates an external pin interrupt (the NMI or IRQ0 to IRQ7) or any of peripheral interrupts (the RTC alarm,
RTC periodic, IWDT, voltage monitoring 1, and voltage monitoring 2 interrupts).
Note 3. This does not include release initiated by a reset on the RES# pin, power-on reset, voltage monitoring reset, or independent
watchdog timer reset. The transition is to the reset state when release is initiated by one of these reset sources.
Note 4. Operation or stopping is selected by the sub-clock oscillator control bit (RTCEN) in RTC control register 3 (RCR3).
Note 5. Operation or stopping is selected by setting the IWDT sleep mode count stop control bit (IWDTSLCSTP) in option function select
register 0 (OFS0) in IWDT auto-start mode. In any mode other than IWDT auto-start mode, operation or stopping is selected by
the setting of the sleep mode count stop control bit (SLCSTP) in the IWDT count stop control register (IWDTCSTPR).
Note 6. Stopping or operation is controlled by the module-stop setting bits (MSTPA4 and MSTPA5, respectively) in module stop control
register A (MSTPCRA) for 8-bit timers 0 and 1 (unit 0) and 2 and 3 (unit 1).
Note 7. In the case of a transition to software standby mode when the setting of the software cut bit in the flash HOCO software standby
control register (FHSSBYCR.SOFTCUT2) is 1, the voltage monitoring circuits are stopped and the low power consumption
function of the power-on reset circuit is enabled.
Note 8. While the 8-bit timer and RTC are operated, the related pins continue operation.
SBYCR.SSBY = 0
Reset state
WAIT Sleep mode
RES# pin = High* 4 instruction*1
SBYCR.SSBY = 0
All interrupts MSTPCRA.ACSE = 1
MSTPCRA = FFFF FF[C-F]Fh
MSTPCRB = FFFF FFFFh
Upper 16 bits in MSTPCRC = FFFFh
WAIT instruction*1
Interrupt*3 SBYCR.SSBY = 1
Software standby
mode
Note 1. If an interrupt that becomes a canceling source is accepted while making a transition to the program stop state after the WAIT instruction
has been executed, the transition to the program stop state is canceled and the interrupt exception handling is executed.
Note 2. “Interrupts” here indicates an external pin interrupt (the NMI or IRQ0 to IRQ7) or any of peripheral interrupts (the 8-bit timer, RTC alarm,
RTC periodic, IWDT, voltage monitoring 1, voltage monitoring 2, and oscillator-stopped detection interrupts). However, an 8-bit timer
interrupt is only effective when the value of the corresponding module-stop setting bit (MSTPA4 or MSTPA5, respectively) in module-stop
control register A (MSTPCRA) for 8-bit timer 0 and 1 (unit 0) or 2 and 3 (unit 1) is 0.
Note 3. “Interrupts” here indicates an external pin interrupt (the NMI or IRQ0 to IRQ7) or any of peripheral interrupts (the RTC alarm, RTC periodic,
IWDT, voltage monitoring 1, and voltage monitoring 2 interrupts).
Note 4. The LOCO is the source of the operating clock following a transition from the reset state to normal operating mode.
Note 5. Makes a transition from sleep mode, all-module clock stop mode, or software standby mode to normal operating mode by an interrupt. In
the case of recovery from sleep mode, the clock source for subsequent use is selectable.
For details, see section 11.2.6, Sleep Mode Return Clock Source Switching Register (RSTCKCR). For software standby mode, the clock
source after returning is the same as that before returning.
When a RES# pin reset, power-on reset, voltage monitoring 0 reset, or independent watchdog timer reset is generated in any state, a transition to
the reset state is made.
SSBY — — — — — — — — — — — — — — —
Note: • Set the PRCR.PRC1 bit to 1 (write enabled) before rewriting this register.
b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16
Note: • Set the PRCR.PRC1 bit to 1 (write enabled) before rewriting this register.
b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16
Note: • Set the PRCR.PRC1 bit to 1 (write enabled) before rewriting this register.
b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16
— — — — — — — — — — — — — — — MSTPC
0
Value after reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Note: • Set the PRCR.PRC1 bit to 1 (write enabled) before rewriting this register.
Note 1. The MSTPC0 bit should not be set to 1 during access to the corresponding RAM. The corresponding RAM should not be
accessed while the MSTPC0 bit is set to 1.
Note 2. The MSTPC19 bit should be rewritten while the oscillation of the clock to be controlled by this bit is stable. For entering software
standby mode after rewriting this bit, wait for two cycles of the slowest clock among the clocks output by the oscillators actually
oscillating and execute the WAIT instruction.
b7 b6 b5 b4 b3 b2 b1 b0
— — — OPCM — OPCM[2:0]
TSF
Value after reset: 0 0 0 0 0 0 1 0
Note: • Set the PRCR.PRC1 bit to 1 (write enabled) before rewriting this register.
OPCCR is used to reduce power consumption in normal operating mode, sleep mode, and all-module clock stop mode.
Power consumption can be reduced according to the operating frequency and operating voltage to be used by the OPCCR
setting.
OPCCR should not be modified in the following cases:
When the operating power control transition status flag (OPCMTSF) is 1 (operating power control mode switching
is in progress)
When the ROM P/E mode entry i bit in the flash P/E mode entry register (FENTRYR.FENTRYi) is 1 (ROM P/E
mode, E2 DataFlash P/E mode) (i = 0, D)
Period from the time of WAIT instruction execution for a sleep mode transition, to return from sleep mode to
normal operation
Writing to the ROM while it is being programmed or erased is impossible because write access to the OPCCR register is
not allowed.
For the procedure to use in shifting to an operational power control mode, refer to section 11.5, Function for Lower
Operating Power Consumption.
Table 11.3 shows the operating power control modes along with the operating frequency ranges, operating voltage
ranges, and power consumption.
Table 11.3 Relationship between Operating Power Control Mode, Operating Range, and Power Consumption
Operating Frequency Range
Power Consumption
During Flash
OPCM Operating Memory
Operating Power Control Mode During Flash Memory Read
[2:0] Bits Voltage Range Programming/
Erasure
Middle-speed operating mode 1A 010b 3.6 V to 5.5 V 32 MHz max 32 MHz max 32 MHz max 32 MHz max 4 MHz to 32 MHz Large
1.62 V to 2.7 V 8 MHz max 8 MHz max 8 MHz max 8 MHz max —
Middle-speed operating mode 1B 011b 3.6 V to 5.5 V 32 MHz max 32 MHz max 32 MHz max 32 MHz max —
1.62 V to 2.7 V 8 MHz max 8 MHz max 8 MHz max 8 MHz max 4 MHz to 8 MHz
Low-speed operating mode 1 110b 3.6 V to 5.5 V 8 MHz max 8 MHz max 8 MHz max 8 MHz max —
2.7 V to 3.6 V —
1.8 V to 2.7 V 4 MHz max 4 MHz max 4 MHz max 4 MHz max —
1.62 V to 1.8 V 2 MHz max 2 MHz max 2 MHz max 2 MHz max —
Low-speed operating mode 2 111b 3.6 V to 5.5 V 32.768 kHz max 32.768 kHz max 32.768 kHz max 32.768 kHz max —
2.7 V to 3.6 V —
1.8 V to 2.7 V —
[V] [V]
5.50 5.50
1A
Voltage
Voltage
3.60 3.60
1B
2.70 2.70
1.80 1.80
1.62 1.62
Figure 11.2 Relationship between the Operating Voltages and Operating Frequencies in Middle-Speed
Operating Modes 1A and 1B
[V] [V]
5.50 5.50
Voltage
Voltage
3.60 3.60
P/E disabled
2.70 2.70
1.80 1.80
1.62 1.62
Figure 11.3 Relationship between the Operating Voltages and Operating Frequencies in Low-Speed
Operating Mode 1
Note: • The OPCM[2:0] bits cannot be set to 111b (low-speed operating mode 2) when the HOCOCR.HCSTP bit is 0
(HOCO operated).
Figure 11.4 shows the relationship between the operating voltages and operating frequencies in low-speed operating
mode 2.
[V] [V]
5.50 5.50
Voltage
Voltage
3.60 3.60
P/E disabled
2.70 2.70
1.80 1.80
1.62 1.62
Figure 11.4 Relationship between the Operating Voltages and Operating Frequencies in Low-Speed
Operating Mode 2
b7 b6 b5 b4 b3 b2 b1 b0
RSTCK — — — — RSTCKSEL[2:0]
EN
Value after reset: 0 0 0 0 0 0 0 0
Note: • Set the PRCR.PRC1 bit to 1 (write enabled) before rewriting this register.
b7 b6 b5 b4 b3 b2 b1 b0
— — — MSTS[4:0]
Note: • Set the PRCR.PRC1 bit to 1 (write enabled) before rewriting this register.
MOSCWTCR is used to control the oscillation stabilization wait time of the main clock oscillator.
Transmission of the main clock signal to the LSI internally starts after the number of cycles of the main clock set in the
MOSCWTCR register have been counted.
Set the MSTS[4:0] bits so that the wait time is at least as long as the main clock oscillator stabilization time
(tMAINOSC). For example, if the frequency of the oscillator in use is 10 MHz (so that the period is 100 ns) and the
MSTS[4:0] bits are set to 01101b, the wait time will be 100 ns × 131072 cycles, which is approximately 13.11 ms.
The wait time is not required when the main clock is externally input.
MOSCWTCR can only be rewritten when the MOSCCR.MOSTP bit is 1; do not rewrite MOSCWTCR with other
settings.
b7 b6 b5 b4 b3 b2 b1 b0
— — — SSTS[4:0]
Note: • Set the PRCR.PRC1 bit to 1 (write enabled) before rewriting this register.
SOSCWTCR is used to select the oscillation stabilization wait time of the sub-clock oscillator.
The sub-clock is provided to the LSI internally after the number of sub-clock cycles specified with SOSCWTCR has
been counted.
Set the SSTS[4:0] bits so that the wait time is at least as long as the sub-clock oscillator stabilization time (tSUBOSC).
For example, if the frequency of the oscillator in use is 32.768 kHz (so that the period is 30.5 μs) and the SSTS[4:0] bits
are set to 01101b, the wait time will be 30.5 μs × 32768 cycles, which is approximately 2 s + 1 s = 3 s.
Writing to alter the setting in register SOSCWTCR is only possible when the SOSTP bit in SOSCCR is 1 (sub-clock
oscillator is stopped). Do not attempt to change the setting if this is not the case.
b7 b6 b5 b4 b3 b2 b1 b0
— — — HSTS2[4:0]
Note: • Set the PRCR.PRC1 bit to 1 (write enabled) before rewriting this register.
Note 1. When this value is set, the HOCO oscillation stabilization time 2 (tHOCO2) is established and a clock whose HOCO oscillation
frequency (fHOCO) accuracy is described in the electrical characteristics section is present immediately after the supply of that
clock is started.
The supply of this clock is possible even when a setting that provides a smaller cycle count than this setting is specified. In such
case, however, the HOCO frequency accuracy that is described in the electrical characteristics section is not guaranteed at the
beginning of the supply of the clock because the HOCO oscillation stabilization time 2 (tHOCO2) cannot be established. In either
case, the HOCO frequency accuracy described in the electrical characteristics section is established in the tHOCO2 time after
the beginning of the clock supply.
HOCOWTCR2 is used to select the oscillation stabilization wait time of the HOCO.
The supply of the HOCO clock to the internal LSI is started after the number of HOCO clocks equivalent to the number
of cycles specified in this register are counted.
HOCOWTCR2 can only be rewritten when the HOCOCR.HCSTP bit is 1 (HOCO stopped); do not rewrite
HOCOWTCR2 with other settings.
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — SOFTCUT[2:0]
Note: • Set the PRCR.PRC1 bit to 1 (write enabled) before rewriting this register.
To use the voltage detection circuit (LVD) in software standby mode, set the SOFTCUT[2] bit to 0. To stop the voltage
detection circuit (LVD) for reducing power consumption and enable the low power consumption function of the power-
on reset circuit, set the SOFTCUT[2] bit to 1.
(1) Switching from Normal Power Consumption Mode to Low Power Consumption Mode
Example: From middle-speed operating mode 1A to low-speed operating mode 1
(High-speed operation in the operating power control mode used before mode-switching)
↓
Set to switch from the HOCO clock to the LOCO clock (clock source and frequency division ratio)
↓
Write to OPCCR
↓
Confirm that the OPCCR.OPCMTSF flag is 0
↓
(Low-speed operation in the switched operating power control mode)
(2) Switching from Low Power Consumption Mode to Normal Power Consumption Mode
Example: From low-speed operating mode 2 to middle-speed operating mode 1A
(Low-speed operation in the operating power control mode used before mode-switching)
↓
Write to OPCCR
↓
Confirm that the OPCCR.OPCMTSF flag is 0
↓
Set to switch from the LOCO clock to the HOCO clock (clock source and frequency division ratio)
↓
(High-speed operation in the switched operating power control mode)
The method described below can be used to shorten the time taken by transitions between modes.
In cases where the transition is from a mode with higher to a mode with lower power consumption, the transition
takes the shortest time when the system clock is set to the value for the highest available frequency after the
transition.
In cases where the transition is from a mode with lower to a mode with higher power consumption, the transition
also takes the shortest time when the system clock is set to the value for the highest available frequency before the
transition.
Note 1. The MSTPCRA.MSTPA4 and MSTPA5 bits select operation or stop of these modules.
Note 2. Transitions to all-module clock stop mode are not to be made in some states of DTC or DMAC operations.
Before setting the MSTPCRA.MSTPA28 bit to 1, clear the DMAST.DMST bit of the DMAC and the
DTCST.DTCST bit of the DTC so that the DTC and DMAC are not activated.
Note 3. For details, see section 2, CPU.
Note 4. For details, see section 14, Interrupt Controller (ICUb).
Note 5. When a POE interrupt source condition is satisfied while the setting to enable POE interrupts is in place,
recovery from all-module clock stop mode does not proceed but the flag to indicate satisfaction of the source
condition is retained. If a different source leads to recovery from all-module clock stop mode in this situation, a
POE interrupt is generated after recovery.
Note 1. The MSTPA4 and MSTPA5 bits of MSTPCRA select operation or stopping of these modules.
Note 2. If a condition for the independent watchdog timer to stop counting applied (OFS0.IWDTSTRT = 0 and
OFS0.IWDTSLCSTP = 1, or OFS0.IWDTSTRT = 1 and IWDTCSTPR.SLCSTP = 1) at the time of a transition to
all-module clock stop mode, using a reset from the independent watchdog timer to release the chip from all-
module clock stop mode is impossible because the independent watchdog timer is stopped.
Note 3. For details, see section 14, Interrupt Controller (ICUb).
Note 4. For details, see section 2, CPU.
In software standby mode, when 000b is set to the FHSSBYCR.SOFTCUT[2:0] bits, internal power supply to the high-
speed on-chip oscillator and the power-on reset circuit continues. Since power supply start-up stabilization time is not
required at resumption, resumption time from software standby mode is quicker compared to other modes.
When 010b is set to the SOFTCUT[2:0] bits, power supply to the high-speed on-chip oscillator stops, and low power
consumption function of the internal power supply is enabled, so the current consumption is reduced.
When 100b is set to the SOFTCUT[2:0] bits, the voltage detection circuit (LVD) stops and the low power consumption
function of the power-on reset circuit is enabled, so the current consumption is reduced. At this time, the voltage
detection characteristics of the power-on reset circuit is changed. For details, refer to section 38, Electrical
Characteristics.
When 110b is set to the SOFTCUT[2:0] bits, power supply to the high-speed on-chip oscillator stops and the low power
consumption function of the internal power supply is enabled. Furthermore, the voltage detection circuit (LVD) stops and
the low power consumption function of the power-on reset circuit is enabled, so the current consumption is significantly
reduced. At this time, the voltage detection characteristics of the power-on reset circuit is changed. For details, refer to
section 38, Electrical Characteristics.
When the high-speed on-chip oscillator is not used, the power supply can be turned off with HOCOPCR.HOCOPCNT
settings, so the current consumption is reduced even more. For details, refer to section 9, Clock Generation Circuit.
Clear the DMAST.DMST bit of the DMAC and the DTCST.DTCST bit of the DTC to 0 before executing the WAIT
instruction.
Counting by the IWDT stops if a transition to software standby mode is made while the IWDT is being used in auto-start
mode and the OFS0.IWDTSLCSTP bit is 1. In the same way, counting by the IWDT stops if a transition to software
standby mode is made while the IWDT is being used in register start mode and the SLCSTP bit in IWDTCSTPR is 1.
Furthermore, counting by the IWDT continues if a transition to software standby mode is made while the IWDT is being
used in auto-start mode and the OFS0.IWDTSLCSTP bit is 0 (counting by the IWDT continues through transitions to
low power consumption modes). In the same way, counting by the IWDT continues if a transition to software standby
mode is made while the IWDT is being used in register start mode and the SLCSTP bit in IWDTCSTPR is 0.
When the oscillation stop detection function is enabled (OSTDCR.OSTDE = 1), software standby mode cannot be
entered. To make a transition to software standby mode, execute a WAIT instruction after disabling the oscillation stop
detection function (OSTDCR.OSTDE = 0).
To use software standby mode, make the following settings and then execute a WAIT instruction.
(1) Clear the PSW.I bit*1 of the CPU to 0.
(2) Set the interrupt destination to be used for recovery from software standby mode to the CPU.
(3) Set the priority*2 of the interrupt to be used for recovery from software standby mode to a level higher than the
setting of the PSW.IPL[3:0] bits*1 of the CPU.
(4) Set the IERm.IENj bit*2 for the interrupt to be used for recovery from software standby mode to 1.
(5) For the last I/O register to which writing proceeded, read the register to confirm that the value written has been
reflected.
(6) Execute a WAIT instruction (executing a WAIT instruction causes automatic setting of the PSW.I bit*1 of the CPU
to 1).
Oscillator
ICLK
IRQn pin
SSBY
11.7.8 Point for Caution when Using the Sub-Clock as the Source of the System Clock
If the sub-clock is in use as the source of the system clock, make sure that the RTC or the low-speed clock oscillator is
operating (by setting the RCR3.RTCEN = 1 or the LOCOCR.LCSTP = 0, respectively) for a transition to software
standby mode.
Reset
Non-maskable interrupt
Interrupt
Unconditional trap
13.1.3 Reset
A reset is generated by input of a reset signal to the CPU. This has the highest priority of any exception and is always
accepted.
13.1.5 Interrupt
Interrupts are generated by the input of interrupt signals to the CPU. A fast interrupt can be selected as the interrupt with
the highest priority. In the case of the fast interrupt, hardware pre-processing and hardware post-processing are handled
fast. The priority level of the fast interrupt is 15 (the highest). The exception handling of interrupts is masked when the I
bit in PSW is 0.
Generation of
exception event
Hardware post-processing
When an exception is accepted, hardware processing by the RX CPU is followed by access to the vector to acquire the
address of the branch destination. In the vector, a vector address is allocated to each exception, and the branch destination
address of the exception handling routine is written to each vector address.
Hardware pre-processing by the RX CPU handles saving of the contents of the program counter (PC) and processor
status word (PSW). In the case of a fast interrupt, the contents are saved in the backup PC (BPC) and the backup PSW
(BPSW), respectively. In the case of exceptions other than a fast interrupt, the contents are saved in the stack area.
General purpose registers and control registers other than the PC and PSW that are to be used within the exception
handling routine must be saved on the stack by a user program at the start of the exception handling routine.
On completion of processing by an exception handling routine, registers saved on the stack are restored and the RTE
instruction is executed to restore execution from the exception handling routine to the original program. For return from
a fast interrupt, the RTFI instruction is used instead. In the case of a non-maskable interrupt, however, finish the program
or reset the system without returning to the original program.
Hardware post-processing by the RX CPU handles restoration of the contents of PC and PSW. In the case of a fast
interrupt, the values of BPC and BPSW are restored to PC and PSW, respectively. In the case of exceptions other than a
fast interrupt, the values are restored from the stack to PC and PSW.
13.3.2 Vector and Site for Saving the Values in the PC and PSW
The vector for each type of exception and the site for saving the values of the program counter (PC) and processor status
word (PSW) are listed in Table 13.2.
Table 13.2 Vector and Site for Saving the Values in the PC and PSW
Exception Vector Site for Saving the Values in the PC and PSW
Undefined instruction exception Fixed vector table Stack
Privileged instruction exception Fixed vector table Stack
Reset Fixed vector table Nowhere
Non-maskable interrupt Fixed vector table Stack
Interrupt Fast interrupt FINTV BPC and BPSW
Other than above Relocatable vector table (INTB) Stack
Unconditional trap Relocatable vector table (INTB) Stack
(c) Saving PC
For a fast interrupt
PC BPC
For exceptions other than a fast interrupt
PC Stack
(b) Restoring PC
For a fast interrupt
BPC PC
For exceptions other than a fast interrupt
Stack PC
13.5.3 Reset
1. The control registers are initialized.
2. The vector is fetched from address FFFF FFFCh.
3. The fetched vector is set to the PC.
13.5.5 Interrupt
1. The value of the processor status word (PSW) is saved on the stack (ISP) or, for the fast interrupt, in the backup
PSW (BPSW).
2. The processor mode select bit (PM), the stack pointer select bit (U), and the interrupt enable bit (I) in PSW are
cleared to 0.
3. If the interrupt was generated during the execution of an RMPA, SCMPU, SMOVB, SMOVF, SMOVU, SSTR,
SUNTIL, or SWHILE instruction, the value of the program counter (PC) for that instruction is saved. For other
instructions, the PC value of the next instruction is saved. Saving of the PC is in the backup PC (BPC) for fast
interrupts.
4. The processor interrupt priority level bits (IPL[3:0]) in PSW indicate the interrupt priority level of the interrupt.
5. The vector for an interrupt source other than the fast interrupt is fetched from the relocatable vector table. For the
fast interrupt, the address is fetched from the fast interrupt vector register (FINTV).
6. The fetched vector is set to the PC and processing branches to the exception handling routine.
Note 1. For the DTC and DMAC activation sources, refer to Table 14.3, Interrupt Vector Table.
Interrupt controller
Clock
Voltage monitoring 2 interrupt
Voltage monitoring 1 interrupt generation
Clock restoration request
IWDT underflow/refresh error
Clock
circuit
Oscillation stop detection interrupt NMI
SR restoration
NMI pin Digital filter Detection
judgment
CPU
Clock restoration enable level
Interrupt request
CPU priority level
IR clear Interrupt acceptance
IRQFL IRQFL IRQCR IER cntl judgment
TE0 TC0
NMIER : Non-maskable interrupt enable register IR : Interrupt request register IRQFLTE0 : IRQ pin digital filter enable register 0
NMICR : NMI pin interrupt control register IER : Interrupt request enable register IRQFLTC0 : IRQ pin digital filter setting register 0
NMICLR : Non-maskable interrupt status clear register IPR : Interrupt source priority register NMIFLTE : NMI pin digital filter enable register
NMISR : Non-maskable interrupt status register FIR : Fast interrupt set register NMIFLTC : NMI pin digital filter setting register
IRQCR : IRQ control register DTCER : DTC activation enable register
DMRSR : DMAC activation request select register
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — — IR
Note 1. For an edge detection interrupt, only 0 can be written to this bit; do not write 1.
For a level detection interrupt, neither 0 nor 1 can be written.
IRn is provided for each interrupt source, where “n” indicates the interrupt vector number.
For the correspondence between interrupt sources and interrupt vector numbers, see Table 14.3, Interrupt Vector
Table.
When level detection has been selected for an IRQi pin, the interrupt request is withdrawn by driving the IRQi pin high.
Do not write 0 or 1 to the IR flag while level detection is selected.
b7 b6 b5 b4 b3 b2 b1 b0
Note: • Write 0 to the bit that corresponds to the vector number for reservation. These bits are read as 0.
b7 b6 b5 b4 b3 b2 b1 b0
— — — — IPR[3:0]
Note 1. When the interrupt is specified as a fast interrupt, it can be issued even if the priority level is level 0.
For the correspondence between interrupt sources and IPRn registers, see Table 14.3, Interrupt Vector Table.
FIEN — — — — — — — FVCT[7:0]
The fast interrupt function based on the FIR register setting is applicable only to interrupts to the CPU. It will not affect
any transfer request to the DTC or DMAC.
Before writing to this register, be sure to disable interrupt requests (IERm.IENj bit = 0).
For details on the fast interrupt, see section 13, Exception Handling, and section 14.4.6, Fast Interrupt.
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — — SWINT
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — — DTCE
An interrupt source that has been selected as a source for DMAC activation should not be specified as a source for DTC
activation. See Table 14.3, Interrupt Vector Table, for the interrupt sources that are selectable as sources for DTC
activation.
Address(es): DMRSR0 0008 7400h, DMRSR1 0008 7404h, DMRSR2 0008 7408h, DMRSR3 0008 740Ch
b7 b6 b5 b4 b3 b2 b1 b0
DMRS[7:0]
To specify the same interrupt source for multiple DMRSRm registers is disabled. The interrupt source that has been
selected for the DMRSRm activation should not be specified as the source for the DTC activation. Otherwise, the correct
operation is not guaranteed.
b7 b6 b5 b4 b3 b2 b1 b0
— — — — IRQMD[1:0] — —
Only change the settings of this register while the corresponding interrupt request enable bit is prohibiting the interrupt
request (IENj bit in IERm is 0). After changing the setting, clear the IR flag in IRn before setting the interrupt enable bit.
However, when the change is to the low level, the IR flag does not require clearing.
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
The NMISR register monitors the status of a non-maskable interrupt source. Writing to the NMISR register is ignored.
The setting in the non-maskable interrupt enable register (NMIER) does not affect the status flags in NMISR.
Before the end of the non-maskable interrupt handler, read the NMISR register and confirm the generation status of other
non-maskable interrupts. Be sure to confirm that all of the bits in the NMISR register are set to 0 before the end of the
handler.
When the IWDT underflow/refresh error interrupt is generated while this interrupt is enabled at its source.
[Clearing condition]
When 1 is written to the NMICLR.IWDTCLR bit
b7 b6 b5 b4 b3 b2 b1 b0
Note 1. A 1 can be written to this bit only once, and subsequent write accesses are no longer enabled.
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
— — — — NMIMD — — —
Change the setting of the NMICR register before the NMI pin interrupt is enabled (before setting the NMIER.NMIEN bit
to 1).
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — — NFLTE
N
Value after reset: 0 0 0 0 0 0 0 0
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — NFCLKSEL[1:0]
Item Description
Source of interrupt request Name of the source for generation of the interrupt request
generation
Name Name of the interrupt
Vector no. Vector number for the interrupt
Vector address offset Value of the offset from the base address for the vector table
Form of interrupt detection “Edge” or “level” as the method for detection of the interrupt
CPU interrupt “○” in this column indicates usability as a CPU interrupt.
DTC activation “○” in this column indicates usability as a request for DTC activation.
DMAC activation “○” in this column indicates usability as a request for DMAC activation.
sstb return “○” in this column indicates usability as a request for return from software-standby mode.
sacs return “○” in this column indicates usability as a request for return from all-module clock-stop mode.
IER Name of the interrupt request enable register (IER) and bit corresponding to the vector number
IPR Name of the interrupt source priority register (IPR) corresponding to the interrupt source
DTCER Name of the DTC activation enable register (DTCER) corresponding to the DTC activation source
sacs Return
sstb Return
Source of
Interrupt Vector Form of
DMAC
Request Vector Address Interrupt
CPU
DTC
Generation Name No.*1 Offset Detection IER IPR DTCER
— For an 0 0000h — × × × × × — — —
unconditional trap
— For an 1 0004h — × × × × × — — —
unconditional trap
— For an 2 0008h — × × × × × — — —
unconditional trap
— For an 3 000Ch — × × × × × — — —
unconditional trap
— For an 4 0010h — × × × × × — — —
unconditional trap
— For an 5 0014h — × × × × × — — —
unconditional trap
— For an 6 0018h — × × × × × — — —
unconditional trap
— For an 7 001Ch — × × × × × — — —
unconditional trap
— For an 8 0020h — × × × × × — — —
unconditional trap
— For an 9 0024h — × × × × × — — —
unconditional trap
— For an 10 0028h — × × × × × — — —
unconditional trap
— For an 11 002Ch — × × × × × — — —
unconditional trap
— For an 12 0030h — × × × × × — — —
unconditional trap
— For an 13 0034h — × × × × × — — —
unconditional trap
— For an 14 0038h — × × × × × — — —
unconditional trap
— For an 15 003Ch — × × × × × — — —
unconditional trap
— Reserved 17 0044h — × × × × × — — —
— Reserved 18 0048h — × × × × × — — —
— Reserved 19 004Ch — × × × × × — — —
— Reserved 20 0050h — × × × × × — — —
— Reserved 22 0058h — × × × × × — — —
— Reserved 24 0060h — × × × × × — — —
— Reserved 25 0064h — × × × × × — — —
— Reserved 26 0068h — × × × × × — — —
— Reserved 35 008Ch — × × × × × — — —
— Reserved 36 0090h — × × × × × — — —
— Reserved 37 0094h — × × × × × — — —
— Reserved 38 0098h — × × × × × — — —
sacs Return
sstb Return
Source of
Interrupt Vector Form of
DMAC
Request Vector Address Interrupt
CPU
DTC
Generation Name No.*1 Offset Detection IER IPR DTCER
— Reserved 39 009Ch — × × × × × — — —
— Reserved 40 00A0h — × × × × × — — —
— Reserved 41 00A4h — × × × × × — — —
— Reserved 42 00A8h — × × × × × — — —
— Reserved 43 00ACh — × × × × × — — —
— Reserved 48 00C0h — × × × × × — — —
— Reserved 49 00C4h — × × × × × — — —
— Reserved 50 00C8h — × × × × × — — —
— Reserved 51 00CCh — × × × × × — — —
— Reserved 52 00D0h — × × × × × — — —
— Reserved 53 00D4h — × × × × × — — —
— Reserved 54 00D8h — × × × × × — — —
— Reserved 55 00DCh — × × × × × — — —
— Reserved 56 00E0h — × × × × × — — —
— Reserved 58 00E8h — × × × × × — — —
— Reserved 59 00ECh — × × × × × — — —
— Reserved 60 00F0h — × × × × × — — —
— Reserved 61 00F4h — × × × × × — — —
— Reserved 62 00F8h — × × × × × — — —
— Reserved 72 0120h — × × × × × — — —
— Reserved 73 0124h — × × × × × — — —
— Reserved 74 0128h — × × × × × — — —
— Reserved 75 012Ch — × × × × × — — —
— Reserved 76 0130h — × × × × × — — —
— Reserved 77 0134h — × × × × × — — —
— Reserved 78 0138h — × × × × × — — —
— Reserved 79 013Ch — × × × × × — — —
— Reserved 80 0140h — × × × × × — — —
— Reserved 81 0144h — × × × × × — — —
— Reserved 82 0148h — × × × × × — — —
— Reserved 83 014Ch — × × × × × — — —
— Reserved 84 0150h — × × × × × — — —
— Reserved 85 0154h — × × × × × — — —
sacs Return
sstb Return
Source of
Interrupt Vector Form of
DMAC
Request Vector Address Interrupt
CPU
DTC
Generation Name No.*1 Offset Detection IER IPR DTCER
— Reserved 86 0158h — × × × × × — — —
— Reserved 87 015Ch — × × × × × — — —
— Reserved 90 0168h — × × × × × — — —
— Reserved 91 016Ch — × × × × × — — —
— Reserved 94 0178h — × × × × × — — —
— Reserved 95 017Ch — × × × × × — — —
— Reserved 96 0180h — × × × × × — — —
— Reserved 97 0184h — × × × × × — — —
— Reserved 98 0188h — × × × × × — — —
— Reserved 99 018Ch — × × × × × — — —
sacs Return
sstb Return
Source of
Interrupt Vector Form of
DMAC
Request Vector Address Interrupt
CPU
DTC
Generation Name No.*1 Offset Detection IER IPR DTCER
sacs Return
sstb Return
Source of
Interrupt Vector Form of
DMAC
Request Vector Address Interrupt
CPU
DTC
Generation Name No.*1 Offset Detection IER IPR DTCER
sacs Return
sstb Return
Source of
Interrupt Vector Form of
DMAC
Request Vector Address Interrupt
CPU
DTC
Generation Name No.*1 Offset Detection IER IPR DTCER
Peripheral clock
Interrupt signal
System clock
IRn.IR flag
*1 *2
Note 1. One of the following requests is issued: CPU interrupt request, DTC activation request, and DMAC activation
request. For details of the setting, see section 14.4.3, Selecting Interrupt Request Destinations.
Note 2. When the CPU interrupt request is specified, this flag is set to 0 on acceptance of a CPU interrupt. For the timing of
0 setting at the DTC activation or DMAC activation, see Table 14.4 Operation at DMAC/DTC Activation.
Figure 14.3 to Figure 14.6 show the interrupt signals of the interrupt controller. Note that the timings of the interrupts
with interrupt vector numbers 64 to 95 are different from those of other interrupts. For the IRQ pin interrupts with
interrupt vector numbers 64 to 79, “internal delay + 2 PCLK cycles” of delay is added after the IRQ pin input. For the
interrupts with interrupt vector numbers 80 to 95, “2 PCLK cycles” of delay is added.
If an interrupt signal is generated every clock cycle, the subsequent interrupts cannot be detected; secure two or more
clock cycles of the system clock or peripheral clock, whichever is slower, between issuance of continuous interrupt
requests.
Interrupt signal
System clock
IRn.IR flag
Figure 14.3 Interval Required between Issuance of Continuous Interrupt Requests (when the Frequency of
System Clock is Slower than that of the Peripheral Clock)
While the IRn.IR flag is 1 after an interrupt request is generated, the interrupt request that is generated again will be
ignored.*1
Figure 14.4 shows the timing for IRn.IR flag re-setting.
Note 1. When the transmission or reception interrupt of the SCI, RSPI, or RIIC is generated with the IRn.IR flag being 1,
the interrupt request is retained. After the IRn.IR flag is cleared to 0, the IRn.IR flag is set to 1 again by the
retained request. For details, see descriptions of the interrupts in section 27, Serial Communications Interface
(SCIe, SCIf), section 29, I2C Bus Interface (RIIC), and section 30, Serial Peripheral Interface (RSPI).
IRn.IR flag
If an interrupt is disabled after the IRn.IR flag is set to 1 (output of the interrupt request is disabled by the interrupt enable
bit of the relevant peripheral module), the IRn.IR flag is not affected but retains its state. Figure 14.5 shows operation
when the interrupt is disabled.
Interrupt Signal
IRn.IR flag
Figure 14.5 Relationship between IRn.IR Flag Operation and Disabling of Interrupt Request
Interrupt signal
System clock
IRn.IR flag
Figure 14.7 shows the procedure for handling level detection interrupts.
IRn.IR = 1
Confirm IRn.IR flag
IRn.IR = 0
When an interrupt request that is enabled at the corresponding source is generated, the corresponding IRn.IR flag is set to 1.
Setting the IERm.IENj bit to enable an interrupt request allows the interrupt request for which the corresponding IRn.IR
is 1 to be output to the interrupt request destination. Setting the IERm.IENj bit to disable an interrupt request suspends
the output of the interrupt request for which the corresponding IRn.IR is 1.
The IRn.IR flag is not affected by the IERm.IENj bit.
Note 1. To disable the transmission or reception interrupt of the SCI, RSPI, or RIIC from the enabled state, clear the
IRn.IR flag to 0 using the above procedure. For details, see descriptions of the interrupts in section 27, Serial
Communications Interface (SCIe, SCIf), section 29, I2C Bus Interface (RIIC), and section 30, Serial Peripheral
Interface (RSPI).
Note 1. Do not set a DTC activation enable bit (DTCERn.DTCE) and a DMAC activation request select register
(DMRSRm) to select the same source. Do not select the same source in more than one DMRSRm register.
Table 14.4 shows operation when the DTC or the DMAC is the request destination.
DISEL for the DMAC is set by the DMACm.DMCSL.DISEL bit; DISEL for the DTC is set by the DTC.MRB.DISEL bit.
Note 1. When the IRn.IR flag is 1, an interrupt request (DTC or DMAC activation request) that is generated again will be ignored.
Note 2. When the DISEL bit is 0, operation with the remaining number of transfer operations being 0 differs according to whether the
source is for DTC or DMAC.
Note 3. For chain transfer, DTC transfer continues until the last chain transfer ends. Whether a CPU interrupt is generated at the end of
chain transfer, the IRn.IR flag clear timing, and the interrupt request destination after transfer are determined by the state of DISEL
and the remaining transfer count at the end of chain transfer. For the chain transfer, see Table 17.3, Chain Transfer Conditions in
section 17, Data Transfer Controller (DTCa).
The request destination for an interrupt should be changed while the IERm.IENj bit is 0.
When a source is to be changed to an interrupt request or the DMA activation source is to be changed while a transfer is
not complete (i.e. while the DMACm.DMCNT.DTE bit has not been cleared) after the settings described under (1)
DMAC Activation have been made, follow the procedure below.
1. For both the source to be withdrawn and the source that will have a new target for activation, clear the IENj bits in
IERm to 0.
2. Check the state of transfer by the DMAC. If transfer is in progress, wait for its completion.
3. Make the settings described under (1) DMAC Activation.
When a source is to be changed to an interrupt request or the DTC transfer information is to be changed while a transfer
is not complete (i.e. while the DTCERn.DTCE bit has not been cleared) after the settings described under (2) DTC
Activation have been made, follow the procedure below.
1. For both the source to be withdrawn and the source that will have a new target for activation, clear the IENj bits in
IERm to 0.
2. Check the state of transfer by the DTC. If transfer is in progress, wait for its completion.
3. Make the settings described under (2) DTC Activation.
(1) Determining Priority when the CPU is the Request Destination of the Interrupt
A source selected for the fast interrupt has the highest priority. After that, an interrupt source with a larger value of the
interrupt priority level select bits (IPR[3:0]) in IPRn takes priority. If interrupts with the same priority level are generated
by multiple sources, the source with the smallest vector number takes precedence.
(2) Determining Priority when the DTC is the Request Destination of the Interrupt
The IPR[3:0] bits in IPRn have no effect. An interrupt source with a smaller vector number takes precedence.
(3) Determining Priority when the DMAC is the Request Destination of the Interrupt
The IPR[3:0] bits in IPRn have no effect. Regarding the order of priority of DMAC channels, see section 16, DMA
Controller (DMACA).
Sampling clock
for digital filter
IRQFLTE0.FLTENi bit
Pulses removed
IRn.IR flag
Before software standby mode is entered, set the IRQFLTE0.FLTENi and NMIFLTE.NFLTEN bits to 0 (digital filter
disabled). To use the digital filter again after return from software standby mode, set the IRQFLTE0.FLTENi or
NMIFLTE.NFLTEN bit to 1 (digital filter enabled).
After 1 is written to the NMIER register, subsequent write access to the NMIEN bit in NMIER is ignored. The NMI
interrupt cannot be disabled. It can be disabled only by a reset.
For the flow of non-maskable interrupt processing, see section 13, Exception Handling.
Writing 1 to the NMICLR.NMICLR bit clears the NMI status flag (NMISR.NMIST) to 0.
Writing 1 to the NMICLR.OSTCLR bit clears the oscillation stop detection interrupt status flag (NMISR.OSTST) to 0.
Writing 1 to the NMICLR.IWDTCLR bit clears the IWDT underflow/refresh error status flag (NMISR.IWDTST) to 0.
Writing 1 to the NMICLR.LVD1CLR bit clears the voltage monitoring 1 interrupt status flag (NMISR.LVD1ST) to 0.
Writing 1 to the NMICLR.LVD2CLR bit clears the voltage monitoring 2 interrupt status flag (NMISR.LVD2ST) to 0.
Interrupt requests through the IRQ pins that do not satisfy the above conditions are not detected while the clock is
stopped in software standby mode.
Non-maskable interrupts
Use the NMIER register to enable the given interrupt request.
15. Buses
15.1 Overview
Table 15.1 lists the bus specifications, Figure 15.1 shows the bus configuration, and Table 15.2 lists the addresses
assigned for each bus.
Note 1. The peripheral module clock used as the operating clock is PCLKD for S12AD.
P/E: Programming/Erasure
ICLK synchronization
CPU
Instruction bus
Operand bus
On-chip
RAM
ROM
DTC/
DMAC (m)
Internal peripheral
bus 1
Internal peripheral bus 2 Internal peripheral bus 6
Peripheral DTC/
module DMAC (s) E2
Peripheral Peripheral
••• ROM (P/E) DataFlash
module module
memory
Note: • The solid arrows indicate the directions of the access being requested of the bus master .
Note: • DTC/DMAC (m) is used for bus mastership, while DTC/DMAC (s) is for register access.
Requests for bus mastership from the CPU (internal main bus 1) and other bus masters (internal main bus 2) are
arbitrated through internal peripheral buses 1, 2, and 6.
The priority order of two internal main buses can be set using the bus priority control register (BUSPRI). The priority
order can be set with the internal peripheral bus 1 priority control bits (BUSPRI.BPIB[1:0]), internal peripheral bus 2 and
3 priority control bits (BUSPRI.BPGB[1:0]), and internal peripheral bus 6 priority control bits (BUSPRI.BPFB[1:0]) for
the corresponding internal peripheral buses. When the priority order is fixed, internal main bus 2 has priority over
internal main bus 1. When the priority order is toggled, a bus has a lower priority when the request of that bus is
accepted.
The order of accepting requests may change depending on the BUSPRI setting (Refer to Figure 15.2).
Internal main bus 1 (R11) (R11) (R11) R11 R12 (R13) (R13) R13
>
>
Internal main bus 2 R21 R22 R23 R24 R25
(1), (2) : The priority order does not change because the priority of the accepted request is low.
No request issued
ROM access
CPU instruction ROM ROM ROM ROM ROM ROM ROM
fetching
RAM access
15.2.7 Restrictions
(1) Prohibition of Access that Spans Multiple Areas of Address Space
Single access that spans two areas of the address space is prohibited, and operation of such an access is not guaranteed.
Ensure that a single word or long-word access does not span across two areas by crossing address space area boundaries.
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — — STSCL
R
Value after reset: 0 0 0 0 0 0 0 0
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — — IGAEN
b7 b6 b5 b4 b3 b2 b1 b0
— MST[2:0] — — — IA
ADDR[12:0] — — —
Note 1. These bits can be written to only once while the DTC and DMAC are stopped. When they are written to more than one time, the
operation is not guaranteed.
16.1 Overview
Table 16.1 lists the specifications of the DMAC, and Figure 16.1 shows a block diagram of the DMAC.
Note 1. For details on DMAC activation sources, see Table 14.3, Interrupt Vector Table in section 14, Interrupt Controller (ICUb).
DMAC
Activation control DMAC registers
DMAC channels
(CH0 to CH3)
DMA
DMA start transfer DMSAR
4
request request DMDAR
arbitration DMCRA
DMCRB
DMOFR
Interrupt DMTMD
controller DMAMD
DMSTS
DMCNT
DMAC 4
response
Interrupt 4
request
Register control
DMAC response
control
DMAC core
Source address DMAC
Destination address control
Transfer counter circuit
Block counter
Transfer mode
Bus interface
Internal peripheral
bus interface 1
Internal main bus 2
Address(es): DMAC0.DMSAR 0008 2000h, DMAC1.DMSAR 0008 2040h, DMAC2.DMSAR 0008 2080h, DMAC3.DMSAR 0008 20C0h
b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16
Set DMSAR while DMAC activation is disabled (the DMST bit in DMAST = 0) or DMA transfer is disabled (the DTE
bit in DMCNT = 0).
Setting bits 31 to 29 is invalid; a value of bit 28 is extended to bits 31 to 29. Reading DMSAR returns the extended value.
Address(es): DMAC0.DMDAR 0008 2004h, DMAC1.DMDAR 0008 2044h, DMAC2.DMDAR 0008 2084h, DMAC3.DMDAR 0008 20C4h
b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16
DMDAR specifies the start address of the transfer destination. Set DMDAR while DMAC activation is disabled (the
DMST bit in DMAST = 0) or DMA transfer is disabled (the DTE bit in DMCNT = 0).
Setting bits 31 to 29 is invalid; a value of bit 28 is extended to bits 31 to 29. Reading DMDAR returns the extended
value.
Address(es): DMAC0.DMCRA 0008 2008h, DMAC1.DMCRA 0008 2048h, DMAC2.DMCRA 0008 2088h, DMAC3.DMCRA 0008 20C8h
DMCRAH
b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16
— — — — — —
DMCRAL
DMCRAH
b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16
— — — — — —
DMCRAL
0 0 0 0 0 0
Note: • Set the same value for DMCRAH and DMCRAL in repeat transfer mode and block transfer mode.
Address(es): DMAC0.DMCRB 0008 200Ch, DMAC1.DMCRB 0008 204Ch, DMAC2.DMCRB 0008 208Ch, DMAC3.DMCRB 0008 20CCh
— — — — — —
DMCRB specifies the number of block transfer operations and repeat transfer operations in block and repeat transfer
mode, respectively.
The number of transfer operations is one when the setting is 001h, 1023 when it is 3FFh, and 1024 when it is 000h.
In repeat transfer mode, the value is decremented by one when the final data of one repeat size is transferred.
In block transfer mode, the value is decremented by one when the final data of one block size is transferred.
In normal transfer mode, DMCRB is not used. The setting is invalid.
Address(es): DMAC0.DMTMD 0008 2010h, DMAC1.DMTMD 0008 2050h, DMAC2.DMTMD 0008 2090h, DMAC3.DMTMD 0008 20D0h
Note 1. DMAC activation source is selected using the DMRSRm registers of the ICU. For details on DMAC activation sources, see Table
14.3, Interrupt Vector Table in section 14, Interrupt Controller (ICUb).
Address(es): DMAC0.DMINT 0008 2013h, DMAC1.DMINT 0008 2053h, DMAC2.DMINT 0008 2093h, DMAC3.DMINT 0008 20D3h
b7 b6 b5 b4 b3 b2 b1 b0
DARIE Bit (Destination Address Extended Repeat Area Overflow Interrupt Enable)
When an extended repeat area overflow on the destination address occurs while this bit is set to 1, the DTE bit in
DMCNT is cleared to 0. At the same time, the ESIF flag in DMSTS is set to 1 to indicate that an interrupt by an extended
repeat area overflow on the destination address is requested.
When block transfer mode is used with the extended repeat area function, an interrupt is requested after completion of a
1-block size transfer. When setting 1 in the DTE bit in DMACm.DMCNT of the channel for which a transfer has been
stopped, the transfer is resumed from the state when the transfer is stopped.
When the extended repeat area is not specified for the destination address, this bit is ignored.
SARIE Bit (Source Address Extended Repeat Area Overflow Interrupt Enable)
When an extended repeat area overflow on the source address occurs while this bit is set to 1, the DTE bit in DMCNT is
cleared to 0. At the same time, the ESIF flag in DMSTS is set to 1 to indicate that an interrupt by an extended repeat area
overflow on the source address is requested.
When block transfer mode is used with the extended repeat area function, an interrupt is requested after completion of a
1-block size transfer. When setting 1 in the DTE bit in DMACm.DMCNT of the channel for which a transfer has been
stopped, the transfer is resumed from the state when the transfer is stopped.
When the extended repeat area is not specified for the source address, this bit is ignored.
Address(es): DMAC0.DMAMD 0008 2014h, DMAC1.DMAMD 0008 2054h, DMAC2.DMAMD 0008 2094h, DMAC3.DMAMD 0008 20D4h
b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16
Write to this register while the DMAC operation is stopped or DMA transfer is disabled (not during data transfer).
Setting bits 31 to 25 is invalid; a value of bit 24 is extended to bits 31 to 25. Reading DMOFR returns the extended value.
Address(es): DMAC0.DMCNT 0008 201Ch, DMAC1.DMCNT 0008 205Ch, DMAC2.DMCNT 0008 209Ch, DMAC3.DMCNT 0008 20DCh
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — — DTE
[Setting condition]
When 1 is written to this bit.
[Clearing conditions]
When 0 is written to this bit.
When the specified total volume of data transfer is completed.
When DMA transfer is stopped by the repeat size end interrupt.
When DMA transfer is stopped by the extended repeat area overflow interrupt.
Address(es): DMAC0.DMREQ 0008 201Dh, DMAC1.DMREQ 0008 205Dh, DMAC2.DMREQ 0008 209Dh, DMAC3.DMREQ 0008 20DDh
b7 b6 b5 b4 b3 b2 b1 b0
— — — CLRS — — — SWRE
Q
Value after reset: 0 0 0 0 0 0 0 0
[Setting condition]
When 1 is written to this bit.
[Clearing conditions]
When a DMA transfer request by software is accepted and DMA transfer is started while the CLRS bit is set to 0
(the SWREQ bit is cleared after DMA transfer is started by software).
When 0 is written to this bit.
Address(es): DMAC0.DMSTS 0008 201Eh, DMAC1.DMSTS 0008 205Eh, DMAC2.DMSTS 0008 209Eh, DMAC3.DMSTS 0008 20DEh
b7 b6 b5 b4 b3 b2 b1 b0
[Setting conditions]
When 1-repeat size data transfer is completed in repeat transfer mode with the RPTIE bit in DMINT set to 1.
When 1-block data transfer is completed in block transfer mode with the RPTIE bit in DMINT set to 1.
When an extended repeat area overflow on the source address occurs while the SARIE bit in DMINT is set to 1 and
the SARA[4:0] bits in DMAMD are set to a value other than 00000b (extended repeat area is specified on the
transfer source address)
When an extended repeat area overflow on the destination address occurs while the DARIE bit in DMINT is set to 1
and the DARA[4:0] bits in DMAMD are set to a value other than 00000b (extended repeat area is specified on the
transfer destination address)
[Clearing conditions]
When 0 is written to this bit.
When 1 is written to the DTE bit in DMCNT.
[Setting conditions]
When the specified number of unit-transfers are completed in normal transfer mode (the value of DMCRAL
becoming 0 on completion of transfer)
When the specified number of repeat transfer operations are completed in repeat transfer mode (the value of
DMCRB becoming 0 on completion of transfer))
When the specified number of blocks have been transferred in block transfer mode (the value of DMCRB becoming
0 on completion of transfer)
[Clearing conditions]
When 0 is written to this bit
When 1 is written to the DTE bit in DMCNT
[Setting condition]
When the DMAC starts data transfer operation
[Clearing condition]
When data transfer in response to one transfer request is completed
Address(es): DMAC0.DMCSL 0008 201Fh, DMAC1.DMCSL 0008 205Fh, DMAC2.DMCSL 0008 209Fh, DMAC3.DMCSL 0008 20DFh
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — — DISEL
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — — DMST
[Setting condition]
When 1 is written to this bit
[Clearing condition]
When 0 is written to this bit
16.3 Operation
DMSAR DMDAR
Data 1 Data 1
Data 3 Data 3
Data 4 Data 4
Data 5 Data 5
Data 6 Data 6
Data 3 Data 3
Data 4 Data 4
Data 1
Data 2
Data 3
Data 4
DMSAR
First block
Transfer
N-th block
Example:
Eight bytes are specified as an extended repeat area by the lower three bits of DMACm.DMSAR (SARA[4:0]
bits in DMACm.DMAMD = 00011b).
The data size is eight bits (SZ[1:0] bits in DMACm.DMTMD = 00b).
Memory area
00014002h 00014002h
00014003h 00014003h
00014004h 00014004h
00014005h 00014005h
00014006h 00014006h
00014007h 00014007h
An extended repeat area overflow interrupt
00014008h request can be generated.
00014009h
When an interrupt by an extended repeat area overflow is used in block transfer mode, the following should be taken into
consideration.
When a transfer is stopped by an interrupt by an extended repeat area overflow, the address register must be set so that
the block size is a power of 2 or the block size boundary is aligned with the extended repeat area boundary. When an
overflow on the extended repeat area occurs during a transfer of one block, the interrupt by the overflow is suspended
until transfer of the block is completed, and the transfer overruns.
Figure 16.6 shows an example when the extended repeat area function is used in block transfer mode.
Example:
Eight bytes are specified as an extended repeat area by the lower three bits of DMACm.DMSAR (SARA[4:0] bits in
DMACm.DMAMD = 00011b),
block transfer mode with block size 5 is set (DMACm.DMCRA = 00050005h), and
transfer source address is not specified as a block area.
Data size is eight bits (SZ[1:0] bits in DMACm.DMTMD = 00b).
Memory area
Repeated
00013FFEh DMSAR value Second block
First block transfer
range transfer
00013FFFh
00014009h
Figure 16.6 Example of Extended Repeat Area Function in Block Transfer Mode
Note 1. When setting a negative value in the DMA offset register, the value must be 2’s complement. The 2's complement is obtained by
the following formula.
2’s complement of a negative offset value = ~ (offset) + 1 (~: bit inversion)
Transfer
Data 2 Address A2
= address A1 + offset value
Offset value
Data 3 Address A3
= address A2 + offset value
Offset value
Data 4 Address A4
= address A3 + offset value
In Figure 16.7, the transfer data is 32 bits long, and offset addition and increment are set as the transfer source address
update mode and transfer destination address update mode, respectively. The second and subsequent data is each read
from the transfer source address obtained by adding the offset value to the previous address. The data read from the
addresses at the specified intervals is written to the continuous locations on the destination.
First
Data 1 Data 5 Data 9 Data 13 cycle Data 1 Data 2 Data 3 Data 4
Transfer
Data 2 Data 6 Data 10 Data 14 Second cycle Data 5 Data 6 Data 7 Data 8
Data 3 Data 7 Data 11 Data 15 Third cycle Data 9 Data 10 Data 11 Data 12
Data 4 Data 8 Data 12 Data 16 Fourth cycle Data 13 Data 14 Data 15 Data 16
Address
Data 5 Data 5 Data 5 Data 2 First
returned
Address cycle
Data 9 Data 9 Data 9 Data 3
returned Transfer source
Data 13 Data 13 Data 13 address written by Data 4
Data 2 Data 2 Data 2 CPU Data 5
Offset value
Figure 16.8 XY Conversion Operation Using Offset Addition in Repeat Transfer Mode
When a transfer starts, the offset value is added to the transfer source address every time data is transferred. The transfer data
is written to the destination continuous addresses. When data 4 is transferred, which means that the repeat size of transfers is
completed, the transfer source address returns to the transfer start address (address of data 1 on the transfer source) and a
repeat size end interrupt is requested. While this interrupt stops the transfer temporarily, perform the following.
DMAC0.DMSAR: Rewrite the DMA transfer source address to the address of data 5
(with the above example, the data 1 address + 4).
DMAC0.DMCNT: Set the DTE bit to 1.
The DMA transfer is resumed from the state when the DMA transfer is stopped. After that, the operations described
above are repeated until the transfer source data is transposed to the destination area (XY conversion).
Start
Data transfer
No
Number of repeat operations = 0
Yes
No
Repeat size = 0
Yes
End
: User side processing
Figure 16.9 XY Conversion Flowchart Using Offset Addition in Repeat Transfer Mode
(2) DMAC Activation by Interrupt Requests from On-Chip Peripheral Modules or External Interrupt
Requests
Interrupt requests from the on-chip peripheral modules and external interrupt requests can be specified as the DMAC
activation sources. The activation source can be selected separately for each channel using the DMRSRm registers (m =
0 to 3) of the ICU.
The DMAC is activated when an interrupt request from the on-chip peripheral module or an external interrupt request is
generated while the DCTG[1:0] bits in DMTMD of DMACm is set to 01b (interrupts from the peripheral modules and
the external interrupt pins are selected), the DTE bit in DMCNT of DMACm is set to 1 (DMA transfer is enabled), and
the DMST bit in DMAST is set to 1 (DMAC activation is enabled).
For interrupt requests specified as DMAC activation sources, see Table 14.3, Interrupt Vector Table, in section 14,
Interrupt Controller (ICUb).
System clock
DMAC activation
request
DMAC access R W
Data transfer
Figure 16.10 DMAC Operation Timing Example (1) (DMA Activation by Interrupt from Peripheral Module/
External Interrupt Input Pin, Normal Transfer Mode, Repeat Transfer Mode)
System clock
DMAC activation
request
DMAC access
Data transfer
Figure 16.11 DMAC Operation Timing Example (2) (DMA Activation by Interrupt from Peripheral Module/
External Interrupt Input Pin, Block Transfer Mode, Block Size = 4)
Note 1. This is the case when the block size is 2 or more. When the block size is 1, normal transfer cycle is applied.
Cr and Cw depend on the access destination. For the number of cycles for each access destination, see section 35, RAM,
section 36, ROM (Flash Memory for Code Storage), section 5, I/O Registers.
The unit for +1 in “Data Transfer (Read)” column is one system clock cycle (ICLK).
For the operation example, see section 16.3.5, Operation Timing.
To use peripheral function Set the peripheral module as a DMACm request Set the control register for the peripheral function without
interrupts as DMA activation source. starting it.
sources
To use external pin interrupts as Set the IRQ pin function using the interrupt
DMA activation sources Set the IRQ pin function without enabling it.
controller (ICU).
Note 1. Setting of the DMAST.DMST bit does not necessarily have to follow the settings for the individual activation sources.
Writing to the registers for the channels when the corresponding DMACm.DMCNT.DTE bit is set to 1 is prohibited
(except for DMACm.DMCNT). In this case, writing must be performed after the bit is cleared to 0.
16.5 Interrupts
Each DMAC channel can output an interrupt request to the CPU or the DTC after transfer in response to one request is
completed. When the transfer destination is the on-chip peripheral bus, an interrupt request is generated upon completion
of data write to the write buffer not to the actual transfer destination.
Table 16.8 lists the relation among the interrupt sources, the interrupt status flags, and the interrupt enable bits. Figure
16.13 shows the schematic logic diagram of interrupt outputs. Figure 16.14 shows the DMAC interrupt handling
routine to resume or terminate DMA transfer.
Table 16.8 Relation among Interrupt Sources, Interrupt Status Flags, and Interrupt Enable Bits
Interrupt Sources Interrupt Enable Bits Interrupt Status Flags Request Output Enable Bits
Transfer end — DMACm.DMSTS.DTIF DMACm.DMINT.DTIE
Escape Repeat size end DMACm.DMINT.RPTIE DMACm.DMSTS.ESIF DMACm.DMINT.ESIE
transfer end
Source address extended repeat DMACm.DMINT.SARIE
area overflow
Destination address extended DMACm.DMINT.DARIE
repeat area overflow
DTIE
DTIF
ESIE
When the specified repeat (or block)
size of data transfer is completed
ESIF
DARIE
Specifically, the different procedures are used for canceling an interrupt to restart DMA transfer in the following two
cases: (1) discontinuing or terminating DMA transfer and (2) continuing DMA transfer.
Continue
Is suspended transfer Terminate
continued?
Discontinue
Write 1 to DTE bit in DMACm.DMCNT. Is another data transfer End
performed?
Start another transfer
16.7.4 Interrupt Request by the DMA Activation Source Flag Control Register (DMCSL)
at the End of each Transfer
While the DMACm.DMCSL.DISEL bit is 1, an interrupt is issued to the CPU at the end of each transfer that has been
activated by one DMA request. Unlike the transfer end interrupt that the DMAC outputs or the escape end interrupt, the
interrupt of this type is issued to the CPU at the end of DMA transfer without clearing the interrupt flag of the DMAC
activation source to 0 by changing the interrupt request destination to the CPU. In this case, since the interrupt flag is not
cleared to 0 at the end of DMAC transfer, it should be cleared to 0 by the CPU interrupt routine.
The interrupt flag is cleared when the CPU interrupt is accepted.
For the change of the settings on the interrupt flag or the interrupt request destination, see section 14, Interrupt
Controller (ICUb). For the DMACm.DMCSL.DISEL bit setting, see section 16.2.12, DMA Activation Source Flag
Control Register (DMCSL).
16.7.5 Setting of DMAC Activation Source Select Register of the Interrupt Controller
(ICU.DMRSRm)
The DMAC activation source select register (ICU.DMRSRm) should be set while the DMA transfer enable bit
(DMACm.DMCNT.DTE) is cleared to 0 (DMA transfer is disabled). Moreover, the DTC activation enable register
(ICU.DTCERm) that corresponds to the same vector number that has been set by the ICU.DMRSRm register should not
be set to 1. For details on the ICU.DTCERn and ICU.DMRSRm, see section 14, Interrupt Controller (ICUb).
17.1 Overview
Table 17.1 lists the specifications of the DTC, and Figure 17.1 shows a block diagram of the DTC.
DTC
MRA
MRB
8 Register CRA
Vector number
Interrupt SAR
controller DAR
Activation
Start request control
DTC response
DTCCR Bus interface
DTC
DTCVBR
response
DTCADMOD control
DTCST
DTCSTS
Internal peripheral
bus interface 1 Internal main bus 2
b7 b6 b5 b4 b3 b2 b1 b0
x: Undefined
b7 b6 b5 b4 b3 b2 b1 b0
x: Undefined
b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16
x: Undefined
b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16
x: Undefined
CRA
CRAH CRAL
x: Undefined
Note: • The function depends on transfer mode.
Note: • Set CRAH and CRAL to the same value in repeat transfer mode and block transfer mode.
x: Undefined
CRB is used to set the block transfer count for block transfer mode.
The transfer count is 1, 65535, and 65536 when the set value is 0001h, FFFFh, and 0000h, respectively. The CRB value
is decremented (–1) when the final data of a single block size is transferred.
When normal transfer mode or repeat transfer mode is selected, this register is not used and the set value is ignored.
CRB cannot be accessed directly from the CPU.
b7 b6 b5 b4 b3 b2 b1 b0
— — — RRS — — — —
b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16
0 0 0 0 0 0 0 0 0 0
DTCVBR is used to set the base address for calculating the DTC vector table address.
It can be set in the range of 0000 0000h to 07FF FC00h and F800 0000h to FFFF FC00h in 1-Kbyte units.
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — — SHORT
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — — DTCST
ACT — — — — — — — VECN[7:0]
[Setting condition]
When the DTC is activated by a transfer request
[Clearing condition]
When transfer by the DTC is completed in response to a transfer request.
The DTC performs the following operations at each data transfer (or the last of the consecutive transfers in the case of a
chained transfer).
On completion of a specified round of data transfer, the DTCERn.DTCE bit is cleared to 0 and an interrupt is
requested to the CPU.
If the MRB.DISEL bit is 1, an interrupt is requested to the CPU on completion of data transfer.
For the other transfers, the interrupt status flag of the startup source is cleared to 0 at the start of data transfer.
:
:
:
+4n
:
Transfer data (n) :
start address :
4 bytes
4 bytes
Start address 3 (0) 2 (1) 1 (2) 0 (3) Start address 3 (0) 2 (1) 1 (2) 0 (3)
4 bytes
17.4 Operation
The DTC transfers data in accordance with the transfer data. Storage of the transfer data in the RAM area is required
before DTC operation.
When the DTC is activated, it reads the DTC vector corresponding to the vector number. Then the DTC reads transfer
data from the transfer data store address pointed by the DTC vector, transfers data, and then writes back the transfer data
after the data transfer. Storing transfer data in the RAM area allows data transfer of arbitrary number of channels.
There are three transfer modes: normal transfer mode, repeat transfer mode, and block transfer mode.
The DTC specifies a transfer source address in SAR and a transfer destination address in DAR. The values of these
registers are incremented, decremented, or address-fixed independently after data transfer.
Table 17.2 lists transfer modes of the DTC.
Setting the CHNE bit in MRB to 1 allows multiple transfers (chain transfer) on a single startup source. Setting the CHNS
bit in MRB also enables chain transfer when specified data transfer is completed.
Figure 17.4 shows the operation flowchart of the DTC. Table 17.3 lists chain transfer conditions.
START
Match and
RRS bit = 1 Compare vector
numbers. Match?
Read data to be
transferred
Update transfer data
start address
YES
CHNE bit = 1?
NO YES
CHNS = 0?
NO
YES
MD[1:0] = 01b?
(Repeat transfer?)
NO
YES YES
Last data transfer? Last data transfer?
(Transfer counter = 1?)*1 (Transfer counter = 1?)*1
NO NO
YES
DISEL = 1?
NO
Write transfer data Write transfer data Write transfer data Write transfer data
END
Note 1. Counter value before starting data transfer
Table 17.4 Transfer Data Write-Back Skip Conditions and Applicable Registers
SM[1:0] Bits in MRA DM[1:0] Bits in MRB SAR Register DAR Register
b3 b2 b3 b2
0 0 0 0 Skip Skip
0 0 0 1
0 1 0 0
0 1 0 1
0 0 1 0 Skip Write-back
0 0 1 1
0 1 1 0
0 1 1 1
1 0 0 0 Write-back Skip
1 0 0 1
1 1 0 0
1 1 0 1
1 0 1 0 Write-back Write-back
1 0 1 1
1 1 1 0
1 1 1 1
Data 3 Data 3
Data 4 Data 4
Data 5 Data 5
Data 6 Data 6
Data 3 Data 3
Data 4 Data 4
Data 1
Data 2
Data 3
Data 4
Figure 17.6 Memory Map of Repeat Transfer Mode (Transfer Source: Repeat Area)
SAR
First block
Transfer
N-th block
Figure 17.7 Memory Map of Block Transfer Mode (Transfer Destination: Block Area)
Data area
Transfer data
DTC vector table allocated in the RAM
Writing 1 to the CHNE and CHNS bits in MRB enables chain transfer to be performed only after completion of specified
data transfer. In repeat transfer mode, chain transfer is performed after completion of specified data transfer.
For details on chain transfer conditions, see Table 17.3, Chain Transfer Conditions.
System clock
DTC access R W
System clock
DTC access
System clock
DTC access R W R W
Vector read Transfer data Data Transfer data Transfer data Data Transfer data
read transfer write read transfer write
Figure 17.11 Example (3) of DTC Operation Timing (Short-Address Mode, Chain Transfer)
System clock
DTC access
R W
System clock
DTC access R W RR W
n = Vector number
Note: • When startup sources (vector numbers) of (1) and (2) are the same and the RRS bit = 1, the transfer data read for request (2) is skipped.
[1] Setting the RRS bit in DTCCR to 0 resets the transfer data read
skip flag. After that, transfer data read is not skipped while the
Set the RRS bit in DTCCR to 0 [1] DTC is activated. When transfer data is updated, be sure to make
this setting.
[2] Allocate transfer data (MRA, MRB, SAR, DAR, CRA, and CRB) in
the data area. For setting transfer data, see section 17.2, Register
Set transfer data [2] Descriptions. For how to allocate transfer data, see section 17.3.1,
(MRA, MRB, SAR, DAR, CRA, and CRB) Allocating Transfer Data and DTC Vector Table.
[3] Set transfer data start addresses in the DTC vector table. For how
to set the DTC vector table, see section 17.3.1, Allocating Transfer
Set transfer data start addresses in Data and DTC Vector Table.
[3]
the DTC vector table
[4] Setting the RRS bit in DTCCR to 1 can skip the second and the
subsequent transfer data read cycles for continuous DTC
activation due to the same interrupt source. The RRS bit can
Set the RRS bit in DTCCR to 1 [4] always be set to 1, but this setting during DTC transfer becomes
valid from the next transfer.
[6] Set the enable bit for a startup source interrupt to 1. When a
Set the enable bit for
[6] source interrupt is generated, the DTC is activated. For the setting
a startup source interrupt
of the interrupt source enable bit, refer to the setting of the module
Setting for each activation that is to be a startup source.
source
Common setting
for DTC [7] Set the DTC module start bit (DTCST.DTCST) to 1.
Note: • The DTCST.DTCST bit can be set even if the setting for each
Set the DTCST.DTCST bit to 1 [7] activation source is not completed.
End
1. Set normal transfer mode for input data for the first data transfer. Set the following:
Transfer source address: Fixed, CRA = 0000h (65,536 times), CHNE bit = 1 (chain transfer enabled) in MRB,
CHNS bit = 1 (chain transfer is performed only when the transfer counter is 0) in MRB, and DISEL bit = 0 (an
interrupt request to the CPU is generated when specified data transfer is completed) in MRB.
2. Prepare the upper 8-bit address of the start address at every 65,536 times of the transfer destination address for the
first data transfer in another area (such as ROM). For example, when setting the input buffer to 200000h to
21FFFFh, prepare 21h and 20h.
3. For the second data transfer, set repeat transfer mode (source side: repeat area) for re-setting the transfer destination
address of the first data transfer. Specify the upper 8 bits of DAR in the first transfer data area for the transfer
destination. At this time, set CHNE bit = 0 (chain transfer disabled) in MRB and DISEL bit = 0 (an interrupt request
to the CPU is generated when specified data transfer is completed) in MRB. When setting the input buffer
mentioned above to 200000h to 21FFFFh, set the transfer counter to 2.
4. The first data transfer is performed by an interrupt 65,536 times. When the transfer counter of the first data transfer
becomes 0, the second data transfer starts. Set the upper 8 bits of the transfer source address of the first data transfer
to 21h. The transfer counter (lower 16 bits) of the transfer destination address of the first data transfer is 0000h.
5. In succession, the first data transfer is performed by an interrupt 65,536 times specified for the first data transfer.
When the transfer counter of the first data transfer becomes 0, the second data transfer starts. Set the upper 8 bits of
the transfer source address of the first data transfer to 20h. The transfer counter (lower 16 bits) of the transfer
destination address of the first data transfer is 0000h.
6. Steps 4 and 5 above are repeated infinitely. Since the second data transfer is in repeat transfer mode, no interrupt
request to the CPU is generated.
Input circuit
Input buffer
Address 3 2 1 0 Address 0 1 2 3
4 bytes 4 bytes
Address 3 2 1 0 Address 0 1 2 3
4 bytes 4 bytes
17.10.3 Setting the DTC Activation Enable Register (ICU.DTCERn) of the Interrupt
Controller
The DMAC should not be activated by setting the DMAC activation request select register (ICU.DMRSRn (n = number
of DMAC channel)) to the same vector number that has been specified by setting the ICU.DTCERn register 1 (DTC
transfer enable). For details on the ICU.DTCERn and ICU.DMRSRn registers (n = number of DMAC channel), refer to
section 14, Interrupt Controller (ICUb).
Table 18.1 lists the specifications of the ELC, and Figure 18.1 shows a block diagram of the ELC.
Note 1. The single-port and port group specified as the input generate an event according to the change in the connected signal value.
In products with 64-pin packages, when ports PC0 and PC1 are selected in port switching register A (PSRA), input to ports PB6
and PB7 and the output port event function of the ELC cannot be used.
In products with 48-pin packages, when ports PC0 to PC3 are selected in port switching register B (PSRB), input to ports PB0,
PB1, PB3, and PB5 and the output port event function of the ELC cannot be used.
Peripheral modules
Event control
(except timer)
ELCR
DTC
ELSR1 to ELSR25
ICU
ELOPA Timer event
input control
Internal peripheral bus 2
LVD
ELOPB
DOC
PDBF1
PEL0, PEL1
b7 b6 b5 b4 b3 b2 b1 b0
ELCON — — — — — — —
18.2.2 Event Link Setting Register n (ELSRn) (n = 1 to 4, 10, 12, 15, 18, 20, 22, 24, 25)
Address(es): ELSR1: 0008 B102h, ELSR2: 0008 B103h, ELSR3: 0008 B104h, ELSR4: 0008 B105h,
ELSR10: 0008 B10Bh, ELSR12: 0008 B10Dh, ELSR15: 0008 B110h, ELSR18: 0008 B113h,
ELSR20: 0008 B115h, ELSR22: 0008 B117h, ELSR24: 0008 B119h, ELSR25: 0008 B11Ah
b7 b6 b5 b4 b3 b2 b1 b0
ELS[7:0]
ELSRn specifies an event signal to be linked for each peripheral module. Table 18.2 shows the correspondence between
ELSRn registers and the peripheral modules. Table 18.3 shows the correspondence between the event signal names set
in ELSRn and the signal numbers.
Note 1. Do not set the DOC data operation condition met signal (ELS[7:0] bits = 6Ah) in the ELSR24 or ELSR25 register.
Table 18.3 Correspondence between Event Signal Names Set in ELSRn.ELS[7:0] Bits and Signal Numbers (1 / 2)
ELS[7:0] Bit Value Name of Event Signal Set in ELSR
00001000 (08h) MTU1 compare match 1A signal
00001001 (09h) MTU1 compare match 1B signal
00001010 (0Ah) MTU1 overflow signal
00001011 (0Bh) MTU1 underflow signal
00001100 (0Ch) MTU2 compare match 2A signal
00001101 (0Dh) MTU2 compare match 2B signal
00001110 (0Eh) MTU2 overflow signal
00001111 (0Fh) MTU2 underflow signal
00010000 (10h) MTU3 compare match 3A signal
00010001 (11h) MTU3 compare match 3B signal
00010010 (12h) MTU3 compare match 3C signal
00010011 (13h) MTU3 compare match 3D signal
00010100 (14h) MTU3 overflow signal
00010101 (15h) MTU4 compare match 4A signal
00010110 (16h) MTU4 compare match 4B signal
00010111 (17h) MTU4 compare match 4C signal
00011000 (18h) MTU4 compare match 4D signal
00011001 (19h) MTU4 overflow signal
00011010 (1Ah) MTU4 underflow signal
00100010 (22h) TMR0 compare match A0 signal
00100011 (23h) TMR0 compare match B0 signal
00100100 (24h) TMR0 overflow signal
00101000 (28h) TMR2 compare match A2 signal
00101001 (29h) TMR2 compare match B2 signal
00101010 (2Ah) TMR2 overflow signal
00111010 (3Ah) SCI5 error (receive error or error signal detection) signal
00111011 (3Bh) SCI5 receive data full signal
00111100 (3Ch) SCI5 transmit data empty signal
00111101 (3Dh) SCI5 transmit end signal
01001110 (4Eh) RIIC0 communication error or event generation signal
01001111 (4Fh) RIIC0 receive data full signal
01010000 (50h) RIIC0 transmit data empty signal
01010001 (51h) RIIC0 transmit end signal
01010010 (52h) RSPI0 error (mode fault, overrun, or parity error) signal
01010011 (53h) RSPI0 idle signal
01010100 (54h) RSPI0 receive data full signal
01010101 (55h) RSPI0 transmit data empty signal
01010110 (56h) RSPI0 transmit end signal (except during clock synchronous operation in
slave mode)
01011000 (58h) A/D conversion end signal of 12-bit A/D converter
01011011 (5Bh) LVD1 voltage detection signal
01100001 (61h) DTC transfer end signal
01100011 (63h) Input edge detection signal of input port group 1
01100101 (65h) Input edge detection signal of single input port 0
01100110 (66h) Input edge detection signal of single input port 1
01101001 (69h) Software event signal
Table 18.3 Correspondence between Event Signal Names Set in ELSRn.ELS[7:0] Bits and Signal Numbers (2 / 2)
ELS[7:0] Bit Value Name of Event Signal Set in ELSR
01101010 (6Ah) DOC data operation condition met signal
Settings other than above are prohibited.
b7 b6 b5 b4 b3 b2 b1 b0
ELOPA determines the operation of MTU1 to MTU3 in the MTU when an event is input. All events must be disabled
when the ELC function is not to be used.
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — MTU4MD[1:0]
ELOPB determines the operation of MTU4 in the MTU when an event is input. All events must be disabled when the
ELC function is not to be used.
b7 b6 b5 b4 b3 b2 b1 b0
— — TMR2MD[1:0] — — TMR0MD[1:0]
ELOPD determines the operation of TMR0 and TMR2 in the TMR when an event is input. All events must be disabled
when the ELC function is not to be used.
b7 b6 b5 b4 b3 b2 b1 b0
PGR1 specifies a group for I/O port bits. PGR1 specifies each port bit in the same 8-bit I/O port as the member of a
group. One to eight port bits can be specified as the members of the same group as required. The correspondence
between PGR1 and ports is shown in Table 18.4.
b7 b6 b5 b4 b3 b2 b1 b0
X: Don't care
For the output port group, PGC1 specifies the form of outputting the signal externally via the port when the event signal
is input. For the input port group, PGC1 enables/disables overwriting of PDBF and specifies the conditions of event
generation (edge of the externally input signal).
The correspondence between PGC1 and ports is shown in Table 18.4.
b7 b6 b5 b4 b3 b2 b1 b0
PDBF1 is an 8-bit readable/writable register used in combination with PGR1. For PDBF1 operations, see section 18.3,
Operation. Table 18.4 shows registers related to port groups and corresponding port numbers.
Table 18.4 Registers Related to Port Groups and Corresponding Port Numbers
Port Group Setting Register (PGR) Port Group Control Register (PGC) Port Buffer Register (PDBF) Port Number
PGR1 register PGC1 register PDBF1 register Port B
Note: • Since pins PE0 to PE5 are not available, bits b0 to b5 of the PGR2 and PDBF2 registers cannot be set.
b7 b6 b5 b4 b3 b2 b1 b0
X: Don’t care
PELn specifies the 1-bit port (hereinafter referred to as a single-port) to which an event is to be linked, the port operation
upon the event signal input, and the conditions of event generation. In the RX220 Group, a total of two bits in either port
B (8-bit port) can be specified as single-ports.
b7 b6 b5 b4 b3 b2 b1 b0
WI WE — — — — — SEG
18.3 Operation
Module
External pin
Module n
Interrupt CPU
Status flag control
circuit
Interrupt enable
control
Note 1. See the descriptions on the bit in the relevant timer section.
Note 1. See the description on the bit in the A/D converter section.
Note 1. Port B
(4) Input Port Group Operation upon Event Input and Event Generation
An input port group generates an event when the signal value of any one of the external pins connected to the relevant
port group changes. The event generation condition is specified using the PGC1 registers. When an event is input to an
input port group, the signal value of the external pin upon event input is transferred to PDBF1. In this case, only the
values of the bits specified as members of the input port group are transferred. An example of operation is shown in
Figure 18.4.
Port B7
On-chip module
Event link
Port B6
Port B5
Port B4
Event link
Port B2
Port B1
Port B0
PDBF1 PDBF1
register register External signal
0 0 PB7
0 0
PB6
0 0
PB5
0 0
PB4
0 1
PB3
0 0 PB2
0 1 PB1
0 0 PB0
PB3 1 0 1 1 PB3
PB2 0 0 0 0 PB2
PB1 1 0 1 1 PB1
PB0 0 0 0 0 PB0
Event signal
Note: • PB3 to PB0 are specified as an output port group.
1 0 1 0 0 0
PB3
0 0 0 1 0 0
PB2
0 0 0 0 1 0
PB1
0 0 0 0 0 1
PB0
PB3
PB2
PB1
PB0
Event signal
Specifying input pull-up, open-drain output, switching of driving ability, or 5-V tolerance is available for other signals on
pins that also function as general I/O pins.
Port 3: P35
Internal bus
Reading the port
0: OFF
ODR0, ODR1
PDR 0
Peripheral module output enable *1 1
*2
PODR 0
Peripheral module output signal *1 1
ISEL bit
*3
Analog input *4
Address(es): PORT0.PDR 0008 C000h, PORT1.PDR 0008 C001h, PORT2.PDR 0008 C002h, PORT3.PDR 0008 C003h,
PORT4.PDR 0008 C004h, PORT5.PDR 0008 C005h, PORTA.PDR 0008 C00Ah, PORTB.PDR 0008 C00Bh,
PORTC.PDR 0008 C00Ch, PORTD.PDR 0008 C00Dh, PORTE.PDR 0008 C00Eh, PORTH.PDR 0008 C011h,
PORTJ.PDR 0008 C012h
b7 b6 b5 b4 b3 b2 b1 b0
B7 B6 B5 B4 B3 B2 B1 B0
m = 0 to 5, A to E, H, J
PDR is used to select the input or output direction for individual pins of the corresponding port m when the pins are
configured as the general I/O pins.
Each bit of PORTm.PDR corresponds to each pin of port m; I/O direction can be specified in 1-bit units. In products with
less than 100 pins, the bit corresponding to the port m pin that does not exist is reserved. Write 1 (output) to the bit.
The PORT3.PDR.B5 bit is reserved, because the P35 pin is input only. The bit corresponding to a pin that does not exist
is also reserved. A reserved bit is read as 0. The write value should be 0.
Address(es): PORT0.PODR 0008 C020h, PORT1.PODR 0008 C021h, PORT2.PODR 0008 C022h, PORT3.PODR 0008 C023h,
PORT4.PODR 0008 C024h, PORT5.PODR 0008 C025h, PORTA.PODR 0008 C02Ah, PORTB.PODR 0008 C02Bh,
PORTC.PODR 0008 C02Ch, PORTD.PODR 0008 C02Dh, PORTE.PODR 0008 C02Eh, PORTH.PODR 0008 C031h,
PORTJ.PODR 0008 C032h
b7 b6 b5 b4 b3 b2 b1 b0
B7 B6 B5 B4 B3 B2 B1 B0
m = 0 to 5, A to E, H, J
PODR holds the data to be output from the pins used for general output ports.
In products with less than 100 pins, the bit corresponding to the port m pin that does not exist is reserved. Write 0 (low
output) to the bit.
The PORT3.PODR.B5 bit is reserved, because the P35 pin is input only. The bit corresponding to a pin that does not exist
is reserved. A reserved bit is read as 0. The write value should be 0.
Address(es): PORT0.PIDR 0008 C040h, PORT1.PIDR 0008 C041h, PORT2.PIDR 0008 C042h, PORT3.PIDR 0008 C043h,
PORT4.PIDR 0008 C044h, PORT5.PIDR 0008 C045h, PORTA.PIDR 0008 C04Ah, PORTB.PIDR 0008 C04Bh,
PORTC.PIDR 0008 C04Ch, PORTD.PIDR 0008 C04Dh, PORTE.PIDR 0008 C04Eh, PORTH.PIDR 0008 C051h,
PORTJ.PIDR 0008 C052h
b7 b6 b5 b4 b3 b2 b1 b0
B7 B6 B5 B4 B3 B2 B1 B0
x: Undefined
m = 0 to 5, A to E, H, J
Address(es): PORT0.PMR 0008 C060h, PORT1.PMR 0008 C061h, PORT2.PMR 0008 C062h, PORT3.PMR 0008 C063h,
PORT4.PMR 0008 C064h, PORT5.PMR 0008 C065h, PORTA.PMR 0008 C06Ah, PORTB.PMR 0008 C06Bh,
PORTC.PMR 0008 C06Ch, PORTD.PMR 0008 C06Dh, PORTE.PMR 0008 C06Eh, PORTH.PMR 0008 C071h,
PORTJ.PMR 0008 C072h
b7 b6 b5 b4 b3 b2 b1 b0
B7 B6 B5 B4 B3 B2 B1 B0
b0 B0 Pm0 Pin Mode Control 0: Use pin as general I/O port. R/W
1: Use pin as I/O port for peripheral
b1 B1 Pm1 Pin Mode Control R/W
functions.
b2 B2 Pm2 Pin Mode Control R/W
b3 B3 Pm3 Pin Mode Control R/W
b4 B4 Pm4 Pin Mode Control R/W
b5 B5 Pm5 Pin Mode Control R/W
b6 B6 Pm6 Pin Mode Control R/W
b7 B7 Pm7 Pin Mode Control R/W
m = 0 to 5, A to E, H, J
Each bit of PORTm.PMR corresponds to each pin of port m; pin function can be specified in 1-bit units. In products with
less than 100 pins, the bit corresponding to the port m pin that does not exist is reserved. Write 0 (general I/O port) to the
bit.
The bit corresponding to a pin that does not exist is reserved. A reserved bit is read as 0. The write value should be 0.
Address(es): PORT1.ODR0 0008 C082h, PORT3.ODR0 0008 C086h, PORTA.ODR0 0008 C094h, PORTB.ODR0 0008 C096h,
PORTC.ODR0 0008 C098h, PORTE.ODR0 0008 C09Ch
b7 b6 b5 b4 b3 b2 b1 b0
B7 B6 B5 B4 B3 B2 B1 B0
m = 1, 3, A to C, E
In products with less than 100 pins, the bit corresponding to the port m pin that does not exist is reserved. Write 0
(CMOS output) to the bit.
The bits corresponding to a pin that does not exist or pins with no open-drain output allocation are reserved. A reserved
bit is read as 0. The write value should be 0.
Address(es): PORT1.ODR1 0008 C083h, PORT2.ODR1 0008 C085h, PORT3.ODR1 0008 C087h, PORTA.ODR1 0008 C095h,
PORTB.ODR1 0008 C097h, PORTC.ODR1 0008 C099h
b7 b6 b5 b4 b3 b2 b1 b0
B7 B6 B5 B4 B3 B2 B1 B0
m = 1 to 3, A to C
In products with less than 100 pins, the bit corresponding to the port m pin that does not exist is reserved. Write 0
(CMOS output) to the bit. The PORT3.ODR1.B2 bit is reserved, because the P35 pin is input only.
The bits corresponding to a pin that does not exist or pins with no open-drain output allocation are reserved. A reserved
bit is read as 0. The write value should be 0.
Address(es): PORT0.PCR 0008 C0C0h, PORT1.PCR 0008 C0C1h, PORT2.PCR 0008 C0C2h, PORT3.PCR 0008 C0C3h,
PORT4.PCR 0008 C0C4h, PORT5.PCR 0008 C0C5h, PORTA.PCR 0008 C0CAh, PORTB.PCR 0008 C0CBh,
PORTC.PCR 0008 C0CCh, PORTD.PCR 0008 C0CDh, PORTE.PCR 0008 C0CEh, PORTH.PCR 0008 C0D1h,
PORTJ.PCR 0008 C0D2h
b7 b6 b5 b4 b3 b2 b1 b0
B7 B6 B5 B4 B3 B2 B1 B0
b0 B0 Pm0 Input Pull-Up Resistor Control 0: Disables an input pull-up resistor. R/W
1: Enables an input pull-up resistor.
b1 B1 Pm1 Input Pull-Up Resistor Control R/W
b2 B2 Pm2 Input Pull-Up Resistor Control R/W
b3 B3 Pm3 Input Pull-Up Resistor Control R/W
b4 B4 Pm4 Input Pull-Up Resistor Control R/W
b5 B5 Pm5 Input Pull-Up Resistor Control R/W
b6 B6 Pm6 Input Pull-Up Resistor Control R/W
b7 B7 Pm7 Input Pull-Up Resistor Control R/W
m = 0 to 5, A to E, H, J
While a pin is in the input state with the corresponding bit in PORTm.PCR set to 1, the pull-up resistor connected to the
pin is enabled.
When a pin is set as a general port output pin, or a peripheral function output pin, the pull-up resistor for the pin is
disabled regardless of the settings of PCR.
The pull-up resistor is also disabled in the reset state.
The B5 bit in PORT3.PCR is reserved. The bit corresponding to a pin that does not exist is reserved. A reserved bit is
read as 0. The write value should be 0.
Address(es): PORT1.DSCR 0008 C0E1h, PORTB.DSCR 0008 C0EBh, PORTC.DSCR 0008 C0ECh
b7 b6 b5 b4 b3 b2 b1 b0
B7 B6 B5 B4 B3 B2 B1 B0
m = 1, B, C
The bit corresponding to a pin with the fixed drive capacity can be read from or written to. However, the drive capacity
cannot be changed.
When high-drive output is selected, switching noise increases compared to when normal output is selected. Carefully
evaluate the effect of noise on the MCU caused by adjacent pins before selecting high-drive output.
The bit corresponding to a pin that does not exist is reserved. A reserved bit is read as 0. The write value should be 0.
b7 b6 b5 b4 b3 b2 b1 b0
PSEL7 PSEL6 — — — — — —
The PSRA register is for 64-pin packages. The PSRA register is used to select either the general I/O functions of PB6
and PB7 or those of PC0 and PC1. When 1 is written to the PSEL6 and PSEL7 bits, port C can be used as an 8-bit port.
As for the I/O functions of the peripheral functions, functions multiplexed with PB6 and PB7 are enabled. To enable the
peripheral functions, write 1 to the corresponding pin mode control bit of the PORTB.PMR register.
Rewriting to this register must be performed when the PMR, PDR, and PCR registers for the corresponding pins are 0.
b7 b6 b5 b4 b3 b2 b1 b0
The PSRB register is for 48-pin packages. The PSRB register is used to select either the general I/O functions of PB0,
PB1, PB3, and PB5 and those of PC0 to PC3. When 1 is written to the PSEL0, PSEL1, PSEL3, and PSEL5 bits, port C
can be used as an 8-bit port.
As for the I/O functions of the peripheral functions, functions multiplexed with PB0, PB1, PB3, and PB5 are enabled. To
enable the peripheral functions, write 1 to the corresponding pin mode control bit of the PORTB.PMR register.
Rewriting to this register must be performed when the PMR, PDR, and PCR registers for the corresponding pins are 0.
Note 1. Clear the PORTn.PMR bit, the PmnPFS.ISEL bit and the PmnPFS.ASEL bit to 0.
Note 2. In the case of release when the setting is for output, the port is an input over the period from release from the reset state to the
pin becoming an output. Since the voltage on the pin is undefined while it is an input, this may lead to an increase in the current
drawn.
b7 b6 b5 b4 b3 b2 b1 b0
B0WI PFSWE — — — — — —
b7 b6 b5 b4 b3 b2 b1 b0
— — — — PSEL[3:0]
The Pmn pin function control register (PmnPFS) selects the pin function. Bits PSEL[3:0] select the peripheral function
assigned to each port pin.
The ISEL bit is set when a pin is used as an IRQ input pin. This setting can be used with the combination of the
peripheral function, though IRQn (external pin interrupt) of the same number should not be enabled by two or more pins.
The ASEL bit is set when a pin is used as an analog pin. When switching a pin to analog using the ASEL bit, set the
corresponding port mode register bit (PORTm.PMR) to “general I/O port” and the port direction register bit
(PORTm.PDR) to “input”. The pin state cannot be read at this point. The PmnPFS register is protected by the write-
protect register (PWPR). Modify the register after releasing the protection.
The ISEL bit to which IRQn is not specified is reserved. The ASEL bit to which analog input/output is not specified is
reserved.
Address(es): P12PFS 0008 C14Ah, P13PFS 0008 C14Bh, P14PFS 0008 C14Ch, P15PFS 0008 C14Dh,
P16PFS 0008 C14Eh, P17PFS 0008 C14Fh
b7 b6 b5 b4 b3 b2 b1 b0
— ISEL — — PSEL[3:0]
Address(es): P20PFS 0008 C150h, P21PFS 0008 C151h, P22PFS 0008 C152h, P23PFS 0008 C153h,
P24PFS 0008 C154h, P25PFS 0008 C155h, P26PFS 0008 C156h, P27PFS 0008 C157h
b7 b6 b5 b4 b3 b2 b1 b0
— — — — PSEL[3:0]
Table 20.7 Register Settings for Input/Output Pin Function in 64-Pin and 48-Pin
Pin
PSEL[3:0]
Settings P26 P27
0000b Hi-Z
(initial
value)
0001b MTIOC2A MTIOC2B
0101b TMO1 TMCI3
1010b TXD1 SCK1
SMOSI1
SSDA1
Address(es): P30PFS 0008 C158h, P31PFS 0008 C159h, P32PFS 0008 C15Ah, P33PFS 0008 C15Bh,
P34PFS 0008 C15Ch
b7 b6 b5 b4 b3 b2 b1 b0
— ISEL — — PSEL[3:0]
Address(es): P40PFS 0008 C160h, P41PFS 0008 C161h, P42PFS 0008 C162h, P43PFS 0008 C163h,
P44PFS 0008 C164h, P45PFS 0008 C165h, P46PFS 0008 C166h, P47PFS 0008 C167h
b7 b6 b5 b4 b3 b2 b1 b0
ASEL — — — — — — —
b7 b6 b5 b4 b3 b2 b1 b0
— — — — PSEL[3:0]
Table 20.11 Register Settings for Input/Output Pin Function in 100-Pin and 64-Pin
Pin
PSEL[3:0] Settings P54 P55
0000b (initial value) Hi-Z
0001b MTIOC4B MTIOC4D
0101b TMCI1 TMO3
Address(es): PA0PFS 0008 C190h, PA1PFS 0008 C191h, PA2PFS 0008 C192h, PA3PFS 0008 C193h,
PA4PFS 0008 C194h, PA5PFS 0008 C195h, PA6PFS 0008 C196h, PA7PFS 0008 C197h
b7 b6 b5 b4 b3 b2 b1 b0
Address(es): PB0PFS 0008 C198h, PB1PFS 0008 C199h, PB2PFS 0008 C19Ah, PB3PFS 0008 C19Bh,
PB4PFS 0008 C19Ch, PB5PFS 0008 C19Dh, PB6PFS 0008 C19Eh, PB7PFS 0008 C19Fh
b7 b6 b5 b4 b3 b2 b1 b0
— ISEL — — PSEL[3:0]
Address(es): PC0PFS 0008 C1A0h, PC1PFS 0008 C1A1h, PC2PFS 0008 C1A2h, PC3PFS 0008 C1A3h,
PC4PFS 0008 C1A4h, PC5PFS 0008 C1A5h, PC6PFS 0008 C1A6h, PC7PFS 0008 C1A7h
b7 b6 b5 b4 b3 b2 b1 b0
— — — — PSEL[3:0]
Address(es): PD0PFS 0008 C1A8h, PD1PFS 0008 C1A9h, PD2PFS 0008 C1AAh, PD3PFS 0008 C1ABh,
PD4PFS 0008 C1ACh, PD5PFS 0008 C1ADh, PD6PFS 0008 C1AEh, PD7PFS 0008 C1AFh
b7 b6 b5 b4 b3 b2 b1 b0
— ISEL — — PSEL[3:0]
Address(es): PE0PFS 0008 C1B0h, PE1PFS 0008 C1B1h, PE2PFS 0008 C1B2h, PE3PFS 0008 C1B3h,
PE4PFS 0008 C1B4h, PE5PFS 0008 C1B5h, PE6PFS 0008 C1B6h, PE7PFS 0008 C1B7h
b7 b6 b5 b4 b3 b2 b1 b0
Table 20.22 Register Settings for Input/Output Pin Function in 100-Pin and 64-Pin
Pin
PSEL[3:0]
Settings PE0 PE1 PE2 PE3 PE4 PE5
0000b Hi-Z
(initial value)
0001b — MTIOC4C MTIOC4A MTIOC4B MTIOC4D MTIOC4C
0010b — — — — MTIOC1A MTIOC2B
0111b — — — POE8# — —
1100b SCK12 TXD12 RXD12 CTS12# — —
TXDX12 RXDX12 RTS12#
SIOX12 SMISO12 SS12#
SMOSI12 SSCL12
SSDA12
Address(es): PH0PFS 0008 C1C8h, PH1PFS 0008 C1C9h, PH2PFS 0008 C1CAh, PH3PFS 0008 C1CBh
b7 b6 b5 b4 b3 b2 b1 b0
— ISEL — — PSEL[3:0]
Table 20.24 Register Settings for Input/Output Pin Function in 100-Pin, 64-Pin, and 48-Pin
Pin
PSEL[3:0] Settings PH0 PH1 PH2 PH3
0000b (initial value) Hi-Z
0101b — TMO0 TMRI0 TMCI0
0111b CACREF — — —
b7 b6 b5 b4 b3 b2 b1 b0
— — — — PSEL[3:0]
(5) Points to note regarding the port mode register (PMR), port direction register (PDR), and port mn pin function
selection register (PmnPFS) settings for pins that have multiplexed pin functions are listed in Table 20.26.
TIORH TIORL
TCR TMDR
TSR
TGRC
TGRD
TGRA
TGRB
TCNT
MTU3
Interrupt request signals
MTU3: TGIA3
TIER
TGIB3
TIORH TIORL
TCR TMDR
MTIOC3B TCIV3
TSR
MTIOC3C MTU4: TGIA4
TGRC
TGRD
TGRA
TGRB
MTU4
TCNT
MTIOC3D TGIB4
MTU4: MTIOC4A TGIC4
TIER
MTIOC4B TGID4
MTIOC4C TCIV4
MTIOC4D
TOER TOCR
TGCR
TCNTS
TCDR
TDDR
TCBR
Input pins
TCNTW
MTU5: TGIU5
TCNTU
TCNTV
TGRW
TGRU
TGRV
MTU5
TIOR
MTU5: MTIC5U
TIER
TCR
TSR
TGIV5
MTIC5V
Module data bus TGIW5
MTIC5W
BUS I/F
PCLK/4
PCLK/16 A/D converter start request signals
NFCR
MTU0 to 4: TRGAN
TSTR
PCLK/64
PCLK/256 MTU0: TRG0AN
PCLK/1024 TRG0BN
External clock: MTCLKA TRG0EN
TCR TMDR
TRG0FN
TSR
MTCLKB
MTCLKC MTU4: TRG4ABN
MTU2
TGRA
TGRB
TCNT
MTCLKD
Interrupt request signals
TIOR
TIER
MTU0: TGIA0
Control logic for MTU 0 to 2
MTIOC0B TGID0
TSR
MTIOC0C TGIE0
TGRA
TGRB
TCNT
MTU1
MTIOC0D TGIF0
MTU1: MTIOC1A TCIV0
TIOR
TIER
TCIU1
TSR
MTU2: TGIA2
TGRC
TGRD
TGRA
TGRB
TGRE
TGRF
TCNT
TGIB2
MTU1
TCIV2
TIER
MTU2
TCIU2
Address(es): MTU0.TCR 0008 8700h, MTU1.TCR 0008 8780h, MTU2.TCR 0008 8800h, MTU3.TCR 0008 8600h,
MTU4.TCR 0008 8601h, MTU5.TCRU 0008 8884h, MTU5.TCRV 0008 8894h, MTU5.TCRW 0008 88A4h
b7 b6 b5 b4 b3 b2 b1 b0
x: Don’t care
The MTU has a total of eight TCR registers, one each for MTU0 to MTU4 and three (TCRU, TCRV, and TCRW) for
MTU5.
TCR is an 8-bit readable/writable register that controls the TCNT operation for each channel. TCR values should be
specified only while TCNT operation is stopped.
Note: • Bits 7 to 2 are reserved in MTU5. These bits are read as 0. The write value should be 0.
Address(es): MTU0.TMDR 0008 8701h, MTU1.TMDR 0008 8781h, MTU2.TMDR 0008 8801h, MTU3.TMDR 0008 8602h,
MTU4.TMDR 0008 8603h
b7 b6 b5 b4 b3 b2 b1 b0
TMDR is an 8-bit readable/writable register that specifies the operating mode of each channel. TMDR values should be
specified only while TCNT operation is stopped.
x: Don't care
Note 1. PWM mode 2 cannot be set for MTU3 and MTU4.
Note 2. Phase counting mode cannot be set for MTU0, MTU3, and MTU4.
Note 3. Reset-synchronized PWM mode and complementary PWM mode can only be set for MTU3.
When MTU3 is set to reset-synchronized PWM mode or complementary PWM mode, the MTU4 settings become ineffective and
conform to the MTU3 setting, respectively. The initial values should be set for MTU4.
Reset-synchronized PWM mode and complementary PWM mode cannot be set for MTU0, MTU1 and MTU2.
Address(es): MTU0.TIORH 0008 8702h, MTU1.TIOR 0008 8782h, MTU2.TIOR 0008 8802h, MTU3.TIORH 0008 8604h,
MTU4.TIORH 0008 8606h
b7 b6 b5 b4 b3 b2 b1 b0
IOB[3:0] IOA[3:0]
Note 1. If the IOn[3:0] (n = A, B) bits are changed to an “output prohibited” setting (0000b or 0100b) while output of the low or high level
or toggling of the output in response to compare matches is in progress, the output becomes high impedance.
Address(es): MTU0.TIORL 0008 8703h, MTU3.TIORL 0008 8605h, MTU4.TIORL 0008 8607h
b7 b6 b5 b4 b3 b2 b1 b0
IOD[3:0] IOC[3:0]
Note 1. If the IOn[3:0] (n = C, D) bits are changed to an “output prohibited” setting (0000b or 0100b) while output of the low or high level
or toggling of the output in response to compare matches is in progress, the output becomes high impedance.
Address(es): MTU5.TIORU 0008 8886h, MTU5.TIORV 0008 8896h, MTU5.TIORW 0008 88A6h
b7 b6 b5 b4 b3 b2 b1 b0
— — — IOC[4:0]
The MTU has a total of 11 TIOR registers, two each for MTU0, MTU3, and MTU4, one each for MTU1 and MTU2, and
three (MTU5.TIORU/V/W) each for MTU5.
TIOR should be set when TMDR is set to select normal mode, PWM mode, or phase counting mode.
The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also
that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified.
When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer
register.
x: Don't care
x: Don't care
Note 1. When the MTU0.TMDR.BFB is set to 1 and MTU0.TGRD is used as a buffer register, this setting is invalid and input capture/
output compare is not generated.
x: Don't care
x: Don't care
x: Don't care
x: Don't care
Note 1. When the BFB bit in MTU3.TMDR is set to 1 and MTU3.TGRD is used as a buffer register, this setting is invalid and input
capture/output compare is not generated.
x: Don't care
x: Don't care
Note 1. When the BFB bit in MTU4.TMDR is set to 1 and MTU4.TGRD is used as a buffer register, this setting is invalid and input
capture/output compare is not generated.
x: Don't care
x: Don't care
Note 1. When the BFA bit in MTU0.TMDR is set to 1 and MTU0.TGRC is used as a buffer register, this setting is invalid and input
capture/output compare is not generated.
x: Don't care
x: Don't care
x: Don't care
x: Don't care
Note 1. When the BFA bit in MTU3.TMDR is set to 1 and MTU3.TGRC is used as a buffer register, this setting is invalid and input
capture/output compare is not generated.
x: Don't care
x: Don't care
Note 1. When the BFA bit in MTU4.TMDR is set to 1 and MTU4.TGRC is used as a buffer register, this setting is invalid and input
capture/output compare is not generated.
x: Don't care
b7 b6 b5 b4 b3 b2 b1 b0
TCNTCMPCLR is an 8-bit readable/writable register that specifies requests to clear MTU5.TCNTU, MTU5.TCNTV,
and MTU5.TCNTW.
Address(es): MTU0.TIER 0008 8704h, MTU1.TIER 0008 8784h, MTU2.TIER 0008 8804h, MTU3.TIER 0008 8608h,
MTU4.TIER 0008 8609h
b7 b6 b5 b4 b3 b2 b1 b0
The MTU has a total of seven TIER registers, two each for MTU0 and one each for MTU1 to MTU5.
TIER is an 8-bit readable/writable register that enables or disables interrupt requests in each channel.
TIER2 (MTU0)
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — TGIEF TGIEE
TIER (MTU5)
b7 b6 b5 b4 b3 b2 b1 b0
Address(es): MTU0.TSR 0008 8705h, MTU1.TSR 0008 8785h, MTU2.TSR 0008 8805h, MTU3.TSR 0008 862Ch,
MTU4.TSR 0008 862Dh
b7 b6 b5 b4 b3 b2 b1 b0
TCFD — — — — — — —
x: Undefined
The MTU has a total of five TSR registers, one each for MTU0 to MTU4.
TSR is an 8-bit readable/writable register that indicates the status of each channel.
Address(es): MTU0.TBTM 0008 8726h, MTU3.TBTM 0008 8638h, MTU4.TBTM 0008 8639h
b7 b6 b5 b4 b3 b2 b1 b0
The MTU has a total of three TBTM registers, one each for MTU0, MTU3 and MTU4.
TBTM is an 8-bit readable/writable register that specifies the timing for transferring data from the buffer register to the
timer general register in PWM mode.
b7 b6 b5 b4 b3 b2 b1 b0
x: Undefined
Note: • TADCR must not be accessed in 8-bit units; it should be accessed in 16-bit units.
Note: • When interrupt skipping is disabled (the T3AEN and T4VEN bits in the timer interrupt skipping set register (TITCR) are cleared to
0 or the interrupt skipping count setting bits (T3ACOR and T4VCOR) in TITCR are cleared to 0), do not link A/D converter start
requests with interrupt skipping operation (clear the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in the timer A/D converter start
request control register (TADCR) to 0).
Note: • If link with interrupt skipping is enabled while interrupt skipping is disabled, A/D converter start requests will not be issued.
Note 1. Do not set any bit from among b6 and b4 to b0 to 1 unless complementary PWM mode is not selected.
TADCR is a 16-bit readable/writable register that enables or disables A/D converter start requests and specifies whether
to link A/D converter start requests with interrupt skipping operation.
Note 1. Data is transferred from the cycle set buffer register to the cycle set register when the crest of the MTU4.TCNT count is reached
in complementary PWM mode, when a compare match occurs between MTU3.TCNT and MTU3.TGRA in reset-synchronized
PWM mode, or when a compare match occurs between MTU4.TCNT and MTU4.TGRA in PWM mode 1 or normal operation
mode.
Note 2. These settings are prohibited when complementary PWM mode is not selected.
21.2.10 Timer A/D Converter Start Request Cycle Set Registers A and B (TADCORA
and TADCORB)
Note: • MTU4.TADCORA and MTU4.TADCORB must not be accessed in 8-bit units; they should always be accessed in
16-bit units.
TADCORA and TADCORB are 16-bit readable/writable registers. When the MTU4.TCNT count reaches the value in
TADCORA or TADCORB, a corresponding A/D converter start request will be issued.
The TADCORA and TADCORB values after reset are FFFFh.
21.2.11 Timer A/D Converter Start Request Cycle Set Buffer Registers A and B
(TADCOBRA and TADCOBRB)
Note: • MTU4.TADCORA and MTU4.TADCORB must not be accessed in 8-bit units; they should always be accessed in
16-bit units.
TADCOBRA and TADCOBRB are 16-bit readable/writable registers. When the crest or trough of the MTU4.TCNT
count is reached, these register values are transferred to TADCORA and TADCORB, respectively.
The TADCOBRA and TADCOBRB values after reset are FFFFh.
Address(es): MTU0.TCNT 0008 8706h, MTU1.TCNT 0008 8786h, MTU2.TCNT 0008 8806h, MTU3.TCNT 0008 8610h,
MTU4.TCNT 0008 8612h, MTU5.TCNTU 0008 8880h, MTU5.TCNTV 0008 8890h, MTU5.TCNTW 0008 88A0h
Note: • The TCNT counters must not be accessed in 8-bit units; they should always be accessed in 16-bit units.
The MTU has a total of eight TCNT counters, one each for MTU0 to MTU4 and three (MTU5.TCNTU, TCNTV, and
TCNTW) for MTU5. TCNT is a 16-bit readable/writable counter.
TCNT is initialized to 0000h by a reset.
Address(es): MTU0.TGRA 0008 8708h, MTU0.TGRB 0008 870Ah, MTU0.TGRC 0008 870Ch, MTU0.TGRD 0008 870Eh,
MTU0.TGRE 0008 8720h, MTU0.TGRF 0008 8722h, MTU1.TGRA 0008 8788h, MTU1.TGRB 0008 878Ah,
MTU2.TGRA 0008 8808h, MTU2.TGRB 0008 880Ah, MTU3.TGRA 0008 8618h, MTU3.TGRB 0008 861Ah,
MTU3.TGRC 0008 8624h, MTU3.TGRD 0008 8626h, MTU4.TGRA 0008 861Ch, MTU4.TGRB 0008 861Eh,
MTU4.TGRC 0008 8628h, MTU4.TGRD 0008 862Ah, MTU5.TGRU 0008 8882h, MTU5.TGRV 0008 8892h,
MTU5.TGRW 0008 88A2h
Note: • The TGR registers must not be accessed in 8-bit units; they should always be accessed in 16-bit units. TGR
registers are initialized to FFFFh.
The MTU has a total of 21 TGR registers, six for MTU0, two each for MTU1 and MTU2, four each for MTU3 and
MTU4, and three for MTU5. TGR is a 16-bit readable/writable register.
TGRA, TGRB, TGRC, and TGRD function as either output compare or input capture registers. TGRC and TGRD for
MTU0, MTU3, and MTU4 can also be designated for operation as buffer registers. TGR buffer register combinations are
TGRA and TGRC, and TGRB and TGRD.
MTU0.TGRE and MTU0.TGRF function as compare registers. When the MTU0.TCNT count matches the
MTU0.TGRE value, an A/D converter start request can be issued. TGRF can also be designated for operation as a buffer
register. TGR buffer register combination is TGRE and TGRF.
MTU5.TGRU, MTU5.TGRV, and MTU5.TGRW function as compare match, input capture, or external pulse width
measurement registers.
b7 b6 b5 b4 b3 b2 b1 b0
TSTR (MTU5)
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — — RWE
TRWER enables or disables access to the registers and counters that have write-protection capability against accidental
modification in MTU3 and MTU4.
b7 b6 b5 b4 b3 b2 b1 b0
Note 1. To output the inactive level from each pin when the MTU output is set to disabled, first set the data direction register (PDR) and
port output data register (PODR) of I/O ports to output the inactive level from general I/O ports, and then set the port mode
register (PMR) to use general I/O ports.
TOER enables or disables output settings for output pins MTIOC4D, MTIOC4C, MTIOC3D, MTIOC4B, MTIOC4A,
and MTIOC3B.
These pins do not output correctly if the TOER bits have not been set. In MTU3 and MTU4, set TOER prior to setting
TIOR.
Set TOER after clearing the CST3 and CST4 bits in TSTR to 0 (see Figure 21.35 and Figure 21.38).
b7 b6 b5 b4 b3 b2 b1 b0
Note 1. Setting the TOCR1.TOCL bit to 1 prevents accidental modification when the CPU goes out of control.
Note 2. Clearing the TOCR1.TOCS bit to 0 makes this bit setting valid.
Note 3. If dead-time is not generated, the negative-phase output is always the exact inverse of the positive-phase output. In this case,
only the OLSP bit is valid.
Note 4. This bit can be set to 1 only once after a power on reset. After 1 is written, 0 cannot be written to the bit.
TOCR1 is 8-bit readable/writable registers that enable or disable PWM-synchronized toggle output in complementary
PWM mode and reset-synchronized PWM mode, and control inversion of PWM output level.
Note: • The initial output value of negative-phase waveform changes to an active level after the dead time has passed since counting
starts.
Figure 21.2 shows an example of output in complementary PWM mode (one phase) when OLSN = 1 and OLSP = 1.
MTU3.TCNT value
MTU3.TGRA
MTU3.TCNT
MTU4.TCNT
MTU4.TGRA
TDDR
0000h Time
Compare match
output (up-count)
Initial Compare match output
Positive-phase output Active level
output (down-count)
Initial Compare match output
output (down-count)
Active Compare match
Negative-phase output output (up-count) Active level
level
b7 b6 b5 b4 b3 b2 b1 b0
Note 1. Setting the TOCR1.TOCS bit to 1 makes this bit setting valid.
Note 2. If dead-time is not generated, the negative-phase output is always the exact inverse of the positive-phase output. In these cases,
only the OLSiP bits are valid (i = 1 to 3).
TOCR2 control inversion of PWM output level in complementary PWM mode and reset-synchronized PWM mode.
Note: • The initial output value of negative-phase waveform changes to an active level after the dead time has passed since counting
starts.
Note: • The initial output value of negative-phase waveform changes to an active level after the dead time has passed since counting
starts.
Note: • The initial output value of negative-phase waveform changes to an active level after the dead time has passed since counting
starts.
b7 b6 b5 b4 b3 b2 b1 b0
TOLBR is 8-bit readable/writable registers that function as buffer registers for TOCR2 and specify the PWM output level
in complementary PWM mode and reset-synchronized PWM mode.
Figure 21.3 shows an example of the PWM output level setting procedure in buffer operation.
[2] Use bits BF1 and BF0 in TOCR2 to select the TOLBR buffer transfer
timing. Use bits OLS3N to OLS1N and OLS3P to OLS1P to specify the
PWM output levels.
Set TOCR2 [2]
[3] The TOLBR initial setting must be the same value as specified in bits
OLS3N to OLS1N and OLS3P to OLS1P in TOCR2.
Figure 21.3 Example of PWM Output Level Setting Procedure in Buffer Operation
b7 b6 b5 b4 b3 b2 b1 b0
— BDC N P FB WF VF UF
TGCR control the output waveform necessary for brushless DC motor control in reset-synchronized PWM mode and
complementary PWM mode. These register settings are ineffective for anything other than complementary PWM mode
and reset-synchronized PWM mode.
Note: • Accessing the TCNTS in 8-bit units is prohibited. Always access in 16-bit units.
TCNTS is 16-bit read-only counters that are used only in complementary PWM mode.
The TCNTS value after reset is 0000h.
Note: • Accessing the TDDR in 8-bit units is prohibited. Always access in 16-bit units.
TDDR is 16-bit registers, used only in complementary PWM mode, that specify the MTU3.TCNT and MTU4.TCNT
counter offset value. In complementary PWM mode, when the MTU3.TCNT and MTU4.TCNT counters are cleared and
then restarted, the TDDR value is loaded into the MTU3.TCNT counter and the count operation starts. The TDDR value
after reset is FFFFh.
Note: • Accessing the TCDR in 8-bit units is prohibited. Always access in 16-bit units.
TCDR is 16-bit registers used only in complementary PWM mode. Set half the PWM carrier cycle as the TCDR value.
TCDR is constantly compared with the TCNTS counter in complementary PWM mode, and when a match occurs, the
TCNTS counter switches direction (down-count to up-count). The TCDR value after reset is FFFFh.
Note: • Accessing the TCBR in 8-bit units is prohibited. Always access in 16-bit units.
TCBR is 16-bit registers, used only in complementary PWM mode, that function as buffer registers for TCDR. The
TCBR value is transferred to TCDR with the transfer timing set in TMDR. The TCBR value after reset is FFFFh.
b7 b6 b5 b4 b3 b2 b1 b0
Note 1. When 0 is specified for the interrupt skipping count, no interrupt skipping will be performed.
Before changing the interrupt skipping count, be sure to clear the TITCR.T3AEN and TITCR.T4VEN bits to 0 to clear the timer
interrupt skipping counter (TITCNT).
b7 b6 b5 b4 b3 b2 b1 b0
— T3ACNT[2:0] — T4VCNT[2:0]
Note: • To clear the TITCNT, clear the T3AEN and T4VEN bits in TITCR to 0.
TITCNT is 8-bit readable counters. TITCNT retain their values even after stopping the count operation of MTU4.TCNT
and MTU3.TCNT.
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — BTE[1:0]
TBTER is 8-bit readable/writable registers that enable or disable transfer from the buffer registers used in
complementary PWM mode to the temporary registers and specify whether to link the transfer with interrupt skipping
operation.
Note 1. Data is transferred according to the MD3 to MD0 bit setting in TMDR. For details, refer to section 21.3.8, Complementary PWM
Mode.
Note 2. When interrupt skipping is disabled (the T3AEN and T4VEN bits are cleared to 0 in the timer interrupt skipping set register
(TITCR) or the interrupt skipping count setting bits (T3ACOR and T4VCOR) in TITCR are cleared to 0), be sure to disable link of
buffer transfer with interrupt skipping (clear the BTE1 bit in the timer buffer transfer set register (TBTER) to 0). If link with
interrupt skipping is enabled while interrupt skipping is disabled, buffer transfer will not be performed.
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — — TDER
TDER is 8-bit readable/writable registers that control dead time generation in complementary PWM mode. The MTU3
has one TDER register. TDER should be modified only while TCNT stops.
b7 b6 b5 b4 b3 b2 b1 b0
CCE — — — — — — WRE
Note 1. Do not set this bit to 1 unless complementary PWM mode is selected.
Note 2. Do not set this bit to 1 unless complementary PWM mode 1 is selected.
TWCR is 8-bit readable/writable registers. TWCR controls the output waveform when synchronous counter clearing
occurs in MTU3.TNCT and MTU4.TNCT in complementary PWM mode and specifies whether to clear the counters at
MTU3.TGRA compare match.
The CCE bit and WRE bit in TWCR should be modified only while TCNT stops.
Address(es): MTU0.NFCR 0008 8690h, MTU1.NFCR 0008 8691h, MTU2.NFCR 0008 8692h, MTU3.NFCR 0008 8693h,
MTU4.NFCR 0008 8694h
b7 b6 b5 b4 b3 b2 b1 b0
Note 1. These bits are reserved in the NFCRs for MTU1 and MTU2. These bits are read as 0, and writing to them is not possible.
MTUn.NFCR is 8-bit readable and writable register (n = 0 to 4). These registers control enabling and disabling of the
noise filters for the MTIOCnm (n = 0 to 4; m = A to D) pins and sets the sampling clocks for the noise filters.
NFCR (MTU5)
b7 b6 b5 b4 b3 b2 b1 b0
MTU5.NFCR is 8-bit readable and writable register. This register controls enabling and disabling of the noise filters for
the MTIC5m (m = U, V, W) pins and sets the sampling clock for the noise filters.
21.3 Operation
Operation selection [1] Set the TPSC[2:0] bits in TCR to select the counter
clock. At the same time, set the CKEG[1:0] bits in
TCR to select the input clock edge.
Select counter clock [1]
Select counter clearing [3] Designate the TGR selected in [2] as an output
[2]
source compare register by means of TIOR.
Select output compare [4] Set the periodic counter cycle in the TGR selected
[3]
register in [2].
Set period [4] [5] Set the CST bit in TSTR to 1 to start the counter
operation.
Start count operation [5]
Start count operation [5]
Free-running counter
Periodic counter
TCNT value
FFFFh
0000h Time
CST bit
TCIV
When compare match is selected as the TCNT clearing source, TCNT for the relevant channel performs periodic count
operation. TGR for setting the cycle is designated as an output compare register, and counter clearing by compare match
is selected by means of bits CCLR[2:0] in TCR. After the settings have been made, TCNT starts up-count operation as a
periodic counter when the corresponding bit in TSTR is set to 1. When the count matches the value in TGR, TCNT is
cleared to 0000h.
If the value of the corresponding TGIE bit in TIER is 1 at this point, the MTU requests an interrupt. After a compare
match, TCNT starts counting up again from 0000h.
Figure 21.6 illustrates periodic counter operation.
0000h Time
TSTR.CST
TGI
Output selection
[1] Select initial value low output or high output, and
compare match output value low output, high output,
or toggle output, by means of TIOR. The set initial
Select waveform output [1] value is output at the MTIOC pin until the first
mode compare match occurs.
Set output timing [2] [3] Set the CST bit in TSTR to 1 to start the count
operation.
Waveform output
Figure 21.7 Example of Procedure for Setting Waveform Output by Compare Match
TCNT value
FFFFh
TGRA
TGRB
0000h Time
No change No change
High output
MTIOCA
No change No change Low output
MTIOCB
TCNT value
Counter cleared by TGRB compare match
FFFFh
TGRB
TGRA
0000h Time
Toggle output
MTIOCB
0160h
0010h
0005h
0000h Time
MTIOCA
MTIOCB
TGRB 0180h
Synchronous operation
selection
Set synchronous
[1]
operation
Yes
[1] Set 1 in the SYNC bit in TSYR corresponding to the channels to be designated for synchronous operation.
[2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the same
value is simultaneously written to the other TCNT counters.
[3] Use the CCLR[2:0] bits in TCR to specify TCNT clearing by input capture/output compare, etc.
[4] Use the CCLR[2:0] bits in TCR to designate synchronous clearing for the counter clearing source.
[5] Set 1 in the CST bit in TSTR for the relevant channels, to start the count operation.
MTIOC0A
MTIOC1A
MTIOC2A
Input capture
signal
Select TGR function [1] [2] Designate TGR for buffer operation with bits BFA
and BFB in TMDR.
Set buffer operation [2] [3] Set the CST bit in TSTR to 1 to start the count
operation.
Buffer operation
TCNT value
MTU0.TGRB 0520h
0450h
0200h
MTU0.TGRA
0000h Time
MTIOCA
TCNT value
0F07h
09FBh
0532h
0000h Time
MTIOCA
(3) Selecting Timing for Transfer from Buffer Registers to Timer General Registers in Buffer
Operation
The timing for transfer from buffer registers to timer general registers can be selected in PWM mode 1 or 2 for MTU0 or
in PWM mode 1 for MTU3 and MTU4 by setting the timer buffer operation transfer mode registers (MTU0.TBTM,
MTU3.TBTM, and MTU4.TBTM). Either compare match (initial setting) or TCNT clearing can be selected for the
transfer timing. TCNT clearing as transfer timing is one of the following cases.
Figure 21.19 shows an operation example in which PWM mode 1 is designated for MTU0 and buffer operation is
designated for MTU0.TGRA and MTU0.TGRC. The settings used in this example are MTU0.TCNT clearing by
compare match B, high output at compare match A, and low output at compare match B. The TTSA bit in MTU0.TBTM
is set to 1.
MTU0.TCNT
value
MTU0.TGRB
0520h
0450h
0200h
MTU0.TGRA
0000h Time
MTIOCA
Figure 21.19 Example of Buffer Operation When MTU0.TCNT Clearing is Selected for MTU0.TGRC-to-
MTU0.TGRA Transfer Timing
Note: • When phase counting mode is set for MTU1 or MTU2, the counter clock setting is invalid and the counters
operate independently in phase counting mode.
For simultaneous input capture of MTU1.TCNT and MTU2.TCNT during cascaded operation, additional input capture
input pins can be specified by the timer input capture control register (TICCR). The input-capture condition is of edges in
the signal produced by taking the logical OR of the input level on the main input pin and the input level on the added
input pin. Accordingly, if either is at the high, a change in the level of the other will not produce an edge for detection.
For details, see (4) Cascaded Operation Example (c). For input capture in cascade connection, refer to section 21.6.22,
Simultaneous Input Capture in MTU1.TCNT and MTU2.TCNT in Cascade Connection.
Table 21.45 lists the TICCR setting and input capture input pins.
Set cascading [1] [2] Set the CST bit in TSTR for the upper and lower
channels to 1 to start the count operation.
Cascaded operation
MTCLKC
MTCLKD
MTU2.TCNT FFFD FFFE FFFF 0000 0001 0002 0001 0000 FFFF
MTU2.TCNT
value
FFFFh
C256h
6128h
0000h Time
MTIOC1A
MTIOC2A
MTU2.TGRA C256h
As TICCR.I1AE is 0, data is not captured in MTU2.TGRA at
the MTIOC1A input timing.
MTU2.TCNT
value
FFFFh
C256h
9192h
6128h
2064h
0000h Time
MTIOC1A *1
*1
MTIOC2A
Note 1. When either input signal is at the high level, an edge in the other input signal does not act as the
condition for capture.
MTU0.TCNT
value
Compare match between MTU0.TCNT and TGRA
MTU0.TGRA
0000h Time
MTU2.TCNT value
FFFFh
D000h
0000h Time
MTIOC1A
MTIOC2A
MTU1.TGRA 0513h
MTU2.TGRA D000h
Note: • In PWM mode 2, PWM output is not possible for the TGR register in which the PWM cycle is set.
PWM mode [1] Set the TPSC[2:0] bits in TCR to select the counter clock.
At the same time, set the CKEG[1:0] bits in TCR to select
the input clock edge.
Select counter clock [1]
[2] Set the CCLR[2:0] bits in TCR to select the TGR to be used
as the TCNT clearing source.
Select counter clearing [2]
source
[3] Select the PWM mode with bits MD[3:0] in TMDR.
[5] Set the cycle in the TGR selected in [2], and set the duty in
Select waveform output
level [4] the other TGR.
[6] Set the CST bit in TSTR to 1 to start the count operation.
Set TGR [5]
PWM mode
TGRA
TGRB
0000h Time
MTIOCA
MTU1.TGRB
MTU1.TGRA
MTU0.TGRD
MTU0.TGRC
MTU0.TGRB
MTU0.TGRA
0000h
Time
MTIOC0A
MTIOC0B
MTIOC0C
MTIOC0D
MTIOC1A
Figure 21.28 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode.
TCNT value
TGRB modified
TGRA
TGRB
TGRB TGRB modified modified
0000h Time
MTIOCA 0% duty
TGRB modified
TGRA
TGRB modified
0000h Time
TGRB
TGRB modified
0000h Time
Select phase counting [1] [2] Set the CST bit in TSTR to 1 to start the
mode count operation.
MTCLKA (MTU1)
MTCLKC (MTU2)
MTCLKB (MTU1)
MTCLKD (MTU2)
TCNT value
Up-counting Down-counting
Time
: Rising edge
: Falling edge
MTCLKA (MTU1)
MTCLKC (MTU2)
MTCLKB (MTU1)
MTCLKD (MTU2)
TCNT value
Up-counting Down-counting
Time
: Rising edge
: Falling edge
MTCLKA (MTU1)
MTCLKC (MTU2)
MTCLKB (MTU1)
MTCLKD (MTU2)
TCNT value
Up-counting Down-counting
Time
: Rising edge
: Falling edge
MTCLKA (MTU1)
MTCLKC (MTU2)
MTCLKB (MTU1)
MTCLKD (MTU2)
TCNT value
Up-counting Down-counting
Time
: Rising edge
: Falling edge
MTU1
MTCLKA Edge
detection MTU1.TCNT
MTCLKB circuit
MTU1.TGRA
(Speed cycle capture)
MTU1.TGRB
(Position cycle capture)
MTU0.TCNT
MTU0.TGRA
(Speed control cycle)
MTU0.TGRC
(Position control cycle)
MTU0.TGRB
(Pulse width capture)
MTU0.TGRD
(Buffer operation)
MTU0
Reset-synchronized [1] Clear the CST3 and CST4 bits in TSTR to 0 to stop the TCNT
PWM mode operation. Specify the reset-synchronized PWM mode while
MTU3.TCNT and MTU4.TCNT are stopped.
Stop count operation [1] [2] Set the Pmn pin function control register and the port I/O register.
[3] Set bits TPSC[2:0] and CKEG[1:0] In the MTU3.TCR to select the
PFS setting [2] counter clock and clock edge for channel 3. Set the CCLR[2:0]
bits in the MTU3.TCR to select TGRA compare-match as a
Select counter clock and counter clear source.
counter clear source [3]
[4] When performing brushless DC motor control, set bit BDC in the
timer gate control register (TGCR) and set the feedback signal
input source and output chopping or gate signal direct output.
Brushless DC motor
control setting [4]
[5] Set MTU3.TCNT and MTU4.TCNT to 0000h.
TCNT setting [5] [6] MTU3.TGRA is the cycle register. Set the waveform cycle value
in MTU3.TGRA. Set the transition timing of the PWM output
waveforms in MTU3.TGRB, MTU4.TGRA, and MTU4.TGRB. Set
TGR setting [6] times within the compare match range of MTU3.TCNT.
Reset-synchronized PWM mode [9] Set the enabling/disabling of the PWM waveform output pin in
TOER.
[10] Set the CST3 bit in the TSTR to 1 to start the count operation.
MTU3.TGRA
MTU3.TGRB
MTU4.TGRA
MTU4.TGRB
0000h
Time
MTIOC3B
MTIOC3D
MTIOC4A
MTIOC4C
MTIOC4B
MTIOC4D
Figure 21.36 Example of Reset-Synchronized PWM Mode Operation (When TOCR1’s OLSN = 1 and OLSP = 1)
Note 1. Avoid setting the MTIOC3C pin as a timer I/O pin in complementary PWM mode.
Note 1. Access can be enabled or disabled according to the setting in TRWER (timer read/write enable register).
MTU3.TGRA compare-
MTU4.TCNT underflow
match interrupt
MTU3.TGRC TCBR
interrupt
PWM cycle
Comparator Match output
signal
Output controller
PWM output 1
PWM output 2
MTU3.TCNT TCNTS MTU4.TCNT
MTU4.TGRA
MTU4.TGRB
Temp 2
Temp 3
Temp 1
POE1#
POE2#
POE3#
External cutoff
interrupt
Figure 21.37 Block Diagram of MTU3 and MTU4 in Complementary PWM Mode
[1] Clear bits CST3 and CST4 in the timer start register (TSTR) to 0 to stop
Complementary PWM mode timer counter (TCNT) operation. Specify complementary PWM mode while
MTU3.TCNT and MTU4.TCNT are stopped.
[2] Set the Pmn pin function control register and the port I/O register.
Stop count operation [1]
[3] Set the same counter clock and clock edge for MTU3 and MTU4 with bits
TPSC[2:0] and bits CKEG[1:0] in the timer control register (TCR). Use bits
CCLR[2:0] to set synchronous clearing only when restarting by
PFS setting [2] synchronous clearing with another channel during complementary PWM
mode operation.
[4] When performing brushless DC motor control, set bit BDC in the timer gate
Select counter clock and control register (TGCR) and set the feedback signal input source and
counter clear source [3]
output chopping or gate signal direct output.
[9] Set the dead time in the dead time register (TDDR), 1/2 the carrier cycle in
the timer cycle data register (TCDR) and timer cycle buffer register
Enable/disable dead time [8] (TCBR), and 1/2 the carrier cycle plus the dead time in MTU3.TGRA and
generation MTU3.TGRC. When no dead time generation is selected, set 1 in TDDR
and 1/2 the carrier cycle + 1 in MTU3.TGRA and MTU3.TGRC.
Dead time, carrier cycle [10] Enable or disable toggle output synchronized with the PWM cycle using bit
setting [9]
PSYE in the timer output control register 1 (TOCR1), and set the PWM
output level with bits OLSP and OLSN.
When specifying the PWM output level by using TOLBR as a buffer for
Enable PWM cyclic output, MTU2.TOCR2, see Figure 21.3, Example of PWM Output Level Setting
set PWM output level [10] Procedure in Buffer Operation.
[12] Set enabling/disabling of PWM waveform output pin output in the timer
Enable waveform output [12] output master enable register (TOER).
[13] Set bits CST3 and CST4 in TSTR to 1 simultaneously to start the count
operation.
Start count operation [13]
MTU3.TCNT
MTU4.TCNT
TCNTS
Counter value
MTU3.TGRA
TCDR
MTU3.TCNT
MTU4.TCNT
TCNTS
TDDR
0000h
Time
MTU3.TGRA
TCNTS
TCDR
MTU3.TCNT
MTU4.TGRA MTU4.TCNT
MTU4.TGRC
TDDR
0000h
Buffer register
6400h 0080h
MTU4.TGRC
Compare register
6400h 0080h
MTU4.TGRA
Note: • The value set in MTU3.TGRC should be the sum of 1/2 the PWM carrier cycle set in TCBR and dead time Td set in TDDR.
When dead time generation is disabled by TDER, TGRC should be set to 1/2 the PWM carrier cycle + 1.
Ta Tb1 Ta Tb2 Ta
MTU3.TGRA
= TCDR + 1 TCNTS
TCDR
MTU3.TCNT
MTU4.TCNT
MTU4.TGRA
MTU4.TGRC
TDDR = 1
0000h
Buffer register
MTU4.TGRC Data 1 Data 2
Compare register
MTU4.TGRA Data 1 Data 2
The settings should be made so as to achieve the following relationship between registers TCDR and TDDR.
TCDR setting > TDDR setting × 2 + 2
The MTU3.TGRA and MTU3.TCDR settings are made by setting values in buffer registers MTU3.TGRC and
MTU3.TCBR. The values set in MTU3.TGRC and MTU3.TCBR are transferred simultaneously to MTU3.TGRA and
MTU3.TCDR with the transfer timing selected with the TMDR.MD[3:0] bits.
The new PWM cycle is reflected from the next cycle when data is updated at the crest, or from the current cycle when
updated in the trough. Figure 21.42 illustrates the operation when the PWM cycle is updated at the crest.
See the following section (h), Register Data Updating, for the method of updating the data in each buffer register.
MTU3.TCNT
MTU3.TGRA MTU4.TCNT
Time
R01UH0292EJ0110 Rev.1.10
temporary register temporary register temporary register temporary register temporary register temporary register
to compare register to compare register to compare register to compare register to compare register to compare register
Counter value
MTU3.TGRA
MTU4.TGRC
MTU4.TGRA
0000h
Time
MTU3.TCNT values
MTU3.TCNT
MTU4.TCNT
MTU4.TGRA
TDDR
Time
Initial output Dead time
Positive phase
output Active level
Negative phase
output Active level
MTU3.TCNT values
MTU3.TCNT
MTU4.TCNT
TDDR
MTU4.TGRA
Time
Initial output
Positive phase
output Active level
Negative phase
output
The positive-phase and negative-phase turn-off timing is generated by a compare match with the MTU3.TCNT counter,
and the turn-on timing by a compare match with the MTU4.TCNT counter, which operates with a delay of the dead time
behind the MTU3.TCNT counter. In the T1 period, compare match a that turns off the negative phase has the highest
priority, and compare matches before a are ignored. In the T2 period, compare match c that turns off the positive phase
has the highest priority, and compare matches before c are ignored.
In most cases, compare matches occur in the order a b c d (or c d a' b') as shown in Figure 21.46.
If compare matches deviate from the a b c d order, since the time for which the negative phase is off is shorter
than twice the dead time, the positive phase is not turned on. If compare matches deviate from the c d a' b' order,
since the time for which the positive phase is off is shorter than twice the dead time, the negative phase is not turned on.
As shown in Figure 21.47, if compare match c follows compare match a before compare match b, compare match b is
ignored and the negative phase is turned on by compare match d. This is because turning off the positive phase has higher
priority due to the occurrence of compare match c (positive-phase off timing) before compare match b (positive-phase on
timing) (consequently, the waveform does not change because the positive phase goes from off to off).
Similarly, in the example in Figure 21.48, compare match a' with new data in the temporary register occurs before
compare match c, but until compare match c, which turns off the positive phase, other compare matches are ignored. As
a result, the negative phase is not turned on.
Thus, in complementary PWM mode, compare matches at turn-off timings take precedence, and turn-on timing compare
matches that occur before a turn-off timing compare match are ignored.
TCDR
a b
a' b'
TDDR
0000h
a b
TDDR
0000h
Positive phase output
TCDR
a b
TDDR
c d
a' b'
0000h
Positive phase output
TCDR
a b
a' b'
TDDR
0000h
Figure 21.49 Example of 0% and 100% Waveform Output in Complementary PWM Mode (1)
TCDR
a b
a b
TDDR
0000h
c d
Positive phase output
Figure 21.50 Example of 0% and 100% Waveform Output in Complementary PWM Mode (2)
TCDR
a b
TDDR
0000h
Figure 21.51 Example of 0% and 100% Waveform Output in Complementary PWM Mode (3)
TCDR
a b
TDDR
0000h
c b' d a'
Positive phase output
Figure 21.52 Example of 0% and 100% Waveform Output in Complementary PWM Mode (4)
TCDR
TDDR
0000h
Positive phase output
Figure 21.53 Example of 0% and 100% Waveform Output in Complementary PWM Mode (5)
MTU3.TGRA
MTU3.TCNT
MTU4.TCNT
0000h
Toggle output
MTIOC3A pin
Figure 21.54 Example of Toggle Output Waveform Synchronized with PWM Output
TCNTS
MTU3.TGRA
TCDR
MTU3.TCNT
MTU4.TCNT
TDDR
0000h
MTU1.TCNT
(n) Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode
Setting the WRE bit in TWCR to 1 suppresses initial output when synchronous counter clearing occurs in the Tb interval
at the trough in complementary PWM mode and controls abrupt change in duty cycle at synchronous counter clearing.
Initial output suppression through setting WRE bit to 1 is applicable only when synchronous clearing occurs in the Tb
interval at the trough as indicated by (10) or (11) in Figure 21.56. When synchronous clearing occurs outside that
interval, the initial value specified by the OLSN and OLSP bits in TOCR1 is output. Even in the Tb interval at the trough,
if synchronous clearing occurs in the initial output period (indicated by (1) in Figure 21.56) immediately after the
counters start operation, initial value output is not suppressed.
Synchronous clearing generated in MTU0 to MTU2 can cause counter clearing in the MTU.
Counter start
Tb interval Tb interval Tb interval
MTU3.TGRA
TCDR MTU3.TCNT
MTU3.TGRB
MTU4.TCNT
TDDR
0000h
Positive phase
output
Negative phase
output
Output waveform is active-low
(1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11)
Example of Procedure for Setting Output Waveform Control at Synchronous Counter Clearing in
Complementary PWM Mode.
An example of the procedure for setting output waveform control at synchronous counter clearing in complementary
PWM mode is shown in Figure 21.57.
Output waveform control at [1] Clear bits CST3 and CST4 in the timer start
synchronous counter clearing
register (TSTR) to 0 to stop count operation.
Specify TWCR while MTU3.TCNT and
MTU4.TCNT are stopped.
Stop count operation [1]
[2] Read bit WRE in TWCR and then write 1 to it to
suppress initial value output at counter clearing.
Set TWCR and
complementary PWM mode [2] [3] Set bits CST3 and CST4 in TSTR to 1 to start
count operation.
Figure 21.57 Example of Procedure for Setting Output Waveform Control at Synchronous Counter Clearing in
Complementary PWM Mode
Examples of Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode
Figure 21.58 to Figure 21.61 show examples of output waveform control in which the MTU operates in
complementary PWM mode and synchronous counter clearing is generated while the WRE bit in TWCR is set to 1. In
the examples shown in Figure 21.58 to Figure 21.61, synchronous counter clearing occurs at timing (3), (6), (8), and
(11) shown in Figure 21.56, respectively.
MTU3.TGRA
TCDR
MTU3.TGRB
MTU3.TCNT
MTU4.TCNT
TDDR
0000h
Positive phase
output
Negative phase
output
Output waveform is active-low.
Synchronous clearing
Bit WRE = 1
MTU3.TGRA
TCDR
MTU3.TGRB
MTU3.TCNT
MTU4.TCNT
TDDR
0000h
Positive phase
output
Negative phase
output
Output waveform is active-low.
MTU3.TGRA
TCDR
MTU3.TGRB
MTU3.TCNT
MTU4.TCNT
TDDR
0000h
Positive phase
output
Negative phase
output
Output waveform is active-low.
MTU3.TGRA
TCDR
MTU3.TGRB
MTU3.TCNT
MTU4.TCNT
TDDR
0000h
Positive phase
output
Initial value output is suppressed.
Negative phase
output
Output waveform is active-low.
Counter cleared by
MTU3.TGRA compare match
MTU3.TGRA
TCDR
MTU3.TGRB
TDDR
0000h
Positive phase
output
Negative phase
output
Output waveform is active-high.
(p) Example of Waveform Output for Driving AC Synchronous Motor (Brushless DC Motor)
In complementary PWM mode, a brushless DC motor can easily be controlled using the timer gate control register
(TGCR). Figure 21.63 to Figure 21.66 show examples of brushless DC motor driving waveforms created using TGCR.
To switch the output phases for a 3-phase brushless DC motor by means of external signals detected with a Hall element,
etc., clear the FB bit in TGCR to 0. In this case, the external signals indicating the magnetic pole position should be input
to timer input pins MTIOC0A, MTIOC0B, and MTIOC0C in MTU0 (set with PFS). When an edge is detected at pin
MTIOC0A, MTIOC0B, or MTIOC0C, the output on/off state is switched automatically.
When the FB bit is 1, the output on/off state is switched when the UF, VF, or WF bit in TGCR is cleared to 0 or set to 1.
The driving waveforms are output from the 6-phase output pins for complementary PWM mode.
With this 6-phase output, while the output is turned on, chopping output is available through complementary PWM mode
output function by setting the N bit or P bit in TGCR to 1. When the N bit or P bit is 0, the level output is selected.
The active level of the 6-phase output (on output level) can be set with the OLSN and OLSP bits in the timer output
control register1 (TOCR1) regardless of the setting of the N and P bits.
MTIOC0B pin
MTIOC0C pin
MTIOC3D pin
MTIOC4A pin
MTIOC4C pin
MTIOC4B pin
MTIOC4D pin
MTIOC0B pin
MTIOC0C pin
MTIOC3D pin
MTIOC4A pin
MTIOC4C pin
MTIOC4B pin
MTIOC4D pin
TGCR UF bit
VF bit
WF bit
MTIOC3D pin
MTIOC4A pin
MTIOC4C pin
MTIOC4B pin
MTIOC4D pin
Figure 21.65 Example of Output Phase Switching through UF, VF, and WF Bit Settings (1)
TGCR UF bit
VF bit
WF bit
MTIOC3D pin
MTIOC4A pin
MTIOC4C pin
MTIOC4B pin
MTIOC4D pin
Figure 21.66 Example of Output Phase Switching through UF, VF, and WF Bit Settings (2)
Interrupt skipping [1] Set bits T3AEN and T4VEN in the timer interrupt skipping set
register (TITCR) to 0 to clear the skipping counter.
[2] Specify the interrupt skipping count within the range from 0 to 7
Clear interrupt skipping counter [1] times in bits T3ACOR2 to T3ACOR0 and T4VCOR2 to T4VCOR0
in TITCR, and enable interrupt skipping through bits T3AEN and
T4VEN.
Set skipping count and
[2]
enable interrupt skipping Note: • The setting of TITCR must be done while the TGIA3 and
TCIV4 interrupt requests are disabled by the settings of
registers MTU3.TIER and MTU4.TIER under the condition
in which compare match never occur.
Interrupt skipping
MTU3.TCNT
MTU4.
TCNT
Period during which Period during which Period during which Period during which
skipping count can skipping count can skipping count can skipping count can
be changed be changed be changed be changed
Figure 21.68 Periods during which Interrupt Skipping Count can be Changed
Skipping counter 00 01 02 03 00 01 02 03
Note: • This function must always be used in combination with interrupt skipping.
When interrupt skipping is disabled (the T3AEN and T4VEN bits in the timer interrupt skipping set register
(TITCR) are cleared to 0 or the skipping count setting bits (T3ACOR and T4VCOR) in TITCR are cleared to 0),
make sure that buffer transfer is not linked with interrupt skipping (clear the BTE1 bit in the timer buffer transfer
set register (TBTER) to 0).
If buffer transfer is linked with interrupt skipping while interrupt skipping is disabled, buffer transfer is never
performed.
MTU3.
TCNT
MTU4.
TCNT
Data 1
(1) No data is transferred from the buffer register to the temporary register in the buffer transfer -disabled period
(setting TBTER.BTE[1:0] to 01b).
(2) Data is transferred from the temporary register to the compare register even in the compare transfer-disabled
period.
(3) After buffer transfer is enabled, data is transferred from the buffer register to the temporary register .
Figure 21.70 Example of Operation when Buffer Transfer is Disabled (BTE[1:0] = 01b)
(1) When the buffer register is modified within one carrier cycle of the generation of a TGIA3 interrupt
TGIA3 interrupt generated TGIA3 interrupt generated
MTU3.
TCNT
MTU4.
TCNT
TITCR.T3ACOR[2:0] bits 2
TITCNT.T3ACNT[2:0] bits 0 1 2 0 1
(2) When the buffer register is modified after one carrier cycle has elapsed from generation of a TGIA3 interrupt
TGIA3 interrupt generated TGIA3 interrupt generated
MTU3.
TCNT
MTU4.
TCNT
TITCR.T3ACOR[2:0] bits 2
TITCNT.T3ACNT[2:0] bits 0 1 2 0 1
Figure 21.71 Example of Operation when Buffer Transfer is Linked with Interrupt Skipping
(BTE[1:0] = 10b)
Figure 21.72 Relationship between Bits T3AEN and T4VEN in TITCR and Buffer Transfer-Enabled Period
22 registers in total
MTU3.TCR and MTU4.TCR, MTU3.TMDR and MTU4.TMDR, MTU3.TIORH and MTU4.TIORH, MTU3.TIORL
and MTU4.TIORL, MTU3.TIER and MTU4.TIER, MTU3.TCNT and MTU4.TCNT, MTU3.TGRA and MTU4.TGRA,
MTU3.TGRB and MTU4.TGRB, TOER, TOCR1, TOCR2, TGCR, TCDR, and TDDR
This function can disable CPU access to the mode registers, control registers, and counters to prevent miswriting due to
CPU runaway. In the access-disabled state, the applicable registers are read as undefined and writing to these registers is
ignored.
(1) Example of Procedure for Specifying A/D Converter Start Request Delaying Function
Figure 21.73 shows an example of procedure for specifying the A/D converter start request delaying function.
[1] Set the cycle in the timer A/D converter start request cycle set buffer
A/D converter start request
delaying function register (MTU4.TADCOBRA/B) and timer A/D converter start
request cycle set register (MTU4.TADCORA/B). (The same initial
value must be specified in the cycle set buffer register and cycle set
Set A/D converter start request cycle register.)
[1]
[2] Use bits BF[1:0] in the timer A/D converter start request control
register (TADCR) to specify the timing of buffer transfer from the
•Set the timing of transfer from cycle [2] timer A/D converter start request cycle set buffer register to A/D
set buffer register converter start request cycle set register.
•Set linkage with interrupt skipping
•Enable A/D converter start request • Specify whether to link with interrupt skipping through bits ITA3AE,
delaying function ITA4VE, ITB3AE, and ITB4VE.
• Use bits UT4AE, DT4AE, UT4BE, and DT4BE to enable A/D
converter start requests (TRG4AN or TRG4BN).
Note: • Perform TADCR setting while MTU4.TCNT is stopped.
A/D converter start request Note: • Do not set BF1 to 1 when complementary PWM mode is not
delaying function selected.
Note: • Do not set ITA3AE, ITA4VE, ITB3AE, ITB4VE, DT4AE, or
DT4BE to 1 when complementary PWM mode is not selected.
Figure 21.73 Example of Procedure for Specifying A/D Converter Start Request Delaying Function
(2) Basic Example of A/D Converter Start Request Delaying Function Operation
Figure 21.74 shows a basic example of A/D converter start request signal (TRG4AN) operation when the trough of
MTU4.TCNT is specified for the buffer transfer timing and an A/D converter start request signal is output during
MTU4.TCNT down-counting.
Transfer from cycle buffer Transfer from cycle buffer Transfer from cycle buffer
register to cycle register register to cycle register register to cycle register
MTU4.TADCORA
MTU4.TCNT
MTU4.TADCOBRA
Figure 21.74 Basic Example of A/D Converter Start Request Signal (TRG4AN) Operation
(4) A/D Converter Start Request Delaying Function Linked with Interrupt Skipping
A/D converter start requests (TRG4AN and TRG4BN) can be issued in coordination with interrupt skipping by making
settings in the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in the timer A/D converter start request control register
(TADCR). Figure 21.75 shows an example of A/D converter start request signal (TRG4AN) operation when TRG4AN
output is enabled during MTU4.TCNT up-counting and down-counting and A/D converter start requests are linked with
interrupt skipping.
Figure 21.76 shows another example of A/D converter start request signal (TRG4AN) operation when TRG4AN output
is enabled during MTU4.TCNT up-counting and A/D converter start requests are linked with interrupt skipping.
MTU4.TCNT
MTU4.TADCORA
TGIA3 interrupt
skipping counter 00 01 02 00 01
TCIV4 interrupt 00 01 02 00 01
skipping counter
Figure 21.75 Example of A/D Converter Start Request Signal (TRG4AN) Operation Linked with Interrupt
Skipping (when the output of TRG4AN in counting up and down by TCNT is enabled)
MTU4.TCNT
MTU4.TADCORA
TGIA3 interrupt
skipping counter 00 01 02 00 01
TCIV4 interrupt
skipping 00 01 02 00 01
counter
Figure 21.76 Example of A/D Converter Start Request Signal (TRG4AN) Operation Linked with Interrupt
Skipping (when the output of TRG4AN in counting up by TCNT is enabled)
[2] In TIOR, select the high level or low level for the pulse
Select counter clock [1] width measuring condition.
PCLK
MTIC5U
MTU5.
0000 0001 0002 0003 0004 0005 0006 0007 0007 0008 0009 000A 000B
TCNTU
Figure 21.78 Example of External Pulse Width Measurement (Measuring High Pulse Width)
Tdead
[1] Place MTU3 and MTU4 in complementary PWM mode. For details, refer to the
Complementary PWM mode [1] Complementary PWM Mode section.
[2] Specify the external pulse width measurement function for the target TIOR in
External pulse width MTU5. For details, refer to the External Pulse Width Measurement section.
measurement [2]
[3] Set bits CST3 and CST4 in MTU.TSTR and bits CSTU5, CSTV5, and CSTW5 in
MTU5.TSTR to 1 to start count operation.
Start count operation in
[3]
MTU3, MTU4 and MTU5 [4] When the capture condition specified in TIOR is satisfied, the MTU5.TCNT
value is captured in MTU5.TGR.
MTU5.TCNT [5] For U-phase dead time compensation, when an interrupt is generated at the
input capture occurs [4]*1
crest (TGIA3) or trough (TCIV4) in complementary PWM mode, read the
MTU5.TGRU value, calculate the difference in time between MTU5.TGRU and
MTU3.TGRB, and write the corrected value to MTU3.TGRD in the interrupt
Interrupt processing [5] processing.
For the V phase and W phase, read the MTU5.TGRV and MTU5.TGRW values
and write the corrected values to MTU4.TGRC and MTU4.TGRD, respectively,
in the same way as for U-phase compensation.
The MTU5.TCNT value should be cleared through the TCNTCMPCLR setting or
by software.
– +
MTU Complementary DC
PWM output
MTU3
MTU4
Level conversion
W
Dead time
delay input Inverter output V
Motor
MTU5 monitor signals U W
V
U
W#
V#
U#
(2) TCNT Capture at Crest and/or Trough in Complementary PWM Mode Operation
The MTU5.TCNT value is captured in MTU5.TGR at either the crest or trough or at both the crest and trough during
complementary PWM mode operation. The timing for capturing in MTU5.TGR can be selected by TIOR.
Figure 21.82 shows operation for the capture of MTU5.TCNT on crests and in troughs in complementary PWM mode.
Tdead
Figure 21.82 MTU5.TCNT Capture at Crest and/or Trough in Complementary PWM Mode Operation
Sampling clock
Eliminated pulse
Input capture input pin or
external pulse input pin
Matching three times
Signal conveyed
internally
Note: • This table lists the initial state immediately after a reset. The relative channel priorities can be changed by the interrupt controller.
(1) A/D Converter Activation by TGRA Input Capture/Compare Match or at MTU4.TCNT Trough in
Complementary PWM Mode
The A/D converter can be activated by the occurrence of a TGRA input capture/compare match in each channel. In
addition, if complementary PWM mode operation is performed while the TTGE2 bit in MTU4.TIER is set to 1, the A/D
converter can be activated at the trough of MTU4.TCNT count (MTU4.TCNT = 0000h).
A/D converter start request signal TRGAN is issued to the A/D converter under either of the following conditions.
When a TGRA input capture/compare match occurs on a channel while the TTGE bit in TIER is set to 1
When the MTU4.TCNT count reaches the trough (MTU4.TCNT = 0000h) during complementary PWM mode
operation while the TTGE2 bit in MTU4.TIER is set to 1
When either condition is satisfied, if A/D converter start signal TRGAN from the MTU is selected as the trigger in the
A/D converter, A/D conversion will start.
(2) A/D Converter Activation by Compare Match between MTU0.TCNT and MTU0.TGRE
A compare match between MTU0.TCNT and MTU0.TGRE activates the A/D converter.
A/D converter start request signal TRG0EN is issued when a compare match occurs between MTU0.TCNT and
MTU0.TGRE. If A/D converter start signal TRG0EN from the MTU is selected as the trigger in the A/D converter, A/D
conversion will start.
(3) A/D Converter Activation by Compare Match between MTU0.TCNT and MTU0.TGRF
A compare match between MTU0.TCNT and MTU0.TGRF activates the A/D converter.
A/D converter start request signal TRG0FN is issued when a compare match occurs between MTU0.TCNT and
MTU0.TGRF. If A/D converter start signal TRG0FN from the MTU is selected as the trigger in the A/D converter, A/D
conversion will start.
(4) A/D Converter Activation by Input Capture or Compare Match with MTU0.TGRA or
MTU0.TGRB
The A/D converter can be activated when an input capture or compare match occurs between MTU0.TCNT and
MTU0.TGRA or MTU0.TGRB.
When an input capture or compare match occurs between MTU0.TCNT and MTU0.TGRA or MTU0.TGRB. A/D
converter start request signal TRG0AN or TRG0BN is issued. If A/D converter start signal TRG0AN or TRG0BN from
the MTU is selected as the trigger in the A/D converter, A/D conversion will start.
(5) A/D Converter Activation by A/D Converter Start Request Delaying Function
The A/D converter can be activated by generating A/D converter start request signal TRG4AN or TRG4BN when the
MTU4.TCNT count matches the TADCORA or TADCORB value if the UT4AE, DT4AE, UT4BE, or DT4BE bit in the
A/D converter start request control register (TADCR) is set to 1. For details, refer to section 21.3.9, A/D Converter
Start Request Delaying Function.
A/D conversion will start if A/D converter start signal TRG4ABN from the MTU is selected as the trigger in the A/D
converter when TRG4AN or TRG4BN is generated.
Table 21.58 Interrupt Sources and A/D Converter Start Request Signals
Target Registers A/D Start Request Source A/D Converter Start Request Signal
MTU0.TGRA and MTU0.TCNT Input capture/compare match TRGAN
MTU1.TGRA and MTU1.TCNT
MTU2.TGRA and MTU2.TCNT
MTU3.TGRA and MTU3.TCNT
MTU4.TGRA and MTU4.TCNT
MTU4.TCNT MTU4.TCNT trough in complementary PWM mode
MTU0.TGRA and MTU0.TCNT Input capture/compare match TRG0AN
MTU0.TGRB and MTU0.TCNT TRG0BN
MTU0.TGRE and MTU0.TCNT Compare match TRG0EN
MTU0.TGRF and MTU0.TCNT TRG0FN
TADCORA and MTU4.TCNT or TRG4ABN
TADCORB and MTU4.TCNT
PCLK
PCLK
TCNT N-1 N
PCLK
PCLK
Figure 21.87 Count Timing in External Clock Operation (Phase Counting Mode)
PCLK
TCNT N N+1
TGR N
MTIOC pin
Figure 21.88 Output Compare Output Timing (Normal Mode or PWM Mode)
PCLK
TCNT N N+1
TGR N
MTIOC pin
Figure 21.89 Output Compare Output Timing (Complementary PWM Mode or Reset-Synchronized PWM Mode)
PCLK
TGR N N+2
PCLK
TCNT N 0000h
TGR N
PCLK
TGR N
PCLK
TCNT N 0000h
TGR N
PCLK
TCNT
n n+1
TGRA, TGRB n N
TGRC, TGRD N
PCLK
TCNT N N+1
TGRC, TGRD n N
PCLK
TCNT n 0000h
PCLK
TCNTS 0000h
Buffer register n N
Temporary register n N
Figure 21.97 Transfer Timing from Buffer Register to Temporary Register (TCNTS Stop)
PCLK
Buffer register n N
Temporary register n N
Figure 21.98 Transfer Timing from Buffer Register to Temporary Register (TCNTS Operating)
PCLK
P-1 P 0000h
TCNTS
Temporary register N
Compare register n N
PCLK
TCNT N N+1
TGR N
Interrupt signal
PCLK
TCNT N-1 N
TGR N
Interrupt signal
PCLK
TCNT N
TGR N
Interrupt signal
PCLK
TCNT N
TGR N
Interrupt signal
PCLK
Overflow signal
Interrupt signal
PCLK
Underflow signal
Interrupt signal
Phase Phase
Overlap difference Overlap difference Pulse width Pulse width
MTCLKA
(MTCLKC)
MTCLKB
(MTCLKD)
Figure 21.106 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
MTU0 to MTU4
CNTCLK
f=
(N + 1)
MTU5
CNTCLK
f=
N
f: Counter frequency
CNTCLK: The counter-clock frequency set by TCR.TPSC[2:0] bits
N: TGR setting
Written by CPU
PCLK
TCNT N 0000h
Figure 21.107 Contention between TCNT Write and Counter Clear Operations
Written by CPU
PCLK
TCNT N M
Written by CPU
PCLK
TCNT N N+1
TGR N M
Figure 21.109 Contention between TGR Write Operation and Compare Match
21.6.7 Contention between Buffer Register Write Operation and Compare Match
If a compare match occurs in a TGR write cycle, the data before write operation is transferred to TGR by the buffer
operation.
Figure 21.110 shows the timing in this case.
Written by CPU
PCLK
Buffer register N M
TGR N
Figure 21.110 Contention between Buffer Register Write Operation and Compare Match
21.6.8 Contention between Buffer Register Write and TCNT Clear Operations
When the buffer transfer timing is set at the TCNT clear timing by the timer buffer operation transfer mode register
(TBTM), if TCNT clearing occurs in a TGR write cycle, the data before write operation is transferred to TGR by the
buffer operation.
Figure 21.111 shows the timing in this case.
Written by CPU
PCLK
Buffer register N M
TGR N
Figure 21.111 Contention between Buffer Register Write and TCNT Clear Operations
Read by CPU
PCLK
TGR N M
Figure 21.112 Contention between TGR Read Operation and Input Capture (MTU0 to MTU5)
Written by CPU
PCLK
TCNT M
TGR M
Figure 21.113 Contention between TGR Write Operation and Input Capture (MTU0 to MTU4)
Written by CPU
PCLK
TCNT M
TGR write data
TGR N
Figure 21.114 Contention between TGR Write Operation and Input Capture (MTU5)
21.6.11 Contention between Buffer Register Write Operation and Input Capture
If an input capture signal is generated in a buffer register write cycle, the buffer operation takes precedence and the buffer
register write operation is not performed.
Figure 21.115 shows the timing in this case.
Written by CPU
PCLK
TCNT N
TGR M N
Buffer register M
Figure 21.115 Contention between Buffer Register Write Operation and Input Capture
PCLK
Disabled
MTU1.TCNT input clock
MTU1.TCNT M
MTU1.TGRA M
MTU1.TGRB N M
MTU0.TCNT P
MTU0.TGRA to D Q P
Figure 21.116 Contention between MTU2.TCNT Write Operation and Overflow/Underflow in Cascaded Operation
MTU3.TGRA
TCDR
MTU3.TCNT
MTU4.TCNT
TDDR
0000h
Figure 21.117 Counter Value when Stopped in Complementary PWM Mode (MTU3 and MTU4 Operation)
21.6.15 Buffer Operation and Compare Match Flags in Reset-Synchronized PWM Mode
When setting buffer operation in reset-synchronized PWM mode, set the BFA and BFB bits in MTU4.TMDR to 0.
Setting the BFA bit in MTU4.TMDR to 1 disables MTIOC4C pin waveform output. Setting the BFB bit in
MTU4.TMDR to 1 also disables MTIOC4D pin waveform output.
In reset-synchronized PWM mode, buffer operation in MTU3 and MTU4 depends on the settings in the BFA and BFB
bits of MTU3.TMDR. For example, if the BFA bit in MTU3.TMDR is set to 1, MTU3.TGRC functions as a buffer
register for MTU3.TGRA. At the same time, MTU4.TGRC functions as a buffer register for MTU4.TGRA.
While the MTU3.TGRC and MTU3.TGRD are operating as buffer registers, the corresponding TGIC and TGID
interrupt requests are never generated.
Figure 21.118 shows an example of MTU3.TGR, MTU4.TGR, MTIOC3m, and MTIOC4m operation with the BFA and
BFB bits in MTU3.TMDR set to 1 and the BFA and BFB bits in MTU4.TMDR set to 0. (m= A to D)
MTU3.TGRA Data are transferred from the buffer in response to compare matches
MTU3.TCNT with MTU3.TGRA.
Point a MTU3.TGRA
MTU3.TGRC
MTU3.TGRC
MTU3.TGRB, MTU4.TGRA
MTU4.TGRB
Point b MTU3.TGRB, MTU3.TGRD
MTU3.TGRD, MTU4.TGRC
MTU4.TGRA, MTU4.TGRC
MTU4.TGRD MTU4.TGRB, MTU4.TGRD
0000h
MTIOC3A
MTIOC3B
MTIOC3D
MTIOC4A
MTIOC4C
MTIOC4B
MTIOC4D
Figure 21.118 Buffer Operation and Compare Match Flags in Reset-Synchronized PWM Mode
0000h
PCLK
Not generated
TCIV interrupt signal
PCLK
TCNT FFFFh M
Not generated
Interrupt signal
21.6.23 Notes when Complementary PWM Mode Output Protection Functions are not
Used
The complementary PWM mode output protection functions are initially enabled. If the functions are not used, the
POE.POECR2 register should be set to 00h.
Condition 1: In portion (10) of the initial output inhibition period in Figure 21.122, synchronous clearing occurs within
the dead-time period for PWM output.
Condition 2: In portions (10) and (11) of the initial output inhibition period in Figure 21.123, synchronous clearing
occurs when any condition from among MTU3.TGRB ≤ TDDR, MTU4.TGRA ≤ TDDR, or MTU4.TGRB
≤ TDDR is satisfied.
Synchronous clearing
10 11 10 11
MTU3.
MTU3.TGRA
TCNT
Tb interval Tb interval
MTU4.
TCNT
TGR
TDDR
Positive phase
output
Synchronous clearing
10 11 10 11
MTU3.TGRA
MTU3.
TCNT Tb interval Tb interval
MTU4.
TCNT
TDDR
TGR
Positive phase
output
Negative phase
output
Although there is no period for output of the active level over this Dead time is
interval, synchronous clearing leads to output of the active level. eliminated.
PCLK
TSTR.CST
TCNT 0000h
TGR 0000h
Interrupt signal
21.7.3 Overview of Pin Initialization Procedures and Mode Transitions in Case of Error
during Operation
When making a transition to a mode (Normal, PWM1, PWM2, or PCM) in which the pin output level is selected by
the timer I/O control register (TIOR) setting, initialize the pins by means of TIOR setting.
In PWM mode 1, since a waveform is not output to the MTIOCnB (MTIOCnD) pins, setting TIOR will not
initialize the pins. If initialization is required, carry it out in normal mode, then switch to PWM mode 1.
In PWM mode 2, since a waveform is not output to the cycle register pins, setting TIOR will not initialize the pins.
If initialization is required, carry it out in normal mode, then switch to PWM mode 2.
In normal mode or PWM mode 2, if TGRC and TGRD operate as buffer registers, setting TIOR will not initialize
the buffer register pins. If initialization is required, clear buffer mode, carry out initialization, then set buffer mode
again.
In PWM mode 1, if either TGRC or TGRD operates as a buffer register, setting TIOR will not initialize the TGRC
pin. To initialize the TGRC pin, clear buffer mode, carry out initialization, then set buffer mode again.
When making a transition to a mode (CPWM or RPWM) in which the pin output level is selected by the timer
output control register (TOCR) setting, switch to normal mode, perform initialization with TIOR, restore TIOR to
its initial value, and temporarily disable output in MTU3 and MTU4 with the timer output master enable register
(TOER). After that, operate the MTU in accordance with the mode setting procedure (TOCR setting, TMDR
setting, and TOER setting).
Note: • Channel number is substituted for “n” indicated in this section unless otherwise specified.
Pin initialization procedures are described below for the numbered combinations in Table 21.59. The active level is
assumed to be low.
(1) Operation When Error Occurs in Normal Mode and Operation is Restarted in Normal Mode
Figure 21.125 shows a case in which an error occurs in normal mode and operation is restarted in normal mode after re-
setting.
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14]
Reset TMDR TOER TIOR MPC TSTR Match Error Port TSTR TMDR TIOR MPC TSTR
(normal) (1) (1 init (MTU) (1) occurs output (0) (normal) (1 init (MTU) (1)
0 out) 0 out)
MTU module output
MTIOCnA
MTIOCnB
PORT output
Pxx Hi-Z
Pxx Hi-Z
[1] After a reset, the MTU output goes low and the ports enter high-impedance state.
[2] After a reset, the TMDR setting is for normal mode.
[3] For MTU3 and MTU4, enable output with TOER before initializing the pins with TIOR.
[4] Initialize the pins with TIOR. (In the example, the initial output is a high level, and a low level is output on compare
match occurrence.)
[5] Use the MPC and the port mode register (PMR) for the I/O port to set up MTU output.
[6] Start count operation by setting TSTR.
[7] Output goes low on compare match occurrence.
[8] An error occurs.
[9] Use the port direction register (PDR) and port mode register (PMR) for the input port pin to switch it to operate as a
general output port pin, and the port output data register (PODR) to select output of the non-active level.
[10] Stop count operation by setting TSTR.
[11] This step is not necessary when restarting in normal mode.
[12] Initialize the pins with TIOR.
[13] Use the MPC and the port mode register (PMR) for the I/O port to set up MTU output.
[14] Restart operation by setting TSTR.
(2) Operation When Error Occurs in Normal Mode and Operation is Restarted in PWM Mode 1
Figure 21.126 shows a case in which an error occurs in normal mode and operation is restarted in PWM mode 1 after
re-setting.
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14]
Reset TMDR TOER TIOR MPC TSTR Match Error Port TSTR TMDR TIOR MPC TSTR
(normal) (1) (1 init (MTU) (1) occurs output (0) (PWM1) (1 init (MTU) (1)
0 out) 0 out)
MTU module output
MTIOCnA
PORT output
Pxx Hi-Z
Pxx Hi-Z
(3) Operation When Error Occurs in Normal Mode and Operation is Restarted in PWM Mode 2
Figure 21.127 shows a case in which an error occurs in normal mode and operation is restarted in PWM mode 2 after
re-setting.
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14]
Reset TMDR TOER TIOR MPC TSTR Match Error Port TSTR TMDR TIOR MPC TSTR
(normal) (1) (1 init (MTU) (1) occurs output (0) (PWM2) (1init (MTU) (1)
0 out) 0 out)
MTU module output
MTIOCnA Not initialized (cycle register)
MTIOCnB
PORT output
Pxx Hi-Z
Pxx Hi-Z
(4) Operation When Error Occurs in Normal Mode and Operation is Restarted in Phase Counting
Mode
Figure 21.128 shows a case in which an error occurs in normal mode and operation is restarted in phase counting mode
after re-setting.
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14]
Reset TMDR TOER TIOR MPC TSTR Match Error Port TSTR TMDR TIOR MPC TSTR
(normal) (1) (1 init (MTU) (1) occurs output (0) (PCM) (1 init (MTU) (1)
0 out) 0 out)
MTU module output
MTIOCnA
MTIOCnB
PORT output
Pxx Hi-Z
Pxx Hi-Z
Figure 21.128 Error Occurrence in Normal Mode, Recovery in Phase Counting Mode
(5) Operation When Error Occurs in Normal Mode and Operation is Restarted in Complementary
PWM Mode
Figure 21.129 shows a case in which an error occurs in normal mode and operation is restarted in complementary PWM
mode after re-setting.
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18]
Reset TMDR TOER TIOR MPC TSTR Match Error Port TSTR TIOR TIOR TOER TOCR TMDR TOER MPC TSTR
(normal) (1) (1 init (MTU) (1) occurs output (0) (0 init (disabled) (0) (CPWM) (1) (MTU) (1)
0 out) 0 out)
MTU module output
MTIOC3A
MTIOC3B
MTIOC3D
PORT output
Pxx Hi-Z
Pxx Hi-Z
Pxx Hi-Z
Figure 21.129 Error Occurrence in Normal Mode, Recovery in Complementary PWM Mode
(6) Operation When Error Occurs in Normal Mode and Operation is Restarted in Reset-
Synchronized PWM Mode
Figure 21.130 shows a case in which an error occurs in normal mode and operation is restarted in reset-synchronized
PWM mode after re-setting.
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18]
Reset TMDR TOER TIOR MPC TSTR Match Error Port TSTR TIOR TIOR TOER TOCR TMDR TOER MPC TSTR
(normal) (1) (1 init (MTU) (1) occurs output (0) (0 init (disabled) (0) (RPWM) (1) (MTU) (1)
0 out) 0 out)
MTU module output
MTIOC3A
MTIOC3B
MTIOC3D
PORT output
Pxx Hi-Z
Pxx Hi-Z
Pxx Hi-Z
Figure 21.130 Error Occurrence in Normal Mode, Recovery in Reset-Synchronized PWM Mode
(7) Operation When Error Occurs in PWM Mode 1 and Operation is Restarted in Normal Mode
Figure 21.131 shows a case in which an error occurs in PWM mode 1 and operation is restarted in normal mode after
re-setting.
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14]
Reset TMDR TOER TIOR MPC TSTR Match Error Port TSTR TMDR TIOR MPC TSTR
(PWM1) (1) (1 init (MTU) (1) occurs output (0) (normal) (1 init (MTU) (1)
0 out) 0 out)
MTU module output
MTIOCnA
PORT output
Pxx Hi-Z
Pxx Hi-Z
[1] After a reset, the MTU output goes low and the ports enter high-impedance state.
[2] Set PWM mode 1.
[3] For MTU3 and MTU4, enable output with TOER before initializing the pins with TIOR.
[4] Initialize the pins with TIOR. (In the example, the initial output is a high level, and a low level is output on compare
match occurrence. In PWM mode 1, the MTIOCnB side is not initialized.)
[5] Use the MPC and the port mode register (PMR) for the I/O port to set up MTU output.
[6] Start count operation by setting TSTR.
[7] Output goes low on compare match occurrence.
[8] An error occurs.
[9] Use the port direction register (PDR) and port mode register (PMR) for the input port pin to switch it to operate as a
general output port pin, and the port output data register (PODR) to select output of the non-active level.
[10] Stop count operation by setting TSTR.
[11] Set normal mode.
[12] Initialize the pins with TIOR.
[13] Use the MPC and the port mode register (PMR) for the I/O port to set up MTU output.
[14] Restart operation by setting TSTR.
(8) Operation When Error Occurs in PWM Mode 1 and Operation is Restarted in PWM mode 1
Figure 21.132 shows a case in which an error occurs in PWM mode 1 and operation is restarted in PWM mode 1 after
re-setting.
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14]
Reset TMDR TOER TIOR MPC TSTR Match Error Port TSTR TMDR TIOR MPC TSTR
(PWM1) (1) (1 init (MTU) (1) occurs output (0) (PWM1) (1 init (MTU) (1)
0 out) 0 out)
MTU module output
MTIOCnA
MTIOCnB Not initialized (MTIOCnB) Not initialized (MTIOCnB)
PORT output
Pxx Hi-Z
Pxx Hi-Z
(9) Operation When Error Occurs in PWM Mode 1 and Operation is Restarted in PWM mode 2
Figure 21.133 shows a case in which an error occurs in PWM mode 1 and operation is restarted in PWM mode 2 after
re-setting.
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14]
Reset TMDR TOER TIOR MPC TSTR Match Error Port TSTR TMDR TIOR MPC TSTR
(PWM1) (1) (1 init (MTU) (1) occurs output (0) (PWM2) (1 init (MTU) (1)
0 out) 0 out)
MTU module output
MTIOCnA Not initialized (cycle register)
PORT output
Pxx Hi-Z
Pxx Hi-Z
(10) Operation When Error Occurs in PWM Mode 1 and Operation is Restarted in Phase Counting
Mode
Figure 21.134 shows a case in which an error occurs in PWM mode 1 and operation is restarted in phase counting mode
after re-setting.
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14]
Reset TMDR TOER TIOR MPC TSTR Match Error Port TSTR TMDR TIOR MPC TSTR
(PWM1) (1) (1 init (MTU) (1) occurs output (0) (PCM) (1 init (MTU) (1)
0 out) 0 out)
MTU module output
MTIOCnA
PORT output
Pxx Hi-Z
Pxx Hi-Z
Figure 21.134 Error Occurrence in PWM Mode 1, Recovery in Phase Counting Mode
(11) Operation When Error Occurs in PWM Mode 1 and Operation is Restarted in Complementary
PWM Mode
Figure 21.135 shows a case in which an error occurs in PWM mode 1 and operation is restarted in complementary
PWM mode after re-setting.
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
Reset TMDR TOER TIOR MPC TSTR Match Error Port TSTR TMDR TIOR TIOR TOER TOCR TMDR TOER MPC TSTR
(PWM1) (1) (1 init (MTU) (1) occurs output (0) (normal) (0 init (disabled) (0) (CPWM) (1) (MTU) (1)
0 out) 0 out)
MTU module output
MTIOC3A
MTIOC3B Not initialized (MTIOCnB)
Pxx Hi-Z
Pxx Hi-Z
Figure 21.135 Error Occurrence in PWM Mode 1, Recovery in Complementary PWM Mode
(12) Operation When Error Occurs in PWM Mode 1 and Operation is Restarted in Reset-
Synchronized PWM Mode
Figure 21.136 shows a case in which an error occurs in PWM mode 1 and operation is restarted in reset-synchronized
PWM mode after re-setting.
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
Reset TMDR TOER TIOR MPC TSTR Match Error Port TSTR TMDR TIOR TIOR TOER TOCR TMDR TOER MPC TSTR
(PWM1) (1) (1 init (MTU) (1) occurs output (0) (normal) (0 init (disabled) (0) (RPWM) (1) (MTU) (1)
0 out) 0 out)
MTU module output
MTIOC3A
MTIOC3B Not initialized (MTIOC3B)
Pxx Hi-Z
Pxx Hi-Z
Figure 21.136 Error Occurrence in PWM Mode 1, Recovery in Reset-Synchronized PWM Mode
(13) Operation When Error Occurs in PWM Mode 2 and Operation is Restarted in Normal Mode
Figure 21.137 shows a case in which an error occurs in PWM mode 2 and operation is restarted in normal mode after
re-setting.
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
Reset TMDR TIOR MPC TSTR Match Error Port TSTR TMDR TIOR MPC TSTR
(PWM2) (1 init (MTU) (1) occurs output (0) (normal) (1 init (MTU) (1)
0 out) 0 out)
MTU module output
MTIOCnA Not initialized (cycle register)
MTIOCnB
PORT output
Pxx Hi-Z
Pxx Hi-Z
[1] After a reset, the MTU output goes low and the ports enter high-impedance state.
[2] Set PWM mode 2.
[3] Initialize the pins with TIOR. (In the example, the initial output is a high level, and a low level is output on compare
match occurrence. In PWM mode 2, the cycle register pins are not initialized. In the example, MTIOCnA is the
cycle register.)
[4] Use the MPC and the port mode register (PMR) for the I/O port to set up MTU output.
[5] Start count operation by setting TSTR.
[6] Output goes low on compare match occurrence.
[7] An error occurs.
[8] Use the port direction register (PDR) and port mode register (PMR) for the input port pin to switch it to operate as a
general output port pin, and the port output data register (PODR) to select output of the non-active level.
[9] Stop count operation by setting TSTR.
[10] Set normal mode.
[11] Initialize the pins with TIOR.
[12] Use the MPC and the port mode register (PMR) for the I/O port to set up MTU output.
[13] Restart operation by setting TSTR.
(14) Operation When Error Occurs in PWM Mode 2 and Operation is Restarted in PWM Mode 1
Figure 21.138 shows a case in which an error occurs in PWM mode 2 and operation is restarted in PWM mode 1 after
re-setting.
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
Reset TMDR TIOR MPC TSTR Match Error Port TSTR TMDR TIOR MPC TSTR
(PWM2) (1 init (MTU) (1) occurs output (0) (PWM1) (1 init (MTU) (1)
0 out) 0 out)
MTU module output
MTIOCnA Not initialized (cycle register)
PORT output
Pxx Hi-Z
Pxx Hi-Z
(15) Operation When Error Occurs in PWM Mode 2 and Operation is Restarted in PWM Mode 2
Figure 21.139 shows a case in which an error occurs in PWM mode 2 and operation is restarted in PWM mode 2 after
re-setting.
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
Reset TMDR TIOR MPC TSTR Match Error Port TSTR TMDR TIOR MPC TSTR
(PWM2) (1 init (MTU) (1) occurs output (0) (PWM2) (1 init (MTU) (1)
0 out) 0 out)
MTU module output
MTIOCnA Not initialized (cycle register) Not initialized (cycle register)
MTIOCnB
PORT output
Pxx Hi-Z
Pxx Hi-Z
(16) Operation When Error Occurs in PWM Mode 2 and Operation is Restarted in Phase Counting
Mode
Figure 21.140 shows a case in which an error occurs in PWM mode 2 and operation is restarted in phase counting mode
after re-setting.
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
Reset TMDR TIOR MPC TSTR Match Error Port TSTR TMDR TIOR MPC TSTR
(PWM2) (1 init (MTU) (1) occurs output (0) (PCM) (1 init (MTU) (1)
0 out) 0 out)
MTU module output
MTIOCnA Not initialized (cycle register)
MTIOCnB
PORT output
Pxx Hi-Z
Pxx Hi-Z
Figure 21.140 Error Occurrence in PWM Mode 2, Recovery in Phase Counting Mode
(17) Operation When Error Occurs in Phase Counting Mode and Operation is Restarted in Normal
Mode
Figure 21.141 shows a case in which an error occurs in phase counting mode and operation is restarted in normal mode
after re-setting.
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
Reset TMDR TIOR MPC TSTR Match Error Port TSTR TMDR TIOR MPC TSTR
(PCM) (1 init (MTU) (1) occurs output (0) (normal) (1 init (MTU) (1)
0 out) 0 out)
MTU module output
MTIOCnA
MTIOCnB
PORT output
Pxx Hi-Z
Pxx Hi-Z
Figure 21.141 Error Occurrence in Phase Counting Mode, Recovery in Normal Mode
[1] After a reset, the MTU output goes low and the ports enter high-impedance state.
[2] Set phase counting mode.
[3] Initialize the pins with TIOR. (In the example, the initial output is a high level, and a low level is output on compare
match occurrence.)
[4] Use the MPC and the port mode register (PMR) for the I/O port to set up MTU output.
[5] Start count operation by setting TSTR.
[6] Output goes low on compare match occurrence.
[7] An error occurs.
[8] Use the port direction register (PDR) and port mode register (PMR) for the input port pin to switch it to operate as a
general output port pin, and the port output data register (PODR) to select output of the non-active level.
[9] Stop count operation by setting TSTR.
[10] Set normal mode.
[11] Initialize the pins with TIOR.
[12] Use the MPC and the port mode register (PMR) for the I/O port to set up MTU output.
[13] Restart operation by setting TSTR.
(18) Operation When Error Occurs in Phase Counting Mode and Operation is Restarted in PWM
Mode 1
Figure 21.142 shows a case in which an error occurs in phase counting mode and operation is restarted in PWM mode 1
after re-setting.
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
Reset TMDR TIOR MPC TSTR Match Error Port TSTR TMDR TIOR MPC TSTR
(PCM) (1 init (MTU) (1) occurs output (0) (PWM1) (1 init (MTU) (1)
0 out) 0 out)
MTU module output
MTIOCnA
PORT output
Pxx Hi-Z
Pxx Hi-Z
Figure 21.142 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 1
(19) Operation When Error Occurs in Phase Counting Mode and Operation is Restarted in PWM
Mode 2
Figure 21.143 shows a case in which an error occurs in phase counting mode and operation is restarted in PWM mode 2
after re-setting.
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
Reset TMDR TIOR MPC TSTR Match Error Port TSTR TMDR TIOR MPC TSTR
(PCM) (1 init (MTU) (1) occurs output (0) (PWM2) (1 init (MTU) (1)
0 out) 0 out)
MTU module output
MTIOCnA Not initialized (cycle register)
MTIOCnB
PORT output
Pxx Hi-Z
Pxx Hi-Z
Figure 21.143 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 2
(20) Operation When Error Occurs in Phase Counting Mode and Operation is Restarted in Phase
Counting Mode
Figure 21.144 shows a case in which an error occurs in phase counting mode and operation is restarted in phase
counting mode after re-setting.
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
Reset TMDR TIOR MPC TSTR Match Error Port TSTR TMDR TIOR MPC TSTR
(PCM) (1 init (MTU) (1) occurs output (0) (PCM) (1 init (MTU) (1)
0 out) 0 out)
MTU module output
MTIOCnA
MTIOCnB
PORT output
Pxx Hi-Z
Pxx Hi-Z
Figure 21.144 Error Occurrence in Phase Counting Mode, Recovery in Phase Counting Mode
(21) Operation When Error Occurs in Complementary PWM Mode and Operation is Restarted in
Normal Mode
Figure 21.145 shows a case in which an error occurs in complementary PWM mode and operation is restarted in normal
mode after re-setting.
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14]
Reset TOCR TMDR TOER MPC TSTR Match Error Port TSTR TMDR TIOR MPC TSTR
(CPWM) (1) (MTU) (1) occurs output (0) (normal) (1 init (MTU) (1)
0 out)
MTU module output
MTIOC3A
MTIOC3B
MTIOC3D
PORT output
Pxx Hi-Z
Pxx Hi-Z
Pxx Hi-Z
Figure 21.145 Error Occurrence in Complementary PWM Mode, Recovery in Normal Mode
[1] After a reset, the MTU output goes low and the ports enter high-impedance state.
[2] Select the complementary PWM output level and enable or disable cyclic output with TOCR.
[3] Set complementary PWM mode.
[4] Enable output in MTU3 and MTU4 with TOER.
[5] Use the MPC and the port mode register (PMR) for the I/O port to set up MTU output.
[6] Start count operation by setting TSTR.
[7] The complementary PWM waveform is output on compare match occurrence.
[8] An error occurs.
[9] Use the port direction register (PDR) and port mode register (PMR) for the input port pin to switch it to operate as a
general output port pin, and the port output data register (PODR) to select output of the non-active level.
[10] Stop count operation by setting TSTR. (MTU output becomes the initial complementary PWM output value).
[11] Set normal mode (MTU output goes low).
[12] Initialize the pins with TIOR.
[13] Use the MPC and the port mode register (PMR) for the I/O port to set up MTU output.
[14] Restart operation by setting TSTR.
(22) Operation When Error Occurs in Complementary PWM Mode and Operation is Restarted in
PWM Mode 1
Figure 21.146 shows a case in which an error occurs in complementary PWM mode and operation is restarted in PWM
mode 1 after re-setting.
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14]
Reset TOCR TMDR TOER MPC TSTR Match Error Port TSTR TMDR TIOR MPC TSTR
(CPWM) (1) (MTU) (1) occurs output (0) (PWM1) (1 init (MTU) (1)
0 out)
MTU module output
MTIOC3A
Pxx Hi-Z
Pxx Hi-Z
Figure 21.146 Error Occurrence in Complementary PWM Mode, Recovery in PWM Mode 1
(23) Operation When Error Occurs in Complementary PWM Mode and Operation is Restarted in
Complementary PWM Mode
Figure 21.147 shows a case in which an error occurs in complementary PWM mode and operation is restarted in
complementary PWM mode after re-setting (when operation is restarted using the cycle and duty settings at the time of
stopping the counter).
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
Reset TOCR TMDR TOER MPC TSTR Match Error Port TSTR MPC TSTR Match
(CPWM) (1) (MTU) (1) occurs output (0) (MTU) (1)
MTIOC3B
MTIOC3D
PORT output
Pxx Hi-Z
Pxx Hi-Z
Pxx Hi-Z
Figure 21.147 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode
(24) Operation When Error Occurs in Complementary PWM Mode and Operation is Restarted in
Complementary PWM Mode with New Settings
Figure 21.148 shows a case in which an error occurs in complementary PWM mode and operation is restarted in
complementary PWM mode after re-setting (operation is restarted using new cycle and duty settings).
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17]
Reset TOCR TMDR TOER MPC TSTR Match Error Error TSTR TMDR TOER TOCR TMDR TOER MPC TSTR
(CPWM) (1) (MTU) (1) occurs occurs (0) (normal) (0) (CPWM) (1) (MTU) (1)
MTIOC3B
MTIOC3D
PORT output
Pxx Hi-Z
Pxx Hi-Z
Pxx Hi-Z
Figure 21.148 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode
(25) Operation When Error Occurs in Complementary PWM Mode and Operation is Restarted in
Reset-Synchronized PWM Mode
Figure 21.149 shows a case in which an error occurs in complementary PWM mode and operation is restarted in reset-
synchronized PWM mode after re-setting.
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17]
Reset TOCR TMDR TOER MPC TSTR Match Error Port TSTR TMDR TOER TOCR TMDR TOER MPC TSTR
(CPWM) (1) (MTU) (1) occurs output (0) (normal) (0) (RPWM) (1) (MTU) (1)
MTIOC3B
MTIOC3D
PORT output
Pxx Hi-Z
Pxx Hi-Z
Pxx Hi-Z
Figure 21.149 Error Occurrence in Complementary PWM Mode, Recovery in Reset-Synchronized PWM Mode
(26) Operation When Error Occurs in Reset-Synchronized PWM Mode and Operation is Restarted
in Normal Mode
Figure 21.150 shows a case in which an error occurs in reset-synchronized PWM mode and operation is restarted in
normal mode after re-setting.
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14]
Reset TOCR TMDR TOER MPC TSTR Match Error Port TSTR TMDR TIOR MPC TSTR
(RPWM) (1) (MTU) (1) occurs output (0) (normal) (1 init (MTU) (1)
0 out)
MTU module output
MTIOC3A
MTIOC3B
MTIOC3D
PORT output
Pxx Hi-Z
Pxx Hi-Z
Pxx Hi-Z
Figure 21.150 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in Normal Mode
[1] After a reset, the MTU output goes low and the ports enter high-impedance state.
[2] Select the reset-synchronized PWM output level and enable or disable cyclic output with TOCR.
[3] Set reset-synchronized PWM mode.
[4] Enable output in MTU3 and MTU4 with TOER.
[5] Use the MPC and the port mode register (PMR) for the I/O port to set up MTU output.
[6] Start count operation by setting TSTR.
[7] The reset-synchronized PWM waveform is output on compare match occurrence.
[8] An error occurs.
[9] Use the port direction register (PDR) and port mode register (PMR) for the input port pin to switch it to operate as a
general output port pin, and the port output data register (PODR) to select output of the non-active level.
[10] Stop count operation by setting TSTR. (MTU output becomes the initial reset-synchronized PWM output value.)
[11] Set normal mode (positive-phase MTU output goes low, and negative-phase output goes high).
[12] Initialize the pins with TIOR.
[13] Use the MPC and the port mode register (PMR) for the I/O port to set up MTU output.
[14] Restart operation by setting TSTR.
(27) Operation When Error Occurs in Reset-Synchronized PWM Mode and Operation is Restarted
in PWM Mode 1
Figure 21.151 shows a case in which an error occurs in reset-synchronized PWM mode and operation is restarted in
PWM mode 1 after re-setting.
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14]
Reset TOCR TMDR TOER MPC TSTR Match Error Port TSTR TMDR TIOR MPC TSTR
(RPWM) (1) (MTU) (1) occurs output (0) (PWM1) (1 init (MTU) (1)
0 out)
MTU module output
MTIOC3A
Pxx Hi-Z
Pxx Hi-Z
Figure 21.151 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in PWM Mode 1
(28) Operation When Error Occurs in Reset-Synchronized PWM Mode and Operation is Restarted
in Complementary PWM Mode
Figure 21.152 shows a case in which an error occurs in reset-synchronized PWM mode and operation is restarted in
complementary PWM mode after re-setting.
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16]
Reset TOCR TMDR TOER MPC TSTR Match Error Port TSTR TOER TOCR TMDR TOER MPC TSTR
(RPWM) (1) (MTU) (1) occurs output (0) (0) (CPWM) (1) (MTU) (1)
MTIOC3B
MTIOC3D
PORT output
Pxx Hi-Z
Pxx Hi-Z
Pxx Hi-Z
Figure 21.152 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in Complementary PWM Mode
(29) Operation When Error Occurs in Reset-Synchronized PWM Mode and Operation is Restarted
in Reset-Synchronized PWM Mode
Figure 21.153 shows a case in which an error occurs in reset-synchronized PWM mode and operation is restarted in
reset-synchronized PWM mode after re-setting.
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
Reset TOCR TMDR TOER MPC TSTR Match Error Port TSTR MPC TSTR Match
(RPWM) (1) (MTU) (1) occurs output (0) (MTU) (1)
MTIOC3B
MTIOC3D
PORT output
Pxx Hi-Z
Pxx Hi-Z
Pxx Hi-Z
Figure 21.153 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in Reset-Synchronized PWM
Mode
Table 21.61 Timer General Register and Timer I/O Control Register used in the Input Capture Operation by ELC
Channel No. Register Name Bit Name of TIOR Register
Channel 1 TGRA register TIOR.IOA[3:0] bits
Channel 2 TGRA register TIOR.IOA[3:0] bits
Channel 3 TGRA register TIORH.IOA[3:0] bits
Channel 4 TGRA register TIORH.IOA[3:0] bits
22.1 Overview
Table 22.1 lists the specifications of the POE, and Figure 22.1 shows a block diagram of the POE.
The POE has input-level detection circuits, output-level comparison circuits, an input for the oscillation-stopped
detection signal from the clock generation circuit, and a high-impedance request/interrupt request generation circuit as
shown in Figure 22.1.
POECR1
POECR2
ICSR3
OSTST
Oscillation stop detection signal
from the clock generation circuit
OCSR1
MTIOC4A Output level
MTIOC4C comparison circuit High-impedance request signal
for MTU3 and MTU4 pins
MTIOC4B Output level
MTIOC4D comparison circuit
High-impedance request
signal for MTU0 pins
Input level detection circuit
POE3# Falling edge detection
circuit
POE2#
ICSR1
PCLK/8
PCLK/16
PCLK/128
SPOER
ICSR1: Input level control/status register 1 OCSR1: Output level control/status register 1
ICSR2: Input level control/status register 2 SPOER: Software port output enable register
ICSR3: Input level control/status register 3 POECR1: Port output enable control register 1
POECR2: Port output enable control register 2
When low-level sampling has been set by the POE0M[1:0] to POE3M[1:0] bits, writing 0 to the POE0F to POE3F flags
requires high level input on the POE0# to POE3# pins.
For details, see section 22.3.5, Release from the High-Impedance.
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — CH0HI CH34HI
Z Z
Value after reset: 0 0 0 0 0 0 0 0
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
— — — OSTST — — OSTST — — — — — — — — —
F E
Value after reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
22.3 Operation
The target pins for high-impedance control and conditions to place the pins in high-impedance are described below.
PCLK
POE# input
MTIOC3B
High-impedance*1
Note 1. The other MTU complementary PWM output pins and MTU0 pins also enter
the high-impedance in the similar timing.
PCLK
Sampling clock
POE# input
MTIOC3B
High-impedance*1
When low level is Flag set (POE# received)
[1] [2] [3] [16]
sampled at all points
Note 1. The other MTU complementary PWM output pins and MTU0 pins also enter the high-impedance in the similar timing.
PCLK
MTIOC3D
High-impedance
Note 1. In this case, the low level has been set as the active level for the MTIOC3B and MTIOC3D pins.
22.4 Interrupts
The POE issues a request to generate an interrupt when the corresponding condition below is matched during input-level
detection, output-level comparison, or oscillation stop by the clock generation circuit. Table 22.4 shows the interrupt
sources and their request conditions.
On acceptance of an OEI1 or OEI2 interrupt, the first line of the exception handling routine for the given interrupt should
confirm that the flag for the given flag has been set to 1.
23.1 Overview
Table 23.1 lists the specifications of the TMR.
Figure 23.1 shows a block diagram of the 8-bit timer module (unit 0), and Figure 23.2 shows that of the 8-bit timer
module (unit 1).
Note 1. For details, see section 27, Serial Communications Interface (SCIe, SCIf).
TMRI0 TMRI2
High output ○ ○ ○ ○ ○ ○
Toggle output ○ ○ ○ ○ ○ ○
TCNT overflow — — — — — —
Cascaded connection TMR1 overflow TMR0 compare — TMR3 overflow TMR2 compare —
match A match A
Module stop setting*2 MSTPCRA.MSTPA5 bit (unit 0), MSTPCRA.MSTPA4 bit (unit 1)
○: Possible
—: Impossible
Note 1. For details, see section 27, Serial Communications Interface (SCIe, SCIf).
Note 2. For details, see section 11, Low Power Consumption.
Counter clock 1
TMCI0 Counter clock 0
Clock select
TMCI1
TCORA TCORA
Compare match A1
Compare match A0 Comparator A0 Comparator A1
TCSR TCSR
Event signal input
Event signal output
TCR TCR
TCCR TCCR
TCSTR
Channel 0 Channel 1
CMIA0 (TMR0) (TMR1)
CMIA1
CMIB0
CMIB1
OVI0
OVI1
Interrupt signal
Counter clock 3
TMCI2 Counter clock 2
Clock select
TMCI3
TCORA TCORA
Compare match A3
Compare match A2 Comparator A2 Comparator A3
To SCI6
Overflow 3
TMO2 Overflow 2 TCNT TCNT
TCSR TCSR
Event signal input
Event signal output
TCR TCR
TCCR TCCR
TCSTR
Channel 2 Channel 3
CMIA2 (TMR2) (TMR3)
CMIA3
CMIB2
CMIB3
OVI2
OVI3
Interrupt signal
Address(es): TMR0.TCNT 0008 8208h, TMR1.TCNT 0008 8209h, TMR2.TCNT 0008 8218h, TMR3.TCNT 0008 8219h
TMR0.TCNT(TMR2.TCNT) TMR1.TCNT(TMR3.TCNT)
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
Address(es): TMR0.TCORA 0008 8204h, TMR1.TCORA 0008 8205h, TMR2.TCORA 0008 8214h, TMR3.TCORA 0008 8215h
TMR0.TCORA(TMR2.TCORA) TMR1.TCORA(TMR3.TCORA)
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
Address(es): TMR0.TCORB 0008 8206h, TMR1.TCORB 0008 8207h, TMR2.TCORB 0008 8216h, TMR3.TCORB 0008 8217h
TMR0.TCORB(TMR2.TCORB) TMR1.TCORB(TMR3.TCORB)
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
Address(es): TMR0.TCR 0008 8200h, TMR1.TCR 0008 8201h, TMR2.TCR 0008 8210h, TMR3.TCR 0008 8211h
b7 b6 b5 b4 b3 b2 b1 b0
Note 1. To use an external reset, set the PORTn.PDR.Bn bit for the corresponding pin to 0 and the PORTn.PMR.Bn bit to 1. For details,
see section 19, I/O Ports.
Address(es): TMR0.TCCR 0008 820Ah, TMR1.TCCR 0008 820Bh, TMR2.TCCR 0008 821Ah, TMR3.TCCR 0008 821Bh
b7 b6 b5 b4 b3 b2 b1 b0
Note 1. To use an external reset, set the PORTn.PDR.Bn bit for the corresponding pin to 0 and the PORTn.PMR.Bn bit to 1. For details,
see section 19, I/O Ports.
Note 1. To use an external reset, set the PORTn.PDR.Bn bit for the corresponding pin to 0 and the PORTn.PMR.Bn bit to 1. For details,
see section 19, I/O Ports.
Note 2. If the clock input of TMR0 (TMR2) is the overflow signal of the TMR1.TCNT (TMR3.TCNT) counter and that of TMR1 (TMR3) is
the compare match signal of the TMR0.TCNT (TMR2.TCNT) counter, no incrementing clock is generated. Do not use this
setting.
b7 b6 b5 b4 b3 b2 b1 b0
— — — — OSB[1:0] OSA[1:0]
Note 1. When the OSA[1:0] and OSB[1:0] bits are all 0, the output enable signal corresponding to the TMOn pin is negated and a
request for high-impedance output is issued to the I/O port. Timer output is low until the first compare match occurs after a reset
when either of the OSA[1:0] or OSB[1:0] bits are 1.
TMR1.TCSR, TMR3.TCSR
b7 b6 b5 b4 b3 b2 b1 b0
— — — — OSB[1:0] OSA[1:0]
Note 1. When the OSA[1:0] and OSB[1:0] bits are all 0, the output enable signal corresponding to the TMOn pin is negated and a
request for high-impedance output is issued to the I/O port. Timer output is low until the first compare match occurs after a reset
when either of the OSA[1:0] or OSB[1:0] bits are 1.
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — — TCS
The TCS bit is valid only when the count start operation is selected by the ELOPD register of the event controller (ELC).
For details, see section 23.7, Link Operation by ELC, or section 18, Event Link Controller (ELC).
23.3 Operation
TCNT
FFh
Counter clear
TCORA
TCORB
00h
TMOn
TCORB
TCORA
TCNT
00h
TMRIn
TMOn
PCLK
TCNT
input clock
PCLK
External clock
input pin
TCNT
input clock
Figure 23.6 Count Timing for External Clock Input (at Both Edges)
PCLK
TCNT N N+1
TCORA or TCORB N
CMIAn or CMIBn
PCLK
TMOn
PCLK
TCNT N 00h
PCLK
2 PCLK
Clear signal
PCLK
2 PCLK
Clear signal
PCLK
Internal overflow
signal
OVIn
f = PCLK / (N + 1)
PCLK
TCNT N 00h
PCLK
TCNT N M
PCLK
TCNT N N+1
TCORA or TCORB N M
Not high.
Figure 23.15 Conflict between TCORA or TCORB Write and Compare Match
Table 23.8 Switching of Frequency Dividing Clocks and TCNT Operation (1/2)
Timing to Change the
No. TCCR.CKS[2:0] Bits TCNT Clock Operation
1 Switching from low to low*1
Clock before
switching
Clock after
switching
TCNT
input clock
Clock after
switching
*3
TCNT
input clock
Clock after
switching
TCNT
input clock
Table 23.8 Switching of Frequency Dividing Clocks and TCNT Operation (2/2)
Timing to Change the
No. TCCR.CKS[2:0] Bits TCNT Clock Operation
4 Switching from high to high
Clock before
switching
Clock after
switching
TCNT
input clock
Note 1. Includes switching from low to stop, and from stop to low.
Note 2. Includes switching from stop to high.
Note 3. Generated because the change of the signal levels is considered as an edge; TCNT is incremented.
Note 4. Includes switching from high to stop.
PCLK
TCNT 00h
CMIAn or CMIBn
24.1 Overview
Table 24.1 lists the specifications for the CMT.
Figure 24.1 shows a block diagram of the CMT (unit 0). A two-channel CMT constitutes a unit. Unit 0 and unit 1 are the
same in terms of specifications.
CMCOR
CMCOR
CMCNT
CMCNT
CMCR
CMCR
Internal Peripheral
— — — — — — — — — — — — — — STR1 STR0
— — — — — — — — — — — — — — STR3 STR2
Address(es): CMT0.CMCR 0008 8002h, CMT1.CMCR 0008 8008h, CMT2.CMCR 0008 8012h, CMT3.CMCR 0008 8018h
— — — — — — — — — CMIE — — — — CKS[1:0]
x: Undefined
Address(es): CMT0.CMCNT 0008 8004h, CMT1.CMCNT 0008 800Ah, CMT2.CMCNT 0008 8014h, CMT3.CMCNT 0008 801Ah
Address(es): CMT0.CMCOR 0008 8006h, CMT1.CMCOR 0008 800Ch, CMT2.CMCOR 0008 8016h, CMT3.CMCOR 0008 801Ch
24.3 Operation
CMCNT value
Counter cleared by compare match with CMCOR
CMCOR
0000h
Time
PCLK
24.4 Interrupts
PCLK
CMCNT N 0
CMCOR N
Interrupt request
(pulse)
Write to CMCNT
PCLK
CMCNT N 0000h
Figure 24.5 Conflict between Write and Compare Match Processes of CMCNT
Write to CMCNT
PCLK
Count clock
CMCNT N M
Table 25.1 lists the specifications of the RTC, Figure 25.1 shows a block diagram of the RTC, and Table 25.2 shows
the pin configuration of the RTC.
Note 1. Satisfy the frequency of the peripheral module clock (PCLKB) the frequency of the count source clock.
Bus interface
To each
RCR2 RTCOUT
function Time counter Alarm function
Prescaler
Alarm comparison
RMONCNT RYRCNT
Interrupt control
ALM
RCR1 PRD
CUP
R64CNT: 64-Hz counter RSECAR/BCNT0AR: Second alarm register/Binary counter 0 alarm register
RSECCNT/BCNT0: Second counter/Binary counter 0 RMINAR/BCNT1AR: Minute alarm register/Binary counter 1 alarm register
RMINCNT/BCNT1: Minute counter/Binary counter 1 RHRAR/BCNT2AR: Hour alarm register/Binary counter 2 alarm register
RHRCNT/BCNT2: Hour counter/Binary counter 2 RWKAR/BCNT3AR: Day-of-week alarm register/Binary counter 3 alarm register
RWKCNT/BCNT3: Day-of-week counter/Binary counter 3 RDAYAR/BCNT0AER: Date alarm register/Binary counter 0 alarm enable register
RDAYCNT: Date counter RMONAR/BCNT1AER: Month alarm register/Binary counter 1 alarm enable register
RMONCNT: Month counter RYRAR/BCNT2AER: Year alarm register/Binary counter 2 alarm enable register
RYRCNT: Year counter RYRAREN/BCNT3AER: Year alarm enable register/Binary counter 3 alarm enable register
RCR1: RTC control register 1
RCR2: RTC control register 2
RCR3: RTC control register 3
RADJ: Time error adjustment register
b7 b6 b5 b4 b3 b2 b1 b0
x: Undefined
The R64CNT counter is used in both calendar count mode and in binary count mode.
The 64-Hz counter (R64CNT) generates the period for a second by counting up periods of the 128-Hz clock.
The state in the sub-seconds range can be confirmed by reading this counter.
This counter is cleared to 00h by an RTC software reset or executing 30-second adjustment.
To read this counter, follow the procedure in section 25.3.5, Reading 64-Hz Counter and Time.
b7 b6 b5 b4 b3 b2 b1 b0
— SEC10[2:0] SEC1[3:0]
x: Undefined
RSECCNT is used for setting and counting the BCD-coded second value. It counts carries generated once per second in
the 64-Hz counter.
The setting range is decimal 00 to 59. The RTC will not operate normally if any other value is set. Before writing to this
register, be sure to stop the count operation through the setting of the START bit in RCR2.
To read this counter, follow the procedure in section 25.3.5, Reading 64-Hz Counter and Time.
b7 b6 b5 b4 b3 b2 b1 b0
BCNT[7:0]
x: Undefined
b7 b6 b5 b4 b3 b2 b1 b0
— MIN10[2:0] MIN1[3:0]
x: Undefined
RMINCNT is used for setting and counting the BCD-coded minute value. It counts carries generated once per minute in
the second counter.
A value from 00 through 59 (practically in BCD) can be specified; if a value outside of this range is specified, the RTC
does not operate correctly. Before writing to this register, be sure to stop the count operation through the setting of the
START bit in RCR2.
To read this counter, follow the procedure in section 25.3.5, Reading 64-Hz Counter and Time.
b7 b6 b5 b4 b3 b2 b1 b0
BCNT[15:8]
x: Undefined
b7 b6 b5 b4 b3 b2 b1 b0
— PM HR10[1:0] HR1[3:0]
x: Undefined
RHRCNT is used for setting and counting the BCD-coded hour value. It counts carries generated once per hour in the
minute counter.
The specifiable time differs according to the setting in the hours mode bit (RCR2.HR24).
When the RCR2.HR24 bit is 0: From 00 to 11 (practically in BCD)
When the RCR2.HR24 bit is 1: From 00 to 23 (practically in BCD)
If a value outside of this range is specified, the RTC does not operate correctly. Before writing to this register, be sure to
stop the count operation through the setting of the START bit in RCR2.
The PM bit is only enabled when the RCR2.HR24 bit is 0. Otherwise, the setting in the PM bit has no effect.
To read this counter, follow the procedure in section 25.3.5, Reading 64-Hz Counter and Time.
b7 b6 b5 b4 b3 b2 b1 b0
BCNT[23:16]
x: Undefined
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — DAYW[2:0]
x: Undefined
RWKCNT is used for setting and counting in the BCD-coded day-of-week value. It counts carries generated once per
day in the hour counter.
A value from 0 through 6 (practically in BCD) can be specified; if a value outside of this range is specified, the RTC does
not operate correctly. Before writing to this register, be sure to stop the count operation through the setting of the START
bit in RCR2.
To read this counter, follow the procedure in section 25.3.5, Reading 64-Hz Counter and Time.
b7 b6 b5 b4 b3 b2 b1 b0
BCNT[31:24]
x: Undefined
b7 b6 b5 b4 b3 b2 b1 b0
— — DATE10[1:0] DATE1[3:0]
x: Undefined
b7 b6 b5 b4 b3 b2 b1 b0
— — — MON10 MON1[3:0]
x: Undefined
— — — — — — — — YR10[3:0] YR1[3:0]
x: Undefined
b7 b6 b5 b4 b3 b2 b1 b0
x: Undefined
RSECAR is an alarm register corresponding to the BCD-coded second counter RSECCNT. When the ENB bit is set to 1,
the RSECAR value is compared with the RSECCNT value. From among the alarm registers (RSECAR, RMINAR,
RHRAR, RWKAR, RDAYAR, RMONAR, and RYRAREN), only those selected with the ENB bits set to 1 are compared
with the corresponding counters. When the respective values all match, the corresponding IR92.IR flag of the ICU is set
to 1.
RSECAR values from 00 through 59 (practically in BCD) can be specified; if a value outside of this range is specified,
the RTC does not operate correctly.
This register is cleared to 00h by an RTC software reset.
b7 b6 b5 b4 b3 b2 b1 b0
BCNTAR[7:0]
x: Undefined
The BCNT0AR counter is a readable/writable alarm register corresponding to 32-bit binary counter b7 to b0.
This register is cleared to 00h by an RTC software reset.
b7 b6 b5 b4 b3 b2 b1 b0
x: Undefined
RMINAR is an alarm register corresponding to the BCD-coded minute counter RMINCNT. When the ENB bit is set to 1,
the RMINAR value is compared with the RMINCNT value. From among the alarm registers (RSECAR, RMINAR,
RHRAR, RWKAR, RDAYAR, RMONAR, and RYRAREN), only those selected with the ENB bits set to 1 are compared
with the corresponding counters. When the respective values all match, the corresponding IR92.IR flag of the ICU is set
to 1.
RMINAR values from 00 through 59 (practically in BCD) can be specified; if a value outside of this range is specified,
the RTC does not operate correctly.
This register is cleared to 00h by an RTC software reset.
b7 b6 b5 b4 b3 b2 b1 b0
BCNTAR[15:8]
x: Undefined
The BCNT1AR counter is a readable/writable alarm register corresponding to 32-bit binary counter b15 to b8.
This register is cleared to 00h by an RTC software reset.
b7 b6 b5 b4 b3 b2 b1 b0
x: Undefined
RHRAR is an alarm register corresponding to the BCD-coded hour counter RHRCNT. When the ENB bit is set to 1, the
RHRAR value is compared with the RHRCNT value. From among the alarm registers (RSECAR, RMINAR, RHRAR,
RWKAR, RDAYAR, RMONAR, and RYRAREN), only those selected with the ENB bits set to 1 are compared with the
corresponding counters. When the respective values all match, the corresponding IR92.IR flag of the ICU is set to 1.
The specifiable time differs according to the setting in the time mode bit (RCR2.HR24).
When the RCR2.HR24 bit is 0: From 00 to 11 (practically in BCD)
When the RCR2.HR24 bit is 1: From 00 to 23 (practically in BCD)
If a value outside of this range is specified, the RTC does not operate correctly.
When the RCR2.HR24 bit is 0, be sure to set the PM bit.
When the RCR2.HR24 bit is 1, the setting in the PM bit has no effect.
This register is cleared to 00h by an RTC software reset.
b7 b6 b5 b4 b3 b2 b1 b0
BCNTAR[23:16]
x: Undefined
The BCNT2AR counter is a readable/writable alarm register corresponding to 32-bit binary counter b23 to b16.
This register is cleared to 00h by an RTC software reset.
b7 b6 b5 b4 b3 b2 b1 b0
ENB — — — — DAYW[2:0]
x: Undefined
RWKAR is an alarm register corresponding to the BCD-coded day-of-week counter RWKCNT. When the ENB bit is set
to 1, the RWKAR value is compared with the RWKCNT value. From among the alarm registers (RSECAR, RMINAR,
RHRAR, RWKAR, RDAYAR, RMONAR, and RYRAREN), only those selected with the ENB bits set to 1 are compared
with the corresponding counters. When the respective values all match, the corresponding IR92.IR flag of the ICU is set
to 1.
RWKAR values from 0 through 6 (practically in BCD) can be specified; if a value outside of this range is specified, the
RTC does not operate correctly.
This register is cleared to 00h by an RTC software reset.
b7 b6 b5 b4 b3 b2 b1 b0
BCNTAR[31:24]
x: Undefined
The BCNT3AR counter is a readable/writable alarm register corresponding to 32-bit binary counter b31 to b24.
This register is cleared to 00h by an RTC software reset.
b7 b6 b5 b4 b3 b2 b1 b0
x: Undefined
RDAYAR is an alarm register corresponding to the BCD-coded date counter RDAYCNT. When the ENB bit is set to 1,
the RDAYAR value is compared with the RDAYCNT value. From among the alarm registers (RSECAR, RMINAR,
RHRAR, RWKAR, RDAYAR, RMONAR, and RYRAREN), only those selected with the ENB bits set to 1 are compared
with the corresponding counters. When the respective values all match, the corresponding IR92.IR flag of the ICU is set
to 1.
RDAYAR values from 01 through 31 (practically in BCD) can be specified; if a value outside of this range is specified,
the RTC does not operate correctly.
This register is cleared to 00h by an RTC software reset.
b7 b6 b5 b4 b3 b2 b1 b0
ENB[7:0]
x: Undefined
The BCNT0AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary
counter b7 to b0. Among the ENB[31:0] bits, the binary counter (BCNT[31:0]) corresponding to the bits which are set to
1 and the binary alarm register (BCNTAR[31:0]) are compared, and when all match, the ICU IR92.IR flag becomes 1.
This register is cleared to 00h by an RTC software reset.
b7 b6 b5 b4 b3 b2 b1 b0
x: Undefined
RMONAR is an alarm register corresponding to the BCD-coded month counter RMONCNT. When the ENB bit is set to
1, the RMONAR value is compared with the RMONCNT value. From among the alarm registers (RSECAR, RMINAR,
RHRAR, RWKAR, RDAYAR, RMONAR, and RYRAREN), only those selected with the ENB bits set to 1 are compared
with the corresponding counters. When the respective values all match, the corresponding IR92.IR flag of the ICU is set
to 1.
RMONAR values from 01 through 12 (practically in BCD) can be specified; if a value outside of this range is specified,
the RTC does not operate correctly.
This register is cleared to 00h by an RTC software reset.
b7 b6 b5 b4 b3 b2 b1 b0
ENB[15:8]
x: Undefined
The BCNT1AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary
counter b15 to b8. Among the ENB[31:0] bits, the binary counter (BCNT[31:0]) corresponding to the bits which are set
to 1 and the binary alarm register (BCNTAR[31:0]) are compared, and when all match, the ICU IR92.IR flag becomes 1.
This register is cleared to 00h by an RTC software reset.
— — — — — — — — YR10[3:0] YR1[3:0]
x: Undefined
— — — — — — — — ENB[23:16]
x: Undefined
The BCNT2AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary
counter b23 to b16. Among the ENB[31:0] bits, the binary counter (BCNT[31:0]) corresponding to the bits which are set
to 1 and the binary alarm register (BCNTAR[31:0]) are compared, and when all match, the ICU IR92.IR flag becomes 1.
This register is cleared to 0000h by an RTC software reset.
b7 b6 b5 b4 b3 b2 b1 b0
ENB — — — — — — —
x: Undefined
When the ENB bit in RYRAREN is set to 1, the RYRAR value is compared with the RYRCNT value. From among the
alarm registers (RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, RMONAR, and RYRAREN), only those selected
with the ENB bits set to 1 are compared with the corresponding counters. When the respective values all match, the
corresponding IR92.IR flag of the ICU is set to 1.
This register is cleared to 00h by an RTC software reset.
b7 b6 b5 b4 b3 b2 b1 b0
ENB[31:24]
x: Undefined
The BCNT3AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary
counter b31 to b24. Among the ENB[31:0] bits, the binary counter (BCNT[31:0]) corresponding to the bits which are set
to 1 and the binary alarm register (BCNTAR[31:0]) are compared, and when all match, the ICU IR92.IR flag becomes 1.
This register is cleared to 00h by an RTC software reset.
b7 b6 b5 b4 b3 b2 b1 b0
x: Undefined
The RCR1 register is used in both calendar count mode and in binary count mode.
Bits AIE, PIE, and PES[3:0] are updated in synchronization with the count source. When RCR1 is modified, check that
all the bits have been updated without fail before continuing with further processing.
b7 b6 b5 b4 b3 b2 b1 b0
x: Undefined
b7 b6 b5 b4 b3 b2 b1 b0
x: Undefined
b7 b6 b5 b4 b3 b2 b1 b0
— — — — RTCDV[2:0] RTCEN
x: Undefined
The following are examples that may significantly affect oscillation accuracy:
b7 b6 b5 b4 b3 b2 b1 b0
PMADJ[1:0] ADJ[5:0]
x: Undefined
The RADJ register is used in both calendar count mode and in binary count mode.
Adjustment is performed by the addition to or subtraction from the prescaler.
In case when the automatic adjustment enable (RCR2.AADJE) bit is 0, adjustment is performed when writing to the
RADJ.
In case when the RCR2.AADJE bit is 1, adjustment is performed in the interval specified by the automatic adjustment
period select (RCR2.AADJP) bit.
The current adjustment by software may be invalid if the following adjustment value is specified within 320 cycles of the
count source after the register setting. To perform adjustment consecutively, wait for 320 cycles or more of the count
source after the register setting and then specify the next adjustment value.
RADJ is updated in synchronization with the count source. When RADJ is modified, check that all the bits have been
updated without fail before continuing with further processing.
This register is cleared to 00h by an RTC software reset.
25.3 Operation
Power on
Clock and count mode settings Clock supply setting and count mode setting
No
START = 0 Wait for the RCR2.START bit to be cleared to 0
Yes
No
RESET = 0 Wait for the RCR2.RESET bit to be cleared to 0
Yes
Note 1. This step is not necessary when the START bit is set to 0 and the counter mode is set.
A value corresponding to the counter mode setting must be written to the RCR2.CNTMD bit.
No
START = 0 Wait for the START bit in RCR2 to be cleared to 0
Yes
Reset the prescaler and 64CNT Write 1 to the RESET bit in RCR2*1
Set clock error adjustment values Set clock error adjustment values
No
START = 1 Wait for the START bit in RCR2 to be set to 1
Yes
Note 1. This step is not necessary for the time-setting procedure because an RTC software reset
is executed in the clock setting procedure of the initial settings for the power supply.
No
ADJ30 = 0 Wait for the ADJ30 bit in RCR2 to be cleared to 0
Yes
Enable the RTC carry interrupt request Write 1 to the CIE bit in RCR1
Clear the carry flag Write 0 to the IR63.IR flag of the ICU
Yes
Carry flag = 1? Read the IR63.IR flag of the ICU for checking
No
Clear the carry flag Write 0 to the IR63.IR flag of the ICU
Enable the ICU carry interrupt request Write 1 to the IER07.IEN7 bit of the ICU
Enable the RTC carry interrupt request Write 1 to the CIE bit in RCR1
Clear the carry flag Write 0 to the IR63.IR flag of the ICU
Yes
Interrupt?
No
Disable the RTC carry interrupt Write 0 to the CIE bit in RCR1*1
If a carry occurs while the 64-Hz counter and time are being read, the correct time will not be obtained, so they must be
read again. The procedure for reading the time without using interrupts is shown in (a) in Figure 25.6, and the procedure
using carry interrupts in (b). To keep the program simple, method (a) should be used in most cases.
Enable the RTC alarm interrupt request Write 1 to the AIE bit in RCR1
Enable the ICU alarm interrupt request Write 1 to the IER0B.IEN4 bit of the ICU
Monitor alarm time Wait for alarm interrupt or the IR92.IR flag of
(wait for interrupt or check alarm flag) the ICU to be set to 1
In calendar count mode, an alarm can be generated by any one of year, month, date, day-of-week, hour, minute or second,
or any combination of those. Write 1 to the ENB bit in the alarm registers involved in the alarm setting, and set the alarm
time in the lower bits. Write 0 to the ENB bit in registers not involved in the alarm setting.
In binary count mode, an alarm can be generated in any bit combination of 32 bits. Write 1 to the ENB bit of the alarm
enable register corresponding to the target bit of the alarm, and set the alarm time to the alarm register. For bits that are
not target of the alarm, write 0 to the ENB bit of the alarm enable register.
When the counter and the alarm time match, the IR92.IR flag of the ICU is set to 1. Alarm detection can be confirmed by
reading this bit, but an interrupt should be used in most cases. If 1 has been set in the IER0B.IEN4 bit of the ICU, an
alarm interrupt is generated in the event of alarm, enabling the alarm to be detected.
Writing 0 clears the IR92.IR flag of the ICU.
When the counter and the alarm time match in a low power consumption state, this LSI returns from the low power
consumption state.
Enable the alarm interrupt The AIE bit in the RCR1 register has been set to 1
Yes
Register settings:
RADJ.PMADJ[1:0] = 10b (subtraction)
RADJ.ADJ[5:0] = 1 (01h)
This is written to the RADJ register once per 1-second interrupt.
Alarm registers
Clock counters
Detail
Rising edges of the R64CNT signals
64-Hz signal in R64CNT are detected in the same way.
The counter must be stopped before writing to any of the above registers.
Interrupts
are The set period elapses
generated
with the
specified
period. An interrupt is generated Confirm generation of a periodic interrupt
Note 1. When a interrupt generation period is changed while the periodic interrupt is used, an interrupt
may be generated at the completion of the setting. If the interrupt is generated immediately after
the setting, the period is not guaranteed for two interrupts including the current interrupt.
25.5.5 Points for Caution when Writing to and Reading from Registers
When reading a counter register such as the second counter/binary counter 0 after having written to the counter
register, follow the procedure in section 25.3.5, Reading 64-Hz Counter and Time.
When reading the count registers, alarm registers, year alarm enable register, bits RCR2.AADJE, AADJP, and
HR24, or RCR3 register after having written to the registers, perform three dummy read operations to ensure that
the written value has been reflected in the register.
When reading the RCR1.CIE, RTCOS, and RCR2.RTCOE bits after having written to the register, the written value
can be read.
To read the value from the timer counter after return from a reset, or period in software standby mode, wait for 1/
128 second while the clock is operating (the RCR2.START bit = 1).
26.1 Overview
The IWDT has two start modes: auto-start mode, in which counting automatically starts after release from the reset state,
and register start mode, in which counting is started by refreshing the IWDT (writing to the register).
In auto-start mode, necessary settings (clock division ratio, refresh window start and end positions, time-out period, reset
or non-maskable interrupt request output at an underflow, and count stop control in sleep mode) should be made in
option function select register 0 (OFS0) before release from the reset state.
In register start mode, necessary settings (clock division ratio, refresh window start and end positions, time-out period,
reset or non-maskable interrupt request output at an underflow, and count stop control in sleep mode) should be made in
the respective registers before the counter is started by refreshing after release from the reset state.
Set the IWDT start mode select bit (OFS0.IWDTSTRT) to select auto-start mode or register start mode.
When auto-start mode is selected (OFS0.IWDTSTRT = 0), the IWDT control register (IWDTCR), IWDT reset control
register (IWDTRCR), and IWDT count stop control register (IWDTCSTPR) settings are disabled and option function
select register 0 (OFS0) settings are enabled.
When register start mode is selected (OFS0.IWDTSTRT = 1), option function select register 0 (OFS0) settings are
ignored and the IWDTCR, IWDTRCR, and IWDTCSTPR settings take effect.
Specifications of the IWDT are listed in Table 26.1.
Note 1. Satisfy the frequency of the peripheral module clock (PCLKB) 4 × (the frequency of the count clock source after division).
To use the IWDT, two clocks (peripheral clock (PCLK) and IWDT-dedicated clock (IWDTCLK)) should be supplied so
that the IWDT works while the peripheral clock (PCLK) stops. The bus interface and registers operate with PCLK, and
the 14-bit down-counter and control circuits operate with IWDTCLK.
Signal lines between the blocks operating with the peripheral clock and IWDT-dedicated clock are connected through
synchronization circuits.
Figure 26.1 is a block diagram of the IWDT.
Clock
frequency
divider
IWDTCLK
IWDTCLK IWDTCLK/16
IWDTCLK/32
IWDTCLK/64 IWDT control circuit 14-bit down-counter
IWDTCLK/128
IWDTCLK/256
IWDTCSTPR
IWDTCR
IWDTRR
IWDTSR
b7 b6 b5 b4 b3 b2 b1 b0
There are some restrictions on writing to the IWDTCR register. For details, refer to section 26.3.2, Control over
Writing to the IWDTCR, IWDTRCR, and IWDTCSTPR Registers.
In auto-start mode, the settings in the IWDTCR register are disabled, and the settings in option function select register 0
(OFS0) are enabled. The bit setting made to the IWDTCR register can also be made in option function select register 0
(OFS0). For details, refer to section 26.3.8, Correspondence between Option Function Select Register 0 (OFS0)
and IWDT Registers.
Table 26.3 Relationship between Time-Out Period and Window Start and End Counter Values
TOPS[1:0] Bits Time-Out Period Window Start and End Counter Value
b1 b0 Cycles Counter Value 100% 75% 50% 25%
0 0 1024 03FFh 03FFh 02FFh 01FFh 00FFh
0 1 4096 0FFFh 0FFFh 0BFFh 07FFh 03FFh
1 0 8192 1FFFh 1FFFh 17FFh 0FFFh 07FFh
1 1 16384 3FFFh 3FFFh 2FFFh 1FFFh 0FFFh
Figure 26.2 RPSS[1:0] and RPES[1:0] Bit Settings and the Refresh-Permitted Period
IWDTSR is initialized by the reset source of the IWDT. IWDTSR is not initialized by other reset sources.
b7 b6 b5 b4 b3 b2 b1 b0
RSTIR — — — — — — —
QS
Value after reset: 1 0 0 0 0 0 0 0
There are some restrictions on writing to the IWDTRCR register. For details, refer to section 26.3.2, Control over
Writing to the IWDTCR, IWDTRCR, and IWDTCSTPR Registers.
In auto-start mode, the IWDTRCR register setting are disabled, and the settings in option function select register 0
(OFS0) enabled. The bit setting mode to the IWDTRCR register can also be made in option function select register 0. For
details, refer to section 26.3.8, Correspondence between Option Function Select Register 0 (OFS0) and IWDT
Registers.
b7 b6 b5 b4 b3 b2 b1 b0
SLCST — — — — — — —
P
Value after reset: 1 0 0 0 0 0 0 0
IWDTCSTPR controls whether to stop the IWDT down-counter at transitions to low power consumption modes. There
are some restrictions on writing to the IWDTCSTPR register. For details, refer to section 26.3.2, Control over Writing
to the IWDTCR, IWDTRCR, and IWDTCSTPR Registers.
In auto-start mode, the settings in the IWDTCSTPR register are ignored, and the settings in option function select
register 0 (OFS0) take effect. The bit setting mode to the IWDTCSTPR register can also be made in option function
select register 0 (OFS0). For details, refer to section 26.3.8, Correspondence between Option Function Select
Register 0 (OFS0) and IWDT Registers.
26.3 Operation
Counter value
100%
Refresh-
prohibited
75% period
Refresh-
50% permitted
period
25% Refresh-
prohibited
0% period
RES# pin
Control register
(IWDTCR) (1) (2) (2) (2)
Status flag
H
Refresh error flag cleared
Active: High L
H
Underflow flag Status flag
Active: High L cleared
Interrupt request
(WUNI) H
Active: Low
Reset output H
from IWDT
L
Active: High
Counter value
100%
Refresh-
prohibited period
75%
50% Refresh-
permitted period
25%
Refresh-
prohibited period
0%
RES# pin
Refresh H
the counter
Active: High L
Underflow
Refresh error Refresh error
Status flag
Refresh error flag H cleared
Active: High L
Interrupt request
(WUNI) H
Active: Low L
Reset output
from IWDT
Active: High L
26.3.2 Control over Writing to the IWDTCR, IWDTRCR, and IWDTCSTPR Registers
Writing to the IWDT control register (IWDTCR), IWDT reset control register (IWDTRCR), or IWDT count stop control
register (IWDTCSTPR) is only possible once between the release from the reset state and the first refresh operation.
After a refresh operation (counting starts) or IWDTCR, IWDTRCR, or IWDTCSTPR is written to, the protection signal
in the IWDT becomes 1 to protect IWDTCR, IWDTRCR, and IWDTCSTPR against subsequent attempts at writing.
This protection is released by the reset source of the IWDT. With other reset sources, the protection is not released.
Figure 26.5 sows control waveforms produced in response to writing to the IWDTCR.
RES# pin
IWDTCR register 33F3h (initial value) 00F3h 00F3h 33F3h (initial value)
Register
protection signal
(internal signal) IWDTCR register is protected
(writing-disabled period)
Writing is possible
[Sample sequences of writing that are valid for refreshing the counter]
00h→FFh
00h (n–1-th time) →00h (n-th time) →FFh
00h→access to another register or read from IWDTRR→FFh
[Sample sequences of writing that are not valid for refreshing the counter]
23h (a value other than 00h) →FFh
00h→54h (a value other than FFh)
00h→AAh (00h and a value other than FFh) →FFh
Even when 00h is written to IWDTRR outside the refresh-permitted period, if FFh is written to IWDTRR in the refresh-
permitted period, the writing sequence is valid and refreshing will be done.
After FFh is written to the IWDTRR register, refreshing the down-counter requires up to four cycles of the signal for
counting (the clock division ratio selection (the clock division ratio selection (IWDTCR.CKS[3:0]) bits determine how
many cycles of the IWDT-dedicated clock (IWDTCLK) make up one cycle for counting). Therefore, writing FFh to the
IWDTRR should be completed four-count cycles before the end position of the refresh-permitted period or a counter
underflow. The value of the down-counter can be checked by the counter bits (IWDTSR.CNTVAL[13:0]).
Figure 26.6 shows the IWDT refresh-operation waveforms when PCLK > IWDTCLK and clock division ratio =
IWDTCLK.
Peripheral clock
(PCLK)
IWDT-dedicated
clock (IWDTCLK)
Data written to
00h 54h 00h FFh
IWDTRR register
Invalid
Refresh
synchronization signal
Refresh signal
(after synchronization Refresh request
with IWDTCLK)
Refreshing
Figure 26.6 IWDT Refresh Operation Waveforms (IWDTCR.CKS[3:0] = 0000b, IWDTCR.TOPS[1:0] = 11b)
Peripheral clock
(PCLK)
IWDT-dedicated
clock (IWDTCLK)
Refreshing
(after synchronization with IWDTCLK)
Counter value (n+1)h (n)h (n-1)h (n-2)h (n-3)h 3FFFh 3FFEh
Bits
IWDTSR.CNTVAL (n+1)h (n)h (n-1)h (n-2)h (n-3)h 3FFFh
[13:0]
IWDTSR.CNTVAL
[13:0] read signal
(internal signal)
IWDTSR.CNTVAL
[13:0] read data xxxxh (n+1)h (n)h (n-2)h 3FFFh
Figure 26.7 Processing for Reading IWDT Down-Counter Value (IWDTCR.CKS[3:0] = 0000b,
IWDTCR.TOPS[1:0] = 11b)
26.3.8 Correspondence between Option Function Select Register 0 (OFS0) and IWDT
Registers
Table 26.5 lists the correspondence between option function select register 0 (OFS0) and the IWDT registers (IWDT
control register (IWDTCR), IWDT reset control register (IWDTRCR), and IWDT count stop control register
(IWDTCSTPR)) regarding control of the down-counter, reset or interrupt request output, and count stop function.
Control can be switched between option function select register 0 (OFS0) and the IWDT registers (IWDTCR,
IWDTRCR, and IWDTCSTPR) through the setting of the IWDT start mode select bit (OFS0.IWDTSTRT) in option
function select register 0 (OFS0).
Note that option function select register 0 (OFS0) setting should be kept unchanged during IWDT operation.
For details on option function select register 0 (OFS0), see section 7.2.1, Option Function Select Register 0
(OFS0).
Table 26.5 Correspondence between Option Function Select Register 0 (OFS0) and IWDT Registers
OFS0 Register IWDT Registers
(Effective in Auto-Start Mode) (Effective in Register Start Mode)
Target of Control Function OFS0.IWDTSTRT = 0 OFS0.IWDTSTRT = 1
Down-counter Time-out period selection OFS0.IWDTTOPS[1:0] IWDTCR.TOPS[1:0]
Clock frequency division ratio OFS0.IWDTCKS[3:0] IWDTCR.CKS[3:0]
selection
Window start position selection OFS0.IWDTRPSS[1:0] IWDTCR.RPSS[1:0]
Window end position selection OFS0.IWDTRPES[1:0] IWDTCR.RPES[1:0]
Reset output or Reset output or interrupt request OFS0.IWDTRSTIRQS IWDTRCR.RSTIRQS
interrupt request output selection
output
Count stop Sleep mode count stop control OFS0.IWDTSLCSTP IWDTCSTPR.SLCSTP
27.1 Overview
Table 27.1 lists the specifications of the SCIe module, Table 27.2 lists the specifications of the SCIf module, and Table
27.3 lists the specifications of the individual SCI channels.
Figure 27.1 is a block diagram depicting SCI1 and 9. Figure 27.2 is a block diagram depicting SCI5 and SCI6. Figure
27.3 is a block diagram depicting SCI12 (the SCIf module).
TEI
TXI
RXI
ERI
TEI
TXI
RXI
ERI
TMO0, TMO2
TMO1, TMO3 TMR
SCK12
RTS12#/CTS12#/SS12#
TMO0, 1
TMR
SCIe
SMISO12/RXDX12
TXD12/SSDA12/
SMOSI12/TXDX12/
SCIX0 interrupt signal SIOX12
Timer unit
Table 27.4 to Table 27.7 list the pin configuration of the SCIs for the individual modes.
Table 27.4 Input and Output Pins of the SCIs (Asynchronous/Clock Synchronous Modes)
Channel Pin Name I/O Function
SCI1 SCK1 I/O SCI1 clock input/output
RXD1 Input SCI1 receive data input
TXD1 Output SCI1 transmit data output
CTS1#/RTS1# I/O SCI1 transfer start control input/output
SCI5 SCK5 I/O SCI5 clock input/output
RXD5 Input SCI5 receive data input
TXD5 Output SCI5 transmit data output
CTS5#/RTS5# I/O SCI5 transfer start control input/output
SCI6 SCK6 I/O SCI6 clock input/output
RXD6 Input SCI6 receive data input
TXD6 Output SCI6 transmit data output
CTS6#/RTS6# I/O SCI6 transfer start control input/output
SCI9 SCK9 I/O SCI9 clock input/output
RXD9 Input SCI9 receive data input
TXD9 Output SCI9 transmit data output
CTS9#/RTS9# I/O SCI9 transfer start control input/output
SCI12 SCK12 I/O SCI12 clock input/output
RXD12 Input SCI12 receive data input
TXD12 Output SCI12 transmit data output
CTS12#/RTS12# I/O SCI12 transfer start control input/output
Address(es): SCI1.RDR 0008 A025h, SCI5.RDR 0008 A0A5h, SCI6.RDR 0008 A0C5h, SCI9.RDR 0008 A125h,
SCI12.RDR 0008 B305h
b7 b6 b5 b4 b3 b2 b1 b0
Address(es): SCI1.TDR 0008 A023h, SCI5.TDR 0008 A0A3h, SCI6.TDR 0008 A0C3h, SCI9.TDR 0008 A123h,
SCI12.TDR 0008 B303h
b7 b6 b5 b4 b3 b2 b1 b0
Address(es): SCI1.SMR 0008 A020h, SCI5.SMR 0008 A0A0h, SCI6.SMR 0008 A0C0h, SCI9.SMR 0008 A120h,
SCI12.SMR 0008 B300h
b7 b6 b5 b4 b3 b2 b1 b0
Note 1. n is the decimal notation of the value of n in BRR (see section 27.2.9, Bit Rate Register (BRR)).
Note 2. In clock synchronous mode, this bit setting is invalid and a fixed data length of 8 bits is used.
Note 3. LSB-first is fixed and the MSB (bit 7) in TDR is not transmitted in transmission.
Note 4. Writable only when TE in SCR = 0 and RE in SCR = 0 (both serial transmission and reception are disabled).
Address(es): SCI1.SMR 0008 A020h, SCI5.SMR 0008 A0A0h, SCI6.SMR 0008 A0C0h, SCI9.SMR 0008 A120h,
SCI12.SMR 0008 B300h
b7 b6 b5 b4 b3 b2 b1 b0
Note 1. n is the decimal notation of the value of n in BRR (see section 27.2.9, Bit Rate Register (BRR)).
Note 2. S is the value of S in BRR (see section 27.2.9, Bit Rate Register (BRR)).
Note 3. Writable only when TE in SCR = 0 and RE in SCR = 0 (both serial transmission and reception are disabled).
Address(es): SCI1.SCR 0008 A022h, SCI5.SCR 0008 A0A2h, SCI6.SCR 0008 A0C2h, SCI9.SCR 0008 A122h,
SCI12.SCR 0008 B302h
b7 b6 b5 b4 b3 b2 b1 b0
Address(es): SCI1.SCR 0008 A022h, SCI5.SCR 0008 A0A2h, SCI6.SCR 0008 A0C2h, SCI9.SCR 0008 A122h,
SCI12.SCR 0008 B302h
b7 b6 b5 b4 b3 b2 b1 b0
When GM in SMR = 1
b1 b0
0 0: Output fixed low
x 1: Clock output
1 0: Output fixed high
b2 TEIE Transmit End Interrupt Enable This bit should be 0 in smart card interface mode. R/W
b3 MPIE Multi-Processor Interrupt Enable This bit should be 0 in smart card interface mode. R/W
b4 RE Receive Enable 0: Serial reception is disabled R/W*2
1: Serial reception is enabled
b5 TE Transmit Enable 0: Serial transmission is disabled R/W*2
1: Serial transmission is enabled
b6 RIE Receive Interrupt Enable 0: RXI and ERI interrupt requests are disabled R/W
1: RXI and ERI interrupt requests are enabled
b7 TIE Transmit Interrupt Enable 0: A TXI interrupt request is disabled R/W
1: A TXI interrupt request is enabled
x: Don’t care
Note 1. Writable only when TE = 0 and RE = 0.
Note 2. A 1 can be written only when TE = 0 and RE = 0, while the SMR.CM bit is 1. After setting TE or RE to 1, only 0 can be written in
TE and RE. While the SMR.CM bit is 0, writing is enabled under any condition.
Address(es): SCI1.SSR 0008 A024h, SCI5.SSR 0008 A0A4h, SCI6.SSR 0008 A0C4h, SCI9.SSR 0008 A124h,
SCI12.SSR 0008 B304h
b7 b6 b5 b4 b3 b2 b1 b0
x: Undefined
Address(es): SCI1.SSR 0008 A024h, SCI5.SSR 0008 A0A4h, SCI6.SSR 0008 A0C4h, SCI9.SSR 0008 A124h,
SCI12.SSR 0008 B304h
b7 b6 b5 b4 b3 b2 b1 b0
x: Undefined
Address(es): SCI1.SCMR 0008 A026h, SCI5.SCMR 0008 A0A6h, SCI6.SCMR 0008 A0C6h, SCI9.SCMR 0008 A126h,
SCI12.SCMR 0008 B306h
b7 b6 b5 b4 b3 b2 b1 b0
Note 1. Writable only when TE in SCR = 0 and RE in SCR = 0 (both serial transmission and reception are disabled).
Note 2. S is the value of S in BRR (see section 27.2.9, Bit Rate Register (BRR)).
Address(es): SCI1.BRR 0008 A021h, SCI5.BRR 0008 A0A1h, SCI6.BRR 0008 A0C1h, SCI9.BRR 0008 A121h,
SCI12.BRR 0008 B301h
b7 b6 b5 b4 b3 b2 b1 b0
PCLK 106
Clock synchronous, simple SPI N= –1
8 22n-1 B
PCLK 106
Simple I2C *1 N= –1
64 22n-1 B
Table 27.9 Calculating Widths at High and Low Level for SCL
Mode SCL Formula (Result in Seconds)
I2C Width at high level 1
(minimum value) (N+1) × 4 × 22n-1 × 7 ×
PCLK × 106
Width at low level 1
(minimum value) (N+1) × 4 × 22n-1 × 8 ×
PCLK × 106
Table 27.12 lists sample N settings in BRR in normal asynchronous mode. Table 27.13 lists the maximum bit rate
settable for each operating frequency. Examples of BRR (N) settings in clock synchronous mode and simple SPI mode
are listed in Table 27.15. Examples of BRR (N) settings in smart card interface mode are listed in Table 27.17.
Examples of BRR (N) settings in simple I2C mode are listed in Table 27.19. In smart card interface mode, the number of
base clock cycles S in a 1-bit data transfer time can be selected. For details, see section 27.6.4, Receive Data
Sampling Timing and Reception Margin. Table 27.14 and Table 27.16 list the maximum bit rates with external
clock input.
When the asynchronous mode base clock select bit (ABCS) in the serial extended mode register (SEMR) is set to 1 in
asynchronous mode, the bit rate is two times that of listed in Table 27.12.
Table 27.12 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode)
Operating Frequency PCLK (MHz)
8 9.8304 10 12 12.288
Bit Rate
(bps) n N Error (%) n N Error (%) n N Error (%) n N Error (%) n N Error (%)
110 2 141 0.03 2 174 –0.26 2 177 –0.25 2 212 0.03 2 217 0.08
150 2 103 0.16 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00
300 1 207 0.16 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00
600 1 103 0.16 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00
1200 0 207 0.16 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00
2400 0 103 0.16 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00
4800 0 51 0.16 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00
9600 0 25 0.16 0 31 0.00 0 32 –1.36 0 38 0.16 0 39 0.00
19200 0 12 0.16 0 15 0.00 0 15 1.73 0 19 –2.34 0 19 0.00
31250 0 7 0.00 0 9 –1.70 0 9 0.00 0 11 0.00 0 11 2.40
38400 — — — 0 7 0.00 0 7 1.73 0 9 –2.34 0 9 0.00
Table 27.13 Maximum Bit Rate for Each Operating Frequency (Asynchronous Mode)
PCLK (MHz) Maximum Bit Rate (bps) n N
8 250000 0 0
9.8304 307200 0 0
10 312500 0 0
12 375000 0 0
12.288 384000 0 0
14 437500 0 0
16 500000 0 0
17.2032 537600 0 0
18 562500 0 0
19.6608 614400 0 0
20 625000 0 0
25 781250 0 0
Note: • When the ABCS bit in SEMR is set to 1, the bit rate is two times.
Table 27.14 Maximum Bit Rate with External Clock Input (Asynchronous Mode)
Maximum Bit Rate (bps)
PCLK (MHz) External Input Clock (MHz) SEMR.ABCS Bit = 0 SEMR.ABCS Bit = 1
8 2.0000 125000 250000
9.8304 2.4576 153600 307200
10 2.5000 156250 312500
12 3.0000 187500 375000
12.288 3.0720 192000 384000
14 3.5000 218750 437500
16 4.0000 250000 500000
17.2032 4.3008 268800 537600
18 4.5000 281250 562500
19.6608 4.9152 307200 614400
20 5.0000 312500 625000
25 6.2500 390625 781250
Table 27.15 BRR Settings for Various Bit Rates (Clock Synchronous Mode, Simple SPI Bus Mode)
Operating Frequency PCLK (MHz)
8 10 16 20 25
Bit Rate (bps) n N n N n N n N n N
110
250 3 124 — — 3 249
500 2 249 — — 3 124 — —
1k 2 124 — — 2 249 — — 3 97
2.5 k 1 199 1 249 2 99 2 124 2 155
5k 1 99 1 124 1 199 1 249 2 77
10 k 0 199 0 249 1 99 1 124 1 155
25 k 0 79 0 99 0 159 0 199 0 249
50 k 0 39 0 49 0 79 0 99 0 124
100 k 0 19 0 24 0 39 0 49 0 62
250 k 0 7 0 9 0 15 0 19 0 24
500 k 0 3 0 4 0 7 0 9 — —
1M 0 1 0 3 0 4 — —
2M 0 0*1 — — 0 1 — — — —
2.5 M 0 0*1 0 1 — —
4M 0 0*1 — — — —
5M 0 0*1 — —
6.25 M 0 0*1
7.5 M
Table 27.16 Maximum Bit Rate with External Clock Input (Clock Synchronous Mode, Simple SPI Mode)
PCLK (MHz) External Input Clock (MHz) Maximum Bit Rate (bps)
8 1.3333 1333333.3
10 1.6667 1666666.7
12 2.0000 2000000.0
14 2.3333 2333333.3
16 2.6667 2666666.7
18 3.0000 3000000.0
20 3.3333 3333333.3
25 4.1667 4166666.7
Table 27.17 BRR Settings for Various Bit Rates (Smart Card Interface Mode, n = 0, S = 372)
Bit Rate (bps) PCLK (MHz) n N Error (%)
9600 7.1424 0 0 0.00
10.00 0 1 30
10.7136 0 1 25
13.00 0 1 8.99
14.2848 0 1 0.00
16.00 0 1 12.01
18.00 0 2 15.99
20.00 0 2 6.66
25.00 0 3 12.49
Table 27.18 Maximum Bit Rate for Each Operating Frequency (Smart Card Interface Mode, S = 372)
PCLK (MHz) Maximum Bit Rate (bps) n N
10.00 13441 0 0
10.7136 14400 0 0
13.00 17473 0 0
16.00 21505 0 0
18.00 24194 0 0
20.00 26882 0 0
25.00 33602 0 0
Table 27.19 BRR Settings for Various Bit Rates (Simple I2C Mode)
Operating Frequency PCLK (MHz)
8 10 16 20 25
Bit Rate
(bps) n N Error (%) n N Error (%) n N Error (%) n N Error (%) n N Error (%)
10 k 0 24 0.0 0 31 –2.3 1 12 –3.8 1 15 –2.3 1 19 –2.3
25 k 0 9 0.0 0 12 –3.8 1 4 0.0 1 6 –10.7 1 7 –2.3
50 k 0 4 0.0 0 6 –10.7 1 2 –16.7 1 3 –21.9 1 3 –2.3
100 k 0 2 –16.7 0 3 –21.9 0 4 0.0 0 6 –10.7 1 1 –2.3
250 k 0 0 0.0 0 1 –37.5 0 1 0.0 0 2 –16.7 0 3 –21.9
350 k 0 1 –10.7 0 2 –25.6
Table 27.20 Minimum Widths at High and Low Level for SCL at Various Bit Rates (Simple I2C Mode)
Operating Frequency PCLK (MHz)
8 10 16 20
Min. Widths at
High/Low Level High/Low High/Low High/Low High/Low
for SCL (μs) n N Width n N Width n N Width n N Width
10 k 0 24 43.75/50.00 0 31 44.80/51.20 1 12 45.5/52.00 1 15 44.80/51.20
25 k 0 9 17.50/20.00 0 12 18.2/20.80 1 4 17.50/20.00 1 6 19.60/22.40
50 k 0 4 8.75/10.00 0 6 9.80/11.20 1 2 10.50/12.00 1 3 11.20/12.80
100 k 0 2 5.25/6.00 0 3 5.60/6.40 0 4 4.37/5.00 0 6 4.90/5.60
250 k 0 0 1.75/2.00 0 1 2.80/3.20 0 1 1.75/2.00 0 2 2.10/2.40
350 k 0 1 1.40/1.60
Operating Frequency
PCLK (MHz)
25
Min. Widths at
High/Low Level High/Low
for SCL (μs) n N Width
10 k 1 19 44.80/51.20
25 k 1 7 17.92/20.48
50 k 1 3 8.96/10.24
100 k 1 1 4.48/5.12
250 k 0 3 2.24/2.56
350 k 0 2 1.68/1.92
Address(es): SCI1.SEMR 0008 A027h, SCI5.SEMR 0008 A0A7h, SCI6.SEMR 0008 A0C7h, SCI9.SEMR 0008 A127h,
SCI12.SEMR 0008 B307h
b7 b6 b5 b4 b3 b2 b1 b0
b3 to b1 — Reserved These bits are read as 0. The write value should be 0. R/W
b4 ABCS Asynchronous Mode (Valid only in asynchronous mode) R/W*1
Base Clock Select 0: Selects 16 base clock cycles for 1-bit period
1: Selects 8 base clock cycles for 1-bit period
b5 NFEN Digital Noise Filter (In asynchronous mode) R/W*1
Function Enable 0: Noise cancellation function for the RXDn input signal is disabled.
1: Noise cancellation function for the RXDn input signal is enabled.
(in simple I2C mode)
0: Noise cancellation function for the SSCLn and SSDAn input signals is
disabled.
1: Noise cancellation function for the SSCLn and SSDAn input signals is
enabled.
The NFEN bit should be 0 in any mode other than above.
b6 — Reserved These bits are read as 0. The write value should be 0. R/W
b7 RXDESE Asynchronous Start Bit (Valid only in asynchronous mode) R/W*1
L Edge Detection Select 0: The low level on the RXDn pin is detected as the start bit.
1: A falling edge on the RXDn pin is detected as the start bit.
Note 1. Writable only when TE in SCR = 0 and RE in SCR = 0 (both serial transmission and reception are disabled).
SEMR selects the clock source for 1-bit period in asynchronous mode.
For SCI5, SCI6, and SCI12, the TMOn output (n = 0 to 3) of TMR units 0 and 1 can be set as the serial transfer base
clock.
Figure 27.4 shows a setting example when the TMOn output of TMRn (n = 0 to 3) is selected.
When using SCI6, set TMO2 as the base clock and TMO3 as clock enable.
Base clock 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3
TMO0 output
4 MHz
Clock enable
TMO1 output
1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3
SCK5
internal base clock 4 MHz
= 4 MHz x 3/4 3 MHz
= 3 MHz (average)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5
Figure 27.4 Example of Average Transfer Rate Setting when TMR Clock is Input
Address(es): SCI1.SNFR 0008 A028h, SCI5.SNFR 0008 A0A8h, SCI6.SNFR 0008 A0C8h, SCI9.SNFR 0008 A128h,
SCI12.SNFR 0008 B308h
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — NFCS[2:0]
In simple I2C mode, the standard settings for the clock source
selected for the on-chip baud rate generator are given below.
b2 b0
0 0 1: The clock signal divided by 1 is used with the noise filter.
0 1 0: The clock signal divided by 2 is used with the noise filter.
0 1 1: The clock signal divided by 4 is used with the noise filter.
1 0 0: The clock signal divided by 8 is used with the noise filter.
Note 1. Writing to these bits is only possible when the RE and TE bits in the SCR are 0 (disabling reception and transmission).
Address(es): SCI1.SIMR1 0008 A029h, SCI5.SIMR1 0008 A0A9h, SCI6.SIMR1 0008 A0C9h, SCI9.SIMR1 0008 A129h,
SCI12.SIMR1 0008 B309h
b7 b6 b5 b4 b3 b2 b1 b0
IICDL[4:0] — — IICM
Note 1. Writing to these bits is only possible when the RE and TE bits in the SCR are 0 (disabling reception and transmission).
SIMR1 is used to select simple I2C mode and the number of delay stages for the SSDA output.
Address(es): SCI1.SIMR2 0008 A02Ah, SCI5.SIMR2 0008 A0AAh, SCI6.SIMR2 0008 A0CAh, SCI9.SIMR2 0008 A12Ah,
SCI12.SIMR2 0008 B30Ah
b7 b6 b5 b4 b3 b2 b1 b0
Note 1. Writing to these bits is only possible when the RE and TE bits in the SCR are 0 (disabling serial reception and transmission).
SIMR2 is used to select how reception and transmission are controlled in simple I2C mode.
Address(es): SCI1.SIMR3 0008 A02Bh, SCI5.SIMR3 0008 A0ABh, SCI6.SIMR3 0008 A0CBh, SCI9.SIMR3 0008 A12Bh,
SCI12.SIMR3 0008 B30Bh
b7 b6 b5 b4 b3 b2 b1 b0
Note 1. Only generate a start condition after checking the bus state and confirming that it is free.
Note 2. Generate a restart or stop condition after checking the bus state and confirming that it is busy.
Note 3. Do not set more than one from among the IICSTAREQ, IICRSTAREQ, and IICSTPREQ bits to 1 at a given time.
Note 4. Execute the generation of a condition after the value of the IICSTIF flag is 0.
SIMR3 is used to control the simple I2C mode start and stop conditions, and to hold the SSDAn and SSCLn pins at fixed
levels.
Address(es): SCI1.SISR 0008 A02Ch, SCI5.SISR 0008 A0ACh, SCI6.SISR 0008 A0CCh, SCI9.SISR 0008 A12Ch,
SCI12.SISR 0008 B30Ch
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — — IICACK
R
Value after reset: 0 0 x x 0 x 0 0
x: Undefined
Address(es): SCI1.SPMR 0008 A02Dh, SCI5.SPMR 0008 A0ADh, SCI6.SPMR 0008 A0CDh, SCI9.SPMR 0008 A12Dh,
SCI12.SPMR 0008 B30Dh
b7 b6 b5 b4 b3 b2 b1 b0
Note 1. Writing to these bits is only possible when the RE and TE bits in the SCR are 0 (disabling reception and transmission).
Note 2. Only 0 can be written to these bits, which clears the flag.
SPMR is used to select the extension settings in asynchronous and clock-synchronous modes.
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — — ESME
Table 27.21 Settings of the ESME Bits and Guaranteed Operation by Timer Operation Mode
ESME bit Timer Mode Break Field Low Width Judgment Break Field Low Width Output
Mode Mode
0 ○*1 × ×
1 ○ ○ ○
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
When SCI12.SEMR.ABCS = 1
b7 b6
0 0: Rising edge of the 4th cycle of SCI base clock
0 1: Rising edge of the 5th cycle of SCI base clock
1 0: Rising edge of the 6th cycle of SCI base clock
1 1: Rising edge of the 7th cycle of SCI base clock
Note 1. The period of the SCI base clock is 1/16 of a single bit period when the SCI12.SEMR.ABCS is 0, and 1/8 of a single bit period
when the SCI12.SEMR.ABCS is 1. To use the SCI base clock, set the SCI12.SCR.TE bit to 1.
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — — SDST
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
CF0DR is an 8-bit readable and writable register that holds a value for comparison with Control Field 0.
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
CF0RR is a read-only register that holds the value received in Control Field 0. Writing to this register from the CPU or
DTC is not possible.
b7 b6 b5 b4 b3 b2 b1 b0
PCF1DR is an 8-bit readable and writable register that holds the 8-bit primary value for comparison with Control Field 1.
b7 b6 b5 b4 b3 b2 b1 b0
PCF1DR is an 8-bit readable and writable register that holds the 8-bit secondary value for comparison with Control Field
1.
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
CF1RR is a read-only register that holds the value received in Control Field 1. Writing to this register from the CPU or
DTC is not possible.
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — — TCST
b7 b6 b5 b4 b3 b2 b1 b0
Note 1. Rewrite the TOMS[1:0] and TCSS[2:0] bits only when the timer is stopped (TCST = 0).
b7 b6 b5 b4 b3 b2 b1 b0
TPRE consists of an eight-bit reload register, a read buffer, and a counter, each of which has FFh as its initial value. The
counter counts down in synchronization with the counter clock selected by the TMR.TCSS[2:0] bits, and is reloaded with
the value in the reload register when it underflows. Underflows of this register provide the clock source to drive counting
by the TCNT register. The reload register and read buffer are allocated to the same address, so in writing, transfer is to
the reload register and in reading, transfer is of the counter value from the read buffer.
It takes 1 system operating clock cycle to load a value from the reload register to the counter.
b7 b6 b5 b4 b3 b2 b1 b0
TCNT consists of an eight-bit reload register, a read buffer, and a counter, each of which has FFh as its initial value. This
down-counter counts underflows of the TPRE register until the TCNT register underflows, and is then reloaded with the
value from the reload register. The reload register and read buffer are allocated to the same address, so in writing, transfer
is to the reload register and in reading, transfer is of the counter value from the read buffer.
It takes 1 system operating clock cycle to load a value from the reload register to the counter.
Idle state
(mark state)
1 LSB MSB 1
1 2 3 4 5 6 7 8 9 10 11 12
CHR PE MP STOP
S: Start bit
STOP: Stop bit
P: Parity bit
MPB: Multi-processor bit
27.3.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI operates on a base clock with a frequency of 16 times*1 the bit rate.
In reception, the SCI samples the falling edge of the start bit using the base clock, and performs internal synchronization.
Since receive data is sampled at the rising edge of the 8th pulse*1 of the base clock, data is latched at the middle of each
bit, as shown in Figure 27.6. Thus the reception margin in asynchronous mode is determined by formula (1) below.
1 D - 0.5
M= (0.5 - ) - (L - 0.5) F - (1 + F) × 100 [%] ... Formula (1)
2N N
M: Reception margin
N: Ratio of bit rate to clock (N = 16 when ABCS in SEMR = 0, N = 8 when ABCS in SEMR = 1)
D: Duty cycle of clock (D = 0.5 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock frequency deviation
Assuming values of F = 0 and D = 0.5 in formula (1), the reception margin is determined by the formula below.
However, this is only the computed value, and a margin of 20% to 30% should be allowed in system design.
Note 1. This is an example when the ABCS bit in SEMR is 0. When the ABCS bit is 1, a frequency of 8 times the bit rate
is used as a base clock and receive data is sampled at the rising edge of the 4th pulse of the base clock.
16 clock pulses
8 clock pulses
0 7 15 0 7 7 15 0
Internal base clock
Synchronization
sampling timing
Data sampling
timing
27.3.3 Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input to the SCKn pin can be
selected as the SCI's transfer clock, according to the setting of the CM bit in SMR and the CKE[1:0] bits in SCR.
When an external clock is input to the SCKn pin, the clock frequency should be 16 times the bit rate (when ABCS in
SEMR = 0) and 8 times the bit rate (when ABCS in SEMR = 1). In addition, when an external clock is specified, the base
clock of TMR0 and TMR1 can be selected by the ACS0 bit in SEMR of SCIn (n = 5, 6, 12).
When the SCI is operated on an internal clock, the clock can be output from the SCKn pin. The frequency of the clock
output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the
transmit data, as shown in Figure 27.7.
SCKn
TXDn 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1
1 frame
Figure 27.7 Phase Relationship between Output Clock and Transmit Data
(Asynchronous Mode: SMR.CHR = 0, PE = 1, MP = 0, STOP = 1)
Start initialization [ 1 ] Make I/O port settings to enable input and output functions
as required for TXDn, RXDn, and SCKn pins.
Clear the SCR.TIE, RIE, TE, RE, and [ 2 ] Set the clock selection in SCR.
TEIE bits to 0
When the clock output is selected in asynchronous mode,
the clock is output immediately after SCR settings are made.
Set the I/O port functions [1]
[ 3 ] Clear the SIMR1.IICM bit to 0.
Clear the SPMR.CKPH and CKPOL bits to 0.
Set bits CKE[1:0] in SCR [2] Step [3] can be skipped if the values have not been changed
from the initial values.
Clear the SIMR1.IICM bit to 0
[3] [ 4 ] Set the data transmission/reception format in SMR, SCMR,
Clear the SPMR.CKPH and CKPOL bits to 0
and SEMR.
Set data transmission/reception format in [ 5 ] Write a value corresponding to the bit rate to BRR.
SMR, SCMR, and SEMR [4]
This step is not necessary if an external clock is used.
Initialization completion
1. The SCI transfers data from TDR to TSR when data is written to TDR in the TXI interrupt processing routine. The
TXI interrupt request at the beginning of transmission is generated when the TE bit in SCR is set to 1 after the TIE
bit in SCR is set to 1 or when these two bits are set to 1 simultaneously by a single instruction.
2. Transmission starts after the CTSE bit in SPMR is set to 0 (disabling the CTS function) and a low level on the CTS#
pin causes data transfer from TDR to TSR. If the TIE bit in SCR is 1 at this time, a TXI interrupt request is
generated. Continuous transmission is obtainable by writing the next data for transmission to TDR in the TXI
interrupt processing routine before transmission of the current data for transmission is completed.
3. Data is sent from the TXDn pin in the following order: start bit, transmit data, parity bit or multi-processor bit (may
be omitted depending on the format), and stop bit.
4. The SCI checks for updating of (writing to) TDR at the time of stop bit output.
5. When TDR is updated, setting of the CTSE bit in SPMR to 0 (CTS function disabled) or a low level input on the
CTSn# pin cause the next transfer of the next data for transmission from TDR to TSR and sending of the stop bit,
after which serial transmission of the next frame starts.
6. If TDR is not updated, the TEND flag in SSR is set to 1, the stop bit is sent, and then the mark state is entered in
which 1 is output. If the TEIE flag in SCR is 1 at this time, the TEND flag in SSR is set to 1 and a TEI interrupt
request is generated.
(TIE=1)
TXI interrupt flag
(IRn in ICU*1)
(TIE=0)
SSR.TEND flag
TXI interrupt Data written to TXI interrupt Data written to TDR in TXI TEI interrupt
request TDR in TXI request interrupt processing routine request generated
generated interrupt generated (Set the TIE bit to 0 and the
processing TEIE bit to 1 after writing the
routine last data)
1 frame
Note 1. Refer to Section 14, Interrupt Controller (ICUb) for the corresponding interrupt vector number.
Figure 27.9 Example of Operation for Serial Transmission in Asynchronous Mode (from the Middle of
Transmission until Transmission Completion) (Example with 8-Bit Data, Parity, One Stop Bit)
Figure 27.10 shows a sample flowchart for serial transmission in asynchronous mode.
Yes
No
Break output [4]
Yes
Set the I/O port functions
End
1. When the value of the RE bit in SCR becomes 1, the output signal on the RTSn# pin goes to the low level.
2. When the SCI monitors the communications line and detects a start bit, it performs internal synchronization, stores
receive data in RSR, and checks the parity bit and stop bit.
3. If an overrun error occurs, the ORER flag in SSR is set to 1. If the RIE bit in SCR is 1 at this time, an ERI interrupt
request is generated. Receive data is not transferred to RDR.
4. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in
SCR is 1 at this time, an ERI interrupt request is generated.
5. If a framing error (when the stop bit is 0) is detected, the FER bit in SSR is set to 1 and receive data is transferred to
RDR. If the RIE bit in SCR is 1 at this time, an ERI interrupt request is generated.
6. When reception finishes successfully, receive data is transferred to RDR. If the RIE bit in SCR is 1 at this time, an
RXI interrupt request is generated. Continuous reception is enabled by reading the receive data transferred to RDR
in this RXI interrupt processing routine before reception of the next receive data is completed. Reading out the
received data that have been transferred to RDR causes the RTSn# pin to output the low level.
SSR.FER flag
Note 1. Refer to Section 14, Interrupt Controller (ICUb) for the corresponding interrupt vector number.
Figure 27.11 Example of SCI Operation for Serial Reception in Asynchronous Mode (1)
(Example with 8-Bit Data, Parity, One Stop Bit)
SSR.FER flag
RTSn# pin
1 frame
Note 1. Refer to Section 14, Interrupt Controller (ICUb) for the corresponding interrupt vector number.
Figure 27.12 Example of SCI Operation for Serial Reception in Asynchronous Mode (2) (when RTS Function Is
Used) (Example with 8-Bit Data, Parity, One Stop Bit)
Table 27.23 lists the states of the SSR status flags and receive data handling when a receive error is detected.
If a receive error is detected, an ERI interrupt request is generated but an RXI interrupt request is not generated. Data
reception cannot be resumed while the receive error flag is 1. Accordingly, clear the ORER, FER, and PER bits to 0
before resuming reception. Moreover, be sure to read the RDR during overrun error processing.
Figure 27.13 and Figure 27.14 show samples of flowcharts for serial data reception.
Initialization [1]
[ 1 ] SCI initialization:
Start data reception The RXDn automatically becomes the input pin
for data being received.
No
RXI interrupt [ 5 ] Serial reception continuation procedure:
To continue serial reception, before the stop bit
of the current frame is received, read data from
Yes
RDR in the RXI interrupt processing routine. The
RDR data can also be read by activating the
DMAC or DTC.
Read receive data in RDR [4]
No
All data received? [5]
Yes
End
[3]
Error processing
No
SSR.ORER flag = 1
Yes
No
SSR.FER flag = 1
Yes
Yes
Break?
No
No
SSR.PER flag = 1
Yes
Read the SSR.ORER, PER, and FER flags. [8] [ 8 ] Confirming that the error flag is actually clear:
Read the error flag to confirm that its value is
actually 0.
<End>
Transmitting
station
Communication line
(MPB = 1)
Serial data
01h AAh
(MPB = 1) (MPB = 0)
Initialization
[1] [ 1 ] SCI initialization:
The TXDn automatically becomes the output pin for
data being transmitted.
Start data transmission After the TE bit in SCR is set to 1, 1 is output for a
frame, and transmission is enabled.
Yes
No
[4]
Break output
Yes
End
0 D0 D1 D7 1 1 0 D0 D1 D7 0 1 Idle state
(mark state)
MPIE
MPIE = 0 RXI interrupt request RDR data read in RXI RXI interrupt request not
(multi-processor interrupt processing MPIE bit set to 1 again
generated. RDR retains
interrupt) generated when the received ID
routine the state.
does not match the ID of
the receiving station itself
(a) When the received ID does not match the ID of the receiving station itself
0 D0 D1 D7 1 1 0 D0 D1 D7 0 1 Idle state
(mark state)
MPIE
MPIE = 0 RXI interrupt request RDR data read in RXI Since the received ID matches MPIE bit set to 1 again
(multi-processor interrupt processing the ID of the receiving station
interrupt) generated routine itself, reception continued and
data received in RXI interrupt
processing routine
(b) When the received ID matches the ID of the receiving station itself
Figure 27.17 Example of SCI Reception (8-Bit Data/Multi-Processor Bit/One Stop Bit)
Initialization [1]
[ 1 ] SCI initialization:
The RXDn automatically becomes the input pin for
data being received.
Start data reception
[ 2 ] ID reception cycle:
Set the MPIE bit in SCR to 1 and wait for ID
Set MPIE bit in SCR to 1. [2]
reception.
No
RXI interrupt? [4]
Yes
Yes
FER flag = 1 or ORER flag = 1
No
No
All data received? [5]
Error processing
Yes
(Continued to next page)
End
[5]
Error processing
No
SSR.ORER flag = 1
Yes
No
SSR.FER flag = 1
Yes
Yes
Break?
No
Read the SSR.ORER, PER, and FER flags. [8] [ 8 ] Confirming that the error flag is actually clear:
Read the error flag to confirm that its value is
actually 0.
<End>
LSB MSB
Serial data Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
27.5.1 Clock
Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the
SCKn pin can be selected, according to the setting of the CKE[1:0] bits in SCR.
When the SCI is operated on an internal clock, the synchronization clock is output from the SCKn pin. Eight
synchronization clock pulses are output in the transfer of one character, and when no transfer is performed the clock is
held high. However, when only data reception is performed, output of the synchronizing clock signal continues until the
CTS function is enabled and the high level is input on the CTSn# pin, an overflow error occurs, or the RE bit in SCR is
set to 0. When the CTS function is enabled, the synchronous clock signal output is stopped if the CTSn# pin input is high
on completion of the frame reception.
Start initialization [ 1 ] Make I/O port settings to enable input and output
functions as required for TXDn, RXDn, and SCKn
pins.
Clear bits TIE, RIE, TE, RE, and TEIE in
SCR to 0
[ 2 ] Set the clock selection in SCR.
When an internal clock is selected, the SCK pin
Set the I/O port functions [1] functions as the clock output pin.
Set TE or RE bit in SCR to 1, and set TIE and [ 6 ] Set the TE bit or RE bit in SCR to 1. Also set the
[6] TIE and RIE bits in SCR.
RIE bits in SCR
Setting the TE and RE bits allows TXDn and RXDn
to be used.
Transmission/reception
Note: • In simultaneous transmit and receive operations, the TE and RE bits in SCR should both be to 0 or
set to 1 simultaneously.
1. The SCI transfers data from TDR to TSR when data is written to TDR in the TXI interrupt processing routine. The
TXI interrupt request at the beginning of transmission is generated when the TE bit in SCR is set to 1 after the TIE
bit in SCR is set to 1 or when these two bits are set to 1 simultaneously by a single instruction.
2. After transferring data from TDR to TSR, the SCI starts transmission. When the SCR.TIE bit is set to 1 at this time,
a TXI interrupt request is generated. Continuous transmission is enabled by writing the next transmit data to TDR in
this TXI interrupt processing routine before transmission of the current transmit data has finished. When TEI
interrupt requests are in use, set the SCR.TIE bit to 0 (disabling TXI requests) and the SCR.TEIE bit to 1 (enabling
TEI requests) after the last of the data to be transmitted are written to the TDR from the processing routine for TXI
requests.
3. 8-bit data is sent from the TXDn pin in synchronization with the output clock when clock output mode has been
specified and in synchronization with the input clock when use of an external clock has been specified. Output of
the clock signal is suspended until the input CTS signal is at the low level while the CTSE bit in SPMR is 1
(enabling the CTS function).
4. The SCI checks for updating of (writing to) the TDR at the time of the last bit output.
5. When TDR is updated, the next transmit data is transferred from TDR to TSR, and serial transmission of the next
frame is started.
6. If TDR is not updated, set the SSR flag in TEND to 1 and the TXDn pin retains the output state of the last bit. If the
TEIE bit in SCR is 1 at this time, a TEI interrupt request is generated. The SCKn pin is held high.
Synchronization
clock
Note 1. Refer to Section 14, Interrupt Controller (ICUb) for the corresponding interrupt vector number.
Figure 27.22 Example of Operation for Serial Transmission in Clock Synchronous Mode
(from the Middle of Transmission until Transmission Completion)
No
TEI interrupt
Yes
End
Note: • When the external clock is in use (the value of the SCR.CKE[1:0] bits is 10b or 11b), the rising edge on the SCK pin for
the last bit sets the SSR.TEND flag to 1. Clearing the SCR.TE bit to 0 immediately after this may lead to insufficient
received-data hold time on the receiver side.
1. The value of the RE bit in SCR becoming 1 places the signal output on the RTS pin at the low level (when the RTS
function is in use).
2. The SCI performs internal initialization and starts receiving data in synchronization with a synchronization clock
input or output, and stores the receive data in RSR.
3. If an overrun error occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is 1 at this time, an ERI interrupt
request is generated. Receive data is not transferred to RDR.
4. When reception finishes successfully, receive data is transferred to RDR. If the RIE bit in SCR is 1 at this time, an
RXI interrupt request is generated. Continuous reception is enabled by reading the receive data transferred to RDR
in this RXI interrupt processing routine before reception of the next receive data is completed. Reading out the
received data that have been transferred to RDR causes the RTSn# pin to output the low level (when the RTS
function is in use).
Synchronization
clock
SSR.ORER flag
1 frame
Note 1. Refer to Section 14, Interrupt Controller (ICUb) for the corresponding interrupt vector number.
Figure 27.24 Example of Operation for Serial Reception in Clock Synchronous Mode (1) (when RTS Function is
not Used)
Synchronization
clock
SSR.ORER flag
RTSn# pin
1 frame
Note 1. Refer to Section 14, Interrupt Controller (ICUb) for the corresponding interrupt vector number.
Figure 27.25 Example of Operation for Serial Reception in Clock Synchronous Mode (2) (when RTS Function is
Used)
Data transfer cannot be resumed while a receive error flag is 1. Accordingly, clear the ORER, FER, and PER bits in SSR
to 0 before resuming reception. Moreover, be sure to read the RDR during overrun error processing.
Figure 27.26 shows a sample flowchart for serial data reception.
No
All data received? [5]
Yes
<End>
<End>
End
Note: • When switching from transmit or receive operation to simultaneous transmit and receive operations, first clear
the TIE, RIE, TE, RE, and TEIE bits in SCR to 0, and then set TIE, RIE, TE, and RE bits to 1 simultaneously.
VCC
TXDn
I/O
RXDn Data line
SCKn CLK
Clock line
Port RST
Reset line
RX220 IC card
Main unit of the device to
be connected
In normal transmission/reception
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
For communications with IC cards of the direct convention type and inverse convention type, follow the procedure
below.
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Figure 27.30 Direct Convention (SDIR in SCMR = 0, SINV in SCMR =0, PM in SMR = 0)
Ds D7 D6 D5 D4 D3 D2 D1 D0 Dp
Figure 27.31 Inverse Convention (SDIR in SCMR = 1, SINV in SCMR =1, PM in SMR = 1)
1 D - 0.5
M= (0.5 - ) - (L - 0.5) F - (1 + F) × 100 [%]
2N N
Assuming values of F = 0, D = 0.5, and N = 372 in the above formula, the reception margin is determined by the formula
below.
Synchronization sampling
timing
Figure 27.32 Receive Data Sampling Timing in Smart Card Interface Mode
(When Clock Frequency is 372 Times the Bit Rate)
To change reception mode to transmission mode, first check that reception has completed, and then initialize the SCI. At
the end of initialization, set TE = 1 and RE = 0. Reception completion can be verified by reading the RXI request, ORER,
or PER flag in SSR.
To change transmission mode to reception mode, first check that transmission has completed, and then initialize the SCI.
At the end of initialization, set TE = 0 and RE = 1. Transmission completion can be verified by reading the TEND flag in
SSR.
1. When an error signal from the receiver end is sampled after one-frame data has been transmitted, the ERS flag in
SSR is set to 1. If the RIE bit in SCR is 1 at this time, an ERI interrupt request is generated. Clear the ERS flag to 0
before the next parity bit is sampled.
2. For a frame in which an error signal is received, the TEND flag in SSR is not set. Data is retransferred from TDR to
TSR allowing automatic data retransmission.
3. If no error signal is returned from the receiver, the ERS flag is not set to 1.
4. In this case, the SCI judges that transmission of one-frame data (including retransfer) has been completed, and the
TEND flag is set. If the TIE bit in SCR is 1 at this time, a TXI interrupt request is generated. Writing transmit data
to TDR starts transmission of the next data.
Figure 27.35 shows a sample flowchart of serial transmission. All the processing steps are automatically performed
using a TXI interrupt request to activate the DTC or DMAC.
When the TEND flag in SSR is set to 1 in transmission, if the TIE bit in SCR is 1, a TXI interrupt request is generated.
The DTC or DMAC is activated by a TXI interrupt request if the TXI interrupt request is specified as a source of DTC or
DMAC activation beforehand, allowing transfer of transmit data. The TEND flag is automatically cleared to 0 when the
DTC or DMAC transfers the data.
If an error occurs, the SCI automatically re-transmits the same data. During this retransmission, the TEND flag is kept to
0 and the DTC or DMAC is not activated. Therefore, the SCI and DTC or DMAC automatically transmit the specified
number of bytes, including retransmission in the case of error occurrence. However, since the ERS flag is not
automatically cleared, set the RIE bit to 1 beforehand to enable an ERI interrupt request to be generated at error
occurrence, and clear the ERS flag to 0.
When transmitting/receiving data using the DTC or DMAC, be sure to make settings to enable the DTC or DMAC
before making SCI settings.
For DTC or DMAC settings, see section 16, DMA Controller (DMACA) and section 17, Data Transfer Controller
(DTCa).
(n + 1)-th transfer
n-th transfer frame Retransfer frame frame
(DE)
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Ds D0 D1 D2 D3 D4
[2] [4]
SSR.FER flag/
SSR.ERS flag
[1] [3]
Note that the SSR.TEND flag is set in different timings depending on the GM bit setting in SMR. Figure 27.34 shows
the TEND flag generation timing.
I/O data Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
11.0 etu
When GM bit in SMR = 1
Start
Initialization
No
SSR.ERS flag = 0?
Yes
Error processing
No
TXI interrupt
Yes
No
Write all transmit data
Yes
No
SSR.ERS flag = 0?
Yes
Error processing
No
TXI interrupt
Yes
End
1. If a parity error is detected in receive data, the PER flag in SSR is set to 1. When the RIE bit in SCR is 1 at this time,
an ERI interrupt request is generated. Clear the PER flag to 0 before the next parity bit is sampled.
2. For a frame in which a parity error is detected, no RXI interrupt is generated.
3. When no parity error is detected, the PER flag in SSR is not set to 1.
4. In this case, data is determined to have been received successfully. When the RIE bit in SCR is 1, an RXI interrupt
request is generated.
Figure 27.37 shows a sample flowchart for serial data reception. All the processing steps are automatically performed
using an RXI interrupt request to activate the DTC or DMAC.
In reception, setting the RIE bit to 1 allows an RXI interrupt request to be generated. The DTC or DMAC is activated by
an RXI interrupt request if the RXI interrupt request is specified as a source of DTC or DMAC activation beforehand,
allowing transfer of receive data.
If an error occurs during reception and either the ORER or PER flag in SSR is set to 1, a receive error interrupt (ERI)
request is generated. Clear the error flag after the error occurrence. If an error occurs, the DTC or DMAC is not activated
and receive data is skipped. Therefore, the number of bytes of receive data specified in the DTC or DMAC is transferred.
Even if a parity error occurs and the PER flag is set to 1 during reception, receive data is transferred to RDR, thus
allowing the data to be read.
Note 1. For operations in block transfer mode, see section 27.3, Operation in Asynchronous Mode.
(n + 1)-th transfer
n-th transfer frame Retransfer frame frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Ds D0 D1 D2 D3 D4
[2] [4]
SSR.PER flag
[1] [3]
Start
Initialization
SSR.ORER = 0 and No
SSR.PER = 0?
Yes
Error processing
No
RXI interrupt
Yes
No
All data received?
Yes
Clear bits RIE and RE
in SCR to 0
SCR.CKE0 bit
SCKn
At power-on and transitions to/from software standby mode, use the following procedure to secure the appropriate clock
duty cycle.
(1) At Power-On
To secure the appropriate clock duty cycle simultaneously with power-on, use the following procedure.
1. Initially, port input is enabled in the high-impedance state. To fix the potential level, use a pull-up or pull-down
resistor.
2. Fix the SCKn pin to the specified output by setting the SCR.CKE[1] bit and I/O port functions.
3. Set SMR and SCMR to enable smart card interface mode.
4. Set the SCR.CKE[0] bit to 1 to start clock output.
(a) At transition from smart card interface mode to software standby mode
1. Set I/O port functions to make the SCKn pin fixed with a desired output value in software standby mode.
2. Write 0 to the TE and RE bits in SCR to stop transmission/reception.
Simultaneously, set the SCR.CKE[1] bit to the value for the output fixed state in software standby mode.
3. Write 0 to the SCR.CKE[0] bit to stop the clock.
4. Wait for one cycle of the serial clock. In the mean time, the clock output is fixed to the specified level with the duty
cycle retained.
5. After switching the SCKn pin to the general I/O port function, make a transition to software standby mode.
(b) Return from software standby mode to smart card interface mode
6. Cancel software standby mode.
7. Set the SCR.CKE[0] bit to 1 to start clock output. A clock signal with the appropriate duty cycle is then generated.
Software
Normal operation standby Normal operation
SCKn
1 7 1 1 8 1 1 1
1 7 1 1 8 1 1 1
n (n = 1 or larger)
10-bit address format transmission
11110b + SLA
S (2 bits) W# A SLA (8 bits) A DATA (8 bits) A A/A# P
1 7 1 1 8 1 8 1 1 1
n (n = 1 or larger)
10-bit address format reception
11110b + SLA 11110b + SLA
S (2 bits) W# A SLA (8 bits) A Sr (2 bits) R A DATA (8 bits) A A# P
1 7 1 1 8 1 1 7 1 1 8 1 1 1
n (n = 1 or larger)
MSB LSB
SSDAn D7-D1 D0 D7-D1 D0 D7-D1 D0
S: Indicates a start condition, i.e. the master device changing the level on the SSDAn line from the high to the low level
while the SSCLn line is at the high level.
SLA: Indicates a slave address, by which the master device selects a slave device.
R/W#: Indicates the direction of transfer (reception or transmission). The value 1 corresponds to transfer from the slave device
to the master device and 0 corresponds to transfer from the master device to the slave device.
A/A#: Indicates an acknowledge bit. This is returned by the slave device for master transmission and by the master device for
master reception. Return of the low level indicates ACK and return of the high level indicates NACK.
Sr: Indicates a restart condition, i.e. the master device changing the level on the SSDAn line from the high to the low level
while the SSCLn line is at the high level and after the setup time has elapsed.
DATA: Indicates the data being received or transmitted.
P: Indicates a stop condition, i.e. the master device changing the level on the SSDAn line from the low to the high level
while the SSCLn line is at the high level.
Writing 1 to the IICRSTAREQ bit in SIMR3 causes the generation of a start condition. The generation of a start
condition proceeds through the following operations.
The SSDAn line is released and the SSCLn line is kept at the low level.
The period at low level for the SSCLn line is secured as half of a bit period at the bit rate determined by the setting
of the BRR.
The SSCLn line is released (transition from the low to the high level).
Once the high level on the SSCLn line is detected, the setup time for the restart condition is secured as half of a bit
period at the bit rate determined by the setting of the BRR.
The level on the SSDAn line falls (from the high level to the low level).
The hold time for the restart condition is secured as half of a bit period at the bit rate determined by the setting of the
BRR.
The level on the SSCLn line falls (from the high level to the low level), the IICRSTAREQ bit in SIMR3 is cleared
(to 0), and a restart-condition generated interrupt is output.
Writing 1 to the IICSTPREQ bit in SIMR3 causes the generation of a stop condition. The generation of a stop condition
proceeds through the following operations.
The level on the SSDAn line falls (from the high level to the low level) and the SSCLn line is kept at the low level.
The period at low level for the SSCLn line is secured as half of a bit period at the bit rate determined by the setting
of the BRR.
The SSCLn line is released (transition from the low to the high level).
Once the high level on the SSCLn line is detected, the setup time for the stop condition is secured as half of a bit
period at the bit rate determined by the setting of the BRR.
The SSDAn is released (transition from the low to the high level), the IICSTPREQ bit in SIMR3 is cleared (to 0),
and a stop-condition generated interrupt is output.
Figure 27.42 shows the timing of operations in the generation of start, restart, and stop conditions.
SSCLn
SSDAn
SIMR3.IICSTAREQ
SIMR3.IICRSTAREQ
SIMR3.IICSTPREQ
SIMR3.IICSDAS
11b 01b 00b 01b 00b 01b 11b
SIMR3.IICSCLS
Figure 27.42 Timing of Operations in the Generation of Start, Restart, and Stop Conditions
SSCLn line
Set the value in BRR. [ 5 ] Set the values in SEMR, SNFR, SIMR1, SIMR2, and
[4]
SPMR.
In SEMR, set the NFEN bit.
Set the values in SEMR, SNFR, SIMR1, In SNFR, set the NFCS[2:0] bits.
[5]
SIMR2, and SPMR. In SIMR1, set the IICM bit to 1 and the IICDL[4:0] bits
as required.
In SIMR2, set the IICACKT and IICCSC bits to 1 and
Set the SCR.RE and TE bit to 1 and set the
[6] the IICINTM bits as required.
SCR.TIE, RIE and TEIE bits.
In SPMR, clear all the bits to 0.
Start of transmission or reception [ 6 ] Set the RE and TE bits in the SCR to 1. Then, set the
SCR.TIE, RIE, and TEIE bits (for transmission and
when the SIMR2.IICINTM bit is 1, clear the RIE bit).
Setting the TE and RE bits to 1 makes the SSCLn and
SSDAn pin functions available.
Figure 27.45 Example of the Flow of SCI Initialization (for Simple I2C Mode)
SSCLn
Reception of ACK
Note 1. For details on the corresponding interrupt vector number see Section 14, Interrupt Controller (ICUb).
Figure 27.46 Example of Operations for Master Transmission in I2C Bus Mode
(with Seven-Bit Slave Addresses, Transmission Interrupts, and Reception Interrupts in Use)
When the SIMR2.IICINTM bit is set to 0 (ACK and NACK interrupts are used) during master transmission, the DTC or
DMAC is activated by the ACK interrupt as the trigger and necessary number of data bytes are transmitted. When the
NACK is received, error processing, such as transmission stop and re-transmission, is performed by the NACK interrupt
as the trigger.
SSCLn
STI interrupt flag Generation of RXI interrupt request Acceptance or RXI interrupt request
(IRn in the ICU*1)
Note 1. For details on the corresponding interrupt vector number see Section 14, Interrupt Controller (ICUb).
Figure 27.47 Example 2 of Operations for Master Transmission in Simple I2C Bus Mode
(with Seven-Bit Slave Addresses, ACK Interrupts, and NACK Interrupts in Use)
Set the SIMR3.IICSTIF to 0, and set the [5] Steps for continuing with serial transmission:
SIMR3.IICSCLS[1:0] and IICSDAS[1:0] bits to 00b.
When transmission is to continue, write further data for
transmission to TDR. Except for the first data to be
Write the slave address and value for the transmitted, a TXI request can activate the DMAC or DTC to
[3] handle writing of data to TDR.
R/W bit in TDR.
No
TXI interrupt?
Yes
Yes
Yes
No
All data transmitted? [5]
Yes
No
STI interrupt?
Yes
End
Figure 27.48 Example of the Procedure for Master Transmission Operations in Simple I2C Mode
(with Transmission Interrupts and Reception Interrupts in Use)
Start
condition Slave address (7 bits) R Received data Stop condition
SSCLn
TXI interrupt flag RXI is assumed to have been disabled by Generation of RXI interrupt request
(IRn in the ICU*1) setting SCR.RIE = 0.
Note 1. For details on the corresponding interrupt vector number, see Section 14, Interrupt Controller (ICUb).
Figure 27.49 Example of Operations for Master Reception in I2C Bus Mode
(with Seven-Bit Slave Addresses, Transmission Interrupts, and Reception Interrupts in Use)
Yes
[6] NACK is transmitted in response to the last data.
No
SISR.IICACKR = 0? [4]
[7] Generation of a stop condition.
Yes
Set SIMR2.IICACKT to 0.
Set SCR.RIE to 1.
Yes
Next data is the last?
[5]
No Set SIMR2.IICACKT to 1. [6]
Write FFh as dummy data to TDR.
Write FFh as dummy data to TDR.
No
RXI interrupt?
No
RXI interrupt?
Yes
Yes
Read received data from RDR.
Read received data from RDR.
No
TXI interrupt? No
TXI interrupt?
Yes
Yes
Yes
End
Figure 27.50 Example of the Procedure for Master Reception Operations in Simple I2C Mode
(with Transmission Interrupts and Reception Interrupts in Use)
SMOSIn (output)
Device 3 (slave)
SSn# (input)
SCKn (input)
SMISOn (output)
SMOSIn (input)
Figure 27.51 Example of Connections via a Simple SPI Mode (In Single Master Mode, SPMR.SSE Bit = 0)
Table 27.24 States of Pins by Mode and Input Level on the SSn# Pin
Mode Input on SSn# pin State of SMOSIn pin State of SMISOn pin State of SCKn pin
Master mode*1 High level Output for data Input for received data Clock output*3
(transfer can proceed) transmission*2
Low level High impedance Input for received data High impedance
(transfer cannot proceed) (but disabled)
Slave mode High level Input for received data High impedance Clock input
(transfer can proceed) (but disabled) (but disabled)
Low level Input for received data Output for data Clock input
(transfer cannot proceed) transmission
Note 1. When there is only a single master (SPMR.SSE = 0), transfer is possible regardless of the input level on the SSn# pin (this is
equivalent to input of a high level on the SSn# pin). Since the SSn# pin function is not required, the pin is available for other
purposes.
Note 2. The SMOSIn pin output is in the high-impedance state when transmission is disabled (SCR.TE bit = 0).
Note 3. The SCKn pin output is in the high-impedance state when transmission is disabled (SCR.TE and RE bits = 00b) in a multi-master
configuration (SPMR.SSE = 1).
SSn# pin
(slave)
SCKn pin
(CKPOL = 0)
SCKn pin
(CKPOL = 1)
SMOISIn pin Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
SMISOn pin Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
SSn# pin
(slave)
SCKn pin
(CKPOL = 0)
SCKn pin
(CKPOL = 1)
SMOISIn pin Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
SMISOn pin Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Figure 27.52 Relation between Clock Signal and Transmit/Receive Data in Simple SPI Mode
Break Field low width Break Field Inter Field Space Inter Field Space
high width
Information Frame
Data Field Data Field Data Field CRC16 Upper Field CRC16 Lower Field
Inter Field Space Inter Field Space Inter Field Space Inter Field Space
Figure 27.53 Protocol for Serial Transfer by the Extended Serial Mode Control Section
(1) With Break Field low width output mode as the operating mode for the timer, writing 1 to the TCST bit in TCR
starts counting by the timer, and the low level will be output from the TXDX12 pin over the period corresponding to
the TCNT and TPRE settings.
(2) The output on the TXDX12 pin is inverted when the timer counter underflows, and the BFDF bit in STR is set to 1.
An SCIX0 interrupt is also generated if the value of the BFDIE bit in ICR is 1.
(3) Writing 0 to the TCST bit in TCR stops counting by the timer, and SCI2 is used to send the data for Control Field 0.
After the Break Field low width output, stop counting before the next underflow occurs.
(4) Once the data for Control Field 0 have been transmitted, SCI12 is used to send the data for Control Field 1.
(5) Once the data for Control Field 1 have been transmitted, SCI12 is used to send an Information Frame.
Omit the Break Field and Control Field 0 to suit the structure of the Start Frame.
Break Field low width Control Field 0 Control Field 1 Data Field
Write 1 to
STCR.BFDCL
STR.BFDF
Start
Set SCI12.CR2.RTS[1:0], BCCS[1:0], Set the timing of sampling for RXDX12 reception, clock for bus-collision detection,
and DFCS[2:0] and sampling clock for the RXDX12 signal’s digital filter.
Set 10b to SCI12.TMR.TOMS[1:0] Set Break Field low width output mode as the operating mode of the timer.
Set SCI12.TMR.TCSS[2:0] Set the clock source for counting, TCNT, and TPRE to values that suit the period
Set TCNT and TPRE for the Break Field low width.
Set 1 to SCI12.TCR.TCST Start the timer counter and output of the Break Field low width.
The BFDF bit in STR is set to 1 on output of the Break Field low width. At
No
SCI12.STR.BFDF = 1? this time, if the BFDIE bit in ICR is 1, an SCIX0 interrupt is generated.
Yes
After output of the Break Field low width is completed, stop the timer
Clear SCI12.TCR.TCST to 0
counting before the next underflow of the timer occurs.
Set SCI12.SCR.TE to 0 and then 1. After setting the SCI12.SCR.TE bit to 0, set it to 1.
No
TXI interrupt?
The transmission data empty interrupt request (TXI) is generated. Write
transmit data in Control Field 0 to TDR with the TXI interrupt processing
Yes routine.
No
TXI interrupt?
The transmission data empty interrupt request (TXI) is generated. Write
transmit data in Control Field 1 to TDR with the TXI interrupt processing
Yes routine.
Figure 27.57 shows an example of operations to receive a Start Frame, which is composed of the Break Field low width,
Control Field 0, and Control Field 1. Figure 27.58 and Figure 27.59 are flowcharts for the reception of a Start Frame,
and Figure 27.60 is a state transition diagram for the extended serial mode control section.
Operations when the extended serial mode control section is to be used to receive a Start Frame are as listed below. Be
sure to use the SCI12 in asynchronous mode.
(1) With Break Field low width detection mode as the operating mode for the timer, writing 1 to the SDST bit in CR3
enables detection of the Break Field low width. RXDX12 input to the SCI12 module is disabled at this time.
(2) Low-level input on the RXDX12 pin continuing over a period longer than that corresponding to the settings of
TCNT and TPRE is detected as the Break Field low width. At this time, the BFDF bit in STR is set to 1. An SCIX0
interrupt is also generated if the value of the BFDIE bit in ICR is 1.
(3) When the input from the RXDX12 pin goes high after the Break Field low width, the RXDSF bit in CR0 becomes
zero and reception of Control Field 0 by the SCI12 module starts.
(4) If the data received in Control Field 0 match the data set in CF0DR, the CF0MF bit in STR is set to 1. An SCIX1
interrupt is also generated if the value of the CF0MIE bit in ICR is 1. Reception of Control Field 1 by the SCI12
module starts after that. If the data received in Control Field 0 do not match the data set in CF0DR, a transition to
the state prior to Break Field low width detection proceeds.
(5) If the data received in Control Field 1 match the data set in PCF1DR and SCF1DR, the CF1MF bit in STR is set to
1. An SCIX1 interrupt is also generated if the value of the CF1MIE bit in ICR is 1. Transfer of the Information
Frame by the SCI12 module starts after that. If the data received in Control Field 1 do not match the data set in
either or both of PCF1DR and SCF1DR, a transition to the state prior to Break Field low width detection proceeds.
Omit the Break Field and Control Field 0 to suit the structure of the Start Frame.
Break Field low width Control Field 0 Control Field 1 Data Field
SCI12 RXD
8 bits 8 bits
input
Write 1 to
CR3.SDST Clear to 0 after Break Field
low width detection
CR0.RXDSF
Specified period for
TCNT and TPRE Write 1 to
STCR.BFDCL
STR.BFDF
Write 1 to
STCR.CF0MCL
STR.CF0MF
Write 1 to
STCR.CF1MCL
STR.CF1MF
Start
Set SCI12.CR1.CF1DS[1:0] and PIBE Select the data for comparison with Control Field 1 and the
presence or absence of a priority interrupt bit.
Set the bits for comparison in Control Field 1 of SCI12.CF1CR Select the bits for comparison in Control Field 1.
Set the bits for comparison in Control Field 0 of SCI12.CF0CR Select the bits for comparison in Control Field 0.
Set SCI12.TMR.TCSS[2:0], and set SCI12.TCNT and Set the clock source for counting, TCNT, and TPRE to values
SCI12.TPRE that suit the period for the Break Field low width.
Set SCI12.PCR.SHARPS, RXDXPS, and TXDXPS Set the RXDX12 and TXDX12 pins.
Initialization
CR3.SDST = 1
Break Field
Non-match
Control Field 0
CR3.SDST = 1
Non-match
Control Field 1
Information Frame
Steps (1) to (4) are the same as in Figure 27.57, for Start-Frame reception.
(5) If the value of the bit selected by the PIBS[2:0] bits in CR1 matches the corresponding bit in PCF1DR, the PIBDF
bit in STR is set to 1. An SCIX1 interrupt is also generated if the value of the PIBDIE bit in ICR is 1. Transfer of the
Information Frame by the SCI12 module starts after that. If the data received in Control Field 1 do not match the
data set in either or both of PCF1DR and SCF1DR and the priority interrupt bit is not detected, a transition to the
state prior to Break Field low width detection proceeds.
Break Field low width Control Field 0 Control Field 1 Data Field
SCI12 RXD
8 bits
input
Write 1 to
CR3.SDST Clear to 0 after Break Field The bit specified by PIBS[2:0] in CR1
low width detection matches the value set in PCF1DR.
CR0.RXDSF
Specified period for
TCNT and TPRE Write 1 to
STCR.BFDCL
STR.BFDF
Write 1 to
STCR.CF0MCL
STR.CF0MF
STR.PIBDF
Write 1 to
STCR.PIBDCL
(1) (2) (3) (4) (5)
Figure 27.61 Example of Operations at the Time of Start-Frame Reception (with Priority Interrupts in Use)
CR2.BCCS[1:0]
No division
Bus-collision clock
STR.BCDF
Write 1 to
Conditions for the above figure: STCR.BCDCL
ESMER: ESME = 1
CR2: BCCS[1:0] = 01b
PCR: TXDXPS = 0, RXDXPS = 0
ICR: BCDIE = 1
CR2.DFCS[2:0]
PCLK/8
PCLK/16
PCLK/32
PCLK/128
RXDX12 input C C C
signal D Q D Q D Q Match-
detection
circuit
Sampling clock
(1) Writing 1 to the BRME bit in CR0 enables bit-rate measurement. Only set BRME to 1 when you wish to proceed
with bit-rate measurement. Furthermore, bit-rate measurement will not proceed during a Break Field, even if BRME
is set to 1.
(2) After detection of the Break Field low width, bit-rate measurement starts when the level input on the RXDX12 pin
becomes high.
(3) Once bit-rate measurement has started, counter values from the timer are retained in the read buffers on the input of
valid edges from the RXDX12 pin (rising and falling edges) and the counter is reloaded. An SCIX3 interrupt is also
generated if the value of the AEDIE bit in ICR is 1. Retention by TCNT and TPRE is released by reading these
registers.
(4) The bit rate as calculated from the values counted during intervals between valid edges can be used for adjusting the
rate by changing the settings of the SCI12 module. To disable the bit-rate measurement after a match with Control
Field 1, write 0 to the BRME bit in CR0.
Retained*3
Retention released Retained
Read buffer*1 11 10 0F 0E 0D FD FC FB FA F9 F8
*2 *4
STR.AEDF Read the counter value*5
Write 1 to
STCR.AEDCL
Note 1. The contents of the read buffers are read by reading TCNT and TPRE .
Note 2. The AEDF bit in STR becomes 1 on detection of a valid edge.
Note 3. The current counter value is retained in the read buffers on detection of a valid edge .
Note 4. The value retained in the read buffers due to one valid edge is not updated to the new value even if a further valid edge is detected.
Note 5. Retention of a value in a read buffer due to a valid edge is released by reading TCNT or TPRE .
16 clocks
27.9.8 Timer
The timer has the following operating modes.
FFFFh
Underflow
Contents of the counter (hex.)
Counting stops
Counting stops
Count started after reloading Count started
after reloading
0000h
Set to 1 by the
Set to 0 by the
program
program
TCR.TCST
STR.BFDF
Figure 27.66 Example of Operations in Break Field Low Width Output Mode
FFFFh Underflow
Determinable
Contents of the counter (hex.)
Determinable
Determination state after Determination
state after
started reloading started
reloading
n
0000h
Set to 1 by the program
TCR.TCST
STR.BFDF
Figure 27.67 Example of Operations in Break Field Low Width Determination Mode
TXDn/SDAn,
RXDn/SCLn
internal signals
Not match
Match D Q
Com- CLK
parator
TXDn/SSDAn,
RXDn/SSCLn
input signal D Q D Q
Note 1. To temporarily prohibit TXI interrupts at the time of transmission of the last of the data and so on when you wish
a new round of transmission to start after handling of the transmission-completed interrupt, control prohibiting
and permitting of the interrupt by using the interrupt request enable bit in the interrupt controller rather than
using the SCR.TIE bit. This can prevent the suppression of TXI interrupt requests in the transfer of new data.
Data transmission/reception using the DTC or DMAC is also possible in smart card interface mode, similar to in the
normal SCI mode. In transmission, when the TEND flag in SSR is set to 1, a TXI interrupt request is generated. This TXI
interrupt request activates the DTC or DMAC allowing transfer of transmit data if the TXI request is specified
beforehand as a source of DTC or DMAC activation. The TEND flag is automatically cleared to 0 when the DTC or
DMAC transfers the data.
If an error occurs, the SCI automatically re-transmits the same data. During the retransmission, the TEND flag is kept to
0 and the DTC or DMAC is not activated. Therefore, the SCI and DTC or DMAC automatically transmit the specified
number of bytes, including retransmission in the case of error occurrence. However, the ERS flag in SSR is not
automatically cleared to 0 at error occurrence. Therefore, the ERS flag must be cleared by previously setting the RIE bit
in SCR to 1 to enable an ERI interrupt request to be generated at error occurrence.
When transmitting/receiving data using the DTC or DMAC, be sure to make settings to enable the DTC or DMAC
before making SCI settings. For DTC or DMAC settings, see section 16, DMA Controller (DMACA) and section 17,
Data Transfer Controller (DTCa).
In reception, an RXI interrupt request is generated when receive data is set to RDR. This RXI interrupt request activates
the DTC or DMAC allowing transfer of receive data if the RXI request is specified beforehand as a source of DTC or
DMAC activation. If an error occurs, the error flag is set. Therefore, the DTC or DMAC is not activated and an ERI
interrupt request is issued to the CPU instead; the error flag must be cleared.
Note 1. Activation of the DTC or DMAC is only possible when the SIMR2.IICINTM bit is 1 (selecting reception and interrupts).
Table 27.29 Interrupt Sources of the Extended Serial Mode Control Section
Interrupt Request Status Flag Interrupt Factors
SCIX0 interrupt (Break Field low width BFDF Detection of a Break Field low width longer than the interval corresponding
detected) to the timer setting
Completion of the output of a Break Field low width over the interval
corresponding to the timer setting
Underflow of the timer
SCIX1 interrupt (Control Field 0 match) CF0MF The data received in Control Field 0 matching the value set in CF0DR
SCIX1 interrupt (Control Field 1 match) CF1MF The data received in Control Field 1 matching the value set in PCF1DR or
SCF1DR
SCIX1 interrupt (priority interrupt bit PIBDF The value of the bit specified as the priority interrupt bit matching the value set
detected) in PCF1DR
SCIX2 interrupt (bus collision detected) BCDF The output level on the TXDX12 pin and the input level on the RXDX12 pin not
matching on three consecutive cycles of the bus-collision detection clock
SCIX3 interrupt (valid edge detected) AEDF Detection of a valid edge during bit-rate measurement
27.13.4 Receive Error Flags and Transmit Operations (Clock Synchronous Mode Only)
Transmission cannot be started when a receive error flag (ORER) in SSR is set to 1, even if data is written to TDR. Be
sure to clear the receive error flags to 0 before starting transmission. Note also that the receive error flags cannot be
cleared to 0 even if the RE bit in SCR is cleared to 0 (serial reception disabled).
(2) Reception
Before specifying the module stop state or making a transition to software standby mode, stop the receive operations (RE
= 0 in SCR). If transition is made during data reception, the data being received will be invalid.
To receive data in the same reception mode after cancellation of the low power consumption state, set the RE bit to 1, and
then start reception. To receive data in a different reception mode, initialize the SCI first.
Figure 27.72 shows a sample flowchart for transition to software standby mode during reception.
<Data transmission>
No [ 2 ] Set the I/O port function, and switch from the TXDn
SSR.TEND = 1
pin to the general I/O port.
Yes [ 3 ] Clear the TIE and TEIE bits in the SCR if they are
Make the I/O port function settings currently set to 1.
[2]
No
Change operating mode?
Initialization SCR.TE = 1
Figure 27.69 Example of Flowchart for Transition to Software Standby Mode during Transmission
Transition to
software standby Software standby mode
Transmission start Transmission end mode canceled
SCR.TE bit
TXDn output pin Port input/output High output Stop Port input/output High output
Figure 27.70 Port Pin States during Transition to Software Standby Mode
(Internal Clock, Asynchronous Transmission)
Transition to
software standby Software standby
Transmission start Transmission end mode mode canceled
SCR.TE bit
TXDn output pin Port input/output Marking output Last TXD bit retained Port input/output High output*1
Figure 27.71 Port Pin States during Transition to Software Standby Mode
(Internal Clock, Clock Synchronous Transmission)
Data reception
Yes
SCR.RE = 0
Make transition to software standby mode [2] [ 2 ] Setting for the module stop state is included.
No
Change operating mode?
Yes
Initialization SCR.RE = 1
Figure 27.72 Example of Flowchart for Transition to Software Standby Mode during Reception
SCKn pin
(SPMR.CKPOL = 0)
SCKn pin
(SPMR.CKPOL = 1)
RXDn pin Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
RXI source
Figure 27.73 Timing of the RXI Interrupt in Simple SPI Mode (with Clock Delay)
(1) Set the SCR.RIE bit of the SCI (SCIe) to 0 to disable the output of interrupt requests. Check the error flags in the
SSR register for SCIe on completion of the reception of a start frame, because an ERI interrupt is not generated if a
reception error occurs. After reception of the start frame is completed, set the SCR.RIE bit of the SCIe to 1 by the
time the first byte of the information frame is received.
(2) Set the SCR.RIE bit of the SCIe to 1 to disable RXI interrupts and enable ERI interrupts for ICU.
Clear the IRn.IR flag to enable the acceptance of RXI interrupts by ICU by the time the first byte of the information
frame is received after the completion of start frame reception.
Clear the ESMER.ESME bit to 0 Disable extended serial functions. The state
of the control section is initialized.
Set all bits in STCR to 1 Clear all flags in the STR register.
Set the AEDIE, BCDIE, CF1MIE, CF0MIE and Set interrupt enable bits as required.
BFDIE bits in the ICR.
Set the TCR.TCST bit to 1 Start counting by the timer so that judgment of break fields is possible.
Set the CR3.SDST bit to 1. This starts detection of the start frame.
Completion of reception error handling Note 1. The setting in this step is not necessary if the setting conditions
have not been changed.
Figure 27.74 Example of Flowchart for Reception Error Handling (During Reception of the Start Frame)
28.1 Overview
Enabling the IrDA function by using the IRE bit in the IRCR register allows encoding and decoding the TXD5 and
RXD5 signals of the SCI5 to the waveforms conforming to the IrDA standard 1.0 (IRTXD5 and IRRXD5 pins).
Connecting these waveforms to an infrared transmitter/receiver implements infrared data communication conforming to
the IrDA standard 1.0 system.
With the IrDA standard 1.0 system, data transfer can be started at 9600 bps and the transfer rate can be changed
whenever necessary. Since the IrDA interface cannot change the transfer rate automatically, the transfer rate should be
changed through software.
Figure 28.1 is a block diagram showing cooperation between the IrDA and SCI5.
IrDA SCI5
IRE bit = 0
TXD5/IRTXD5 TXD5
Phase inverter Pulse encoder
IRE bit = 1
IRE bit = 1
RXD5/IRRXD5 Phase inverter Pulse decoder RXD5
IRE bit = 0
IRCR
Figure 28.1 Block Diagram Showing Cooperation between IrDA and SCI5
b7 b6 b5 b4 b3 b2 b1 b0
Note 1. The IRCR register values are retained in module stop function mode, sleep mode, all-module clock stop mode, and software
standby mode.
28.3 Operation
(1) Set the corresponding pins to IRTXD5 and IRRXD5 by the pin function select register (Pmn.PFS = 1010b) of the
multi-function pin controller (MPC).
(2) Set the general I/O port to the port mode by the port mode register (PORTm.PMR = 0) of the I/O port.
(3) Specify the IrDA function by the IRCR register.
(4) Set the SCI5-related registers of the serial communications interface.
28.3.2 Transmission
In transmission, the signals output from the SCI5 (UART frames) are converted to the IR frame data through the IrDA
interface (see Figure 28.2). When the IRCR.IRTXINV bit is 0 and serial data is 0, high-level pulses with 3/16 the width
of the bit rate (1-bit width period) are output (initial setting). The high-level pulse width can be changed by setting the
IRCR.IRCKS[2:0] bits. The standard prescribes that the minimum high-level pulse width should be 1.41 μs and the
maximum high-level pulse width be (3/16 + 2.5%) × bit rate or (3/16 × bit rate) + 1.08 μs. When the peripheral module
clock PCLK is 20 MHz, the high-level pulse width can be 1.41 μs to 1.6 μs. When serial data is 1, no pulses are output.
UART frame
Data
Start bit Stop bit
0 1 0 1 0 0 1 1 0 1
Transmission Reception
IR frame
Data
Start bit Stop bit
0 1 0 1 0 0 1 1 0 1
28.3.3 Reception
In reception, the IR frame data is converted to the UART frame data through the IrDA interface and is input to the SCI5.
Low-level data is output when the IRCR.IRRXINV bit is 0 and a high-level pulse is detected; high-level data is output
when no pulse is detected for a 1-bit period. Note that pulses shorter than the minimum pulse width of 1.41 μs are not
recognized.
29.1 Overview
Table 29.1 lists the specifications of the RIIC, Figure 29.1 shows a block diagram of the RIIC, and Figure 29.2 shows
an example of I/O pin connections to external circuits (I2C bus configuration example). Table 29.2 lists the I/O pins of
the RIIC.
PCLK
CKS[2:0]
PS
ICMR1
BC[2:0]
IIC (PCLK/1 to PCLK/128)
Output
SCL Transfer clock ICBRH
control
generator ICBRL
CLO SCLE
Noise SCLI
canceller
SCL, SDA ICCR1
NF[1:0] NFE
IICRST
Transmission/ SDAI
reception control ST, RS, SP
circuit ICCR2
DLCS
PS BBSY, MST, TRS
WAIT, RDRFS
ICFER
IIC, IIC/2
SDDL[2:0]
SDA output delay control ICMR2
SARU0 SARL0
FMPE
TMOF
Timeout circuit
ICIER
Interrupt generator
Interrupt request
(TXI, TEI, RXI, STI, SPI, NAKI, ALI, TMOI)
SCL SCL
SCLin
SCLout#
SDA SDA
SDAin
SDAout#
SDA
SDA
SCL
SCL
(Master) SCLin SCLin
SCLout# SCLout#
SDAin SDAin
SDAout# SDAout#
(Slave 1) (Slave 2)
Figure 29.2 Connections to the External Circuit by the I/O Pins (I2C Bus Configuration Example)
The input level of the signals for RIIC is CMOS when I2C bus is selected (the ICMR3.SMBS bit = 0), or TTL when
SMBus is selected (the ICMR3.SMBS bit = 1).
Note 1. Same address with ones of the slave address registers, SARL0, SARU0. Care should be taken.
b7 b6 b5 b4 b3 b2 b1 b0
SDAO Bit (SDA Output Control/Monitor) and SCLO Bit (SCL Output Control/Monitor)
These bits are used to directly control the SDA and SCL signals output from the RIIC.
When writing to these bits, also write 0 to the SOWP bit.
The result of setting these bits is input to the RIIC via the input buffer. When slave mode is selected, a START condition
may be detected and the bus may be released depending on the bit settings.
Do not rewrite these bits during a START condition, STOP condition, repeated START condition, or during transmission
or reception. Operation after rewriting under the above conditions is not guaranteed.
When reading these bits, the state of signals output from the RIIC can be read.
Note: • If an internal reset is initiated using the IICRST bit for a bus hang-up occurred during communication with the
master device in slave mode, the states may become different between the slave device and the master device
(due to the difference in the bit counter information). For this reason, do not initiate an internal reset in slave
mode, but initiate restoration processing from the master device. If an internal reset is necessary because the
RIIC hangs up with the SCL line in a low level output state in slave mode, initiate an internal reset and then issue
a restart condition from the master device or resume communication from the start condition issuance after
issuing a stop condition. If communication is restarted by initiating a reset solely in the slave device without
issuing a start condition or restart condition from the master device, synchronization will be lost because the
master and slave devices operate asynchronously.
b7 b6 b5 b4 b3 b2 b1 b0
Note 1. When the MTWP bit in ICMR1 is set to 1, the MST and TRS bits can be written to.
Note: • Set the ST bit to 1 (start condition issuance request) when the BBSY flag is set to 0 (bus free).
Note that arbitration may be lost if the ST bit is set to 1 (start condition issuance request) when the BBSY flag is
set to 1 (bus busy).
Note: • Writing to the SP bit is not possible while the setting of the BBSY flag is 0 (bus free).
Note: • Do not set the SP bit to 1 while a restart condition is being issued.
[Setting conditions]
When a start condition is issued normally according to the start condition issuance request (when a start condition is
detected with the ST bit set to 1)
When the R/W# bit added to the slave address is set to 0 in master mode
When the address received in slave mode matches the address enabled in ICSER, with the R/W# bit set to 1
When 1 is written to the TRS bit with the MTWP bit in ICMR1 set to 1
[Clearing conditions]
When a stop condition is detected
The AL (arbitration-lost) flag in ICSR2 being set to 1
In master mode, reception of a slave address to which an R/W# bit with the value 1 is appended
In slave mode, a match between the received address and the address enabled in ICSER when the value of the
received R/W# bit is 0 (including cases where the received address is the general call address)
In slave mode, a restart condition is detected (a start condition is detected with ICCR2.BBSY = 1 and ICCR2.MST
= 0)
When 0 is written to the TRS bit with the MTWP bit in ICMR1 set to 1
When 1 is written to the IICRST bit in ICCR1 to apply an RIIC reset or an internal reset
b7 b6 b5 b4 b3 b2 b1 b0
Note 1. Set the BCWP bit to 0 to rewrite the BC[2:0] bits. The BC[2:0] bits must be rewritten by using the MOV instruction.
b7 b6 b5 b4 b3 b2 b1 b0
Note 1. The setting DLCS = 1 (IIC/2) only becomes valid when SCL is at the low level. When SCL is at the high level, the setting DLCS
= 1 becomes invalid and the clock source becomes the internal reference clock (IIC).
Note: • Set the SDA output delay time to meet the I2C bus standard (within the data enable time/acknowledge enable
time*1) or the SMBus standard (within the data hold time: 300 ns or more, and SCL-clock low-level period - the
data setup time: 250 ns). Note that, if a value outside the standard is set, communication with communication
devices may malfunction or it may seemingly become a start condition or stop condition depending on the bus
state.
Note 1. Data enable time/acknowledge enable time
3,450 ns (up to 100 kbps: standard mode [Sm])
900 ns (up to 400 kbps: fast mode [Fm])
b7 b6 b5 b4 b3 b2 b1 b0
Note 1. If it is attempted to write 1 to both ACKWP and ACKBT bits, the ACKBT bit cannot be set to 1.
Note 2. The WAIT and RDRFS bits are valid only in receive mode (invalid in transmit mode).
ICMR3 has functions to send/receive acknowledge, to select the RDRF set timing in RIIC receive operation, and to
control WAIT operation.
Note: • Set the noise range to be filtered out by the noise filter within a range less than the SCL line high-level period or
low-level period. If the noise range is set to a value of (SCL clock width: high-level period or low-level period,
whichever is shorter) - [1.5 internal reference clock (IIC) cycles + analog noise filter: 120 ns (reference values)]
or more, the SCL clock is regarded as noise by the noise filter function of the RIIC, which may prevent the RIIC
from operating normally.
Note: • The ACKBT bit must be written to while the ACKWP bit is 1. If the ACKBT bit is written to with the ACKWP bit
cleared to 0, writing to the ACKBT bit is disabled.
Note: • When the value of the WAIT bit is to be read, be sure to read the ICDRR beforehand.
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
AL Flag (Arbitration-Lost)
This flag shows that bus mastership has been lost (loss in arbitration) due to a bus conflict or some other reason when a
start condition is issued or an address and data are transmitted. The RIIC monitors the level on the SDA line during
transmission and, if the level on the line does not match the value of the bit being output, sets the value of the AL bit to 1
to indicate that the bus is occupied by another device.
The RIIC can also set the flag to indicate the detection of loss of arbitration during NACK transmission in master mode
or during data transmission in slave mode.
[Setting conditions]
When master arbitration-lost detection is enabled: ICFER.MALE = 1
When the internal SDA output state does not match the SDA line level at the rising edge of SCL clock except for the
ACK period during data (including slave address) transmission in master transmit mode (when the SDA line is
driven low while the internal SDA output is at a high level (the SDA pin is in the high-impedance state))
When a start condition is detected while the ST bit in ICCR2 is 1 (start condition issuance request) or the internal
SDA output state does not match the SDA line level
When the ST bit in ICCR2 is set to 1 (start condition issuance request) with the BBSY flag in ICCR2 set to 1.
When NACK arbitration-lost detection is enabled: ICFER.NALE = 1
When the internal SDA output state does not match the SDA line level at the rising edge of SCL clock in the ACK
period during NACK transmission in receive mode
When slave arbitration-lost detection is enabled: ICFER.SALE = 1
When the internal SDA output state does not match the SDA line level at the rising edge of SCL clock except for the
ACK period during data transmission in slave transmit mode
[Clearing conditions]
When 0 is written to the AL bit after reading AL = 1
When 1 is written to the IICRST bit in ICCR1 to apply an RIIC reset or an internal reset
Table 29.5 Relationship between Arbitration-Lost Generation Sources and Arbitration-Lost Enable Functions
ICFER ICSR2
MALE NALE SALE AL Error Arbitration-Lost Generation Source
1 × × 1 Start condition When internal SDA output state does not match SDA line level when a
issuance error start condition is detected while the ST bit in ICCR2 is 1
When ST in ICCR2 is set to 1 with BBSY in ICCR2 set to 1
1 Transmit data When transmit data (including slave address) does not match the bus
mismatch state in master transmit mode
× 1 × 1 NACK When ACK is detected during transmission of NACK in master receive
transmission mode or slave receive mode
mismatch
× × 1 1 Transmit data When transmit data does not match the bus state in slave transmit mode
mismatch
×: Don’t care
Note: • When the NACKF flag is set to 1, the RIIC suspends data transmission/reception. Writing to ICDRT in transmit
mode or reading from ICDRR in receive mode with the NACKF flag set to 1 does not enable data transmit/receive
operation. To restart data transmission/reception, clear the NACKF flag to 0.
Note: • When the NACKF flag is set to 1 while the NACKE bit in ICFER is 1, the RIIC suspends data transmission/
reception. Here, if the TDRE flag is 0 (next transmit data has been written), data is transferred to the ICDRS
register and the ICDRT register becomes empty at the rising edge of the ninth clock cycle, but the TDRE flag is
not set to 1.
Address(es): RIIC0.SARL0 0008 830Ah RIIC0.SARL1 0008 830Ch RIIC0.SARL2 0008 830Eh
b7 b6 b5 b4 b3 b2 b1 b0
SVA[6:0] SVA0
Address(es): RIIC0.SARU0 0008 830Bh RIIC0.SARU1 0008 830Dh RIIC0.SARU2 0008 830Fh
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — SVA[1:0] FS
b7 b6 b5 b4 b3 b2 b1 b0
— — — BRL[4:0]
b7 b6 b5 b4 b3 b2 b1 b0
— — — BRH[4:0]
ICBRH is a 5-bit register to set the high-level period of SCL clock. ICBRH is valid in master mode. If the RIIC is used
only in slave mode, this register need not to set the high-level period.
ICBRH counts the high-level period with the internal reference clock source (IIC) specified by the CKS[2:0] bits in
ICMR1.
If the digital noise filter is enabled (the NFE bit in ICFER is 1), set the ICBRH register to a value at least one greater than
the number of stages in the noise filter. Regarding the number of stages in the noise filter, see the description of the
ICMR3.NF[1:0] bits.
The I2C transfer rate and the SCL clock duty are calculated using the following expression.
Transfer rate = 1 / {[(ICBRH + 1) + (ICBRL + 1)] / IIC*1 + SCL line rising time [tr] + SCL line falling time [tf]}
Duty cycle = {SCL line rising time [tr]*2 + (ICBRH + 1) / IIC} / {SCL line falling time [tf]*2 + (ICBRL + 1) / IIC}
Note: • ICBRH/ICBRL settings in these tables are calculated using the following values:
SCL line rising time (tr): 100 kbps or less, [Sm]: 1000 ns, 400 kbps or less, [Fm]: 300 ns
SCL line falling time (tf): 400 kbps or less, [Sm/Fm]: 300 ns
For the specified values of SCL line rising time (tr) and SCL line falling time (tf), see the I2C bus standard from NXP
Semiconductors.
b7 b6 b5 b4 b3 b2 b1 b0
When ICDRT detects a space in the I2C bus shift register (ICDRS), it transfers the transmit data that has been written to
ICDRT to ICDRS and starts transmitting data in transmit mode.
The double-buffer structure of ICDRT and ICDRS allows continuous transmit operation if the next transmit data has
been written to ICDRT while the ICDRS data is being transmitted.
ICDRT can always be read and written. Write transmit data to ICDRT once when a transmit data empty interrupt (TXI)
request is generated.
b7 b6 b5 b4 b3 b2 b1 b0
When 1 byte of data has been received, the received data is transferred from the I2C bus shift register (ICDRS) to ICDRR
to enable the next data to be received.
The double-buffer structure of ICDRS and ICDRR allows continuous receive operation if the received data has been read
from ICDRR while ICDRS is receiving data.
ICDRR cannot be written. Read data from ICDRR once when a receive data full interrupt (RXI) request is generated.
If ICDRR receives the next receive data before the current data is read from ICDRR (while the RDRF flag in ICSR2 is
1), the RIIC automatically holds the SCL clock low one cycle before the RDRF flag is set to 1 next.
b7 b6 b5 b4 b3 b2 b1 b0
TMOCNTU TMOCNTL
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
TMOCNTU TMOCNTL
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
— — — —
Note: • Same address with ones of the slave address registers, SARL0,SARU0. Care should be taken.
TMOCNTL register
Bit Symbol Bit Name Description R/W
b7 to b0 TMOCNTL Timeout internal counter Timeout internal counter low-order W*1
Note 1. Value in timeout internal counter cannot be read. When value is read, the read value is FFh.
TMOCNTU register
Bit Symbol Bit Name Description R/W
b7 to b0 TMOCNTU Timeout internal counter Timeout internal counter high-order*1 W*2
Note 1. When TMOS = 1 (short mode), bits b7 to b4 are reserved bits. They are writable. However, the value written is disabled.
Note 2. Value in timeout internal counter cannot be read. When value is read, the read value is FFh.
The timeout internal counter (TMOCNTL/TMOCNTU) is initialized (TMOCNTL = 00h, TMOCNTU = 00h) after a
reset, while ICCR1.IICRST = 1 or ICFER.TMOE = 1 and PCLK/1 is selected with ICMR1.CKS[2:0] = 000b setting, and
when the counter clear conditions specified by the ICMR2.TMOH/TMOL bit (SCL rising edge/falling edge detection)
are met.
The TMOCNTL and TMOCNTU counters can be accessed as 16-bit registers in 16-bit units.
29.3 Operation
1 7 1 1 8 1 1 1
n (n = 1 or more)
1 7 1 1 8 1 8 1 1 1
n (n = 1 or more)
1 7 1 1 8 1 1 7 1 1 8 1 1 1
n (n = 1 or more)
SDA
SCL 1 to 7 8 9 1 to 7 8 9 1 to 7 8 9
S: Start condition. The master device drives the SDA line low from high level while the SCL line is at a high level.
SLA: Slave address, by which the master device selects a slave device.
R/W#: Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to
the slave device when R/W is 0.
A: Acknowledge. The receive device drives the SDA line low. (In master transmit mode, the slave device returns acknowledge. In
master receive mode, the master device returns acknowledge.)
Sr: Restart condition. The master device drives the SDA line low from the high level after the setup time has elapsed with the SCL
line at the high level.
DATA: Transmitted or received data
P: Stop condition. The master device drives the SDA line high from low level while the SCL line is at a high level.
Initial settings
TMOCNTL = 00h
*2, *4 The timeout internal counter is initialized *3
TMOCNTU = 00h
ICFER.TMOE = 1 *2
End
[Legend] n = 0 to 2
Note 1. When the RIIC is used only in slave mode, set the ICBRL register to a value longer than the
data setup time.
Note 2. Set these registers as necessary.
Note 3. Those procedures need to be added only when using timeout function. Not needed when
not using timeout function.
Note 4. The diagram above is for 8-bit access. For 16-bit access, set 0000h to the address listed in
Table 29.3, Register Allocation for 16-Bit Access.
(1) Set the ICCR1.ICE bit to 1 (internal reset) after setting the ICCR1.IICRST bit to 1 (RIIC reset) with the ICCR1.ICE
bit cleared to 0 (SCL and SDA pins in inactive state). This initializes the various flags and internal state of ICSR1.
After that, set registers SARLy, SARUy, ICSER, ICMR1, ICBRH, and ICBRL (y = 0 to 2), and set the other
registers as necessary (for initial settings of the RIIC, see Figure 29.5). When the necessary register settings have
been completed, clear the ICCR1.IICRST bit to 0 (to release the reset state). This step is not necessary if
initialization of the RIIC has already been completed.
(2) Read the BBSY flag in ICCR2 to check that the bus is open, and then set the ST bit in ICCR2 to 1 (start condition
issuance request). Upon receiving the request, the RIIC issues a start condition. At the same time, the BBSY flag
and the START flag in ICSR2 are automatically set to 1 and the ST bit is automatically cleared to 0. At this time, if
the start condition is detected and the internal levels for the SDA output state and the levels on the SDA line have
matched while the ST bit is 1, the RIIC recognizes that issuing of the start condition as requested by the ST bit has
been successfully completed, and the MST and TRS bits in ICCR2 are automatically set to 1, placing the RIIC in
master transmit mode. The TDRE flag in ICSR2 is also automatically set to 1 in response to setting of the TRS bit to
1.
(3) Check that the TDRE flag in ICSR2 is 1, and then write the value for transmission (the slave address and the R/W#
bit) to ICDRT. Once the data for transmission are written to ICDRT, the TDRE flag is automatically cleared to 0, the
data are transferred from ICDRT to ICDRS, and the TDRE flag is again set to 1. After the byte containing the slave
address and R/W# bit has been transmitted, the value of the TRS bit is automatically updated to select master
transmit or master receive mode in accord with the value of the transmitted R/W# bit. If the value of the R/W# bit
was 0, the RIIC continues in master transmit mode.
Since the ICSR2.NACKF flag being 1 at this time indicates that no slave device recognized the address or there was
an error in communications, write 1 to the ICCR2.SP bit to issue a stop condition.
For data transmission with an address in the 10-bit format, start by writing 1111 0b, the two higher-order bits of the
slave address, and W to ICDRT as the first address transmission. Then, as the second address transmission, write the
eight lower-order bits of the slave address to ICDRT.
(4) After confirming that the TDRE flag in ICSR2 is 1, write the data for transmission to the ICDRT register. The RIIC
automatically holds the SCL line low until the data for transmission are ready or a stop condition is issued.
(5) After all bytes of data for transmission have been written to the ICDRT register, wait until the value of the TEND
flag in ICSR2 returns to 1, and then set the SP bit in ICCR2 to 1 (stop condition issuance request). Upon receiving a
stop condition issuance request, the RIIC issues the stop condition.
(6) Upon detecting the stop condition, the RIIC automatically clears the MST and TRS bits in ICCR2 to 00b and enters
slave receive mode. Furthermore, it automatically clears the TDRE and TEND flags to 0, and sets the STOP flag in
ICSR2 to 1.
(7) After checking that the ICSR2.STOP flag is 1, clear the ICSR2.NACKF and STOP flags to 0 for the next transfer
operation.
Master transmission
No
ICCR2.BBSY = 0?
[2] Check I2C bus occupation and issue
Yes a start condition.
ICCR2.ST = 1
ICSR2.NACKF = 0?
No
Yes
No
ICSR2.TDRE = 1?
Yes
No
All data transmitted?
Yes
No
ICSR2.TEND = 1?
Yes
ICSR2.STOP = 0
ICCR2.SP = 1
No
ICSR2.STOP = 1? [6] Check stop condition issuance
Yes
TMOCNTL = 00h
*1, *2
TMOCNTU = 00h
ICSR2.STOP = 0
Note 1. Those procedures need to be added only when using timeout function. Not needed when
not using timeout function.
Note 2. The diagram above is for 8-bit access. For 16-bit access, set 0000h to the address listed in
Table 29.3, Register Allocation for 16-Bit Access.
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4
SCL
TEND
RDRF
ACKBT 0 (ACK)
START
ST
Figure 29.7 Master Transmit Operation Timing (1) (7-Bit Address Format)
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4
SCL
TEND
RDRF
ACKBT 0 (ACK)
START
ST
Write 1 Write
data to Write data to
ICDRT Write data to Write data to
to ST (11110b + 2 ICDRT ICDRT ICDRT
(lower 8 bits)
bits + W) (DATA 1) (DATA 2)
[2] [3] [4] [4]
Figure 29.8 Master Transmit Operation Timing (2) (10-Bit Address Format)
7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
SCL
BBSY
MST
TEND
RDRF
ACKBT 0 (ACK)
STOP
SP
(1) Set the ICCR1.ICE bit to 1 (internal reset) after setting the ICCR1.IICRST bit to 1 (RIIC reset) with the ICCR1.ICE
bit cleared to 0 (SCL and SDA pins in inactive state). This initializes the various flags and internal state of ICSR1.
After that, set registers SARLy, SARUy, ICSER, ICMR1, ICBRH, and ICBRL (y = 0 to 2), and set the other
registers as necessary (for initial settings of the RIIC, see Figure 29.5). When the necessary register settings have
been completed, clear the ICCR1.IICRST bit to 0 (to release the reset state). This step is not necessary if
initialization of the RIIC has already been completed.
(2) Read the BBSY flag in ICCR2 to check that the bus is open, and then set the ST bit in ICCR2 to 1 (start condition
issuance request). Upon receiving the request, the RIIC issues a start condition. When the RIIC detects the start
condition, the BBSY flag and the START flag in ICSR2 are automatically set to 1 and the ST bit is automatically
cleared to 0. At this time, if the start condition is detected and the levels for the SDA output and the levels on the
SDA line have matched while the ST bit is 1, the RIIC recognizes that issuing of the start condition as requested by
the ST bit has been successfully completed, and the MST and TRS bits in ICCR2 are automatically set to 1, placing
the RIIC in master transmit mode. The TDRE flag in ICSR2 is also automatically set to 1 in response to setting of
the TRS bit to 1.
(3) Check that the TDRE flag in ICSR2 is 1, and then write the value for transmission (the first byte indicates the slave
address and value of the R/W# bit) to ICDRT. Once the data for transmission are written to ICDRT, the TDRE flag
is automatically cleared to 0, the data are transferred from ICDRT to ICDRS, and the TDRE flag is again set to 1.
Once the byte containing the slave address and R/W# bit has been transmitted, the value of the ICCR2.TRS bit is
automatically updated to select transmit or receive mode in accord with the value of the transmitted R/W# bit. If the
value of the R/W# bit was 1, the TRS bit is cleared to 0 on the rising edge of the ninth cycle of SCL (the clock
signal), placing the RIIC in master receive mode. At this time, the TDRE flag is automatically cleared to 0 and the
ICSR2.RDRF flag is automatically set to 1.
Since the ICSR2.NACKF flag being 1 at this time indicates that no slave device recognized the address or there was
an error in communications, write 1 to the ICCR2.SP bit to issue a stop condition.
For master reception from a device with a 10-bit address, start by using master transmission to issue the 10-bit
address, and then issue a restart condition. After that, transmitting 1111 0b, the two higher-order bits of the slave
address, and the R bit places the RIIC in master receive mode.
(4) Dummy read ICDRR after confirming that the RDRF flag in ICSR2 is 1; this makes the RIIC start output of the
SCL (clock) signal and start data reception.
(5) After 1 byte of data has been received, the RDRF flag in ICSR2 is set to 1 on the rising edge of the eighth or ninth
cycle of SCL clock (the clock signal) as selected by the RDRFS bit in ICMR3. Reading out ICDRR at this time will
produce the received data, and the RDRF flag is automatically cleared to 0 at the same time. Furthermore, the value
of the acknowledgement field received during the ninth cycle of SCL clock is returned as the value set in the
ACKBT bit of ICMR3. Furthermore, if the next byte to be received is the next to last byte, set the ICMR3.WAIT bit
to 1 (for wait insertion) before reading the ICDRR (containing the second byte from last). As well as enabling
NACK output even in the case of delays in processing to set the ICMR3.ACKBT bit to 1 (NACK) in step (6), due to
other interrupts, etc., this fixes the SCL line to the low level on the rising edge of the ninth clock cycle in reception
of the last byte, so the state is such that issuing a stop condition is possible.
(6) When the ICMR3.RDRFS bit is 0 and the slave device must be notified that it is to end transfer for data reception
after transfer of the next (final) byte, set the ACKBT bit in ICMR3 to 1 (NACK).
(7) After reading out the byte before last from the ICDRR register, if the value of the ICSR2.RDRF flag is confirmed to
be 1, write 1 to the SP bit in ICCR2 (stop condition issuance request) and then read the last byte from ICDRR. When
ICDRR is read, the RIIC is released from the wait state and issues the stop condition after low-level output in the
ninth clock cycle is completed or the SCL line is released from the low-hold state.
(8) Upon detecting the stop condition, the RIIC automatically clears the MST and TRS bits in ICCR2 to 00b and enters
slave receive mode. Furthermore, detection of the stop condition leads to setting of the STOP flag in ICSR2 to 1.
(9) After checking that the ICSR2.STOP flag is 1, clear the ICSR2.NACKF and STOP flags to 0 for the next transfer
operation.
No
ICCR2.BBSY = 0? (2) Check I2C bus occupation and issue
Yes a start condition.
ICCR2.ST = 1
No
ICSR2.TDRE = 1?
Yes
TMOCNTL = 00h *1, *2
TMOCNTU = 00h
Write the ICDRT register
(3) Transmit the slave address followed by
No R and check ACK.
ICSR2.RDRF = 1?
Yes
TMOCNTL = 00h *1, *2
TMOCNTU = 00h
No
ICSR2.NACKF = 0?
Yes
ICMR3.WAIT = 1 (4) Set to WAIT
Yes
Next data = last byte?
No
Dummy read the ICDRR register
TMOCNTU = 00h
ICMR3.RDRFS = 1 *3
ICMR3.ACKBT = 1
(6) Read received data
Read the ICDRR register When receiving 1 byte, perform
dummy read.
No
ICSR2.RDRF = 1?
Yes
TMOCNTL = 00h *1, *2
TMOCNTU = 00h
ICMR3.RDRFS = 0 *3
(9) Processing for the next transfer operation
ICMR3.ACKBT = 0
ICSR2.NACKF = 0
ICSR2.STOP = 0
Master reception ends
Note 1. These settings are required only when timeout detection is enabled.
Note 2. Word access can be also performed as a 16-bit register.
Note 3. These bits can be set at the same time.
Master reception
No
ICCR2.BBSY = 0?
Yes [2] Check I2C bus occupation and issue a start condition.
ICCR2.ST = 1
No
ICSR2.TDRE = 1?
Yes
TMOCNTL = 00h
*1, *2
TMOCNTU = 00h
TMOCNTL = 00h
*1, *2
TMOCNTU = 00h
Yes
ICSR2.NACKF = 0?
No
Yes
Perform dummy read of ICDRR [4] Perform dummy read.
No
ICSR2.RDRF = 1?
TMOCNTL = 00h
*1, *2
TMOCNTU = 00h
Yes [5] Read received data and prepare for receiving final
data.
Yes
Next data = Final byte - 1?
No
Yes
Next data = Final byte - 2?
ICMR3.WAIT = 1
No
Read ICDRR
ICMR3.RDRFS = 1
*2
[6] Change RDRF set timing and set the
ICMR3.ACKBT = 1 acknowledgement and read data of (final byte – 1
byte).
Read ICDRR
No
ICSR2.RDRF = 1?
Yes
TMOCNTL = 00h
*1, *2
TMOCNTU = 00h
ICSR2.STOP = 0 ICSR2.STOP = 0
[7] Read final data and SCL release by writing ACKBT
and issue a stop condition
ICCR2.SP = 1 ICCR2.SP = 1
ICMR3.ACKBT = 1
ICMR3.WAIT = 0
Yes
TMOCNTL = 00h
*1, *2
TMOCNTU = 00h
ICMR3.RDRFS = 0
*2
ICSR2.NACKF = 0
ICSR2.STOP = 0
Note 1. These settings are required only when timeout detection is enabled.
Note 2. Word access can be also performed as a 16-bit register.
Note 3. These bits can be set at the same time.
Figure 29.11 Example of Master Reception (7-Bit Address Format, 3 Bytes or More)
SCL
MST
TDRE
Receive data (7-bit address + R) Receive data (DATA 1)
TEND
RDRF
ICDRR XXXX (Initial value/last data for reception) XXXX (Initial value/last data for reception) DATA 1
ACKBT 0 (ACK)
START
ST
Figure 29.12 Master Receive Operation Timing (1) (7-Bit Address Format, when RDRFS = 0)
Automatic low hold (to prevent wrong transmission) Master transmit mode Master receive mode
S 1 to 7 8 9 1 to 8 9 Sr 1 2 3 4 5 6 7 8 9 1 2 3 4
SCL
MST
TRS Transmit data (upper 10 bits + W)Transmit data (lower 10 bits) Transmit data (upper 10 bits + R)
TDRE
Transmit data (upper 10 bits + R)
TEND
RDRF
ICDRR XXXX (Initial value/last data for reception) XXXX (Initial value/last data for reception )
ACKBT 0 (ACK)
START
ST
RS
Figure 29.13 Master Receive Operation Timing (2) (10-Bit Address Format, when RDRFS = 0)
BBSY
MST
TRS
TDRE
TEND Receive data (DATA n-2) Receive data (DATA n-1) Receive data (DATA n)
RDRF
STOP
SP
WAIT
Read ICDRR
Write 1 Read ICDRR Write 1 Read ICDRR Write 1 Clear Clear
(last data for reception
to WAIT (DATA n-2) to ACKBT (DATA n-1) to SP WAIT to 0 STOP to 0
[DATA n])
[5] [6] [7] [9]
(1) Follow the procedure in Figure 29.5 to make initial settings for the RIIC. This step is not necessary if initialization
of the RIIC has already been completed. After initial settings, the RIIC will stay in the standby state until it receives
a slave address that it matches.
(2) After receiving a matching slave address, the RIIC sets one of the corresponding bits ICSR1.HOA, GCA, and AASy
(y = 0 to 2) to 1 on the rising edge of the ninth cycle of SCL clock (the clock signal) and outputs the value set in the
ICMR3.ACKBT bit to the acknowledge bit on the ninth cycle of SCL clock. If the value of the R/W# bit that was
also received at this time is 1, the RIIC automatically places itself in slave transmit mode by setting both the TRS bit
and the TDRE flag in ICSR2 to 1.
(3) After the ICSR2.TEND flag is confirmed to be 1, write the data for transmission to the ICDRT register. At this time,
if the RIIC receives no acknowledge from the master device (receives an NACK signal) while the ICFER.NACKE
bit is 1, the RIIC suspends transfer of the next data.
(4) Wait unit the ICSR2.TEND flag is set to 1 while the ICSR2.TDRE flag is 1, after the ICSR2.NACKF flag is set to 1
or the last byte for transmission is written to the ICDRT register. When the ICSR2.NACKF flag or the TEND flag is
1, the RIIC drives the SCL line low on the ninth falling edge of SCL clock.
(5) When the ICSR2.NACKF flag or the ICSR2.TEND flag is 1, dummy read ICDRR to complete the processing. This
releases the SCL line.
(6) Upon detecting the stop condition, the RIIC automatically clears bits ICSR1.HOA, GCA, and AASy (y = 0 to 2),
flags ICSR2.TDRE and TEND, and the ICCR2.TRS bit to 0, and enters slave receive mode.
(7) After checking that the ICSR2.STOP flag is 1, clear the ICSR2.NACKF and STOP flags to 0 for the next transfer
operation.
Slave transmission
No
ICSR2.NACKF=0?
Yes
No
ICSR2.TDRE=1?
Yes
TMOCNTL = 00h
*1, *2
No
All data transmitted?
Yes
No
ICSR2.TEND=1?
Yes
TMOCNTL = 00h
*1, *2
TMOCNTU = 00h
No
ICSR2.STOP=1? [5] Check stop condition detection
Yes
TMOCNTL = 00h
*1, *2
TMOCNTU = 00h
ICSR2.STOP = 0
Note 1. Those procedures need to be added only when using timeout function.
Not needed when not using timeout function.
Note 2. The diagram above is for 8-bit access. For 16-bit access, set 0000h to
the address listed in Table 29.3, Register Allocation for 16-Bit Access.
Slave receive mode Slave transmit mode Automatic low hold (to prevent wrong transmission)
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4
SCL
TEND
RDRF
AASy
ICDRT XXXX (Initial value/last data for transmission) DATA 1 DATA 2 DATA 3
ICDRS 7-bit address + R DATA 1 DATA 2
ICDRR XXXX (Initial value/last data for reception)
ACKBT 0 (ACK)
START
NACKF
Figure 29.16 Slave Transmit Operation Timing (1) (7-Bit Address Format)
7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
SCL
ACKBT 0 (ACK)
STOP
NACKF
(1) Follow the procedure in Figure 29.5 to make initial settings for the RIIC. This step is not necessary if initialization
of the RIIC has already been completed. After initial settings, the RIIC will stay in the standby state until it receives
a slave address that it matches.
(2) After receiving a matching slave address, the RIIC sets one of the corresponding bits ICSR1.HOA, GCA, and AASy
(y = 0 to 2) to 1 on the rising edge of the ninth cycle of SCL clock (the clock signal) and outputs the value set in the
ICMR3.ACKBT bit to the acknowledge bit on the ninth cycle of SCL clock. If the value of the R/W# bit that was
also received at this time is 0, the RIIC continues to place itself in slave receive mode and sets the RDRF flag in
ICSR2 to 1.
(3) After the ICSR2.STOP flag is confirmed to be 0 and the ICSR2.RDRF flag to be 1, dummy read ICDRR (the
dummy value consists of the slave address and R/W# bit when the 7-bit address format is selected, or the lower
eight bits when the 10-bit address format is selected).
(4) When ICDRR is read, the RIIC automatically clears the ICSR2.RDRF flag to 0. If reading of ICDRR is delayed and
a next byte is received while the RDRF flag is still set to 1, the RIIC holds the SCL line low from one SCL cycle
before the timing with which RDRF should be set. In this case, reading ICDRR releases the SCL line from being
held at the low level.
When the ICSR2.STOP flag is 1 and the ICSR2.RDRF flag is also 1, read ICDRR until all the data is completely
received.
(5) Upon detecting the stop condition, the RIIC automatically clears bits ICSR1.HOA, GCA, and AASy (y = 0 to 2) to
0.
(6) After checking that the ICSR2.STOP flag is 1, clear the ICSR2.STOP flag to 0 for the next transfer operation.
Slave reception
No
ICSR2.STOP = 0?
Yes
No No
ICSR2.RDRF = 1? ICSR2.RDRF = 1?
No
All data received?
TMOCNTL = 00h
*1, *2
TMOCNTU = 00h
Note 1. Those procedures need to be added only when using timeout function.
ICSR2.STOP=0
Not needed when not using timeout function.
Note 2. The diagram above is for 8-bit access. For 16-bit access, set 0000h to
End of slave reception the address listed in Table 29.3, Register Allocation for 16-Bit Access.
SCL
MST
TRS
TDRE
Receive data (7-bit address + W) Receive data (DATA 1)
TEND
RDRF
AASy
ICDRR XXXX (Initial value/last data for reception) 7-bit address + W DATA 1
ACKBT 0 (ACK)
START
NACKF
[3] [3][4]
Figure 29.19 Slave Receive Operation Timing (1) (7-Bit Address Format, when RDRFS = 0)
7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
SCL
MST
TRS
TDRE
Receive data (DATA n-2) Receive data (DATA n-1) Receive data (DATA n)
TEND
RDRF
AASy
ACKBT 0 (ACK)
STOP
NACKF
SCL
ICBRL ICBRL
[SCL synchronization]
Counter clear Counter clear
SCL
ICBRH: I2C bus bit rate high-level register (SCL clock high-level period counter)
ICBRL: I2C bus bit rate low-level register (SCL clock low-level period counter)
Figure 29.21 Generation and Synchronization of the SCL Signal from the RIIC
Analog noise filter delay time + PCLK sampling error (1 PCLK (max))
Digital noise filter delay time (NFE, NF[1:0] settings = 0.5 PCLK (min), 1 IIC to 4 IIC (max))
Transmit mode
SDA output delay time (DLCS,SDDL[2:0] settings = 0 (min) to 14 IIC (max))
SDA output release timing
S 8 9
SCL
SDA b7 to b1 b0 ACK/NACK
Receive mode
SDA output release timing
1 to 7 8 9 P
SCL
SDA b7 to b1 b0 ACK/NACK
Master mode
SCL ST 1 2 to 8 9 RS 1 to 9 SP
SDA b7 b6 to b0 ACK/NACK
*1 *1 *1
BBSY
ST
Mismatch
SCL/SDA
Match D Q
internal signal
CLK
Com-
parator
PCLK
SCL/SDA
D Q D Q D Q D Q D Q
input signal
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5
SCL
SDA 7-bit slave address W ACK Data (DATA 1) ACK Data (DATA 2)
BBSY
Address match
AASy
Receive data (7-bit address) Receive data (DATA 1)
TRS
TDRE
RDRF
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5
SCL
SDA 7-bit slave address R ACK Data (DATA 1) ACK Data (DATA 2)
BBSY
Address match
AASy Transmit data (DATA 1) Transmit data (DATA 2)
TRS
TDRE
RDRF
Figure 29.24 AASy Flag Set Timing with 7-Bit Address Format Selected
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5
SCL
SDA 1 1 1 1 0 Upper 2 bits W ACK 10-bit slave address (lower 8 bits) ACK Data
BBSY
Address match
AASy
Receive data (lower addresses)
TRS
TDRE
RDRF
Read ICDRR
(Dummy read [lower addresses])
S 1 2 3 4 5 6 7 8 9 1 to 8 9 Sr 1 2 3 4 5 6 7 8 9
SCL
SDA 1 1 1 1 0 Upper 2 bits W ACK Lower 8 bits ACK R 1 1 1 1 0 Upper 2 bits R ACK
BBSY
Address match
AASy
Receive data (lower addresses)
TRS
TDRE
RDRF
Read ICDRR
(Dummy read [lower addresses])
Figure 29.25 AASy Flag Set Timing with 10-Bit Address Format Selected
[In the case of SAR0L: 7-bit address, SAR1L: 7-bit address, SAR2: 10-bit address (1)]
S 1 2 3 4 5 6 7 8 9 1 to 8 9 Sr 1 2 3 4 5 6 7 8 9
SCL
SDA 7-bit slave address (SAR0L) R/W ACK DATA ACK 7-bit slave address (SAR1L) R/W ACK
BBSY
Address mismatch
AAS0 Address match
Address match
AAS1
AAS2
[In the case of SAR0L: 7-bit address, SAR1L: 7-bit address, SAR2: 10-bit address (2)]
S 1 2 3 4 5 6 7 8 9 1 to 8 9 Sr 1 2 3 4 5 6 7 8 9
SCL
SDA 7-bit slave address (SAR1L) R/W ACK DATA ACK 1 1 1 1 0 Upper 2 bits W ACK
BBSY
AAS0
AAS1 Address match Address mismatch
AAS2
[In the case of SAR0L: 7-bit address, SAR1L: 7-bit address, SAR2: 10-bit address (3)]
S 1 2 3 4 5 6 7 8 9 1 to 8 9 Sr 1 2 3 4 5 6 7 8 9
SCL
SDA 1 1 1 1 0 Upper 2 bits W ACK Lower 8 bits ACK 7-bit slave address (SAR0L) R/W ACK
BBSY
Address match
AAS0
AAS1
Figure 29.26 AASy Flag Set/Clear Timing with 7-Bit/10-Bit Address Formats Mixed
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5
SCL
BBSY
AAS0
Receive data (7-bit address) Receive data (DATA 1)
AAS1
AAS2
Figure 29.27 Timing of GCA Flag Setting during Reception of General Call Address
[Device-ID reception]
S 1 2 3 4 5 6 7 8 9 1 to 8 9 Sr 1 2 3 4 5 6 7 8 9
SCL
BBSY
Slave address match
AASy
TDRE
RDRF
Read ICDRR
(Dummy read [7-bit address/lower 10 bits])
[When address received after a restart condition is detected does not match the Device-ID]
S 1 2 3 4 5 6 7 8 9 1 to 8 9 Sr 1 2 3 4 5 6 7 8 9
SCL
SDA 1 1 1 1 1 0 0 W ACK Address ACK 7-bit slave address (other station) R/W ACK
BBSY
Receive data (7-bit address/lower 10 bits) Slave address match Slave address mismatch
AASy
Device-ID mismatch
Device-ID match (1111 100b + W)
DID
RDRF
Read ICDRR
(Dummy read [7-bit address/lower 10 bits])
[When address before the Device-ID + R does not match the slave address]
S 1 2 3 4 5 6 7 8 9 1 to 8 9 Sr 1 2 3 4 5 6 7 8 9
SCL
AASy
Device-ID match (1111 100b + R) Device-ID match (1111 100b + R)
DID
The previous value is retained.
TDRE
RDRF
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5
SCL
BBSY
AAS0
Receive data (7-bit address) Receive data (DATA 1)
AAS1
AAS2
Figure 29.29 HOA Flag Set Timing during Reception of Host Address
BBSY
Transmit data (7-bit address + W) Transmit data (DATA 1) Transmit data (DATA 2)
AASy
TRS
TDRE
RDRF
Automatic low-hold
[Slave transmit mode] Automatic low-hold (to prevent wrong transmission) (to prevent wrong
transmission)
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3
SCL
TDRE
RDRF
S 1 2 3 4 5 6 7 8 9 P S 1 2 3 4 5 6 7 8 9
SCL
TRS
TDRE
NACKF
Write data to ICDRT Write data to ICDRT Write 1 to SP Clear NACKF Write data to ICDRT Write data to ICDRT
(7-bit address + W) (DATA 1) (7-bit address + W) (DATA 1)
[Slave transmit mode] Automatic low-hold (to prevent wrong transmission) Bus free time
(ICBRL)
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
SCL
TDRE
NACKF
(1) One-Byte Receive Operation and Automatic Low-Hold Function Using the WAIT Bit
When the WAIT bit in ICMR3 is set to 1, the RIIC performs one-byte receive operation using the WAIT bit function.
Furthermore, when the ICMR3.RDRFS bit is 0, the RIIC automatically sends the ACKBT bit value in ICMR3 for the
acknowledge bit in the period from the falling edge of the eighth SCL clock cycle to the falling edge of the ninth SCL
clock cycle, and automatically holds the SCL line low at the falling edge of the ninth SCL clock cycle using the WAIT bit
function. This low-hold is released by reading data from ICDRR, which enables bytewise receive operation.
The WAIT bit function is enabled for receive frames after a match with the RIIC’s own slave address (including the
general call address and host address) is obtained in master receive mode or slave receive mode.
(2) One-Byte Receive Operation (ACK/NACK Transmission Control) and Automatic Low-Hold
Function Using the RDRFS Bit
When the RDRFS bit in ICMR3 is set to 1, the RIIC performs one-byte receive operation using the RDRFS bit function.
When the RDRFS bit is set to 1, the RDRF flag (receive data full) in ICSR2 is set to 1 at the rising edge of the eighth
SCL clock cycle, and the SCL line is automatically held low at the falling edge of the eighth SCL clock cycle. This low-
hold is released by writing a value to the ACKBT bit in ICMR3, but cannot be released by reading data from ICDRR,
which enables receive operation by the ACK/NACK transmission control according to the data received in byte units.
The RDRFS bit function is enabled for receive frames after a match with the RIIC’s own slave address (including the
general call address and host address) is obtained in master receive mode or slave receive mode.
Automatic low-hold
[RDRFS = 0, WAIT = 0]
(to prevent failure to receive data)
9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4
SCL
RDRF
RDRF
RDRF
ACKBT
RDRF
ACKBT
Figure 29.32 Automatic Low-Hold Operation in Receive Mode (Using RDRFS and WAIT Bits)
SDA 1
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5
SCL
TRS
AL
AASy
TDRE
Clear AL to 0
[When data transmission conflicts after general call address is sent] Transmit data mismatch Release SCL/SDA
(Arbitration lost)
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5
SCL
SDA 0 0 0 0 0 0 0 W ACK 1
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5
SCL
BBSY
MST
Receive data
TRS
AL
Read ICDRR
Bus free (BBSY = 0) start condition issuance (ST = 1) error Bus busy (BBSY =1) start condition issuance (ST = 1) error
SDA mismatch
PCLK PCLK PCLK
S 1 S 1 2 S 1 2 6 7 8 9 1
ST ST ST
AL AL AL
29.9.2 Function to Detect Loss of Arbitration during NACK Transmission (NALE Bit)
The RIIC has a function to cause arbitration to be lost if the internal SDA output level does not match the level on the
SDA line (the high output as the internal SDA output; i.e. the SDA pin is in the high-impedance state) and the low level
is detected on the SDA line during transmission of NACK in receive mode. Arbitration is lost due to a conflict of NACK
transmission and ACK transmission when two or more master devices receive data from the same slave device
simultaneously in a multi-master system. Such conflict occurs when multiple master devices send/receive the same
information through a single slave device. Figure 29.35 shows an example of arbitration-lost detection during
transmission of NACK.
2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5
SCL
BBSY
MST
Receive data Receive data
TRS
AL
RDRFS
RDRF
ACKBT
The following explains arbitration-lost detection using an example where two master devices (master A and master B)
and a single slave device are connected through the bus. In this example, master A receives two bytes of data from the
slave device, and master B receives four bytes of data from the slave device.
If master A and master B access the slave device simultaneously, because the slave address is identical, arbitration is not
lost in both master A and master B during access to the slave device. Therefore, both master A and master B recognize
that they have obtained the bus mastership and operate as such. Here, master A sends NACK when it has received two
final bytes of data from the slave device. Meanwhile, master B sends ACK because it has not received necessary four
bytes of data. At this time, the NACK transmission from master A and the ACK transmission from master B conflict. In
general, if a conflict like this occurs, master A cannot detect ACK transmitted by master B and issues a stop condition.
Therefore, the issuance of the stop condition conflicts with the SCL clock output of master B, which disturbs
communication.
When the RIIC receives ACK during transmission of NACK, it detects a defeat in conflict with other master devices and
causes arbitration to be lost.
If arbitration is lost during transmission of NACK, the RIIC immediately cancels the slave match condition and enters
slave receive mode. This prevents a stop condition from being issued, preventing a communication failure on the bus.
Similarly, in the ARP command processing of SMBus, the function to detect loss of arbitration during transmission of
NACK is also available for eliminating the extra clock cycle processing (such as FFh transmission processing) necessary
if the UDID (Unique Device Identifier) of assign address does not match in the Get UDID (general) processing after the
Assign address command.
The RIIC detects arbitration-lost during transmission of NACK when the following condition is met with the NALE bit
in ICFER set to 1 (arbitration-lost detection during NACK transmission enabled).
2 3 4 5 6 7 8 9 1 2 3 4 5
SCL
2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6
SCL
BBSY
MST
TRS
AL
TDRE
IIC IIC
BBSY BBSY
MST MST
TRS TRS
TDRE TDRE
START START
ST RS
Figure 29.37 Start Condition/Restart Condition Issue Timing (ST and RS Bits)
SCL 8 9 P
Issue stop
SDA b0 ACK/NACK condition
IIC
BBSY
MST
TRS
TDRE
STOP
SP
The internal counter of the timeout function works using the internal reference clock (IIC) set by the CKS[2:0] bits in
ICMR1 as a count source. It functions as a 16-bit counter when long mode is selected (TMOS bit = 0 in ICMR2) or a 14-
bit counter when short mode is selected (TMOS bit = 1).
The SCL line level (low/high or both levels) during which this counter is activated can be selected by the setting of the
TMOH and TMOL bits in ICMR2. If both TMOL and TMOH bits are cleared to 0, the internal counter does not work.
[Timeout function]
Start internal Start internal Start internal Start internal Start internal Start internal
counter counter counter counter counter counter
Clear internal Clear internal Clear internal Clear internal Clear internal Clear internal Clear internal
counter counter counter counter counter counter counter
SCL
SDA
IIC
BBSY
TMOE
TMOH
TMOL
[Example of operation when TMOH = 1 and TMOL = 1] When a stat condition is issued In the slave-address matched state
14-bit counter 16-bit counter
Clear internal counter Start internal counter overflows
overflows
TMOS = 0 TMOS = 1
7 8 9 P S 1 2 7 8 9 1 2
SCL
SDA A/NA Bus free time 7-bit slave address R/W ACK Data
BBSY
ST
TMOE
TMOF
Figure 29.39 Timeout Function (TMOE, TMOS, TMOH, and TMOL Bits)
Figure 29.40 shows the operation timing of the extra SCL clock cycle output function (CLO bit).
SDA line is held low due to irregular bits Release SDA line
ICBRH ICBRL ICBRH ICBRL ICBRH ICBRL
Extra clock cycle Extra clock cycle
SCL 9 output output
IIC
BBSY
MST
TRS
CLO
Figure 29.40 Extra SCL Clock Cycle Output Function (CLO Bit)
condition. In master transmit mode, immediately stop the transmit operation (writing data to ICDRT).
SMBus standard TLOW:SEXT: Total clock low-level extended period (slave device)
TLOW:MEXT: Total clock low-level extended period (master device)
Start Stop
TLOW:SEXT
S 1 2 7 8 9 1 2 7 8 9 1 2 7 8 9 P
SCL
SDA 7-bit slave address R/W ACK Data ACK Data A/NA
BBSY
TDRE
TEND
RDRF
RDRFS
START
STOP
Bus interface
Internal
Module data bus peripheral bus 2
SPDR
SPSCR
Parity circuit
SPSSR
SPDCR
SPCKD
SSLND
Shift register
SPND
SPCR2
SPCMD
Clock
Loopback
Loopback
Loopback 2 Slave
Normal Master
MISOA
SPTI
Loopback SPRI
Slave
Loopback 2 SPII
SPEI
SSLA0
SSLA1 to SSLA3
RSPCKA
Table 30.2 lists the input and output pins used in the RSPI.
The RSPI automatically switches the input/output direction of the SSLA0 pin. SSLA0 is set as an output when the RSPI
is a single master and as an input when the RSPI is a multi-master or a slave. Pins RSPCKA, MOSIA, and MISOA are
automatically set as inputs or outputs according to the setting of master or slave and the level input on the SSLA0 pin
(see section 30.3.2, Controlling RSPI Pins).
b7 b6 b5 b4 b3 b2 b1 b0
If the SPCR.MSTR, SPCR.MODFEN, and SPCR.TXMD bits are changed while the SPCR.SPE bit is 1, subsequent
operations cannot be guaranteed.
b7 b6 b5 b4 b3 b2 b1 b0
If the contents of SSLP are changed while the SPCR.SPE bit is 1, subsequent operations are not guaranteed.
b7 b6 b5 b4 b3 b2 b1 b0
If the contents of SPPCR are changed while the SPCR.SPE bit is 1, subsequent operations are not guaranteed.
b7 b6 b5 b4 b3 b2 b1 b0
x: Undefined
SPSR indicates the operating status of the RSPI. Writing to SPSR can only be performed under certain conditions.
The active level of the SSLAi signal is determined by the SSLP.SSLiP bit (SSL signal polarity setting bit).
[Clearing condition]
When SPSR is read while the MODF flag is 1, and then writes the value 0 to the MODF flag
b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16
SPD31 SPD30 SPD29 SPD28 SPD27 SPD26 SPD25 SPD24 SPD23 SPD22 SPD21 SPD20 SPD19 SPD18 SPD17 SPD16
SPD15 SPD14 SPD13 SPD12 SPD11 SPD10 SPD9 SPD8 SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0
SPDR is the interface with the buffers that hold data for transmission and reception by the RSPI. The transmit buffer
(SPTX) and receive buffer (SPRX) are independent but are both mapped to SPDR. Figure 30.2 shows the Configuration
of SPDR.
SPTX2
SPTX3
SPDR
SPRX2
SPRX3
Note 1. The destination buffer and stage for access is automatically switched by hardware.
The transmit and receive buffers have four stages each. The number of stages to be used is selectable by the number of
frames specification bits in the RSPI data control register (SPDCR.SPFC[1:0]). The eight stages of the buffer are all
mapped to the single address of SPDR.
Data written to SPDR are written to a transmit-buffer stage (SPTXn) and then transmitted from the buffer. The receive
buffer holds received data on completion of reception. The receive buffer is not updated if an overrun is generated.
Furthermore, if the data length is other than 32 bits, bits not referred to in SPTXn (n = 0 to 3) are stored in the
corresponding bits in SPRXn. For example, if the data length is nine bits, the SPTXn[31:9] bits are stored in
SPRXn[31:9] (and received data are stored in the SPRXn[8:0] bits).
(a) Writing
Data written to SPDR are written to a transmit buffer (SPTXn). This is not influenced by the value of the
SPDCR.SPRDTD bit unlike when reading the SPDR register.
The transmit buffer includes a transmit buffer write pointer which is automatically updated to indicate the next stage each
time data is written to SPDR.
Figure 30.3 shows the configuration of the bus interface with the transmit buffer in the case of writing to SPDR.
SPTX0
SPDR
SPTX1
SPTX2
SPTX3
The sequence for switching the transmit buffer write pointer differs with the setting of the frame-number setting bits in
the RSPI data control register (SPDCR.SPFC[1:0]).
Settings of the SPFC[1:0] bits and sequence of switching the pointer among SPTX0 to SPTX3.
When the SPFC[1:0] bits are 00b: SPTX0 → SPTX0 → SPTX0 → …
When the SPFC[1:0] bits are 01b: SPTX0 → SPTX1 → SPTX0 → SPTX1 → …
When the SPFC[1:0] bits are 10b: SPTX0 → SPTX1 → SPTX2 → SPTX0 → SPTX1 → …
When the SPFC[1:0] bits are 11b: SPTX0 → SPTX1 → SPTX2 → SPTX3 → SPTX0 → SPTX1 → …
When 1 is written to the RSPI function enable bit in the RSPI control register (SPCR.SPE) while the bit’s current value is
0, SPTX0 will be the destination the next time writing proceeds.
When writing to the transmit buffer (SPTXn) after generation of the RSPI transmission interrupt, write the number of
frames set by the number of frames specification bits (SPFC[1:0]) in the RSPI data control register (SPDCR). Writing to
the transmit buffer (SPTXn) before the next RSPI transmission interrupt breaks off write access to the SPDR.
(b) Reading
SPDR can be read to read the value of a receive buffer (SPRXn; n = 0 to 3) or a transmit buffer (SPTXn; n = 0 to 3). The
setting of the RSPI receive/transmit data selection bit in the RSPI data control register (SPDCR.SPRDTD) selects
whether reading is of the receive or transmit buffer.
The structure of the SPDR when it is read includes two independent pointers (receive buffer read pointer and transmit
buffer read pointer). Reading SPDR causes automatic updating of the pointer so that it indicates the next stage of the
buffer.
Figure 30.4 shows the configuration of the bus interface with the receive and transmit buffers in the case of reading
from SPDR.
SPRX0
SPRX1
0
SPRX2
SPRX3
SPDR
SPTX0
SPTX1
1
SPTX2
SPTX3
The sequence for switching the receive buffer read pointer is the same as that for the transmit buffer write pointer. When
reading is from the transmit buffer, the value before that most recently written is read. Furthermore, only the read pointer
for the buffer that is currently selected for reading by the setting of the RSPI receive/transmit selection bit in the RSPI
data control register (SPDCR.SPRDTD) is updated, and the state of the read pointer for the other buffer is preserved.
When 1 is written to the RSPI function enable bit in the RSPI control register (SPCR.SPE) while the bit’s current value is
0, SPRX0 will be indicated by the buffer read pointer the next time reading proceeds.
If the transmit buffer is read in the interval after writing of the number of frames of data for transmission specified in the
number of frames specification bits (SPFC[1:0]) in the RSPI data control register (SPDCR) and generation of the RSPI
transmission interrupt, and before the next RSPI transmission interrupt, all bits of the value read are 0.
The SPTXn buffer-reading pointer is cleared when the number of frames of data for transmission specified in the number
of frames specification bits (SPFC[1:0]) in the RSPI data control register (SPDCR) are written after generation of the
RSPI transmission interrupt.
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — SPSLN[2:0]
SPSCR sets the sequence length when the RSPI operates in master mode. When changing the SPSCR.SPSLN[2:0] bits
while both the SPCR.MSTR and SPCR.SPE bits are 1, the bits should be changed while the SPSR.IDLNF flag is 0.
b7 b6 b5 b4 b3 b2 b1 b0
— SPECM[2:0] — SPCP[2:0]
SPSSR indicates the sequence control status when the RSPI operates in master mode.
Any writing to SPSSR is ignored.
b7 b6 b5 b4 b3 b2 b1 b0
SPBR sets the bit rate in master mode. If the contents of SPBR are changed while both the SPCR.MSTR and SPCR.SPE
bits are 1, subsequent operations cannot be guaranteed.
When the RSPI is used in slave mode, the bit rate depends on the bit rate of the input clock (bit rate satisfying the
electrical characteristics should be used) regardless of the settings of SPBR and the SPCMDm.BRDV[1:0] bits (bit rate
division setting bits).
The bit rate is determined by combinations of the SPBR setting and the SPCMDm.BRDV[1:0] bit setting. The equation
for calculating the bit rate is given below. In the equation, n denotes an SPBR setting (0, 1, 2, …, 255), and N denotes a
BRDV[1:0] bit setting (0, 1, 2, 3).
f (PCLK)
Bit rate =
2 × (n + 1) 2N
Table 30.3 lists examples of the relationship among the SPBR settings, the BRDV[1:0] settings, and bit rates.
Table 30.3 Relationship among SPBR Settings, BRDV[1:0] Settings, and Bit Rates
Bit Rate
Division
SPBR (n) BRDV[1:0] Bits (N) Ratio PCLK = 32 MHz
0 0 2 16.0 Mbps
1 0 4 8.00 Mbps
2 0 6 5.33 Mbps
3 0 8 4.00 Mbps
4 0 10 3.20 Mbps
5 0 12 2.67 Mbps
5 1 24 1.33 Mbps
5 2 48 667 kbps
5 3 96 333 kbps
255 3 4096 7.81 kbps
b7 b6 b5 b4 b3 b2 b1 b0
Up to four frames can be transmitted or received in one round of transmission or reception activation. The amount of data
in each transfer is controlled by the combination of the SPCMDm.SPB[3:0] bits, the SPSCR.SPSLN[2:0] bits, and the
SPDCR.SPFC[1:0] bits.
When changing the SPDCR.SPFC[1:0] bits while the SPCR.SPE bit is 1, the bits should be changed while the
SPSR.IDLNF flag is 0.
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — SCKDL[2:0]
SPCKD sets a period from the beginning of SSLAi signal assertion to RSPCK oscillation (RSPCK delay) when the
SPCMDm.SCKDEN bit is 1. If the contents of SPCKD are changed while both the SPCR.MSTR and SPCR.SPE bits are
1, subsequent operations cannot be guaranteed.
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — SLNDL[2:0]
SSLND sets a period (SSL negation delay) from the transmission of a final RSPCK edge to the negation of the SSLAi
signal during a serial transfer by the RSPI in master mode. If the contents of SSLND are changed while both the
SPCR.MSTR and SPCR.SPE bits are 1, subsequent operations cannot be guaranteed.
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — SPNDL[2:0]
SPND sets a non-active period (next-access delay) of the SSLAi signal after termination of a serial transfer when the
SPCMDm.SPNDEN bit is 1. If the contents of SPND are changed while both the SPCR.MSTR and SPCR.SPE bits are 1,
subsequent operations cannot be guaranteed.
b7 b6 b5 b4 b3 b2 b1 b0
If the SPPE bit or SPOE bit in SPCR2 is changed while the SPCR.SPE bit is 1, subsequent operations cannot be
guaranteed.
Address(es): RSPI0.SPCMD0 0008 8390h, RSPI0.SPCMD1 0008 8392h, RSPI0.SPCMD2 0008 8394h, RSPI0.SPCMD3 0008 8396h,
RSPI0.SPCMD4 0008 8398h, RSPI0.SPCMD5 0008 839Ah, RSPI0.SPCMD6 0008 839Ch, RSPI0.SPCMD7 0008 839Eh
SCKDE SLNDE SPNDE LSBF SPB[3:0] SSLKP SSLA[2:0] BRDV[1:0] CPOL CPHA
N N N
Value after reset: 0 0 0 0 0 1 1 1 0 0 0 0 1 1 0 1
SPCMDm register is used to set a transfer format for the RSPI in master mode. Each channel has eight RSPI command
registers (SPCMD0 to SPCMD7). Some of the bits in SPCMD0 register is used to set a transfer mode for the RSPI in
slave mode. The RSPI in master mode sequentially references SPCMDm register according to the settings in the
SPSCR.SPSLN[2:0] bits, and executes the serial transfer that is set in the referenced SPCMDm register.
SPCMDm register should be set while the transmit buffer is empty (data for the next transfer is not set) and before setting
of the data that is to be transmitted when that SPCMDm register is referenced.
SPCMDm that is referenced by the RSPI in master mode can be checked by means of the SPSSR.SPCP[2:0] bits. If the
contents of SPCMDm are changed while the SPCR.MSTR bit is 0 and the SPCR.SPE bit is 1, subsequent operations
cannot be guaranteed.
30.3 Operation
In this section, the serial transfer period means a period from the beginning of driving valid data to the fetching of the
final valid data.
Table 30.5 Relationship between RSPI Modes and SPCR Settings and Description of Each Mode
Slave Master
Slave Single-Master Multi-Master (Clock Synchronous (Clock Synchronous
Mode (SPI Operation) (SPI Operation) (SPI Operation) Operation) Operation)
MSTR bit setting 0 1 1 0 1
MODFEN bit setting 0 or 1 0 1 0 0
SPMS bit setting 0 0 0 1 1
RSPCKA signal Input Output Output/Hi-Z Input Output
MOSIA signal Input Output Output/Hi-Z Input Output
MISOA signal Output/Hi-Z Input Input Output Input
SSLA0 signal Input Output Input Hi-Z*1 Hi-Z*1
SSLA1 to SSLA3 signals Hi-Z*1 Output Output/Hi-Z Hi-Z*1 Hi-Z*1
SSL polarity modification Supported Supported Supported — —
function
Transfer rate Up to PCLK/8 Up to PCLK/2 Up to PCLK/2 Up to PCLK/8 Up to PCLK/2
Clock source RSPCK input On-chip baud rate On-chip baud rate RSPCK input On-chip baud rate
generator generator generator
Clock polarity Two Two Two Two Two
Clock phase Two Two Two One (CPHA = 1) Two
First transfer bit MSB/LSB MSB/LSB MSB/LSB MSB/LSB MSB/LSB
Transfer data length 8 to 32 bits 8 to 32 bits 8 to 32 bits 8 to 32 bits 8 to 32 bits
Burst transfer Possible Possible Possible — —
(CPHA = 1) (CPHA = 0,1) (CPHA = 0,1)
RSPCK delay control Not supported Supported Supported Not supported Supported
SSL negation delay Not supported Supported Supported Not supported Supported
control
Next-access delay Not supported Supported Supported Not supported Supported
control
Transfer activation SSL input active or Transmit buffer is written Transmit buffer is written RSPCK oscillation Transmit buffer is written
method RSPCK oscillation to at generation of a to at generation of a to at generation of a
transmit buffer empty transmit buffer empty transmit buffer empty
interrupt request interrupt request interrupt request
Sequence control Not supported Supported Supported Not supported Supported
Transmit buffer empty Supported Supported Supported Supported Supported
detection
Receive buffer full Supported*2 Supported*2 Supported*2 Supported*2 Supported*2
detection
Overrun error detection Supported*2 Supported*2 Supported*2 Supported*2 Supported*2
Parity error detection Supported*2,*3 Supported*2,*3 Supported*2,*3 Supported*2,*3 Supported*2,*3
Mode fault error Supported Not supported Supported Not supported Not supported
detection (MODFEN = 1)
The RSPI in single-master mode (SPI operation) or multi-master mode (SPI operation) determines MOSI signal values
during the SSL negation period (including the SSL retention period during a burst transfer) according to MOIFE and
MOIFV bit settings in SPPCR, as listed in Table 30.7.
Table 30.7 MOSI Signal Value Determination during SSL Negation Period
MOIFE Bit MOIFV Bit MOSIA Signal Value during SSL Negation Period
0 0, 1 Final data from previous transfer
1 0 Always low
1 1 Always High
Note 1. In the transfer format corresponding to the case where the SPCMDm.CPHA bit is 0, there are slave devices for
which the SSL signal cannot be fixed to the active level. In situations where the SSL signal cannot be fixed, the
SSLAi output of this LSI should be connected to the SSL input of the slave device.
RSPCKA
RSPCK RSPCK
MOSIA
MOSI MOSI
MISOA
MISO MISO
SSLA0
SSL0 SSL
SSLA1
SSL1
SSLA2
SSL2
SSLA3
SSL3
Note 1. When SSLA0 is at the non-active level, the pin state is Hi-Z.
RSPCK RSPCKA
RSPCK
MOSI MOSIA
MOSI
MISO MISOA
MISO
SSL SSL0
SSLA0
SSL1
SSLA1
SSL2
SSLA2
SSL3
SSLA3
RSPCK RSPCKA
RSPCK
MOSI MOSIA
MOSI
MISO MISOA
MISO
SSL SSLA0
SSL0
SSLA1
SSL1
SSLA2
SSL2
SSL3
SSLA3
RSPCKA
RSPCK RSPCK
MOSIA
MOSI MOSI
MISOA
MISO MISO
SSLA0
SSL0 SSL
SSLA1
SSL1
SSLA2
SSL2
SSLA3
SSL3 RSPI slave 1
RSPCK
MOSI
MISO
SSL
RSPI slave 2
RSPCK
MOSI
MISO
SSL
RSPI slave 3
RSPCK
MOSI
MISO
SSL
RSPCK RSPCKA
RSPCK
MOSI MOSIA
MOSI
MISO MISOA
MISO
SSLX SSLA0
SSL0
SSLY SSLA1
SSL1
SSLA2
SSL2
SSLA3
SSL3
RSPCKA
RSPCK
MOSIA
MOSI
MISOA
MISO
SSLA0
SSL0
SSLA1
SSL1
SSLA2
SSL2
SSLA3
SSL3
RSPCKA
RSPCK RSPCK
RSPCKA
MOSIA
MOSI MOSI
MOSIA
MISOA
MISO MISO
MISOA
SSL0
SSLA0 SSL0
SSLA0
SSL1
SSLA1 SSL1
SSLA1
SSL2
SSLA2 SSL2
SSLA2
SSL3
SSLA3 SSL3
SSLA3
Port Y Port X
RSPI slave 1
RSPCK
MOSI
MISO
SSL
RSPI slave 2
RSPCK
MOSI
MISO
SSL
RSPCKA
RSPCK RSPCK
MOSIA
MOSI MOSI
MISOA
MISO MISO
SSLA0
SSL0 SSL
SSLA1
SSL1
SSLA2
SSL2
SSLA3
SSL3
Figure 30.11 Master (Clock Synchronous Operation)/Slave (Clock Synchronous Operation) Configuration
Example (This LSI = Master)
RSPCK RSPCKA
RSPCK
MOSI MOSIA
MOSI
MISO MISOA
MISO
SSL SSLA0
SSL0
SSLA1
SSL1
SSLA2
SSL2
SSLA3
SSL3
Figure 30.12 Master (Clock Synchronous Operation)/Slave (Clock Synchronous Operation) Configuration
Example (This LSI = Slave, CPHA = 1)
D0 D1 D2 Dn-2 Dn-1 Dn
SPCMDm.SPB[3:0] (m = SPSSR.SPCP[2:0])
D0 D1 D2 Dn-2 Dn-1 P
SPCMDm.SPB[3:0] (m = SPSSR.SPCP[2:0])
Transfer start
T31 T30 T29 T28 T27 T26 T25 T24 T23 T08 T07 T06 T05 T04 T03 T02 T01 T00
Copy
Output T31 T30 T29 T28 T27 T26 T25 T24 T23 T08 T07 T06 T05 T04 T03 T02 T01 T00
Bit 31 Bit 0
Shift register
Transfer end
Shift register
Bit 31 Bit 0
R31 R30 R29 R28 R27 R26 R25 R24 R23 R08 R07 R06 R05 R04 R03 R02 R01 R00 Input
Copy
R31 R30 R29 R28 R27 R26 R25 R24 R23 R08 R07 R06 R05 R04 R03 R02 R01 R00
Bit 31 Bit 0
SPDR (receive buffer)
Transfer start
T31 T30 T29 T28 T27 T26 T25 T24 T23 T08 T07 T06 T05 T04 T03 T02 T01 T00
Output Copy
T31 T30 T29 T28 T27 T26 T25 T24 T23 T08 T07 T06 T05 T04 T03 T02 T01 T00
Transfer end
Shift register
Bit 31 Bit 24 Bit 23 Bit 0
T31 T30 T29 T28 T27 T26 T25 T24 R23 R00 Input
R08 R07 R06 R05 R04 R03 R02 R01
Copy
T31 T30 T29 T28 T27 T26 T25 T24 R23 R08 R07 R06 R05 R04 R03 R02 R01 R00
Transfer start
T31 T30 T29 T28 T27 T26 T25 T24 T23 T08 T07 T06 T05 T04 T03 T02 T01 T00
Copy
Output T00 T01 T02 T03 T04 T05 T06 T07 T08 T23 T24 T25 T26 T27 T28 T29 T30 T31
Bit 31 Bit 0
Shift register
Transfer end
Shift register
Bit 31 Bit 0
R00 R01 R02 R03 R04 R05 R06 R07 R08 R23 R24 R25 R26 R27 R28 R29 R30 R31 Input
Copy (SPCR.TXMD = 0)
R31 R30 R29 R28 R27 R26 R25 R24 R23 R08 R07 R06 R05 R04 R03 R02 R01 R00
Bit 31 Bit 0
SPDR (receive buffer)
Transfer start
T31 T30 T29 T28 T27 T26 T25 T24 T23 T08 T07 T06 T05 T04 T03 T02 T01 T00
Copy
Output T00 T01 T02 T03 T04 T05 T06 T07 T08 T23 T24 T25 T26 T27 T28 T29 T30 T31
Bit 31 Bit 0
Shift register
Transfer end
Input
Shift register
Bit 31 Bit 0
R00 R01 R02 R03 R04 R05 R06 R07 R08 R23 T24 T25 T26 T27 T28 T29 T30 T31
Copy
T31 T30 T29 T28 T27 T26 T25 T24 R23 R08 R07 R06 R05 R04 R03 R02 R01 R00
Bit 31 Bit 0
SPDR (receive buffer)
Transfer start
Parity calculated
Parity added
T31 T30 T29 T28 T27 T26 T25 T24 T23 T08 T07 T06 T05 T04 T03 T02 T01 P
Copy
Output T31 T30 T29 T28 T27 T26 T25 T24 T23 T08 T07 T06 T05 T04 T03 T02 T01 P
Bit 31 Bit 0
Shift register
Transfer end
Shift register
Bit 31 Bit 0
R31 R30 R29 R28 R27 R26 R25 R24 R23 R08 R07 R06 R05 R04 R03 R02 R01 P Input
Copy (SPCR.TXMD = 0)
R31 R30 R29 R28 R27 R26 R25 R24 R23 R08 R07 R06 R05 R04 R03 R02 R01 P
Bit 31 Bit 0
SPDR (receive buffer)
Transfer start
T31 T30 T29 T28 T27 T26 T25 T24 T23 T08 T07 T06 T05 T04 T03 T02 T01 T00
Parity added
T31 T30 T29 T28 T27 T26 T25 T24 T23 T08 T07 T06 T05 T04 T03 T02 T01 P
Output Copy
T31 T30 T29 T28 T27 T26 T25 T24 T23 T08 T07 T06 T05 T04 T03 T02 T01 P
Transfer end
Shift register
Bit 31 Bit 24 Bit 23 Bit 0
T31 T30 T29 T28 T27 T26 T25 T24 R23 R08 R07 R06 R05 R04 R03 R02 R01 P Input
Copy
T31 T30 T29 T28 T27 T26 T25 T24 R23 R08 R07 R06 R05 R04 R03 R02 R01 P
Transfer start
T31 T30 T29 T28 T27 T26 T25 T24 T23 T08 T07 T06 T05 T04 T03 T02 T01 T00
Bit 31 Bit 0
P T30 T29 T28 T27 T26 T25 T24 T23 T08 T07 T06 T05 T04 T03 T02 T01 T00
Copy
Output T00 T01 T02 T03 T04 T05 T06 T07 T08 T23 T24 T25 T26 T27 T28 T29 T30 P
Bit 31 Bit 0
Shift register
Transfer end
Shift register
Bit 31 Bit 0
R00 R01 R02 R03 R04 R05 R06 R07 R08 R23 R24 R25 R26 R27 R28 R29 R30 P Input
Copy
P R30 R29 R28 R27 R26 R25 R24 R23 R08 R07 R06 R05 R04 R03 R02 R01 R00
Bit 31 Bit 0
SPDR (receive buffer)
Transfer start
T31 T30 T29 T28 T27 T26 T25 T24 T23 T08 T07 T06 T05 T04 T03 T02 T01 T00
Bit 31 Bit 0
T31 T30 T29 T28 T27 T26 T25 T24 P T08 T07 T06 T05 T04 T03 T02 T01 T00
Copy
Output T00 T01 T02 T03 T04 T05 T06 T07 T08 P T24 T25 T26 T27 T28 T29 T30 T31
Bit 31 Bit 0
Shift register
Transfer end
Input
Shift register
Bit 31 Bit 0
R00 R01 R02 R03 R04 R05 R06 R07 R08 P T24 T25 T26 T27 T28 T29 T30 T31
Copy
T31 T30 T29 T28 T27 T26 T25 T24 P R08 R07 R06 R05 R04 R03 R02 R01 R00
Bit 31 Bit 0
SPDR (receive buffer)
30.3.5.1 CPHA = 0
Figure 30.23 shows a sample transfer format for the serial transfer of 8-bit data when the SPCMDm.CPHA bit is 0.
Note that clock synchronous operation (the SPCR.SPMS bit is 1) is not guaranteed when the RSPI operates in slave
mode (SPCR.MSTR = 0) and the CPHA bit is 0. In Figure 30.23, RSPCKA (CPOL = 0) indicates the RSPCKA signal
waveform when the SPCMDm.CPOL bit is 0; RSPCKA (CPOL = 1) indicates the RSPCKA signal waveform when the
CPOL bit is 1. The sampling timing represents the timing at which the RSPI fetches serial transfer data into the shift
register. The input/output directions of the signals depend on the RSPI settings. For details, see section 30.3.2,
Controlling RSPI Pins.
When the SPCMDm.CPHA bit is 0, the driving of valid data to the MOSIA and MISOA signals commences at an SSLAi
signal assertion timing. The first RSPCKA signal change timing that occurs after the SSLAi signal assertion becomes the
first transfer data fetch timing. After this timing, data is sampled at every 1 RSPCK cycle. The change timing for MOSIA
and MISOA signals is always 1/2 RSPCK cycles after the transfer data fetch timing. The CPOL bit setting does not affect
the RSPCK signal operation timing; it only affects the signal polarity.
t1 denotes a period from an SSLAi signal assertion to RSPCKA oscillation (RSPCK delay). t2 denotes a period from the
termination of RSPCKA oscillation to an SSLAi signal negation (SSL negation delay). t3 denotes a period in which
SSLAi signal assertion is suppressed for the next transfer after the end of serial transfer (next-access delay). t1, t2, and t3
are controlled by a master device running on the RSPI system. For a description of t1, t2, and t3 when the RSPI of this
LSI is in master mode, see section 30.3.10.1, Master Mode Operation.
Start End
Serial transfer period
RSPCK
1 2 3 4 5 6 7 8
cycle
RSPCK
RSPCKA
(CPOL = 0)
(CPOL = 0)
RSPCKA
RSPCK
(CPOL==1)
(CPOL 1)
Sampling
timing
MOSIA
MOSI
MISOA
MISO
SSLAi
SSLi
t1 t2 t3
30.3.5.2 CPHA = 1
Figure 30.24 shows a sample transfer format for the serial transfer of 8-bit data when the SPCMDm.CPHA bit is 1.
However, when the SPCR.SPMS bit is 1, the SSLAi signals are not used, and only the three signals RSPCKA, MOSIA,
and MISOA handle communications. In Figure 30.24, RSPCK (CPOL = 0) indicates the RSPCKA signal waveform
when the SPCMDm.CPOL bit is 0; RSPCK (CPOL = 1) indicates the RSPCKA signal waveform when the CPOL bit is
1. The sampling timing represents the timing at which the RSPI fetches serial transfer data into the shift register. The
input/output directions of the signals depend on the RSPI mode (master or slave). For details, see section 30.3.2,
Controlling RSPI Pins.
When the SPCMDm.CPHA bit is 1, the driving of invalid data to the MISOA signal commences at an SSLAi signal
assertion timing. The output of valid data to the MOSIA and MISOA signals commences at the first RSPCKA signal
change timing that occurs after the SSLAi signal assertion. After this timing, data is updated at every 1 RSPCK cycle.
The transfer data fetch timing is always 1/2 RSPCK cycles after the data update timing. The SPCMDm.CPOL bit setting
does not affect the RSPCKA signal operation timing; it only affects the signal polarity.
t1, t2, and t3 are the same as those in the case of CPHA = 0. For a description of t1, t2, and t3 when the RSPI of this LSI
is in master mode, see section 30.3.10.1, Master Mode Operation.
Start End
Serial transfer period
RSPCK
cycle 1 2 3 4 5 6 7 8
RSPCK
RSPCKA
(CPOL
(CPOL==0)0)
RSPCKA
RSPCK
(CPOL==1)1)
(CPOL
Sampling
timing
MOSIA
MOSI
MISOA
MISO
SSLAi
SSLi
t1 t2 t3
SPDR access W W
RSPCKA
(CPHA = 1, CPOL = 0)
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
TXMD
(TXMD = 0)
SPRI
(1)
OVRF
(2)
The operation of the flags at timings shown in steps (1) and (2) in the figure is described below.
(1) When a serial transfer ends with the receive buffer of SPDR empty, the RSPI generates a receive buffer full interrupt
request (SPRI) and copies the received data in the shift register to the receive buffer.
(2) When a serial transfer ends with the receive buffer of SPDR holding data that was received in the previous serial
transfer, the RSPI sets the SPSR.OVRF flag to 1 and discards the received data in the shift register.
SPDR access W W
RSPCKA
(CPHA = 1, CPOL = 0)
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
TXMD
(TXMD = 1)
(1)
Receive buffer
Empty
state
SPRI
(2)
OVRF
(3)
The operation of the flags at timings shown in steps (1) to (3) in the figure is described below.
(1) Make sure there is no data left in the receive buffer and the SPSR.OVRF flag is 0 before entering the mode of
transmit operations only (SPCR.TXMD = 1).
(2) When a serial transfer ends with the receive buffer of SPDR empty, if the mode of transmit operations only is
selected (SPCR.TXMD = 1), the RSPI does not copy the data in the shift register to the receive buffer.
(3) Since the receive buffer of SPDR does not hold data that was received in the previous serial transfer, even when a
serial transfer ends, the SPSR.OVRF flag retains the value of 0, and the data in the shift register is not copied to the
receive buffer.
When performing transmit operations only (SPCR.TXMD = 1), the RSPI transmits transmit data but does not receive
received data. Therefore, the SPSR.OVRF flag remains cleared to 0 at the timings of (1) to (3).
SPDR access W W R
RSPCKA
(CPHA = 1, CPOL = 0)
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
(1) (3)
SPTI
(2) (4)
(5)
SPRI
The operation of the interrupts at timings shown in steps (1) to (5) in the figure is described below.
1. When transmit data is written to SPDR when the transmit buffer of SPDR is empty (data for the next transfer is not
set), the RSPI writes data to the transmit buffer.
2. If the shift register is empty, the RSPI copies the data in the transmit buffer to the shift register and generates a
transmit buffer empty interrupt request (SPTI). How a serial transfer is started depends on the mode of the RSPI.
For details, see section 30.3.10, SPI Operation, and section 30.3.11, Clock Synchronous Operation.
3. When transmit data is written to SPDR by the transmit buffer empty interrupt routine, the data is transferred to the
transmit buffer. Because the data being transferred serially is stored in the shift register, the RSPI does not copy the
data in the transmit buffer to the shift register.
4. When the serial transfer ends with the receive buffer of SPDR being empty, the RSPI copies the receive data in the
shift register to the receive buffer and generates a receive buffer full interrupt request (SPRI). Since the shift register
becomes empty upon completion of serial transfer, when the transmit buffer had been full before the serial transfer
ended, the RSPI copies the data in the transmit buffer to the shift register. Even when received data is not copied
from the shift register to the receive buffer in an overrun error status, upon completion of the serial transfer, the
RSPI determines that the shift register is empty, thus data transfer from the transmit buffer to the shift register is
enabled.
5. When SPDR is read by the receive buffer full interrupt routine, the receive data can be read.
If SPDR is written to when the transmit buffer holds data that has not yet been transmitted, the RSPI does not update the
data in the transmit buffer. When writing to SPDR, make sure to use a transmit buffer empty interrupt request. To use an
RSPI transmit interrupt, set the SPTIE bit in SPCR to 1.
If the RSPI function is disabled (the SPE bit in SPCR being 0), set the SPTIE bit to 0.
When serial transfer ends with the receive buffer being full, the RSPI does not copy data from the shift register to the
receive buffer, and detects an overrun error (see section 30.3.8, Error Detection). To prevent a receive data overrun
error, read the received data using a receive buffer full interrupt request before the next serial transfer ends. To use an
RSPI receive interrupt, set the SPCR.SPRIE bit to 1.
Transmission and reception interrupts or the corresponding IRn.IR flags (where n is the vector number) in ICU can be
used to confirm the states of the transmission and reception buffers. See section 14, Interrupt Controller (ICUb), for
the vector numbers.
Table 30.8 Relationship between Non-Normal Transfer Operations and RSPI Error Detection Function
Occurrence Condition RSPI Operation Error Detection
A SPDR is written when the transmit buffer is full. The contents of the transmit buffer are kept. None
Missing write data.
B Serial transfer is started in slave mode when transmit Data received in previous serial transfer is None
data is still not loaded on the shift register. serially transmitted.
C SPDR is read when the receive buffer is empty. Previously received serial data is output. None
D Serial transfer terminates when the receive buffer is full. The contents of the receive buffer are kept. Overrun error
Missing serial receive data.
E An incorrect parity bit is received when performing full- The parity error flag is asserted. Parity error
duplex synchronous serial communications with the par-
ity function enabled.
F The SSLA0 input signal is asserted when the serial Driving of the RSPCKA, MOSIA, SSLA1 to Mode fault error
transfer is idle in multi-master mode. SSLA3 output signals is stopped.
RSPI function is disabled.
G The SSLA0 input signal is asserted during serial transfer Serial transfer is suspended. Mode fault error
in multi-master mode. Missing transmit/receive data.
Driving of the RSPCKA, MOSIA, SSLA1 to
SSLA3 output signals is stopped.
RSPI function is disabled.
H The SSLA0 input signal is negated during serial transfer Serial transfer is suspended. Mode fault error
in slave mode. Missing transmit/receive data.
Driving of the MISOA output signal is
stopped.
RSPI function is disabled.
On operation A described in Table 30.8, the RSPI does not detect an error. To prevent data omission during the writing
to SPDR, write operations to SPDR should be executed using a transmit interrupt request.
Likewise, the RSPI does not detect an error on operation B. In a serial transfer that was started before the shift register
was updated, the RSPI sends the data that was received in the previous serial transfer, and does not treat the operation
indicated in B as an error. Note that the received data from the previous serial transfer is retained in the receive buffer of
SPDR, thus it can be correctly read (if SPDR is not read before the end of the serial transfer, an overrun error may occur).
Similarly, the RSPI does not detect an error on operation C. To prevent extraneous data from being read, SPDR read
operation should be executed using a receive interrupt request.
An overrun error shown in D is described in section 30.3.8.1, Overrun Error. A parity error shown in E is described in
section 30.3.8.2, Parity Error. A mode fault error shown in F to H is described in section 30.3.8.3, Mode Fault
Error.
For the transmit and receive interrupts, refer to section 30.3.7, Transmit Buffer Empty/Receive Buffer Full
Interrupts.
SPSR access R W
SPDR access R
RSPCKA
(CPHA = 1, CPOL = 0)
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
(2) (3)
Receive buffer
Full Empty
state
OVRF (4)
(1)
The operation of the flags at the timing shown in steps (1) to (4) in the figure is described below.
1. If a serial transfer terminates with the receive buffer full, the RSPI detects an overrun error, and sets the OVRF flag
to 1. The RSPI does not copy the data in the shift register to the receive buffer. Even if the SPPE bit is 1, parity
errors are not detected. In master mode, the RSPI copies the pointer value to SPCMDm register to the
SPSSR.SPECM[2:0] bits.
2. When SPDR is read, the RSPI outputs the data in the receive buffer can be read. The receive buffer becoming empty
does not clear the OVRF flag.
3. If the serial transfer ends with the OVRF flag being 1 (an overrun error), the RSPI does not copy the data in the shift
register to the receive buffer. A reception-buffer interrupt is not generated. Even if the SPPE bit is 1, parity errors
are not detected. When in master mode, the RSPI does not update the SPSSR.SPECM[2:0] bits. When in an overrun
error state and the RSPI does not copy the received data from the shift register to the receive buffer, upon
termination of the serial transfer, the RSPI determines that the shift register is empty; in this manner, data transfer
from the transmit buffer to the shift register is enabled.
4. If the value 0 is written to the OVRF flag after SPSR is read when the OVRF flag is 1, OVRF flag is cleared to 0.
The occurrence of an overrun can be checked either by reading SPSR or by using an RSPI error interrupt and reading
SPSR. When executing a serial transfer, measures should be taken to ensure the early detection of overrun errors, such as
reading SPSR immediately after SPDR is read. When the RSPI is used in master mode, the pointer value to SPCMDm
register at the occurrence of the error can be checked by reading the SPSSR.SPECM[2:0] bits.
If an overrun error occurs and the OVRF flag is set to 1, normal reception operations cannot be performed until the
OVRF flag is cleared.
SPSR access R W
RSPCKA
(CPHA = 1, CPOL = 0)
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
PERF (2)
(1)
OVRF (3)
The operation of the flags at the timing shown in steps (1) to (3) in the figure is described below.
1. If a serial transfer terminates with the RSPI not detecting an overrun error, the RSPI copies the data in the shift
register to the receive buffer. The RSPI judges the received data at this timing, and sets the PERF flag to 1 if a parity
error is detected. In master mode, the RSPI copies the pointer value to SPCMDm register to the
SPSSR.SPECM[2:0] bits.
2. If the value 0 is written to the PERF flag after SPSR register is read when the PERF flag is 1, the PERF flag is
cleared to 0.
3. When the RSPI detects an overrun error and serial transfer is terminated, the data in the shift register is not copied to
the receive buffer. The RSPI does not perform parity error detection at this timing.
The occurrence of a parity error can be checked either by reading SPSR register or by using an RSPI error interrupt and
reading SPSR register. When executing a serial transfer, measures should be taken to ensure the early detection of parity
errors, such as reading SPSR. When the RSPI is used in master mode, the pointer value to SPCMDm register at the
occurrence of the error can be checked by reading the SPSSR.SPECM[2:0] bits.
Initialization by the clearing of the SPE bit does not initialize the control bits of the RSPI. For this reason, the RSPI can
be started in the same transfer mode as prior to the initialization if the SPE bit is set to 1 again.
The OVRF and MODF flags in SPSR are not initialized, nor is the value of the RSPI sequence status register (SPSSR)
initialized. For this reason, even after the RSPI is initialized, data from the receive buffer can be read in order to check
the status of error occurrence during an RSPI transfer.
The transmit buffer is initialized to an empty state. Therefore, if the SPTIE bit in SPCR is set to 1 after RSPI
initialization, an RSPI transmit interrupt is generated. When the RSPI is initialized, in order to disable any RSPI transmit
interrupt, the value 0 should be written to the SPTIE bit simultaneously with the writing of the value 0 to the SPE bit. To
disable any RSPI transmit interrupt after a mode fault error is detected, use an error handling routine to write the value 0
to the SPTIE bit.
Sequence length setting Determining reference command Loading transfer format settings
SPSCR
Command
pointer control
SPCMD0
SPCMD1
SPCMD2
SPCMD3
SPCMD4 SCKDEN SLDNEN SPNDEN
SPCMD5 CPHA SSLND SPND
SPCKD
SPCMD6 CPOL
SPCMD7 BRDV[1:0]
SSLA[2:0]
SSLKP
SPB[3:0]
LSBF
Transfer format determiner
Figure 30.30 Procedure for Determining the Form of Serial Transfer in Master Mode
In this section, a frame is the combination of the data (SPDR) and the settings (SPCMDm).
Data
(SPDR) Frame
Data
+
Settings
Settings
(SPCMD)
Figure 30.32 shows the relationship between the command and the transmit and receive buffers in the sequence of
operations specified by the settings in Table 30.4.
SPTX0/SPRX0
Setting 1-1
SPCMD0
Only 1 frame
SPTX0/SPRX0 SPTX1/SPRX1
Setting 1-2
SPCMD0 SPCMD0
SPTX0/SPRX0 SPTX1/SPRX1
Setting 2-1
SPCMD0 SPCMD1
1st frame 2nd frame 3rd frame 4th frame 5th frame
1st frame 2nd frame 3rd frame 4th frame 5th frame 6th frame
1st frame 2nd frame 3rd frame 4th frame 5th frame 6th frame 7th frame
1st frame 2nd frame 3rd frame 4th frame 5th frame 6th frame 7th frame 8th frame
Figure 30.32 Correspondence between the RSPI Command Register and Transmit/Receive Buffers in
Sequence Operations
RSPCKA
RSPCKn
(CPHA = 1,
CPOL = 0)
SSLinSSLAi
(1) Based on SPCMD0, the RSPI asserts the SSLAi signal and inserts RSPCK delays.
(2) The RSPI executes serial transfers according to SPCMD0.
(3) The RSPI inserts SSL negation delays.
(4) Since the SPCMD0.SSLKP bit is 1, the RSPI keeps the SSLAi signal value on SPCMD0. This period is sustained,
at the shortest, for a period equal to the next-access delay of SPCMD0. If the shift register is empty after the passage
of a minimum period, this period is sustained until the transmit data is stored in the shift register for the next
transfer.
(5) Based on SPCMD1, the RSPI asserts the SSLAi signal and inserts RSPCK delays.
(6) The RSPI executes serial transfers according to SPCMD1.
(7) Because the SPCMD1.SSLKP bit is 0, the RSPI negates the SSLAi signal. In addition, a next-access delay is
inserted according to SPCMD1.
If the SSLAi signal output settings in the SPCMDm register in which 1 is assigned to the SSLKP bit are different from
the SSLAi signal output settings in the SPCMDm register to be used in the next transfer, the RSPI switches the SSLAi
signal status to SSLAi signal assertion ((5) in Figure 30.33) corresponding to the command for the next transfer. Note
that if such an SSLAi signal switching occurs, the slaves that drive the MISOA signal compete, and collision of signal
levels may occur.
The RSPI in master mode references the SSLAi signal operation within the module for the case where the SSLKP bit is
not used. Even when the SPCMDm.CPHA bit is 0, the RSPI can accurately start serial transfers by using the SSLAi
signal assertion for the next transfer that is detected internally. For this reason, burst transfers in master mode can be
executed irrespective of CPHA bit settings (see section 30.3.10, SPI Operation).
Table 30.9 Relationship among SCKDEN Bit, SPCKD, and RSPCK Delay Value
SPCMDm.SCKDEN Bit SPCKD.SCKDL[2:0] Bits RSPCK Delay Value
0 000 to 111 1 RSPCK
1 000 1 RSPCK
001 2 RSPCK
010 3 RSPCK
011 4 RSPCK
100 5 RSPCK
101 6 RSPCK
110 7 RSPCK
111 8 RSPCK
Table 30.10 Relationship among SLNDEN Bit, SSLND, and SSL Negation Delay Value
SPCMDm.SLNDEN Bit SSLND.SLNDL[2:0] Bits SSL Negation Delay Value
0 000 to 111 1 RSPCK
1 000 1 RSPCK
001 2 RSPCK
010 3 RSPCK
011 4 RSPCK
100 5 RSPCK
101 6 RSPCK
110 7 RSPCK
111 8 RSPCK
Table 30.11 Relationship among SPNDEN Bit, SPND, and Next-Access Delay Value
SPCMDm.SPNDEN Bit SPND.SPNDL[2:0] Bits Next-Access Delay Value
0 000 to 111 1 RSPCK + 2 PCLK
1 000 1 RSPCK + 2 PCLK
001 2 RSPCK + 2 PCLK
010 3 RSPCK + 2 PCLK
011 4 RSPCK + 2 PCLK
100 5 RSPCK + 2 PCLK
101 6 RSPCK + 2 PCLK
110 7 RSPCK + 2 PCLK
111 8 RSPCK + 2 PCLK
Start of initialization in
master mode
End of initialization in
master mode
Start processing
End of initial settings for transmission
Yes
Yes
No
SPII interrupt?
Yes
SPCR.SPE = 0,
SPCR2.SPIIE = 0
End of
processing for
transmission
Start processing
End of initial settings for reception
Yes
Set SPCR2.SPIIE = 0 [2] Prohibit SPII interrupts. Read receive data from SPDR [4] [4] Access when the interrupt
processing routine is executed once
is to the number of frames set in
SPDCR.SPFC[1:0].
[3] Set the SPE bit to “enabled”.
Set SPCR.SPE = 1, SPTIE = 1,
SPRIE = 1, and SPEIE = 1 Enable the required interrupts at No
Have the last of the data been
the same time. read?
Yes
Start error
End of initial settings processing
Yes
Repeat the transfer processing [6] Run the initialization processing again, etc.
Start of initialization in
slave mode
Set RSPI slave select polarity • Sets polarity of SSL0 input signal
register (SSLP)
End of initialization in
slave mode
Start processing
End of initial settings for transmission
Yes
Yes
End of
processing for
transmission
Start processing
End of initial settings for reception
Yes
Set SPCR2.SPIIE = 0 [2] Prohibit SPII interrupts. Read receive data from SPDR [4] [4] Access when the interrupt
processing routine is executed once
is to the number of frames set in
SPDCR.SPFC[1:0].
[3] Set the SPE bit to “enabled”.
Set SPCR.SPE = 1, SPTIE = 1,
SPRIE = 1, and SPEIE = 1 Enable the required interrupts at No
Have the last of the data been
the same time. read?
Yes
End of
processing for
reception
Start error
End of initial settings processing
Yes
Repeat the transfer processing [5] Run the initialization processing again, etc.
Command
pointer control
SPCMD0
SPCMD1
SPCMD2
SPCMD3
SPCMD4 CPHA SCKDEN SLDNEN SPNDEN
SPCMD5 CPOL
BRDV[1:0] SPCKD SSLND SPND
SPCMD6 SSLA[2:0]
SPCMD7 SSLKP
SPB[3:0]
LSBF
Figure 30.42 Procedure for Determining the Form of Serial Transmission in Master Mode
In this section, a frame is the combination of the data (SPDR) and the settings (SPCMDm).
Data
(SPDR) Frame
Data
+
Settings
Settings
(SPCMD)
Figure 30.44 shows the relationship between the command and the transmit and receive buffers in the sequence of
operations specified by the settings in Table 30.4.
SPTX0/SPRX0
Setting 1-1
SPCMD0
Only 1 frame
SPTX0/SPRX0 SPTX1/SPRX1
Setting 1-2
SPCMD0 SPCMD0
SPTX0/SPRX0 SPTX1/SPRX1
Setting 2-1
SPCMD0 SPCMD1
1st frame 2nd frame 3rd frame 4th frame 5th frame
1st frame 2nd frame 3rd frame 4th frame 5th frame 6th frame
1st frame 2nd frame 3rd frame 4th frame 5th frame 6th frame 7th frame
1st frame 2nd frame 3rd frame 4th frame 5th frame 6th frame 7th frame 8th frame
Figure 30.44 Correspondence between the RSPI Command Register and Transmit/Receive Buffers in
Sequence Operations
Start of initialization in
master mode
Set RSPI pin control • Sets MOSI signal value when transfer is in idle state.
register (SPPCR)
End of initialization in
master mode
Figure 30.45 Example of Initialization Flowchart in Master Mode (Clock Synchronous Operation)
Start of initialization in
slave mode
End of initialization in
slave mode
Figure 30.46 Example of Initialization Flowchart in Slave Mode (Clock Synchronous Operation)
Table 30.12 SPLP2 and SPLP Bit Settings and Received Data
SPPCR.SPLP2 Bit SPPCR.SPLP Bit Received Data
0 0 Input data from the MOSIA pin or MISOA pin
0 1 Reversed transmit data
1 0 Transmit data
1 1 Transmit data
Transmission
(MOSIA/MISOA) Shift register
Loopback
Loopback2
Normal
Reception
(MISOA/MOSIA)
Figure 30.47 Configuration of Shift Register I/O Paths in Loopback Mode (Master Mode)
Start of self-diagnosis of
parity circuit
No parity error
No parity error
(2) Overrun
The condition for this event signal being output in response to an overrun is completion of serial transfer while the
reception buffer contains data that have not been read and the value of the SPCR.TXMD bit is 0, in which case the OVRF
flag is set to 1.
Whether the operation is in master mode or slave mode, an event is not output if 0 is written to the SPCR.SPE bit in
transmission or the SPCR.SPE bit is cleared by the mode fault error.
31.1 Overview
Table 31.1 lists the specifications of the CRC calculator, and Figure 31.1 shows a block diagram of the CRC calculator.
Note 1. The circuit does not have functionality to divide data for calculation into a data-block size. Write data in 8-bit units.
Control signal
CRCCR
Internal peripheral bus 2
CRC code
CRCDIR generation
circuit
CRCDOR
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
CRCDIR is an 8-bit readable/writable register, to which the bytes to be CRC-operated are written.
CRCDOR is a 16-bit readable/writable register that contains the result of CRC calculation.
In general, the value will be 0 if there is no CRC error when the calculated CRC code matches the CRC code that
continues on, for verification, from the transferred data.
When an 8-bit CRC (X8 + X2 + X + 1 polynomial) is in use, the valid CRC code is obtained in the lower-order byte (b7
to b0). The higher-order byte (b15 to b8) is not updated.
31.3 Operation
The CRC calculator generates CRC codes for use in LSB-first or MSB-first transfer.
The following figures show examples in which the CRCCR.GPS[1:0] bits are set to 11b so the CRC code is calculated by
using a 16-bit CRC (with the polynomial X16 + X12 + X5 + 1), and the CRC code is calculated for the value “F0h”.
When an 8-bit CRC (with the polynomial X8 + X2 + X + 1) is in use, the valid bits of the CRC code are obtained in the
lower-order byte of CRCDOR.
Clear CRCDOR
6. Read CRCDOR
CRC code = 0000h no error
Clear CRCDOR
6. Read CRCDOR
CRC code = 000h no error
1. CRC code
After specifying the method for generation calculation, write data to CRCDIR in order of (1), (2), (3), and (4).
7 0
CRCDIR (1)
7 0
CRCDIR (2)
7 0
CRCDIR (3)
7 0
CRCDIR (4)
2. Transmission data
7 07 0 7 07 07 07 0
(H) (L) (4) (3) (2) (1) Output
approximation register
AVCC0
Successive
AVSS0
12-bit D/A A/D data register A/D control register
VREFH0
VREFL0
Power
generator Interrupt signal
Comparator (S12ADI0, GBADI)
(for self test)
+
AN015
Sample & hold -
circuit Event signal output to ELC
AN014
AN008
Analog multiplexer
AN007
AN006
AN005
AN004
AN003
AN002
AN001
AN000
Table 32.3 lists the input pins of the 12-bit A/D converter.
— — — — AD[11:0]
AD[11:0] — — — —
AD[13:0] — —
When A/D-converted value addition mode is selected, the AD[13:0] bits in ADDRy show the value added by the A/D-
converted value of the respective channels. In A/D-converted value addition mode, the setting of the ADRFMT bit in
ADCER becomes invalid and the format of the register becomes left-aligned.
The following minimum and maximum values apply to channels on which A/D-converted value addition mode is
selected.
— — — — AD[11:0]
AD[11:0] — — — —
AD[13:0] — —
When A/D-converted value addition mode is selected, the AD[13:0] bits in ADDBLDR show the value added by the
A/D-converted value of the respective channels. In A/D-converted value addition mode, the setting of the ADRFMT bit
in ADCER becomes invalid and the format of the register becomes left-aligned.
— — — — AD[11:0]
AD[11:0] — — — —
AD[13:0] — —
When A/D-converted value addition mode is selected, the AD[13:0] bits in ADOCDR show the value added by the A/D-
converted value of the internal reference voltage. In A/D-converted value addition mode, the setting of the ADRFMT bit
in ADCER becomes invalid and the format of the register becomes left-aligned.
DIAGST[1:0] — — AD[11:0]
AD[11:0] — — DIAGST[1:0]
Table 32.4 Relationship between DBLANS Bit Settings and Double Trigger Enabled Channels
DBLANS[4:0] Duplication Channel DBLANS[4:0] Duplication Channel
00000 AN000 01000 AN008
00001 AN001 01001 AN009
00010 AN002 01010 AN010
00011 AN003 01011 AN011
00100 AN004 01100 AN012
00101 AN005 01101 AN013
00110 AN006 01110 AN014
00111 AN007 01111 AN015
ANSA[15:0]
ADANSA selects analog input channels for A/D conversion from among AN000 to AN015. In group scan mode, group
A channels are to be selected.
ANSB[15:0]
ADANSB selects channels for A/D conversion in group B from among AN000 to AN015 in group scan mode. ADANSB
is not used in any other scan mode. The channels for conversion can be selected from among the channels other than
group A channels, which are selected by the ADANSA register or ADCSR.DBLANS[4:0] bits in double trigger mode.
The ANSB[0] bit corresponds to AN000 and the ANSB[15] bit corresponds to AN015. When A/D conversion of analog
inputs of the channels is to be performed, A/D conversion of the internal reference voltage should not be performed.
The ANSB[15:0] bits should be set while the ADST bit is 0.
ADS[15:0]
ADADS selects the channels 0 to 15 on which A/D conversion is performed successively two to four times and then
converted values are added (integrated).
Figure 32.2 shows a scanning operation sequence in which both the ADS[2] and ADS[6] bits are set to 1.
In continuous scan mode (ADCSR.ADCS = 10b), it is assumed that the addition count is set to 3 (ADADC.ADC[1:0] =
11b) and the channels AN000 to AN007 are selected (ADANSA.ANSA[15:0] = 00FFh). The conversion process begins
with AN000. The AN002 conversion is performed successively 4 times, and the added (integrated) value is returned to
the A/D data register 2. After that the AN003 conversion process is started. The AN006 conversion is performed
successively 4 times and the added (integrated) value is returned to the A/D data register 6. After conversion of AN007,
the conversion operation is once again performed in the same sequence from AN000.
For the channel for which the addition mode is not selected, the A/D data register format is determined by the ADRFMT
bit in ADCER (right-alignment or left-alignment).
Continuous
conversion count
3 times
AN002 AN006 AN002
1 time AN000 AN001 AN002 AN003 AN004 AN005 AN006 AN007 AN000 AN001 AN002 • • •
Conversion in progress
Figure 32.2 Scan Conversion Sequence with ADADC.ADC[1:0] = 11b, ADS[2] = 1, and ADS[6] = 1
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — ADC[1:0]
ADADC sets the addition count for the channels for which A/D-converted value addition mode is selected, and for A/D
conversion of the internal reference voltage.
voltage and the conversion result is stored into the self-diagnosis data register (ADRD). ADRD can then be read by
software to determine whether the conversion result falls within the normal range (normal) or not (abnormal). Self-
diagnosis is executed once at the beginning of each scan, and one of the three voltages is converted. The execution time
of self-diagnosis equals to the A/D conversion time of one channel. To execute self-diagnosis, A/D conversion of the
internal reference voltage should not be selected. If selected, self-diagnosis is not executed. When self-diagnosis is
selected in group scan mode, self-diagnosis is separately executed for group A and group B.
The DIAGM bit should be set while the ADST bit is 0.
For details on the format of the data registers, see section 32.2.1, A/D Data Registers y (ADDRy) (y = 0 to 15),
section 32.2.2, A/D Data Duplication Register (ADDBLDR), section 32.2.3, A/D Internal Reference Voltage
Data Register (ADOCDR), and section 32.2.4, A/D Self-Diagnosis Data Register (ADRD).
— — — — TRSA[3:0] — — — — TRSB[3:0]
Table 32.5 List of A/D Conversion Startup Sources Selected by TRSB[3:0] Bits
Module Source Remarks TRSB[3] TRSB[2] TRSB[1] TRSB[0]
MTU TRG0AN TRGA input capture/compare match from MTU0 0 0 0 1
TRG0BN TRGB input capture/compare match B from MTU0 0 0 1 0
TRGAN TRGA input capture/compare match or MTU4.TCNT 0 0 1 1
underflow (trough) in complementary PWM mode from
MTU0 to MTU4
TRG0EN TRGE compare match from MTU0 0 1 0 0
TRG0FN TRGF compare match from MTU0 0 1 0 1
TRG4AN MTU4.TADCORA and MTU4.TCNT compare match 0 1 1 0
(interrupt skipping function 1)
TRG4BN MTU4.TADCORB and MTU4.TCNT compare match 0 1 1 1
(interrupt skipping function 1)
TRG4ABN MTU4.TADCORA and MTU4.TCNT compare match and 1 0 0 0
MTU4.TADCORB and MTU4.TCNT compare match
(interrupt skipping function 1)
ELC ELC Trigger from ELC 1 0 0 1
Table 32.6 List of A/D Conversion Startup Sources Selected by TRSA[3:0] Bits
Module Source Remarks TRSA[3] TRSA[2] TRSA[1] TRSA[0]
ADC ADST Software trigger — — — —
External ADTRG0# A/D conversion start trigger pin 0 0 0 0
input
MTU TRG0AN TRGA input capture/compare match from MTU0 0 0 0 1
TRG0BN TRGB input capture/compare match B from MTU0 0 0 1 0
TRGAN TRGA input capture/compare match or MTU4.TCNT 0 0 1 1
underflow (trough) in complementary PWM mode from
MTU0 to MTU4
TRG0EN TRGE compare match from MTU0 0 1 0 0
TRG0FN TRGF compare match from MTU0 0 1 0 1
TRG4AN MTU4.TADCORA and MTU4.TCNT compare match 0 1 1 0
(interrupt skipping function 1)
TRG4BN MTU4.TADCORB and MTU4.TCNT compare match 0 1 1 1
(interrupt skipping function 1)
TRG4ABN MTU4.TADCORA and MTU4.TCNT compare match and 1 0 0 0
MTU4.TADCORB and MTU4.TCNT compare match
(interrupt skipping function 1)
ELC ELC Trigger from ELC 1 0 0 1
— — — — — — OCS — — — — — — — OCSAD —
OCSAD Bit (Internal Reference Voltage A/D Converted Value Addition Mode Select)
The OCSAD bit selects A/D conversion for the internal reference voltage. Setting the OCSAD bit to 1 performs A/D
conversion of the internal reference voltage successively 2 to 4 times that is set with the ADC[1:0] bits in ADADC and
returns the integrated value to the A/D internal reference voltage data register (ADOCDR). The OCSAD bit should be set
while the ADST bit in ADCSR is 0.
Address: ADSSTR0: 0008 9060h, ADSSTR1: 0008 9073h, ADSSTR2: 0008 9074h, ADSSTR3: 0008 9075h,
ADSSTR4: 0008 9076h, ADSSTR5: 0008 9077h, ADSSTR6: 0008 9078h, ADSSTR7: 0008 9079h,
ADSSTRL: 0008 9061h, ADSSTRO: 0008 9071h
b7 b6 b5 b4 b3 b2 b1 b0
SST[7:0]
b7 b6 b5 b4 b3 b2 b1 b0
— — — ADNDIS[4:0]
32.3 Operation
Channel 5 (AN005) Waiting for conversion A/D conversion 2 Waiting for conversion
Channel 6 (AN006) Waiting for conversion A/D conversion 3 Waiting for conversion
(2)
Stored
ADDR4 A/D conversion result 1
(2)
ADDR5 A/D conversion result 2
(2)
ADDR6 A/D conversion result 3
(3)
S12ADI0
Figure 32.3 Example of Operation in Single Scan Mode (Basic Operation: AN004 to AN006 Selected)
Channel 0 (AN000) Waiting for conversion A/D conversion 1 Waiting for conversion
Channel 8 (AN008) Waiting for conversion A/D conversion 2 Waiting for conversion
Stored (2)
ADRD Result of A/D conversion for self-diagnosis
Stored (3)
ADDR0 A/D conversion result 1
Stored (3)
ADDR8 A/D conversion result 2
(4)
S12ADI0
Interrupt generated
Figure 32.4 Example of Operation in Single Scan Mode (Basic Operation + Self-Diagnosis)
Internal reference voltage Waiting for conversion A/D conversion of internal reference voltage Waiting for conversion
Stored (2)
ADOCDR A/D conversion result of internal reference voltage
(2)
S12ADI0
Figure 32.5 Example of Operation in Single Scan Mode (Internal Reference Voltage Selected)
Trigger (TRG4ABN)
A/D conversion A/D conversion
performed once performed once
Set Set
A/D conversion
ADST started
(1) (4)
A/D conversion time (3) A/D conversion time (7)
Channel 3 (AN003) Waiting for A/D conversion 1 Waiting for conversion A/D conversion 2 Waiting for conversion
conversion
Stored (2)
ADDR3 A/D conversion result 1
Stored (5)
ADDBLDR A/D conversion result 2
(6)
S12ADI0
(6)
Interrupt generated
Note: • In the figure, AN003 is set to be duplicated and the TRG4ABN trigger is selected.
Figure 32.6 Example of Operation in Single Scan Mode (Double Trigger Mode Selected; AN003 Duplicated)
Channel 2 (AN002) Waiting for conversion A/D conversion 3 Waiting for conversion
(2) (2)
Stored Stored
ADDR0 A/D conversion result 1 A/D conversion result 4
(2)
ADDR1 A/D conversion result 2
(2)
ADDR2 A/D conversion result 3
(3)
S12ADI0
Interrupt generated
Figure 32.7 Example of Operation in Continuous Scan Mode (Basic Operation: AN000 to AN002 Selected)
Channel 2 (AN002) Waiting for conversion A/D conversion 2 Waiting for conversion
(4)
S12ADI0
Interrupt generated
Note 1. Data for A/D conversion 3 is ignored.
Figure 32.8 Example of Operation in Continuous Scan Mode (Basic Operation + Self-Diagnosis)
Timer count
Event B
Event A
Time
TRG4AN (1) Group A scanned (3)
(2)
TRG4BN Group B scanned
(4)
S12ADI0 interrupt
GBADI interrupt
Figure 32.9 Example of Operation in Group Scan Mode (Basic Operation: MTU Triggers Used)
Timer count
TRG4ABN event
TRG0AN event
Time
(3) (5)
TRG4ABN
Group A Group A
scanned scanned
(1) (4) (6)
TRG0AN
Group B scanned
S12ADI0 interrupt
(2)
GBADI interrupt
Figure 32.10 Example of Operation in Group Scan Mode with Double Trigger Mode (Basic Operation: MTU
Triggers Used)
The scan conversion time for the first cycle in continuous scan mode is tSCAN for single scan minus tED.
The scan conversion time for the second and subsequent cycles in continuous scan mode is fixed to (tDIS × n) + tDIAG +
(tCONV × n).
The disconnection detection assist processing time (tDIS) is the value set in the ADNDIS[3:0] bits.
The self-diagnosis A/D conversion processing time (tDIAG) is 30 states (fixed) + the value set in the ADSSTR0.SST[7:0]
bits.
The A/D conversion processing time (tCONV) is 30 states (fixed) + the value set in the ADSSTRn.SST[7:0] bits*3.
Note 1. When the disconnection detection assist function is not used, tDIS = 0.
Note 2. When the self-diagnosis function is not used, tDIAG = 0.
Note 3. Registers in Table 32.7.
Table 32.8 Scan Conversion Time (in Terms of PCLK and ADCLK Cycles)
Scan Conversion Time
Item Symbol Conditions (Cycles)
Start-of-scanning-delay time*1 tD MTU, ELC, or software trigger 2 PCLK + 4 ADCLK
External trigger 4 PCLK + 4 ADCLK
Disconnection detection assist tDIS Set by ADNDIS[3:0] bits (initial value 00h) 0 ADCLK
processing time
Self-diagnosis A/D conversion tDIAG Set by ADSSTR0.SST[7:0] bits (initial value 14h) 50 ADCLK
processing time*1
A/D conversion processing time*1 tCONV Set by ADSSTRn.SST[7:0] bits (initial value 14h) 50 ADCLK
End-of-scanning-delay time*1 tED — 1 PCLK + 3 ADCLK
Scan conversion time*2 tSCAN — 5 PCLK + (50n + 87) ADCLK
Note 1. For tD, tDIAG, tCONV, and tED, refer to Figure 32.11 and Figure 32.12.
Note 2. It is assumed that scan conversion is activated by the external trigger, disconnection detection assist function is deselected, self-
diagnosis A/D conversion is selected, and single scan mode is selected. n indicates the number of channels.
tSCAN
ADST bit
Figure 32.11 Scan Conversion Timing (Activated by Software, or Triggers from the MTU or ELC)
tSCAN
ADST bit
ADST
A/D conversion Sampling time Conversion time Sampling time Conversion time
Disconnection detection assisting time (0 to 15 ADCLK cycles) Disconnection detection assisting time (0 to 15 ADCLK cycles)
Figure 32.13 A/D Conversion with Disconnection Detection Assist Function Used
On
Precharge
Precharge control signal
Note 1. The conversion result with disconnection depends on the external circuit used; the circuit should be fully
evaluated before used for the system.
Off
Precharge
control signal
On
Discharge
control signal
Analog input
ANn Discharge
VREFL0
PCLK
4 states
Asynchronous trigger
32.3.10 Starting A/D Conversion with Synchronous Trigger from Peripheral Modules
The A/D conversion can be started by a synchronous trigger of the MTU or ELC. To start the A/D conversion by a
synchronous trigger, the ADCSR.TRGE bit should be set to 1, the ADCSR.EXTRG bit should be cleared to 0, and the
relevant source should be selected by ADSTRGR.TRSA[3:0] and TRSB[3:0] bits.
32.5.3 Notes on Event Reception from ELC during 12-bit A/D Conversion
When an event occurs during A/D conversion, it is invalid.
This LSI
Equivalent circuit of
A/D converter
Rs
Cs
Note 1. Value to achieve high-speed conversion of 1.56 μs. The value differs depending on the analog power supply voltage and analog
input pins to be used. For details, see section 38, Electrical Characteristics.
Note 2. Values when the voltage condition is AVCC0 2.7 V.
VCC
0.1 µF
VSS
AVCC0
0.1 µF
AVSS0
VREFH0
0.1 µF
VREFL0
AVCC0
VREFH0
Rin*2 0.1 µF
AN000 to AN015
*1 *1
AVSS0
0.1 µF
VREFL0
10 µF 0.01 µF
32.7.12 Port Setting when 12-bit A/D Converter Inputs are Used
If any one of port 4 or port E pins is used as an analog input pin for the 12-bit A/D converter, none of port 0 and port 4
output pins should be used. This is because an analog power supply is used for parts of the ports 0 and 4 circuits.
33. Comparator A
Comparator A compares a reference input voltage and an analog input voltage. Comparator A1 and comparator A2 are
independent of each other. Note that these comparators A1 and A2 share the voltage detection circuit with voltage
monitor 1 and voltage monitor 2. Either “comparator A1 and comparator A2” or “voltage monitor 1 and voltage monitor
2” can be selected to use the voltage detection circuit.
33.1 Overview
The comparison result of the reference input voltage and analog input voltage can be read by software. An input
voltage to the CVREFA pin can be selected as the reference input voltage. Also, the comparator A1 interrupt and
comparator A2 interrupt can be used.
Table 33.1 lists the comparator A specifications, Figure 33.1 shows a block diagram of comparator A, and Table
33.2 shows the pin configuration of comparator A.
= 10b
= 11b
LOCO 1/2 1/2 1/2
LVD1SR register
LVD1E LVD1CMPE
b1 LVD1RIE
LVD1RI
LVD1DFDIS = 0 LVD1MON
+ Digital LVD1RN = 0
filter
CMPA1 EXVCCINP1 = 1 Voltage monitor 1
- LVD1DFDIS = 1 Fixed
period LVD1RN = 1 reset signal
negation (Low is valid)
LVD1DET
Edge
selection b0
EXVREFINP1 = 1 circuit Voltage monitor 1/
comparator A1
Voltage detection 1 signal is non-maskable
driven high when LVD1E bit is interrupt signal
0 (disabled). LVD1IDTSEL[1:0]
LVD1IRQSEL Voltage monitor 1/
comparator A1
maskable interrupt
signal
LVD1/comparator A1
EXVCCINP1, EXVREFINP1, LVD1E: Bits in LVCMPCR ELC event
LVD1LVL[3:0]: Bits in LVDLVLR
LVD1DFDIS, LVD1FSAMP[1:0], LVD1CMPE, LVD1RIE, LVD1RI, LVD1RN: Bits in LVD1CR0
LVD1IDTSEL[1:0], LVD1IRQSEL: Bits in LVD1CR1
LVD1DET, LVD1MON: Bits in LVD1SR
= 10b
= 11b
LOCO 1/2 1/2 1/2
LVD2SR register
LVD2E LVD2CMPE
b1 LVD2RIE
LVD2RI
LVD2DFDIS = 0 LVD2MON
+ Digital LVD2RN = 0
CMPA2 filter
EXVCCINP2 = 1 Voltage monitor 2
- LVD2DFDIS = 1 Fixed
period LVD2RN = 1 reset signal
negation (Low is valid)
LVD2DET
Edge
selection b0
EXVREFINP2 = 1 circuit Voltage monitor 2/
CVREFA comparator A2
Voltage detection 1 signal is non-maskable
driven high when LVD2E bit is interrupt signal
0 (disabled). LVD2IDTSEL[1:0]
LVD2IRQSEL Voltage monitor 2/
comparator A2
maskable interrupt
signal
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — LVD1IR LVD1IDTSEL
QSEL [1:0]
Value after reset: 0 0 0 0 0 0 0 1
Note: • Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — LVD1M LVD1D
ON ET
Value after reset: 0 0 0 0 0 0 1 0
Note: • Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
Note 1. Only 0 can be written to this bit. After writing 0 to this bit, it takes two system clock cycles for the bit to be read as 0.
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — LVD2IR LVD2IDTSEL[1:
QSEL 0]
Value after reset: 0 0 0 0 0 0 0 1
Note: • Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — LVD2M LVD2D
ON ET
Value after reset: 0 0 0 0 0 0 1 0
Note: • Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
Note 1. Only 0 can be written to this bit. After writing 0 to this bit, it takes two system clock cycles for the bit to be read as 0.
b7 b6 b5 b4 b3 b2 b1 b0
Note: • Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
The EXVREFINP1, EXVCCINP1, EXVREFINP2, and EXVCCINP2 bits can only be modified when the LVD1E and
LVD2E bits are 0 (voltage detection circuit disabled)
b7 b6 b5 b4 b3 b2 b1 b0
Note: • Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
LVD1DFDIS Bit (Voltage Monitoring 1/Comparator A1 Digital Filter Disable Mode Select)
Set the LOCOCR.LCSTP bit to 0 (the LOCO operates) if the LVD1DFDIS bit is to be set to 0 (digital filter circuit
enabled).
Set the LVD1DFDIS bit to 1 (digital filter circuit disabled) when using a voltage monitoring 1 circuit in software standby
mode.
b7 b6 b5 b4 b3 b2 b1 b0
Note: • Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
LVD2DFDIS Bit (Voltage Monitoring 2/Comparator A2 Digital Filter Disable Mode Select)
Set the LOCOCR.LCSTP bit to 0 (the LOCO operates) if the LVD2DFDIS bit is to be set to 0 (digital filter circuit
enabled).
Set the LVD2DFDIS bit to 1 (digital filter circuit disabled) when using a voltage monitoring 2 circuit in software standby
mode.
33.4 Operation
Comparator A1 and comparator A2 operate independently.
The comparison result of the reference input voltage and analog input voltage can be read by software. An input voltage
to the CVREFA pin can be used as the reference input voltage. The comparator A1 interrupt and the comparator A2
interrupt can be used, and non-maskable or maskable can be selected for each interrupt type.
33.4.1 Comparator A1
Table 33.5 shows the procedure for setting bits related to the comparator A1 interrupt/ELC, Table 33.6 shows the
procedures for stopping bits related to the comparator A1 interrupt/ELC, and Figure 33.2 shows an operating
example of comparator A1.
Table 33.5 Procedures for Setting Bits Related to the Comparator A1 Interrupt/ELC
Step No. When Using Digital Filter When Using No Digital Filter
1 *2 Set the LVCMPCR.EXVREFINP1 bit to 1 (CVREFA pin input voltage).
Set the LVCMPCR.EXVCCINP1 bit to 1 (CMPA1 pin input voltage).
2 *1 Select the sampling clock for the digital filter by setting the ―
LVD1CR0.LVD1FSAMP[1:0] bits.
3 *1, *2 Set the LVD1CR0.LVD1RI bit to 0 (comparator A1 interrupt).
4 Set the LVD1CR1.LVD1IDTSEL[1:0] bits to select the interrupt request timing.
Set the LVD1CR1.LVD1IRQSEL bit to select the interrupt type.
5 *2 Set the LVCMPCR.LVD1E bit to 1 (enabling the circuit for comparator A1).
6 *2 Wait for at least td(E-A) or longer.
7 Set the LVD1CR0.LVD1CMPE bit to 1 (enabling output of the results of comparison by the comparator A1 circuit).
8 Wait for at least one cycle of the LOCO. ―
9 Clear the LVD1CR0.LVD1DFDIS bit to 0 (enabling the ―
digital filter).
10 Wait for at least 2n + 3 cycles of the LOCO (where n = 1, 2, ―
4, 8, and the sampling clock for the digital filter is the
LOCO frequency-divided by n).
11 Clear the LVD1SR.LVD1DET bit to 0.
12 Set the LVD1CR0.LVD1RIE bit to 1 (enable comparator A1 interrupts).
Events to the ELC are always output regardless of the setting of this bit.
Note 1. Executing steps 2 and 3 at the same time (with a single instruction) creates no problems.
Note 2. Steps 1, 3, 5, and 6 are not required if operation is with the setting to select the comparator A1 interrupt (LVD1CR0.LVD1RI = 0)
and operation can be restarted by simply changing the settings of the LVD1CR0.LVD1DFDIS and LVD1FSAMP bits or
LVD1CR1.LVD1IRQSEL and LVD1IDTSEL bits after operation is stopped or if restarting is in a case where the settings related
to the comparator A1 circuit were not changed after operation was stopped.
Table 33.6 Procedures for Stopping Bits Related to the Comparator A1 Interrupt/ELC
Step No.
1 Set the LVD1CR0.LVD1RIE bit to 0 (disable comparator A1 interrupts).
2 Clear the LVD1CR0.LVD1CMPE bit to 0 (comparator A1 circuit comparison result output is disabled).
3 *1 Clear the LVCMPCR.LVD1E bit to 0 (comparator A1 circuit disabled).
4 Modify settings of bits related to the voltage detection circuit registers other than LVCMPCR.LVD1E,
LVD1CR0.LVD1RIE, and LVD1CR0.LVD1CMPE.
Note 1. Step 3 is not required if operation is with the setting to select the comparator A1 interrupt (LVD1CR0.LVD1RI = 0) and operation
can be restarted by simply changing the settings of the LVD1CR0.LVD1DFDIS and LVD1FSAMP bits or
LVD1CR1.LVD1IRQSEL and LVD1IDTSEL bits after operation is stopped or if restarting is in a case where the settings related
to the comparator A1 circuit were not changed after operation was stopped.
CVREFA
CMPA1
1n + 2 to 2n + 3 1n + 2 to 2n + 3
cycles of the LOCO cycles of the LOCO
LVD1DFDIS bit is set to 0 LVD1DET bit
(digital filter enabled) and
LVD1IDTSEL[1:0] bits are set Set to 0 by program.
to 10b (when drop or rise is
detected) Voltage monitoring 1/
comparator A1 interrupt
request
Set to 0 by program.
LVD1DFDIS bit is set to 0
LVD1DET bit
(digital filter enabled),
LVD1IDTSEL[1:0] bits are set
to 00b (when rise is detected). Voltage monitoring 1/
comparator A1 interrupt
request
Set to 0 by program.
LVD1DFDIS bit is set to 0 LVD1DET bit
(digital filter enabled),
LVD1IDTSEL[1:0] bits are set
to 01b (when drop is detected). Voltage monitoring 1/
comparator A1 interrupt
request
Set to 0 by program.
LVD1DFDIS bit is set to 1 LVD1DET bit
(digital filter disabled),
LVD1IDTSEL[1:0] bits are set
Voltage monitoring 1/
to 00b (when rise is detected).
comparator A1 interrupt
request
Set to 0 by program.
LVD1DFDIS bit is set to 1 LVD1DET bit
(digital filter disabled),
LVD1IDTSEL[1:0] bits are set Voltage monitoring 1/
to 01b (when drop is detected). comparator A1 interrupt
request
Note 1. When the voltage monitoring 0 reset is not in use, VCC VCC min.
33.4.2 Comparator A2
Table 33.7 shows the procedure for setting bits related to the comparator A2 interrupt, Table 33.8 shows the
procedures for stopping bits related to the comparator A2 interrupt, and Figure 33.3 shows an operating example
of comparator A2.
Table 33.7 Procedures for Setting Bits Related to the Comparator A2 Interrupt
Step No. When Using Digital Filter When Using No Digital Filter
1 *2 Set the LVCMPCR.EXVREFINP2 bit to 1 (CVREFA pin input voltage).
Set the LVCMPCR.EXVCCINP2 bit to 1 (CMPA2 pin input voltage).
2 *1 Select the sampling clock for the digital filter by setting the ―
LVD2CR0.LVD2FSAMP[1:0] bits.
3 *1, *2 Set the LVD2CR0.LVD2RI bit to 0 (comparator A2 interrupt).
4 Set the LVD2CR1.LVD2IDTSEL[1:0] bits to select the interrupt request timing.
Set the LVD2CR1.LVD2IRQSEL bit to select the interrupt type.
5 *2 Set the LVCMPCR.LVD2E bit to 1 (enabling the circuit for comparator A2).
6 *2 Wait for at least td(E-A) or longer.
7 Set the LVD2CR0.LVD2CMPE bit to 1 (enabling output of the results of comparison by the comparator A2 circuit).
8 Wait for at least one cycle of the LOCO. ―
9 Clear the LVD2CR0.LVD2DFDIS bit to 0 (enabling the ―
digital filter).
10 Wait for at least 2n + 3 cycles of the LOCO (where n = 1, 2, ―
4, 8, and the sampling clock for the digital filter is the
LOCO frequency-divided by n).
11 Clear the LVD2SR.LVD2DET bit to 0.
12 Set the LVD1CR0.LVD1RIE bit to 1 (enable comparator A2 interrupts).
Note 1. Executing steps 2 and 3 at the same time (with a single instruction) creates no problems.
Note 2. Steps 1, 3, 5, and 6 are not required if operation is with the setting to select the comparator A2 interrupt (LVD2CR0.LVD2RI = 0)
and operation can be restarted by simply changing the settings of the LVD2CR0.LVD2DFDIS and LVD2FSAMP bits or
LVD2CR1.LVD2IRQSEL and LVD2IDTSEL bits after operation is stopped or if restarting is in a case where the settings related
to the comparator A2 circuit were not changed after operation was stopped.
Table 33.8 Procedures for Stopping Bits Related to the Comparator A2 Interrupt
Step No.
1 Set the LVD2CR0.LVD2RIE bit to 0 (disable comparator A2 interrupts).
2 Clear the LVD2CR0.LVD2CMPE bit to 0 (comparator A2 circuit comparison result output is disabled).
3 *1 Clear the LVCMPCR.LVD2E bit to 0 (comparator A2 circuit disabled).
4 Modify settings of bits related to the voltage detection circuit registers other than LVCMPCR.LVD2E,
LVD2CR0.LVD2RIE, and LVD2CR0.LVD2CMPE.
Note 1. Step 3 is not required if operation is with the setting to select the comparator A2 interrupt (LVD2CR0.LVD2RI = 0) and operation
can be restarted by simply changing the settings of the LVD2CR0.LVD2DFDIS and LVD2FSAMP bits or
LVD2CR1.LVD2IRQSEL and LVD2IDTSEL bits after operation is stopped or if restarting is in a case where the settings related
to the comparator A2 circuit were not changed after operation was stopped.
CVREFA
CMPA2
1n + 2 to 2n + 3 1n + 2 to 2n + 3
cycles of the LOCO cycles of the LOCO
LVD2DFDIS bit is set to 0 LVD2DET bit
(digital filter enabled) and
LVD2IDTSEL[1:0] bits are set Set to 0 by program.
to 10b (when drop or rise is
detected) Voltage monitoring 2/
comparator A2 interrupt
request
Set to 0 by program.
LVD2DFDIS bit is set to 0
LVD2DET bit
(digital filter enabled),
LVD2IDTSEL[1:0] bits are set
to 00b (when rise is detected). Voltage monitoring 2/
comparator A2 interrupt
request
Set to 0 by program.
LVD2DFDIS bit is set to 0 LVD2DET bit
(digital filter enabled),
LVD2IDTSEL[1:0] bits are set
to 01b (when drop is detected). Voltage monitoring 2/
comparator A2 interrupt
request
Set to 0 by program.
LVD2DFDIS bit is set to 1 LVD2DET bit
(digital filter disabled),
LVD2IDTSEL[1:0] bits are set
Voltage monitoring 2/
to 00b (when rise is detected).
comparator A2 interrupt
request
Set to 0 by program.
LVD2DFDIS bit is set to 1 LVD2DET bit
(digital filter disabled),
LVD2IDTSEL[1:0] bits are set Voltage monitoring 2/
to 01b (when drop is detected). comparator A2 interrupt
request
Event signal
output
operation circuit
Operation Interrupt
circuit control circuit
DODSR
OMS[1:0] DOPCIE
DOCR
b7 b6 b5 b4 b3 b2 b1 b0
DODIR is a 16-bit readable/writable register in which 16-bit data for use in the operations are stored.
DODSR is a 16-bit readable/writable register in which 16-bit data for use as a reference in data comparison mode are
stored. This register also stores the results of operations in data addition and data subtraction modes.
34.3 Operation
OMS[1:0] in
DOCR xxb 00b
Writing 1 to
DOPCFCL in DOCR
DOPCF in 1
DOCR 0
OMS[1:0] in
DOCR xxb 01b
Writing 1 to DOPCFCL in
DOCR
DOPCF in 1
DOCR 0
OMS[1:0] in
DOCR xxb 10b
Writing 1 to DOPCFCL
in DOCR
DOPCF in 1
DOCR 0
35. RAM
The RX220 Group has an on-chip high-speed static RAM.
35.1 Overview
Table 35.1 lists the specifications of the RAM.
Note 1. Selectable by the RAME bit in SYSCR1. For details on SYSCR1, see section 3.2.3, System Control Register 1 (SYSCR1).
Note 2. The capacity of RAM differs depending on the products.
RAM Capacity RAM Address
16 Kbytes RAM0: 0000 0000h to 0000 3FFFh
8 Kbytes RAM0: 0000 0000h to 0000 1FFFh
4 Kbytes RAM0: 0000 0000h to 0000 0FFFh
35.2 Operation
Stopping supply of the clock signal places the RAM in the module stop state. The RAM operates after initialization by a
reset.
The RAM is not accessible in the module stop state. Do not allow transitions to the module stop state while access to
RAM is in progress.
For details on the MSTPCRC register, see section 11, Low Power Consumption.
36.1 Overview
Table 36.1 lists the specifications of the ROM, Table 36.2 lists the correspondence between ROM capacity and ROM
addresses, and Figure 36.1 shows a block diagram of the ROM, E2 DataFlash, and related modules.
CPU
FCU
ROM area
FMODR User area: 256 Kbytes max.
Memory bus 2
FASTAT User boot area: 16 Kbytes
FAEINT
Module internal bus
DFLRE0
DFLWE0
FSTATR0
FIFERR
FSTATR1
FENTRYR
FRDYI
FRESETR
FCMDR
FRDYIE
FCPSR
DFLBCCNT E2 DataFlash area
DFLBCSTAT
PCKAR
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — FLWE[1:0]
FWEPROR is initialized by a reset due to the signal on the RES# pin, by transitions to software standby mode and by the
power supply voltage falling below the threshold for detection.
b7 b6 b5 b4 b3 b2 b1 b0
— — — FRDM — — — —
D
Value after reset: 0 0 0 0 0 0 0 0
b7 b6 b5 b4 b3 b2 b1 b0
When any bit from among the DFLWPE, DFLRPE, DFLAE, and ROMAE bits in FASTAT is set to 1, the
FSTATR0.ILGLERR bit is set to 1, which places the FCU in the command-locked state (see section 36.8.2,
Command-Locked State). To clear the command-locked state, a status register clear command must be issued to the
FCU after setting FASTAT to 10h.
[Setting condition]
After the FCU detects an error and enters the command-locked state
[Clearing condition]
After the FCU issues a status register clear command under conditions where FASTAT is set to 10h
[Setting conditions]
Read access to a ROM programming/erasure address when the FCU is in ROM P/E normal mode
ROM programming/erasure address ranges
ROM
Capacity FENTRY0 bit is 1
32 Kbytes 00FF 8000h to 00FF FFFFh
64 Kbytes 00FF 0000h to 00FF FFFFh
128 Kbytes 00FE 0000h to 00FF FFFFh
256 Kbytes 00FC 0000h to 00FF FFFFh
Read access to a ROM-reading address while FENTRYR has placed the ROM in ROM P/E mode
ROM
Capacity ROM programming/erasure address ranges
32 Kbytes FFFF 8000h to FFFF FFFFh
64 Kbytes FFFF 0000h to FFFF FFFFh
128 Kbytes FFFE 0000h to FFFF FFFFh
256 Kbytes FFFC 0000h to FFFF FFFFh
[Clearing condition]
When 0 is written after reading 1
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
[Setting condition]
The FCU has initiated a write suspend command.
[Clearing condition]
The FCU has accepted a resume command.
[Setting condition]
The FCU has initiated an erasure suspend command.
[Clearing condition]
The FCU has accepted a resume command.
[Setting condition]
After starting programming/erasure process, the FCU enters a state in which P/E suspend commands can be
received.
[Clearing conditions]
The FCU has accepted a P/E suspend command.
During programming/erasure process, the FCU enters the command-locked state.
[Setting conditions]
An error occurs during programming.
A programming command is issued to areas protected by a lock bit.
[Clearing condition]
After the FCU processes a status register clear command
[Setting conditions]
An error occurs during erasure.
A block erase command is issued to areas protected by a lock bit.
[Clearing condition]
After the FCU processes a status register clear command
[Setting conditions]
The FCU detects an illegal command.
The FCU detects an illegal ROM/E2 DataFlash access
(one of the ROMAE, DFLAE, DFLRPE, and DFLWPE bits in FASTAT is 1).
The setting of FENTRYR is invalid.
[Clearing condition]
After the FCU processes a status register clear command under conditions where FASTAT is set to 10h
b7 b6 b5 b4 b3 b2 b1 b0
FCUER — — FLOCK — — — —
R ST
Value after reset: 0 0 0 0 0 0 0 0
b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — — FRDYI
E
Value after reset: 0 0 0 0 0 0 0 0
To place the ROM/E2 DataFlash in ROM P/E mode so that the FCU can accept commands, either the FENTRYD or
FENTRY0 bit must be set to 1. Note that if more than one of these bits are set to 1, the FSTATR0.ILGLERR bit is set to
1 and the FCU enters the command-locked state.
After writing to the FENTRYR to initiate a transition to ROM-reading mode, read the register and confirm that it actually
holds the new setting before reading the ROM.
FENTRYR is initialized by a reset, or when the FRESETR.FRESET bit is set to 1.
FPKEY[7:0] — — — — — — — FPROT
CN
Value after reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[Setting condition]
55h is written to the FPKEY[7:0] bits and 1 is written to the FPROTCN bit in word access when the value of
FENTRYR is other than 0000h.
[Clearing conditions]
Data is written in byte access.
Data is written in word access when the FPKEY[7:0] bits are other than 55h.
55h is written to the FPKEY[7:0] bits and 0 is written to the FPROTCN bit in word access.
The value of FENTRYR is 0000h.
FRKEY[7:0] — — — — — — — FRESE
T
Value after reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CMDR[7:0] PCMDR[7:0]
— — — — — — — — — — — — — — — ESUSP
MD
Value after reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
— — — — — — — — PEERRST[7:0]
— — — — — — — — PCKA[7:0]
Note: • When the PCKA[7:0] bits are set to values outside the range from 4 to 32 MHz, do not issue a programming
command to the ROM/E2 DataFlash.
Note: • When the PCKA[7:0] bits are set to a frequency that is different from the FCLK, the data of the ROM/E2
DataFlash may be damaged.
Note: • Please note that the programming time depends on the frequency to some extent even if the PCKA[7:0] bits are
used.
When
the user
User area area
Address FFFE 0000h Address 00FE 0000h capacity
(256 Kbytes) is 256
When Kbytes
the user
When area
Address FFFF 0000h Address 00FF 0000h capacity
When the user
the user area is 128
Address FFFF 8000h Address 00FF 8000h Kbytes
area capacity
capacity is 64
Address FFFF FFFFh Address 00FF FFFFh is 32 Kbytes
Kbytes
For reading
Address FF7F C000h
User boot area
(16 Kbytes)
Address FF7F FFFFh
User area
Address FFFC 0000h Erasure block
EB127
User area
2 Kbytes
× 128 blocks Address FFFE 0000h Erasure block
EB63
2 Kbytes
× 64 blocks
User area
Address FFFF 0000h Erasure block User area Erasure block
2 Kbytes
× 32 blocks EB31 Address FFFF 8000h EB15
2 Kbytes × 16 blocks
Address FFFF FFFFh EB00 Address FFFF FFFFh EB00
64-Kbyte ROM 32-Kbyte ROM
Note 1. The entire ROM may be erased at the time of booting up. Specified blocks can subsequently be erased. For details, refer to
section 36.10.4, ID Code Protection (Boot Mode).
Programming and erasure of the user boot area are only possible in boot mode.
In boot mode, a host is able to program, erase, or read the user area, user boot area, or data area via an SCI.
In boot mode, RAM is employed for the boot program. For this reason, preserving the contents of RAM is not
possible in this case.
In user boot mode, booting up from the user boot area and then programming and reading of the user area and data
area via a desired interface become possible (after booting up from the boot area).
FENTRYR = AA80h
ROM/E2 DataFlash
E2 DataFlash P/E mode
read mode
FENTRYR = AA00h
FENTRYR = AA01h
FENTRYR = AA00h
(B)
ROM P/E normal ROM status read
mode mode
(A)
(A) (C)
(C) (B)
ROM lock bit read
mode
Figure 36.4 Mode Transitions of the FCU (Associated with the ROM)
The lock bit read 2 command is also used as the blank check command for the E2 DataFlash memory. That is, when a
lock bit read 2 command is issued for the E2 DataFlash, blank checking is executed for the E2 DataFlash memory (see
section 37, E2 DataFlash Memory (Flash Memory for Data Storage)).
Commands for the FCU are issued by write access to addresses within the range for ROM programming and erasure.
Table 36.6 lists the formats of the FCU commands. Write access as listed in Table 36.6 and in accordance with certain
conditions causes the FCU to execute processing for the corresponding command.
For details on the conditions for the acceptance of the individual FCU commands, see section 36.6.3, Connections
between FCU Modes and Commands. For how to use the FCU commands, see section 36.6.4, FCU Command
Usage.
Address
Address
Address
Address
Address
Address
Data
Data
Data
Data
Data
Data
Data
Command
P/E normal mode transition 1 RA FFh — — — — — — — — — — — —
Status read mode transition 1 RA 70h — — — — — — — — — — — —
Lock bit read mode transition 1 RA 71h — — — — — — — — — — — —
(lock bit read 1)
Peripheral clock notification 6 RA E9h RA 03h WA 0F0Fh RA 0F0Fh RA D0h — — — —
Programming 4 RA E8h RA 01h WA WDn — — — — — — RA D0h
(2-byte programming; N = 1)
Programming 7 RA E8h RA 04h WA WDn RA WDn RA WDn — — RA D0h
(8-byte programming; N = 4)
Programming 67 RA E8h RA 40h WA WDn RA WDn RA WDn RA WDn RA D0h
(128-byte programming; N = 64)
Block erase 2 RA 20h BA D0h — — — — — — — — — —
P/E suspend 1 RA B0h — — — — — — — — — — — —
P/E resume 1 RA D0h — — — — — — — — — — — —
Status register clear 1 RA 50h — — — — — — — — — — — —
Lock bit read 2 2 RA 71h BA D0h — — — — — — — — — —
Lock bit programming 2 RA 77h BA D0h — — — — — — — — — —
Table 36.7 Acceptable Commands and the State and Mode (ROM P/E Mode) of the FCU
P/E Normal Lock-Bit Read
Mode Status Read Mode Mode
Programming during Erasure Suspended State
Programming Suspended
Programming Suspended
Programming or Erasure
Programming or Erasure
Processing to Suspend
Erasure Suspended
Erasure Suspended
Erasure Suspended
Other State
Other State
Other State
FSTATR0.FRDY bit 1 1 1 0 0 0 0 1 1 0 1 1 1 1 1
FSTATR0.SUSRDY bit 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
FSTATR0.ERSSPD bit 0 1 0 0 1 0/1 0 0 1 0/1 0/1 0 0 1 0
FSTATR0.PRGSPD bit 1 0 0 0 0 0/1 0 1 0 0/1 0/1 0 1 0 0
FASTAT.CMDLK bit 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0
Normal mode transition A A A × × × × A A × × A A A A
Status read transition A A A × × × × A A × × A A A A
Lock-bit read transition (lock bit read 1) A A A × × × × A A × × A A A A
Peripheral clock notification × × A × × × × × × × × A × × A
Programming × * A × × × × × * × × A × * A
Block erase × × A × × × × × × × × A × × A
P/E suspend × × × A × × × × × × × × × × ×
P/E resume A A × × × × × A A × × × A A ×
Status register clear A A A × × × × A A × A A A A A
Lock bit read 2 A A A × × × × A A × × A A A A
Lock bit programming × * A × × × × × * × × A × * A
A: Acceptable
*: Only programming is acceptable for blocks other than the block where erasure was suspended
×: Not acceptable
Start
End
Start
Yes
FCU
ILGLERR bit check initialization
1
0
FRESETR.FRESET = 1
Read FASTAT
writing
ILGLERR = 0
ERSERR = 0
Wait
PRGERR = 0 10h
(tFCUR)*2
Yes
No
FRESETR.FRESET = 0
Write 10h to FASTAT
writing
Write AA00h to
FENTRYR
Read FENTRYR
0000h
No
Yes
Write 02h to
FWEPROR
End
Note 1. tE2K: Erasure time for a 2-Kbyte erasure block (see section 38, Electrical Characteristics)
Note 2. tFCUR: Reset pulse width during programming/erasure (see section 38, Electrical Characteristics)
Start
When the ILGLERR bit is 1, the normal mode transition command is not
FSTATR0 check accepted by the FCU.
End
Start
Write 70h to the address for ROM Transition to ROM status read mode
programming and erasure in bytes
End
Figure 36.8 Procedure for Transition to ROM Status Read Mode and the Status Checking
Start
Check the FSTATR0.ILGLERR bit Check the transition to ROM lock bit read mode
End
Figure 36.9 Procedure for Transition to ROM Lock-Bit Read Mode and Lock-Bit Reading
Start
No error
Issue a peripheral clock Issued only one time after a peripheral clock is set.
notification command For details, see section, “Using the Peripheral Clock Notification Command”.
No error
Error
Error check
No error
Check the
execution result of NG
the FCU
command*2
OK
End
Note 1. Selected among the programming, block erase, lock bit programming, and lock bit read 2 commands.
Note 2. To check the result of programming/erasure processing, enter ROM read mode and read data from the ROM
(see section, “Switching to ROM Read Mode”).
Figure 36.10 Simple Flowchart of the Procedure for Programming and Erasure
Start
Set PCKAR to
frequency of FlashIF clock (FCLK)
n=1
n = 3?
No
Yes
Timeout
FRDY bit check
0 tPCKA*1 No
1 Yes
FCU initialization
FRESETR.FRESET = 1
writing
Wait
ILGLERR bit check
(tFCUR)*2
FRESETR.FRESET = 0
writing
End
(4) Programming
The programming command is used to write data to the ROM.
In the first cycle of the programming command, the value E8h is written as a byte to the address range for programming
and erasure of the ROM. In the second cycle, the values, 01h (for 2-byte programming), 04h (for 8-byte programming),
or 40h (for 128-byte programming) are written to the same address range. In the third cycle, write the actual data to be
programmed, as a word unit, to the start address of the target area for programming.
In the case of 128-byte programming, 128 bytes (64 words) of data are written to the ROM in the third to the 66th cycles,
divided into 64 rounds. The start address of 128 bytes for programming is specified in the third cycle. The address range
specified at this time must be an integral multiple of 128. The address range specified in the fourth to the 66th cycles
does not need to be the address range for actual programming.
In the case of 8-byte programming, 8 bytes (4 words) of data are written to the ROM in the third to the sixth cycles,
divided into four rounds. The start address of 8 bytes for programming is specified in the third cycle. The address range
specified at this time must be an integral multiple of 8. The address range specified in the fourth to the sixth cycles does
not need to be the address range for actual programming.
In the case of 2-byte programming, the address range and data for programming are specified in the third cycle. The
address range must be an even number.
Once the value D0h has been written as a byte to the address range for programming and erasure of the ROM in the 67th
cycle, the FCU begins the actual process of programming the ROM. The FSTATR0.FRDY bit can be used to check
whether or not the programming has been completed.
Addresses that can be used in the first to 67th cycles differ according to the setting of the FENTRYR.FENTRY0 bit.
Ensure that the addresses suit the setting of FENTRYR.FENTRY0 bit. If issuing of the command is attempted with an
erroneous combination of the setting of the FENTRYR.FENTRY0 bit and the specified addresses, the FCU will detect
the error and enter the command-blocked state (see section 36.8.2, Command-Locked State).
In cases where the target range in the third to 66th cycles includes addresses that do not require programming, use FFFFh
as the data for programming to those addresses. To execute programming with lock bit protection disabled, proceed with
programming after setting the FPROTR.FPROTCN bit to 1.
Start
n=1
n=N
No
Yes
Timeout
FRDY bit check
0 (tP128 x 1.1)*1 No
1 Yes
FCU initialization
FRESETR.FRESET = 1
writing
Wait
ILGLERR bit and PRGERR bit check
(tFCUR)*2
FRESETR.FRESET = 0
writing
End
Note 1. tP128: Programming time for 128-byte data (see section 38, Electrical Characteristics)
Note 2. tFCUR: Reset pulse width during programming/erasure (see section 38, Electrical Characteristics)
(5) Erasure
To erase data from the ROM, use the block erase command.
Write 20h to the ROM programming/erasure address in byte access in the first cycle of the block erase command. When
D0h is written to an arbitrary address in a target erasure block in byte access in the second cycle, the FCU starts the
erasure processing for the ROM. Whether erasure is completed can be checked with the FSTATR0.FRDY bit. Reading
the erased ROM by the CPU returns FFFF FFFFh in 32 bits.
To execute an erasure with lock bit protection disabled, set the FPROTR.FPROTCN bit before erasure.
Start
Write D0h to arbitrary address in Use the address for ROM programming and erasure
erasure block in bytes (Do not use a read address)
Timeout
FRDY bit check
0 (tE2K x 1.1)*1 No
1 Yes
FCU initialization
FRESETR.FRESET = 1
writing
Wait
ILGLERR bit and ERSERR bit check
(tFCUR)*2
FRESETR.FRESET = 0
writing
End
Note 1. tE2K: Erasure time for a 2-Kbyte erasure block (see section 38, Electrical Characteristics)
Note 2. tFCUR: Reset pulse width during programming/erasure (see section 38, Electrical Characteristics)
Start
Write D0h to arbitrary address in Use the address for ROM programming and erasure
erasure block in bytes (Do not use a read address)
Timeout
FRDY bit check
0 (tP128 x 1.1)*1 No
1 Yes
FCU initialization
FRESETR.FRESET = 1
writing
FRESETR.FRESET = 0
writing
End
Note 1. tP128: Programming time for 128-byte data (see section 38, Electrical Characteristics)
Note 2. tFCUR: Reset pulse width during programming/erasure (see section 38, Electrical Characteristics)
Start
Timeout
FRDY bit check
0 (10 µs)
No
1 Yes
FCU initialization
FRESETR.FRESET = 1
writing
FRESETR.FRESET = 0
FLOCKST bit check
writing
End
Note 1. tFCUR: Reset pulse width during programming/erasure (see section 38, Electrical Characteristics)
Figure 36.15 Procedure for Reading Lock Bit in Register Read Mode
Start
0
Read FASTAT
10h
Yes
No
End
Start
ILGLERR, ERSERR,
PRGERR, FCUERR = 1
Error bit check
ILGLERR = 0
ERSERR = 0
PRGERR = 0
FCUERR = 0
0
SUSRDY bit check
FCUERR = 0
FCUERR bit check
1
1 Timeout No
10h
(tSEED x 1.1)*1 Yes
Yes No
FCU initialization
Write 10h to FASTAT
FRESETR.FRESET = 1
writing
Wait
(tFCUR)*2 Issue a status register
ERSSPD bit and PRGSPD bit clear command
check
FRESETR.FRESET = 0
writing
End
Start
Timeout
FRDY bit check
(tE2K x 1.1)*1
0 No
1 Yes
FCU initialization
FRESETR.FRESET = 1
writing
FRESETR.FRESET = 0
writing
End
Note 1. tE2K: Erasure time for a 2-Kbyte erasure block (see section 38, Electrical Characteristics)
Note 2. tFCUR: Reset pulse width during programming/erasure (see section 38, Electrical Characteristics)
Note 1. Programming/erasure is performed by generating multiple pulses for a single programming/erasure command.
FCU command E S R S R S R S
FRDY bit
SUSRDY bit
ERSSPD bit
Erasure pulse
FCU command E S R S
FRDY bit
SUSRDY bit
ERSSPD bit
Erasure pulse
36.8 Protection
Protection against programming/erasure for the ROM includes software protection and command-locked state.
Table 36.8 Errors that Lead to the Command-Locked State (Types Dedicated to ROM and Types Common to
ROM and E2 DataFlash)
ILGLERR
PRGERR
ERSERR
FCUERR
ROMAE
Type Description
FENTRYR setting More than one bit is set to 1 among the FENTRYD and FENTRY0 bits in FENTRYR 1 0 0 0 0
error
The FENTRYR setting at suspension disagrees with that at resumption 1 0 0 0 0
Illegal command error Undefined code is specified in the first cycle of an FCU command 1 0 0 0 0
Other than D0h is specified in the last cycle of a multi-cycle FCU command 1 0 0 0 0
The peripheral clock is set to other than 1 to 100 MHz in PCKAR 1 0 0 0 0
(an error is not detected if the setting is from 1 to 4 MHz or from 32 to 100 MHz)
A command other than the suspend command is issued during programming/erasure 1 0 0 0 0
A suspend command is issued during processing other than programming/erasure 1 0 0 0 0
A suspend command is issued in the suspended state 1 0 0 0 0
A resume command is issued in other than the suspended state 1 0 0 0 0
A programming/erasure-related command (programming/lock bit programming/block 1 0 0 0 0
erase) is issued in the programming suspended state
A block erase command is issued in the erasure suspended state 1 0 0 0 0
A programming or lock bit programming command is issued to an erasure suspend 1 0 0 0 0
target area in the erasure suspended state
Other than 01h, 04h, or 40h is specified in the second cycle of a programming 1 0 0 0 0
command
A command is issued in the command-locked state 1 0/1 0/1 0/1 0/1
Erasure error An error occurs during erasure 0 1 0 0 0
When the FPROTR.FPROTCN bit is 0, a block erase command is issued to an 0 1 0 0 0
erasure block whose lock bit is set to 0
Programming error An error occurs during programming 0 0 1 0 0
When the FPROTR.FPROTCN bit is 0, a programming or lock bit programming 0 0 1 0 0
command is issued to an erasure block whose lock bit is set to 0
FCU error An error occurs during FCU internal processing 0 0 0 1 0
ROM access violation When the FENTRYR.FENTRY0 bit is 1 in ROM P/E normal mode, a read access 1 0 0 0 1
command is issued for addresses:
00FF 8000h to 00FF FFFFh when the user area capacity is 32 Kbytes,
00FF 0000h to 00FF FFFFh when the user area capacity is 64 Kbytes,
00FE 0000h to 00FF FFFFh when the user area capacity is 128 Kbytes,
or 00FC 0000h to 00FF FFFFh when the user area capacity is 256 Kbytes.
When the FENTRYR.FENTRY0 bit is 0, an access command is issued for addresses: 1 0 0 0 1
00FF 8000h to 00FF FFFFh when the user area capacity is 32 Kbytes,
00FF 0000h to 00FF FFFFh when the user area capacity is 64 Kbytes,
00FE 0000h to 00FF FFFFh when the user area capacity is 128 Kbytes,
or 00FC 0000h to 00FF FFFFh when the user area capacity is 256 Kbytes.
When FENTRYR has set ROM in ROM P/E mode, a read access command is issued 1 0 0 0 1
for addresses
FFFF 8000h to FFFF FFFFh when the user area capacity is 32 Kbytes,
FFFF 0000h to FFFF FFFFh when the user area capacity is 64 Kbytes,
FFFE 0000h to FFFF FFFFh when the user area capacity is 128 Kbytes,
or FFFC 0000h to FFFF FFFFh when the user area capacity is 256 Kbytes.
RX220
ROM
E2 DataFlash
Host
Table 36.9 Input and Output Pins Associated with the ROM
Pin Name I/O Description
MD Input Selection of operating mode
PC7 Input Selection of boot mode or User boot mode
P30/RXD1 Input Used in boot mode to receive data via SCI1 (for host communications)
P26/TXD1 Output Used in boot mode to transmit data from SCI1 (for host communications)
00h,......,00h
(1)
Activated in boot mode (Bit rate adjustment)
Bit rate adjustment
(Reset in boot mode)
55h
Figure 36.23 Transfer Format Used by SCI in Automatic Adjustment of Bit Rate
Host RX220
55h
Set the bit rate for SCI transfer on the host to satisfy either of the conditions Table 36.10.
31 24 23 16 15 8 7 0
(2) ID Code
The ID code can be set to any desired value. However, if the control code is 52h and the ID code is 50h, 72h, 6Fh, 74h,
65h, 63h, 74h, FFh, ..., FFh (from the ID code 1 field), there is no determination of matching and the ID code is always
considered to be non-matching. Accordingly, reading, programming, and erasure from the host are prohibited.
.SECTION ID_CODE,CODE
.ORG 0FFFFFFA0h
.LWORD 45010203h
.LWORD 04050607h
.LWORD 08090A0Bh
.LWORD 0C0D0E0Fh
36.10.5 UB Code
For the UB code, see section 7.3, UB Code.
If the host has sent an undefined command, the RX220 returns a response indicating a command error in the format
shown below. The command field holds the first byte of the undefined command sent from the host.
In the inquiry/selection command wait, send selection commands from the host in the order of device selection, clock
mode selection, and new bit rate selection to set up the RX220 according to the responses to inquiry commands. Note
that the supported device inquiry and clock mode inquiry commands are the only inquiry commands that can be sent
before the clock mode selection command; other inquiry commands must not be issued before the clock mode selection
command. If commands are issued in an incorrect order, the RX220 returns a response indicating a command error.
Figure 36.26 shows an example of the procedure to use commands in the inquiry/selection command wait.
Start
Device selection
End
Figure 36.26 Example of Procedure to Use Inquiry/Selection Commands for User Area/User Boot Area
Each command is described in detail below. The “command” in the description indicates a command sent from the host
to the RX220 and the “response” indicates a response sent from the RX220 to the host. The “checksum” is byte-size data
calculated so that the sum of all bytes to be sent by the RX220 becomes 00h.
Command 20h
SUM
Size (1 byte): Total number of bytes in the device count, character count, device code, and series name fields
Device count (1 byte): Number of device types supported by the boot program
Character count (1 byte): Number of characters included in the device code and series name fields
Device code (4 bytes): Chip recognition code
Series name (n bytes): ASCII code for the supported device
SUM (1 byte): Checksum
Response 06h
Command 21h
Size (1 byte): Total number of bytes in the mode count and mode fields
Mode (1 byte): Supported clock mode (for example, 01h indicates clock mode 1)
SUM (1 byte): Checksum
Response 06h
Command 22h
Size (1 byte): Total number of bytes in the clock type count, multiplication ratio count, and multiplication ratio
fields
Clock type count (1 byte): Number of clock types (for example, 02h indicates two clock types; that is, a system clock and a
peripheral clock)
Multiplication ratio count (1 byte): Number of supported multiplication/division ratios (for example, 04h indicates that four
multiplication ratios are supported for the system clock (multiplied by 1, multiplied by 2, multiplied
by 4, and multiplied by 8))
Multiplication ratio (1 byte): A positive value indicates a multiplication ratio (for example, 04h = 4 = multiplied by 4)
A negative value indicates a division ratio (for example, FEh = –2 = divided by 2)
SUM (1 byte): Checksum
Command 23h
SUM
Size (1 byte): Total number of bytes in the clock type count, minimum frequency, and maximum frequency fields
Clock type count (1 byte): Number of clock types (for example, 02h indicates two clock types; that is, a system clock and a
peripheral clock)
Minimum frequency (2 bytes): Minimum value of the operating frequency (for example, 07D0h indicates 20.00 MHz).
This value should be calculated by multiplying the frequency value (MHz) to two decimal places by 100.
Maximum frequency (2 bytes): Maximum value of the operating frequency
This value is represented in the same format as the minimum frequency
SUM (1 byte): Checksum
Command 24h
Size (1 byte): Total number of bytes in the area count, area start address, and area end address fields
Area count (1 byte): Number of user boot areas (consecutive areas are counted as one area)
Area start address (4 bytes): Start address of a user boot area
Area end address (4 bytes): End address of a user boot area
SUM (1 byte): Checksum
Command 25h
Size (1 byte): Total number of bytes in the area count, area start address, and area end address fields
Area count (1 byte): Number of user areas (consecutive areas are counted as one area)
Area start address (4 bytes): Start address of a user area
Area end address (4 bytes): End address of a user area
SUM (1 byte): Checksum
Command 26h
Size (2 bytes): Total number of bytes in the block count, block start address, and block end address fields
Block count (1 byte): Number of erasure blocks in the user area
Block start address (4 bytes): Start address of an erasure block
Block end address (4 bytes): End address of an erasure block
SUM (1 byte): Checksum
Command 27h
Size (1 byte): Number of characters included in the programming size field (fixed at 2)
Programming size (2 bytes): Programming unit (bytes)
SUM (1 byte): Checksum
Host RX220
Confirmation (06h)
Response (06h)
Response 06h
Confirmation 06h
Response 06h
Size (1 byte): Total number of bytes in the bit rate, input frequency, clock type count, and multiplication ratio fields
Bit rate (2 bytes): New bit rate (for example, 00C0h indicates 19200 bps)
1/100 of the new bit rate value should be specified.
Input frequency (2 bytes): Frequency input to the RX220 (for example, 04E2h indicates 12.50 MHz)
This value should be calculated by multiplying the input frequency value to two decimal places by 100.
Clock type count (1 byte): Number of clock types (for example, 02h indicates two clock types; that is, a system clock and a
peripheral clock)
Multiplication ratio 1 (1 byte): Multiplication/division ratio of the input frequency to obtain the system clock (ICLK)
A positive value indicates a multiplication ratio (for example, 04h = 4 = multiplied by 4)
A negative value indicates a division ratio (for example, FEh = –2 = divided by 2)
Multiplication ratio 2 (1 byte): Multiplication/division ratio of the input frequency to obtain the peripheral clock (PCLK)
This value is represented in the same format as multiplication ratio 1
SUM (1 byte): Checksum
Error: Error code
11h: Checksum error
24h: Bit rate selection error
25h: Input frequency error
26h: Multiplication ratio error
27h: Operating frequency error
Command 40h
Response ACK
Command 4Fh
Size (1 byte): Total number of bytes in the status and error fields (fixed at 2)
Status (1 byte): Current status of RX220 (see Table 36.13)
Error (1 byte): Error status of RX220 (see Table 36.14)
SUM (1 byte): Checksum
If the host has sent an undefined command, the RX220 returns a response indicating a command error. For the contents
of a command error, see section 36.10.6, Inquiry/Selection Command Wait.
Response ACK
If the host has sent an undefined command, the RX220 returns a response indicating a command error. For the contents
of a command error, see section 36.10.6, Inquiry/Selection Command Wait.
To program the ROM, issue a programming selection command (user/data area programming selection, user boot area
programming selection) and then a 256-byte programming command from the host. Upon reception of a programming
selection command, the RX220 enters the programming data wait state (see section 36.10.2, State Transitions in Boot
Mode). In response to a 256-byte programming command sent from the host in this state, the RX220 starts programming
the ROM. When the host sends a 256-byte programming command specifying FFFF FFFFh as the programming start
address, the RX220 detects it as the end of programming and enters the programming/erasure command wait.
To erase the ROM, issue an erasure selection command and then a block erase command from the host. Upon reception
of an erasure selection command, the RX220 enters the erasure block selection wait state (see section 36.10.2, State
Transitions in Boot Mode). In response to a block erase command sent from the host in this state, the RX220 erases the
specified block in the ROM. When the host sends a block erase command specifying FFh as the block number, the
RX220 detects it as the end of erasure and enters the programming/erasure command wait.
Start
End
Start
Erasure selection
End
Each command is described in detail below. The “command” in the description indicates a command sent from the host
to the RX220 and the “response” indicates a response sent from the RX220 to the host. The “checksum” is byte-size data
calculated so that the sum of all bytes to be sent by the RX220 becomes 00h.
Command 42h
Response 06h
Command 43h
Response 06h
Response 06h
Command 48h
Response 06h
Response 06h
Size (1 byte): Total number of bytes in the area, read start address, and reading size fields
Area (1 byte): Target area to be read
00h: User boot area
01h: User area
Read start address (4 bytes): Start address of the area to be read
Reading size (4 bytes): Size of data to be read (bytes)
SUM (1 byte): Checksum
Data (1 byte): Data read from the ROM
Error (1 byte): Error code
11h: Checksum error
2Ah: Address error
The value specified for area selection is neither 00h nor 01h.
The specified read start address is outside the selected area.
2Bh: Data size error
00h is specified for the reading size.
The reading size is larger than the area.
The end address calculated from the read start address and the reading size is outside the
selected area.
Command 4Ah
Command 4Bh
Command 4Ch
Response 06h
Command 4Dh
Response 06h
Command 71h Size Area A15 to A8 A23 to A16 A31 to A24 SUM
A15 to A8 (1 byte):The last address in the specified block (bits 15 to 8)
A23 to A16 (1 byte):The last address in the specified block (bits 23 to 16)
A31 to A24 (1 byte):The last address in the specified block (bits 31 to 24)
Response Status
Size (1 byte): Total number of bytes in the area, A15 to A8, A23 to A16, and A31 to A24
Area (1 byte): Target area to be read
01h: User area
A15 to A8 (1 byte) A15 to A8 of the last address in the specified block (bits 15 to 8)
A23 to A16 (1 byte): A23 to A16 of the last address in the specified block (bits 23 to 16)
A31 to A24 (1 byte): A31 to A24 of the last address in the specified block (bits 31 to 24)
SUM (1 byte): Checksum
Status (1 byte): Bit 6 locked at 0
Bit 6 unlocked at 1
Error (1 byte): Error code
11h: Checksum error
2Ah: Address error (the specified address is not in the target area)
Command 77h Size Area Third highest Second highest Highest order SUM
order address order address address
Response 06h
Size (1 byte): Total number of bytes in the area, third highest order address, second highest order address,
and highest order address fields (fixed at 4 in the RX220)
Area (1 byte): Target area to be locked
01h: User area
Third highest order address (1 byte): Third highest order address at the specified block's end address (8 to 15 bits)
Second highest order address (1 byte): Second highest order address at the specified block's end address (16 to 23 bits)
Highest order address (1 byte): Highest order address at the specified block's end address (24 to 31 bits)
SUM (1 byte): Checksum
Error (1 byte): Error code
11h: Checksum error
2Ah: Address error (the specified address is not in the target area)
53h: Lock cannot be done due to a programming error
Command 7Ah
Response 06h
Command 75h
Response 06h
Table 36.17 Specifications for ID Code Protection on Connection of the On-Chip Debugger
Control State of
Code ID Code Protection Operations at On-Chip Debugger Connection
FFh FFh, …, FFh Protection disabled The ID code always matches and connection to the on-chip
(all bytes FFh) debugger is permitted.
52h 50h, 72h, 6Fh, 74h, 65h, Protection enabled The ID code is always non-matching and connection to the on-chip
63h, 74h debugger is prohibited.
Other than Other than above Protection enabled Matching ID code: Authentication of the on-chip debugger is ended
above and connection with the on-chip debugger is permitted.
Non-matching ID code: The ID code protection waiting state is
entered again.
37.1 Overview
Table 37.1 lists the specifications of the E2 DataFlash memory, and Figure 37.1 is a block diagram of the ROM, E2
DataFlash memory, and related modules.
CPU
FCU
ROM area
FMODR
Memory bus 2
FASTAT
FAEINT
Module internal bus
DFLRE0
DFLWE0
FIFERR FSTATR0
FSTATR1
FRDYI FENTRYR
FRESETR
FCMDR
FRDYIE
FCPSR
DFLBCCNT E2 DataFlash area
DFLBCSTAT Data area: 8 Kbytes
PCKAR
For input and output pins associated with the E2 DataFlash, see Table 36.9, Input and Output Pins Associated with
the ROM.
b7 b6 b5 b4 b3 b2 b1 b0
— — — FRDM — — — —
D
Value after reset: 0 0 0 0 0 0 0 0
b7 b6 b5 b4 b3 b2 b1 b0
When any bit from among the DFLWPE, DFLRPE, DFLAE, and ROMAE bits in FASTAT is set to 1, the
FSTATR0.ILGLERR bit is set to 1, which places the FCU in the command-locked state (see section 37.7.2,
Command-Locked State). To clear the command-locked state, a status register clearing command must be issued to the
FCU after setting FASTAT to 10h.
[Setting condition]
A programming/erasure command is issued for an E2 DataFlash area for which programming or erasure is disabled
by DFLWE0.
[Clearing condition]
When 0 is written after reading 1
[Setting condition]
A read command is issued for an E2 DataFlash area for which reading is disabled by DFLRE0.
[Clearing condition]
When 0 is written after reading 1
[Setting conditions]
A read command is issued for an E2 DataFlash area in E2 DataFlash P/E normal mode and when the FENTRYD bit
in FENTRYR is set to 1.
A write command is issued for an E2 DataFlash area when the FENTRYD bit is set to 0.
A command is issued for an E2 DataFlash area when the FENTRY0 in FENTRYR is set to 1.
[Clearing condition]
When 0 is written after reading 1
[Setting condition]
After the FCU detects an error and enters the command-locked state
[Clearing condition]
After the FCU has processed a status register clearing command
b7 b6 b5 b4 b3 b2 b1 b0
DFLRE0 is a register to enable or disable the DB00 to DB63 blocks of the data area (see Figure 37.3) to be read.
DFLWE0 is a register to enable or disable the DB00 to DB63 blocks of the data area (see Figure 37.3) to be
programmed or erased.
To place the ROM/E2 DataFlash in ROM P/E mode so that the FCU can accept commands, the FENTRYD or FENTRY0
bit must be set to 1. If more than one bit is set to 1, the ILGLERR bit is set in FSTATR0 and the FCU enters the command-
locked state.
After writing to the FENTRYR to initiate a transition to ROM-reading mode, read the register and confirm that it actually
holds the new setting before proceeding to read the ROM.
FENTRYR is initialized by a reset, or when the FRESET bit in FRESETR is set to 1.
For FSTATR0, see section 36.2.5, Flash Status Register 0 (FSTATR0).
For FRESETR, see section 36.2.10, Flash Reset Register (FRESETR).
BCSIZ — — — — BCADR[10:0]
E
Value after reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
— — — — — — — — — — — — — — — BCST
Data area
(8 Kbytes)
Figure 37.2 Configuration of the Data Area for the E2 DataFlash Memory
Note 1. All flash memory areas may be erased at the time of booting up. Specified blocks can subsequently be erased. For details, refer
to section 36.10.4, ID Code Protection (Boot Mode), section 36.10.2, State Transitions in Boot Mode
In boot mode, a host is able to program/erase or read the data area via an SCI.
In boot mode, RAM is employed for use in the boot program. For this reason, preserving the contents of RAM is not
possible in this case.
In user boot mode, any desired interface can be used for programming or reading of the user area and data area
following booting up from the user boot area.
FENTRYR = AA01h
ROM/E2 DataFlash read ROM P/E mode
mode
FENTRYR = AA00h
FENTRYR = AA80h
FENTRYR = AA00h
(B)
E2 DataFlash P/E E2 DataFlash status read
normal mode mode
(A)
(A) (C)
(C) (B)
E2 DataFlash lock bit read
mode
Figure 37.4 Mode Transitions of the FCU (Associated with the E2 DataFlash)
Commands other than the blank-checking command are also for use with the ROM.
The blank-checking command for the E2 DataFlash memory is also used as the lock bit read 2 command for the ROM.
That is, when the same command is issued for the ROM, a lock bit of the ROM is read.
Commands for the FCU are issued by write access to addresses within the E2 DataFlash area.
Table 37.4 lists the formats of the programming commands and the blank checking command. For the formats of FCU
commands other than programming and blank checking commands, see section 36.6.2, FCU Commands.
Write access as listed in Table 37.4 and in accord with certain conditions causes the FCU to execute processing for the
corresponding command. For details on the conditions for acceptance of the individual FCU commands, see section
37.6.3, Connections between FCU Modes and Commands. For how to use the FCU commands, see section
37.6.4, FCU Command Usage.
Table 37.4 FCU Command Formats (Commands Dedicated to the E2 DataFlash Memory)
Number First Cycle Second Cycle Third Cycle 4th to (N+2)th Cycle (N+3)th Cycle
of Bus
Command Cycles Address Data Address Data Address Data Address Data Address Data
Programming 4 EA E8h EA 01h WA WDn — — EA D0h
(2-byte programming; N = 1)
Programming 7 EA E8h EA 04h WA WDn EA WDn EA D0h
(8-byte programming; N = 4)
Blank checking 2 EA 71h BA D0h — — — — — —
Address column EA: Address within the E2 DataFlash area. Any address in the range from 0010 0000h to 0010 1FFFh.
WA: Start address of programming data
BA: Block start address within the E2 DataFlash area (2-Kbyte block)
Data columns WDn: nth word of data for programming (n = 1 to N)
Table 37.5 Acceptable Commands and the State and Mode (E2 DataFlash P/E Mode) of the FCU
P/E Normal Lock-Bit Read
Mode Status Read Mode Mode
Programming during Erasure Suspended State
Programming Suspended
Programming Suspended
Programming or Erasure
programming or Erasure
Processing to Suspend
Erasure Suspended
Erasure Suspended
Erasure Suspended
Blank Checking
Other State
Other State
Other State
FSTATR0.FRDY bit 1 1 1 0 0 0 0 1 1 0 1 1 1 1 1
FSTATR0.SUSRDY bit 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
FSTATR0.ERSSPD bit 0 1 0 0 1 0/1 0 0 1 0/1 0/1 0 0 1 0
FSTATR0.PRGSPD bit 1 0 0 0 0 0/1 0 1 0 0/1 0/1 0 1 0 0
FASTAT.CMDLK bit 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0
P/E normal mode transition A A A × × × × A A × × A A A A
Status read mode transition A A A × × × × A A × × A A A A
Lock-bit read mode transition A A A × × × × A A × × A A A A
(lock bit read 1)
Peripheral clock notification × × A × × × × × × × × A × × A
Programming × * A × × × × × * × × A × * A
Block erasure × × A × × × × × × × × A × × A
P/E suspension × × × A × × × × × × × × × × ×
P/E resumption A A × × × × × A A × × × A A ×
Status register clearing A A A × × × × A A × A A A A A
Blank checking A A A × × × × A A × × A A A A
A: Acceptable
*: Only programming is acceptable for blocks other than the block where erasure was suspended
×: Not acceptable
(2) Programming
To program the E2 DataFlash, use one of the programming commands.
Use byte access to write E8h to an address within the E2 DataFlash area in the first cycle of the programming command,
and the number of words (N)*1 to be programmed in the second cycle. Access the peripheral bus in words from the third
cycle to cycle N + 2 of the command. In the third cycle, write the first word of data for programming to the address
where the target area for programming starts.
In the case of 8-byte programming, 8 bytes (4 words) of data are written to the E2 DataFlash in the third to the sixth
cycles, divided into four rounds. The start address of 8 bytes for programming is specified in the third cycle. The address
range specified at this time must be an integral multiple of 8. The address range specified in the fourth to the sixth cycles
does not need to be the address range for actual programming.
In the case of 2-byte programming, the address range and data for programming are specified in the third cycle. The
address range must be an even number.
After writing words to addresses in the E2 DataFlash area N times, write byte D0h to an address within the E2 DataFlash
area in cycle N + 3; the FCU will then start actual programming of the E2 DataFlash. Read the FRDY bit in FSTATR0 to
confirm the completion of E2 DataFlash programming.
If the area accessed in the third cycle to cycle N + 2 includes addresses that do not require programming, write FFFFh as
the programming data for those addresses. Moreover, programming and erasure of the block that contains the address
must be enabled by the corresponding setting for protection from programming and erasure in the DFLWE0 register.
Figure 37.5 shows the procedure for E2 DataFlash programming.
Start
n=1
n=N
No
Yes
Timeout
FRDY bit check
0 (tDP2/tDP8 × 1.1)*1 No
1 Yes
FCU initialization
FRESETR.FRESET = 1
writing
Wait
ILGLERR bit and PRGERR bit check (tFCUR)*2
FRESETR.FRESET = 0
writing
End
Note 1. tDP2/tDP8: Time required for programming 2-/8-byte data (see section 38, Electrical Characteristics)
Note 2. tFCUR: Reset pulse width during programming/erasure (see section 38, Electrical Characteristics)
(3) Erasure
To erase the E2 DataFlash, use the block erasure command. The E2 DataFlash is erased in the same way as the ROM (see
section 36, ROM (Flash Memory for Code Storage)).
Note that the E2 DataFlash has a programming and erasure protection function that is controlled by DFLWE0. Erasure
can only be performed with protection provided by the DFLWE0 setting disabled, so set the programming/erasure enable
bit for the target erasure block to 1 before issuing the erasure command.
Start
Timeout
FRDY bit check
0 (tBC2K × 1.1)*1 No
1 Yes
FCU initialization
Wait
(tFCUR)*2
Check DFLBCSTAT
FRESETR.FRESET = 0
writing
End
Note 1. tBC2K: Time required for blank check of 2-Kbyte data (see section 38, Electrical Characteristics)
Note 2. tFCUR: Reset pulse width during programming/erasure (see section 38, Electrical Characteristics)
37.7 Protection
There are two types of E2 DataFlash programming/erasure protection: software protection and command-locked state.
Table 37.6 Errors that Lead to the Command-Locked State (for E2 DataFlash Only)
ILGLERR
PRGERR
DFLWPE
ERSERR
DFLRPE
DFLAE
Error Description
Illegal command error The value specified in the second cycle of a programming command was 1 0 0 0 0 0
other than 01h and 04h.
A lock bit programming command was issued for an area in the E2 1 0 0 0 0 0
DataFlash while the FENTRYD bit of FENTRYR register was set to 1.
E2 DataFlash access error A read access command was issued for the E2 DataFlash area while 1 0 0 1 0 0
FENTRYD = 1 in FENTRYR in E2 DataFlash P/E normal mode.
A write access command was issued for the E2 DataFlash area while 1 0 0 1 0 0
FENTRYD = 0.
An access command was issued for the E2 DataFlash area while the 1 0 0 1 0 0
FENTRY0 bit in FENTRYR was 1.
E2 DataFlash read protect A read access command was issued for the E2 DataFlash area while it was 1 0 0 0 1 0
error protected against reading by the DFLRE0 setting.
E2 DataFlash A program/block erase command was issued for the E2 DataFlash area 1 0 0 0 0 1
programming protect error while it was protected against programming and erasure by the DFLWE0
setting.
Each command is described in detail below. The “command” in the description indicates a command sent from the host
to the RX220 and the “response” indicates a response sent from the RX220 to the host. The “checksum” is byte-size data
calculated so that the sum of all bytes to be sent by the RX220 becomes 00h.
Command 2Ah
Command 2Bh
Size (1 byte): Total number of bytes in the area count, area start address, and area end
address fields
Area count (1 byte): Number of data areas (consecutive areas are counted as one area)
Area start address (4 bytes): Start address of a data area
Area end address (4 bytes): End address of a data area
SUM (1 byte): Checksum
The information concerning the block configuration in the data area is included in the response to the erasure block
information inquiry command (see section 36.10.6, Inquiry/Selection Command Wait).
Each command is described in detail below. The “command” in the description indicates a command sent from the host
to the RX220 and the “response” indicates a response sent from the RX220 to the host. The “checksum” is byte-size data
calculated so that the sum of all bytes to be sent by the RX220 becomes 00h.
Command 61h
Command 62h
Response 06h
Error
response E2h 52h
Caution: Permanent damage to the LSI may result if absolute maximum ratings are exceeded.
To preclude any malfunctions due to noise interferences, insert capacitors of high frequency characteristics between the VCC
and VSS pins, between the AVCC0 and AVSS0 pins, and between the VREFH0 and VREFL0 pins. Place capacitors of 0.1 µF or
so as close to every power pin and use the shortest and heaviest possible traces.
Connect the VCL pin to a VSS pin via a 0.1 µF (±20% accuracy) capacitor. The capacitor must be placed as close to the pin as
possible.
Note 1. Ports 12, 13, 16, and 17 are 5 V tolerant.
Note 2. Set to the same potential as VCC. When the A/D converter is not used, do not leave the AVCC0, VREFH0, AVSS0, and VREFL0
pins open. Connect the AVCC0 and VREFH0 pins to VCC, and the AVSS0 and VREFL0 pins to VSS, respectively.
Note 3. The maximum value is 6.5 V.
38.2 DC Characteristics
Note 1. Supply current values do not include output charge/discharge current from all pins. The values apply when internal pull-up MOSs
are in the off state.
Note 2. Clock supply to the peripheral functions is stopped. This does not include BGO operation. The clock source is HOCO. BCLK,
FCLK, and PCLK are set to divided by 64.
Note 3. Clocks are supplied to the peripheral functions. This does not include BGO operation. The clock source is HOCO. BCLK, FCLK,
and PCLK are ICLK divided by 1.
Note 4. This is the increase if data is programmed to or erasing from the ROM or E2 DataFlash during program execution.
Note 5. Clock supply to the peripheral functions is stopped. This does not include BGO operation. The clock source is HOCO. BCLK,
FCLK, and PCLK are set to divided by 64.
Note 6. Clocks are supplied to the peripheral functions. This does not include BGO operation. The clock source is HOCO. BCLK, FCLK,
and PCLK are ICLK divided by 1.
Note 7. Clock supply to the peripheral functions is stopped. This does not include BGO operation. The clock source is the sub oscillation
circuit. BCLK, FCLK, and PCLK are set to divided by 64.
Note 8. Clocks are supplied to the peripheral functions. This does not include BGO operation. The clock source is the sub oscillation
circuit. BCLK, FCLK, and PCLK are ICLK divided by 1.
Note 9. VCC = 3.3 V.
25
20
10
Ta = 25°C, ICLK = 20 MHz*1
0
1.0 2.0 3.0 4.0 5.0 6.0
VCC (V)
Note 1. All peripheral operation is normal. This does not include BGO operation.
Average value of the tested middle samples during product evaluation.
Note 2. All peripheral operation is maximum. This does not include BGO operation.
Average value of the tested upper-limit samples during product evaluation.
Figure 38.1 Voltage Dependency in Medium-Speed Operating Modes 1A and 1B (Reference Data)
VCC (V)
Note 1. All peripheral operation is normal. This does not include BGO operation.
Average value of the tested middle samples during product evaluation.
Note 2. All peripheral operation is maximum. This does not include BGO operation.
Average value of the tested upper-limit samples during product evaluation.
200
150
ICC (A)
100
50
Ta = 25°C, ICLK = 32.768 kHz*1
0
1.0 2.0 3.0 4.0 5.0 6.0
VCC (V)
Note 1. All peripheral operation is normal. This does not include BGO operation.
Average value of the tested middle samples during product evaluation.
Note 2. All peripheral operation is maximum. This does not include BGO operation.
Average value of the tested upper-limit samples during product evaluation.
Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.
Note 2. The IWDT and LVD are stopped.
Note 3. VCC = 3.3 V.
100 Ta = 105°C*2
Ta = 85°C*2
Ta = 105°C*1
ICC (A)
Ta = 55°C*2
10
Ta = 85°C*1
Ta = 25°C*2
Ta = 55°C*1
Ta = 25°C*1
1
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VCC (V)
Note 1. Average value of the tested middle samples during product evaluation.
Note 2. Average value of the tested upper-limit samples during product evaluation.
Figure 38.4 Voltage Dependency in Software Standby Mode (SOFTCUT Bit = 11xb) (Reference Data)
100
10
ICC (A)
0.1
-50 -30 -10 10 30 50 70 90
Ta (°C)
Note 1. Average value of the tested middle samples during product evaluation.
Note 2. Average value of the tested upper-limit samples during product evaluation.
Figure 38.5 Temperature Dependency in Software Standby Mode (SOFTCUT Bit = 11xb) (Reference
Data)
Note: • Please contact Renesas Electronics sales office for derating of operation under Ta = +85°C to +105°C. Derating is the
systematic reduction of load for the sake of improved reliability.
Note 1. Total power dissipated by the entire chip (including output currents)
1/fr(VCC)
VCC Vr(VCC)
IOH/IOL vs VOH/VOL
60
50
VCC = 5.5 V
40
30
VCC = 3.3 V
20
VCC = 2.7 V
10
IOH/IOL [mA]
VCC = 1.62 V
0
0 1 2 3 4 5 6
VCC = 1.62 V
–10
VCC = 2.7 V
–20
VCC = 3.3 V
–30
–40
VCC = 5.5 V
–50
–60
VOH/VOL [V]
Figure 38.7 VOH/VOL and IOH/IOL Voltage Characteristics at Ta = 25°C when Normal Output is
Selected (Reference Data)
IOH/IOL vs VOH/VOL
5
Ta = –40°C
4 Ta = 25°C
Ta = 105°C
3
1
IOH/IOL [mA]
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
–1
–2
Ta = 105°C
–3
Ta = 25°C
–4
Ta = –40°C
–5
VOH/VOL [V]
Figure 38.8 VOH/VOL and IOH/IOL Temperature Characteristics at VCC = 1.62 V when Normal Output
is Selected (Reference Data)
IOH/IOL vs VOH/VOL
20
Ta = –40°C
15 Ta = 25°C
Ta = 105°C
10
5
IOH/IOL [mA]
0
0 0.5 1 1.5 2 2.5 3
–5
–10
Ta = 105°C
Ta = 25°C
–15
Ta = –40°C
–20
VOH/VOL [V]
Figure 38.9 VOH/VOL and IOH/IOL Temperature Characteristics at VCC = 2.7 V when Normal Output is
Selected (Reference Data)
IOH/IOL vs VOH/VOL
30
Ta = –40°C
Ta = 25°C
20
Ta = 105°C
10
IOH/IOL [mA]
0
0 0.5 1 1.5 2 2.5 3 3.5
–10
Ta = 105°C
–20
Ta = 25°C
Ta = –40°C
–30
VOH/VOL [V]
Figure 38.10 VOH/VOL and IOH/IOL Temperature Characteristics at VCC = 3.3 V when Normal Output is
Selected (Reference Data)
IOH/IOL vs VOH/VOL
60
Ta = –40°C
50
Ta = 25°C
40
Ta = 105°C
30
20
10
IOH/IOL [mA]
0
0 1 2 3 4 5 6
–10
–20
–30
Ta = 105 °C
–40
Ta = 25°C
–50
Ta = –40°C
–60
VOH/VOL [V]
Figure 38.11 VOH/VOL and IOH/IOL Temperature Characteristics at VCC = 5.5 V when Normal Output is
Selected (Reference Data)
IOH/IOL vs VOH/VOL
120
VCC = 5.5 V
100
80
60
VCC = 3.3 V
40
VCC = 2.7 V
20
IOH/IOL [mA]
VCC = 1.62 V
0
0 1 2 3 4 5 6
VCC = 1.62 V
–20
VCC = 2.7 V
–40 VCC = 3.3 V
–60
–80
VCC = 5.5 V
–100
–120
VOH/VOL [V]
Figure 38.12 VOH/VOL and IOH/IOL Voltage Characteristics at Ta = 25°C when High-Drive Output is
Selected (Reference Data)
IOH/IOL vs VOH/VOL
12
Ta = –40°C
10
Ta = 25°C
8 Ta = 105°C
2
IOH/IOL [mA]
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
–2
–4
Ta = 105°C
–6
Ta = 25°C
–8 Ta = –40°C
–10
–12
VOH/VOL [V]
Figure 38.13 VOH/VOL and IOH/IOL Temperature Characteristics at VCC = 1.62 V when High-Drive
Output is Selected (Reference Data)
IOH/IOL vs VOH/VOL
50
40 Ta = –40°C
Ta = 25°C
30
Ta = 105°C
20
10
IOH/IOL [mA]
0
0 0.5 1 1.5 2 2.5 3
–10
Ta = 105°C
–20
Ta = 25°C
–30 Ta = –40°C
–40
–50
VOH/VOL [V]
Figure 38.14 VOH/VOL and IOH/IOL Temperature Characteristics at VCC = 2.7 V when High-Drive
Output is Selected (Reference Data)
IOH/IOL vs VOH/VOL
60
Ta = –40°C
50
Ta = 25°C
40
Ta = 105°C
30
20
10
IOH/IOL [mA]
0
0 0.5 1 1.5 2 2.5 3 3.5
–10
–20
Ta = 105°C
–30
Ta = 25°C
–40
Ta = –40°C
–50
–60
VOH/VOL [V]
Figure 38.15 VOH/VOL and IOH/IOL Temperature Characteristics at VCC = 3.3 V when High-Drive
Output is Selected (Reference Data)
IOH/IOL vs VOH/VOL
140
120 Ta = –40°C
100 Ta = 25°C
80 Ta = 105°C
60
40
IOH/IOL [mA]
20
0
0 1 2 3 4 5 6
–20
–40
–60 Ta = 105°C
–80 Ta = 25°C
–100 Ta = –40°C
–120
–140
VOH/VOL [V]
Figure 38.16 VOH/VOL and IOH/IOL Temperature Characteristics at VCC = 5.5 V when High-Drive
Output is Selected (Reference Data)
80
70
VCC = 5.5 V
60
50
IOL [mA]
40
VCC = 3.3 V
30
VCC = 2.7 V
20
10
0
0 1 2 3 4 5 6
VOL [V]
Figure 38.17 VOL and IOL Voltage Characteristics of RIIC Output Pin at Ta = 25°C (Reference Data)
30
Ta = –40°C
25
Ta = 25°C
20
IOL [mA]
Ta = 105°C
15
10
0
0 0.5 1 1.5 2 2.5 3
VOL [V]
Figure 38.18 VOL and IOL Temperature Characteristics of RIIC Output Pin at VCC = 2.7 V (Reference
Data)
40
Ta = –40°C
35
Ta = 25°C
30
25
IOL [mA]
Ta = 105°C
20
15
10
0
0 0.5 1 1.5 2 2.5 3 3.5
VOL [V]
Figure 38.19 VOL and IOL Temperature Characteristics of RIIC Output Pin at VCC = 3.3 V (Reference
Data)
80
Ta = –40°C
70
Ta = 25°C
60
Ta = 105°C
50
IOL [mA]
40
30
20
10
0
0 1 2 3 4 5 6
VOL [V]
Figure 38.20 VOL and IOL Temperature Characteristics of RIIC Output Pin at VCC = 5.5 V (Reference
Data)
38.3 AC Characteristics
Note 1. The VCC is 2.7 to 5.5 V and the FCLK must be running at a frequency of at least 4 MHz during programming or erasing of the
flash memory.
Note 2. The lower-limit frequency of PCLKD is 1 MHz when the A/D converter is in use.
Note 1. The VCC is 1.62 to 3.6 V and the FCLK must be running at a frequency of at least 4 MHz during programming or erasing of the
flash memory.
Note 2. The lower-limit frequency of PCLKD is 1 MHz when the A/D converter is in use.
HOCO clock power supply stabilization time tHOCOP — — 350 µs Figure 38.26
Note 1. The time interval from the time P36 and P37 are configured for input and the main clock oscillator stopping bit
(MOSCCR.MOSTP) is set to 0 (operating) until the clock becomes available.
Note 2. When specifying the main clock oscillator stabilization time, load MOSCWTCR register with a stabilization time value that is
greater than the resonator-vendor-recommended value. When determining the main lock oscillation stabilization wait time, allow
an adequate margin (2 times is recommended) for the main clock oscillation stabilization time.
Start using the main clock in the main clock oscillation stabilization wait time (tMAINOSCWT) after setting up the main clock
oscillator for operation with the MOSCCR.MOSTP bit.
The indicated value is a reference value that is measured for an 8 MHz resonator.
Note 3. When specifying the sub-clock oscillation stabilization time, load SOSCWTCR register with the resonator-vendor-recommended
stabilization time value minus 2 seconds. When determining the sub-clock oscillation stabilization wait time, allow an adequate
margin (2 times is recommended) for the sub-clock oscillation stabilization time. Start using the sub-clock in the sub-clock
oscillation stabilization wait time (tSUBOSCWT) after setting up the sub-clock oscillator for operation with the SOSCCR.SOSTP
or RCR3.RTCEN bit.
tEXcyc
tEXH tEXL
tEXr tEXf
MOSCCR.MOSTP
tMAINOSC
tMAINOSCWT
Main clock
LOCOCR.LCSTP
tLOCOWT
LOCO clock
RES#
Internal reset
tRESWT
OFS1.HOCOEN
tHOCO1
HOCO clock
Figure 38.24 HOCO Clock Oscillation Start Timing (After Reset is Canceled by Setting the
OFS1.HOCOEN Bit to 0)
HOCOCR.HCSTP
tHOCO2
HOCO clock
Figure 38.25 HOCO Clock Oscillation Start Timing (Oscillation is Started by Setting the
HOCOCR.HCSTP Bit)
HOCOPCR.HOCOPCNT
HOCOCR.HCSTP
tHOCOP
SOSCCR.SOSTP
tSUBOSC
tSUBOSCWT
Sub-clock
1.55 V
VCC
RES#
tRESWP
Internal reset
tRESWT
RES#
Internal reset
tRESWT
Note 1. The recovery time varies depending on the state of each oscillator when the WAIT instruction is executed. The recovery time
when multiple oscillators are operating varies depending on the operating state of the oscillators that are not selected as the
system clock source, and depends on the time set in the wait control registers corresponding to the oscillators.
Note 2. The indicated value is measured for an 8 MHz crystal resonator. ICLK is set to divided by 1.
Note 3. When RCR3.RTCEN = 1, the time will be the time set in the SOSCWTCR register minus 2 s.
Note 4. When the external clock frequency is 20 MHz. ICLK is set to divided by 1.
Note 5. ICLK is set to divided by 1.
Note 6. When the frequency is 50 MHz, HOCOWTCR2.HSTS2[4:0] = 10101b and ICLK is set to divided by 2.
When the frequency is 32 MHz, HOCOWTCR2.HSTS2[4:0] = 10100b and ICLK is set to divided by 1.
Oscillator
ICLK
IRQ
NMI
tNMIW
IRQ
tIRQW
PCLK
Port
tPRW
PCLK
Output
compare output
Input capture
input
tTICW
PCLK
MTCLKA to
MTCLKD
tTCKWL tTCKWH
PCLK
POEn# input
tPOEW
PCLK
TMCI0 to TMCI3
tTMCWL tTMCWH
SCKn
(n = 1, 5, 6, 9, 12)
tScyc
SCKn
tTXD
TXDn
tRXS tRXH
RXDn
n = 1, 5, 6, 9, 12
PCLK
ADTRG0#
tTRGW
VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC
Figure 38.41 RSPI Clock Timing and Simple SPI Clock Timing
SSLA0 to
SSLA3
output tLEAD tLAG
tSSLr, tSSLf
RSPCKA SCKn
CPOL = 0 CKPOL = 0
output output
RSPCKA SCKn
CPOL = 1 CKPOL = 1
output output
tSU tH
MOSIA SMOSIn
MSB OUT DATA LSB OUT IDLE MSB OUT
output output
(n = 1, 5, 6, 9, 12)
Figure 38.42 RSPI Timing (Master, CPHA = 0) (Bit Rate: PCLKB Set to Division Ratio Other Than
Divided by 2) and Simple SPI Timing (Master, CKPH = 1)
tTD
SSLA0 to
SSLA3
output tLEAD tLAG
tSSLr, tSSLf
RSPCKA
CPOL = 0
output
RSPCKA
CPOL = 1
output
tSU tHF tHF
Figure 38.43 RSPI Timing (Master, CPHA = 0) (Bit Rate: PCLKB Set to Divided by 2)
SSLA0 to
SSLA3
output tLEAD tLAG
tSSLr, tSSLf
RSPCKA SCKn
CPOL = 0 CKPOL = 0
output output
RSPCKA SCKn
CPOL = 1 CKPOL = 1
output output
tSU tH
MOSIA SMOSIn
MSB OUT DATA LSB OUT IDLE MSB OUT
output output
(n = 1, 5, 6, 9, 12)
Figure 38.44 RSPI Timing (Master, CPHA = 1) (Bit Rate: PCLKB Set to Division Ratio Other Than
Divided by 2) and Simple SPI Timing (Master, CKPH = 0)
tTD
SSLA0 to
SSLA3
output tLEAD tLAG
tSSLr, tSSLf
RSPCKA
CPOL = 0
output
RSPCKA
CPOL = 1
output
tSU tHF tH
MISOA
MSB IN DATA LSB IN MSB IN
input
MOSIA
MSB OUT DATA LSB OUT IDLE MSB OUT
output
Figure 38.45 RSPI Timing (Master, CPHA = 1) (Bit Rate: PCLKB Set to Divided by 2)
RSPI SimpleSPI
tTD
SSLA0 SSn#
input input
tLEAD tLAG
RSPCKA SCKn
CPOL = 0 CKPOL = 0
input input
RSPCKA SCKn
CPOL = 1 CKPOL = 1
input input
tSA tOH tOD tREL
MISOA SMISOn MSB OUT DATA LSB OUT MSB IN MSB OUT
output output
(n = 1, 5, 6, 9, 12)
Figure 38.46 RSPI Timing (Slave, CPHA = 0) and Simple SPI Timing (Slave, CKPH = 1)
SSLA0 SSn#
input input
tLEAD tLAG
RSPCKA SCKn
CPOL = 0 CKPOL = 1
input input
RSPCKA SCKn
CPOL = 1 CKPOL = 0
input input
tSA tOH tOD tREL
(n = 1, 5, 6, 9, 12)
Figure 38.47 RSPI Timing (Slave, CPHA = 1) and Simple SPI Timing (Slave, CKPH = 0)
VIH
SDA
VIL
tBUF
tSCLH
tSTAH tSTAS tSP tSTOS
SCL
Figure 38.48 RIIC Bus Interface Input/Output Timing and Simple IIC Bus Interface Input/Output
Timing
Note: • The characteristics apply when no pin functions other than A/D converter input are used. Absolute accuracy includes
quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not
include quantization errors.
Note 1. The conversion time is the sum of the sampling time and the comparison time. As the test conditions, the number of sampling
states is indicated.
Note 2. The value in parentheses indicates the sampling time.
Note: • The characteristics apply when no pin functions other than A/D converter input are used. Absolute accuracy includes
quantization errors. Offset error, full-scale error, DNL differential nonlinearity error, and INL integral nonlinearity error do not
include quantization errors.
Note 1. The conversion time is the sum of the sampling time and the comparison time. As the test conditions, the number of sampling
states is indicated.
Note 2. The value in parentheses indicates the sampling time.
RX220
R0
ANi
FFFh
Full-scale error
Integral nonlinearity
error (INL)
A/D converter
output code Ideal line of actual A/D
Actual A/D conversion conversion characteristic
characteristic
Absolute accuracy
Absolute accuracy
Absolute accuracy is the difference between output code based on the theoretical A/D conversion characteristics, and the
actual A/D conversion result. When measuring absolute accuracy, the voltage at the midpoint of the width of analog
input voltage (1-LSB width), that can meet the expectation of outputting an equal code based on the theoretical A/D
conversion characteristics, is used as an analog input voltage. For example, if 12-bit resolution is used and if reference
voltage (VREFH0) = 5.12 V, then 1-LSB width becomes 1.25 mV, and 0 mV, 1.25 mV, 2.5 mV, ... are used as analog
input voltages.
If analog input voltage is 10 mV, absolute accuracy = ±5 LSB means that the actual A/D conversion result is in the range
of 003h to 00Dh though an output code, 008h, can be expected from the theoretical A/D conversion characteristics.
Offset error
Offset error is the difference between a transition point of the ideal first output code and the actual first output code.
Full-scale error
Full-scale error is the difference between a transition point of the ideal last output code and the actual last output code.
Table 38.37 Power-on Reset Circuit and Voltage Detection Circuit Characteristics (1)
Conditions: VCC = AVCC, VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C
Item Symbol Min. Typ. Max. Unit Test Conditions
Voltage detection Power-on reset Low power VPOR 1.30 1.40 1.55 V Figure 38.51 and
level (POR) consumption Figure 38.52
function disabled*1
Low power 1.00 1.20 1.45
consumption
function enabled*2
Voltage detection circuit (LVD0)*3 Vdet0_0 3.65 3.80 3.95 V Figure 38.53
Vdet0_1 2.70 2.80 2.90
Vdet0_2 1.80 1.90 2.00
Vdet0_3 1.62 1.72 1.82
Voltage detection circuit (LVD1)*4 Vdet1_0 4.00 4.15 4.30 V Figure 38.54
Vdet1_1 3.85 4.00 4.15
Vdet1_2 3.70 3.85 4.00 At falling edge
Vdet1_3 3.55 3.70 3.85 VCC
Note: • These characteristics apply when noise is not superimposed on the power supply.
Note 1. When the CPU is in a mode other than software standby mode, when the CPU transits to software standby mode with the
FHSSBYCR.SOFTCUT[2] bit set to 0.
Note 2. When the CPU transits to software standby mode with the FHSSBYCR.SOFTCUT[2] bit set to 1.
Note 3. # in the symbol Vdet0_# denotes the value of the OFS1.VDSEL[1:0] bits.
Note 4. # in the symbol Vdet1_# denotes the value of the LVDLVLR.LVD1LVL[3:0] bits.
Table 38.38 Power-on Reset Circuit and Voltage Detection Circuit Characteristics (2)
Conditions: VCC = AVCC0, VSS = AVSS0 = VREFL0 = 0 V, Ta = –40 to +105°C
Item Symbol Min. Typ. Max. Unit Test Conditions
Voltage detection Voltage detection circuit (LVD2)*1 Vdet2_0 4.00 4.15 4.30 V Figure 38.55
level
Vdet2_1 3.85 4.00 4.15
At falling edge VCC
Vdet2_2 3.70 3.85 4.00
Vdet2_3 3.55 3.70 3.85
Vdet2_4 3.40 3.55 3.70
Vdet2_5 3.25 3.40 3.55
Vdet2_6 3.10 3.25 3.40
Vdet2_7 2.95 3.10 3.25
Vdet2_8 2.85 2.95 3.05
Vdet2_9 2.70 2.80 2.90
Vdet2_A 2.55 2.65 2.75
Vdet2_B 2.40 2.50 2.60
Vdet2_C 2.25 2.35 2.45
Vdet2_D 2.10 2.20 2.30
Vdet2_E 1.95 2.05 2.15
Vdet2_F 1.80 1.90 2.00
VCMPA2 1.18 1.33 1.48 EXVCCINP2 = 1
Internal reset time Power-on reset time tPOR — 9 — ms Figure 38.52
Voltage monitoring 0 reset time tLVD0 — 9 — Figure 38.53
Voltage monitoring 1 reset time tLVD1 — 1.4 — Figure 38.54
Voltage monitoring 2 reset time tLVD2 — 1.4 — Figure 38.55
Minimum VCC down time*2 tVOFF 200 — — µs Figure 38.51
Response delay time tdet — — 200 µs Figure 38.52
LVD operation stabilization time (after LVD is enabled) Td(E-A) — — 15 µs Figure 38.54 and
Figure 38.55
Power-on reset enable time tW(POR) 1 — — ms Figure 38.52
VCC = 0.9 V or lower
Hysteresis width (LVD1 and LVD2) V LVH — 100 — mV When selection is from
among VdetX_0 to 7.
— 50 — When selection is from
among VdetX_8 to F.
Note: • These characteristics apply when noise is not superimposed on the power supply.
Note 1. # in the symbol Vdet2_# denotes the value of the LVDLVLR.LVD2LVL[3:0] bits.
Note 2. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels VPOR, Vdet0,
Vdet1, and Vdet2 for the POR/ LVD.
tVOFF
VCC
VPOR
VPOR
VCC
0.9 V
tw(por)
*1
Internal reset signal
(active-low)
tdet tPOR
Note 1. tw(por) is the time required for a power-on reset to be enabled while the external power VCC is being held below the
valid voltage (0.9 V).
When VCC turns on, maintain tw(por) for 1 ms or more.
tVOFF
VCC Vdet0
VPOR
tVOFF
LVD1E
Td(E-A)
LVD1
Comparator output
LVD1CMPE
LVD1MON
Internal reset signal
(active-low)
When LVD1RN = L
When LVD1RN = H
tLVD1
tVOFF
LVD2E
Td(E-A)
LVD2
Comparator output
LVD2CMPE
LVD2MON
Internal reset signal
(active-low)
When LVD2RN = L
When LVD2RN = H
tLVD2
Main clock
tdr
OSTDSR.OSTDF
LOCO clock
ICLK
Table 38.40 ROM (Flash Memory for Code Storage) Characteristics (1)
Item Symbol Min. Typ. Max. Unit Conditions
Reprogramming/erasure cycle*1 NPEC 10000 — — Times
Data hold time After 1000 times tDRP 30*2 — — Year Ta = +85°C
of NPEC
After 10000 times 1*2 — — Year
of NPEC
Note 1. Definition of reprogram/erase cycle: The reprogram/erase cycle is the number of erasing for each block. When the reprogram/
erase cycle is n times (n = 10000), erasing can be performed n times for each block. For instance, when 128-byte programming
is performed 16 times for different addresses in 2-Kbyte block and then the entire block is erased, the reprogram/erase cycle is
counted as one. However, programming the same address for several times as one erasing is not enabled (overwriting is
prohibited).
Note 2. This result is obtained from reliability testing.
Table 38.41 ROM (Flash Memory for Code Storage) Characteristics (2)
FCLK = 4 MHz FCLK = 32 MHz
Item Symbol Unit
Min. Typ. Max. Min. Typ. Max.
Peripheral clock notification command tPCKA — — 960 — — 120 µs
wait time
Table 38.42 ROM (Flash Memory for Code Storage) Characteristics (3)
medium-speed operating mode 1A
Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V
Temperature range for the programming/erasure operation: Ta = –40 to +105°C
FCLK = 4 MHz FCLK = 32 MHz
Item Symbol Unit
Min. Typ. Max. Min. Typ. Max.
Programming time 2 bytes tP2 — 0.19 4.3 — 0.12 2.0 ms
when NPEC ≤ 100 times
8 bytes tP8 — 0.19 4.4 — 0.12 2.0
128 bytes tP128 — 0.67 10.7 — 0.41 4.8
Programming time 2 bytes tP2 — 0.23 5.3 — 0.15 2.5 ms
when NPEC > 100 times
8 bytes tP8 — 0.23 5.4 — 0.15 2.5
128 bytes tP128 — 0.80 13.2 — 0.48 6.0
Erasure time 2 Kbytes tE2K — 13.0 92.8 — 10.5 29 ms
when NPEC ≤ 100 times
Erasure time 2 Kbytes tE2K — 15.9 176.9 — 12.8 60 ms
when NPEC > 100 times
Suspend delay time during programming tSPD — — 0.9 — — 0.8 ms
(in programming/erasure priority mode)
First suspend delay time during tSPSD1 — — 220 — — 120 μs
programming (in suspend priority mode)
Second suspend delay time during tSPSD2 — — 0.9 — — 0.8 ms
programming (in suspend priority mode)
Suspend delay time during erasing tSED — — 0.9 — — 0.8 ms
(in programming/erasure priority mode)
First suspend delay time during erasing tSESD1 — — 220 — — 120 μs
(in suspend priority mode)
Second suspend delay time during erasing tSESD2 — — 0.9 — — 0.8 ms
(in suspend priority mode)
FCU reset time tFCUR 20 μs or longer — — 20 μs or longer — — μs
and FCLK × 6 and FCLK × 6
or greater or greater
Table 38.43 ROM (Flash Memory for Code Storage) Characteristics (4)
medium-speed operating mode 1B
Conditions: VCC = AVCC0 = 1.62 to 3.6 V, VSS = AVSS0 = VREFL0 = 0 V
Temperature range for the programming/erasure operation: Ta = –40 to +105°C
FCLK = 4 MHz FCLK = 32 MHz*1
Item Symbol Unit
Min. Typ. Max. Min. Typ. Max.
Programming time 2 bytes tP2 — 0.25 5.0 — 0.21 2.8 ms
when NPEC ≤ 100 times
8 bytes tP8 — 0.25 5.3 — 0.21 3.0
128 bytes tP128 — 0.92 14.0 — 0.65 8.3
Programming time 2 bytes tP2 — 0.31 6.2 — 0.26 3.5 ms
when NPEC > 100 times
8 bytes tP8 — 0.31 6.6 — 0.26 3.7
128 bytes tP128 — 1.09 17.5 — 0.77 10.0
Erasure time 2 Kbytes tE2K — 21.0 113.6 — 18.5 46 ms
when NPEC ≤ 100 times
Erasure time 2 Kbytes tE2K — 25.6 220.6 — 22.5 90 (1000 times ≥ ms
when NPEC > 100 times NPEC > 100 times),
98 (10000 times ≥
NPEC > 1000 times)
Suspend delay time during programming tSPD — — 1.7 — — 1.6 ms
(in programming/erasure priority mode)
First suspend delay time during tSPSD1 — — 220 — — 120 μs
programming (in suspend priority mode)
Second suspend delay time during tSPSD2 — — 1.7 — — 1.6 ms
programming (in suspend priority mode)
Suspend delay time during erasing tSED — — 1.7 — — 1.6 ms
(in programming/erasure priority mode)
First suspend delay time during erasing tSESD1 — — 220 — — 120 μs
(in suspend priority mode)
Second suspend delay time during tSESD2 — — 1.7 — — 1.6 ms
erasing (in suspend priority mode)
FCU reset time tFCUR 20 μs or — — 20 μs or — — μs
longer and longer and
FCLK × 6 FCLK × 6
or greater or greater
Note 1. The operating frequency is 8 MHz (max.) when the voltage is in the range from 1.62 V to less than 2.7 V.
Note 1. The reprogram/erase cycle is the number of erasing for each block. When the reprogram/erase cycle is n times (n = 100000),
erasing can be performed n times for each block. For instance, when 8-byte programming is performed 16 times for different
addresses in 128-byte block and then the entire block is erased, the reprogram/erase cycle is counted as one. However,
programming the same address for several times as one erasing is not enabled (overwriting is prohibited).
Note 2. This result is obtained from reliability testing.
Note 1. The operating frequency is 8 MHz (max.) when the voltage is in the range from 1.62 V to less than 2.7 V.
tSPD
tSED
Keep-O: Output pins retain their previous values, and input pins become high-impedance.
Hi-Z: High-impedance
Note 1. Input is enabled if the pin is specified as the software standby canceling source while it is used as an external interrupt pin.
HD
*1
D
75 51
NOTE)
1. DIMENSIONS "*1" AND "*2"
76 50 DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
bp
b1
HE
E
c1
Symbol
c
Min Nom Max
D 13.9 14.0 14.1
E 13.9 14.0 14.1
Terminal cross section A2 1.4
HD 15.8 16.0 16.2
100 HE
26 15.8 16.0 16.2
ZE
A 1.7
1 25 A1 0.05 0.1 0.15
Index mark bp 0.15 0.20 0.25
ZD
F b1 0.18
S
c 0.09 0.145 0.20
c1 0.125
A2
A
0° 8°
c
e 0.5
y S *3 x 0.08
A1
e bp L
x
L1 y 0.08
ZD 1.0
Detail F
ZE 1.0
L 0.35 0.5 0.65
L1 1.0
HD
*1
D
48 33
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
49 32 INCLUDE TRIM OFFSET.
bp
b1
HE
E
c1
c
Symbol
Min Nom Max
D 9.9 10.0 10.1
64
E 9.9 10.0 10.1
17 Terminal cross section
A2
ZE
1.4
HD 11.8 12.0 12.2
1 16 HE 11.8 12.0 12.2
Index mark
ZD A 1.7
A1 0.05 0.1 0.15
bp 0.15 0.20 0.25
F
b1 0.18
S c 0.09 0.145 0.20
A2
c
A
c1 0.125
0° 8°
y S
e 0.5
A1
*3 L
e bp
x L1 x 0.08
y 0.08
Detail F
ZD 1.25
ZE 1.25
L 0.35 0.5 0.65
L1 1.0
HD
*1 D
48 33
NOTE)
1. DIMENSIONS "*1" AND "*2"
49 32 DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
bp
b1
c1
c
HE
E
*2 Reference Dimension in Millimeters
Symbol
Terminal cross section
Min Nom Max
D 13.9 14.0 14.1
E 13.9 14.0 14.1
A2 1.4
ZE
A2
ZD
A
Index mark
c
F b1 0.35
S c 0.09 0.145 0.20
A1
L c1 0.125
L1 0° 8°
e 0.8
y S
*3
Detail F x 0.20
e bp
x y 0.10
ZD 1.0
ZE 1.0
L 0.3 0.5 0.7
L1 1.0
HD
*1 D
36 25
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
37 24 2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
bp
b1
HE
c1
c
*2
Reference Dimension in Millimeters
Symbol
Min Nom Max
D 6.9 7.0 7.1
Terminal cross section
48 E 6.9 7.0 7.1
13
A2
ZE
1.4
HD 8.8 9.0 9.2
1 12
HE 8.8 9.0 9.2
ZD
Index mark A 1.7
A1 0 0.1 0.2
F bp 0.17 0.22 0.27
A2
A
b1 0.20
c
c 0.09 0.145 0.20
S
L c1 0.125
A1 0° 8°
L1
e 0.5
y S
*3
bp
Detail F x 0.08
e
x y 0.10
ZD 0.75
ZE 0.75
L 0.35 0.5 0.65
L1 1.0
Description
Rev. Date
Page Summary
0.51 May 24, 2012 — First edition issued
1.00 Dec 21, 2012 All FINEC pin deleted,
RTCb → RTCc, SCIc → SCIe, SCId → SCIf
IrDA Interface added
Terms, changed
Reset generated by the pin → RES# pin reset
Feature
35 IrDA, added
Low-power design and architecture, Real-time clock, Up to seven communications channels,
Operating temp. range, changed
1. Overview
37, 38 Table 1.1 Outline of Specifications:
General I/O ports, Event link controller (ELC),
Realtime clock (RTCc), Serial communications interfaces (SCIe, SCIf), IrDA, Power supply voltage/
Operating frequency, Supply current, Operating temperature, changed
39 Table 1.2 Comparison of Functions for Different Packages, changed
40 Table 1.3 List of Products, changed
Note 1, added
41 Figure 1.1 How to Read the Product Part No., Memory Capacity, and Package Type, changed
42 Figure 1.2 Block Diagram, changed
43, 44 Table 1.4 Pin Functions:
Power supply, On-chip emulator, Serial communications interface (SCIe), changed
47 Figure 1.4 Pin Assignments of the 64-Pin LQFP,
Figure 1.5 Pin Assignments of the 48-Pin LQFP, changed
48, 49 Table 1.5 List of Pins and Pin Functions (100-Pin LQFP), chaned
51 Table 1.6 List of Pins and Pin Functions (64-Pin LQFP), chaned
53 Table 1.7 List of Pins and Pin Functions (48-Pin LQFP), chaned
2. CPU
63 2.4 Data Types: description, chanegd
— 2.4.1 Integer, deleted
— 2.4.2 Bits, deleted
— 2.4.3 Strings, deleted
3. Operating Modes
85 3.2.3 System Control Register 1 (SYSCR1): Bit description, changed
87 Figure 3.1 Mode-Setting Pin Levels and Operating Modes, changed
5. I/O Registers
97 to 111 Table 5.1 List of I/O Registers, changed
Notes 1 and 2, added
8. Voltage Detection Circuit (LVDAa)
141 Table 8.3 Procedures for Setting up Monitoring against Vdet1, changed
141 Table 8.4 Procedures for Setting up Monitoring against Vdet1, changed
9. Clock Generation Circuit
155 9.2.3 Main Clock Oscillator Control Register (MOSCCR): Bit description, changed
163 9.2.11 Main Clock Oscillator Forced Oscillation Control Register (MOFCR): Description, changed
168 9.4.2 Handling of Pins when Sub-Clock is not Used: Description, changed
174, 175 9.7.5 Notes on Sub-Clock, changed
11. Low Power Consumption
194 11.2.4 Module Stop Control Register C (MSTPCRC), changed
196 Table 11.3 Relationship between Operating Power Control Mode, Operating Range, and Power
Consumption, changed
197 • Middle-Speed Operating Mode 1A and
• Middle-Speed Operating Mode 1B: Description, changed
197 Figure 11.2 Relationship between the Operating Voltages and Operating Frequencies in Middle-
Speed Operating Modes 1A and 1B, changed
198 • Low-Speed Operating Mode 1: Description, changed
200 11.2.6 Sleep Mode Return Clock Source Switching Register (RSTCKCR): Description, changed
Description
Rev. Date
Page Summary
1.00 Dec 21, 2012 203 11.2.9 HOCO Wait Control Register 2 (HOCOWTCR2), changed
204 11.2.10 Flash HOCO Software Standby Control Register (FHSSBYCR): Description, changed
206 11.5.1 Setting Operating Power Consumption Control Mode, changed
209 11.6.2.1 Transition to All-Module Clock Stop Mode: Note 5, added
14. Interrupt Controller (ICUb)
247 14.3.1 Interrupt Vector Table: Description, changed
248 Table 14.3 Interrupt Vector Table: Name, changed
15. Buses
— 15.4 Limitations, deleted
17. Data Transfer Controller (DTCa)
319 Figure 17.1 Block Diagram of DTC, changed
332 Figure 17.4 Operation Flowchart of the DTC, changed
347 17.8 Event Link Function, changed
18. Event Link Controller (ELC)
351 Table 18.1 ELC Specifications: Note 1, changed
351 Figure 18.1 Block Diagram of Event Link Controller, changed
353 18.2.2 Event Link Setting Register n (ELSRn) (n = 1 to 4, 10, 12, 15, 18, 20, 22, 24, 25):
Description, changed
353 Table 18.2 Correspondence between ELSRn Registers and Peripheral Functions: Note 1, added
354 Table 18.3 Correspondence between Event Signal Names Set in ELSRn.ELS[7:0] Bits and Signal
Numbers: 01010110 (56h), changed
355 Table 18.3 Correspondence between Event Signal Names Set in ELSRn.ELS[7:0] Bits and Signal
Numbers: 01101010 (6Ah), added
359 Table 18.4 Registers Related to Port Groups and Corresponding Port Numbers: Note 1, added
367 (7) Restrictions on Writing to PODR or PDBF by CPU, changed
369 18.3.6 Procedure for Linking Events: 7., changed
370 18.4.1 Setting the ELSRn Register, added
19. I/O Ports
371 19.1 Overview, chagned
381 19.3.8 Drive Capacity Control Register (DSCR): Description, changed
382 19.3.9 Port Switching Register A (PSRA), added
383 19.3.10 Port Switching Register B (PSRB), added
384 Table 19.3 Treatment of Unused Pins, changed
Notes 1 and 2, added
20. Multi-Function Pin Controller (MPC)
387 Table 20.1 Allocation of Pin Functions to Multiple Pins: Multi-function timer unit 2 MTU4, changed
389 Table 20.1 Allocation of Pin Functions to Multiple Pins: Serial communications interface, changed
393 to 411 20.2.2 P07 Pin Function Control Register (P07PFS) to
20.2.14 PJn Pin Function Control Registers (PJnPFS) (n = 1, 3): Register names, chagned
401 Table 20.12 Register Settings for Input/Output Pin Function in 100-Pin: 1010b, changed
402 Table 20.13 Register Settings for Input/Output Pin Function in 64-Pin: 1010b, changed
402 Table 20.14 Register Settings for Input/Output Pin Function in 48-Pin: 1010b, changed
405 Table 20.18 Register Settings for Input/Output Pin Function in 100-Pin: 1010b, changed
405 Table 20.19 Register Settings for Input/Output Pin Function in 64-Pin: 1010b, changed
412 20.3.1 Procedure for Specifying Input/Output Pin Function, changed
21. Multi-Function Timer Pulse Unit 2 (MTU2a)
418 Figure 21.1 Block Diagram of MTU, changed
440 • TIER (MTU5): Address, changed
501 Figure 21.36 Example of Reset-Synchronized PWM Mode Operation (When TOCR1’s OLSN = 1
and OLSP = 1), chagned
507 (b) Register Operation: Description, changed
515 (j) Method for Generating PWM Output in Complementary PWM Mode: Description, changed
515 (k) 0% and 100% Duty Cycle Output in Complementary PWM Mode, page changed
539 Figure 21.79 Delay in Dead Time in Complementary PWM Mode Operation, changed
540 Figure 21.81 Example of Motor Control Circuit Configuration, changed
541 Figure 21.82 MTU5.TCNT Capture at Crest and/or Trough in Complementary PWM Mode
Operation, changed
545 (4) A/D Converter Activation by Input Capture or Compare Match with MTU0.TGRA or
MTU0.TGRB, changed
Description
Rev. Date
Page Summary
1.00 Dec 21, 2012 559 21.6.9 Contention between TGR Read Operation and Input Capture: Description, changed
568 21.6.24 Point for Caution Regarding MTU5.TCNT and MTU5.TGR Registers, added
574 to 599 (1) Operation when Error Occurs in Normal Mode and Operation is Restarted in Normal Mode to
(29) Operation when Error Occurs in Reset-Synchronized PWM Mode and Operation is Restarted
in Reset-Synchronized PWM Mode: Description changed
Figure 21.126 Error Occurrence in Normal Mode, Recovery in Normal Mode to Figure 21.154 Error
Occurrence in Reset-Synchronized PWM Mode, Recovery in Reset-Synchronized PWM Mode,
changed
601 (3) Counter restart operation: Description, changed
— Figure 21.113 Contention between TGR Read Operation and Input Capture (MTU5), deleted
— Figure 21.124 Example of Synchronous Clearing (when Condition 2 Applies), deleted
25. Realtime Clock (RTCc)
656 25.1 Overview, Table 25.1 Specifications of RTC, Note 1, changed
657 Figure 25.1 Block Diagram of RTC, changed
6547 Table 25.2 Pin Configuration of RTC: RTCOUT, changed
658 to 679 25.2.1 64-Hz Counter (R64CNT) to 25.2.20 Time Error Adjustment Register (RADJ), changed
680 Figure 25.2 Outline of Initial Settings after Power-On, changed
681 Figure 25.3 Clock and the count mode Setting Procedure, changed
682 Figure 25.4 Setting the Time, changed
682 25.3.4 30-Second Adjustment: Description, changed
684 25.3.6 Alarm Function: Description, changed
685, 686 25.3.8.1 Automatic Adjustment, changed
689 (3) Carry interrupt (CUP): Description, changed
689 Figure 25.10 Carry Interrupt (CUP) Timing Chart, changed
690 25.5.1 Register Writing during Counting: Description, changed
690 25.5.2 Use of Periodic Interrupts and 25.5.3 RTCOUT (1-Hz/64-Hz) Clock Output, changed
691 25.5.5 Points for Caution when Writing to and Reading from Registers, changed
691 25.5.6 Changing Count Mode, added
— 25.5.6 Initialization Procedure when the Realtime Clock is not to be Used, deleted
26. Independent Watchdog Timer (IWDTa)
693 Table 26.1 Specifications of IWDT: Note 1, changed
708 26.3.3 Refresh Operation, changed
709 26.3.7 Reading the Down-Counter Value, changed
— Figure 26.7 IWDT Refresh Operation Waveforms (IWDTCR.CKS[3:0] = 0010b,
IWDTCR.TOPS[1:0] = 01b), deleted
— Figure 26.9 Processing for Reading IWDT Down-Counter Value (IWDTCR.CKS[3:0] = 0010b,
IWDTCR.TOPS[1:0] = 11b), deleted
27. Serial Communications Interface (SCIe, SCIf)
711 Table 27.1 Specifications of SCIe: Asynchronous mode, changed
712 Table 27.2 Specifications of SCIf: Asynchronous mode, changed
724 27.2.6 Serial Control Register (SCR): Note 2, changed
729 27.2.7 Serial Status Register (SSR), changed
738 Table 27.15 BRR Settings for Various Bit Rates (Clock Synchronous Mode, Simple SPI Bus Mode):
Note 1, changed
741, 742 27.2.10 Serial Extended Mode Register (SEMR), changed
742 Figure 27.4 Example of Average Transfer Rate Setting when TMR Clock is Input, changed
753 27.2.20 Control Register 2 (CR2): Description, changed
764 27.3 Operation in Asynchronous Mode, changed
770 Figure 27.10 Example of Serial Transmission Flowchart in Asynchronous Mode, changed
774 Figure 27.14 Example of Serial Reception Flowchart (2) (Asynchronous Mode), changed
776 Figure 27.16 Example of Multi-Processor Serial Transmission Flowchart, changed
779 Figure 27.19 Example of Multi-Processor Serial Reception Flowchart (2), changed
787 Figure 27.26 Example of Serial Reception Flowchart (Clock Synchronous Mode), changed
793 27.6.5 Initialization of the SCI (Smart Card Interface Mode): 6., changed
826 Figure 27.63 Example of Operations with the Digital Filter, changed
837 27.13.2 Break Detection and Processing, changed
837 27.13.6 Restrictions on Clock Synchronous Transmission, changed
838 27.13.9 SCI Operations during Low Power Consumption State: (1) Transmission, changed
Description
Rev. Date
Page Summary
1.00 Dec 21, 2012 839 Figure 27.69 Example of Flowchart for Transition to Software Standby Mode during Transmission,
changed
842 27.13.11 Limitation on Using Simple SPI Bus Mode, changed
28. IrDA Interface
844 to 848 Added
29. I2C Bus Interface (RIIC)
852 Table 29.3 Register Allocation for 16-Bit Access, added
881 29.2.18 Timeout internal counter (TMOCNT), changed
883 Figure 29.5 Example of RIIC Initialization Flowchart, changed
885 Figure 29.6 Example of Master Transmission Flowchart, changed
890 Figure 29.10 Example of Master Reception Flowchart (7-Bit Address Format), changed
894 Figure 29.14 Example of Slave Transmission Flowchart, changed
897 Figure 29.17 Example of Slave Reception Flowchart, changed
30. Serial Peripheral Interface (RSPI)
928 30.1 Overview, changed
937 30.2.4 RSPI Status Register (SPSR): Bit description, changed
1004 Table 30.13 Interrupt Sources of RSPI: RSPI idle, changed
1006 30.4.5 Transmit End Event Output, changed
32. 12-Bit A/D Converter (S12ADb)
1054 32.7.7 Allowable Impedance of Signal Source, changed
1054 Table 32.9 Specifications of Analog Input Pins: Max., changed
Notes 1 and 2, changed
34. Data Operation Circuit (DOC)
1073 Table 34.1 Specifications of Data Operation Circuit, changed
1073 Figure 34.1 Block Diagram of Data Operation Circuit, changed
1079 34.5 Event Link Output, 34.5.1 Interrupt Handling and Event Linking, added
36. ROM (Flash Memory for Code Storage)
1093 36.2.8 Flash P/E Mode Entry Register (FENTRYR): Bit description, changed
1114 Figure 36.11 Using the Peripheral Clock Notification Command, changed
1145 (13) Boot Program Status Inquiry, changed
37. E2 DataFlash Memory (Flash Memory for Data Storage)
1158 Table 37.1 Specifications of E2 DataFlash Memory: Protection, changed
38. Electrical Characteristics
1184 to Added
1236
1.10 Dec 20, 2013 All PLQP0064GA-A 14×14 mm, 0.8-mm pitch added
Features
35 ■ Operating temp. range changed
1. Overview
38 Table 1.1 Outline of Specifications changed, Note 1 added
40 Table 1.3 List of Products changed, Note added
41 Figure 1.1 How to Read the Product Part No., Memory Capacity, and Package Type changed
3. Operating Modes
85 3.2.3 System Control Register 1 (SYSCR1) Note added
6. Resets
113 Table 6.2 Targets Initialized by Each Reset Source Note1 added
116 6.2.2 Reset Status Register 1 (RSTSR1) changed
117 6.2.4 Software Reset Register (SWRR) Note added
8. Voltage Detection Circuit (LVDAa)
133 to 137 8.2.1 Voltage Monitoring 1 Circuit/Comparator A1 Control Register 1 (LVD1CR1) to
8.2.5 Voltage Monitoring Circuit/Comparator A Control Register (LVCMPCR) Note added
138 8.2.6 Voltage Detection Level Select Register (LVDLVLR) changed, Note added
139, 140 8.2.7 Voltage Monitoring 1 Circuit/Comparator A1 Control Register 0 (LVD1CR0) and
8.2.8 Voltage Monitoring 2 Circuit/Comparator A2 Control Register 0 (LVD2CR0) Note added
9. Clock Generation Circuit
152, 153 9.2.1 System Clock Control Register (SCKCR) changed, Note added
154 9.2.2 System Clock Control Register 3 (SCKCR3) changed, Note added
155 9.2.3 Main Clock Oscillator Control Register (MOSCCR) changed, Note added
Description
Rev. Date
Page Summary
1.10 Dec 20, 2013 156 to 160 9.2.4 Sub-Clock Oscillator Control Register (SOSCCR) to
9.2.8 High-Speed On-Chip Oscillator Control Register 2 (HOCOCR2) Note added
161 9.2.9 Oscillation Stop Detection Control Register (OSTDCR) changed, Note added
162 9.2.10 Oscillation Stop Detection Status Register (OSTDSR) changed, Note added
163 9.2.11 Main Clock Oscillator Forced Oscillation Control Register (MOFCR) Note added
164 9.2.12 High-Speed On-Chip Oscillator Power Supply Control Register (HOCOPCR) changed,
Note added
170 Figure 9.8 Flow of Recovery from Detection of Oscillator Stop changed
11. Low Power Consumption
190 to 194 11.2.1 Standby Control Register (SBYCR) to 11.2.4 Module Stop Control Register C (MSTPCRC)
Note added
195 11.2.5 Operating Power Control Register (OPCCR) changed, Note added
200 to 204 11.2.6 Sleep Mode Return Clock Source Switching Register (RSTCKCR) to
11.2.10 Flash HOCO Software Standby Control Register (FHSSBYCR) Note added
14. Interrupt Controller (ICUb)
260 14.4.5 Multiple Interrupts added, 14.4.6 Fast Interrupt changed
16. DMA Controller (DMACA)
309 Figure 16.12 Register Setting Procedure changed
17. Data Transfer Controller (DTCa)
329 17.3 Sources of Activation changed
339 Figure 17.8 Chain Transfer Operation changed
349 17.10.1 Transfer Data Start Address: Title changed
18. Event Link Controller (ELC)
351 Table 18.1 ELC Specifications changed
19. I/O Ports
384 Table 19.3 Treatment of Unused Pins changed
20. Multi-Function Pin Controller (MPC)
385 Table 20.1 Allocation of Pin Functions to Multiple Pins changed
21. Multi-Function Timer Pulse Unit 2 (MTU2a)
451 21.2.17 Timer Output Master Enable Registers (TOER), Note 1 changed
510 (g) PWM Cycle Setting changed
25. Realtime Clock (RTCc)
673 25.2.17 RTC Control Register 1 (RCR1) changed
674 to 677 25.2.18 RTC Control Register 2 (RCR2) changed
26. Independent Watchdog Timer (IWDTa)
708 26.3.4 Status Flags changed
27. Serial Communications Interface (SCIe, SCIf)
782 Figure 27.21 Example of SCI Initialization Flowchart (Clock Synchronous Mode) changed
799 (a) At transition from smart card interface mode to software standby mode changed
843 27.13.14 Note on Transmit Enable Bit (TE bit) added
29. I2C Bus Interface (RIIC)
849 to 928 ICRXI → RXI, ICTEI → TEI, ICTXI → TXI, ICEEI → EEI changed
852, 853 29.2.1 I2C Bus Control Register 1 (ICCR1) changed
854 29.2.2 I2C Bus Control Register 2 (ICCR2) changed
885 Figure 29.6 Example of Master Transmission Flowchart changed
890 Figure 29.10 Example of Master Reception (7-Bit Address Format, 1 or 2 bytes) added
893 Figure 29.14 Master Receive Operation Timing (3) (when RDRFS = 0) changed
918 29.11.1 Timeout Function changed
30. Serial Peripheral Interface (RSPI)
937 30.2.4 RSPI Status Register (SPSR) changed
940 (a) Writing changed
989 Figure 30.34 Example of Initialization Flowchart in Master Mode (SPI Operation) changed
1000 Figure 30.45 Example of Initialization Flowchart in Master Mode (Clock Synchronous Operation)
changed
1006 (1) Mode Fault changed
32. 12-Bit A/D Converter (S12ADb)
1040 32.3.2.2 Channel Selection and Self-Diagnosis changed
1044 32.3.3.2 Channel Selection and Self-Diagnosis changed
Description
Rev. Date
Page Summary
1.10 Dec 20, 2013 1048 Figure 32.11 Scan Conversion Timing (Activated by Software, or Triggers from the MTU or ELC),
Figure 32.12 Scan Conversion Timing (Activated by ADTRG0#) changed
33. Comparator A
1060 to 33.2.1 Voltage Monitoring 1 Circuit/Comparator A1 Control Register 1 (LVD1CR1) to
1066 33.2.7 Voltage Monitoring 2 Circuit/Comparator A2 Control Register 0 (LVD2CR0) Note added
34. Data Operation Circuit (DOC)
1077 34.3.1 Data Comparison Mode Note1 added
36. ROM (Flash Memory for Code Storage)
1116 (4) Programming changed: Title changed
1127 Figure 36.20 Suspension during Erasure (Programming/Erasure Priority Mode): Title changed
37. E2 DataFlash Memory (Flash Memory for Data Storage)
1173 Table 37.4 FCU Command Formats (Commands Dedicated to the E2 DataFlash Memory) changed
1175 (2) Programming changed
38. Electrical Characteristics
1187 Table 38.4 DC Characteristics (3) changed
1193 Table 38.8 DC Characteristics (7) added
1194 Table 38.13 Permissible Output Currents (1) changed, Table 38.14 Permissible Output Currents (2)
added
1195 Table 38.15 Output Values of Voltage (1) changed, Table 38.16 Output Values of Voltage (2) added
1211 Table 38.26 Timing of On-Chip Peripheral Modules (1) changed
1223 Table 38.31 A/D Conversion Characteristics (1) changed
1224 Table 38.34 A/D Conversion Characteristics (2) changed
1229 Table 38.38 Power-on Reset Circuit and Voltage Detection Circuit Characteristics (2) changed
RX220 Group
R01UH0292EJ0110