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FPGA DESIGN OF STOPWATCH

Technical Report · January 2021

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FPGA DESIGN OF STOPWATCH

Milica Maljevic, Radovan Rabrenovic and Radovan Stojanovic

Introduction .................................................................................................................................... 3

Block Diagram ................................................................................................................................. 4

Main File ...................................................................................................................................... 5

FSM .............................................................................................................................................. 6

HEX- Decoder .............................................................................................................................. 8

CLK ............................................................................................................................................... 9

BCD Count enable ....................................................................................................................... 9

BCD Count ................................................................................................................................. 10

Waveform diagram ....................................................................................................................... 11

Block scgeme................................................................................................................................. 12

Demonstration link ....................................................................................................................... 12

Reference ...................................................................................................................................... 13

1
Abstract

Timer`s (stopwatch) function is to find out how long it takes in an activity. Here we have tried to
realize a timer of reasonable accuracy and reliability. This timer project is a software and
hardware co-design. The time will be shown on the FPGA board and on the seven-segment
display. The system will be modeled in VHDL (Very-high-speed integrated circuit Hardware
Description Language) and implemented on the Altera DE2 Cyclone II FPGA board.

Keywords: VHDL, Timer, Altera DE2 FPGA Boards

2
Introduction
The timer we designed is a time-keeping device that is meant to measure the time elapsed from
the start to end of any event. The timer has several different functions including both start and
stop reset and is able to clear the hundredth of a second output.
We used the Altera DE2 Cyclone II FPGA Board. The board was used to implement our
timer, and seven segment display on it was used to display the elapsed time. The computing
language that we used to write the program is VHDL. For the functions, we used three (start, stop
and reset) switches and a 50GHz clock. The elapsed time will be displayed on the seven segment
display. When the pause switch is activated, the stopwatch will stop running. When the last
function reset is activated, all digits change to zeros. This project helped us to improve our skills
in VHDL programming, and help us gain more experience working with an FPGA.

3
Block diagram
To simplify the development of complex designs, the design is broken up in to a number of
smaller, less complex blocks. This approach is called "Divide-and-Conquer".
The FPGA will run on a high clock frequency. Hence, a single button press of the user will lead to
an active signal at the input of our blocks for many thousand or even millions of clock cycles.
Thus, an edge detection circuit is needed to ensure that each acknowledge of a button translates
only to a signal being active for one clock cycle. To control the different states of the stop watch,
an FSM (Finite-State-Machine) has to be employed in the design and subsequently this FSM has
to trigger a counter counting the time. This binary value has to be decoded into a representation
matching the inputs of the seven-segment driver.

Fig. 1 Block diagram of the timer

Clock and reset signals have been omitted for simplicity, however, we have to highlight that all
sequential circuits need to be reseted using the system reset signal. Throughout, all clocked gates
should be sensitive to the rising edge of the clock.

4
Implementation

The task has been implementing considering structural modelling style in HDL. The Lab main is
the main file while BCDCount, HexDecoder, FSM, CLK 100Hz are the component files.
The HEX decoder file basically contains the binary to HEX conversion while in FSM file the start
stop reset algorithm is implemented, BCDCount file contains the BCD number count while the
clk100HZ contain the clock input and output and all the subfiles are then called in the main file
using structural programming.

Main File
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;
ENTITY labmain IS
PORT (start,stop,reset,clock_50 : IN STD_LOGIC;
HEX3,HEX2,HEX1,HEX0 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) );
END labmain;
ARCHITECTURE structure OF labmain IS
COMPONENT BCDcount
PORT(clock,reset,enable :IN STD_LOGIC;
carry :OUT STD_LOGIC;
BCD :OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
COMPONENT CLK100Hz
PORT(clk_in :IN STD_LOGIC;
clk_out:OUT STD_LOGIC);
END COMPONENT;
COMPONENT HEXdecoder
PORT(Digin :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Segout :OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END COMPONENT;
COMPONENT fsm
PORT(clock,start,stop,reset :IN STD_LOGIC;
clear,enable :OUT STD_LOGIC);
END COMPONENT;
SIGNAL clear,enable,clk100 : STD_LOGIC;

5
SIGNAL carry2,carry1,carry0 : STD_LOGIC;
SIGNAL BCD3,BCD2,BCD1,BCD0 : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
fsm1 : fsm PORT MAP(clock_50,start,stop,reset,clear,enable);
clkdvd : clk100Hz PORT MAP(clock_50, clk100);
BCDC0 : BCDcount PORT MAP(clk100,clear,enable,carry0,BCD0);
BCDC1 : BCDcount PORT MAP(carry0,clear,'1',carry1,BCD1);
BCDC2 : BCDcount PORT MAP(carry1,clear,'1',carry2,BCD2);
BCDC3 : BCDcount PORT MAP(carry2,clear,'1',OPEN,BCD3);

HEXD0 : HEXdecoder PORT MAP(BCD0,HEX0);

FSM
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;

ENTITY fsm IS
PORT(clock,start,stop,reset :IN STD_LOGIC;
clear,enable :OUT STD_LOGIC);
END fsm;
ARCHITECTURE Behavior OF FSM IS
TYPE state_type IS (nocount,nocountreset,count,countreset);
SIGNAL y: state_type;
BEGIN
PROCESS(clock)
BEGIN
IF(clock'EVENT AND clock='1') THEN
CASE y IS
WHEN nocount=>
IF reset='0' THEN
y<=nocountreset;
ELSIF start='0' THEN

6
y<=count;
ELSE
y<=nocount;
END IF;
WHEN nocountreset=>
IF reset='1' THEN
y<=nocount;
ELSE
y<=nocountreset;
END IF;
WHEN count=>
IF reset='0' THEN
y<=countreset;
ELSIF stop='0' THEN
y<=nocount;
ELSE
y<=count;
END IF;
WHEN countreset=>
IF reset='1' THEN
y<=count;
ELSE
y<=countreset;
END IF;
END CASE;
END IF;
END PROCESS;
WITH y SELECT
clear<= '0' WHEN nocount,
'1' WHEN nocountreset,
'0' WHEN count,
'1' WHEN countreset,
'0' WHEN OTHERS;
WITH y SELECT
enable<='0' WHEN nocount,
'0' WHEN nocountreset,
'1' WHEN count,
'1' WHEN OTHERS;

7
end Behavior;

HEX DECODER

library ieee;
use ieee.std_logic_1164.all;
entity HEXdecoder is
port(
Digin :in std_logic_vector(3 downto 0);
Segout :out std_logic_vector(6 downto 0));
end HEXdecoder;
architecture behavior of HEXdecoder is
begin
with Digin select
Segout <= "1000000" when "0000",
"1111001" when "0001",
"0100100" when "0010",
"0110000" when "0011",
"0011001" when "0100",
"0010010" when "0101",
"0000010" when "0110",
"1111000" when "0111",
"0000000" when "1000",
"0011000" when "1001",
"0001000" when "1010",--A
"0000011" when "1011",--b
"0100111" when "1100",--C
"0100001" when "1101",--d
"0000110" when "1110",--E
"0001110" when "1111",--F
"0110110" when others;--weird character
end behavior;

8
CLK

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk100Hz is
Port (
clk_in : in STD_LOGIC;
clk_out: out STD_LOGIC);
end clk100Hz;
architecture Behavioral of clk100Hz is
signal temporal: STD_LOGIC;
signal counter : integer range 0 to 249999 := 0;
begin
frequency_divider: process (clk_in) begin
if (clk_in'event and clk_in = '1') then
if (counter = 249999) then
temporal <= NOT(temporal);
counter <= 0;
else
counter <= counter + 1;
end if;
end if;
end process;
clk_out <= temporal;
end Behavioral;

BCD Counter enable

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;

ENTITY BCDcountenable IS
PORT ( clock,reset,enable, E : IN STD_LOGIC ;
carry : OUT STD_LOGIC ;
BCD0 : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
END BCDcountenable ;

9
ARCHITECTURE Behavior OF BCDcountenable IS
BEGIN
PROCESS ( clock )
BEGIN
IF (clock'EVENT AND clock = '1') THEN
IF Reset = '1' THEN
BCD0 <= "0000" ;
ELSIF E = '1' THEN
IF BCD0 = "1001" THEN
BCD0 <= "0000" ;
Carry <= '1';
ELSE
BCD0 <= BCD0 + '1';
carry <= '0';
END IF;
END IF;
END IF;
END PROCESS;
END Behavior ;

BCD Count

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;
ENTITY BCDcount IS
PORT ( Clock : IN STD_LOGIC ;
Reset : IN STD_LOGIC ;
Enable : IN STD_LOGIC ;
Carry : OUT STD_LOGIC ;
BCD : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
END BCDcount ;
ARCHITECTURE Behavior OF BCDcount IS
signal count: std_logic_vector(3 downto 0);
BEGIN
PROCESS (Reset, Clock )
BEGIN

10
IF Reset = '1' THEN
count <= "0000";
Carry <= '0';
ELSIF Clock'EVENT AND Clock = '1' THEN
IF Enable = '1' THEN
IF count = "1001" THEN
count <= "0000";
Carry <= '1';
ELSE
count <= count+1;
Carry <= '0';
END IF;
END IF;
END IF;
END PROCESS;
BCD<=count;
END Behavior ;

Waveform diagram

11
Block scheme

Demonstartion link

https://youtu.be/GI0OSW3JfbY

12
Reference
[1] STOJANOVIĆ, Radovan D. AUTOMATIZOVANO PROJEKTOVANJE DIGITALNIH SISTEMA (VHDL I
FPGA).

[2] https://www.terasic.com.tw/attachment/archive/226/DE2_70_User_manual_v105.pdf

13
 14

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