Scribd Logo
Upload

Welcome to Scribd!

  • 85 views

    Exp 2

    Uploaded by

    tahia
    The document describes an experiment to design and verify DTL logic gates (NOR, NOT, and NAND) using transistors and diodes. It provides the theory of DTL logic, circuit diagrams and truth tables for each gate, equipment needed, and the experimental procedure to build and test the gates. Students are asked to construct the circuits, input different combinations, observe outputs, measure voltages, and verify the truth tables.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd

    Exp 2

    Uploaded by

    tahia
    85 views4 pages
    The document describes an experiment to design and verify DTL logic gates (NOR, NOT, and NAND) using transistors and diodes. It provides the theory of DTL logic, circuit diagrams and truth tables for each gate, equipment needed, and the experimental procedure to build and test the gates. Students are asked to construct the circuits, input different combinations, observe outputs, measure voltages, and verify the truth tables.

    Original Title

    Exp-2

    Copyright

    © © All Rights Reserved

    Available Formats

    DOCX, PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    The document describes an experiment to design and verify DTL logic gates (NOR, NOT, and NAND) using transistors and diodes. It provides the theory of DTL logic, circuit diagrams and truth tables for each gate, equipment needed, and the experimental procedure to build and test the gates. Students are asked to construct the circuits, input different combinations, observe outputs, measure voltages, and verify the truth tables.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    85 views4 pages

    Exp 2

    Uploaded by

    tahia
    The document describes an experiment to design and verify DTL logic gates (NOR, NOT, and NAND) using transistors and diodes. It provides the theory of DTL logic, circuit diagrams and truth tables for each gate, equipment needed, and the experimental procedure to build and test the gates. Students are asked to construct the circuits, input different combinations, observe outputs, measure voltages, and verify the truth tables.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 4

    University of Asia Pacific (UAP)

    Dept. of Electrical and Electronic Engineering (EEE)


    EEE 222: Electrical and Electronics Engineering II Lab
    Experiment No- 02
    Design and Verification of DTL Logic Gates

    Objective:
    The objective of this experiment is:
     To build and study logic gates: NOR, NOT and NAND from bipolar transistors using
    the DTL logic family.
     To verify the truth table of constructed gates.

    Theory and Methodology:


    Diode-Transistor Logic, or DTL, refers to the technology for designing and fabricating digital
    circuits wherein logic gates employ both diodes and transistors. DTL offers better noise margins and
    greater fan-outs than RTL, but suffers from low speed, especially in comparison to TTL.
    RTL allows the construction of NOR gates easily, but NAND gates are relatively more difficult to get
    from RTL. DTL, however, allows the construction of simple NAND gates from a single transistor,
    with the help of several diodes and resistors.

    NOT gate:
    When high voltage is applied as input to the inverter which is V cc = +5V. D2 is reverse biased but D1
    is forward biased from the supply V CC which makes the transistor Q1 receives the required amount of
    potential to move into ON condition. When the transistor moves into the ON state, the voltage at B
    terminal will have a path to the earth via resistor R1.
    Now, the transistor will be in short-circuited condition, so that all the V cc voltage gets dropped at R2
    and no voltage appears at the output terminal which is ideally ‘0’ volts.
    In general, there happens some amount of voltage drop at the emitter and collector terminals which is
    approximately 0.2V.
    When a low voltage (0 V) is applied as input to the inverter then D2 is forward biased which makes
    D1 open, so transistor’s base terminal is provided with 0 V or it is grounded. The NPN transistor will
    switch off because there is no base current. As a result, there is no current flow through the transistor.
    Therefore, Vcc will appear at output terminal.

    Figure 1: (a) NOT gate using DTL Logic Circuit (b) Truth Table and symbol.
    NAND gate:
    When both the inputs A and B are at 0V or logic 0, it drives D1 to be reverse biased and thus, the
    transistor will not conduct. Due to this, the voltage +VCC will appear at the output Y. Hence the output
    is logic 1 or logic HIGH at terminal Q.
    When both inputs “A” and “B” are “HIGH” then DA and DB are both reverse-biased and D1
    conducts from the supply which makes the transistor to be in saturated “ON” state and a state
    “LOW” appears at the output (Q). Turning any of the inputs to logic “LOW” will drive the relative
    transistor to the “OFF” state and pulls the output (Q) high to VCC.

    Figure 2: (a) NAND gate using DTL Logic Circuit (b) Truth Table and symbol

    NOR gate
    In the DTL NOR gate, When A=0 and B=0. Then the diodes D2 and D3 are off so transistor Q1
    remains in OFF state, and the voltage at the output is HIGH or 5v.
    If any one of input A or B is high or both are high, then Q1 will be on and then no voltage drop
    occurs between collector and emitter. So Q1 will remain in turn on and therefore output will LOW.

    Figure 3: (a) NOR gate using DTL Logic Circuit (b) Truth Table and symbol
    Equipment:
    1. Transistors - 3pc
    2. Resistors - 5pc
    3. Power Supply
    4. Trainer Board
    5. Multi-meter
    6. Connecting Wires
    7. Diodes
    Circuit Diagram:

    Figure 1: NOT gate

    Figure 2: NAND gate

    Figure 3: NOR gate

    Experimental Procedure:
    a) Construct the circuit shown in (a), (b) and (c).
    b) For different input combinations, find out the logical output by observing the LED and
    measure the value of output voltage using DMM.
    c) Verify the truth table for each gate.
    Data Table:
    a) Data for NOT gate:
    Input Output Logical Output Voltage
    1
    0

    b) Data for NAND gate:


    Input A Input B Output Logical Output Voltage
    0 0
    0 1
    1 0
    1 1

    b) Data for NOR gate:


    Input A Input B Output Logical Output Voltage
    0 0
    0 1
    1 0
    1 1

    Discussion:
    Discuss whether you have managed to achieve your desired results.

    You might also like