Mpa 4150
Mpa 4150
SERVICE MANUAL
ECLER
CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4
VOL
4
5
6 SP CLIP
VOL
4
5
6 SP CLIP
VOL
4
5
6 SP CLIP
VOL
4
5
6 SP CLIP TH MPA 4-150 POWER
3 7 3 7 3 7 3 7 MULTICHANNEL
POWER AMPLIFIER
2 8 2 8 2 8 2 8 OFF
1 9 1 9 1 9 1 9
0 10 0 10 0 10 0 10
ON
SERVICE MANUAL MPA4-150
INDEX
- BLOCK DIAGRAM
- SCHEMATICS
- TECHNICAL CHARACTERISTICS
- WIRING DIAGRAM
- MECHANICAL DIAGRAM
- PACKING DIAGRAM
author: J. Colomines date: 050401
ECLER approved: title:
project: EP05-99
FUNCTIONING DESCRIPTION
product: MPA4-150
The amplifying stage basic structure is actually the one commonly used until now, this is, a
push-pull mounted A-B class amplifier, using P-type (IRFP9240) and N-type (IRFP240) mosfets.
The system's controlling core is a NE5534 OpAmp, which is internally compensated in order to
obtain an amplifying gain ratio equal or greater than 3. The amplifier's feedback runs through a
resistor and a capacitor associated to the OpAmp's non-inverting input.
Transistors BF471 and BF472 are common-base configured, becoming actually a current
source structure. They accomplish a dual function: on one hand, they polarise the mosfet's
gate-source junction, keeping them on their conduction knee. On the other hand, they carry out
the OpAmp's output voltage variations, referred to signal ground.
The polarisation current adjustment is fixed by a 2k5 trimming potentiometer connected to the
BF transistors base. This current is added to the current source's output, which passes through
the BF-transistors load resistors. The bias current stability against temperature is fixed through
the BD437 transistors. Their temperature- dependent base-emitter voltage curve is used to alter
adequately the current source's reference voltage. As a consequence, if the temperature rises,
the reference voltage decreases, thus the gate-source voltage also does, and finally the bias
current also decreases.
The Zobel network, formed by a resistor-inductor-capacitor group, and which is located at the
amplifier's output, intends to keep the amplifier's load impedance as constant as possible, no
matter which load is connected to the stage's output, or which signal frequency is to be
amplified, in order to prevent an inverted-phase feedback signal.
In order to avoid a DC offset on the output signal, a diac-triac tandem system is used, which
shorts the output to signal ground when the DC level is enough to get the diac triggered. To
prevent this from happening while carrying audio signal (sine-wave, music), the diac's reference
voltage is taken from a filter formed by resistor 33k2 and capacitor 1µ.
The protection circuitry supervises at any time the power consumed by the MOSFETS. The
circuitry basically consists on two sections: MOSFET's drain current (Id) monitoring and drain-
source voltage (Vds) monitoring.
When Id exceeds a fixed values a control transistor in every branch starts to conduct like a
switch, apliying a parallel resistor to BF's load resisitor, reduring the gate-source voltage, and
also reducing Id.
If the MOSFET's drain-source voltage (Vds) drops too low, a second circuitry actuates to alter
the control-transistor's triggering level, obtaining a SOA-like curve section and a current stage,
which can be adjusted adequately in order to maintain the MOSFET's power consumption as
close as possible to its SOA.
The amplifying stage basic structure is actually the one commonly used until now, this
is, a push-pull mounted A-B class amplifier, using P-type (IRFP9240) and N-type
(IRFP240) mosfets.
In order to avoid a DC offset on the output signal, a diac-triac tandem system is used,
which shorts the output to signal ground when the DC level is enough to get the diac
triggered. To prevent this from happening while carrying audio signal (sine-wave,
music), the diac's reference voltage is taken from a filter formed by resistor 33k2 and
capacitor 1µ.
The protection circuitry supervises at any time the power consumed by the MOSFETS.
The circuitry basically consists on two sections: MOSFET's drain current (Id) monitoring
and drain-source voltage (Vds) monitoring.
When Id exceeds a fixed values a control transistor in every branch starts to conduct
like a switch, apliying a parallel resistor to BF's load resisitor, reduring the gate-source
voltage, and also reducing Id.
If the MOSFET's drain-source voltage (Vds) drops too low, a second circuitry actuates
to alter the control-transistor's triggering level, obtaining a SOA-like curve section and
a current stage, which can be adjusted adequately in order to maintain the MOSFET's
power consumption as close as possible to its SOA.
Sheet 1 of 2
author: Queralt 000719 FUNCTIONING DESCRIPTION
ECLER approved:
date:
title:
EP05-99
num: 52.0006 version: 01.00
Sheet 2 of 2
PRINTED CIRCUIT 11.0765.03.00
TECHNICAL BRIEFING
product:
Involved series:
When this potentiometer is being replaced, after soldering it on the printed circuit
board, the two leads should be shorted as shown in the picture, in order to ensure a
correct performance depending on the available service part.
- Set the following front-end selector switches to the positions as listed bellow:
- IN1/IN1+IN2 to IN1
- IN2/LINK IN1 to LINK IN1
- LP FILTER ON/OFF to OFF
- ST/B IN1/B IN1+IN2 to ST
- IN3/LINK IN1 to LINK IN1
- IN4/LINK IN2 to LINK IN2
- ST/BRIDGE to ST
- HP FILTER ON/OFF to OFF
VERIFICATION
- Switch the tested unit's Power main switch to ON. Verify that the power on LED is
lit.
- Set the signal generator to ON. At this point, all Signal Present LED's should light up.
- Turn up channel one's input triming potentiometer, and check that it's sweep is
complete and smooth. At its maximum position, check that Vo=20Vrms, and that the
output signal monitored on OUTPUT1 is only dependent from the INPUT1 signal.
- Turn up channel two's input triming potentiometer, and check that it's sweep is
complete and smooth. At its maximum position, check that Vo=20Vrms, and that the
output signal monitored on OUTPUT2 is only dependent from the INPUT2 signal.
- Both output signals should have no phase differs.
- Now change the ST/B IN1/B IN1+IN2 selector to the B IN1+IN2 position, and verify
that OUTPUT1 and OUTPUT2 phase differ has turned to push-pull. S.P. CHII's LED has
turned off, and the unit's channels 1&2 section is now controlled only by channel
one's input trimming potentiometer. Turn it up and leave it at its maximum position.
- Apply a 1KHz square wave signal. Moreover, shunt a 2µ2 capacitor to channel 1's 4Ω
output load. While monitoring the output signal on the osciloscope, vary the input
SHEET 1 OF 3
author: Queralt 000718 VERIFICATION PROCESS
ECLER approved:
date:
title:
signal level until the output signal clips. At this point, a two- or three-cycled ripple
should appear on the flat sections of the square waveform. Repeat this same process
with channel two.
- Disconnect the oscilloscope's both channels test probes, and connect them to outputs
3-4.
- Turn up channel three's input triming potentiometer, and check that it's sweep is
complete and smooth. At its maximum position, check that Vo=20Vrms, and that the
output signal monitored on OUTPUT3 is only dependent from the INPUT3 signal.
- Turn up channel four's input triming potentiometer, and check that it's sweep is
complete and smooth. At its maximum position, check that Vo=20Vrms, and that the
output signal monitored on OUTPUT4 is only dependent from the INPUT4 signal.
- Both output signals should have no phase differs.
- Now change the ST/B IN1/B IN3+IN4 selector to the B IN3+IN4 position, and verify
that OUTPUT1 and OUTPUT2 phase differ has turned to push-pull. S.P. CHII's LED has
turned off, and the unit's channels 1&2 section is now controlled only by channel
three's input trimming potentiometer. Turn it up and leave it at its maximum position.
- Apply a 1KHz square wave signal. Moreover, shunt a 2µ2 capacitor to channel 3's 4Ω
output load. While monitoring the output signal on the osciloscope, vary the input
signal level until the output signal clips. At this point, a two- or three-cycled ripple
should appear on the flat sections of the square waveform. Repeat this same process
with channel four.
- Set back the signal generator to its normal sine-wave operation mode.
- At this point, all clip indicators should be lighting. If necessary, add a little bit of level
to the input signal.
- Set the IN1/IN1+IN2 selector to IN1+IN2, and verify that the output level as
decreased 6dB.
- Return this switch to IN1.
- To verify the thermal protection circuits, short the thermal probe leads 1 and 2, and
verify that the relay releases and opens up, while the THERMAL LED indicator lights on
and the cooling fan increases its speed untill it reaches maximum airflow.
PROTECTIONS
QUALITY CONTROL
All mechanical parts should be visually revised, in order to detect scratches on the
unit's painting; all screws should be on their place,correctly tight and unmarked. Check
out the unit's general presentation.
BURNING (BURN-IN) TEST
Leave the tested unit connected to its correspondent voltage mains socket, applying
input signal and connecting load impedances, and working at 3dB under its maximum
output power level for at least 24 hours.
Verify the unit's sound quality, which should be distorsion- and noise-free. Also check
that all potentiometers can run smoothly their whole sweep, without annoying noises
and crisperings. At their minimum position, check that output signal is completely
cutted off. To ensure that all electrical junctions are well-fixed, hit the tested unit
against your working table, obviously without damaging its outer presentation. Verify
also all inputs and outputs. Also verify the HPF and LPF filters' performance. At last,
short-circuit the output terminals while carrying amplified signal, and verify that once
short-circuit is removed, the amplifying stages still are working.
SHEET 3 OF 3
author: Queralt 000215 TECHNICAL CHARACTERISTICS
ECLER approved:
date:
title:
Weight 11.4kg
Mains Depending on your country See characteristics in the back of the unit.
20
1
16
4
23
1 7
8
24
1
11
27 4
9
1 1
30
1
31
22 1
1 3
1
28
13 1
16
MECHANICAL DIAGRAM
product:
8
1
19
1
32
1
29
1
17
1
1
1
4
2
4
13
4
3
2
5
1
10
1
7
1
3
1
12
2
1
1
Jordi Folch 000524
ECLER drawn:
approved by:
date:
title:
PACKING DIAGRAM EP05-99
number: 32.0049 version 01.01