IMXRT1050CEC
IMXRT1050CEC
IMXRT1050CEC
Rev. 1, 03/2018
Data Sheet: Technical Data
MIMXRT1051DVL6A MIMXRT1052DVL6A
MIMXRT1051DVL6B MIMXRT1052DVL6B
Ordering Information
1.1 Features
The i.MX RT1050 processors are based on Arm Cortex-M7 MPCore™ Platform, which has the
following features:
• Supports single Arm Cortex-M7 MPCore with:
— 32 KB L1 Instruction Cache
— 32 KB L1 Data Cache
— Full featured Floating Point Unit (FPU) with support of the VFPv5 architecture
— Support the Armv7-M Thumb instruction set
• Integrated MPU, up to 16 individual protection regions
• Up to 512 KB I-TCM and D-TCM in total
• Frequency of 600 MHz
• Cortex M7 CoreSight™ components integration for debug
• Frequency of the core, as per Table 9, "Operating ranges," on page 19.
The SoC-level memory system consists of the following additional components:
— Boot ROM (96 KB)
— On-chip RAM (512 KB)
– Configurable RAM size up to 512 KB shared with M7 TCM
• External memory interfaces:
— 8/16-bit SDRAM, up to SDRAM-166
— 8/16-bit SLC NAND FLASH, with ECC handled in software
— SD/eMMC
— SPI NOR FLASH
— Parallel NOR FLASH with XIP support
— Single/Dual channel Quad SPI FLASH with XIP support
• Timers and PWMs:
— Two General Programmable Timers (GPT)
– 4-channel generic 32-bit resolution timer
– Each support standard capture and compare operation
— Four Periodical Interrupt Timer (PIT)
– Generic 16-bit resolution timer
– Periodical interrupt generation
— Four Quad Timers (QTimer)
Junction
Part Number Feature Package Temperature Tj
(C)
Figure 1 describes the part number nomenclature so that characteristics of a specific part number can be
identified (for example, cores, frequency, temperature grade, fuse options, and silicon revision). The
primary characteristic which describes which data sheet applies to a specific part is the temperature grade
(junction) field.
• The i.MX RT1050 Crossover Processors for Consumer Products data sheet (IMXRT1050CEC)
covers parts listed with a “D (Consumer temp)”
Ensure to have the proper data sheet for specific part by verifying the temperature grade (junction) field
and matching it to the proper data sheet. If there are any questions, visit the web page nxp.com/imxrtseries
or contact an NXP representative for details.
M IMX XX @ ## % + VV $ A
Special S
Frequency $
Part # series XX
400 MHz 4
i.MX RT RT
500 MHz 5
600 MHz 6
Family @
700 MHz 7
First Generation RT family 1
800 MHz 8
Reserved 2
1000 MHz A
3
4
5 VV Package Type
6
VL MAPBGA 10 x 10 mm, 0.65 mm
7
8
Temperature +
Sub-Family ##
02 RT1020 Consumer: 0 to + 95 °C D
Tie %
05 RT1050 Industrial: -40 to +105 °C C
1 Reduced Feature General Purpose
2 Full Feature General Purpose
2 Architectural overview
The following subsections provide an architectural overview of the i.MX RT1050 processor system.
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1. Some modules shown in this block diagram are not offered on all derivatives. See Table 1 for details.
3 Modules list
The i.MX RT1050 processors contain a variety of digital and analog modules. Table 2 describes these
modules in alphabetical order.
Table 2. i.MX RT1050 modules list
ACMP1 Analog Comparator Analog The comparator (CMP) provides a circuit for comparing
ACMP2 two analog input voltages. The comparator circuit is
ACMP3 designed to operate across the full range of the supply
ACMP4 voltage (rail-to-rail operation).
ADC1 Analog to Digital Analog The ADC is a 12-bit general purpose analog to digital
ADC2 Converter converter.
AOI And-Or-Inverter Cross Trigger The AOI provides a universal boolean function
generator using a four team sum of products expression
with each product term containing true or complement
values of the four selected inputs (A, B, C, D).
Arm Arm Platform Arm The Arm Core Platform includes one Cortex-M7 core. It
includes associated sub-blocks, such as Nested
Vectored Interrupt Controller (NVIC), Floating-Point
Unit (FPU), Memory Protection Unit (MPU), and
CoreSight debug modules.
CCM Clock Control Module, Clocks, Resets, and These modules are responsible for clock and reset
GPC General Power Power Control distribution in the system, and also for the system
SRC Controller, System Reset power management.
Controller
CSI Parallel CSI Multimedia The CSI IP provides parallel CSI standard camera
Peripherals interface port. The CSI parallel data ports are up to 24
bits. It is designed to support 24-bit RGB888/YUV444,
CCIR656 video interface, 8-bit YCbCr, YUV or RGB,
and 8-bit/10-bit/16-bit Bayer data input.
CSU Central Security Unit Security The Central Security Unit (CSU) is responsible for
setting comprehensive security policy within the i.MX
RT1050 platform.
DAP Debug Access Port System Control The DAP provides real-time access for the debugger
Peripherals without halting the core to:
• System memory and peripheral registers
• All debug configuration registers
The DAP also provides debugger access to JTAG scan
chains. The DAP module is internal to the Cortex-M7
Core Platform.
DCDC DCDC Converter Analog The DCDC module is used for generating power supply
for core logic. Main features are:
• Adjustable high efficiency regulator
• Supports 3.0 V input voltage for A0 and 3.3 V input
voltage for A1
• Supports nominal run and low power standby modes
• Supports at 0.9 ~ 1.3 V output in run mode
• Supports at 0.9 ~ 1.0 V output in standby mode
• Over current and over voltage detection
eDMA enhanced Direct Memory System Control There is an enhanced DMA (eDMA) engine and two
Access Peripherals DMA_MUX.
• The eDMA is a 32 channel DMA engine, which is
capable of performing complex data transfers with
minimal intervention from a host processor.
• The DMA_MUX is capable of multiplexing up to 128
DMA request sources to the 32 DMA channels of
eDMA.
ENET Ethernet Controller Connectivity The Ethernet Media Access Controller (MAC) is
Peripherals designed to support 10/100 Mbit/s Ethernet/IEEE 802.3
networks. An external transceiver interface and
transceiver function are required to complete the
interface to the media. The module has dedicated
hardware to support the IEEE 1588 standard. See the
ENET chapter of the reference manual for details.
EWM External Watchdog Timer Peripherals The EWM modules is designed to monitor external
Monitor circuits, as well as the software flow. This provides a
back-up mechanism to the internal WDOG that can
reset the system. The EWM differs from the internal
WDOG in that it does not reset the system. The EWM,
if allowed to time-out, provides an independent trigger
pin that when asserted resets or places an external
circuit into a safe mode.
FLEXCAN1 Flexible Controller Area Connectivity The CAN protocol was primarily, but not only, designed
FLEXCAN2 Network Peripherals to be used as a vehicle serial data bus, meeting the
specific requirements of this field: real-time processing,
reliable operation in the Electromagnetic interference
(EMI) environment of a vehicle, cost-effectiveness and
required bandwidth. The FlexCAN module is a full
implementation of the CAN protocol specification,
Version 2.0 B, which supports both standard and
extended message frames.
FlexIO1 Flexible Input/output Connectivity and The FlexIO is capable of supporting a wide range of
FlexIO2 Communications protocols including, but not limited to: UART, I2C, SPI,
I2S, camera interface, display interface, PWM
waveform generation, etc. The module can remain
functional when the chip is in a low power mode
provided the clock it is using remain active.
FlexPWM1 Pulse Width Modulation Timer Peripherals The pulse-width modulator (PWM) contains four PWM
FlexPWM2 sub-modules, each of which is set up to control a single
FlexPWM3 half-bridge power stage. Fault channel support is
FlexPWM4 provided. The PWM module can generate various
switching patterns, including highly sophisticated
waveforms.
FlexRAM RAM Memories The i.MX RT1050 has 512 KB of on-chip RAM which
could be flexible allocated to I-TCM, D-TCM, and
on-chip RAM (OCRAM) in a 32 KB granularity. The
FlexRAM is the manager of the 512 KB on-chip RAM
array. Major functions of this blocks are: interfacing to
I-TCM and D-TCM of Arm core and OCRAM controller;
dynamic RAM arrays allocation for I-TCM, D-TCM, and
OCRAM.
FlexSPI Quad Serial Peripheral Connectivity and FlexSPI acts as an interface to one or two external
Interface Communications serial flash devices, each with up to four bidirectional
data lines.
GPIO1 General Purpose I/O System Control Used for general purpose input/output to external ICs.
GPIO2 Modules Peripherals Each GPIO module supports up to 32 bits of I/O.
GPIO3
GPIO4
GPIO5
GPT1 General Purpose Timer Timer Peripherals Each GPT is a 32-bit “free-running” or “set and forget”
GPT2 mode timer with programmable prescaler and compare
and capture register. A timer counter value can be
captured using an external event and can be configured
to trigger a capture event on either the leading or trailing
edges of an input pulse. When the timer is configured to
operate in “set and forget” mode, it is capable of
providing precise interrupts at regular intervals with
minimal processor intervention. The counter has output
compare logic to provide the status and interrupt at
comparison. This timer can be configured to run either
on an external clock or on an internal clock.
KPP Keypad Port Human Machine The KPP is a 16-bit peripheral that can be used as a
Interfaces keypad matrix interface or as general purpose
input/output (I/O). It supports 8 x 8 external key pad
matrix. Main features are:
• Multiple-key detection
• Long key-press detection
• Standby key-press detection
• Supports a 2-point and 3-point contact key matrix
LCDIF LCD interface Multimedia The LCDIF is a general purpose display controller used
Peripherals to drive a wide range of display devices varying in size
and capabilities. The LCDIF is designed to support
dumb (synchronous 24-bit Parallel RGB interface) and
smart (asynchronous parallel MPU interface) LCD
devices.
LPI2C1 Low Power Connectivity and The LPI2C is a low power Inter-Integrated Circuit (I2C)
LPI2C2 Inter-integrated Circuit Communications module that supports an efficient interface to an I2C bus
LPI2C3 as a master.
LPI2C4 The I2C provides a method of communication between
a number of external devices. More detailed
information, see Section 4.9.2, “LPI2C module timing
parameters.
LPSPI1 Low Power Serial Connectivity and The LPSPI is a low power Serial Peripheral Interface
LPSPI2 Peripheral Interface Communications (SPI) module that support an efficient interface to an
LPSPI3 SPI bus as a master and/or a slave.
LPSPI4 • It can continue operating while the chip is in stop
modes, if an appropriate clock is available
• Designed for low CPU overhead, with DMA off
loading of FIFO register access
LPUART1 UART Interface Connectivity Each of the UART modules support the following serial
LPUART2 Peripherals data transmit/receive protocols and configurations:
LPUART3 • 7- or 8-bit data words, 1 or 2 stop bits, programmable
LPUART4 parity (even, odd or none)
LPUART5 • Programmable baud rates up to 5 Mbps.
LPUART6
LPUART7
LPUART8
MQS Medium Quality Sound Multimedia MQS is used to generate 2-channel medium quality
Peripherals PWM-like audio via two standard digital GPIO pins.
QuadTimer1 QuadTimer Timer Peripherals The quad-timer provides four time channels with a
QuadTimer2 variety of controls affecting both individual and
QuadTimer3 multi-channel features.Specific features include
QuadTimer4 up/down count, cascading of counters, programmable
module, count once/repeated, counter preload,
compare registers with preload, shared use of input
signals, prescaler controls, independent
capture/compare, fault input control, programmable
input filters, and multi-channel synchronization.
ROMCP ROM Controller with Memories and The ROMCP acts as an interface between the Arm
Patch Memory Controllers advanced high-performance bus and the ROM. The
on-chip ROM is only used by the Cortex-M7 core during
boot up. Size of the ROM is 96 KB.
RTC OSC Real Time Clock Clock Sources and The RTC OSC provides the clock source for the
Oscillator Control Real-Time Clock module. The RTC OSC module, in
conjunction with an external crystal, generates a 32.678
kHz reference clock for the RTC.
RTWDOG Watch Dog Timer Peripherals The RTWDG module is a high reliability independent
timer that is available for system to use. It provides a
safety feature to ensure software is executing as
planned and the CPU is not stuck in an infinite loop or
executing unintended code. If the WDOG module is not
serviced (refreshed) within a certain period, it resets the
MCU. Windowed refresh mode is supported as well.
SAI1 Synchronous Audio Multimedia The SAI module provides a synchronous audio
SAI2 Interface Peripherals interface (SAI) that supports full duplex serial interfaces
SAI3 with frame synchronization, such as I2S, AC97, TDM,
and codec/DSP interfaces.
SA-TRNG Standalone True Random Security The SA-TRNG is hardware accelerator that generates
Number Generator a 512-bit entropy as needed by an entropy consuming
module or by other post processing functions.
SEMC Smart External Memory Memory and The SEMC is a multi-standard memory controller
Controller Memory Controller optimized for both high-performance and low pin-count.
It can support multiple external memories in the same
application with shared address and data pins. The
interface supported includes SDRAM, NOR Flash,
SRAM, and NAND Flash, as well as 8080 display
interface.
SJC System JTAG Controller System Control The SJC provides JTAG interface, which complies with
Peripherals JTAG TAP standards, to internal logic. The i.MX
RT1050 processors use JTAG port for production,
testing, and system debugging. In addition, the SJC
provides BSR (Boundary Scan Register) standard
support, which complies with IEEE 1149.1 and IEEE
1149.6 standards.
The JTAG port is accessible during platform initial
laboratory bring-up, for manufacturing tests and
troubleshooting, as well as for software debugging by
authorized entities. The i.MX RT1050 SJC incorporates
three security modes for protecting against
unauthorized accesses. Modes are selected through
eFUSE configuration.
SNVS Secure Non-Volatile Security Secure Non-Volatile Storage, including Secure Real
Storage Time Clock, Security State Machine, Master Key
Control, and Violation/Tamper Detection and reporting.
SPDIF Sony Philips Digital Multimedia A standard audio file transfer format, developed jointly
Interconnect Format Peripherals by the Sony and Phillips corporations. Has Transmitter
and Receiver functionality.
Temp Monitor Temperature Monitor Analog The temperature sensor implements a temperature
sensor/conversion function based on a
temperature-dependent voltage to time conversion.
TSC Touch Screen Human Machine With touch controller to support 4-wire and 5-wire
Interfaces resistive touch panel.
USBO2 Universal Serial Bus 2.0 Connectivity USBO2 (USB OTG1 and USB OTG2) contains:
Peripherals • Two high-speed OTG 2.0 modules with integrated
HS USB PHYs
• Support eight Transmit (TX) and eight Receive (Rx)
endpoints, including endpoint 0
uSDHC1 SD/MMC and SDXC Connectivity i.MX RT1050 specific SoC characteristics:
uSDHC2 Enhanced Multi-Media Peripherals All four MMC/SD/SDIO controller IPs are identical and
Card / Secure Digital Host are based on the uSDHC IP. They are:
Controller • Fully compliant with MMC command/response sets
and Physical Layer as defined in the Multimedia
Card System Specification, v4.5/4.2/4.3/4.4/4.41/
including high-capacity (size > 2 GB) cards HC
MMC.
• Fully compliant with SD command/response sets
and Physical Layer as defined in the SD Memory
Card Specifications, v3.0 including high-capacity
SDXC cards up to 2 TB.
• Fully compliant with SDIO command/response sets
and interrupt/read-wait mode as defined in the SDIO
Card Specification, Part E1, v3.0
Two ports support:
• 1-bit or 4-bit transfer mode specifications for SD and
SDIO cards up to UHS-I SDR104 mode (104 MB/s
max)
• 1-bit, 4-bit, or 8-bit transfer mode specifications for
MMC cards up to 52 MHz in both SDR and DDR
modes (104 MB/s max)
• 4-bit or 8-bit transfer mode specifications for eMMC
chips up to 200 MHz in HS200 mode (200 MB/s max)
WDOG1 Watch Dog Timer Peripherals The watchdog (WDOG) Timer supports two comparison
WDOG2 points during each counting period. Each of the
comparison points is configurable to evoke an interrupt
to the Arm core, and a second point evokes an external
event on the WDOG line.
XBAR Cross BAR Cross Trigger Each crossbar switch is an array of muxes with shared
inputs. Each mux output provides one output of the
crossbar. The number of inputs and the number of
muxes/outputs are user configurable and registers are
provided to select which of the shared inputs are routed
to each output.
CCM_CLK1_P/ One general purpose differential high speed clock Input/output (LVDS I/O) is provided.
CCM_CLK1_N It can be used:
• To feed external reference clock to the PLLs and further to the modules inside SoC.
• To output internal SoC clock to be used outside the SoC as either reference clock or as a
functional clock for peripherals.
See the i.MX RT1050 Reference Manual (IMX6ULRM) for details on the respective clock trees.
Alternatively one may use single ended signal to drive CLK1_P input. In this case corresponding
CLK1_N input should be tied to the constant voltage level equal 1/2 of the input signal swing.
Termination should be provided in case of high frequency signals.
After initialization, the CLK1 input/output can be disabled (if not used). If unused either or both of
the CLK1_N/P pairs may remain unconnected.
DCDC_PSWITCH PAD is in DCDC_IN domain and connected the ground to bypass DCDC.
To enable DCDC function, assert to DCDC_IN with at least 1ms delay for DCDC_IN rising edge.
RTC_XTALI/RTC_XTALO If the user wishes to configure RTC_XTALI and RTC_XTALO as an RTC oscillator, a 32.768 kHz
crystal, (100 k ESR, 10 pF load) should be connected between RTC_XTALI and RTC_XTALO.
Keep in mind the capacitors implemented on either side of the crystal are about twice the crystal
load capacitor. To hit the exact oscillation frequency, the board capacitors need to be reduced to
account for board and chip parasitics. The integrated oscillation amplifier is self biasing, but
relatively weak. Care must be taken to limit parasitic leakage from RTC_XTALI and RTC_XTALO
to either power or ground (>100 M). This will debias the amplifier and cause a reduction of startup
margin. Typically RTC_XTALI and RTC_XTALO should bias to approximately 0.5 V.
If it is desired to feed an external low frequency clock into RTC_XTALI the RTC_XTALO pin must
remain unconnected or driven with a complimentary signal. The logic level of this forcing clock
should not exceed VDD_SNVS_CAP level and the frequency should be <100 kHz under typical
conditions.
In case when high accuracy real time clock are not required system may use internal low frequency
ring oscillator. It is recommended to connect RTC_XTALI to GND and keep RTC_XTALO
unconnected.
XTALI/XTALO A 24.0 MHz crystal should be connected between XTALI and XTALO.
The crystal must be rated for a maximum drive level of 250 W. An ESR (equivalent series
resistance) of typical 80 is recommended. NXP SDK software requires 24 MHz on
XTALI/XTALO.
The crystal can be eliminated if an external 24 MHz oscillator is available in the system. In this
case, XTALO must be directly driven by the external oscillator and XTALI mounted with 18 pF
capacitor. The logic level of this forcing clock cannot exceed NVCC_PLL level.
If this clock is used as a reference for USB, then there are strict frequency tolerance and jitter
requirements. See OSC24M chapter and relevant interface specifications chapters for details.
GPANAIO This signal is reserved for NXP manufacturing use only. This output must remain unconnected.
JTAG_nnnn The JTAG interface is summarized in Table 4. Use of external resistors is unnecessary. However,
if external resistors are used, the user must ensure that the on-chip pull-up/down configuration is
followed. For example, do not use an external pull down on an input that has on-chip pull-up.
JTAG_TDO is configured with a keeper circuit such that the non-connected condition is eliminated
if an external pull resistor is not present. An external pull resistor on JTAG_TDO is detrimental and
should be avoided.
JTAG_MOD is referenced as SJC_MOD in the i.MX RT1050 reference manual. Both names refer
to the same signal. JTAG_MOD must be externally connected to GND for normal operation.
Termination to GND through an external pull-down resistor (such as 1 k) is allowed. JTAG_MOD
set to hi configures the JTAG interface to mode compliant with IEEE1149.1 standard. JTAG_MOD
set to low configures the JTAG interface for common SW debug adding all the system TAPs to the
chain.
NC These signals are No Connect (NC) and should be disconnected by the user.
POR_B This cold reset negative logic input resets all modules and logic in the IC.
May be used in addition to internally generated power on reset signal (logical AND, both internal
and external signals are considered active low).
ONOFF ONOFF can be configured in debounce, off to on time, and max time-out configurations. The
debounce and off to on time configurations supports 0, 50, 100 and 500 ms. Debounce is used to
generate the power off interrupt. While in the ON state, if ONOFF button is pressed longer than the
debounce time, the power off interrupt is generated. Off to on time supports the time it takes to
request power on after a configured button press time has been reached. While in the OFF state,
if ONOFF button is pressed longer than the off to on time, the state will transition from OFF to ON.
Max time-out configuration supports 5, 10, 15 seconds and disable. Max time-out configuration
supports the time it takes to request power down after ONOFF button has been pressed for the
defined time.
TEST_MODE TEST_MODE is for NXP factory use. The user must tie this pin directly to GND.
WAKEUP A GPIO powered by SNVS domain power supply which can be configured as wakeup source in
SNVS mode.
Recommendations
Module Pad Name
if Unused
4 Electrical characteristics
This section provides the device and module-level electrical characteristics for the i.MX RT1050
processors.
Junction to Ambient (@200 ft/min) Four-layer board (2s2p) RJMA 39.0 oC/W 1,3
oC/W 6
Junction to Package Top Natural Convection JT 0.6
oC/W 7
Junction to Package Bottom Natural Convection RJB_CSB 22.3
1 Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2 Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
3 Per JEDEC JESD51-6 with the board horizontal.
4 Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
5
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1).
6 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
7
Thermal resistance between the die and the central solder balls on the bottom of the package based on simulation.
Parameter Operating
Symbol Min Typ Max1 Unit Comment
Description Conditions
SUSPEND (DSM) VDD_SOC_IN — 0.925 — 1.3 V Refer to Table 12 Low power mode
Mode current and power consumption
GPIO supplies NVCC_GPIO — 1.65 1.8, 3.6 V All digital I/O supplies
2.8, (NVCC_xxxx) must be powered
NVCC_SD1 3.3 (unless otherwise specified in this
NVCC_SD2 data sheet) under normal
conditions whether the associated
NVCC_EMC I/O pins are in use or not.
to below 3.49 V.
3 In setting VDD_SNVS_IN voltage with regards to Charging Currents and RTC, refer to the i.MX RT1050 Hardware
The typical values shown in Table 10 are required for use with NXP SDK to ensure precise time keeping
and USB operation. For RTC_XTALI operation, two clock sources are available.
• On-chip 40 kHz ring oscillator—this clock source has the following characteristics:
— Approximately 25 µA more Idd than crystal oscillator
— Approximately ±50% tolerance
— No external component required
— Starts up quicker than 32 kHz crystal oscillator
• External crystal oscillator with on-chip support circuit:
— At power up, ring oscillator is utilized. After crystal oscillator is stable, the clock circuit
switches over to the crystal oscillator automatically.
— Higher accuracy than ring oscillator
— If no external crystal is present, then the ring oscillator is utilized
The decision of choosing a clock source should be taken based on real-time clock use and precision
time-out.
VDD_SNVS_IN — 250 A
SYSTEM IDLE • LDO_2P5 set to 2.5 V, LDO_1P1 set to 1.1 V DCDC_IN (3.0 V for A0 4.0 mA
• CPU in WFI, CPU clock gated and 3.3 V for A1)
• 24 MHz XTAL is ON
• 528 PLL is active, other PLLs are power down VDD_HIGH_IN (3.3 V) 4.7
• Peripheral clock gated, but remain powered VDD_SNVS_IN (3.3 V) 0.036
Total 27.63 mW
LOW POWER IDLE • LDO_2P5 and LDO_1P1 are set to Weak mode DCDC_IN (3.0 V for A0 2.2 mA
• WFI, half FlexRAM power down in power gate and 3.3 V for A1)
mode
• All PLLs are power down VDD_HIGH_IN (3.3 V) 0.3
• 24 MHz XTAL is off, 24 MHz RCOSC used as VDD_SNVS_IN (3.3 V) 0.042
clock source
• Peripheral clock gated, but remain powered Total 7.73 mW
SUSPEND • LDO_2P5 and LDO_1P1 are shut off DCDC_IN (3.0 V for A0 0.22 mA
(DSM) • CPU in Power Gate mode and 3.3 V for A1)
• All PLLs are power down
• 24 MHz XTAL is off, 24 MHz RCOSC is off VDD_HIGH_IN (3.3 V) 0.037
• All clocks are shut off, except 32 kHz RTC VDD_SNVS_IN (3.3 V) 0.02
• Peripheral clock gated, but remain powered
Total 0.788 mW
SNVS (RTC) • All SOC digital logic, analog module are shut off DCDC_IN (0 V) 0 mA
• 32 kHz RTC is alive
VDD_HIGH_IN (0 V) 0
Total 0.066 mW
1 Typical process material in fab
2
Average current
NOTE
The currents on the VDD_HIGH_CAP and VDD_USB_CAP were
identified to be the voltage divider circuits in the USB-specific level
shifters.
4.2.2.2.1 LDO_1P1
The LDO_1P1 regulator implements a programmable linear-regulator function from VDD_HIGH_IN (see
Table 9 for minimum and maximum input requirements). Typical Programming Operating Range is 1.0 V
to 1.2 V with the nominal default setting as 1.1 V. The LDO_1P1 supplies the USB Phy, and PLLs. A
programmable brown-out detector is included in the regulator that can be used by the system to determine
when the load capability of the regulator is being exceeded to take the necessary steps. Current-limiting
can be enabled to allow for in-rush current requirements during start-up, if needed. Active-pull-down can
also be enabled for systems requiring this feature.
For information on external capacitor requirements for this regulator, see the Hardware Development
Guide for i.MX RT1050 Crossover Processors (IMXRT1050HDG).
For additional information, see the i.MX RT1050 Reference Manual (IMXRT1050_RM).
4.2.2.2.2 LDO_2P5
The LDO_2P5 module implements a programmable linear-regulator function from VDD_HIGH_IN (see
Table 9 for minimum and maximum input requirements). Typical Programming Operating Range is 2.25 V
to 2.75 V with the nominal default setting as 2.5 V. LDO_2P5 supplies the USB PHY, E-fuse module, and
PLLs. A programmable brown-out detector is included in the regulator that can be used by the system to
determine when the load capability of the regulator is being exceeded, to take the necessary steps.
Current-limiting can be enabled to allow for in-rush current requirements during start-up, if needed.
Active-pull-down can also be enabled for systems requiring this feature. An alternate self-biased
low-precision weak-regulator is included that can be enabled for applications needing to keep the output
voltage alive during low-power modes where the main regulator driver and its associated global bandgap
reference module are disabled. The output of the weak-regulator is not programmable and is a function of
the input supply as well as the load current. Typically, with a 3 V input supply the weak-regulator output
is 2.525 V and its output impedance is approximately 40 .
For information on external capacitor requirements for this regulator, see the Hardware Development
Guide for i.MX RT1050 Crossover Processors (IMXRT1050HDG).
For additional information, see the i.MX RT1050 Reference Manual (IMXRT1050RM).
4.2.2.2.3 LDO_USB
The LDO_USB module implements a programmable linear-regulator function from the USB VUSB
voltages (4.4 V–5.5 V) to produce a nominal 3.0 V output voltage. A programmable brown-out detector
is included in the regulator that can be used by the system to determine when the load capability of the
regulator is being exceeded, to take the necessary steps. This regulator has a built in power-mux that allows
the user to select to run the regulator from either USB VBUS supply, when both are present. If only one
of the USB VBUS voltages is present, then, the regulator automatically selects this supply. Current limit
is also included to help the system meet in-rush current targets.
For information on external capacitor requirements for this regulator, see the Hardware Development
Guide for i.MX RT1050 Crossover Processors (IMXRT1050HDG).
For additional information, see the i.MX RT1050 Reference Manual (IMXRT1050RM).
4.2.2.2.4 DCDC
DCDC can be configured to operate on power-save mode when the load current is less than 50 mA. During
the power-save mode, the converter operates with reduced switching frequency in PFM mode and with a
minimum quiescent current to maintain high efficiency.
DCDC can detect the peak current in the P-channel switch. When the peak current exceeds the threshold,
DCDC will give an alert signal, and the threshold can be configured. By this way, DCDC can roughly
detect the current loading.
DCDC also includes the following protection functions:
• Over current protection. In run mode, DCDC shuts down when detecting abnormal large current in
the P-type power switch.
• Over voltage protection. DCDC shuts down when detecting the output voltage is too high.
• Low voltage detection. DCDC shuts down when detecting the input voltage is too low.
For additional information, see the i.MX RT1050 Reference Manual (IMXRT1050RM).
Parameter Value
Parameter Value
Parameter Value
Parameter Value
Parameter Value
4.2.4.1 OSC24M
This block implements an amplifier that when combined with a suitable quartz crystal and external load
capacitors implement an oscillator. The oscillator is powered from NVCC_PLL.
The system crystal oscillator consists of a Pierce-type structure running off the digital supply. A straight
forward biased-inverter implementation is used.
4.2.4.2 OSC32K
This block implements an amplifier that when combined with a suitable quartz crystal and external load
capacitors implement a low power oscillator. It also implements a power mux such that it can be powered
from either a ~3 V backup battery (VDD_SNVS_IN) or VDD_HIGH_IN such as the oscillator consumes
power from VDD_HIGH_IN when that supply is available and transitions to the backup battery when
VDD_HIGH_IN is lost.
In addition, if the clock monitor determines that the OSC32K is not present, then the source of the 32 K
will automatically switch to a crude internal ring oscillator. The frequency range of this block is
approximately 10–45 kHz. It highly depends on the process, voltage, and temperature.
The OSC32k runs from VDD_SNVS_CAP supply, which comes from the
VDD_HIGH_IN/VDD_SNVS_IN. The target battery is a ~3 V coin cell. Proper choice of coin cell type
is necessary for chosen VDD_HIGH_IN range. Appropriate series resistor (Rs) must be used when
connecting the coin cell. Rs depends on the charge current limit that depends on the chosen coin cell. For
example, for Panasonic ML621:
• Average Discharge Voltage is 2.5 V
• Maximum Charge Current is 0.6 mA
For a charge voltage of 3.2 V, Rs = (3.2-2.5)/0.6 m = 1.17 k.
Table 19. OSC32K main characteristics
Fosc — 32.768 KHz — This frequency is nominal and determined mainly by the crystal selected.
32.0 K would work as well.
Current consumption — 4 A — The 4 A is the consumption of the oscillator alone (OSC32k). Total supply
consumption will depend on what the digital portion of the RTC consumes.
The ring oscillator consumes 1 A when ring oscillator is inactive, 20 A
when the ring oscillator is running. Another 1.5 A is drawn from vdd_rtc in
the power_detect block. So, the total current is 6.5 A on vdd_rtc when the
ring oscillator is not running.
Bias resistor — 14 M — This integrated bias resistor sets the amplifier into a high gain state. Any
leakage through the ESD network, external board leakage, or even a
scope probe that is significant relative to this value will debias the amp. The
debiasing will result in low gain, and will impact the circuit's ability to start
up and maintain oscillations.
Crystal Properties
Cload — 10 pF — Usually crystals can be purchased tuned for different Cloads. This Cload
value is typically 1/2 of the capacitances realized on the PCB on either side
of the quartz. A higher Cload will decrease oscillation margin, but
increases current oscillating through the crystal.
ESR — 50 k 100 k Equivalent series resistance of the crystal. Choosing a crystal with a higher
value will decrease the oscillating margin.
Figure 3. Circuit for parameters Voh and Vol for I/O cells
level through to the target DC level, Vil or Vih. Monotonic input transition time is from 0.1 ns to 1 s.
3 Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.
OVDD
80% 80%
20% 20%
Output (at pad) 0V
tr tf
Output Pad Transition Times, rise/fall tr, tf 15 pF Cload, slow slew rate 2.72/2.79
— —
(Max Drive, ipp_dse=111) 15 pF Cload, fast slew rate 1.51/1.54
Output Pad Transition Times, rise/fall tr, tf 15 pF Cload, slow slew rate 3.20/3.36
— —
(High Drive, ipp_dse=101) 15 pF Cload, fast slew rate 1.96/2.07 ns
Output Pad Transition Times, rise/fall tr, tf 15 pF Cload, slow slew rate 3.64/3.88
— —
(Medium Drive, ipp_dse=100) 15 pF Cload, fast slew rate 2.27/2.53
Output Pad Transition Times, rise/fall tr, tf 15 pF Cload, slow slew rate 4.32/4.50
— —
(Low Drive. ipp_dse=011) 15 pF Cload, fast slew rate 3.16/3.17
Input Transition Times1 trm — — — 25 ns
1
Hysteresis mode is recommended for inputs with transition times greater than 25 ns.
Output Pad Transition Times, rise/fall tr, tf 15 pF Cload, slow slew rate 1.70/1.79
— —
(Max Drive, ipp_dse=101) 15 pF Cload, fast slew rate 1.06/1.15
Output Pad Transition Times, rise/fall tr, tf 15 pF Cload, slow slew rate 2.35/2.43
— —
(High Drive, ipp_dse=011) 15 pF Cload, fast slew rate 1.74/1.77 ns
Output Pad Transition Times, rise/fall tr, tf 15 pF Cload, slow slew rate 3.13/3.29
— —
(Medium Drive, ipp_dse=010) 15 pF Cload, fast slew rate 2.46/2.60
Output Pad Transition Times, rise/fall tr, tf 15 pF Cload, slow slew rate 5.14/5.57
— —
(Low Drive. ipp_dse=001) 15 pF Cload, fast slew rate 4.77/5.15 ns
OVDD
PMOS (Rpu)
Ztl , L = 20 inches
ipp_do pad
predriver
Cload = 1p
NMOS (Rpd)
OVSS
U,(V)
Vin (do)
VDD
t,(ns)
0
U,(V)
Vout (pad)
OVDD
Vref1 Vref2
Vref
t,(ns)
0
Vovdd - Vref1
Rpu = Ztl
Vref1
Vref2
Rpd = Ztl
Vovdd - Vref2
001 260
010 130
Output Driver Rdrv 011 88
Impedance 100 65
101 52
110 43
111 37
Table 26 shows the GPIO output buffer impedance (NVCC_XXXX 3.3 V).
Table 26. GPIO output buffer average impedance (NVCC_XXXX 3.3 V)
001 157
010 78
Output Driver Rdrv 011 53
Impedance 100 39
101 32
110 26
111 23
POR_B
(Input)
CC1
WDOGn_B
(Output)
CC3
NOTE
RTC_XTALI is approximately 32 kHz. RTC_XTALI cycle is one period or
approximately 30 s.
NOTE
WDOGn_B output signals (for each one of the Watchdog modules) do not
have dedicated pins, but are muxed out through the IOMUX. See the IOMUX
manual for detailed information.
SJ1
SJ2 SJ2
JTAG_TCK
(Input) VIH VM VM
VIL
SJ3 SJ3
JTAG_TCK
(Input) VIH
VIL
SJ4 SJ5
Data
Inputs Input Data Valid
SJ6
Data
Output Data Valid
Outputs
SJ7
Data
Outputs
SJ6
Data
Outputs Output Data Valid
JTAG_TCK
(Input) VIH
VIL
SJ8 SJ9
JTAG_TDI
JTAG_TMS Input Data Valid
(Input)
SJ10
JTAG_TDO
(Output) Output Data Valid
SJ11
JTAG_TDO
(Output)
SJ10
JTAG_TDO
Output Data Valid
(Output)
JTAG_TCK
(Input)
SJ13
JTAG_TRST_B
(Input)
SJ12
All Frequencies
ID Parameter1,2 Unit
Min Max
All Frequencies
ID Parameter1,2 Unit
Min Max
1
Address output hold time is configurable by SEMC_*CR0.AH. AH field setting value is 0x0 in above table. When AH is set
with value N, TAHO min time should be ((N + 1) x TCK). See the i.MX RT1050 Reference Manual (IMXRT1050_RM) for more
detail about SEMC_*CR0.AH register field.
2
ADV# low time is configurable by SEMC_*CR0.AS. AS field setting value is 0x0 in above table. When AS is set with value N,
TADL min time should be ((N + 1) x TCK - 1). See the i.MX RT1050 Reference Manual (IMXRT1050_RM) for more detail about
SEMC_*CR0.AS register field.
3 Data output hold time is configurable by SEMC_*CR0.WEH. WEH field setting value is 0x0 in above table. When WEH is set
with value N, TDHO min time should be ((N + 1) x TCK). See the i.MX RT1050 Reference Manual (IMXRT1050_RM) for more
detail about SEMC_*CR0.WEH register field.
4
WE# low time is configurable by SEMC_*CR0.WEL. WEL field setting value is 0x0 in above table. When WEL is set with value
N, TWEL min time should be ((N + 1) x TCK - 1). See the i.MX RT1050 Reference Manual (IMXRT1050_RM) for more detail
about SEMC_*CR0.WEL register field.
4#+
)NTERNAL CLOCK
!$$2 !
4!(/
!$6 4!6/
$!4! $
4$(/
7% 4$6/
3%-#?#,+
4$6/
4$(/
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4)3
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4)3 4)(
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4)(
Table 36. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X1
6&.
7,6 7,+ 7,6 7,+
6,2>@
,QWHUQDO6DPSOH&ORFN
Figure 17. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X0, 0X1
NOTE
Timing shown is based on the memory generating read data on the SCK
falling edge, and FlexSPI controller sampling read data on the falling edge.
Table 37. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case A1)
Value
Symbol Parameter Unit
Min Max
6&.
76&.' 76&.'
6,2>@
76&.'46 76&.'46
'46
Figure 18. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X3 (case A1)
NOTE
Timing shown is based on the memory generating read data and read strobe
on the SCK rising edge. The FlexSPI controller samples read data on the
DQS falling edge.
Table 38. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case A2)
Value
Symbol Parameter Unit
Min Max
6&.
76&.' 76&.' 76&.'
6,2>@
76&.'46 76&.'46 76&.'46
'46
,QWHUQDO6DPSOH&ORFN
Figure 19. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X3 (case A2)
NOTE
Timing shown is based on the memory generating read data on the SCK
falling edge and read strobe on the SCK rising edge. The FlexSPI controller
samples read data on a half cycle delayed DQS falling edge.
Table 39. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0
Table 40. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x1
6&/.
7,6 7,+ 7,6 7,+
6,2>@
,QWHUQDO6DPSOH&ORFN
Figure 20. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1
Table 41. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case B1)
6&.
76&.'
6,2>@
76&.'46
'46
Figure 21. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case B1)
Table 42. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case B2)
6&.
76&.'
6,2>@
6&.
76&.'46
'46
Figure 22. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (case B2)
NOTE
TCSS and TCSH are configured by the FlexSPIn_FLSHAxCR1
register, the default values are shown above. Please refer to the i.MX
RT1050 Reference Manual (IMXRT1050_RM) for more details.
6&.
7&6+
7&66 7&.
&6
7'92 7'92
6,2>@
7'+2 7'+2
specifications.
NOTE
TCSS and TCSH are configured by the FlexSPIn_FLSHAxCR1
register, the default values are shown above. Please refer to the i.MX
RT1050 Reference Manual (IMXRT1050_RM) for more details.
6&.
7&66 7&.
7&6+
&6
7'92 7'92
6,2>@
7'+2 7'+2
CSI_VSYNC
P1
CSI_HSYNC
P7
P2 P5 P6
CSI_PIXCLK
P3 P4
CSI_DATA[23:00]
Figure 25. CSI Gated clock mode—sensor data at falling edge, latch data at rising edge
CSI_VSYNC
P1
CSI_HSYNC
P7
P2 P6 P5
CSI_PIXCLK
P3 P4
CSI_DATA[23:00]
Figure 26. CSI Gated clock mode—sensor data at rising edge, latch data at falling edge
CSI_VSYNC
P1
P6
P4 P5
CSI_PIXCLK
P2 P3
CSI_DATA[23:00]
Figure 27. CSI ungated clock mode—sensor data at falling edge, latch data at rising edge
The CSI enables the chip to connect directly to external CMOS image sensors, which are classified as
dumb or smart as follows:
• Dumb sensors only support traditional sensor timing (vertical sync (VSYNC) and horizontal sync
(HSYNC)) and output-only Bayer and statistics data.
• Smart sensors support CCIR656 video decoder formats and perform additional processing of the
image (for example, image compression, image pre-filtering, and various data output formats).
/ / /
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/&'QB&/.
ULVLQJHGJHFDSWXUH
/&'QB'$7$>@
/&'Q&RQWURO6LJQDOV
/
/
/
/
L4 LCD pixel clock high to data valid (falling edge capture) td(CLKH-DV) -1 1 ns
L5 LCD pixel clock low to data valid (rising edge capture) td(CLKL-DV) -1 1 ns
L6 LCD pixel clock high to control signal valid (falling edge capture) td(CLKH-CTRLV) -1 1 ns
L7 LCD pixel clock low to control signal valid (rising edge capture) td(CLKL-CTRLV) -1 1 ns
4.7 Audio
This section provide information about SAI/I2S and SPDIF.
S12 SAI_BCLK pulse width high/low (input) 40% 60% BCLK period
srckp
srckpl srckph
SPDIF_SR_CLK
VM VM
(Output)
stclkp
stclkpl stclkph
SPDIF_ST_CLK
VM VM
(Input)
4.8 Analog
The following sections provide information about analog interfaces.
4.8.1 DCDC
Table 51 introduces the DCDC electrical specifications.
Table 51. DCDC electrical specifications
Low power mode Open loop mode Ripple is about 15 mV in Run mode
Inductor 4.7 H —
Capacitor 33 F —
Over voltage protection 1.55 V Detect VDDSOC, when the voltage is higher
than 1.6 V, shutdown DCDC.
Low DCDC_IN detection 2.6 V Detect the DCDC_IN, when battery is lower
than 2.6 V, shutdown DCDC.
RAS depends on Sample Time Setting (ADLSMP, ADSTS) and ADC Power Mode (ADHSC, ADLPC). See charts for Minimum
Sample Time vs RAS
ADC Conversion Clock ADLPC=0, ADHSC=1 fADCK 4 — 40 MHz —
Frequency 12 bit mode
ADLPC=0, 460
ADHSC=0
ADLPC=0, 750
ADHSC=1
ADLSMP=0, 4
ADSTS=01
ADLSMP=0, 6
ADSTS=10
ADLSMP=0, 8
ADSTS=11
ADLSMP=1, 12
ADSTS=00
ADLSMP=1, 16
ADSTS=01
ADLSMP=1, 20
ADSTS=10
ADLSMP=1, 24
ADSTS=11
Table 53. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSAD) (continued)
ADLSMP=0 30
ADSTS=01
ADLSMP=0 32
ADSTS=10
ADLSMP=0 34
ADSTS=11
ADLSMP=1 38
ADSTS=00
ADLSMP=1 42
ADSTS=01
ADLSMP=1 46
ADSTS=10
ADLSMP=1, 50
ADSTS=11
ADLSMP=0 0.75
ADSTS=01
ADLSMP=0 0.8
ADSTS=10
ADLSMP=0 0.85
ADSTS=11
ADLSMP=1 0.95
ADSTS=00
ADLSMP=1 1.05
ADSTS=01
ADLSMP=1 1.15
ADSTS=10
ADLSMP=1, 1.25
ADSTS=11
Table 53. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSAD) (continued)
Effective Number of 12 bit mode ENOB 10.1 10.7 — Bits AVGE = 1, AVGS = 11
Bits
Signal to Noise plus See ENOB SINAD SINAD = 6.02 x ENOB + 1.76 dB AVGE = 1, AVGS = 11
Distortion
1
All accuracy numbers assume the ADC is calibrated with VREFH=VDDAD
2
Typical values assume VDDAD = 3.0 V, Temp = 25°C, Fadck=20 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
NOTE
The ADC electrical spec would be met with the calibration enabled
configuration.
4.8.3 ACMP
Table 54 lists the ACMP electrical specifications.
Table 54. Comparator and 6-bit DAC electrical specifications
• CR0[HYSTCTR] = 00 — 1 2
• CR0[HYSTCTR] = 01 — 21 54
• CR0[HYSTCTR] = 10 — 42 108
• CR0[HYSTCTR] = 11 — 64 184
66
287387
636&.
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287387
636&.
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287387
0,62 /6%,1
06%,1 %,7
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026,
287387 06%287 %,7 /6%287
,IFRQILJXUHGDVDQRXWSXW
/6%) )RU/6%) ELWRUGHULV/6%ELWELW06%
66
287387
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66
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636&.
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636&.
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026,
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66
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0,62 VHH
6/$9( 06%287 %,7 6/$9(/6%287
287387 QRWH
026,
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SD2
SD1
SD5
SDx_CLK
SD3
SD6
SD1
SDx_CLK
SD2 SD2
6'
6' 6'
6&.
6'6'
ELWRXWSXWIURPX6'+&WRFDUG
6' 6'
ELWLQSXWIURPFDUGWRX6'+&
6'
6'
6' 6'
6&.
6'6'
ELWRXWSXWIURPX6'+&WRH00&
ELWLQSXWIURPH00&WRX6'+&
6'
M3
ENET_RX_CLK (input)
M4
ENET_RX_DATA3,2,1,0
(inputs)
ENET_RX_EN
ENET_RX_ER
M1 M2
1
ENET_RX_EN, ENET_RX_CLK, and ENET0_RXD0 have the same timing in 10 Mbps 7-wire interface mode.
Figure 43 shows MII transmit signal timings. Table 63 describes the timing parameters (M5–M8) shown
in the figure.
M7
ENET_TX_CLK (input)
M5
M8
ENET_TX_DATA3,2,1,0
(outputs)
ENET_TX_EN
ENET_TX_ER
M6
1 ENET_TX_EN,
ENET_TX_CLK, and ENET0_TXD0 have the same timing in 10-Mbps 7-wire interface mode.
ENET_CRS, ENET_COL
M9
1
ENET_COL has the same timing in 10-Mbit 7-wire interface mode.
M14
M15
ENET_MDC (output)
M10
ENET_MDIO (output)
M11
ENET_MDIO (input)
M12 M13
Figure 46 shows RMII mode timings. Table 66 describes the timing parameters (M16–M21) shown in the
figure.
M16
M17
ENET_CLK (input)
M18
ENET_TX_DATA (output)
ENET_TX_EN
M19
ENET_RX_EN (input)
ENET_RX_DATA[1:0]
ENET_RX_ER
M20 M21
4.10 Timers
This section provide information on timers.
4IMER )NPUTS
4 ). 4 ).(, 4 ).(,
4IMER /UTPUTS
Figure 48. 10 x 10 mm BGA, case x package top, bottom, and side Views
DCDC_IN L1, L2 —
DCDC_IN_Q K4 —
DCDC_GND N1, N2 —
DCDC_LP M1, M2 —
DCDC_PSWITCH K3 —
DCDC_SENSE J5 —
GPANAIO N10 —
NGND_KEL0 K9 —
NVCC_EMC E6, F5 —
NVCC_PLL P10 —
NVCC_SD0 J6 —
NVCC_SD1 K5 —
VDDA_ADC_3P3 N14 —
VDD_HIGH_CAP P8 —
VDD_HIGH_IN P12 —
VDD_SNVS_CAP M10 —
VDD_SNVS_IN M9 —
VDD_SOC_IN F6, F7, F8, F9, G6, G9, H6, H9, J9 —
VDD_USB_CAP K8 —
VSS A1, A14, B5, B10, E2, E13, G7, G8, H7, H8, J7, J8, K2, K13, L9, N5, N8, P1, P14 —
Table 82 shows an alpha-sorted list of functional contact assignments for the 10 x 10 mm package.
Table 82. 10 x 10 mm functional contact assignments
Default Setting
10 x 10 Power Ball
Ball Name
Ball Group Type Default Default Input/
Value
Mode Function Output
RTC_XTALI N9 — — — — — —
RTC_XTALO P9 — — — — — —
USB_OTG1_CHD_B N12 — — — — — —
USB_OTG1_DN M8 — — — — — —
USB_OTG1_DP L8 — — — — — —
USB_OTG1_VBUS N6 — — — — — —
USB_OTG2_DN N7 — — — — — —
USB_OTG2_DP P7 — — — — — —
USB_OTG2_VBUS P6 — — — — — —
XTALI P11 — — — — — —
XTALO N11 — — — — — —
11
Table 83 shows the 10 x 10 mm, 0.65 mm pitch ball map for the i.MX RT1050.
G F E D C B A
NXP Semiconductors
P N M L K J H
NXP Semiconductors
GPIO_SD_B1_08 GPIO_SD_B1_05 GPIO_SD_B1_02 GPIO_SD_B1_06 DCDC_PSWITCH GPIO_SD_B0_01 GPIO_EMC_08
3
P N M L K J H
Package information and contact assignments
91
Revision history
7 Revision history
Table 84 provides a revision history for this data sheet.
Table 84. i.MX RT1050 Data Sheet document revision history
Rev.
Date Substantive Change(s)
Number
Rev. 1 03/2018 • Updated the LCD display resolution in the Section 1.1, “Features
• Updated the Table 1 Ordering information
• Updated the Figure 1, "Part number nomenclature—i.MX RT1050"
• Added 24-bit Parallel CSI in the Figure 2, "i.MX RT1050 system block diagram"
• Updated the SJC description and DCDC input voltage in the Table 2 i.MX RT1050 modules list
• Removed ADC_VREF from the Table 5 Recommended connections for unused analog interfaces
• Updated the DCDC power in the Table 7 Absolute maximum ratings and Table 9 Operating ranges
• Updated the test conditions and DCDC supply voltage in the Table 12 Low power mode current and
power consumption
• Updated the Table 34 SEMC input timing in SYNC mode (SEMC_MCR.DQSMD = 0x1)
• Updated the parameters in the Section 4.5.2, “FlexSPI parameters
• Updated the Table 51 DCDC electrical specifications
• Updated the Table 52 12-bit ADC operating conditions
• Updated the notes of the Table 55 LPSPI Master mode timing and the Table 56 LPSPI Slave mode
timing
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