Interview Questions

1. What is physical design?
The physical design is the process of transforming a circuit description into

physical layout which describes position of the cells and routs for the
interconnections between them.
2. Which design is more complicated 10MHZ or 100MHZ?

100MHZ .Because high frequency means low time period. So it is difficult to
handle the violations in low time period.
3. What is floor planning?

The floor plan is the process of determining the macro placement, power grid
generation and I/O placement.
4. If you have both ir drop and congestion how will you fix it?
a) Spread the macros
b) Spread standard cells
c) Increase the strap width
d) Increase no. of. straps
e) Use proper blockages
5. What is HFNS (high fan out net synthesis)?

HFNS is the process of buffering the high fan out net to balance the load
6) What are the tie high and tie low cells?

These are used to connect the gate of transistor to either power or ground. It
avoid direct connection between power and gate of transistor
Tie high: one terminal is connected to Vdd and another terminal is connected to
Vss
Tie low: one terminal is connected to Vss and another terminal is connected to
Vdd
7) What are power gating cells?
The power gating is to avoid static power dissipation. The power gating cells
are
a) Power switches
b) Level shifters
c) Retention registers
d) Isolation cells
8) What are the checks to be done before cts?

a) Placement – completed.
b) Power ground nets – pre routed.
c) Estimated congestion – acceptable.
d) Estimated timing - acceptable
e) Estimated max transition/capacitance – no violations
f) High fan out nets
9) Where HFNS is used?

Generally at placement stage HFNS. It is also performed at synthesis step using
design complier.
10) What is electro migration?

When high current density continuously flows through a metal due to the high
current the atoms moving with kinetic energy and they transfer the energy to
another atoms and increases the temperature due to these metal will damage.
11) Is zero skew is possible?

Practically it is not possible because all the flip flops are not getting the same
clock. The skew is exist when the two different clocks are present. Zero skew
means all clocks are same practically it is not possible.
12) How to reduce latch up problem?
a) Increase spacing between p-well and n-well.
b) Increase well/substrate doping concentration.
c) Use ground rings around device.
13) What are the check lists after cts?

a) Skew report.
b) Clock tree report.
c) Timing reports for setup and hold.
d) Power and area report.
14) What is synthesis?

It is a process to convert RTL code into design implementation.
15) Which metal layer will be used for clock7 metal layer design?
Why?
Metal 4 and 5. Because the clock nets will consume 30 to 40% of power in the
design. So to reduce the IR drop we are using low resistance metal. Top 6,7
metal layers for power connection and 5,4 for clock nets.
16) What is antenna effect?

Increasing net length can accumulate more changes while manufacturing of the
device due to ionization process. If this net is connected to gate of mosfet it can
damage dielectric property of gate and causing damage to MOSFET.
17) What is cloning and buffering?

Cloning: It is a method of optimization that decreases the load of heavily loaded
cell by replacing the cell.
Buffering: It is a method of optimization that is used to insert buffer in high fan

out nets to decrease the delay.
18) Why NAND gate is preferred than NOR?
At transistor level the mobility of electrons is normally three times that of holes
compared to NOR and NAND gate is faster, less leakage.
19) What is LVS?

It is a class of EDA software that determines whether a particular layout
corresponds to original schematic of design.
20) What is shielding?

Placing ground net in between aggressor and victim nets then voltage discharge
on ground net. This will reduce the cross talk.
21) What is isolation cell?

These are the specials required at the interface between blocks which are shut
down and always on. It is necessary to isolate the floating inputs.
22) What is retention cell?

These cells are the special flops with multiple power supply. When design
blocks are switched off for sleep mode data in all flip flop contained desires to
retain state for this retention flops must be used
23) What are the i/p required for CTS?

a) Detailed placement database.
b) Target for latency and skew if specified.
c) Buffers or inverters to build the clock tree.
d) NDR rules
24) What are the CTS goals?

a) Minimize clock skew.
b) Minimize insertion delay.
c) Minimize power dissipation.

25) What are the effects of CTS?
a) Clock buffers are added.
b) Congestion may increase.
c) Non-clock cells may have been moved to less ideal location.
d) Can introduces timing and max transition/capacitance violations.
26) What are the different types of cells?

Tap cell: These are used to avoid the latch up problem.
End cap cells: These are placed at the edges to avoid cell damage at the end of
the row.
De cap cells: These are placed between power rail and ground rail to avoid
dynamic IR drop.
Filler cells: These are used to connect the gap between the cells.
27) What is HFNS?

To balance the load HFNS is performed. Too many loads will effects the delay
numbers and transition time. By buffering the HFNS the load can be balanced.
28) What is hard macro?

The circuit is fixed and we don’t know which type of gates using inside. We
know only timing information not the functional information.
29) What is soft macro?

The circuit is fixed and we know which type of gates using inside. We know
timing information and also functional information.
30) What is the formula for distance between macros?

Distance between macros = no. of pins * Pitch / available layers .
31) What is CTO (Clock tree optimization)?

It improves the clock skew and clock insertion delay by applying additional
optimization. CTO is performed during clock_opt process.
32) What is difference between normal buffer and clock buffer?
Clock buffer having equal rise and fall time but normal buffer not like that.
Clock buffer usually designed such that an i/p signal with 50% duty cycle
produces an o/p with 50% duty cycle.
33) What is global routing?

It is done to provide instructions to the detailed router about route every net. It
provide for interconnect to be routed.
34) What is detailed routing?

It is where we specify the exact location of the wire/inter connects in channels
specified by the global routing. Metal layer information of the inter connects are
also specified here.
35) Why should we solve setup violations before CTS and hold
violations after CTS?
Even if the hold fix is done before the CTS stage, the additional buffers in the
clock path add up (or in some cases reduce) certain amount of delay. Hence, it
is always recommended to fix the hold violations after the CTS stage.
36) What is the use of virtual clock?

It will help to reduce the delay of the overall operation. It is logically not
connected to any pin of the design and physically does not exist.
37) What is MMMC file?

It is a combination of mode and corner that is required for a particular timing
check such as setup and hold.
38) What is the difference between hierarchical design and flat

design?
Hierarchical design has blocks and sub blocks in an hierarchy. Flat design has
no sub blocks and it has only leaf cells. Hierarchy design takes more runtime
and flat design takes less run time.
39) During power analysis if you are facing IR drop problem then
how did you avoid?
a) Increase power metal layer width
b) Go for high metal layer
c) Spread macros or spread standard cells
d) Provide more straps
40) What are the types of routing?

a) Global routing
b) Track assignment
c) Detailed routing
d) Search and repair
41) What is body effect?

It is the change in threshold voltage resulting from voltage difference between
the transistor and body. This is caused by body biasing.
42) What is glitch?

Glitch is an electric pulse of short duration that is usually result of fault or
design error.
43) What are the benefits of SOI technology?

a) Low parasitic capacitance
b) High speed performance
c) Reduce short channel effect
d) No latch up
e) Low threshold
44) What are the guide lines for macro placement?
Fly lines, port communication, macros are placed at boundaries, spacing
between macros, macro grouping, macro alignment, notches avoiding,
orientation, blockages, avoid crisscross placement of macros.
45) What are the sanity checks in PD?

a) Check_library
b) Check_timing
c) Check_design
d) Report_constraints
e) Report_timing
f) Report_qor
46) What is the difference between halo and blockage?

Halo: It is the region around the boundary of fixed macros in design in which no
other macros or standard cells can be place. If macros moves halo will also
move.
Blockage: It can be specified to any part of the design. If we move block

blockage will not move.
47) Why we apply NDR rules before routing?

Sometimes with default routing it is very hard to avoid cross talk, electro
migration. Fixing the cross talk and electro migration in routing stage is
difficult. So we are applying NDR rules before routing.
48) What are the types of blockages?

Hard blockage: It doesn’t allow inverters, buffers, standard cells.
Soft blockage: It allows inverter and buffers and blocks standard cells.
Partial blockage: It will allows both buffers and standard cells in percentage
value.
49) What is congestion?
When the available tracks are less than the required tracks this effect will occur.
When the signals are more than the tracks the congestion will occur.
50) How to fix congestion?

a) Congestion driven placement.
b) Adjust cell density in congested area.
c) Use proper blockages.
d) Modify the floor plan stage.
51) What are the types in physical verification?

a) LVS
b) DRC
c) ERC
d) LEC
52) How to fix set up and hold violations at a time?

It is not possible to fix both at a time because if we increase the delay in data
path it’s good for hold and bad for setup. But there is only one way to fix it.
a) Buffer the data path for hold fix
b) Slow the clock frequency for set fix.
53) How can you avoid cross talk?

a) Increase the spacing between aggressor and victim nets.
b) Shielding
c) Maintain the stable supply
d) Increase the drive strength of cell
e) Layer jumping
f) Victim net width increases then resistance decreases

g) Guard ring
h) Cell sizing
54) What is cross talk?

It is the undesirable electric interaction between two or more physical adjust
nets due to the cross coupling capacitance. When two nets are in parallel the
electric field of one net is effects the other net which is nearer to it? This is
called cross talk effect.
55) What is scan chain reordering?

It is the process of reconnecting the scan chains in the design to optimize for
routing by reordering the scan chain connection which improves timing and
congestion.

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1. What is physical design?

The physical design is the process of transforming a circuit description into

2. Which design is more complicated 10MHZ or 100MHZ?

3. What is floor planning?

b) Spread standard cells

c) Increase the strap width

d) Increase no. of. straps

e) Use proper blockages

5. What is HFNS (high fan out net synthesis)?

6) What are the tie high and tie low cells?

8) What are the checks to be done before cts?

b) Power ground nets – pre routed.

c) Estimated congestion – acceptable.

d) Estimated timing - acceptable

e) Estimated max transition/capacitance – no violations

f) High fan out nets

9) Where HFNS is used?

10) What is electro migration?

11) Is zero skew is possible?

b) Increase well/substrate doping concentration.

c) Use ground rings around device.

13) What are the check lists after cts?

b) Clock tree report.

c) Timing reports for setup and hold.

d) Power and area report.

14) What is synthesis?

16) What is antenna effect?

17) What is cloning and buffering?

Buffering: It is a method of optimization that is used to insert buffer in high fan

19) What is LVS?

20) What is shielding?

21) What is isolation cell?

22) What is retention cell?

23) What are the i/p required for CTS?

b) Target for latency and skew if specified.

c) Buffers or inverters to build the clock tree.

24) What are the CTS goals?

b) Minimize insertion delay.

c) Minimize power dissipation.

b) Congestion may increase.

c) Non-clock cells may have been moved to less ideal location.

d) Can introduces timing and max transition/capacitance violations.

26) What are the different types of cells?

27) What is HFNS?

28) What is hard macro?

29) What is soft macro?

30) What is the formula for distance between macros?

31) What is CTO (Clock tree optimization)?

33) What is global routing?

34) What is detailed routing?

36) What is the use of virtual clock?

37) What is MMMC file?

38) What is the difference between hierarchical design and flat

b) Go for high metal layer

c) Spread macros or spread standard cells

d) Provide more straps

40) What are the types of routing?

d) Search and repair

41) What is body effect?