Computer Organization & Architecture Course Code: 4350701: Page 1 of 9
Computer Organization & Architecture Course Code: 4350701: Page 1 of 9
Computer Organization & Architecture Course Code: 4350701: Page 1 of 9
1. RATIONALE
This course provides details of the computer system as a whole and its functional
components as part their characteristics, working principles, performance, and internal and
external communication. Interactions including system bus, different types of memory and
input/output organization with Processor. This course also covers hardware architectural
issues and assembly language programming. On top of that, the students are also introduced
to the increasingly important area of hardware evolution and working fundamentals of
processor. This course provides domain specific fundamental knowledge of microprocessor
as well as computer system architecture, working, characteristic and communication with
peripherals which are essential for hardware related domain for all students of computer
engineering and allied branches.
2. COMPETENCY
The course content should be taught and implemented with the aim to develop different
types of skills so that students are able to acquire following competencies:
Examine computer architecture and explore assembly language programing using
8085 instructions set.
3 - 2 4 30 70 25 25 150
(*): Out of 30 marks under the theory CA, 10 marks are for assessment of the micro-project to
facilitate integration of COs and the remaining 20 marks is the average of 2 tests to be taken
during the semester for the assessing the attainment of the cognitive domain UOs required for
the attainment of the COs.
Legends: L-Lecture; T – Tutorial/Teacher Guided Theory Practice; P -Practical; C – Credit, CA -
Continuous Assessment; ESE -End Semester Examination.
5. COURSE MAP (with sample COs, PrOs, UOs, ADOs and topics)
This course map provides the student an overview of the flow and linkages of the various types
of learning outcomes to be attained by the students in all domains of learning leading to the
industry identified competency depicted at the center of this map.
Approx.
Sr. Unit
Practical Outcomes (PrOs) Hrs.
No. No.
required
List Branching and Looping instructions of 8085 with example and execute 3 4
8
basic 2-3 programs associated with said concept.
Total 28
Note
i. More Practical Exercises can be designed and offered by the respective course teacher to
develop the industry relevant skills/outcomes to match the COs. The above table is only a
suggestive list.
ii. The following are some sample ‘Process’ and ‘Product’ related skills (more may be
added/deleted depending on the course) that occur in the above listed Practical Exercises
of this course required which are embedded in the COs and ultimately the competency.
iii. Course faculty can set own’s rubrics for assessment.
1 Regularity 10
2 Concept clarity 30
4 Representation 20
Total 100
The ADOs are best developed through the laboratory/field-based exercises. Moreover, the
level of achievement of the ADOs according to Krathwohl’s ‘Affective Domain Taxonomy’
should gradually increase as planned below:
i. ‘Valuing Level’ in 1st year
ii. ‘Organization Level’ in 2nd year.
iii. ‘Characterization Level’ in 3rd year.
9. UNDERPINNING THEORY
Only the major Underpinning Theory is formulated as higher-level UOs of Revised Bloom’s
taxonomy in order development of the COs and competency is not missed out by the students
and teachers. If required, more such higher-level UOs could be included by the course teacher
to focus on the attainment of COs and competency.
Unit – I 1.1. Classify Evolution of intel 1.1.1. Observe the characteristic of Intel
Basics of Computer Processors processor from 4 bit (4004) to i7
Organization and 1.2.1. Basic CPU Structure
1.2. Prepare chart of Basic CPU
Processor Evolution CU, ALU and MU
Structure & Registers
1.3. Differentiate Bus Organization 1.2.2. Various Registers used in CPU & its
applications
AC, DR, AR, PC, MAR, MBR, IR
1.3.1. Types of Buses used in CPU
Common / Shared Bus v/s
Dedicated Bus
Serial Bus v/s Parallel Bus
Unit – II 2.1. Make a chart of 8085 2.1.1. 8085 Pin Diagram & Pin Functions
8085 Microprocessor architecture and 2.1.2. 8085 Microprocessor Architecture
Microprocessor describe it. 2.1.3. 8085 General Purpose Registers
2.2. Interpret 8085 Instruction 2.1.4. 8085 Flag Register
Execution 2.2.1. 8085 Instruction Execution
● Fetch
● Decode
● Execute operations
Unit – III 3.1. Describe Machine Language 3.1.1. Instruction format opcode &
8085 Assembly Instruction Format & Addressing Operands
Language Modes 3.1.2. Machine Language Instruction
Programming 3.2. Develop programs using 8085 Format: 1-Byte, 2-Byte & 3-Byte
Instruction Set 3.1.3. 8085 Addressing Modes
3.3. Classify various Interrupts of 3.2.1. Data transfer Instructions
8085 3.2.2. Arithmetical Instructions
3.2.3. Logical Instructions
3.2.4. Branching & Looping Instructions
3.2.5. Stack Instructions
3.2.6. I/O and Machine Control
Instructions
3.3.1. Classification of 8085 Interrupts and
its priorities
3.3.2. 8085 Vectored interrupts: TRAP, RST
7.5, RST 6.5, RST 5.5 and RST
Instruction
3.3.3. 8085 Non-Vectored Interrupts: INTR
Note: The UOs need to be formulated at the ‘Application Level’ and above of Revised Bloom’s
Taxonomy’ to accelerate the attainment of the COs and the competency.
items/questions assess the attainment of the UOs. The actual distribution of marks at different
taxonomy levels (of R, U and A) in the question paper may vary slightly from the above table.
● Project Idea 1: Identify any other microprocessor chip like 8085 prepare a model chart.
● Project Idea 2: Make collection of various storage devices and exhibit it in laboratory
● Project Idea 3: Make collection of various types of instructions sets.
● Project Idea 4: Make small scale Program in 8085.
● Project Idea 5: Collect various types of Discs and make a Chart with Explanation
● Project Idea 6: Prepare chart of memory hierarchy
● Project Idea 7: Prepare chart to show instruction pipelining
● Project Idea 8: Prepare chart of various processor evaluation
14. SUGGESTED LEARNING RESOURCES
a. http://www.ddegjust.ac.in/studymaterial/msc-cs/ms-07.pdf
b. http://www.iitg.ernet.in/asahu/cs222/Lects/
c. http://www.srmuniv.ac.in/downloads/computer_architecture.pdf
d. https://www.oshonsoft.com/8085.php
e. Sim8085 - A 8085 microprocessor simulator
f. https://www.sim8085.com/
g. https://youtu.be/8c6K0a8xC8w (for intel processor evolution -sample web resource)
Competency
Examine computer architecture and explore assembly language programing using 8085 instructions set
Sr.
Name and Designation Institute Email
No.
Government Polytechnic
1 Mr. S. B. Prasad [email protected]
Gandhinagar
Government Polytechnic-
2 Jiger P. Acharya [email protected]
Ahmedabad
A. V. Parekh Technical
3 Trivedi Niraj Rajeshkumar [email protected]
Institute, Rajkot