DVCon Europe 2015 TA1 8 Presentation
DVCon Europe 2015 TA1 8 Presentation
DVCon Europe 2015 TA1 8 Presentation
• UVM REG
– register abstraction layer
– programmer’s view
– integrates modeling, checking, stimulus generation and
(some) coverage
• Reuse sequences
– Abstract and conquer
Regitem(s)
Reg item(s)
Bus item(s)
if (!item.randomize() with {
item.burst_kind == SINGLE;
item.size == (rw.n_bits == 8 ? BYTE : (rw.n_bits == 16 ? HALFWORD : WORD));
item.direction == rw.kind == UVM_WRITE ? WRITE : READ;
item.addr == rw.addr;
item.data == rw.data;
})
`uvm_error("RANDERR", "Randomization error")
Constrain AHB burst
return item;
endfunction
endclass
• Register sequencer
– Only one interface
– Cumbersome
– Not versatile
start_item(burst);
finish_item(burst);
num_bytes -= burst.get_num_bytes();
offset += burst.get_num_bytes();
end
endtask
endclass
Move to next block
if (!burst.randomize() with {
addr == offset;
direction == rw_info.kind inside { UVM_READ, UVM_BURST_READ } ? READ : WRITE;
size inside { BYTE, HALFWORD, WORD };
(2 ** size) * burst_len <= num_bytes;
})
`uvm_fatal("RANDERR", "Randomization error")
return burst;
endfunction
endclass
• Non-intrusive changes
– Declare extra constraints in sub-classes
– Polymorphism
– UVM factory
// ...
ifx_ahb_mem_frontdoor::type_id::set_type_override(
ahb_frontdoor_single::get_type());
constraint single_word {
burst_kind == SINGLE;
size == WORD;
}
endclass
// ...
ifx_ahb_seq_item::type_id::set_type_override(
single_word_ahb_seq_item::get_type());
• Practical
– Abstract
– Stimulus reuse