tc3 Tutorial GCA FINAL
tc3 Tutorial GCA FINAL
tc3 Tutorial GCA FINAL
Advanced Constraint
Debugging
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Agenda
Customizing Rules
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Galaxy Constraint Analyzer
Timing Constraints Challenges
• 3rd party IP
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Galaxy Constraint Analyzer
Impact of Constraint Problems
Conflicting constraints
Tapeout delayed!
across hierarchy boundaries
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Galaxy Constraint Analyzer
Look-ahead Technology
• Constraint rule checking to find
missing, incorrect, conflicting or
Constraint Analysis & Debug
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Galaxy Constraint Analyzer
Values
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Galaxy Constraint Analyzer
Built-In Rule Categories
Boundary Conditions
CAP_xxxx – capacitance values
DRV_xxxx – drive constraints
EXD_xxxx – external delays
Exceptions and Case Analysis
CAS_xxxx – case analysis
EXC_xxxx – timing exceptions
Clocks
CLK_xxxx – clock properties
CGR_xxxx _ clock groups
CNL_xxxx – network latencies
CSL_xxxx – clock source latencies
CTR_xxxx – clock transitions
UNC_xxxx – clock uncertainties
General
DES_xxxx – design constraints
LOOP_xxxx – timing loops
NTL_xxxx – netlist
UNT_xxxx – library units
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Focusing the Debugging Effort
Specialized Debugging Commands
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Galaxy Constraint Analyzer
GUI Environment Snapshot
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Galaxy Constraint Analyzer
A Customer Example
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Agenda
• Principle
• Use Model
• Debugging Examples
Customizing Rules
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Block-to-Top Consistency Checking
Introduction
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Block-to-Top Consistency Checking
Principle
Chip_Top
Output
Input USB_core Delay?
Delay? MCP?
Clock
Signals?
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Block-to-Top Consistency Checking
B2T Rule Categories
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Block-to-Top Consistency Checking
Behavioral Constraint Checking
set_multicycle_path 2 \
–from [get_ports in1]
in1
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Block-to-Top Consistency Checking
Behavioral Constraint Checking
set_case_analysis 1 \ set_multicycle_path 2
[get_ports top1] –through [get_pins block/in1]
1
top1
top2 1 in1 1
top3
1
set_case_analysis 1 \
[get_ports top3]
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Block-To-Top Consistency Checking
Recommended Flow
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Block-To-Top Consistency Checking
Sample Script
gca_shell
read_verilog ${TOP_DIR}/design/TopLevel.v
read_verilog ${TOP_DIR}/design/BlockLevel.v
link_design Top
link_design –add Block
current_design Top
source ${CONSTRAINTS}/TopLevel.sdc –echo
analyze_design –verbose
current_design Block
source ${CONSTRAINTS}/Block.sdc –echo
analyze_design -verbose
current_design TopLevel
compare_block_to_top -block_design [get_designs Block] –verbose
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Block-to-Top Consistency Checking
Debugging a Clock Mismatch
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Block-to-Top Consistency Checking
Debugging B2T Violations
Selected
Violation
2 different suggested
commands to get more info
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Block-to-Top Consistency Checking
Dual SDC Viewer
• B2T violations involve two different sets of
constraints.
• Dual SDC browser allows you to compare them
side by side.
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Block-to-Top Consistency Checking
Debugging
Context
switching
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Block-to-Top Consistency Checking
Summary
• Block-to-top consistency checking allows you
to quickly analyze your IP constraints and
flags potential issues
– Very accurate, behavioral checking
– Dedicated violations addressing issues specific to
this comparison
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Agenda
• Principle
• Use Model
• Debugging Example
Customizing Rules
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Analyzing Constraints Changes
Need for SDC Versions Comparison
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Analyzing Constraints Changes
1 Netlist vs. 2 SDCs
Original Modified
Design.v Constraints Constraints
(SDC or Tcl) (SDC or Tcl)
Violations
Report
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Analyzing Constraints Changes
Behavior
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Analyzing Constraints Changes
Usage Model
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Analyzing Constraints Changes
Example
create_clock [get_ports clk] -period 30 -waveform {0 15}
set_clock_uncertainty -setup 0.45 [get_clocks clk]
create_clock -name clk -period 30 -waveform { 0 15 } [get_ports
set_multicycle_path 2 -through \ {clk}]
[list [get_pins {u7/mult/product*}]] set_clock_uncertainty -setup 0.45 [get_clocks {clk}]
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Analyzing Constraints Changes
Example GUI Output Violation Details and
Debugging Hyperlinks
Dedicated
Violations
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Analyzing Constraints Changes
Summary
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Agenda
Customizing Rules
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Customizing Rules
Why User-Defined Rules?
• Built-in rules:
Address most engineers’ needs
Cover a wide range of checks
But might not necessarily be a 100% match to
your design flow requirements
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Customizing Rules
Introduction
User-Defined Rules
Tailor the set of rules exactly to your needs
• Full control on what triggers a violation
• Full control on what gets reported whenever a
violation occurs
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Customizing Rules
Triggering a Violation
• A violation will be triggered if a certain condition is
present in the design
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Customizing Rules
What Objects Are Available?
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Customizing Rules
Use Model
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Customizing Rules
Writing the Tcl Checker
Get the objects of interest: all
the hierarchical pins
proc UDEF_OutDelay_0001_Checker {} {
set hier_cells [get_cells * -filter "is_hierarchical==true“ -quiet]
set hier_pins [get_pins -of_objects $hier_cells -quiet]
If there is an output
delay, the design violates For each pin, look for
our rule and triggers a an eventual output delay
violation.
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Customizing Rules
Declaring a New Rule
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Customizing Rules
Basic Example This example uses the
message only.
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Customizing Rules
Summary
• User Defined Rules are a great way to tailor the
rule sets to your exact needs
Enables the required quality checks for your company
and/or design
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Summary
Advanced Features Benefits
• Faster path to tapeout with 3rd party IP integration
and constraint versions verification
Constraints consistency can be easily verified
Very accurate and intuitive debugging features
Dedicated set of rules targeting specific issues to
these design stages
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