Accelerating LOES timing closure on a high

performance multimillion SOC.

Mahesh Rawal
Broadcom Inc

July 11-12, 2018

SNUG India

SNUG 2018 1
 Agenda

Introduction
LOES implementation methodology
Challenges in LOES timing closure
Proposed solutions to challenges seen
Results
Enhancements and Future work
Conclusion
SNUG 2018 2
 Acronyms

 PSE : Pipelined Scan Enable

 LOC : Launch on Capture
 LOS : Launch on Shift
 LOES : Launch on extra Shift
 STA : Static timing analysis
 PnR : Placement and Routing
 PVT : Process Voltage and Temperature
 CRPR : Clock re-convergence Pessimism Removal
SNUG 2018 3
 Introduction

SNUG 2018 4
Introduction: Transition fault testing
Launch on Capture (LOC)

• Fault sensitization through sequential ATPG engine

• Launch and capture happens during “capture”
• Often results in less ATPG coverage and more pattern
count compared to LOS

Launch on Shift (LOS)

• Fault sensitization through combinational ATPG engine

• Launch happens on shift and capture happens during
“Capture”
• Less pattern count and possible more coverage
compared to LOC
• Timing closure is extremely complex as all paths
starting from Scan enable to all flops need to be
closed.
SNUG 2018 5
Introduction: Transition fault testing
Launch off Extra Shift (LOES)

• Fault sensitization through sequential ATPG

engine
• Includes the merits of both LOS and LOC and
gives optimal fault coverage & test pattern count.
• Eases timing closure complexity issue of LOS
through a Pipeline flop on Scan Enable [PSE]

LOES ENABLE
Scan-
Scan-
Cells
SE D PSE Scan-
Q Cells
Scan-
Cells
Cells

CK

Though LOES provides relief to LOS timing closure problem, it is limited to low
frequencies. At higher frequencies LOES timing closure can pose a lot of issues.
SNUG 2018 6
 LOES Implementation Methodology

SNUG 2018 7
LOES Implementation Methodology
Scan
Scan- Scan
Scan- - Scan
Cells Scan- - Scan
Cells Scan- Cells -
Cells Cells -
Cells Cells
PSE Logic Cells

Scan
Scan- Scan
Scan- - Scan
PSE Logic Cells Scan- PSE - Scan
Cells Scan- Logic Cells -
Cells Cells -
Cells Cells
Cells
PSE Logic
Scan
Scan- Scan
Scan- - Scan
Cells Scan- - Scan
Cells Scan- Cells -
Cells Cells -
Cells Cells
Cells

Load Based Clock-tree Based

Divide the design based on load and put PSE flop. Put few PSE flops, place them manually and build a clock
tree for SE paths.
Backend Implementation starts during ICC Placement stage. Implementation starts with manual placement but Clock
tree building is critical

SNUG 2018 8
 LOES Implementation Methodology
• Inserts a PSE cell per “load” of sink registers.
• “Load” is pre-determined by discussions between PnR and DFT
teams.
DFT • Load can be provided through :
• set_scan_configuration -pipeline_fanout_limit $test_pipe_se_max_fanout

• STA mode is created which targets

• Atspeed paths from PSE flops to Scan Enable pins of Sink flops.
• DFT Specific at speed paths like OCC, Test points.
STA • Frequency, PVT Corners should match with functional mode.

• Implementation scenario is created to target LOES mode.

• Scenario is activated during placement, CTS and routing stages of
PnR backend implementation

SNUG 2018 9
 Challenges in LOES timing closure

SNUG 2018 10
Challenges in LOES timing closure
Placement challenges

• LOES paths are both setup and hold critical.

• PSE flop should ideally be located at central location
corresponding sink flops.
• Wrong placement of PSE flop can result in
• Huge buffer tree.
• Possible usage of leaky cells.

SNUG 2018 11
Challenges in LOES timing closure
Clocking challenges
• LOES paths are both setup and hold critical.
• Default configuration : DFT Compiler connects Clock source to PSE flop.
• “Internal_clocks –multi” option would treat “Any combo cell other than buffer,
inverter” as internal clock source.
• ICG outputs are NOT treated as internal clock source.
• Clock skew differences will exist between PSE flop and sink cell as sink cell
have ICGs along the clock path.

Scan-
Scan-
Cells Scan-
Cells Scan-
Cells
CG Cells
CG PSE SE
Logic

Hard Scan-
Scan-
Cells
Macro PSE Scan-
Top Existing On Chip Cells Scan-
Cells
Clock Clocking Controller Logic
SE Cells

PSE
CG
CG Logic
CG SE Scan-
COMBO Scan-
Cells Scan-
Cells Scan-
Cells
Cells
SNUG 2018 12
 Solution
Placement aware LOES

SNUG 2018 13
 LOES Implementation Methodology
CTS aware LOES
Scan-
Scan-
Cells
Scan- Scan-
Cells
Scan-
Cells Scan-
Cells
Scan-
Cells Cells
Scan-
Cells CG
Cells CG PSE
CG Logic
CG PSE
Logic

Hard Scan-
Hard Scan- Macro Scan-
Cells
Scan-
Cells Top Existing On Chip PSE Scan-
Cells
Macro SE
Existing On Chip PSE Scan-
Cells Logic Scan-
Cells
Top SE Clock Clocking Controller
Scan-
Cells Cells
Clock Clocking Controller Logic
Cells

PSE
PSE CG
CG CG Logic
CG Logic
CG Scan-
CG Scan-
COMBO COMBO Scan-
Cells
Scan-
Cells
Scan- Scan-
Cells
Cells
Scan- Scan-
Cells
Cells
Cells Cells

set_scan_configuration –internal_clocks multi set_scan_configuration –internal_clocks multi

+
Associated internal clocks

SNUG 2018 14
 LOES Implementation Methodology
CTS aware LOES

Take the DFT

inserted design
insert_dft to CTS stage
(Insert and check the
scan and clock skews
Define the PSE flops) between PSE
associated_inte and
rnal_clocks corresponding
Find the property Sink flop and
clocks( clock between Each CRPR.
roots) to which occ Slow clock
the ICG is port and
associated. corresponding
Identify all internal clock
Add other
the nodes collection
internal clock
functional for the domain
nodes to the
Clock driven by this
filtered
Gating OCC
collection
cells in the
design.

SNUG 2018 15
 Results

SNUG 2018 16
 Results – Uniform and Closely placed PSE

Design Information
Technology 16FF

34mm2
Size
Flop Count ~2.5 million
Number of Hardmacros 6
Highest operating frequency 1.66 GHz

Uniformly and closely placed PSE flops for one clock Domain

SNUG 2018 17
 Results – Average CRPR

Average CRPR in PS
66.9
WITHOUT CTS Aware
WITH CTS aware 98.7354

SNUG 2018 18
Results
Advantages

• PSE flops are placed uniformly across layout and close

to sink flops easing the timing closure.
• Probable less use of leaky cells to close the timing for
SE paths and hence reducing overall leakage power.
• Average CRPR is increased.

Overheads
Parameter Design with Design without
Scheme scheme
• Placement aware : LOCKUP 383 279
• Manual work involving two teams. Latches
PSE FLOPS 668 646
• CTS Aware : SCAN 1613 1514
• As internal clock sources are increased we see more
segments in
SCANDEF
number of scan segments in scandef, PSE flops &
Lockup Latches.
SNUG 2018 19
Enhancements and Future work
Associating internal clock nodes
with the OCC clock output.

• set_dft_signal –associated_internal_clock
property is NOT working with OCC Clock
Controller definition.
• Work around is we associate all internal
nodes to slow clock port driving OCC
• We are incorporating CTS aware LOES
methodology in all our designs.

SNUG 2018 20
 Conclusions

Less effort in timing closure.

Probable less usage of leaky cells to close the

timing.

High average CRPR.

Probably Reduced the complex timing ECOs in the

later stage of design cycle.
Achieved LOES timing closure for our design running
at 1.66 GHz
SNUG 2018 21
 Thank You

SNUG 2018 22