1.

A multiplexer with a register circuit converts

1. Serial data to parallel

2. Parallel data to serial
3. Serial data to serial
4. Parallel data to parallel

2. The outputs of SR latches in elevator state machine are feed

back to the ________ gate array for connection to the D-
flipflops.

1. NOT
2. AND
3. OR
4. XOR

3. UVERPROM is stands for

1. Ultra-Variant
2. Ultra-Vibrant
3. Ultra-Voilet
4. Ultra-Visible

4. The ________ gate and ________ gate implementation connected

at the B input of the 4-bit Adder is used to allow
Complemented or Un-Complemented B input to be
connected to the Adder input.

1. AND, NOR
2. AND, NOT
3. AND, OR
4. XOR, NAND
5. If the voltage drop across the active load is 0 volts due to
absence of current the comparator output is a ________.

1. 0
2. 1

6. As data values are written or read from the RAM Stack

Pointer Register increments or decrements its contents
always pointing to the stack ________.

1. Bottom
2. Top
3. Down
4. Vertex

7. The next state table for REQ1, FLOOR1 and OPEN inputs
indicates that the ________ can be pressed at any time either
on the first floor or the second floor in elevator.

1. REQ0
2. OPEN
3. REQ1
4. FLOOR1

8. Why demultiplexer is called a data distributor?

1. The input will be distributed to one of the outputs

2. The input will be selected for the output
3. The output will be distributed to one of the inputs
4. Single input to Single Output

9. Adding two octal numbers "36" and "71" result in ________.

1. 213
2. 123
 3. 127
4. 345

10. For a Standard SOP expression, a ________ is placed in the cell

corresponding to the product term (Minterm) present in the
expression.

1. 0
2. 1
3. x (don't care condition)
4. Any of given option depending on SOP term

11. The maximum value, represented by a single hexadecimal

digit is ________.

1. "E"
2. "F"
3. "G"
4. "H"

12. For a down counter that counts from (111 to 000), if current
state is "101" the next state will be ________.

1. 111
2. 110
3. 010
4. None of the given

13. Cin is part of ________ Adder.

1. Half
2. Full
3. Single
4. Double
14. When the transmission line is idle in an asynchronous
transmission

1. It is set to logic low

2. It is set to logic high
3. It remains in previous state
4. State of transmission line is not used to start
transmission

15. PLDs have In-System Programming (ISP) capability that

allows the ________ to be programmed after they have been
installed on a circuit board.

1. PLAs
2. PALs
3. PLDs
4. EPROM

16. A 3-variable karnaugh map has

1. eight cells
2. three cells
3. sixteen cells
4. four cells

17. Which signal must remain valid in memory write cycle after
data is applied at the data input lines and must remain valid
for a minimum time duration tWD?

1. -CS
2. -WE
3. W
4. OE
18. The ABEL Input file can use a ________ instead of the equation
to specify the Boolean expressions.

1. Truth Table
2. State Diagram
3. Karnaugh Map
4. Logic Circuit

19. In DRAM read cycle R /W- signal is activated to read data

which is made available on the ________ data line.

1. D(IN)
2. D(OUT)
3. D(AB)
4. D(INT)

20. GAL can be reprogrammed as instead of fuses E2CMOS logic

is used which can be programmed to connect a ________ with
a ________.

1. column, row
2. row, column
3. column, column
4. row, row

21. The ROM used by a computer is relatively ________ as it stores

few byres of code used to Boot the Computer system on
power up.

1. Small
2. Large
3. Heavy
4. High
22. Implementation of the FIFO buffer in ________ is usually takes
the form of a circular buffer.

1. RAM
2. ROM
3. PPROM
4. Flash Memory

23. If two numbers in BCD representation generate an invalid

BCD number then the binary ________ is added to the result.

1. 1001
2. 0110
3. 1111
4. 1100

24. 8-bit parallel data can be converted into serial data by using
________ multiplexer.

1. 4-to-2
2. 8-to-1
3. 4-to-4
4. 8-to-4

25. A decade counter can be implemented by truncating the

counting sequence of a MOD-20 counter.

1. True
2. False

26. The normal data inputs to a flip-flop (D, S and R, J and K, T)

are referred to as ________ inputs.

1. Sequential
2. Asynchronous
 3. Synchronous
4. Combinational

27. In distributed mode, for a 1024 x 1024 DRAM memory and a

refresh cycle of 8 msec, each of the 1024 rows has to be
refreshed in ________ when Distributed refresh is used.

1. 4.8 microsec
2. 5.9 microsec
3. 7.8 microsec
4. 5.5 microsec

28. If the number of samples that are collected is reduced by

half, the reconstructed signal will be ________ from/to the
original.

1. Different
2. Same
3. Equal
4. Opposite

29. The ________ input overrides the ________ input.

1. Asynchronous, synchronous
2. Synchronous, asynchronous
3. Preset input (PRE), Clear input (CLR)
4. Clear input (CLR), Preset input (PRE)

30. PALs tend to execute ________ logic.

1. SPD
2. SOP
3. SAC
4. SAP
31. Subtractors also have output to check if 1 has been ________.

1. Primed
2. Shifted
3. Complemented
4. Borrowed

32. Divide-by-32 counter can be achieved by using

1. Flip-Flop and DIV 10

2. Flip-Flop and DIV 16
3. Flip-Flop and DIV 32
4. DIV 16 and DIV 32

33. Demorgan's two theorems prove the equivalency of the

NAND and ________ gates and the NOR and ________ gates
respectively.

1. Negative-OR, Negative-AND
2. Negative-AND, Positive-OR
3. Positive-OR, Negative-AND
4. Positive-OR, Positive-AND

34. The S-R latch has two inputs, therefore ________ different
combinations of inputs can be applied to control the
operation of the S-R latch.

1. two
2. four
3. eight
4. sixteen

35. Select the mode of programming in which GAL16V8 can be

programmed:
 1. Simple Mode
2. Complex Mode
3. Registered Mode
4. All of the given

36. In NAND based S-R latch, output of each ________ gate is

connected to the input of the other ________ gate.

1. NOR, NAND
2. NAND, NOR
3. NOR, NOR
4. NAND, NAND

37. Flash memory Operation are classified into ________ different

operation.

1. Two
2. Three
3. Four
4. Five

38. ________ Counters as the name indicates are not triggered

simultaneously.

1. Asynchronous
2. Synchronous
3. Positive-Edge triggered
4. Negative-Edge triggered

39. The n flip-flops store ________ states.

1. 1
2. 2^n
3. 0
 4. 2^(n+1)

40. Implementing the Adjacent 1s detector circuit directly from

the function table based on the SOP form requires ________
gates for the 8 product terms (minterms) with an 8-input OR
gate.

1. 8 OR
2. 8 AND
3. 8 XOR
4. 8 NOR

41. A NOR based S-R latch is implemented using ________ gates

instead of ________ gates.

1. XOR, NAND
2. NOR, XOR
3. NOR, NAND
4. OR, XOR

42. Two types of memories namely the first in-first out (FIFO)
memory and last in first out (LIFO) are implemented using
________.

1. Shift Registers
2. Circular Buffers
3. Ring Buffers
4. Reduce Registers

43. Memory is arranged in ________.

1. linear fashion
2. two-dimensional manner
3. three-dimensional manner
 4. random fashion

44. Consider A=1, B=0, C=1. A, B and C represent the input of

three bit NAND gate, the output of the NAND gate will be
________.

1. Zero
2. One
3. Undefined
4. No output as input is invalid

45. The domain of the expression AB'CD + AB' + C'D + B is

1. A and D
2. B only
3. A, B, C and D
4. None of the given

46. Which of the following is a volatile memory?

1. PROM
2. DRAM
3. EPROM
4. EEPROM

47. In the keyboard encoder, how many times per second does
the ring counter scan the key board?

1. 600 scans/second
2. 625 scans/second
3. 650 scans/second
4. 700 scans/second

48. A SOP expression can be implemented by an ________

combination of gates.
 1. OR-XOR
2. AND-NAND
3. AND-OR
4. XOR-NOR

49. The terminal count of a 4-bit binary counter in the UP mode

is ________.

1. 1100
2. 0011
3. 1111
4. 0000

50. The output of a NAND gate is ________ when all the inputs are
one.

1. Zero
2. One
3. Available
4. Not available

51. An Asynchronous Down-counter is implemented (Using J-K

flip-flop) by connecting ________.

1. Q output of all flip-flops to clock input of next flip-flops

2. Q' output of all flip-flops to clock input of next flip-flops
3. Q output of all flip-flops to J input of next flip-flops
4. Q' output of all flip-flops to K input of next flip-flops

52. The NOR logic gate is the same as the operation of the
________ gate with an inverter connected to the output.

1. AND
2. NAND
3. OR
 4. NOT

53. You have to choose suitable option when your timer will
reset by considering this given code:
TRSTATE.CLK = clk;
TMRST: = (TRSTATE = = NSY2) # (TRSTATE = = EWY2);

1. NSY2 or EWY2
2. NSSR or TMRST
3. EWSR or NSRED
4. EWRed or EWYel

54. Two signals ________ and ________ provide the timing inputs to
the State Machine.

1. NSSR and EWSR

2. LTIME and STIME
3. PTIME and QTIME
4. NSGrn and NSYel

55. ________ is used when the output is connected back to the

input of the PAL or if the output pin is used as an input only.

1. Combinational Input/Output
2. Combinational Output
3. Combinational Input
4. Programmable polarity

56. In memory write cycle, the time for which the WE signal
remains active is known as the ________.

1. Write address setup

2. Write pulse width
3. Write delay width
 4. Write data time

57. The Static Ram (SRAM) is non-volatile and is not a ________

density memory as a latch is required to store a single bit of
information.

1. Low
2. High
3. Medium
4. Hot

58. The CONSTATE.CLK = Clock is used to indicate that the

________ state variables change on a clock transition.

1. CONSTATE
2. FLOOR
3. MOTION
4. OPEN

59. The Adjacent 1s Detector accepts 4-bit inputs. If ________

adjacents 1s are detected in the input, the output is set to
high.

1. 2
2. 4
3. 1
4. 0

60. The 64-cell array organized as 8 x 8 cell array is considered

1. as an 64 byte memory
2. as a 16 byte memory
3. as an 8 byte memory
4. as an 4 byte memory
61. Which of the following Output Equations determines the
output of the State Machine?

1. MIN = Q0Q1
2. MAX = Q0Q1EN
3. MIN = Q0Q1EN
4. MAX = Q1EN

62. In case of cascading Integrated Circuit counters, the enable

inputs and RCO of the Integrated Circuit counters allow
cascading of multiple counters together.

1. True
2. False

63. The FAST Model Page Access allows ________ memory read
and access times when reading successive data values stored
in consecutive locations on the same row.

1. Slow
2. Faster
3. Medium
4. Modern

64. The AND Gate performs a logical ________ function.

1. Addition
2. Substraction
3. Multiplication
4. Division

65. Canonical form is a unique way of representing ________.

1. SOP
2. Minterm
 3. Boolean Expression
4. POS

66. The Test Vector definition defines the test vectors for all the
three counter inputs and ________ counter output/outputs.

1. One
2. Two
3. Three
4. Four

67. The Synchronous SRAM also has a Burst feature which allows
the Synchronous SRAM to read or write up to ________
location(s) using a single address.

1. One
2. Two
3. Three
4. Four

68. A 4-bit binary up/down counter is in the binary state of zero.

The next state in the DOWN mode is:

1. 0001
2. 1000
3. 1110
4. 1111

69. Which one flip-flop has an invalid output state?

1. T
2. JK
3. SR
4. D
70. Implementation of Latch is required almost ________
transistor.

1. Two
2. Four
3. Six
4. Eight

71. The 74HC163 is a 4-bit Synchronous counter, it has ________

data output pins.

1. 2
2. 4
3. 6
4. 8

72. Consider the sum of weight method for converting decimal

into binary value, ________ is the highest weight for 411.

1. 64
2. 128
3. 256
4. 512

73. The Transition table is very similar to the ________ table.

1. Truth
2. State
3. Transition
4. None of the given