State merging and state splitting via state

assignment: a new FSM synthesis algorithm

M.J. Avedillo
J.M. Quintana
J.L. Huertas

Indexing terms: FSM synthesis, State assignment, State reduction, Design automation

on the binary encoding chosen. The problem of assigning

Abstract: In the paper the authors describe a state a binary representation to the control states is referred to
assignment algorithm for FSMs which produces as state assignment or state encoding. There are many
an assignment of non-necessarily distinct, and approaches for solving this problem, the heuristic ones
eventually, incompletely specified codes. In this being the most promising [6]. It is well known that state
new approach, state reduction and state assign- reduction and state assignment are intimately related.
ment are dealt with concurrently,and a restricted Reducing the number of states corresponds to decreasing
state splitting technique is explored. The algo- the number of transitions of the sequencing functions and
rithm is particularly appropriate for machines eventually to reducing the number of prime implicants in
with compatibility relations among its states a minimal Boolean cover of a two-level logic realisation
because the potentials of state merging are or reducing the number of literals in a multilevel one.
exploited during the state assignment step. The Moreover, a reduction of the number of states may
input to SMAS, the program implementing the correspond to a reduction of the number of bits that are
algorithm, is a symbolic cover of the FSM. The needed for the state encoding. Consequently, the first
output is a Boolean representation of both next phase in a traditional design system has been to obtain a
state and output functions suitable to minimise minimal FSM and the second one its optimal design.
with ESPRESSO. The machines in the MCNC More recently, it has been stated that the classical
benchmark set are used to test the new algorithm assumption of considering each problem in a separated
and to compare it with a well known state assign- way is no longer valid for modern technologies [7]. The
ment program. recommendation [7] is not to seek an FSM with the
minimum number of states but to replace the stages of
state minimisation and state assignment with one stage of
1 Introduction joint minimisation and state assignment. The previously
Computer-aided synthesis of sequential circuits is an mentioned work describes an approach based on parti-
active area of research as many modern CAD VLSI tion theory in which the classical constraint of state
systems treat the control unit of the designed circuit as a assignment using partitions (the product partition is the
finite state machine (FSM) realised with some regular zero partition) is removed. The method has important
structure. Two main problems encountered in the limitations like the treatment of incompletely specified
optimal synthesis of a sequential circuit are the mini- machines. In Reference 8 a state assignment algorithm
misation of the number of the machine’s internal states using the degree of freedom that two or more equivalent
and their assignment. The optimal solution to each of states can be given the same code is sketched. Also, the
these problems is very complex and, classically, they have need for a more general transformation of the FSM
received independent treatment. State reduction of com- aimed at obtaining an equivalent machine that is easier
pletely specified FSM can be achieved in O(n log n) steps to build has been pointed out [SI.
[l] whereas state minimisation of incompletely specified In this paper, a novel approach to the concurrent state
FSM is already NP-complete [2]. This means that most minimisation and state assignment is described. A
probably there will never be an algorithm of less than restricted state splitting technique is also explored. The
exponential complexity and therefore heuristic techniques need for state splitting for optimal state assignment was
must be used. This problem has received renewed atten- pointed out as early as the 1960s. In Reference 10 state
tion in the past few years and very efficient approaches splitting is introduced to increase the possibilities of
have been developed to cope with it [3-51. In order to finding good assignments. Reference 11 relates the exist-
realise the behaviour of a sequential machine it is neces- ence of a type of sequentially redundant faults with the
sary to represent the states by binary sequences. The use of state assignment algorithms which do not take
complexity of the required circuits often strongly depends into account state splitting.

0IEE, 1994 2 Preliminaries

Paper 1228E (C2, E3), first received 26th July 1993 and in revised form 2.1 Background
22nd February 1994
The authors are with the Departamento de Diseiio Anal6gico, Centro
For the sake of completeness some basic concepts in
Nacional de Microelectronica, Edii CICA, Avd. Reina Mercedes s/n, FSM synthesis will be briefly reviewed in this Section
41012 - Sevilla, Spain and the Departamento de Electrbnica y Electro- [12, 131. An FSM can be formally defined as a quintuple
magnetimo, Universidad de W l a M = (I,S, 0, 6, A) where I is a finite set of inputs, S is a
IEE hac.-Cornput. Digit. Tech., Vol. 141, No. 4, July 1994 229
finite, non-empty set of states, 0 is a finite set of outputs, We can split the state s3 into two states called si and
6:f x S - + S is the next state function, and d’ with
1:f x S + O(k S + 0)is the output function for a Mealy 6(x, s;) = 6(x, s;) = 6(x, s3)
(Moore) machine. Either of these functions may be
incompletely specified (i.e. the value of the function need and
not be defined for all possible inputs). We can represent
any deterministic sequential function with this model. qx, si) = qx, s;) = A(x, s3)
The FSM can be separated into two components: a com-
binational circuit and a memory. The memory stores the XP2

(binary) representation of the FSM state throughout 00 01 11 10

computation whereas the combinational circuit generates
S Z I0 s3,-
machineoutput andnext state representation as a func- s-,0
sl. 0
tion of the inputs and the present state. s-.0
sl, 1
Two internal states, Si and S,, of a machine M are s-, - s2.-
compatible if and only if, for every input sequence applic-
s-,- S,. 1
able to both Si and S,, the same output sequence will be -
produced whenever both outputs are specified regardless
of whether the initial state is Si or S,. A compatibility a
class or compatible C, is a set of states such that
members of the set are pairwise compatible. If there is an XIX2
input such that S, is the next state of Si and SIis the next 00 01 11 10
state of S, and ( S k , SJ # (Si, S,) then we say that ( S k , SI)
is implied by (Si, S,). A set of compatibles covers all states s2. 0
of a state table if every state is contained in at least one s-,0
compatible in the set. A set of compatibles is closed if for s,,1
each compatibility class in it, Ci = {Sil, S,,, . .., Sh} and NS. z
...,
any input i,, the set {6(ik, Sil), 6(ik, Siz), 6(ik, Si,,,)} is
b
contained in at least one compatible of the collection. A
fundamental theorem states that, given an incompletely
specified state table, another state table specifying the 10
same external behaviour corresponds to each closed set
of compatibility classes which covers all internal states of
the given table [14]. 01 0 m
11

2.1 Previous examples Y1YZ.Z

In this Section two simple examples are given. Both C
examples will illustrate several useful considerations. The Fig. 1 FSM design with state reduction
first example shows a way of assigning the machine’s NS:next state, z:output
a state table
states which is equivalent to the assignment of the pre- b closed covering C and reducedstate table
viously reduced machine. The second describes a way of e state assignment and transition tabk
assigning the states which is equivalent to the assignment
of the machine after having split some states. The use of XIX2
D type memory elements is assumed in both examples. y,yz 00 01 11 10

s, -00 00 01,-
Example I: Fig. la depicts the state table of an FSM. --,0
sz-rOO 00
The closed covering and the reduced state table obtained --,0
s, + 01 01
by the application of a state reduction algorithm to the
se-11 11 00.-
symbolic description in Fig. l a are shown in Fig. lb. Fig.
sp11 11 00.1
le depicts the state transition table and the state encod-
ing. This result can also be reached assigning the same a Y,Yz.z
code to states s1 and s2, and to the state s, and s5 in the b
original machine. Fig. 2 shows the transition table. Note Fig. 2 FSM assignment with repeated codes
that there are input-present state combinations which a state assignment
belong both to the DC-set and ON-set (OFF-set) of one b transition tabk
or several next state and/or output functions. There is no
input-present state combination belonging simultan- for each input value (x = 0 and x = 1). Fig. 4a shows the
eously to the ON-set and to the OFF-set. Specifying resulting state table. Both si and s’; appear in those cells
those combinations simultaneously in the DC-set and corresponding to input-present state combinations with
ON-set (OFF-set) as part of the ON-set (OFF-set), the s3 as next state in the original description (Fig. 34. This
transition table in Fig. 2 becomes identical to the one in means that any of them can be used to describe the
Fig. le that was obtained with the conventional two step behaviour of the machine. The state transition for the
synthesis approach: state reduction and state assignment. encoding of Fig. 4b is depicted in Fig. 4c. Excitations and
output functions (Fig. 4d) requires only four product
Example 2: The state table of another FSM is shown in terms. The logic minimiser takes advantage of the extra
Fig. 3a. An encoding Fig. 3b, the transition table Fig. 3c degree of freedom introduced by the state splitting. That
and the excitation and output functions requiring five is, choosing 6(0,00) = 10 and 41, 00) = 11 produces a
product terms Fig. 3d are also shown. cheaper implementation.
230 IEE Proc.-Comput.Digit. Tech., Vol. 141, No. 4, July 1994
 The above examples illustrate the state reduction and points out the convenience of considering state splitting
state assignment can be dealt with concurrently and in the context of optimal synthesis of FSMs.
X
0 1
3 Rationale of the new approach
Let us briefly show how the goals of state reduction and
S2
state splitting are achieved by a coding process which
s3 s,.o s,.o
allows a single code to be assigned to a group of states
NS, z and the use of incompletely specified codes.
a Assigning a single code to a group of states is equiva-

-
lent to the transformation of the FSM description by the
s, -00 substitution of a group of states with one single state
s, 01 (state reduction) and the assignment of this internal state
s,-10 in the new description. From classical state reduction
b theory we know that the states which are merged into
one state must be compatible and closure constraints
X
must be satisfied [12, 141. These conditions are used as
Y1Y2 0 1
constraints in our encoding process. That is, the state
reduction is achieved during the assignment process.
01 Assigning an incompletely specified code [13] (group
11 of codes) to a single state is equivalent to the transform-
10 00.0 01.0 ation of the FSM symbolic description consisting in the
substitution of a single state by a group of states (state
Y,Y,,z splitting) and the assignment of this new description.
C There are two reasons for allowing incompletely specified
codes as follows.
Y, =V,fz (1) It is important to cope with the concurrent state
Y , = w , +XY, reduction and state assignment of incompletely specified
z =X'Yz +M,VZ FSMs. In general, for these machines, a closed set of
d compatibles covering a state table (solution to the classic
Fig. 3 Example 2 state reduction phase) is not disjoint. A non-disjoint
(Istale table c transition table gathering of states cannot be achieved via state assign-
b state assignment d excitation and output fundions ment if incompletely specified codes are not allowed.
Thus, concurrent state reduction and state assignment
X
would fail to reach a part of the space of solutions, so
0 1 precluding the possibility of finding some efficient ones.
(2) The Boolean cover of the machine which is sup-
plied to the logic minimiser can have extra flexibility in
this way, because some next state entries have been sub-
stituted by a group of states. The minimiser can take
advantage of this by choosing each time the best state of
NS. z the group to achieve minimisation. In Reference 15 it is
a reported that allowing 'don't care' bits in a state assign-
ment often results in a significant reduction of the com-
s, -00 binational component.
s, -+ 01 Nevertheless, this state splitting is restricted, because
s;+11 the codes assigned to the set of states resulting from the
s;-10 splitting of an original one are constrained to form a
b cube.
X
Y1Y2 0 1 3.1 Basic definitions
In order to formalise the above ideas, several definitions
are introduced.
01
11 01.0
Definition 1: Let ai and bi be two variables which can
take the logic values: 0, 1, and unspecified ("). The inter-
Y,Y,.z section operator n is defined according to following
C table.
y , =Y\Vz ai
Y, = x n O 1 -
2 =x'Y;Yz +wV;v,
d
Fig. 4
a split stale table c transition table
b state assignmm1 d excitation and output functions

IEE Proc.-Comput. Digit. Tech., Vol. 141, No.4, July 1994 231
Definition 2 : Let C(S,) = (yl . .. y ,,,) and C(S,) = state assignment is only free to encode the states in such
(v2, . .. yzJ be the codes of the states S, and S , , respect- a way that a minimal area implementation of a given
ively. Assume each y i j can be logic 0, logic 1 or be, state transition graph (STG) is obtained. The problem we
unspecified. The intersection of the codes C(S,) and propose to solve is more general in the sense that a
C(S,), C(S,) n C(S,) = C, = (c,, . .. c,-,,,), is defined as minimal area implementation of an FSM is sought. As
many STGs can implement the same functionality, our
c,, = y , , n yZj 1 C j d n approach enlarges the search space compared with clas-
i f 3 j l c n , = 0 thenC,=@ sical techniques.
Transformations of the STG like state splitting and
The meaning of C , = 0 is that the set of binary codes state merging are made concurrently with the binary
assigned to S, and the codes assigned to S, have no encoding instead of in a separate synthesis step (state
common elements. reduction) as in conventional design procedures. In this
way the STG transformation is guided by more realistic
Definition 3: Two states S, and S , have compatible criteria than the ones used in symbolic STG manipula-
assignments if the intersection of their codes, C(S,) n tions.
C(S,), is not empty. The problem we propose to solve can be stated as
For example, assume the state S, has been given the
code (001-) and the state S, the code (0010). S, and S, ‘Obtain a valid assignment of the states of the FSM
have compatible assignments because (001-) n (0010) = leading to a minimal area implementation of the
(0010). Identical assignments is a particular case of com- machine’.
patible assignments when the codes of both states are
completely specified.
4 The algorithm
DeJinition 4 ; Two states have discriminated assignments Given a state table describing the external behaviour of
if the intersection of their codes is empty. an FSM, a valid binary representation is built up by
exploring both the potentials of state merging and state
Definition 5 : Given an FSM, an encoding of its states is splitting. Given ns internal states in the symbolic descrip-
valid if the encoded machine and the symbolic descrip- tion, we assume that ns x nb bits are going to be assigned
tion are equivalent; that is, the derived logic implements to a value from the set {0, 1, -}, where nb is the number
the desired behaviour. of bits of the generated codes, and so it is unknown until
the algorithm has finished the assignment process.
Our assignment process is equivalent to both the trans- Fig. 5 shows a Pidgin-C description of the algorithm.
formation of the symbolic description of the FSM and to
the assignment of this new description. Some constraints
need to be imposed on the encoding so that the behav- SMAS (T)
iour of the machine is not changed by the state reduction f
Discriminated-irs = 0;
achieved concurrently with the assignment. Translating
Identicaljmin = 0;
the concepts of symbolic state reduction theory to the lmplied-bv_identicalRai~ = /a;
state assignment context and using Delinitions 1 to 5, it Compulsory_discriminationjmirs=pairs of incompatible states;
can be stated that in order to guarantee that an encoding nb = nb, = Initial-length();
is valid the following constraints must be satisfied. Sinit=s,;
(1) A pair of states with compatible assignments must while ( Compulsory_discriminationjmin! = (0) )
be compatible states or, a pair of incompatible states } (s,, s,) = Selectgair(Compu/so~~discriminationjmin);
must be given discriminated assignments. Discriminategsir(s,,s,);
(2) For each input, the pairs of states which are Update-structures() ;
implied by a pair of states with compatible assignments }
must also have compatible assignments or, the pairs of }
states which imply a pair of states with discriminated DiscriminattmJJair(s,,s,)
assignments must also be given discriminated assign- Candidate-assignments = Explore-codes (s,,S,);
{
ments. if ( Candidate-assignments I ={/a} )
{ for (each assignment E Candidate-assignments)
3 2 New state assignment problem formulation { Evaluate-cost (assignment);
Classically the optimal state assignment problem is for- }
selects minimum cost assignment;
mulated as
1
‘Obtain a distinct single binary code for each state else
of the FSM so that given design constraints are satis- { lncrease_code_length();
fied’. Discriminatepair(s, ,s,);
}
Typical design constraints are that the circuit must be }
constructed with a minimal amount of logic or that Fig. 6 Algorithm’s description @setdocode)
circuit can be built from an interconnection of smaller
subcircuits to obtain superior performance, or that it can
be easily testable. Most of the state assignment algo- Initially the codes of all the states are completely unspeci-
rithms aim to minimise the area of an implementation of fied, the algorithm assigns bits to 0 or 1 until the assign-
the combinational component assuming a predetermined ment is valid according to conditions 1 and 2 stated in
design style (two level, multilevel). Section 3.1. In order to describe how the algorithm
However since a unique code, different from the codes works, we introduce the concept of pair of compulsory
of all other states, must be assigned to each state, the discrimination.
232 IEE Proc.-Cmput. Digit. Tech., Vol. 141, No.4, July I994
DeJnition 6: Two states form a pair of compulsory dis- Procedure Update-structures updates lists DP, IP, IIP
criminationif they cannot have compatible assignments. and CDP. For example, to update CDP we remove from
it those pairs which have been discriminated and add
Incompatible states, and those pairs which imply a pair those implying other pairs just discriminated. Fig. 6 sum-
with discriminated assignments, are pairs of compulsory marises the update procedure.
discrimination.
First we explain the meaning of the data structures. Update of data structures: Update-structures
The list of state pairs with discriminated assignments Let ( s i , s i ) be the discriminated pair.
is stored in Discriminated-pairs (DP); the list of state
+ on list Discrirninated-pairs:
pairs with identical assignments in Identical-pairs (IP);
the list of state pairs which are implied by at least (1) Addition of ( s i . s i ) .
another pair of states with identical assignments in (2) Addition of pairs (si. s k ) or (si, s,.),with k # i, k # j , whose
Implied-by-identical-pairs (IIP) and the list of state pairs assignments have been discriminated as a consequence of
which must have discriminated assignments in assigning a bit of si and/or s i .
Compulsory-discrimination-pairs (CDP). + on list Identical>irs:
The algorithm starts initialising the above lists. The (1) Addition of pairs (st, s k ) or ( s i , se), with k # i. k # j . whose
lists DP, IP, IIP are empty. The list CDP is initialised to assignments are identical as a consequence of assigning a
the set of pairs of incompatible states. bit of si and/or s i .
The initial length of the codes, nb,, is determined.
Since our state assignment algorithm allows state + on list Irnpli~-by_identiwlgairs:
merging and state splitting the length of the resulting (1) Addition of pairs implied by (si. s k ) or (si, s k ) . with k # i ,
encoding is not known beforehand. We start with the k # j . whose assignments are identical as a consequence of
number of bits needed to encode as many states as there assigning a bit of si and/or si. The implication concept is
applied recursively.
are in the maximal incompatible of highest cardinality.
Afterwards, the length of the codes will be increased by --t on list Cornpulso~-discrirnination-pai~:
one bit each time the intermediate assignment cannot be (1) Elimination of ( s i , s i ) .
turned into a valid one with the current number of bits in (2) Elimination of t h m pairs (s,,sk) or ( s i , s,.), with k # i ,
the encoding. To finish the initialisation block, the first k # j , whose assignments have been discriminated as a con-
state in the symbolic description, SI, is selected to have sequence of assigning a bit of s, and/or si.
nb, bits assigned to 0. (3) Addition of pairs (s,,, s
,) implying any pair (si, s,.) or (si,
The basic operation in the process is the discrimi- s k ) , whose assignments have been discriminatedas a conse-
nation of a compulsory discrimination pair quence of assigning a bit of s, and/or s i . The implication
(Discriminate-pair). This operation is repeated until the concept is applied recursively.
list CDP is empty. The pair (Si,Si)to be discriminated
Fig. 6 Update of data structures cflfer having discriminated the pair
next is selected according to a heuristic criteria which will
(Si. S j )
be explained later.
Procedure Discriminate-pair assigns a single bit of the
code of the states Si and/or S j so that these two states Finally, we demonstrate that a state assignment
have discriminated assignments. To achieve the discrim- derived with this algorithm is valid according to condi-
ination, 6rst all legal bit assignments leading to the dis- tions stated in Section 3.1.
crimination of S, and Si are enumerated. Function
Explore-codes stores them in Candidate-assignments. Theorem 1: Given an FSM, an encoding of its states
A bit assignment is not legal if any of the following derived with previous algorithm is a valid assignment.
situations arises:
(a)there is at least a state pair (S,, Sk), m = i, j; k # m, Proof:
which now have identical assignments but it belongs to (a)Suppose it is not a valid assignment because there
CDP; are pairs with compatible assignments which are no com-
(b)there is at least a state pair (S,, S&, m = i, j;k # m, patible states. This would mean an incompatible pair has
which now have discriminated assignments but it belongs not been discriminated yet and so the list of pairs of com-
to IIP. pulsory discrimination would not be empty as it is the
If either (a)or (b) occurs, the number of bits will have to condition for the process to finish.
be increased before a valid encoding is reached. It is (b) Suppose it is not a legal assignment because there
important to point out that legal bit assignment does not are pairs which have compatible codes but they imply
mean that there is guarantee of the existence of a valid pairs with discriminated assignments. This is not possible
encoding with current code length. However, trying to because when discriminating those implied pairs, the
discriminate a given pair using legal bit assignments implying pairs would have been added to the list of pairs
helps in keeping the code length short and has proven to of compulsory discrimination (see Fig. 6).
give good results. The lists IP and IIP are used to easy
and efficiently detect that a given bit assignment is not 4.1 Considerations about order strategies and cost
legal. function
Next, a cost function for each member of It is worth noting that the straight application of our
Candidate-assignments is evaluated and the one which algorithm does not guarantee that the length of the codes
minimises it is selected. Finally, if Candidate-assignments is a minimum. However, several heuristics have been
is empty, the function Increase-code-length adds one developed in order to achieve efficient assignments. For
new state variable. Since the code of every state has the example, the order in which pairs of states are discrimin-
new bit unspecified, there is no state pair with identical ated and the cost function are critical. Very efficient order
codes and so the lists Identicallpairs and strategies have been introduced so that codes longer than
Implied-by-identical-pairs are emptied. minimum ones are not usually generated. Moreover, the
IEE Proc.-Comput. Digit. Tech., Vol. 141, No. 4, July 1994 233
potential of state merging leads, in some cases, to assign- assignments implies the addition of pairs to that list. The
ments with a number of state variables which is less than fist and third options glienate the pairs (s,, s8) V d
the minimum needed to code the number of states in the (sl, s,). The second and fourth discriminate the pans
initial symbolic description. The number of pairs in CDP (s,, s8) and (sl, s,). In this case the first assignment is
each state belongs to is evaluated. For state Si this arbitrarily selected. This is frequent at the first stages of
number is referred to as Ind (Si). Each state pair (Si, Si)in the procedure because there are many unspecified bits in
CDP has associated an index equal to the sum of Ind (Si) the codes of the states. The data structures are updated
and Ind (Si).In each iteration the pair with the maximum and the results are
index is discriminated.
The cost function has been designed to force the Code matrix:
number of bits to be small. In this sense each pair of s1 00 s2 - s3 - s, -
states is discriminated so that the cardinality of the
resulting Discriminated-pairs list is a minimum. It also s5 - s, 1- s7 - sg 0-
aims at reducing the area of final realisations by taking
into account the fulfillment of the adjacencies derived Compulsory-discrimination-pairs = {(si, s3), (sir SS),
from Humphrey’s or Armstrong’s rules [16, 171. (s2 3 s7), (s2 > s8b (s3 SS), (s3
6 2 7 s6), (s4,s6), (s4,s7)?
7 9

(sS, s6)r (ss 9 s7)9 6 7>

4 2 Example 3
As an example of how the algorithm works we use the Iteration 2: The pair selected to be discriminated is
FSM shown in Fig. 7 taken from Reference 18. To sim- (s7, se). Candidate bit assignments are
plify the explanation only the first mentioned cost criteria (1) s7 1- (2) s, -1 (3) s7 -0

g
is evaluated.
ss C
L se 00 sg 01
OOO 001 010 011 100 101 110 Those bits already assigned appear in bold. The cost
function is evaluated for first and third assignments but
not for the second one. This is because it is not legal.
Clearly if this second option is taken, the states s1 and ss
have identical assignments but the pair (si,s8) belongs to
the list of pairs of compulsory discrimination. The dis-
crimination of two states with identical codes can only be
achieved by adding a new state variable.
s. 0 The assignment (1) discriminates the pairs (s7, se) and
(sl, s7). The pair ( s 7 , s8) is the only one removed from the
NS, z CDP list. The discrimination of (sl, s7) which did not
belong to CDP involves adding to that list those state
Fig. 7 State tablefor FSM in Example 3
pairs which imply (sl, s7) and have not discriminated
assignments. In this case the pairs (s3, sq), (s3, s7) and
Initialisation phase (s3, s,) must be added to the list. The cost of this assign-
N , the cardinality of the largest maximal incompatible, ment is 14 (there are 14 pairs in the resulting CDP list).
is three and so the initial code length nb = nb, = The assignment (3) discriminates the pairs (s7, se) and
Clog2 NI = 2 (sl, se) which are then removed from CDP. It does not
reqlure the addition of any pair to that list and so its cost
Code Matrix: is 10.
s1 00 s2 - s3 - sq - Assignment (3) is chosen since it minimises the cost
function. Updated data structures are
s5 - s, - s7 - ss -
Code Matrix:
Discriminated-pairs = ; {a}
Identical-pairs = ; {a}
Implied-by-identical-pairs = {a} s1 00 s2 - s3 - s, -
Compulsory-discrimination-pairs = incompatible state ss - s6 1- s7 -0 ss 01
pairs = {(sl, s3b(sly (sl. sa), (s2, s6), ( ~ 2s7),
s6)9 , ( ~ 2SE),
,
(s3 9 s5), (s3 9 SE), (s49 s6h (s4 9 s7)r (s5 9 s6)9 (ss 9 s7), (ss I s8b Discriminated-pairs = {(sl, s& (sir s8), (s6, s8), ( ~ 7 ~, 8 ) )
(s7, se)} Identical-pairs = { ; a}
Implied-by-identical-pairs = { 0)
Compulsory-discriminationgairs = {(sl, s3), (s2, se),
Assignment phase
(s2 s7), (s2 Ss), (s3 3 sg), (SI ssb (s4 s6), (s4 s7)9 (ss s6),
Iteration I : The number of pairs in CDP each state 9 9 9 9 9 9

belongs to is evaluated. The pair (s,, se) maximises the (ss s7))
7

+
parameters Ind (Si) Ind (Si)and so this pair is selected
to be discriminated in this stage. Iteration 3 : The pair (ss,sa) is discriminated next. Again
The assignments which discriminate the states S, and candidate assignments are enumerated
Ss are
(1) s6 1- (2) s6 0- (3) 36 -1 (4) s6 -0 (1) s3 1- (3) s3 -1
~5 0- cost = 6 s5 -0 cost = 9
S8 0- S8 1- se-0 S8 -1
The four assignments have the same cost. In every case (2) s3 0- (4) s3 -0
the resulting CDP list has 12 elements. None of the four s5 1- cost = 15 SS -1 cost = 14
234 I E E Proc.-Comput. Digit.Tech., Vol. 141,No. 4, July I994
 Table 1 : Example 3 summary
Iteration 4 Iteration 5 Iteration 6 Iteration 7
Pair to discriminate (s2,s,) (%I Se) (s3,ss) (s2. SEJ
Minimum cost s, & s3 1- s3 11 s2 00
discriminating s, 10 s4 0- se 10 ss 01
assianment cost = 6 cost = 3 cost = 1 cost = 0

Assignment (1) is selected and updated data structures combinational component in an PLA implementation of
are the FSM and the time which is required for design.
Table 2 depicts the results for the first group of
Code Matrix: machines and Table 3 for the second group. The number
s1 00 s, - s3 1- s4 - of primary inputs ( n ~ ]primary
, outputs (no) and states (ns)
are shown for each of the machines to which SMAS (C
s5 0- S6 1- s, -0 ss 01 implementation of the new algorithm), NOVA [21]
Discriminated-pairs = {(sl, s6), (sl,s3), (s,, s8), (sj, s5), (i-hybrid algorithm*), and a synthesis procedure includ-
(s3 (s5 s6). s8b ( s 7 , s 8 ) )
ing state reduction (ARNES [5] + NOVA i-hybrid) have
9

Identical-pairs =
9

; {a}
9
been applied. The number of state variables (nu), the
Implied-by-identical-pairs = {a} number of product terms (tp) after logic minimisation
and the size ((2ni + 3nu + no) x tp) of the PLA imple-
Compulsory-discrimination-pairs = {(s2, s6), (s2, s,),
(82 s8b (s4, s6), (s4 s 7 ) 9 (s5 s 7 ) }
9 9 9
menting the combinational component for the assign-
ments obtained with each program after code shifting?
While CDP is not empty the algorithm follows discrimi- and minimisation with ESPRESSO [22] are also shown
nating state pairs. The remaining iterations do not intro- in Tables 2 and 3. Times are given in seconds in a SUN
duce anything new. Table 1 presents a summary. Workstation 4/330. Columns with ratio of sizes, A, and
The state assignment obtained with the algorithm is: A , are included with:
s1 00 s, 00 SJ 11 s4 0-
sizeSMAS A, = SizeSMAS
A, =
s5 0- S6 10 s, 10 S8 01 S ~ Z ~ N O V A . & ~ SiZe(ARNES)+ (NOVAawu)
The state encoding derived with our algorithm is equiva- Both tables show that in all the cases the number of
lent to the following state merging C = {(sl, s2, s4, ss), state variables in SMAS's assignments is less than or
(s3), (s6. s7), (s4. s5, s8)}. So the coding procedure is equal to the number of state variables in NOVA's assign-
equivalent to the generation of a symbolic description ments. Concerning group 1 machines, SMAS obtains
with four states and to the binary encoding of it. more efficient implementations (in terms of size) than
A two level realisation of the FSM using this encoding NOVA in 15 of the 17 machines in Table 2. In particular,
requires eight product terms and two memory elements. let us focus on the set formed by donzfile, modulol2, s l a
Using the symbolic description in Fig. 7 as input to a and s8. These machines do not need to be realised as
conventional state assignment program produces an FSMs. NOVA is not able to detect it and supplies an
encoding with three state variables. In particular a two assignment for them. This leads to realisations which are
level realisation with 13 product terms and three memory expensive in terms of area. None of the machines in
elements was obtained with the well known state assign- Table 3 is more efficiently assigned with NOVA than it is
ment tool NOVA [SI. with SMAS. On average the area savings with SMAS is
around 50% for group 1 and 57% for group 2. Also the
5 Experimental results time comparison is favourable for SMAS.
The algorithm is particularly suited to those machines for
which state merging applies and so a subset of the One of the NOVA's options. It achieves a very good trade-off between
MCNC machines (group 1) [19], those with compatibles quality of the solutions and CPU time. It uses codes with minimum
or equivalent states, has been used to test the algorithm. length
Many examples picked out from switching circuit text- t Each bit position which is '1' in the code of the state appearing more
times in the next state field is complemented in the d e s of all the
books and journal papers on minimisation have also states. This 'classic' heuristic is incorporated in many state assignments
been tried, all of them are in Reference 20 (group 2). Two tools and has been reported to lead to area savings. Clearly, this oper-
figures of merit are focused on: the area occupied by the ation cannot change a valid assignment into an invalid one

IEE Pr0c.-Comput. Digit. Tech., Vol. 141, No.4, July 1994 235
 Table 2: Experimental results for group 1 machines
NOVA i-hybrid ARNES + NOVA i-hybrid SMAS A, A2
ni no nv tp size time nv tp size time nv tp size time
bbara 4 2 4 25 550 1.9 3 20 380 1.5 3 21 399 0.8 0.72 1.05
bbsse 7 7 4 30 990 3.0 4 31 1023 5.2 4 28 924 5.2 0.93 0.90
beecount 3 4 3 13 247 1.1 2 9 144 1.0 3 10 190 0.3 0.77 1.32
donfile 2 1 5 35 700 394 0 0 0 0.1 0 0 0 0.1 0.00 1.00
ex1 9 19 5 48 2496 38.6 5 41 2132 34.7 5 53 2756 32.1 1.10 1.29
ex2 2 2 5 29 609 3.4 3 12 180 3.4 3 12 180 1.7 0.30 1.oo
ex3 2 2 4 18 324 1.4 3 10 150 1.6 3 8 120 0.4 0.37 0.80
ex5 2 2 4 14 252 3.7 2 6 72 1.1 2 7 84 0.2 0.33 1.16
ex7 2 2 4 17 306 2.3 2 9 108 1.3 2 8 96 0.3 0.31 0.88
lion9 2 1 4 8 136 1.9 2 7 77 0.9 3 9 126 0.3 0.93 1.63
mark1 5 16 4 21 798 23.4 4 17 646 5.5 4 21 798 3.7 1.00 1.23
modulo12 1 1 4 13 195 0.9 0 0 0 0.1 0 0 0 0.1 0.00 1.00
opus 5 6 4 16 448 1.9 4 16 448 1.6 4 15 420 0.9 0.94 0.94
sla 8 6 5 76 281 2 5.0 0 0 0 12.7 0 0 0 12.7 0.00 1.00
S8 4 1 3 10 180 1.1 0 0 0 0.1 0 0 0 0.1 0.00 1.OO
tbk 6 3 5 154 4620 979 4 53 1431 146.6 4 55 1485 48.2 0.32 1.03
train11 2 1 4 9 153 3.3 2 6 66 1.1 2 6 66 0.3 0.43 1.oo
ni no. of input variables
no no. of outputs
tp no. of product terms
time in seconds on a workstation SUN 41330
size (2ni+3nv+no) x t p

Table 3: Experimental results for group 2 machines

NOVA;-hybrid ARNES + NOVA i-hybrid SMAS A, A2

ni no nv tp size time nv tp size time nv tp size time
FSMl 2 1 3 8 112 1.1 2 5 55 0.8 2 4 44 0.1 0.39 0.80
FSM2 2 1 4 12 204 1.6 2 8 88 1.1 3 11 154 0.3 0.75 1.75
FSM3 2 1 3 11 154 1.2 2 5 5 0.7 2 5 55 0.2 0.36 1.00
FSM4 2 1 3 8 112 1.0 2 4 44 0.9 2 4 44 0.1 0.39 1.00
FSM5 2 1 3 9 126 1.3 2 5 55 0.9 2 6 66 0.1 0.52 1.20
FSM6 2 1 5 31 620 164 4 15 255 2.6 4 15 255 3.6 0.41 1.OO
FSM7 2 1 4 15 255 6.9 2 8 88 0.8 2 7 77 0.2 0.30 0.87
FSM8 2 1 3 9 126 1.4 2 7 77 0.9 2 7 77 0.1 0.61 1.oo
FSM9 3 1 4 15 255 6.1 2 7 91 0.9 2 7 91 0.4 0.36 1.oo
FSM10 3 1 3 18 288 4.0 3 13 208 1.5 2 8 104 0.3 0.36 0.50
FSM11 2 1 3 10 140 1.3 2 7 77 0.9 3 6 84 0.2 0.60 1.09
FSMl2 2 1 4 13 221 3.5 2 8 88 0.9 2 7 77 0.3 0.35 0.87
FSMl3 3 1 3 13 208 1.4 2 8 104 0.9 2 8 104 0.1 0.50 1.OO
FSM14 2 1 3 7 98 0.9 1 3 24 0.8 1 3 24 0.1 0.24 1.00
FSMl5 3 1 4 11 209 5.4 2 4 52 1.0 2 4 52 0.4 0.25 1.00
ni no. of input variables
no no. of outputs
tp no. of product terms
time in seconds on a workstation SUN 4/330
size (2ni + 3nv +no) x tp
Next we compare SMAS with the synthesis procedure binary codes have been stated so that the initial symbolic
including state reduction with ARNES and optimal state machine and the encoded one have the same functional-
assignment with NOVA. In six out of the 17 machines in ity. The algorithm is original and paves the way for a
Table 2, the same area results were obtained with both new treatment of state assignment.
approaches. In seven machines worse results were Experimental results have been shown. The algorithm
obtained with SMAS and better in four cases. For is extremely advantageous (reductions of around 50%)
machines from Table 3, the area results were identical in for the assignment of non-minimised FSMs because of
eight cases, in three SMAS achieved more expensive the power of state merging. It achieves slightly worse
implementations and in the remaining four SMAS results than NOVA for previously minimised machines.
obtained cheaper realisations. The CPU time invested by Paying more attention to the cost function will lead to
SMAS is smaller for both groups of machines, with the more efficient assignment of FSMs with a minimum
exception of FSM6. number of states. More exact criteria such as input and
and output constraint satisfaction [23, 241 for two level
6 Conclusions implementations are being incorporated into the cost
function instead of counting state adjacencies. Finally,
We have presented a state assignment algorithm which, future work includes a BDD-based [25] version of the
concurrently with the assignment of binary codes in the algorithm.
symbolic representation, exploits the potentials of state
merging and state splitting. The algorithm heuristically
minimises the area of the combinational component after 7 References
logic reduction. The conventional constraint of giving 1 HOPCROFT, J.: ‘An n log n algorithm for minimizing states in a
each state a unique distinct code have been removed and finite automaton’, in KOHAVI, (Ed.): ‘Theory of machines and
conditions under which two states can share one or more computation’(Academic Press, 1971), pp. 189-196

236 I E E Proc.-Comput. Digit. Tech., Vol. 141, No. 4, July 1994

 2 PFLEEGER, C.P.: ‘State reduction m incompletely specified finite- switching theory’, in ‘Networks and switching theory’ (Academic
state machines’, IEEE Trans. Cornput., 1973, C-22, (12), pp. 1099- Press, 1968)
1102 15 TSENG, C., PRABHU, A.M., LI, C., MEHMOOD, Z., and TONG,
3 HACHTEL, G.D., RHO, J.-K., SOMENZI, F., and JACOBY, R.: M.M.: ‘A versatile finite state machine synthesis system’. Pro-
‘Exact and heuristic algorithms for the minimization of incompletely d i n g s of the 1986 International Symposium on Circuits and
specified state machines’. Proceedings of the European Design Systems, 1986, pp. 206-209
Automation Conference, 1991, pp. 184-191 16 HUMPHREY, W.S.: ‘Switching circuits with computer applica-
4 KANNAN, L.N., and SARMA, D.: ‘Fast heuristic algorithms for tions’ (McGraw-Hill Book Company, New York, 1957). Section
linite state machine minimization’. Proceedings of the European 10.5, pp. 233-252
Design Automation Conference, 1991, pp. 192-196 17 ARMSTRONG, D.B.: ‘A programmed algorithm for assigning
5 AVEDILLO, MJ., QUINTANA, J.M., and HUERTAS, J.L.: ‘E&- internal d e s to sequential machines’, IRE Trans. Electro. Cornput.,
dent state reduction methods for PLA-based sequential circuits’, 1962, EC-11, pp. 46-472
IEE Proc. E, 1992,139, (6) 18 DE SARKAR, S.C., BASUY, A.K., and CHOUDHURY, A.K.: ‘On
6 VILLA, T.: ‘NOVA: state assignment of linite state machines for the determination of irredundant prime closed sets’, IEEE Trans.
optimal two-level logic implementation’, IEEE Trans. Cornput- Cornput., 1971, C-20, pp. 933-938
Aided Des. Integr. Circuits Syst., 19w,9, (9), pp. 90-924 19 LISANKE, R.: ‘Introduction of synthesis benchmarks’. Inter-
7 LEE, E.B., and PERKOWSKI, M.A.: ‘Concurrent minimization national Workshop on h g i c Synthesis,North Carolina, 1989
and state assignment of h i t e state machines’. Proaedmgs of the 20 REUSCH, B., and MERZENICH, W.: ‘Minimal coverings for
1984 International Conference on Syst., Man. and Cyb., IEEE, incompletely specified’sequentialmachines’, Acta Inform., 1986, 22,
Halifax, October 1984 pp. 663-678
8 ASHAR, P., DEVADAS, S, and NEWTON, A.R.: ‘Sequential logic 21 VILLA, T.: ‘NOVA, User’s Manual‘. University of California,
synthesis’ (Kluwer Academic Publishers, 1992) Berkeley, October 1988
9 RUDELL, R., SANGIOVANNI-VICENTELLI, A.L., and DE 22 BRAYTON, R.K., HACHTEL, G.D., McMULLEN, C., and
MICHELI, G.: ‘A h i t e state machine synthesis system’. Pro- SANGIOVANNI-VINCENTELLI, A.L.: ‘Logic minimization algo-
ceedings of International Symp. on Circuits and Systems, May 1985, rithms for VLSI synthesis’ (Kluwcr Academic Publishers, Boston,
pp. 617-650 Massachusetts, 196%)
10 HARTMANIS, J., and STEARNS, R.E.: ‘Some dangers in the state 23 DE MICHELI, G., BRAYTON, R.K., and SANGIOVANNI-
reduction of sequential machines’, I& Control, 1962,!5, pp. 252-260 VINCENTELLI. A.L.: ‘KISS:a oromam for ootimal state assign-
11 DEVADAS, S., MA, H.-K.T, NEWTON, A.R., and ment of finite-’ state machine2 Proceedingi of Internatioial
SANGIOVANNI-VINCENTELLI, A. : ‘Irredundant sequential Conferena on Computer Aided Design, Novemher 1984, pp. 209-
machines via optimal logic synthesis’, IEEE Trans.CompubAided 211
Des. Integr. CirnUts Syst., 1990,9, (l), pp. 8-17 24 DE MICHELI, G.: ‘Symbolic design of combinational and sequen-
12 UNGER, S.H.: ‘Asynchronous sequential switching circuits’ (Wiley- tial logic circuits implemented by two-level macros’, IEEE Trans.
Interscience, New York, 1969) Cornput.-Aided Des. Integr. Circuits Syst., 1986, CAD-5,pp. 597-616
13 KOHAVI, 2.: ‘Switching and h i t e automata theory’ (McGraw-Hill 25 BRYANT, R.E.: ‘Graph based algorithms for Boolean function
Book Company, New York, 1978). 2nd edn. manipulation’, IEEE Trans. Cornput., 1986, CJS, (8), pp. 677-691
14 GRASSELLI, A., and LUCCIO, F.: ‘Some covering problems in

IEE Proc-Cornput. Digit. Tech., Vol. 141, No. 4, July 1994 237