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Robust and energy-efficient carbon nanotube FET-based MVL gates:

A novel design approach
Fazel Sharifi a, Mohammad Hossein Moaiyeri a, Keivan Navi a,n, Nader Bagherzadeh b
a
Faculty of Electrical and Computer Engineering, Shahid Beheshti University, G.C., Tehran, Iran
b
Department of Electrical Engineering and Computer Science, University of California, Irvine, United States

art ic l e i nf o a b s t r a c t

Article history: In this paper energy-efficient multiple valued logic (MVL) circuits based on carbon nanotube field effect
Received 24 November 2014 transistor (CNTFET) are proposed. These circuits are designed based on the unique properties of CNTFETs,
Received in revised form such as having same mobility for electrons and holes and also capability of adopting desirable threshold
31 July 2015
voltage by adjusting the CNTs diameters. The proposed designs have high driving capability, larger noise
Accepted 29 September 2015
margins and higher robustness as compared to the previous CNTFET-based designs. The proposed qua-
ternary circuits are examined using HSPICE simulator with the standard CNTFET technology. Simulation
Keywords: results demonstrate more energy-efficient and robust operation of the proposed designs, as compared to
Nanoelectronics the other state-of-the-art CNTFET-based MVL circuits, recently presented in the literature. According to the
Multiple valued logic (MVL)
simulation results the proposed STNOT, STNAND and STNOR circuits have on average 82%, 76% and 45%
CNTFET
lower power-delay product (PDP), respectively as compared to their state-of-the-art counterparts. In
Low-power design
addition, the proposed QNOT, QNAND and QNOR circuits have the average PDP improvements of 79%, 42%
and 61%, respectively, as compared the other recently presented CNTFET-based quaternary designs.
& 2015 Elsevier Ltd. All rights reserved.

1. Introduction Carbon nanotube field effect transistor (CNTFET) is a promising

alternative to silicon transistor for achieving low power and high
Digital computation is generally performed on two-valued performance. CNTFET avoids most problems of nanoscale MOSFET
(binary) logic. Powerful computational elements and tools have technology, such as very high leakage power dissipation, reduced
already supported binary logic to reach its present status. gate control and velocity saturation [5,6]. The other advantage of
Multiple-valued logic (MVL) is an alternative logic which uses CNTFET is that the threshold voltage of a CNTFET is determined
more than two logical values.
dominantly based on the diameter of its CNT channels. Hence,
MVL circuits have attracted the attention of researchers, due to
multiple-threshold circuits can be achieved by utilizing CNTFETs
some of their important features related to reduction of the
with different diameters. This property is very useful in designing
number of interconnections and increased information content
voltage-mode MVL circuits [7,8].
per unit area. In other word, MVL allows more information to be
Some MOSFET and CNTFET-based MVL circuits, specifically for
transmitted over a given set of lines or to be stored on a given
register length, thus reducing the complexity of interconnects and ternary and quaternary logics, have been presented so far in the
chip area and achieving simplicity and energy efficiency in digital literature [9–19]. However, they have some critical drawbacks
design [1–4]. Among MVL systems, using e base (eE 2.718) leads such as using very large ohmic resistors [9,10], requiring obsolete
to the most efficient implementation of the switching systems [1]. depletion-mode MOSFET [11–16], high static power consumption
However, due to the restrictions on hardware implementation, [17–19] non-full swing nodes [9,10] and limited fan-out [19].
designers are limited to use natural numbers as the radices for In this study, energy-efficient quaternary gates tolerant to
computations. On the other hand, power-of-two radices take process, voltage and temperature variations are proposed for
advantage of simple conversion between MVL signals and binary nanoelectronics, which are designed based on the complementary
signals, generated by the existing binary circuits. Therefore CNTFET style.
researchers focus on radices 3 and 4 for hardware implementation. The rest of the paper is organized as follows: Section 2 briefly
reviews the CNTFET device. The proposed designs are described in
n
Corresponding author. Section 3. In Section 4, the simulation results, analyses and com-
E-mail address: [email protected] (K. Navi). parisons are presented and finally Section 5 concludes this paper.

http://dx.doi.org/10.1016/j.mejo.2015.09.018
0026-2692/& 2015 Elsevier Ltd. All rights reserved.

Please cite this article as: F. Sharifi, et al., Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach,
Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.09.018i
2 F. Sharifi et al. / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎

Table 1
The truth table of standard ternary NOT, NAND and NOR.

a b STNOT (a) STNAND (a,b) STNOR (a,b)

0 0 2 2 2
0 1 2 2 1
0 2 2 2 0
1 0 1 2 1
1 1 1 1 1
1 2 1 1 0
2 0 0 2 0
2 1 0 1 0
2 2 0 0 0

and p þ for pCNTFET. MOSFET-like CNTFET has very high ION/IOFF

ratio which makes it suitable for high-performance and energy-
Fig. 1. Schematic of CNTFET. efficient applications [21]. In this paper MOSFET-like CNTFETs are
used for designing and simulating the circuits.
2. Carbon nanotube field effect transistor (CNTFET)

Carbon nanotube (CNT) is a sheet of graphene rolled up along a 3. Proposed designs

wrapping vector, which can be single-wall (SWCNT) or multi-wall
(MWCNT). Single-wall CNT is a single nanotube and multi-wall CNT 3.1. Ternary circuits
is made of two or more coaxial nanotubes. Rolling up the graphene
sheet into a tube is assumed based on a vector called the chiral vector In this section new ternary circuits based on CNTFETs are
(n1, n2). Based on (n1, n2), if n1
n2 ¼3k (kA Z), then SWCNT becomes presented. The truth table of ternary functions is shown in Table 1.
conductor and otherwise it becomes semiconductor. Conductive Ternary logic includes three significant logic levels which can
CNTs are used as on-chip interconnects and semiconducting CNTs are be considered as “0”, “1” and “2” symbols; these symbols are
used as the channel of transistors [7]. The schematic of a typical counterpart to 0, ½VDD and VDD voltage levels respectively.
CNTFET device is illustrated in Fig. 1. The gate width of a CNTFET The proposed ternary inverter circuit is shown in Fig. 2. Based
(Wgate) is approximately calculated based on the following equation: on Eqs. (1) and (2), for the CNTFETs of this design with the dia-
meters of 0.626, 0.783 and 1.487 nm, the chiral numbers would be
W gate  MaxðW min ; N  PitchÞ ð1Þ
(8,0), (10,0) and (19,0) and the threshold voltage values (|Vth|)
where Pitch is the distance between the centers of two neigh- would be 0.686 V, 0.559 V and 0.293 V, respectively.
boring SWCNTs under the same gate, Wmin is the minimum gate First consider the input voltage is near 0. For this value the
width, determined by lithography and N is the number of nano- output of inverter1 and inverter2 is VDD, so T3 is OFF and T1 is ON
tubes under the gate. and consequently the output voltage will be VDD. When the input
The threshold voltage of a CNTFET is an inverse function of the voltage is ½VDD, the output of first and second inverters is 0 and
diameter of its CNTs. This capability is utilized to adopt the desired VDD respectively; therefore T3 and T4 are ON and the output vol-
threshold voltage (Vth) by choosing the correct DCNT. The CNTFET tage is ½VDD. Finally when the input voltage is VDD, output of both
threshold voltage is calculated based on Eq. (3). inverters is 0 and T4 is OFF, so T2 is ON and output voltage is 0.
pffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Based on the STNOT design methodology, STNAND and STNOR
3a0 n1 2 þn1 n2 þ n2 2 pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
DCNT ¼  0:0783 n1 2 þ n1 n2 þ n2 2 ð2Þ circuits are proposed which are shown in Figs. 3 and 4 respectively.
π Transient simulation results of the proposed STNOT, STNAND and
Ebg a0 V π 0:43 STNOR are plotted in Fig. 5. These results, which are obtained by
V th  ¼  ð3Þ HSPICE simulations, show the correct operation of the proposed
2e eDCNT DCNT ðnmÞ
ternary circuits.
where e is the unit electron charge, Ebg is the CNT bandgap, a0
(  0.142 nm) is the carbon to carbon bond length in a CNT and Vπ 3.2. Quaternary circuits
(  3.033 eV) is the carbon π–π bond energy in the tight bonding
model [20]. In this section, new quaternary logic gates including a qua-
Based on the type of connections between source/drain regions ternary inverter (QNOT), a quaternary NAND (QNAND) and a
and CNT channels and the type of source/drain regions there are quaternary NOR (QNOR) are proposed. Quaternary logic consists of
three main categories of CNTFETs. The first type is Schottky Barrier four significant logic levels which can be represented by “0”, “1”,
CNTFET (SB-CNTFET) which has metallic source/drain regions. In “2” and “3” symbols. These logic levels are commonly counterpart
this type of CNTFET, the Schottky barrier junctions limit the to 0 V, ⅓VDD, ⅔VDD and VDD voltage levels, respectively.
transconductance in the ON state and increase the reverse cur- The functionalities of the quaternary gates can be described by
rents in the OFF state; thus ION/IOFF ratio becomes rather low. SB- Eqs. (4)–(6).
CNTFET is appropriate for medium to high-performance applica-
QNOTðaÞ ¼ 3
a ð4Þ
tions. The second type of CNTFET is the band-to-band tunneling
CNTFET (T-CNTFET) with CNT source and drain regions with 
3
a if arb
opposite doping types. T-CNTFET has super cut-off characteristics QNANDða; bÞ ¼ Minða; bÞ ¼ ð5Þ
3
b otherwise
and also has low ON current. T-CNTFET is suitable for low stand-by
power application but it is not appropriate for high-performance 
3
a if a Zb
applications. The third type of CNTFETs is the MOSFET-like CNTFET, QNORða; bÞ ¼ Maxða; bÞ ¼ ð6Þ
3
b otherwise
in which source and drain CNT regions are doped n þ for nCNTFET

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 F. Sharifi et al. / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎ 3

VDD VDD

T1

D=0.626nm B D=0.626
nm
IN
T3 Dn=1.487nm
D=0.626nm STNOT 1 A D=0.626
nm
T2 Dn=0.783nm
Dp=0.783nm IN
STNOR A
2 A D=0.626 Dp=1.487nm
T4 B
Dn=0.783nm nm
1/2 VDD B

Fig. 2. The proposed ternary inverter. Dn=0.783nm

Dp=0.783nm Dp=0.783nm

VDD B A

Dn=1.487nm Dn=1.487nm

A D=0.626 B 1/2 VDD

nm Fig. 4. The proposed ternary NOR.

Dn=1.487nm
Operation of the proposed quaternary NAND can be summar-
A D=0.626
STNAND A ized as follows: While both inputs are around VDD, T3 and T4 are
nm
ON, so the output will be 0. While one of the inputs is around
Dp=0.783nm
⅔VDD and the other one is equal or greater than ⅔VDD, T9, T10 and
B D=0.626 B at least one of the T11 and T12 are ON based on the threshold
nm voltage of the inverters connected to the transistors gate, therefore
Dn=1.487nm the output is ⅓VDD. If one of the inputs is around ⅓VDD and the
other one is equal or greater than ⅓VDD, T7, T8 and at least one of
Dp=1.487nm Dp=1.487nm the T5 and T6 are ON, so the output will be ⅔VDD. Moreover while
B one or both of the inputs is around 0, T1 or T2 are ON and other
A
paths to the output are disconnected (T7 or T8, T9 or T10 are OFF),
Dn=0.783nm Dn=0.783nm consequently output is VDD. The operation of the proposed QNOR
is similar to QNAND circuit.
It is worth mentioning that only two distinct diameters are
1/2 VDD utilized for the CNTFETs of the proposed quaternary designs,
Fig. 3. The proposed ternary NAND. whereas the previous CNTFET-based quaternary gates have used at
least three distinct diameters. This alleviates sensitivity to process
variations and enhances manufacturability.
The proposed quaternary inverter, which can be considered as In addition, the proposed quaternary 2-input NAND and NOR
the cornerstone of the other proposed quaternary gates, is shown gates can also be extended to quaternary NAND and NOR circuits
in Fig. 6. with more than two inputs by extending the proposed com-
The operation of the proposed quaternary inverter gate can be plementary CNTFET-based structures of Figs. 7 and 8. The transient
briefly described as follows: when the input voltage is around 0 V, responses of the proposed QNOT, QNAND and QNOR are shown in
T1 is ON and T2–T5 are OFF. So the output voltage will be VDD. Fig. 9, which authenticate the correct operation of the proposed
When the input voltage is around ⅓VDD, T1, T2 and T5 are OFF and circuits.
T3 and T4 are ON and consequently the output voltage will be
⅔VDD. When the input voltage is around ⅔VDD, T1, T2 and T3 are
OFF and T5 and T6 are ON. Consequently the output voltage will 4. Simulation results and comparisons
become ⅓VDD. Finally, if the input value becomes VDD, T1, T3 and
T6 become OFF and T2 becomes ON and consequently the output In this section, the proposed designs are comprehensively
is discharged to 0. examined and compared with the other state-of-the-art CNTFET-
Based on the proposed method for designing the QNOT circuit, based designs. The circuits are simulated using Synopsys HSPICE
a new quaternary NAND and a new quaternary NOR are also with the commonly used compact SPICE model for unipolar
introduced. The operation principles of these two circuits are MOSFET-like CNTFETs including all the non-idealities and para-
similar to the proposed quaternary inverter. The schematic of the sitics [22–24] at 32 nm technology. Simulations are conducted at
proposed QNAND and QNOR circuits is shown in Figs. 7 and 8, different power supplies and also at different temperatures to
respectively. consider the voltage and temperature variations.

Please cite this article as: F. Sharifi, et al., Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach,
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4 F. Sharifi et al. / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎

Fig. 5. Transient response of the proposed STNOT, STNOR and STNAND.

2/3 VDD 2/ 3 VDD

T3 T5 T6
VDD D=2.27nm
B D=2.27 A
D=0.626nm nm
T1 T4
VDD
D=0.626nm D=2.27nm T7 Dn=2.27nm

Dn=2.27nm D=2.27nm B
IN
IN T1 T2
T2 T5
D=0.626nm QNOT D=2.27nm T8 Dp=0.626nm
A D=0.626 B
Dp=2.27nm nm D=2.27nm A
T6
D=2.27nm T3 Dn=2.27nm
T9
D=0.626nm
A D=0.626nm D=2.27nm A
QNAND
1/3 VDD
T4 T10
Fig. 6. The proposed quaternary inverter.
B D=0.626nm D=2.27nm B

Dp=2.27nm T11 T12 Dp=2.27nm

The results of the simulations at 32 nm technology node and
0.9 V supply voltage including the worst-case delay, the average B D=2.27 A
nm
power consumption and the power-delay product (PDP) of the
Dn=0.626nm Dn=0.626nm
cascaded ternary and quaternary designs are presented in
Tables 2 and 3, respectively. According to the simulation results,
the proposed designs consume lower power and have lower PDP 1/ 3 VDD
compared to the state-of-the-art CNTFET-based designs. Fig. 7. The proposed quaternary NAND.
The CNTFET-based circuits also have been simulated at 22 nm
technology node and 0.8 V supply voltage. The results of this
simulation are given in Tables 4 and 5 for the ternary and qua- Figs. 10 and 11 compare the performance of the designs at
ternary designs, respectively. According to the simulation results, 32 nm technology and 0.9 V voltage considering different supply
the proposed designs consume lower power and are more energy- voltages and temperatures respectively. According to the results,
efficient as compared to the state-of-the-art CNTFET-based designs the proposed quaternary designs have lower PDP at all supply
even at 22 nm technology. voltages and temperatures compared to the other designs. The

Please cite this article as: F. Sharifi, et al., Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach,
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 F. Sharifi et al. / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎ 5

proposed STNOT has higher PDP than other designs at supply in CNTFET circuits [25]. In addition, diameter variation is a sig-
voltage of 0.8 V. Since the results of ternary designs with pseudo- nificant issue in multi-diameter CNTFET circuits [17,26]. As a
n-type CNTFETs [18] are very higher than the other designs we result, the Monte Carlo simulation has been conducted to evaluate
eliminate them in upcoming figures. these process variations with up to 715% Gaussian distributions
The operation and performance of the ternary and quaternary and variation at the 73σ level.
gates are also examined in the presence of process variations. Figs. 12 and 13 demonstrate the maximum PDP variation of the
Nanotube density variations, mainly resulted from variations in designs in the presence of CNT density and diameter variations,
the spacing between CNTs on the substrate (Pitch) and variations
respectively. According to the results, the pseudo-n-type QNOT
in the surviving CNT count after metallic CNT removal techniques,
[18] does not work when the diameter deviation reaches 15%. In
are proven experimentally to be the dominant source of variation

2/3 VDD
Table 2
Simulation results of the two cascaded ternary circuits (@ 32 nm and 0.9 V).

Dp=0.783nm Dp=0.626nm Cascaded ternary designs Delay (e-12 s) Power (e-6 W) PDP (e-18 J)

VDD D=2.27 Proposed STNOT 26.1 0.06 1.71

B A
nm STNOT [2] 23.3 0.19 4.49
STNOT [7] 15.1 0.29 4.39
Dn=2.27nm Dn=2.27nm STNOT [18] 16.2 1.51 24.7
Proposed STNAND 12.2 0.04 0.56
B D=0.626nm D=2.27nm B STNAND [2] 23.3 0.19 4.49
STNAND [7] 9.20 0.23 2.20
STNAND [18] 29.3 1.71 51.8
Proposed STNOR 41.8 0.04 2.01
A D=0.626nm STNOR [2] 18.2 0.22 4.01
D=2.27nm A STNOR [7] 28.5 0.35 10.1
STNOR [18] 23.1 3.51 82.1
Dn=0.626nm

QNOR D=2.27nm A

A D=0.626 B Dp=2.27nm Table 3

nm Simulation results of the two cascaded quaternary circuits (@ 32 nm and 0.9 V).
D=2.27nm B
Cascaded quaternary designs Delay (e-10 s) Power (e-6 W) PDP (e-16 J)
Dn=0.626nm
Proposed QNOT 1.43 1.24 1.78
D=2.27 QBuffer [17] 5.14 3.36 17.2
B A QNOT [18] 0.28 62.1 17.8
nm
Proposed QNAND 2.73 4.95 13.5
QAND [17] 5.41 3.02 16.4
QNANAD [18] 0.36 54.8 19.7
Proposed QNOR 2.74 6.79 18.6
1/3 VDD QOR [17] 5.23 3.88 20.3
QNOR [18] 0.36 54.8 19.7
Fig. 8. The proposed quaternary NOR.

Fig. 9. Transient respond of the proposed QNOT, QNOR and QNAND.

Please cite this article as: F. Sharifi, et al., Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach,
Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.09.018i
6 F. Sharifi et al. / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎

addition, the proposed designs work correctly with small para- voltage generators. Moreover, the additional power supplies will
metric variations in the presence of process variations. not have ideal voltages and deviate from the ideal voltage levels
It is worth pointing out that utilizing multiple supply voltages provisional or permanently, which can affect the performance and
leads to some system-level costs related to power grids and robustness of the circuits. In order to examine the effect of supply

Table 4
Simulation results of the two cascaded ternary circuits (@ 22 nm and 0.8 V).

Cascaded ternary designs Delay (e-12 s) Power (e-6 W) PDP (e-18 J)

Proposed STNOT 38.82 0.022 0.875

STNOT [2] 21.54 0.038 0.822
STNOT [7] 19.97 0.066 1.335
STNOT [18] 31.31 0.557 17.44
Proposed STNAND 10.51 0.016 0.178
STNAND [2] 42.63 0.051 2.211
STNAND [7] 9.8734 0.056 0.559
STNAND [18] 53.429 0.538 0.287
Proposed STNOR 69.38 0.016 1.128
STNOR [2] 25.31 0.065 1.670
STNOR [7] 14.46 0.082 1.186
STNOR [18] 38.04 1.080 41.08

Table 5
Simulation results of the two cascaded quaternary circuits (@ 22 nm and 0.8 V).

Cascaded quaternary designs Delay (e-10 s) Power (e-6 W) PDP (e-16 J)

Proposed QNOT 3.410 0.752 2.566

QBuffer [17] 0.380 50.36 19.14
QNOT [18] 12.84 1.052 13.51
Proposed QNAND 9.480 1.806 17.12
QAND [17] 0.490 44.37 21.74
QNAND [18] 13.24 0.957 12.68
Proposed QNOR 5.474 2.760 15.11
QOR [17] 12.98 1.182 15.35
QNOR [18] 0.491 44.45 21.86

1.6 3
3
proposed STNOT Proposed STNAND Proposed STNOR
1.4 2.5
STNOT[2] 2.5 STNAND[2] STNOR[2]
1.2 STNAND[19] STNOR[19]
STNOT[19]
2
PDP (e-18J)

2
PDP (e-18J)

PDP (e-18J)

1
0.8 1.5 1.5
0.6
1 1
0.4
0.5 0.5
0.2
0 0 0
0.8 0.9 1 0.8 0.9 1 0.8 0.9 1
Supply Voltage (V) Supply Voltage (V) Supply Voltage (V)

16 16 16
Proposed QNOT Proposed QNAND Proposed QNOR
14 14 14 QOR[17]
QBuffer[17] QAND[17]
12 12 QNAND[18] 12 QNOR[18]
QNOT[18]
PDP (e-16 J)
PDP (e-16 J)

PDP (e-16 J)

10 10 10

8 8 8
6 6 6
4 4 4
2 2 2
0 0 0
0.8 0.9 1 0.8 0.9 1 0.8 0.9 1
Supply Voltage (V) Supply Voltage (V) Supply Voltage (V)
Fig. 10. PDP of the ternary and quaternary gates vs. supply voltage variation.

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1.2
Proposed STNOT 1.4 Proposed STNOR
1.6 Proposed STNAND
1 STNOR[19]
STNOT[19] 1.4 STNAND[19] 1.2 STNOR[2]
STNOT[2] STNAND[2]
0.8 1.2 1

PDP (e-18J)

PDP (e-18J)
PDP (e-18J)

1 0.8
0.6
0.8
0.6
0.4 0.6
0.4
0.4
0.2 0.2
0.2
0 0 0
0 10 20 30 40 50 60 70 80 0 10 20 30 40 50 60 70 80 0 10 20 30 40 50 60 70 80
Temprature (oC) Temprature (oC) Temprature (oC)

20 20 16
18 Proposed QNOT 18 Proposed QNAND 15 Proposed QNOR
QBuffer[17] QAND[17] QOR[17]
16 16 14
QNOT[18] QNAND[18] QNOR[18]
14 14 13
PDP (e-16J)

PDP (e-16J)
PDP (e-16J)

12 12 12
10 10 11
8 8 10
6 6 9
4 4 8
2 2 7
0 0 6
0 10 20 30 40 50 60 70 80 0 10 20 30 40 50 60 70 80 0 10 20 30 40 50 60 70 80
Temprature (oC) Temprature (oC) Temprature (oC)
Fig. 11. PDP of the ternary and quaternary gates vs. temperature variation.

0.18 0.7 0.9

Proposed STNAND
Maximum PDP variation (e-18j)

Proposed STNOT
Maximum PDP variation (e-18J)
Maximum PDP variation (-18J)

0.16 Proposed STNOR

0.6 0.8
STNOT[2] STNAND[2] STNOR[2]
0.14 0.7
STNOT[19] 0.5 STNAND[19] STNOR[19]
0.12 0.6
0.1 0.4 0.5
0.08 0.3 0.4
0.06 0.3
0.2
0.04 0.2
0.02 0.1 0.1
0 0 0
5 10 15 5 10 15 5 10 15
Density variation (%) Density variation (%) Density variation (%)

8 4
Maximum PDP Variation (e -17J)
Maximum PDP Variation (e -17J)

Proposed QNAND
Maximum PDP Variation (e -17J)

Proposed QNOT 10 Proposed QNOR

7 QBuffer[17] 3.5 QAND[17] QOR[17]
6 QNOT[18] 3 QNAND[18] QNOR[18]
8
5 2.5
6
4 2
3 1.5 4
2 1
2
1 0.5
0 0 0
5 10 15 5 10 15 5 10 15
Density Variation (%) Density Variation (%) Density Variation (%)
Fig. 12. Parameter variations of the designs with respect to CNT density variations.

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1.8 4 8
Proposed STNOR
Maximum PDP Variation (e-18J)
Proposed STNOT Proposed STNAND

Maximum PDP Variation (e-18J)

Maximum PDP Variation (e-18J)
1.6 3.5 7 STNOR[2]
STNOT[2] STNAND[2]
1.4 STNOT[19] STNAND[19] 6 STNOR[19]
3
1.2
2.5 5
1
2 4
0.8
1.5 3
0.6
0.4 1 2

0.2 0.5 1
0 0 0
5 10 15 5 10 15 5 10 15
Diameter Variation (%) Diameter Variation (%) Diameter Variation (%)

5 16 8
Maximum PDP Variation (e -17J)
Maximum PDP Variation (e -17J)

Maximum PDP Variation (e -17J)

4.5 Proposed QNOT Proposed QNAND Proposed QNOR
14 7
QBuffer[17] QAND[17] QOR[17]
4
QNOT[18] 12 QNAND[18] 6 QNOR[18]
3.5
3 10 5
2.5 8 4
2 6 3
1.5
4 2
1
0.5 2 1
0 0 0
5 10 15 5 10 15 5 10 15
Diameter Variation (%) Diameter Variation (%) Diameter Variation (%)
Fig. 13. Parameter variations of the designs with respect to CNT diameter variations.

100 7
Proposed Design Proposed Design
90 Design [2] 6 Design [17]
80 Design [19] Design [18]
Maximum PDP (e-15)
Maximum PDP (e-18 J)

70 Design [18] 5

60 4
50
3
40
30 2
20
1
10
0 0
STNOT STNAND STNOR QNOT/Buff QNAND/AND QNOR/OR
Standard Ternary Logic Circuits Quaternary Logic Circuits

Fig. 14. PDP variations of the designs with respect to supply voltages variations.

voltage variations on the energy efficiency of the circuits, the voltage as compared to the state-of-the-art pseudo-n-type designs
cascaded form of the MVL circuits is simulated in the presence of [18].
random supply voltage variations. For this purpose, the Monte Noise immunity curve (NIC) is used for evaluating and com-
Carlo simulation has been conducted using Gaussian distributions paring the noise tolerance of the proposed designs to the input
with 710% variation at the 7 3σ level. The results, shown in noise pulses. NIC is the locus of noise pulse amplitude (Vnoise) and
Fig. 14, indicate the lower energy consumption of the proposed noise puleswidth (Tnoise). A noise pulse with sufficient width and
circuits, except QNAND, even in the presence of random supply
amplitude may cause the circuit to have a logic error. The area
voltage variations.
below NIC indicates the safe region and above it indicates the
In addition, the results of the Monte Carlo DC analyses of the
unsafe region. It means that if the noise amplitude is higher at a
STNOT and QNOT circuits with Gaussian distribution considering
710% variations in process and supply voltages variations at the point on NIC for a particular width then the circuit will output an
73σ level are shown in Fig. 15. As demonstrated in Fig. 15, the error. Therefore, higher the NIC of a digital circuit, the more
voltage transfer characteristic (VTC) curves of the proposed STNOT immune the circuit to noise. Noise immunity curves were obtained
and QNOT circuits have very steep transition regions and are quite by simulation using a tunable noise injection circuit described in
less sensitive to the simultaneous variations of process and supply detail in previous works [27].

Please cite this article as: F. Sharifi, et al., Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach,
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 F. Sharifi et al. / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎ 9

Fig. 15. The results of the Monte Carlo DC analyses considering both process and voltage variations. (a) The proposed QNOT. (b) Pseudo-n-type QNOT [18]. (c) Proposed
QNOT. (d) Pseudo-n-type QNOT [18].

Table 6 Table 7
Noise margins of the ternary STNOTs (VDD ¼ 0.9 V). Noise Margins of the Quaternary NOTs (VDD ¼0.9 V).

Design NML NMH NML NMH Noise margin (mV) Design NML NMH NML NMH NML NMH Noise margin
021 021 122 122 021 021 122 122 223 223 (mV)
(mV) (mV) (mV) (mV) (mV) (mV) (mV) (mV) (mV) (mV)

Proposed STNOT 160 280 270 160 160 Proposed 210 80 110 100 210 80 80
STNOT [2] 150 300 290 150 150 QNOT
STNOT [18] 120 310 220 160 120 QNOT [17] 180 74 228 85 210 44 44
STNOT [7] 120 180 210 160 120 QNOT [18] 80 45 130 40 180 20 20

Moreover, noise margins of the ternary and quaternary circuits STNOT has better noise immunity compared to pseudo-n-type
for all logic level transitions have been measured and are shown in STNOT [18] and complementary CNTFET STNOT [7].
Tables 6 and 7, respectively. According to the results, the proposed
designs have larger noise margin as compared with the other
state-of-the art CNTFET-based MVL designs. 5. Conclusion
Fig. 16 shows the NIC curves of the ternary and quaternary
inverters. The proposed QNOT shows good noise immunity as In this study new energy-efficient and PVT tolerant multiple
compared to the other quaternary inverters, also the proposed valued logic (MVL) gates are proposed for nanoelectronics. The

Please cite this article as: F. Sharifi, et al., Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach,
Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.09.018i
10 F. Sharifi et al. / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎

350 300
Proposed STNOT Proposed QNOT
STONOT[2] QNOT[17]
STNOT[18] QNOT[18]

Noise Amplitude (mV)

325

Noise Amplitude (mV)

STNOT[19]
250

300

200
275

250 150
50 100 150 200 250 300 50 100 150 200 250 300
Noise width (ps) Noise width (ps)

Fig. 16. Noise immunity curves for the ternary and quaternary inverters.

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Please cite this article as: F. Sharifi, et al., Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach,
Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.09.018i