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LMV722-Q1
SLOS969A – JUNE 2017 – REVISED JANUARY 2018

LMV722-Q1 10-MHz Low-Noise, Low-Voltage Operational Amplifier

1 Features 3 Description
•
1 Qualified for Automotive Applications The LMV722-Q1 device is a low-noise, low-voltage
operational amplifier (op amp) that can be designed
• AEC-Q100 Qualified With the Following Results: into a wide range of applications. The LMV722-Q1
– Device Ambient Operating Temperature: has a unity-gain bandwidth of 10 MHz, slew rate of
–40°C to +125°C 5.25 V/µs, and good voltage and current noise
– Device HBM ESD Classification Level 2 performance.
– Device CDM ESD Classification Level C4B The LMV722-Q1 is designed to provide optimal
• Power-Supply Voltage Range: 2.2 V to 5.5 V performance in low-voltage and low-noise systems
such audio signal path or motor control applications.
• Low Supply Current: 905 µA/Amplifier at 2.2 V The device provides rail-to-rail output swing into
• High Unity-Gain Bandwidth: 10 MHz heavy loads. The input common-mode voltage range
• Rail-to-Rail Output Swing includes ground and the maximum input offset
voltage is 3.5 mV (over recommended temperature
– 600-Ω Load: 120 mV From Either Rail at 2.2 V
range) for the device. The capacitive load capability is
– 2-kΩ Load: 50 mV From Either Rail at 2.2 V also good at low supply voltages. The operating
• Input Common-Mode Voltage Range Includes range is from 2.2 V to 5.5 V.
Ground
Device Information(1)
• Input Voltage Noise: 10.5 nV/√Hz at f = 1 kHz
PART NUMBER PACKAGE BODY SIZE (NOM)

2 Applications LMV722-Q1 VSSOP 3.00 mm × 3.00 mm

• Infotainment (1) For all available packages, see the orderable addendum at
the end of the data sheet.
• Engine Control Unit
• Automotive Lighting
• Audio Signal Path
Simplified Schematic
IN− −
OUT
IN+ +

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 7.4 Device Functional Modes........................................ 12
2 Applications ........................................................... 1 8 Application and Implementation ........................ 13
3 Description ............................................................. 1 8.1 Application Information............................................ 13
4 Revision History..................................................... 2 8.2 Typical Application .................................................. 13
5 Pin Configuration and Functions ......................... 3 9 Power Supply Recommendations...................... 15
9.1 Input and ESD Protection ....................................... 15
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4 10 Layout................................................................... 16
6.2 ESD Ratings.............................................................. 4 10.1 Layout Guidelines ................................................. 16
6.3 Recommended Operating Conditions....................... 4 10.2 Layout Example .................................................... 17
6.4 Thermal Information .................................................. 4 11 Device and Documentation Support ................. 18
6.5 Electrical Characteristics VCC+ = 2.2 V ..................... 5 11.1 Documentation Support ........................................ 18
6.6 Electrical Characteristics VCC+ = 5 V ........................ 6 11.2 Receiving Notification of Documentation Updates 18
6.7 Typical Characteristics .............................................. 7 11.3 Community Resources.......................................... 18
7 Detailed Description ............................................ 12 11.4 Trademarks ........................................................... 18
7.1 Overview ................................................................. 12 11.5 Electrostatic Discharge Caution ............................ 18
7.2 Functional Block Diagram ....................................... 12 11.6 Glossary ................................................................ 18
7.3 Feature Description................................................. 12 12 Mechanical, Packaging, and Orderable
Information ........................................................... 18

4 Revision History
Changes from Original (June 2017) to Revision A Page

• Changed body size from 4.90 mm to 3.00 mm ...................................................................................................................... 1

• CDM value changed from 100 V to 1000 V............................................................................................................................ 4
• Updated Layout Example section ........................................................................................................................................ 17

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5 Pin Configuration and Functions

DGK Package
8-Pin VSSOP
Top View

1OUT 1 8 VCC+

1IN± 2 7 2OUT

1IN+ 3 6 2IN±

VCC± 4 5 2IN+

Not to scale

Pin Functions
PIN
I/O DESCRIPTION
NO. NAME
1 1OUT O Output of amplifier 1
2 1IN– I Inverting input of amplifier 1
3 1IN+ I Non-inverting input of amplifier 1
4 VCC– I Negative power supply
5 2IN+ I Non-inverting input of amplifier 2
6 2IN– I Inverting input of amplifier 2
7 2OUT O Output of amplifier 2
8 VCC+ I Positive power supply

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC+ – VCC– Supply voltage (2) 0 6 V
±Supply
VID Differential input voltage (3) V
voltage
TJ Operating virtual-junction temperature 150 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values (except differential voltages and VCC specified for the measurement of IOS) are with respect to the network GND.
(3) Differential voltages are at IN+ with respect to IN−.

6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per AEC Q100-002 (1) 2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per AEC Q100-011 1000

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC+ – VCC– Supply voltage 2.2 5.5 V
TJ Operating ambient temperature –40 125 °C

6.4 Thermal Information

LMV722-Q1
(1) DGK
THERMAL METRIC UNIT
(VSSOP)
8 PINS
RθJA Junction-to-ambient thermal resistance 176.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 69.5 °C/W
RθJB Junction-to-board thermal resistance 97.7 °C/W
ψJT Junction-to-top characterization parameter 12.7 °C/W
ψJB Junction-to-board characterization parameter 96.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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6.5 Electrical Characteristics VCC+ = 2.2 V

VCC+ = 2.2 V, VCC− = GND, VICR = VCC+/2, VO = VCC+/2, and RL > 1 MΩ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TJ = 25°C 0.02 3
VIO Input offset voltage mV
TJ = –40°C to +125°C 3.5
Input offset voltage average
TCVIO TJ = 25°C 0.6 μV/°C
drift
IIB Input bias current TJ = 25°C 260 nA
IIO Input offset current TJ = 25°C 25 nA
TJ = 25°C 70 88
CMMR Common-mode rejection ratio VICR = 0 V to 1.3 V dB
TJ = –40°C to +125°C 64
VCC+ = 2.2 V to 5 V TJ = 25°C 80 90
PSRR Power-supply rejection ratio dB
VO = 0, VICR = 0 TJ = –40°C to +125°C 70
CMRR ≥ 50 dB TJ = 25°C –0.3
VICR Input common-mode voltage V
TJ = 25°C 1.3
RL = 600 Ω, TJ = 25°C 75 81
VO = 0.75 V to 2 V TJ = –40°C to +125°C 70
AVD Large-signal voltage gain dB
RL = 2 kΩ, TJ = 25°C 75 84
VO = 0.5 V to 2.1 V TJ = –40°C to +125°C 70
TJ = 25°C 2.090 2.125
RL = 600 Ω to VCC+/2
TJ = –40°C to +125°C 2.065
TJ = 25°C 0.071 0.120
TJ = –40°C to +125°C 0.145
VO Output swing V
TJ = 25°C 2.150 2.177
RL = 2 kΩ to VCC+/2
TJ = –40°C to +125°C 2.125
TJ = 25°C 0.056 0.080
TJ = –40°C to +125°C 0.105
Sourcing, VO = 0 V TJ = 25°C 10 14.9
VIN(diff) = ±0.5 V TJ = –40°C to +125°C 5
IO Output current mA
Sinking, VO = 2.2 V TJ = 25°C 10 17.6
VIN(diff) = ±0.5 V TJ = –40°C to +125°C 5
TJ = 25°C 1.81 2.4
ICC Supply current mA
TJ = –40°C to +125°C 2.6
SR Slew rate (1) TJ = 25°C 4.9 V/μs
GBW Gain bandwidth product TJ = 25°C 10 MHz
Φm Phase margin TJ = 25°C 67.4 °
Gm Gain margin TJ = 25°C –9.8 dB
Vn Input-referred voltage noise f = 1 kHz TJ = 25°C 11 nV/√Hz
In Input-referred current noise f = 1 kHz TJ = 25°C 0.3 pA/√Hz
f = 1 kHz, AV = 1,
THD Total harmonic distortion TJ = 25°C 0.004%
RL = 600 Ω, VO = 500 mVpp

(1) Connected as voltage follower with 1-V step input. Number specified is the slower of the positive and negative slew rate.

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6.6 Electrical Characteristics VCC+ = 5 V

VCC+ = 5 V, VCC− = GND, VICR = VCC+/2, VO = VCC+/2, and RL > 1 MΩ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TJ = 25°C –0.08 3
VIO Input offset voltage mV
TJ = –40°C to +125°C 3.5
TCVIO Input offset voltage average drift TJ = 25°C 0.6 μV/°C
IIB Input bias current TJ = 25°C 260 nA
IIO Input offset current TJ = 25°C 25 nA
VICR = 0 V to 4.1 V TJ = 25°C 80 89
CMMR Common-mode rejection ratio dB
VICR = 0 V to 4.1 V TJ = –40°C to +125°C 75
VCC+ = 2.2 V to 5 V,
TJ = 25°C 70 90
VO = 0, VICR = 0
PSRR Power-supply rejection ratio dB
VCC+ = 2.2 V to 5 V,
TJ = –40°C to +125°C 64
VO = 0, VICR = 0
CMRR ≥ 50 dB TJ = 25°C –0.3
VICR Input common-mode voltage V
TJ = 25°C 4.1
RL = 600 Ω, TJ = 25°C 80 87
VO = 0.75 V to 4.8 V TJ = –40°C to +125°C 70
AVD Large-signal voltage gain dB
RL = 2 kΩ, TJ = 25°C 80 94
VO = 0.7 V to 4.9 V TJ = –40°C to +125°C 70
TJ = 25°C 4.84 4.882
RL = 600 Ω to VCC+/2
TJ = –40°C to +125°C 4.815
TJ = 25°C 0.134 0.19
TJ = –40°C to +125°C 0.215
VO Output swing V
TJ = 25°C 4.93 4.952
RL = 2 kΩ to VCC+/2
TJ = –40°C to +125°C 4.905
TJ = 25°C 0.076 0.11
TJ = –40°C to +125°C 0.135
Sourcing, VO = 0 V, TJ = 25°C 20 52.6
VIN(diff) = ±0.5 V TJ = –40°C to +125°C 12
IO Output current mA
Sinking, VO = 2.2 V, TJ = 25°C 15 23.7
VIN(diff) = ±0.5 V TJ = –40°C to +125°C 8.5
TJ = 25°C 2.01 2.4
ICC Supply current mA
TJ = –40°C to +125°C 2.8
SR Slew rate (1) TJ = 25°C 5.25 V/μs
GBW Gain bandwidth product TJ = 25°C 10 MHz
Φm Phase margin TJ = 25°C 72 °
Gm Gain margin TJ = 25°C –11 dB
Vn Input-referred voltage noise f = 1 kHz TJ = 25°C 10.5 nV/√Hz
In Input-referred current noise f = 1 kHz TJ = 25°C 0.2 pA/√Hz
f = 1 kHz, AV = 1,
THD Total harmonic distortion TJ = 25°C 0.001%
RL = 600 Ω, VO = 500 mVpp

(1) Connected as voltage follower with 1-V step input. Number specified is the slower of the positive and negative slew rate.

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6.7 Typical Characteristics

1.4 100
1.3

ISOURCE Sourcing Current (mA)

1.2
ICC Supply Current (mA)

1.1
10
1
0.9
0.8
1
0.7
TA = 40qC
0.6 TA = 25qC
0.5 TA = 85qC
TA = 125qC
0.4 0.1
2 2.5 3 3.5 4 4.5 5 5.5 6 0.001 0.01 0.1 1 10
VCC Supply Voltage (V) D001
Output Voltage Referenced to VCC (V) D002

Figure 1. Supply Current vs Supply Voltage Figure 2. Sourcing Current vs Output Voltage
100 100
ISOURCE Sourcing Current (mA)

IO(sink) Sinking Current (mA)

10 10

1 1

VCC = 5 V
0.1 0.1
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10
Output Voltage Reference to VCC (V) D003
Output Voltage Referenced to VCC (V) D004
VCC = 2.2 V

Figure 3. Sourcing Current vs Output Voltage Figure 4. Sinking Current vs Output Voltage
100 0.3

0.2
VOS Input Offset Voltage (mV)
IO(sink) Sinking Current (mA)

10 0.1

1 -0.1

-0.2

VCC = 5 V
0.1 -0.3
0.001 0.01 0.1 1 10 2 2.5 3 3.5 4 4.5 5
Output Voltage Referenced to VCC (V) D005
VCC Supply Voltage (V) D006

Figure 5. Sinking Current vs Output Voltage Figure 6. VIO vs Supply Voltage

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Typical Characteristics (continued)

0.3 0.3

0.2 0.2

VOS Input Offset Voltage (mV)

Input Offset Voltage (mV)

0.1 0.1

0 0

-0.1 -0.1

-0.2 -0.2

VS = 2.2 V VCC = 5 V
-0.3 -0.3
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.25
Input Common Mode (V) D007
VCM Input Common Mode Voltage (V) D008

Figure 7. Input Offset Voltage vs Input Common-Mode Figure 8. Input Offset Voltage vs Input Common-Mode
Voltage Voltage
0.3 0.3
VCC = 2.2 V VCC = 5 V

0.2 0.2
Input Differential Voltage (mV)

Input Differential Voltage (mV)

0.1 0.1

0 0

-0.1 -0.1

-0.2 -0.2

-0.3 -0.3
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Output Voltage (V) D009
Output Voltage (V) D010

Figure 9. Input Voltage vs Output Voltage Figure 10. Input Voltage vs Output Voltage
100 100
Input Voltage Noise (nV/—Hz)

Input Current Noise (pA/—Hz)

10

10

1 0.1
10 100 1000 10000 100000 10 100 1000 10000 100000
Frequency (Hz) D011
Frequency (Hz) D012

Figure 11. Input Voltage Noise vs Frequency Figure 12. Input Current Noise vs Frequency

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Typical Characteristics (continued)

120 120
VCC = 2.2 V

100 100

80 80

Frequency (Hz)
PSRR (dB)

60 60

40 40

20 20

0 0
100 1000 10000 100000 1000000 1E+7 100 1000 10000 100000 1000000 1E+7
Frequency (Hz) D013
PSRR (dB) D014
VCC = 5 V

Figure 13. Psrr vs Frequency Figure 14. Psrr vs Frequency

80 120 80 120
Gain Gain
70 Phase 105 70 Phase 105
60 90 60 90
50 75 50 75
40 60 40 60
Gain (dB)

Gain (dB)
Phase (q)

Phase (q)
30 45 30 45
20 30 20 30
10 15 10 15
0 0 0 0
-10 -15 -10 -15
-20 -30 -20 -30
1000 10000 100000 1000000 1E+7 1E+8 1000 10000 100000 1000000 1E+7 1E+8
Frequency (Hz) D015
Frequency (Hz) D016
VCC = 2.2 V VCC = 5 V

Figure 15. Gain And Phase vs Frequency Figure 16. Gain And Phase vs Frequency
6 1
Rising
5.8 Falling
5.6
0.1
SR Slew Rate (V/PS)

5.4
5.2
THD (%)

5 0.01
4.8
4.6
0.001
4.4
4.2
4 0.0001
2 2.5 3 3.5 4 4.5 5 100 1000 10000 100000
VCC Supply Voltage (V) D017
Frequency (Hz) D018
VCC = 2.2 V

Figure 17. Slew Rate vs Supply Voltage Figure 18. Thd vs Frequency

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Typical Characteristics (continued)

1 1
Input
0.75 21.2 nf+2 K 0.75

0.5 0.5
0.25 per Division

0.25 per Division

0.25 0.25

0 0

-0.25 -0.25

-0.5 -0.5

-0.75 -0.75 Input

21.2 nf+2 K+2.1O
-1 -1
-3 -2 -1 0 1 2 3 4 5 6 -3 -2 -1 0 1 2 3 4 5 6
2 Ps per Division D019
2 Ps per division D020
VCC = 5 V, RL = 2 kΩ, CL = 21.2 nF, RO = 0 Ω VCC = 5 V, RL = 2 kΩ, CL = 21.2 nF, RO = 2.1 Ω

Figure 19. Pulse Response Figure 20. Pulse Response

1 1
Input
0.75 0.75 21.2 nf+10 K

0.5 0.5
0.25 V per Division

0.25 V per Division

0.25 0.25

0 0

-0.25 -0.25

-0.5 -0.5

-0.75 Input -0.75

21.2 nf+2 K+9.5O
-1 -1
-3 -2 -1 0 1 2 3 4 5 6 -3 -2 -1 0 1 2 3 4 5 6
2 PS per Division D021
2 Ps per Division D022
VCC = 5 V, RL = 2 kΩ, CL = 21.2 nF, RO = 9.5 Ω VCC = 5 V, RL = 10 kΩ, CL = 21.2 nF, RO = 0 Ω

Figure 21. Pulse Response Figure 22. Pulse Response

1 1
Input Input
0.75 2120 pF+10 K 0.75 2120 pF+ 2 K+ 2_2

0.5 0.5
250 mV per Division

250 mV per division

0.25 0.25

0 0

-0.25 -0.25

-0.5 -0.5

-0.75 -0.75

-1 -1
-3.5 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 -3.5 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
1 Ps per Division D023
1 Ps per Division D024
VCC = 2.2 V, RL = 10 kΩ, CL = 2.12 nF, RO = 0 Ω VCC = 2.2 V, RL = 10 kΩ, CL = 2.12 nF, RO = 2.2 Ω

Figure 23. Pulse Response Figure 24. Pulse Response

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Typical Characteristics (continued)

1
Input
0.75 2120 pF+2 K+11_5

0.5

250 mV per Division

0.25

-0.25

-0.5

-0.75

-1
-3.5 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
1 Ps per division D025
VCC = 2.2 V, RL = 10 kΩ, CL = 2.12 nF, RO = 11.5 Ω

Figure 25. Pulse Response

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7 Detailed Description

7.1 Overview
The LMV722-Q1 is a low-power, low-noise, rail-to-rail output op amp. This device is AEC-Q100 qualified for
automotive applications. The LMV722-Q1 operates from a single 2.2 V to 5.5 V supply, is unity-gain stable, and
is suitable for a wide range of general-purpose applications. The input common-mode voltage range includes
ground. Rail-to-rail input and output swing significantly increases dynamic range in low-supply applications and
makes applications suitable for driving sampling analog-to-digital converters (ADCs). The small footprints of the
LMV722-Q1 package saves space on printed-circuit boards and enables good signal integrity and noise
performance during the design of smaller electronic products, such as automotive head units.

7.2 Functional Block Diagram

IN− −
OUT
IN+ +

7.3 Feature Description

7.3.1 Low Noise
The LMV722-Q1 device is a general-purpose op amp that provides low noise of 10.5 nV/√Hz and a wide
bandwidth of 10 MHz. The low noise and wide bandwidth make the LMV722-Q1 device attractive for a variety of
precision applications that require a good balance between cost and performance.

7.3.2 Rail-to-Rail Output

Rail-to-rail output swing provides maximum possible dynamic range at the output. This is particularly important
when operating on low-supply voltages.

7.3.3 Input Includes Ground

This feature allows direct sensing near GND in a single-supply operation.

7.3.4 Signal Integrity

Signals pick up noise between the signal source and the amplifier. By using a physically smaller amplifier
package, such as the 8-pin VSSOP (DGK), the LMV722-Q1 can be placed closer to the signal source; reducing
noise pickup and increasing signal integrity.

7.4 Device Functional Modes

The only mode available for the LMV722-Q1 device is on.

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LMV722-Q1 features 10-MHz bandwidth and 5.25-V/µs slew rate providing good AC performance at very-
low-power consumption. DC applications are well served with a very-low input noise voltage of 10.5 nV / √Hz at 1
kHz, low input bias current, and a typical input offset voltage of 0.02 mV.

8.2 Typical Application

Figure 26 shows the LMV722-Q1 configured in a low-side current sensing application.
Vbus

Iload
Zload
5V
+
LMV722 VOUT

VSHUNT
Rshunt RF
0.1 57.6 k

RG
1.2 k

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Figure 26. LMV722-Q1 in a Low-Side, Current-Sensing Application

8.2.1 Design Requirements

The design requirements for this design are:
• Load current: 0 A to 1 A
• Output voltage: 4.9 V
• Maximum shunt voltage: 100 mV

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Typical Application (continued)

8.2.2 Detailed Design Procedure
The transfer function of the circuit in Figure 26 is given in Equation 1
VOUT ILOAD u RSHUNT u Gain (1)
The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set from
0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is
defined using Equation 2.
VSHUNT _ MAX 100mV
RSHUNT 100m:
ILOAD _ MAX 1A (2)
Using Equation 2, RSHUNT is calculated to be 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is
amplified by the LMV722-Q1 to produce an output voltage of roughly 0 V to 4.9 V. The gain needed by the
LMV722-Q1 to produce the necessary output voltage is calculated using Equation 3:
VOUT _ MAX VOUT _ MIN
Gain
VIN _ MAX VIN _ MIN
(3)
Using Equation 3, the required gain is calculated to be 49 V/V, which is set with resistors RF and RG. Equation 4
is used to size the resistors, RF and RG, to set the gain of the LMV722-Q1 to 49 V/V.
RF
Gain 1
RG (4)
Choosing RF as 57.6 kΩ and RG as 1.2 kΩ provides a combination that equals roughly 49 V/V. Figure 27 shows
the measured transfer function of the circuit shown in Figure 26.

8.2.3 Application Curve

4
Output (V)

0
0 0.2 0.4 0.6 0.8 1
ILOAD (A) C219

Figure 27. Low-Side, Current-Sense, Transfer Function

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9 Power Supply Recommendations

The LMV722-Q1 series is specified for operation from 2.2 V to 5.5 V (±1.1 V to ±2.75 V); many specifications
apply from –40°C to +125°C. The section presents parameters that can exhibit significant variance with regard to
operating voltage or temperature.

CAUTION
Supply voltages larger than 6 V can permanently damage the device; see the Absolute
Maximum Ratings table.

Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see the section.

9.1 Input and ESD Protection

The LMV722-Q1 incorporates internal ESD protection circuits on all pins. For input and output pins, this
protection primarily consists of current-steering diodes connected between the input and power-supply pins.
These ESD protection diodes provide in-circuit, input overdrive protection, as long as the current is limited to 10-
mA, as stated in the Layout Guidelines table. Figure 28 shows how a series input resistor can be added to the
driven input to limit the input current. The added resistor contributes thermal noise at the amplifier input and the
value must be kept to a minimum in noise-sensitive applications.

V+

IOVERLOAD
10-mA maximum
Device VOUT
VIN
5 kW

Figure 28. Input Current Protection

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10 Layout

10.1 Layout Guidelines

For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground
planes. A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise
pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the
ground current. For more detailed information refer to, see Circuit Board Layout Techniques.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much
better as opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As illustrated in Figure 30, keeping RF
and RG close to the inverting input minimizes parasitic capacitance on the inverting input.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is
recommended to remove moisture introduced into the device packaging during the cleaning process. A
low-temperature, post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.

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 LMV722-Q1
www.ti.com SLOS969A – JUNE 2017 – REVISED JANUARY 2018

10.2 Layout Example

V- V-
C3

GND
OUTPUT A OUTPUT B
4

4
3 5 U1B
INPUT A R3A INPUT B R3B
1 7
2 6
U1A
8

8
C4 C2A C2B

V+ GND GND V+ GND

R1A R1B

C1A C1B

R2A R2B

GND GND

Figure 29. Schematic Representation for Figure 30

OUTPUT A

GND GND GND

V+

INPUT A

OUTPUT B
INPUT B

V-
GND GND GND

Figure 30. Layout Example

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11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation
For related documentation see the following:
Texas Instruments, Circuit Board Layout Techniques

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

LMV722QDGKRQ1 ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 R6EQ

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF LMV722-Q1 :

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

• Catalog: LMV722

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 17-Jul-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMV722QDGKRQ1 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 17-Jul-2020

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMV722QDGKRQ1 VSSOP DGK 8 2500 366.0 364.0 50.0

Pack Materials-Page 2
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