Ring Counters
Ring Counters
Ring Counters
Abstract
Ring counters are a type of counters composed of shift registers. They are ex-
tremely fast and require few logic gates. This document introduces two types
of ring counters, the straight ring counter and the Johnson counter. The latter
is elaborated on in detail. Some applications are described as well as commer-
cially available devices and designs using Johnson counters. A generic VHDL
description and a description of the commercially available 4017 are provided.
Table of Contents
1 Ring Counters 3
3 Johnson Counter 4
References 9
List of Figures
1 A 4-bit straight ring counter . . . . . . . . . . . . . . . . . . . . . . . . 3
2 A 5-bit Johnson Counter with Terminal Count . . . . . . . . . . . . . . 4
List of Listings
1 A VHDL description of an n-stage Johnson counter . . . . . . . . . . . 6
2 A VHDL description of the 4017 5-stage Johnson counter . . . . . . . . 7
2
1 Ring Counters
Ring counters are a type of counter created using shift registers. A shift register is
constructed using D-type flip-flops where the output of one flip-flop is connected to
the input of another flip-flop [1]. With ring counters, the output of the last flip-flop is
fed to the input of the first flip-flop. Ring counters do not count using normal binary
code, but their internal state can be used to decode to any output sequence wanted.
b) Johnson counter
There is a third counter type using a shift register, the Linear Feedback Shift Register
(LFSR). It has a more elaborate feedback circuit than the other two ring counters and
is therefore not discussed in this document.
A straight ring counter or Overbeck counter connects the output of the last flip-flop
to the first flip-flop input and circulates a single one bit around the ring. It provides
a one-hot counting sequence. For example, in a 4-register ring counter, with initial
register values of 1000, the repeating sequence is 1000, 0100, 0010, 0001. Note that one
of the flip-flops must be pre-loaded with a logic 1 in order for it to operate properly.
Also note that an n-bit ring counter cycles through exactly n states.
1D 1D 1D 1D
[FF0] [FF1] [FF2] [FF3]
C1 C1 C1 C1
clk
reset
Figure 1: A 4-bit straight ring counter.
Straight ring counters are currently seldom used and there are no commercial devices
available. In the past, they were mainly used as decimal counters using Nixie tubes
and neon tubes [2, 3].
3
3 Johnson Counter
Another form of ring counter is created by feeding back the complement of the contents
of the last flip-flop to the input of the first flip-flop. This is called a twisted ring counter,
but is better known as the Johnson counter. The alternative term Möbius counter is
found in many books and articles because the Johnson counter resembles the famous
Möbius strip [4]. For example, in a 5-flip-flop Johnson counter with an initial register
contents (or state) of 00000, the repeating sequence is 00000, 10000, 11000, 11100,
11110, 11111, 01111, 00111, 00011, 00001. When observing the pattern, it can be
seen that any changes between succeeding states, only one flip-flop changes state. As
a result, any of these states is directly, spike-free decodable with only a two-input
gate [5, 6].
Figure 2 shows a 5-bit Johnson counter with terminal count output tc. This output
becomes high in the last counting state 00001 before returning to 00000.
1D 1D 1D 1D 1D
[FF0] [FF1] [FF2] [FF3] [FF4]
C1 C1 C1 C1 C1
clk
≥1
tc
Figure 2: A 5-bit Johnson Counter with Terminal Count. The reset is omitted for clarity.
Only the two most significant flop-flops have to be sampled, so tc is logic ‘1’ when Q3
is logic ‘0’ and Q4 is logic ‘1’. Using De Morgan’s theorem, the resulting function can
be realised using a NOR gate and the already available flip-flop outputs.
tc = Q3 · Q4 = Q3 + Q4 (1)
It can be easily shown that an n-bit Johnson counter cycles through exactly 2n states.
This becomes increasingly inefficient for n > 2 since any n-bit counter has 2n states
by itself. If the Johnson counter enters a state that does not belong to the original
counting sequence, it will exhibit a single parasitic counting sequence with 2n − 2n
states [7, 8]. This is why most commercial devices incorporate self-correcting logic.
Within a full counting sequence or so, the device will resume normal operation, as
shown for example in the schematic in [9].
Johnson counters are very fast because there is no logic between the output of one
flip-flop and the input of another flip-flop, i.e., there is no next state logic (one would
expect an inverter in the feedback loop but the inverted output of a flip-flop is usually
4
available, especially on ASIC’s [10]). Therefore the maximum frequency at which the
counter operates reliably is given by (2).
1
fmax = (2)
tP (max) (FF) + tsu (FF)
where fmax is the maximum obtainable frequency, tP (max) (FF) is the maximum propa-
gation delay of the flip-flop outputs with respect to the active clock edge and tsu (FF)
is the setup time of the flip-flops. The propagation delay of output tc with respect to
the active clock edge is given by (3).
where tP (min) and tP (max) are the minimum and maximum propagation delays of the
named signals.
5
6 Design using Johnson Counters
A very nice design using Johnson counters is the LFO generator by R.G. Keen [19].
A number of 4017 designs, including an automatic bathroom light switch and a led
chaser circuit, can be found on [20].
Using a number of 4017, one can build a Nixie tube digital clock [21].
The 4026 and 4033 Decade Counters consist of a 5-stage Johnson counter similar to
the 4017 and an output decoder that converts the counter state to 7-segment decoded
outputs [22].
Ben Kuiper describes a range detection circuit using 4017’s (and more 4000-series
devices) in [23].
6
22 generic (n : integer := 5) ;
23 port ( clk : in std_logic ;
24 areset : in std_logic ;
25 count : out std_logic_vector (0 to n -1) ;
26 tc : out std_logic
27 );
28 end entity johnson_counter ;
29
30 architecture rtl of johnson_counter is
31 -- Internal counter signal
32 signal count_int : std_logic_vector (0 to n -1) ;
33 begin
34
7
12 -- This VHDL description describes the behaviour of an CD4017B 5 - stage
13 -- Johnson counter with spike free active high decoded outputs .
14 -- See http :// www . ti . com / lit / ds / symlink / cd4017b . pdf for more information .
15 --
16 -- In some designs , the naming of the pins is different :
17 -- clock -> CP0
18 -- clock_inhibit -> ~ CP1 or not ( CP1 )
19 -- reset -> MR
20 -- carry out -> not (Q) 5 - -9
21 --
22 -- Please note that this design uses clock - gating : the clock is gated
23 -- with an AND gate and a signal clock_inhibit . This is a poor hardware
24 -- design . It produces both pulse - triggered behaviour of the clock input
25 -- ( clock_inhibit must be held stable when clock is high ) and clock skew
26 -- ( the resulting clock pulse is delayed by the AND gate ) .
27 -- PLEASE USE THIS DESIGN FOR REFERENCE ONLY , NOT IN REAL PRODUCTS .
28
29 -- Using the 1164 std_logic
30 library ieee ;
31 use ieee . std_logic_1164 . all ;
32
33 -- The port description of the 4017
34 entity cd4017b is
35 port ( clock : in std_logic ;
36 reset : in std_logic ;
37 clock_inhibit : in std_logic ;
38 q : out std_logic_vector (9 downto 0) ;
39 carry_out : out std_logic
40 );
41 end entity cd4017b ;
42
8
67 -- The outputs
68 carry_out <= not count_int (5) ;
69 q (0) <= not ( not count_int (1) nand not count_int (5) ) ;
70 q (1) <= not ( count_int (1) nand not count_int (2) ) ;
71 q (2) <= not ( count_int (2) nand not count_int (3) ) ;
72 q (3) <= not ( count_int (3) nand not count_int (4) ) ;
73 q (4) <= not ( count_int (4) nand not count_int (5) ) ;
74 q (5) <= not ( count_int (1) nand count_int (5) ) ;
75 q (6) <= not ( not count_int (1) nand count_int (2) ) ;
76 q (7) <= not ( not count_int (2) nand count_int (3) ) ;
77 q (8) <= not ( not count_int (3) nand count_int (4) ) ;
78 q (9) <= not ( not count_int (4) nand count_int (5) ) ;
79
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