energies

Article
A Simple Multilevel Space Vector Modulation
Technique and MATLAB System Generator Built
FPGA Implementation for Three-Level Neutral-Point
Clamped Inverter
P. Madasamy 1 , R. K. Pongiannan 2 , Sekar Ravichandran 3, *, Sanjeevikumar Padmanaban 4 ,
Bharatiraja Chokkalingam 2,5, * , Eklas Hossain 6 and Yusuff Adedayo 5
1 Department of Electrical and Electronics Engineering, Alagappa Chettiar college of Engineering and
Technology, Karaikudi 630003, India; [email protected]
2 Department of Electrical and Electronics Engineering, SRM Institute of Science and Technology,
Chennai 603203, India; [email protected]
3 Department of Electrical and Electronics Engineering, Sreenidhi Institute of Science and Technology,
Hyderabad, Telangana 501301, India
4 Department of Energy Technology, Aalborg University, 6700 Esbjerg, Denmark; [email protected]
5 Department of Electrical Engineering, University of South Africa, Pretoria 1709, South Africa;
[email protected]
6 Oregon Renewable Energy Center (OREC), Department of Electrical Engineering & Renewable Energy,
Oregon Tech, Klamath Falls, OR 97601, USA; [email protected]
* Correspondence: [email protected] (S.R.); [email protected] (B.C.); Tel.: +82-2220-4349 (B.C.)




Received: 29 June 2019; Accepted: 4 November 2019; Published: 14 November 2019


Abstract: The pulse width modulation (PWM) is an important segment in power electronic inverters
and multilevel inverters (MLIs) design. The space vector modulation (SVM) methods own distinct
advantages over other PWM methods. However, MLI SVM has involved more mathematics in
their executions. Hence, the digital signal processors (DSPs) or field programmable gate arrays
(FPGAs) based digital implementations are highly preferred for MLI SVM realizations, which require
exceptional properties. The conventional MLI SVMs use complex mathematical functions to solve
their internal functions to identify the space vector diagram (SVD) sub-triangle and over modulation
boundary switching on-times. Particularly these are the changes in the position of reference vector
with respect to their sub-triangle positions involving higher mathematical functions. This paper
proposes a simplified three-level MLI SVM that reduces the sub-triangle and over modulation
switching on-time calculations with reduced mathematical functions. The proposed MLI SVM
is derived based on two-level SVM without changing the reference vector position, unlike the
traditional approaches. This helps in extending the SVM for any n-level inverter with additional LUTs.
The detailed theoretical study, MATLAB-Simulink system generator simulations and Xilinx FPGA
family SPARTAN-III-3A based experimental implementations are done with three-level neutral point
MLI fed induction motor drive. The theoretical design, analysis, and experimentation results validate
the advantages of the proposed PWM design and its implementation. In addition, the proposed
implementation is executed from the MATLAB Xilinx system generator directly into target FPGA,
which makes it faithful, efficient and minimizes the time spent.

Keywords: pulse width modulation (PWM); multilevel inverter (MLI); space vector modulation
(SVM); field programmable gate array (FPGA)

Energies 2019, 12, 4332; doi:10.3390/en12224332 www.mdpi.com/journal/energies

Energies 2019, 12, 4332 2 of 24

1. Introduction
The involvement of modern power electronics converters in the emerging technology is essential
for the electrical system in the current era. Very particularly, in the overall power electronics segment,
the voltage source two-level inverters are very popular and demanding, due to their application
encroachment in industrial, commercial and non-conventional energy conversion systems [1].
Compared with two-level inverters, multilevel inverters (MLIs) have substantial rewards, which
are intensive in the enhancement of the voltage and current waveform quality, reduction of harmonic
contents, and increment of power handling capability. Nabae et al. invented the first MLI based
on two-level inverter structure called neutral-point clamped (NPC) topology in 1981 [2] which was
followed by the development of cascaded H-bridge (CHB), flying capacitor (FC), and hybrid MLIs in
later years. Even though these MLIs are capable of producing the multi-stepped output voltages with
reduced dv/dt and harmonics for improved power qualities. But, considering the DC-link capacitors
balancing and common mode voltage (CMV) reduction, the MLIs are widely still investigated with
different modulation strategies [3] for compensation methods. Among them, space vector modulation
(SVM) offers better-quality voltage and current output with higher DC-link utilization. In addition,
SVM provides a switching state selection opportunity to improve the performance of the MLI [4–15].
Particularly, the SVM contributions in NPC-MLI are widely researched and applied in the various fields
of drives and renewable energy integration applications [5]. The switching selections in the multilevel
SVM are mainly associated with the space vector diagram (SVD) synthesization and switching states
on-time calculation. The multilevel SVM using two-level concepts are widely explored than the other
MLI SVM methods [4,9,12–16]. However, these methods include complex mathematics to calculate the
target reference voltage vector and recognize inner sub-triangle etc. The Zhang et al. has introduced a
method for finding switching states on-time using direct two-level SVM approach. In this method, the
three-level SVD has fragmented to a six, equal, two-level SVD, and its location of the centre of six virtual
hexagons originated through segregation of the SVD [17]. Similar to this method, in the literature,
many papers have been reported in which shifting the origin to one of the six centres, and αβ-axes are
rotated by 60◦ to use two-level on-time calculations [12–16,18–21]. Even though these methods are
calculating the individual switch on-times from segregated two-level SVM, while extending to higher
levels that need complex mathematical functions to calculate the sub-triangle. Seo et al. [18] proposed
a scheme for an MLI SVM for three-level NPC similar to Zhang et al. where the origin is shifted to
60◦ which sorts six sub-hexagons to compute on-times, thereby involving additional computations.
The three-level SVD based two-level SVD with reduced math function is proposed and implemented
for NPC-MLI [9]. The similar idea is extended to linear modulation (LM) and over modulation (OVM)
region with field programmable gate array (FPGA) implementation for NPC-MLI [19–23].
In [19], the multilevel SVD is divided into six equal two-level SVDs and switching vector on-
time calculations are made through direct transformations from three neighboring switching vectors.
However, the estimation of the on-time calculation is done by extending a set of matrix transformations,
which includes complex computations. Extending the inverter modulation index more than 0.907 is
called as OVM. It requires non-linear mathematical functions to synthesis their reference vector outside
SVD hexagon [24–26]. The industrial drives, such as direct torque and field-oriented controller need
OVM region operations, since linear modulation range operation restricts the inverter modulation
index, and hence, the drives produce limited constant torque as it utilizes only 90% of input DC-link
voltage. Hence, the inverter drive covering OVM is beneficial by means of entire exploitation of the
installed input source capacity, which results in the increased cumulative speed-torque characteristics,
as well as the operating boundary of the traction drives. However, OVM leads to complexities in
hardware implementations, due to non-linearity switching equations [20]. Due to this complexity in the
OVM region synthesization and on-time calculations, many studies are not preferred to include OVM
region operation. Very few implementations have performed in the OVM region operation [21–31].
These implementations are using complex mathematical functions to realize the OVM non-linear region
and on-time calculations. To realize the OVM region, the non-linear trigonometric functions are used
Energies 2019, 12, 4332 3 of 24

to find the modified on-times. These methods are relatively complex to implement [24,25]. Most of the
OVM region studies in MLI SVM have been done by charging the reference vector position [23,24,26–30].
The on-time switching calculations of OVM using virtual vectors were recognized by using modifying
hexagonal trajectory. However, in these methods, there would be portions of the line cycle, where
the preferred reference vector could not be synthesized [28], [30]. Few algorithms were developed
which use additional switching time derived from the outside hexagonal boundary projection [26,29].
However, these methods are introducing lower frequency harmonics, which are affecting the output
waveform quality.
The rapid developments in high-performance microcontrollers, DSPs and FPGAs, have encouraged
the research of work on digital PWM for rapid prototyping. Due to the development of ASIC technology,
the FPGA based implementations have become popular, since it has an ability to implement custom
hardware solutions and reprogramming flexibility. The SVM implementations on FPGA are showing
a higher interest in the current era [6,12,14,32–44]. These implementations are mainly done through
Altera and Xilinx Spartan family. The first successful single chip FPGA implementation of SVM has
been presented by Tzou et al. [33], and followed by a variety of single chip FPGA IP core three-level
SVM implementation and reported the validation [34–36,40]. These implementations have been done
through Altera Vertex and Spartan with large device utilization and computational time. These direct
VHDL code based implementations have suffered from the drawbacks of computational burden (writing
VHDL/Verilog coding), high device utilization, and higher time taken. Particularly at high modulation
ranges, due to the higher mathematical burden, the processing time is being increased [23,29,42].
These methods are very effective for implementation in terms of calculating the switching vectors
and dwell times by means of simple addition and comparison operators without using any angles,
trigonometric function and LUTs. However, the extension to OVM in n-level needed high mathematical
operations and high hardware resources. The low complexity and fewer computation approaches make
the SVM implementations very suitable for real-time application drive systems. The FPGA Spartan
processors are developed on a VHDL code to carry out the implementation into FPGA. By the use of
Xilinx system generator ISE tools, the SVM implementations have focused on increasing the processing
speed, reduce the device utilization and the reconfiguration (partial and full) implementations [37,40].
In any implementation, the resource (FFs, LUTs) utilization is a major factor. Wang et al. [45] deployed
three-level SVM in Spartan-3 FPGA with the consumption of 3,584 slices. Few more attempts were
made with the same FPGA, which were also found to have higher resource utilization [14,23,40]. As an
alternative, the same can be achieved using MATLAB/Simulink-Xilinx System generator tools with
foundation ISE tools [46].
From the wide range of literature in the MLI SVM design and FPGA implementations, the
existing methods involve higher computational complications for finding reference vector location
and the on-time calculations of switching states. Hence, the existing FPGA implementations occupy
higher device utilization and processing time. The reference vector positions in the multilevel SVD
sub-triangle and over modulation boundary on-time calculations need to be rethought. Subsequently,
the FPGA digital implementations era facilitates the exploitation of control degree of freedom in
both LM and OVM region. Therefore, in this paper, a reduced mathematical approach is developed
for identifying the sub-triangles and over modulation boundary area for calculating switching
on-times. The proposed SVM has a direct way for calculating the LM and OVM switching times using
two-level SVM. The proposed SVM is simulated using MATLAB-Simulink ISE system generator and
validated directly in Xilinx family SPARTAN-III-3A XC3SD1800A-FG676 DSP-FPGA processor board.
The implementation is verified through a three-level NPC-MLI fed induction motor drive laboratory
prototype, and the test is performed over a wide range of operating conditions. The proposed SVM
and their FPGA implementations are compared with the other reported methods. The theoretical
design, analysis, and experimentation results validate the advantages of the proposed PWM design
and its implementation.
 experimental results. In conclusion, the rewards of the proposed MLI SVM and its implementation
are presented in Section 8. The list of abbreviations and references are given in the end.

2. State of Art of Space Vector PWM Theory for Two-Level and Multilevel.
Energies 2019, 12, 4332 4 of 24

2.1. Two-Level Space Vector Modulation

The organization of the paper is deliberate as follows: Section 2 explains the space vector PWM
Figure 1a shows the SVD of a two-level inverter [38]. Here, every sector (represented as Si, where
theory for two-level and multilevel. Section 3 deals with the proposed simplified MLI SVM, including
i = 1 to 6) is an equilateral symmetrical triangle with the height of h (= √3/2). Here the edge vectors
both linear and over modulations. Section 4 accomplishes the MATLAB-Simulink implementation, and
(V1 to V6) are named as non-zero (active vectors) and V0 and V7 are called zero vectors. The on-time
Section 5 discusses the FPGA collaborated experimentation setup of three-level MLI. Sections 6 and 7
calculation of SVM switching in any sector is calculated among three nearest switching vectors (one
deal with the distributed implementation of MLI SVM in FPGA MATLAB XSG-ISE and experimental
zero vector and two active vectors). The movement of the reference or target vector V* positioning
results. In conclusion, the rewards of the proposed MLI SVM and its implementation are presented in
inside the sector is synthesizing the switching times. To understand the two-level switching of SVD,
Section 8. The list of abbreviations and references are given in the end.
the sector-1 is considered here, as shown in Figure 1b. The volts-second of V* is determined by
multiplication
2. State of Art of Spaceof V* and sampling
Vector PWM Theory timefor(Ts). Then the and
Two-Level timeMultilevel
integral of V* is estimated through the
summation of products of the two of non-zero vectors (V1 and V2 by referring sector-1) and their time
widths (TSpace
2.1. Two-Level 1 andVector
T2). Modulation
The reference voltage V* volts-sec equation for the sector-1 is calculated as,
Figure 1a shows the SVD of a two-level inverter [37]. Here, every sector √ (represented as Si , where
V ∗ T with
i = 1 to 6) is an equilateral symmetrical triangle = T Vthe+height
T V +of ThV (= 3/2). Here the edge vectors (1)
(V1 to V6) are named as non-zero (active vectors) and V0 and V7 are called zero vectors. The on-time
where T1 and T2 represents time(sec) widths of adjacent switching vectors V1 and V2 correspondingly,
calculation of SVM switching in any sector is calculated among three nearest switching vectors (one
and T0 represents as time (sec) width of zero vector (V0). This zero vector state can be either [000] or
zero vector and two active vectors). The movement of the reference or target vector V* positioning
[111] switching state, or else both. The movement of V* angle (θ) within the sector is computed by
inside the sector is synthesizing the switching times. To understand the two-level switching of SVD,
the sector-1 is considered here, as shown in Figure 1b. The V volts-second of V* is determined by
θ = tan . (2)
multiplication of V* and sampling time (Ts ). Then the timeVintegral of V* is estimated through the
summation of products
The θ values of the two
sample theofV*
non-zero vectors
in different (V1 and
sector (forVexample,
2 by referring
whensector-1) andthe
θ is 115°, their
V*time
approach
widths (T1 and
sector-2, T ).
2 sector-2 lies in an angle between 61° to 120°).
since
β
VL2 [110]
VL3 [010]
h V1 ={0,1}
S2 V2 ={0.5,h}
S1 VS ={VS α0 ,VS β 0 } VL2 [110]
S3 V*Ts
Ma = 1
VL4 [011] θ VL1 [100]
Vz V1 Ta α
V2 T2
S4 [000] S5 Vz
V*Ts
[111]
[000] θ S1 Ma = 0.907

S5 [111] VL1 [100]

V1 T1
VL5 [001] VL6 [101]
(a) (b)

1. (a) Space
FigureFigure vectorvector
1. (a) Space diagram (SVD) (SVD)
diagram for two-level inverter,
for two-level (b) sector-1
inverter, for two-level
(b) sector-1 inverterinverter
for two-level SVD.
SVD.
The reference voltage V* volts-sec equation for the sector-1 is calculated as,
According to the V* position, whether inside or outside the hexagonal SVD (see Figure 1), SVD
V∗ Ts =
is divided into linear modulation T1 V1 +
(where 2 + T0 V
MaT≤2 V0.907) 0
and over modulation (where Ma >(1)0.907),
respectively.
where T1 and T2 represents time(sec) widths of adjacent switching vectors V1 and V2 correspondingly,
The total period is Ts = T1 + T2 + T0. T1 and T2 are calculated from projecting V* position along α-
and T0 represents as time (sec) width of zero vector (V0 ). This zero vector state can be either [000] or
axis and β-axis with respect to SVD origin (zero point). Henceforth, the volts-sec equations for α-axis
[111] switching state, or else both. The movement of V* angle (θ) within the sector is computed by
and β-axis are V Ts = T1 + 0.5T2 and V Ts = hT2. Thus, the active vector time can be written as, T2 = Ts
V /h and T1 = Ts (V − V )/2h. From the givenVswitching frequency, the T1 and T2 help to find the
!
−1 α
zero voltage time T0. θ = tan . (2)
Vβ

The θ values sample the V* in different sector (for example, when θ is 115◦ , the V* approach
sector-2, since sector-2 lies in an angle between 61◦ to 120◦ ).
According to the V* position, whether inside or outside the hexagonal SVD (see Figure 1), SVD is
divided into linear modulation (where Ma ≤ 0.907) and over modulation (where Ma > 0.907), respectively.
Energies 2019, 12, 4332 5 of 24

The total period is Ts = T1 + T2 + T0 . T1 and T2 are calculated from projecting V* position along
α-axis and β-axis with respect to SVD origin (zero point). Henceforth, the volts-sec equations for α-axis
and β-axis are Vsα0 Ts = T1 + 0.5T2 and Vsβ0 Ts = hT2 . Thus, the active vector time can be written as,
T2 = Ts Vsβ0 /h and T1 = Ts (Vsα0 − Vsβ0 )/2h. From the given switching frequency, the T1 and T2 help to
Energies 2019, 11, x FOR PEER REVIEW
find the zero voltage time T0 .
2.2. Multilevel Space Vector Modulation
2.2. Multilevel Space Vector Modulation
Realizing SVM for more than two-level inverter (conventional six-switch inverter) is called MLI
Realizing SVM for more than two-level inverter (conventional six-switch inverter) is called MLI
SVM. Numerous MLI SVM are developed and employed in MLIs for different applications [6,4,12,20].
SVM. Numerous MLI SVM are developed and employed in MLIs for different applications [4,6,12,20].
The difficulty in the multilevel SVM is its complex mathematical needs to locate the V* and find the
The difficulty in the multilevel SVM is its complex mathematical needs to locate the V* and find the
individual vectors. The interesting techniques are proposed in the literature to reduce the complexity
individual vectors. The interesting techniques are proposed in the literature to reduce the complexity
of implementing the MLI SVM with reasonable inverter performances.
of implementing the MLI SVM with reasonable inverter performances.
Any of the three-phase n-level SVD can be separated into six sectors (Si), where i = 1 to 6. These
Any of the three-phase n-level SVD can be separated into six sectors (Si ), where i = 1 to 6.
sectors are further separated into (n−1)2 sub-triangles (Δi,j) where j = 0 to 3 and i = 1 to 6. Hence, the n-
These sectors are further separated into (n−1)2 sub-triangles (∆i ,j ) where j = 0 to 3 and i = 1 to 6. Hence,
level SVD consists of n3 switching states. For example, considering the three-level MLI SVD, as shown
the n-level SVD consists of n3 switching states. For example, considering the three-level MLI SVD, as
in Figure 2, it has 27-switching states (3 = 27) 3and 24-sub-triangles (No. of sub-triangles in each sector
3
shown in Figure 2, it has 27-switching states (3 = 27) and 24-sub-triangles (No. of sub-triangles in each
is (3−1)2 = 4; therefore, 4 × 6 = 24) [6,9]. The switching vector for any level MLI is categorized into
sector is (3−1)2 = 4; therefore, 4 × 6 = 24) [6,9]. The switching vector for any level MLI is categorized
zero vector (ZV), short vector (SV) large vector (LV), and medium vector (MV). Here the ZV, MV and
into zero vector (ZV), short vector (SV) large vector (LV), and medium vector (MV). Here the ZV, MV
LV lie in the origin and boundary of the SVD, whereas, SV is multiple in numbers and placed in the
and LV lie in the origin and boundary of the SVD, whereas, SV is multiple in numbers and placed in
middle portion of the SVD. Table 1 displays the three-level inverter SVD switching states.
the middle portion of the SVD. Table 1 displays the three-level inverter SVD switching states.

β
VL3 [-11-1] VM2 [01-1] VL2 [11-1]

[-110] [110],[00-1]
[010],[-10-1] VS2 ∆
VM3 1,4
VS3 VM1 [10-1]
∆2,1
∆1,3
∆3,1 ∆1,1 V* ∆1,2
VL4 VL1[1-1-1]
[-11-1] [000],[111][-1-1-1] VS1 [100],[0-1-1]
VZ θ
VS4
[011,[-100]
∆6,1 α
∆4,1
∆5,1
[-101]
VM4
VS5 VM6 [1-10]
VS6
[001],[-1-10]
[101],[0-10]

VL5 [-1-11] VM5 [0-11] VL2 [-1-11]

Figure 2. Three-level multilevel inverter (MLI) SVD.

Figure 2. Three-level multilevel inverter (MLI) SVD.
Table 1. Three-level inverter SVD switching states.
Table 1. Three-level inverter SVD switching states.
Switching vector name Switching states Total number of states
Switching
ZV
vector name Switching states
[000], [111], and [−1−1−1]
Total number3 of states
ZV [000], [111], and [−1−1−1] 3
MV [10−1], [01−1], [−110], [−101], [0−11], [1−10] 6
MV [10−1], [01−1], [−110], [−101], [0−11], [1−10] 6
[100], [0−1−1], [110], [00−1],
SVSV [100],[0−1−1],[110],[00−1], 1212
[010], [101], [011], [100], [001], [110], [101], [0−10]
[010],[101],[011],[100],[001], [110],[101],[0−10]
LV
LV [1−1−1],
[1−1−1], [11−1], [−11−1],[−111],
[11−1], [−11−1], [−111],[−1−11],
[−1−11], [1−11]
[1−11]; 6 6

In three-level SVD, the SVs and ZVs have redundancy-switching states that are two for SVs and
three for ZVs. When the MLI level is increased, the number of redundancy-switching states for ZVs
and SVs are increased.
The switching states and their on-time calculations are calculated based on the rotating reference
vector, V* position in any one of the four sub-triangles in the particular sector. For example, when V*
lies in the fouth sub-triangle of first sector (Δ1,4), then the nearest three vectors VS2, VM1 and VL2,
Energies 2019, 12, 4332 6 of 24

In three-level SVD, the SVs and ZVs have redundancy-switching states that are two for SVs and
three for ZVs. When the MLI level is increased, the number of redundancy-switching states for ZVs
and SVs are increased.
The switching states and their on-time calculations are calculated based on the rotating reference
vector, V* position in any one of the four sub-triangles in the particular sector. For example, when
V* lies in the fouth sub-triangle of first sector (∆1,4 ), then the nearest three vectors VS2 , VM1 and VL2 ,
switching state are used to synthesize the V*. The duty cycle of the above nearest switching vectors
δVS2 , δVM2 and δVL2 can be calculated and applied to the pulse generations.
Fixing the V* in the sub-triangle is the most difficult task in the SVD realizations. Few mathematical
approaches have been developed for finding V* at sub-triangle, which needed high-end digital
controllers to implement them [4,7,8,16]. In addition, considering the over modulation operation in
MLI, the complexity is further increased to project the trajectory location in SVD. Once the vector
moves outside the hexagonal boundary of the SVD, positioning the vector in the non-linear region
(unstructured boundary) is predicted from the available switching vector and its on-times. The MLI
SVD over modulation implementations differ from two-level SVD [19,29,30]. In MLI SVD over
modulation, the OVM boundary is operating through the crux of MVs and LVs, whereas, in two-level
SVD OVM the LVs only play to synthesis the on-time calculation of OVM pulses.

3. Proposed Simplified MLI SVM for Entire Modulation Index

One of the important contributions of this paper is to propose the simple mathematical approach
to find out the V* sub-triangle position of MLI SVM. The proposed MLI SVM is developed based on
standard two-level SVM for three-level MLI, and it can be extended for n-level using simple additional
equations. In addition to proposed sub-triangle calculation, the reduced mathematical functions for
calculating OVM switching on-times is achieved by just adding the compensated on-time gain in
over modulation region with LM on-time. Hence, the proposed SVM reduces the implementation
burden, since the complex part of MLI SVM calculations of sub-triangle position and OVM on-times
are minimized.

3.1. Procedure in Generating MLI SVM in Linear Modulation

Figure 3 shows the three-level MLI SVM generation flowchart. Like two-level SVM, the MLI
SVM takes the three-phase signal to calculate two-phase voltage vectors stationary reference frame
(Vα ,Vβ ) [20]. Then, the Vα , Vβ are converted into reference voltage vector in polar form as V* ∠ θ,
where ‘V* ’ is the voltage magnitude, and ‘θ’ is the angle of the V*.
Using V* and θ, the reference vector sector position is calculated. Here, based on the V* magnitude
the SVD operation regions (either LM or OVM) are calculated. In Figure 3, the flow chart is handling
only LM MLI SVM, where the proposed sub-triangle calculations are the same for LM and OVM.
The V* sub-triangle location calculation with-in the sector is calculated through orthogonal time
slope mathematical function in Vα , Vβ plane. The stationary plane of Vsαo and Vsβo are calculated for
every Ts and then mapping for the reference vector V* located in sub-triangle is done by comparing
Vsαi and Vsβi . These logical expressions can be applied for any level for identifying the V* sub-triangle.
The next section explains the proposed sub-triangle calculations.
Energies 2019, 11, x FOR PEER REVIEW

Energies 2019, 12, 4332 7 of 24

comparing V and V . These logical expressions can be applied for any level for identifying the V*
sub-triangle. The next section explains the proposed sub-triangle calculations.

Va, Vb, Vc

Three-Phase to Two-Phase Conversion

V ∗ = V + V ;γ=tan V ⁄V

S = int(θ⁄60) + 1;γ = rem(θ⁄60)

Sub-triangle Identification

V = |V ∗ | cos θ ; V = |V ∗ | sin θ
Zone1 = int V + V ⁄√3 ; Zone2 = int V ⁄h
V = V − Zone1 + 0.5 × Zone2 ; V = V − Zone2 × h

Sub-triangle Identification using Lookup Table

Zone1 Zone2 ,
0 0 Δ
0 1 Δ
1 0
1 1 Δ

Rhombus Triangle Identification

V ≤ √3V

Type-1 sub-triangle Type-2 sub-triangle

Δ = Z + 2Z Δ = Z + 2Z + 1
YES

V = V :V = V V = 0.5 − V ; V =h−V

T = T (V − V ⁄√3); T = T V ⁄h ; T = T − T − T
Figure 4. Flow chart for MLI SVM in LM.

Figure 4. Flow
Figure chart
3. Flow for MLI
chart SVMSVM
for MLI in LM.
in LM.

3.2. Proposed Sub-Triangle Calculations

Energies 2019, 12, 4332 8 of 24

3.2. Proposed Sub-Triangle Calculations

Considering the three-level multilevel SVD, shown in Figure 4, the sub-triangle 1 and 4 (type-1
Energies 2019, 11, x FOR PEER REVIEW
triangles) can be directly calculated from the V* magnitude, sector number and its respective sector
angleFixing
(γ), the V* in the sub-triangle is the most difficult task in the SVD realizations. Few
mathematical approaches have been developed for(finding
γ = rem θ/60). V* at sub-triangle, which needed high-end
(3)
digital controllers
However, to implement
this calculation doesthem [4,7,8,16].
not support In addition,
to calculate considering
sub-triangle 2 andthe over modulation
3 (type-2 triangles).
operation
Hence, in MLI,
in order the complexity
to handle type-1 and is type-2
furthertriangles
increased to project
searching the trajectory
progress, a simplelocation
look-upintable
SVD.andOnce
a
the vector moves outside the hexagonal boundarys of the
s SVD, positioning the vector in the non-linear
searching process is developed directly from Vαi and Vβi . Once the V* sub-triangle is identified, that
region (unstructured
particular sub-triangleboundary) is predicted
can be considered as afrom theand
sector available switchingSVM
then two-level vector and its on-times.
is applied The
to calculate
MLIrespective
the SVD oversub-triangle
modulationswitching
implementations differ calculation.
states on-time from two-level TheSVD
same[19,29,30].
procedureInis MLI SVDtoover
applied all
sectors in the particular Ma and fs . The proposed sub-triangle calculation is explained throughtwo-level
modulation, the OVM boundary is operating through the crux of MVs and LVs, whereas, in sector-1
SVD) as
(∆ OVM the LVsinonly
illustrated play4.to synthesis the on-time calculation of OVM pulses.
Figure
1,j

Figure4.3. SVD
Figure SVD linear
linearmodulation
modulation(LM)
(LM)and
andover
overmodulation
modulation(OVM)
(OVM)boundary.
boundary.

The calculation
3. Proposed of proposed
Simplified MLI SVMsub-triangle involves two
for Entire Modulation approaches: (1) Type-1 sub-triangles,
Index.
(2) Type-2 sub-triangles. The V* position for Type-1 triangles ∆1,1 and ∆1,4 can be calculated directly
One of the important contributions of this paper is to propose the simple mathematical approach
from Vsαi and Vsβi . However, the calculation of Type-2 triangles ∆1,3 and ∆1,2 (orange colored area in
to find out the V* sub-triangle position of MLI SVM. The proposed MLI SVM is developed based on
Figure 5b) portions are challenging. Figure 5 shows the V* location identification for Type-1 and Type-2
standard two-level SVM for three-level MLI, and it can be extended for n-level using simple additional
triangles. According to that, the search process of the triangle of V* can be narrowed down using the
equations. In addition to proposed sub-triangle calculation, the reduced mathematical functions for
two zones in SVD (Zone-1 and Zone-2). The coordinates (Vα0 , Vβ0 ) of these triangles are calculated
calculating OVM switching on-times is achieved by just adding the compensated on-time gain in over
using two integer calculations of Zone-1 and Zone-2 as follows,
modulation region with LM on-time. Hence, the proposed SVM reduces the implementation burden,
√ 
since the complex part of MLI SVM calculations
= int(Vα of
+ sub-triangle
Vα / 3 ), position and OVM on-times (4) are

Zone1
minimized.
Zone2 = int(Vα + h). (5)
3.1. Procedure in Generating MLI SVM in Linear Modulation
In Equation (4), Zone-1 integer denotes the portion of the sector among the two lines joining
Figure divided
the vertices 4 shows the three-level
by distance ‘h’MLI
and SVM generation
inclined flowchart.
at 120◦ with respectLike
to two-level
α-axis. In SVM,
Figurethe 5b,MLI SVM
Zone-1
takes the three-phase signal to calculate two-phase voltage vectors stationary reference
is valued as zero, it indicates that the point V* is below the line B and C. The Zone-1 appears that frame (Vα,Vβ)

[20].point
Then, α, Vβ are converted into reference voltage vector in polar form as V ∠ θ, where ‘V*’ is
V*the
liesVbetween
*
the the points A and B and D and F. The Zone-2 denotes the part of the sector
the voltage
between themagnitude, and ‘θ’the
two lines joining is vertices
the angleseparated
of the V*.by distance ‘h’ and parallel to α-axis. When the
Zone-2 Using V* and
is valued θ, the
as zero, referencethat
it indicates vector sector position
the reference vector tipis V*
calculated. Here,
is positioned basedthe
between onlines
the A
V*
magnitude the SVD operation regions (either LM or OVM) are calculated. In Figure
and D and C and E. When the Zone-2 is valued as integer one, it indicates that the point V* lies above 4, the flow chart
is handling only LM MLI SVM, where the proposed sub-triangle calculations are the same for LM and
OVM.
The V* sub-triangle location calculation with-in the sector is calculated through orthogonal time
slope mathematical function in Vα, Vβ plane. The stationary plane of V and V are calculated for
every Ts and then mapping for the reference vector V* located in sub-triangle is done by
 In Equation (4), Zone-1 integer denotes the portion of the sector among the two lines joining the
vertices divided by distance ‘h’ and inclined at 120◦ with respect to α-axis. In Figure 5b, Zone-1 is
valued as zero, it indicates that the point V* is below the line B and C. The Zone-1 appears that the
point V* lies between the points A and B and D and F. The Zone-2 denotes the part of the sector
Energies 2019, 12, 4332 9 of 24
between the two lines joining the vertices separated by distance ‘h’ and parallel to α-axis. When the
Zone-2 is valued as zero, it indicates that the reference vector tip V* is positioned between the lines A
and D and
the line C and
C and D. E. When the Zone-2
Geometrically, is valued
the Zone-1 andasZone-2
integervalues
one, itare
indicates
acquiredthat
at the point V* liesof
an intersection above
two
the line C and
rectangular D. Geometrically,
regions the Zone-1
(rhombus). Here, the V*and
mayZone-2 values are
be positioned acquired
either at an∆intersection
in triangle 1,2 or ∆ 1,3 . of two
rectangular regions (rhombus). Here, the V* may be positioned either in triangle Δ1,2 or Δ1,3.
F
F
β VL2 [11-1]
Z1=1
Z2=1
∆1,4
∆1,4 [110],[00-1] E
E D
D VM1 [10-1]
VS2
∆1,3
∆1,3 Z1=0
∆1,2 Z2=1
∆1,2 Vz ∆1,1 C
∆1,1 A B VS1 α
A B C [000],[111][-1-1-1] [100],[0-1-1] VL1 [1-1-1]

(a) (b)

Figure 5. (a).
(a). Sector-1
Sector-1with
withZone,
Zone, (b)
(b) sector-1
sector-1 with
with Zone,
Zone, and
and Type-1,
Type-1, Type-2 triangles.

Hence, the
Hence, the V* position in typetype -1-1 triangles
triangles(∆ 1,1 and Δ
(Δ1,1 ∆14
14)) is
is directly identified from Zone-1 Zone-1 and
and
Zone-2 integer
Zone-2 integer values. The Zone-1 and Zone-2
The Zone-1 and Zone-2 receipts zero integer, when the V* is located
integer, when the V* located in a trianglein a triangle
Δ∆1,1
1,1 . TheZone-1
. The Zone-1and andZone-2
Zone-2receipts
receiptsinteger
integer oneone when
when the V* is locatedlocated in triangle∆Δ1,4
in triangle 1,4. However,
However, thethe
Energies
other 2019, 11,
options x FOR
from PEER
the
other options from the Zone-1 REVIEW
Zone-1 and Zone-2 (integers of Zone-1 is zero and Zone-2 is one
one or Zone-1 is
or Zone-1 is
one and
one and Zone-2
Zone-2 is is zero)
zero) are
are not assisting in identifying the Δ ∆1,2 andΔ∆11,3,.3 .
1,2and
Hence,
Hence, the
the Type-2 sub-triangles (∆ (Δ1,2 and Δ1,3.) are calculated in rhombus using diagonal slope
Type-2 sub-triangles 1,2 and ∆1 ,3. ) are calculated in rhombus using diagonal slope
coordinate comparisons. The V* co-ordinates point with respect to rhombus point B can be written as,
coordinate comparisons. The V* co-ordinates point with respect to rhombus point B can be written as,
V = V − int(Zone1) + 0.5 int (Zone2) (6)
Vαi = Vα − int(Zone1) + 0.5 int (Zone2) (6)
V = V + 0.5h (7)
V = V + 0.5h (7)
Figure 6a shows the sub-triangle Δ1,2 βiand Δβ 1,3 rhombus and its slope calculations. The sub-

triangle, anywhere
Figure 6a shows inthe
reference vector
sub-triangle ∆1,2V*and ∆1 ,3 rhombus
is situated by relating
and itsthe slope
slope of B and slope
calculations. of BE. The
The sub-triangle,
slope
anywhere B andinBE can be written
reference as,is situated by relating the slope of B and slope of BE. The slope B and
vector V*
BE can be written as,
V ≤√ √3V (8)
Vβi ≤ 3Vαi (8)
Now, comparing the Equation (8) inequality of the Type-2 sub-triangles (Δ1,2 and Δ1,3.) is
Now, comparing the Equation (8) inequality of the Type-2 sub-triangles (∆1,2 and ∆1 ,3 .) is identified.
identified.

β slope of B of V*= Vαi/Vβi Slope of B and BE

D E
∆1,3 Z2=1 Vβi≤√3Vαi
Z1=0 ∆1,2 Yes No

C
B
Δ1,3 Δ1,2
slope of diagonal B&E = √3
α
(a) (b)

Figure 6. (a).
(a). Sector-1
Sector-1 rhombus
rhombus diagonal
diagonal slope,
slope, (b)
(b) flow
flow chart
chart for
for rhombus
rhombus sub-triangles selection.

3.3. Sub-Triangle Switching On-time Calculations

The flowchart (See Figure 4) shows the complete interpretation of the sub-triangle lookup table
(LUT) identification for Zone-1 and Zone-2. To simplify the switching on-time calculations, all sub-
triangles are further considered into two categories based on their base position either bottom or top.
The first category is called as group-1 triangles (Δ1,1, Δ1,2 and Δ1,4), where it has a base at the bottom.
Similarly, group-1 triangle (Δ1,3) is placed in SVD with the base side at the top. Figure 7 shows the
Energies 2019, 12, 4332 10 of 24

3.3. Sub-Triangle Switching On-time Calculations

The flowchart (See Figure 3) shows the complete interpretation of the sub-triangle lookup table
(LUT) identification for Zone-1 and Zone-2. To simplify the switching on-time calculations, all
sub-triangles are further considered into two categories based on their base position either bottom
or top. The first category is called as group-1 triangles (∆1,1 , ∆1,2 and ∆1 ,4 ), where it has a base at
the bottom. Similarly, group-1 triangle (∆1,3 ) is placed in SVD with the base side at the top. Figure 7
shows the group-1 and group-2 triangle for the calculation of switching on-times. For the group-1
and group-2 triangle valuations, the proposed SVM uses simply the calculation by using Zone-1 and
Energies 2019,
Zone-2 11, x FOR
triangle PEER REVIEW
positions.

β F

Vβi V*

γ ∆1,4 E
D
Vαi α
D F E
β
β β

Vβi ∆1,4
V* E
Vβi V*
D
VS2 VM1 [10-1]
γ ∆1,1 B ∆1,3 γ ∆1,2 C

A α
∆1,2 B
α
Vαi ∆1,1 Vαi
A B VS1 C α

Vαi
E
α γ
D ∆1,3
Vβi
V*

β
B

Figure7.7.Group-1
Figure Group-1triangles 1,11,1, ,∆Δ1,2
triangles(∆(Δ and ∆
1,2 and Δ11,,44)) and
and Group-2
Group-2 (∆
(Δ11,,44)) triangle
triangle representation
representation for
for sector-1.
sector-1.

The group-1 triangle is determined by solving the following Equations (9) and (10),
3.3. Extending to Over Modulation
To move the V* from int(LM
zone1to)OVM
2 region,
+ 2 int (zone2 the
); V* is moved
either to and
∆1,1 , ∆1,3 outside
∆1,4 the hexagonal trajectory. (9)
During this circumstance, the Ma is valued more than 0.9 and the V* moves outside SVD hexagonal
boundary.
Else, Thus, the synthetization of V* in the OVM region is unrealistic (non-linear nature
movement). As a result, to achieve the)2OVM
int(zone1 region
+ 2 int (zone2operation and calculating
) + 1; either∆ 1,2 its switching state(10) on-
times, the traditional approach used trigonometric functions to calculate the OVM voltage vector
Thus the
switching coordinates
state on-times of group-1These
[20,24,30]. triangle and group-2
methods consumetriangles
more can be calculated
mathematical and Vsαi , Vsβi and
asimplementation
0.5 Vsαi , h−Vsβi
complexity. In.addition, these methods are producing higher low frequency harmonics. The proposed
From the
OVM method has individual sub-triangle
a straightforward coordinates,
α, β to
nature the switching
realize switching statesthe
on-time from on-time of each sub-
LM switching time.
triangle
Hence the can non-linearly
be calculatedcan similarly to two-level
be minimized, SVM.helps to avoid the additional lower frequency
which
harmonics. The OVM region is operated in twos zoness as OVM-1 √ (V* is lies from 0.908 to 0.958) and
T1 = Ts (Vαo − Vβo / 3) (11)
OVM-2 (V* is lies from 0.958 to one).
In the OVM-1 region, as shown in Figure T2 =8,Tthere s would be portions of the OVM line cycle, which
s (Vβo /h) (12)
are placed partly within the SVD hexagon and partly outside the hexagon. Hence the two relations
This calculation
are derived can be the
for calculating usedon-time
for n-level MLI
for V* by theregion
circular accumulation of the group
and hexagonal sub-triangles.
region. To differentiate
these two boundaries, the crossover angle (θC) is calculated from the reference vector Ma,

θ = 30° − cos (Π⁄(2√3M )). (13)

Now the V* angle θ fulfills the position θ ≤ θ < Π/3 − θ , the V* remains in hexagonal trajectory,
and another portion follows the circular trajectory (0 ≤ θ <θ to Π/3 − θ ≤ θ < Π/3). Based on the V*
position in SVD, the OVM-1 coordinates (Vα and Vβ) of V* can be calculated from θ and level (n),

V = (√3 (n − 1))⁄(√3 + tan θ), (14)

Energies 2019, 12, 4332 11 of 24

3.4. Extending to Over Modulation

To move the V* from LM to OVM region, the V* is moved to outside the hexagonal trajectory.
During this circumstance, the Ma is valued more than 0.9 and the V* moves outside SVD hexagonal
boundary. Thus, the synthetization of V* in the OVM region is unrealistic (non-linear nature movement).
As a result, to achieve the OVM region operation and calculating its switching state on-times, the
traditional approach used trigonometric functions to calculate the OVM voltage vector switching state
on-times [20,24,30]. These methods consume more mathematical and implementation complexity.
In addition, these methods are producing higher low frequency harmonics. The proposed OVM method
has a straightforward nature to realize switching on-time from the LM switching time. Hence the
non-linearly can be minimized, which helps to avoid the additional lower frequency harmonics.
The OVM region is operated in two zones as OVM-1 (V* is lies from 0.908 to 0.958) and OVM-2 (V* is
lies from 0.958 to one).
In the OVM-1 region, as shown in Figure 8, there would be portions of the OVM line cycle, which
are placed partly within the SVD hexagon and partly outside the hexagon. Hence the two relations are
derived for calculating the on-time for V* circular region and hexagonal region. To differentiate these
two boundaries, the crossover angle (θC ) is calculated from the reference vector Ma ,
√
θc = 30◦ − cos−1 (Π/(2 3Ma )). (13)

Now the V* angle θ fulfills the position θC ≤ θ < Π/3 − θC , the V* remains in hexagonal trajectory,
and another portion follows the circular trajectory (0 ≤ θ <θC to Π/3 − θC ≤ θ < Π/3). Based on the V*
position in SVD, the OVM-1 coordinates (Vα and Vβ ) of V* can be calculated from θ and level (n),
√ √
Vα = ( 3(n − 1))/( 3 + tan θ), (14)
√ √
Vβ = ( 3(n − 1) tan θ)/( 3 + tan θ). (15)

From the Vα and Vβ , the Vsαo and Vsβo are calculated for deriving modified switching on-time,
√
T1 = Ts (Vsαo − Vsβo / 3); To = 0; T2 = Ts . (16)

To realize the circular trajectory and hexagonal trajectory switching on-times, the gain factor (Gt )
can be calculated from the OVM-1 maximum boundary and its actual Ma values. The maximum
volt-seconds loss in OVM-1 region is proportional to (0.9535 − 0.907). Hence, the Gt can be obtained
from LM Ma as,
Gt = ( OVM − 1 − 0.907)/(0.9535 − 0.907). (17)

Adding and subtracting the Gt with T0 , T1 and T2 , the circular trajectory and hexagonal trajectory
switching on-time can be calculated by modifying the V*.
Now from Equations (11), (12), and (17), the hexagonal trajectory switching on-time is derived as,
√
T1 OVM−1 HT = Ts (Vsαo − Vsβo / 3) + 0.5G2t To , (18)

T2 OVM−1 HT = Ts (Vsβo /h) + 0.5G2t To , (19)

To OVM−1 HT = Ts − T1 OVM−1 HT − T2 OVM−1 HT . (20)

Similarly, the circular trajectory switching on-time is derived as,

√
T1 OVM−1 CT = Ts (Vsαo − Vsβo / 3) − 0.5G2t T1 , (21)

T2 OVM−1 CT = Ts (Vsβo /h) − 0.5G2t T2 , (22)

 T =T −T − T . (20)
Similarly, the circular trajectory switching on-time is derived as,
T = T (V − V ⁄√3) − 0.5G T , (21)
Energies 2019, 12, 4332 12 of 24
T = T (V ⁄h) − 0.5G T , (22)
T =T −T − T . (23)
To OVM−1 CT = Ts − T1 OVM−1 HT − T2 OVM−1 HT . (23)
When the V* modulation index Ma is more than 0.9535, then the V* is entered into OVM-2 region.
When the V* modulation index M is more than 0.9535, then the V* is entered into OVM-2 region.
During this time the V* is allowed onlya in the hexagonal trajectory (beyond the OVM-1 HT), and only
During this time the V* is allowed only in the hexagonal trajectory (beyond the OVM-1 HT), and only
six LVs are needed to operate. Hence, the holding angle (θ ) is derived using a similar strategy [9] to
six LVs are needed to operate. Hence, the holding angle (θ ) is derived using a similar strategy [9] to
keep the V* at one of the large vectors. The relations 0 ≤ θh< θ and Π/3 − θ ≤ θ < θ help to find one
keep the V* at one of the large vectors. The relations 0 ≤ θ < θh and Π/3 − θh ≤ θ < θh help to find
of the LV in the particular sector with changing V* position. The on-time equations of OVM-2 are
one of the LV in the particular sector with changing V* position. The on-time equations of OVM-2 are
obtained as,
obtained as,
0 0≤ ≤
θθ<<
θhθ; T; 1T==TsT, ,TT2 =
=TTo =
= 0,
0, (24)
(24)
Π⁄3−−θhθ ≤≤θ θ<<Π/3
Π/3 Π⁄3; ;T2T ==TTs , ,TT1 =
= TTo =
= 0.
0. (25)
(25)
The
The proposed LM and
proposed LM and OVM
OVM do
do not
not change
change V*
V* position.
position. Hence,
Hence, it
it allows
allows simple
simple implementations.
implementations.

β 6 5
Overmodulation OVM-1
Boundary 4 CT region

Linear modulation
∆ 13 OVM-1
Boundary HT region

∆ 12
V*
3
∆ 11 2 OVM-2
∆ 14
region
0 θ θC θH 1 α
Figure 8. OVM boundary for proposed three-level SVM.
Figure 8. OVM boundary for proposed three-level SVM.
4. MATLAB-Simulink Implementation of Three-level SVM
4. MATLAB-Simulink
The proposed MLI Implementation of Three-level
SVM design is established SVM
using MATLAB 13.b Simulink with five subsystems
that are
Theconnected
proposedthrough In anddesign
MLI SVM Out Xilinx SG that helps
is established to implement
using MATLABthe MLISimulink
13.b SVM directly
withfrom
five
MATLAB-Simulink (.mdl) file to target FPGA. Figure 9 illustrates the detailed MATLAB-Simulink
subsystems that are connected through In and Out Xilinx SG that helps to implement the MLI SVM
design flow
directly of proposed
from MLI SVM. (.mdl) file to target FPGA. Figure 9 illustrates the detailed
MATLAB-Simulink
MATLAB-Simulink design flow of proposed MLI SVM.
1) The first block is the “Clarke’s transformation”, in which the three-phase reference rotating frame
are converted into Vα , Vβ .
2) The 2nd block named ‘Sector and γ identifier’ block holds four sub-systems namely reference
vector Ma , θ, sector and γ.
3) The next block is calculating the local vector reference frame ( Vsα0 and Vsβ0 ) and finding the
sub-triangle. Then the switching on-times T1 , T2 , and T0 are calculated (based on two-level SVM).
4) The fouth subsystem is calculating the LM and OVM boundary based on the reference vector Ma .
The subsystem receives the sub-triangles, Vsα0 and Vsβ0 to sample switching pulse period for the
Ts . The switching events of all 27 switching states are stored in LUT.
5) Finally, based on the sector number, sub-triangle number, and Ma boundary, the switching
on-times are calculated and mapped into the corresponding switching states.

The performance of the MLI SVM for 0< Ma ≤0.99 is simulated on a three-level NPC-MLI drive
with 460V DC-link, two 470 µF DC-link capacitors, and 10 kHz switching frequency. The 2.45 kW,
1440 rpm, four poles, and 50 Hz induction motor is used as a load. Figure 10 shows the inverter line
voltage (Vuv ) waveform for LM, OVM-1 and OVM-2 operations. Initially, the simulation studies are
conducted for Ma = 0.5. Here the line voltage (Vuv ) is measured as a 2-level output, because only
Energies 2019, 12, 4332 13 of 24

the SVs and ZVs have participated in the switching sequence. Hence, the Vuv resulted in 2-level
output was 147.8 V with THD value of 13.06 %. Next, the same simulation study is extended for the
higher modulation ranges (more than 0.5) and resulting in increased voltage magnitude. When the
inverter is operated at maximum LM range of 0.907, the Vuv resulted is 268.4 V, as shown in Figure 10.
As expected, the fundamental voltage is increasing linearly by increasing Ma . Here the line voltage at
= 0.950
MaEnergies and Ma =PEER
2019, 11, x FOR
0.990 is observed as 282 V and 295 V, respectively.
REVIEW

Energies 2019, 11, x FORFigure 9. MLI SVM MATLAB-Simulink implementation flow chart.
PEER 9.
REVIEW
Figure MLI SVM MATLAB-Simulink implementation flow chart.

1) The first block isAt

the
LM“Clarke’s
for ma=0.9transformation”,
At OVM forinmwhich
a=0.95 the three-phase reference
At OVM for ma=0.99 rotating frame
are converted into Vα, Vβ.
2) The 2nd block named ʽ Sector and γ identifier’ block holds four sub-systems namely reference
Vuv
vector Ma, θ, sector and γ.
[150V/Div]
3) The next block is calculating the local vector reference frame ( V and V ) and finding the sub-
triangle. Then the switching on-times T1, T2, and T0 are calculated (based on two-level SVM).
4) The fouth subsystem is calculating the LM and OVM boundary based on the reference vector Ma.
Theiusubsystem receives the sub-triangles, V and V to sample switching pulse period for the Ts.
[5A/Div]
The switching events of all 27 switching states are stored in LUT.
5) Finally, based on the sector number, sub-triangle number, and Ma boundary, the switching on-
times are calculated and mapped into the corresponding switching states. [0.025s/Div]

The performance of the MLI SVM for 0˂ Ma ≤0.99 is simulated on a three-level NPC-MLI drive
with 460V VuvDC-link, two 470 μF DC-link capacitors, and 10 kHz switching frequency. The 2.45 kW,
1440 rpm, four poles, and 50 Hz induction motor is usedV
[150V/Div] asuva load. Figure 10 shows the inverter line
[150V/Div]
voltage (Vuv) waveform for LM, OVM-1 and OVM-2 operations. Initially, the simulation studies are
conducted for Ma = 0.5. Here the line voltage (Vuv) is measured as a 2-level output, because only the
SVs and ZVs have participated in the switching sequence. Hence, the Vuv resulted in 2-level output
was 147.8 V with THD Figurevalue
Figure ofSimulation
10. 10. 13.06 %.
Simulation Next,
result
result the
for
for same simulation
modulation
modulation range
range(0.9 study
(0.9˂ < aM
M is extended for the higher
≤0.99).
a ≤ 0.99).
modulation ranges (more than 0.5) and resulting in increased voltage magnitude. When the inverter
is 5. FPGA Collaborated
operated at maximumExperimentation
LM range of 0.907, Setupthe of V
Three-Level
uv resulted MLIis 268.4 V, as shown in Figure 10. As
expected, the fundamental voltage is increasing linearly by increasing
The experimental setup diagram and FPGA are collaborated Three-phase Ma. Here the line voltage
three-level NPC MLIat Ma
= 0.950 and M a = 0.990 is observed as 282 V and 295 V, respectively.
is shown in Figure 11. The NPC-MLI is designed with three integrated surface-mounted
SK100MLIO66T-SEMIKRON four IGBT modules.
Energies 2019, 12, 4332 14 of 24

5. FPGA Collaborated Experimentation Setup of Three-Level MLI

The experimental setup diagram and FPGA are collaborated Three-phase three-level NPC
MLI is shown in Figure 11. The NPC-MLI is designed with three integrated surface-mounted
Energies 2019, 11, x FOR PEER REVIEW
SK100MLIO66T-SEMIKRON four IGBT modules.

JTAG FPGA Board

Gate Driver DSO

Three-level Z- Source NPC-MLI
Su1 Sv1 Sw1
2hp Induction
C1 motor
PC with Xilinx ISE - Dw1
AC to DC
Du1
SG tool + MATLAB
Rectifier N

C2
Du2 Dw
DC-link voltage 2
Su4 Sv4 Sw4
Sensor
Board
VDC Protection circuits

SK100 MLI 066 T NPC-MLI for phase-u

Su1
D1 Su2
D2 Su3
Su4

Three-phase three-level NPC-MLI prototype

SPARTAN-III-3A FPGA

NPC-MLI Modules

DC -link Capacitors,
C1 and C2

Driver Circuit module for

one leg IGBTs 3 Phase Induction Motor

Figure 11.
Figure Three-levelMLI
11. Three-level MLIexperimentation
experimentation with
with SPARTAN-III-3A
SPARTAN-III-3A XC3SD1800A-FG676
XC3SD1800A-FG676 DSP-FPGA.
DSP-FPGA.

Two 100 μF, 1000 V rating DC-link capacitors are used for providing DC-link voltage of the MLI.
The switching module used HCPL4506 opto-isolator to provide the isolation between the FPGA
controller, and IGBT. The Xilinx family SPARTAN-III-3A XC3SD1800A-FG676 DSP-FPGA controller
is used to implement and generate the proposed SVM. The 2.45 kW, 1440 r/min, 50 Hz, 4-pole three-
phase squirrel-cage induction motor (SCIM) drive is used as a load. The YOKOGAWA spectrum
 C1 and C2

Driver Circuit module for

Energies 2019, 12, 4332 3 Phase Induction Motor 15 of 24
one leg IGBTs

Two 100 µF, 1000 V rating DC-link capacitors are used for providing DC-link voltage of the
MLI. The switching module used HCPL4506 opto-isolator to provide the isolation between the FPGA
controller, and IGBT. The Xilinx family SPARTAN-III-3A XC3SD1800A-FG676 DSP-FPGA controller is
used to implement and generate the proposed SVM. The 2.45 kW, 1440 r/min, 50 Hz, 4-pole three-phase
squirrel-cage induction motor (SCIM) drive is used as a load. The YOKOGAWA spectrum analyzer is
used Figure
for capturing the experimental
11. Three-level results. with SPARTAN-III-3A XC3SD1800A-FG676 DSP-FPGA.
MLI experimentation

6. MATLAB-Simulink built FPGA Habitat for Hardware Implementation

Two 100 μF, 1000 V rating DC-link capacitors are used for providing DC-link voltage of the MLI.
The switching module used support
The MATLAB-Simulink HCPL4506 opto-isolator
Xilinx ISE project to providesystem
navigator the isolation
generatorbetween theisFPGA
(SG) tool used
controller, and IGBT.
for the proposed SVMThe Xilinx family SPARTAN-III-3A
implementations XC3SD1800A-FG676
as it allows the minimization of the timeDSP-FPGA controller
spent for design and
is used
cost to implement and generate the proposed SVM. The 2.45 kW, 1440 r/min, 50 Hz, 4-pole three-
of implementation.
phaseThe
squirrel-cage
architectureinduction motor (SCIM)
of the proposed SVM FPGA driveimplementation
is used as a load. The YOKOGAWA
is shown spectrum
in Figure 12. The FPGA
analyzer is used
core contains thefor
twocapturing the experimental
main modules: results. unit; and (2) switching and its mapping unit,
(1) The processing
as shown in Figure 13. These modules can perform in parallel that helps to minimize the processing
6. MATLAB-Simulink
time. The processing unit builtcomprises
FPGA Habitat for Hardware
functional blocks to Implementation
calculate the V*, sector, sub-triangle, αβ
coordinates for LM and OVM trajectory, and logical
The MATLAB-Simulink support Xilinx ISE project navigator routes. The mapping unit consists
system generator (SG)oftool
switching
is used
vectors
for for the corresponding
the proposed sub-triangles.
SVM implementations as it The switching
allows vector-mapping
the minimization unit uses
of the time spentmemory
for design(LUT).
and
It maps the pre-stored
cost of implementation. switching sequence for the MLI based on sector, sub-triangle.

clk Dead
Decoder and Modulation time
its Index
interfacing Calculator Switching
frequency

3-2 Axis
ST Period
converter SVD
Trajectory

Space
Vd and Vq Sector Vector
Register Identifier PWM
Switching Generator
Switching pulse of Sa1 – Sc4

on-time Switching
and states and
Trajectory selection
Sector Sub-trangle unit
magnitude Identifier
and angle
Register

Energies 2019, 11, x FOR PEER REVIEW

Figure 12. Proposed MLI SVM FPGA core structure.

Processing Unit Switching mapping unit

Si

Vref, Sector and sub-

triangle ΔSi,j

on-time
On-time duty cycle

Figure 13. Processing

Processing unit
unit and mapping unit sharing.

The architecture
The core also considers some key
of the proposed SVM design
FPGAmeasures for improving
implementation computation
is shown accuracy
in Figure 12. and
The FPGA
simplifying
core containshardware design
the two main and the
modules: (1)fixed-point arithmetic
The processing unit(2)
unit; and isswitching
adopted for
andimplementing the
its mapping unit,
calculations. The IP core is designed to operate at 20MHz clock frequency, and high
as shown in Figure 13. These modules can perform in parallel that helps to minimize the processingswitching
time. The processing unit comprises functional blocks to calculate the V*, sector, sub-triangle, αβ
coordinates for LM and OVM trajectory, and logical routes. The mapping unit consists of switching
vectors for the corresponding sub-triangles. The switching vector-mapping unit uses memory (LUT).
It maps the pre-stored switching sequence for the MLI based on sector, sub-triangle.
The core also considers some key design measures for improving computation accuracy and
simplifying hardware design and the fixed-point arithmetic unit is adopted for implementing the
Energies 2019, 12, 4332 16 of 24

frequency, as well as the td , is adjustable. The architecture of the proposed SVM sub-blocks is described,
as follows:

1. 3/2 axis converter block: It performs the abc to d-q conversion, which generates the V*and
angle (θ).
2. Ma block: Depending upon the V* requirement, the Ma value of the inverter can be given through
the Ma block.
3. Switching period block: It holds the sampling frequency for the inverter switches.
4. Sector identification block: This block finds the V* location based on the angle (θ) and
V* magnitude.
5. Triangle identifier block: The block computes V* sub-triangle location.
6. Trajectory identifier block: This block measures the trajectory identifier (LM, OVM boundary)
and V* location based on the Ma values. It also calculates θC and θH angles for OVM operation.
7. On-time calculation block: This block calculates the respective switching state on-times based
on two-level SVM calculations. This unit uses the LUTs to store the switching states and the
switching sequences. Lastly, SVM generator unit generates the pulses to the 3-level NPC-MLI
after inserting the dead time (td ).
8. Switching state unit: It holds the 27-switching event.
9. Dead time register block: Holds the timer to add or reduce the td .
10. SVM Generating Unit: This block produces the pulses to the NPC-MLI after inserting the td .

To simplify the interface with the processor, commands to these registers are routed through a
decoder and interface circuit. The clock is acting as a base time for PWM generator and is operated at
100MHz. The overflow flag from PWM generator unit indicates the value of PWM counter when it
reaches the maximum count, which can be used to trigger events for the inverter.

6.1. Implementation of the Proposed MLI SVM Scheme in FPGA

The XSG FPGA environment implementation is divided into five stages as follows: MATLAB
code generation through XSG, VHDL code generation and its simulation, register transfer level (RTL)
file and bit file generation, synthesis and download into target FPGA. Once the RTL file is generated,
the proposed SMV architecture RTL view (shown in Figure 14) and off-line simulation is done to
view the generated inverter pulses using ModelSim 5.8e. Figure 15 shows the ModelSim simulation
results for the proposed MLI SVM. It ensures the desired pulse pattern, td values. After successful
synthesis, the device utilization and power utilization report is generated. It provides the number
of logical blocks, LUTs and FFs to be used in architecture. The proposed MLI SVM uses only 3.7%
LUT memory space in the FPGA, since it uses simple 2-level SVM, and hence, does not require any
additional calculations for calculating the switching on-time. It also minimizes the processing time
for LM and OVM operations. Figure 16a shows the internal structure based on the described SVM
implementation design. After RTL synthesis, the net list is saved as an NGC file. Afterwards, the
JTAG serial mode (“IEEE Standard 1149.1") configuration interface card is used to download the code
to the Target FPGA SPARTAN-III-3A XC3SD1800A-FG676. The JTAG configuration is through the
independent boundary scan selection. Then the regenerated bit file is generated. Finally, the developed
RTL is converted to bit stream format, and then the UCF is written for pin assignment for the mapping
process. Mapping is done to fit the design into the available resource of the target FPGA processor.
Finally, placing the code in target FPGA is done.
(“IEEESPARTAN-III-3A
FPGA Standard 1149.1")XC3SD1800A-FG676.
configuration interface Thecard
JTAG is configuration
used to download the code
is through the to the Target
independent
FPGA SPARTAN-III-3A
boundary scan selection. XC3SD1800A-FG676.
Then the regeneratedThe bit JTAG
file is configuration is through
generated. Finally, the independent
the developed RTL is
boundary to
converted scanbitselection. Then the
stream format, andregenerated
then the UCF bit is
filewritten
is generated.
for pinFinally,
assignmentthe developed RTL is
for the mapping
converted
process. to bit stream
Mapping is doneformat, and
to fit the then into
design the UCF is written
the available for pinofassignment
resource for theprocessor.
the target FPGA mapping
process.placing
Finally, Mapping the iscode
done
in to fit the
target design
FPGA is into the available resource of the target FPGA processor.
done.
Energies 2019, 12, 4332 17 of 24
Finally, placing the code in target FPGA is done.

Figure 14. Register transfer level (RTL) view proposed MLI SVM core.
Register transfer
Figure 14. Register transfer level
level (RTL)
(RTL) view proposed MLI SVM core.

Energies 2019, 11, x FOR PEER REVIEW

using UCF based on reduction of the power losses. The implementation consumes only 0.13 W power
utilization for one cyclic operation of pulse generation.
Due to the simplification of sub-triangle calculations and OVM-1 switching mapping, the overall
device utilization of the proposed SVM implementation becomes 5.88%, which is less than the earlier
implementations [14,23,41,46]. The simplified calculation to find the rhombus sub-triangles selection
and OVM-1 on-time calculations are the primary reasons for the memory reduction (around 0.17%),
while considering the implementation
Figure 15. ModelSim reported
simulation results; in [23].(SThe
12-pulses –Sadditional reductions
) of proposed are achieved
MLI SVM for f = 10by way
kHz,
Figure 15.
of reducing the ModelSim
LUT simulation
usage for results;by
operation 12-pulses
repeating –S1u4w
(S1uswitching4w proposed
) of states. MLI SVM for fs = 10skHz, dead
dead time = 6 µs.
Figure
time = 615.
μs.ModelSim simulation results; 12-pulses (S1u–S4w) of proposed MLI SVM for fs = 10 kHz, dead
time = 6 μs.
6.2. MLI SVM FPGA Implementation Results
6.2. MLI SVM FPGA Implementation Results
There are three types of floor views that are generated for the SVM IC, which are overall floor
view There are utilization,
of device three typesinput
of floor
portviews that
assign are and
view, generated
outputfor the
port SVMview.
assign IC, which
Fromare overall
Figure 16a,floor
it is
view of device
observed utilization,
that the proposedinput
codeport assignvery
occupies view,less
andresource/area.
output port assign
Figureview. From Figure
16b shows 16a,and
the input it is
observed that the proposed code occupies very less resource/area. Figure 16b shows
output port of the proposed implementation. The proposed PWM design I/O’s are mapped properly the input and
output port of the proposed implementation. The proposed PWM design I/O’s are mapped properly

(a) (b)
16.(a)(a)Device
Figure16.
Figure Device area
area utilization,
utilization, (b)(b) input
input andand output
output port
port view
view forfor
thethe implemented
implemented SVM.
SVM.

6.2. MLI SVM FPGA Implementation Results

The processing time of the proposed implementation for LM OVM-1, and OVM-2 are calculated
using [38],
Thereandarethe values
three typesareof13.017
floor μs, 14.561
views thatμs,areand 15.532 μs,
generated forrespectively.
the SVM IC, From
which theare
results,
overallit can
floor
be understood that the proposed FPGA implementations are taking the same time
view of device utilization, input port assign view, and output port assign view. From Figure 16a, it is for all LM values
asobserved
13.017 μs,that
since
thesub-system
proposed code calculation
occupiesis same
veryforlessallresource/area.
the range of LM from16b
Figure 0.5 shows
to 0.907.the
However,
input and
during
outputover
port ofmodulation
the proposed operations, the processing
implementation. time for
The proposed PWM thedesign
proposed
I/O’s implementation
are mapped properly is
increased. The increase in time is because of G calculation for the new on-times.
using UCF based on reduction of the power losses. The implementation consumes only 0.13 W power
t Nevertheless, when
compared
utilizationtofor
theone
early implementations,
cyclic operation of pulse the time taken for OVM is less for the proposed method [23],
generation.
and it Due
is expected while implementing
to the simplification with other
of sub-triangle family FPGAs.
calculations and OVM-1 Similarly, considering
switching mapping, thethe
device
overall
utilization (memory occupied) on FPGA for the proposed implementations, it
device utilization of the proposed SVM implementation becomes 5.88%, which is less than the earlier is considerably lesser.
From the above analysis and results, it is clear that the proposed MLI SVM algorithm and its Sparten-
3 FPGA implementation improved in terms of their owning mathematical complexity and
implementation. Hence, due to this reduced mathematical burden, less device utilization and
processing time, the proposed implementations fit to be considered as an IP core that can be
incorporated into a System On-Chip with other IP cores and it can greatly reduce the area of a PCB
Energies 2019, 12, 4332 18 of 24

implementations [14,23,40,45]. The simplified calculation to find the rhombus sub-triangles selection
and OVM-1 on-time calculations are the primary reasons for the memory reduction (around 0.17%),
while considering the implementation reported in [23]. The additional reductions are achieved by way
of reducing the LUT usage for operation by repeating switching states.
The processing time of the proposed implementation for LM OVM-1, and OVM-2 are calculated
using [37], and the values are 13.017 µs, 14.561 µs, and 15.532 µs, respectively. From the results, it can
be understood that the proposed FPGA implementations are taking the same time for all LM values as
13.017 µs, since sub-system calculation is same for all the range of LM from 0.5 to 0.907. However,
during over modulation operations, the processing time for the proposed implementation is increased.
The increase in time is because of Gt calculation for the new on-times. Nevertheless, when compared
to the early implementations, the time taken for OVM is less for the proposed method [23], and it is
expected while implementing with other family FPGAs. Similarly, considering the device utilization
(memory occupied) on FPGA for the proposed implementations, it is considerably lesser. From the
above analysis and results, it is clear that the proposed MLI SVM algorithm and its Sparten-3 FPGA
implementation improved in terms of their owning mathematical complexity and implementation.
Hence, due to this reduced mathematical burden, less device utilization and processing time, the
proposed implementations fit to be considered as an IP core that can be incorporated into a System
On-Chip with other IP cores and it can greatly reduce the area of a PCB and improve the immunity to
interferences for the power converters design.

7. Experimental Results and Analysis

In order to validate the proposed MLI SVM FPGA implementation, the experimentation study is
conducted for 2.3 kW three-phase induction motor supplied from three-phase three-level NPC-MLI.
The DC-link voltage of the NPC-MLI is maintained at 560 V through an uncontrolled rectifier.
The two 100 µF DC-link capacitors C1 and C2 are connected with DC-link to clamp the voltage.
The switching frequency of 10 kHz and dead time of 6µsec is used between two complementary
switches. The experiment study is performed with modulation index value from 0.7 to maximum
over modulation range (Ma = 0.99). During the study, the speed of the motor is recorded using
digital tacho-generator.
Figure 17a–d depicts the experimental results of MLI line-voltage (Vuv ) and corresponding current
(Iu ) for Ma = 0.7, Ma = 0.9, Ma = 0.95, and Ma = 0.99, respectively. In the LM region, the inverter
output voltage is obtained as 205.2 V and 262.4 V for Ma = 0.7 and Ma = 0.9, respectively. However,
while increasing the Ma from LM to OVM, the fundamental voltage is increased linearly. The Vab for
Ma = 0.7 and Ma = 0.9 is obtained as 280.3 V and 292.5 V, respectively. From the results, it can be seen
that the inverter voltage and current waveforms are changing based on the modulation index value.
However, the voltage and current waveforms are smooth in all the range of modulation indices.
This demonstrates that the proposed SVM is working with full control degree of freedom in the
linear and over modulation region. Figure 18a–d shows the voltage and current harmonics spectrum.
The voltage and its corresponding current harmonics in the LM are lesser when compared with those
in the OVM regions. The line voltage percentage THD is observed as 10.2%, 12.9%, and 13.5% for
Ma = 0.9, Ma = 0.95 and Ma = 0.99, respectively. This increase is due to the non-linearity in the switching
on-times in the OVM region operation. Similarly, the current percentage THD in OVM is higher than
that in LM. When compared with the other multicarrier and selective harmonics elimination PWM
methods, the proposed SVM has lower current and voltage THD in both LM and OVM. In addition,
while changing the inverter operation from one region to another region, the voltage and current
waveforms are smooth, and there are no abrupt changes.
Energies 2019, 12, 4332 19 of 24
Energies 2019, 11, x FOR PEER REVIEW

Vuv[V]

iu[A]

time
(a)

Vuv[V]

iu[A]
time

(b)

Vuv[V]

iu[A]

time

(c)

Vuv[V]

iu[A]

time
(d)

Figure 17. Line voltage (Vuv ) and Phase current (Iu ) waveform; (a) Vuv for Ma = 0.7, (b) Vuv for
Ma = 0.9, (c) Vuv for Ma = 0.95, (d) Vuv for Ma = 0.99.
Energies 2019, 11, x FOR PEER REVIEW

Figure
Energies 17.4332
2019, 12, Line voltage (Vuv) and Phase current (Iu) waveform; (a) Vuv for Ma = 0.7, (b) Vuv for Ma = 0.9,
20 of 24
(c) Vuv for Ma = 0.95, (d) Vuv for Ma = 0.99.

Vuv = 209.3V THDVuv = 9.5% Vuv = 267.5V THDVuv = 10.2%

THD I u = 1.2% THD Iu = 1.5%

Harmonics order
Harmonics order

(a) (b)
Vuv = 278.4V Vuv = 295.2V
THDVuv = 12.9% THDVuv = 13.5%

THD I u = 2.9% THD I u = 3.5%

Harmonics order
Harmonics order

(c) (d)

Figure 18. Line

Line voltage
voltage harmonics
harmonicsspectrum;
spectrum;(a) Ma a= =
(a)atatM 0.7, (b)(b)
0.7, atat
MM = 0.9,
a =a0.9, (c) (c)
at M a = 0.958,
= 0.958,
ata M (d) at
(d)Mat
a=

Ma = 0.997.
0.997.

The induction
However, motor speed
the voltage variations
and current for the modulation
waveforms are smoothindex in allrange fromof
the range a = 0.7 to Maindices.
Mmodulation = 0.99
are measured and plotted in Figure 19. From the results, it can be seen that the
This demonstrates that the proposed SVM is working with full control degree of freedom in the linearmotor speed changes
in linear
and over with the SVM
modulation modulation
region. Figure index. This illustrates
18a–d shows the voltage that
andthecurrent
proposed SVM can
harmonics be directly
spectrum. The
employed
voltage andtoitsopen-loop drives.
corresponding In closed-loop
current harmonicsoperation,
in the LM depending
are lesser whenon the control requirement,
compared with those in
the proposed
OVM
Energies 2019, 11,SVM
regions. voltage
The
x FOR line
PEER reference
voltage
REVIEW magnitude
percentage THD andisfrequency
observed as can10.2%,
be changed
12.9%, easily without
and 13.5% any
for M a =

additional
0.9, Ma = 0.95mathematical
and Ma = 0.99,calculations.
respectively. This increase is due to the non-linearity in the switching on-
times in the OVM region operation. Similarly, the current percentage THD in OVM is higher than that
Nr = 996 rpm Nr = 1076 rpm
in LM. When compared with the other multicarrier and selective harmonics Nr = 1118 elimination PWM
1200 rpm
methods, the proposed SVM has lower current and voltage THD in both LM and OVM. In addition,
Motor Speed (Nr)

while changing the inverter 1100 operation from one region to another region, the voltage and current
waveforms are smooth, and there are Nrno
= 845 rpm changes.
abrupt
900
The induction motor speed variations for the modulation index range from Ma = 0.7 to Ma = 0.99
are measured and plotted 600 in Figure 19. From the results, it can be seen that the motor speed changes
in linear with the SVM modulation index. This illustrates that the proposed SVM can be directly
employed to open-loop300 drives. In closed-loop operation, depending Maon the control requirement, the
proposed SVM voltage reference magnitude and frequency can be changed easily without any
0.25 0.5 0.75 0.9 0.95 0.99
additional mathematical calculations. LM OVM

Figure 19. Motor speed response while changing modulation index.

Figure 19. Motor speed response while changing modulation index.

8. Conclusions
In this paper, the detailed theoretical analytical study on MLI SVM and its digital implementation
practices are explained. In addition to the previous method of SVM, the paper has also proposed a
simplified mathematical approach to find out the MLI SVD sub-triangles, switching on-time
Energies 2019, 12, 4332 21 of 24

8. Conclusions
In this paper, the detailed theoretical analytical study on MLI SVM and its digital implementation
practices are explained. In addition to the previous method of SVM, the paper has also proposed a
simplified mathematical approach to find out the MLI SVD sub-triangles, switching on-time calculation
in both linear and over modulation. The proposed three-level MLI-SVM is exhibited based on two-level
SVM without changing the reference vector position, unlike the traditional approaches. Hence, it can
be easily prolonged with additional LUTs for any n-level inverter without any significant increase in
computations. The proposed MLI SVM is comprehensively analyzed and validated for implementation
in Xilinx family SPARTAN-III-3A XC3SD1800A-FG676 FPGA. The mathematical procedure involved
in the proposed MLI SVM is reduced compared to the early attempts; hence, the device utilization
and processing time are considerably reduced. The MATLAB–Simulink SG based simulation and
SPARTAN-III-3A XC3SD1800A-FG676 FPGA implementation are performed to validate the proposed
SVM with 2 kW three-phase three-level NPC MLI fed induction motor drive system. The presented
results are confirming the performance of the MLI SVM at different modulation depths of the NPC
MLI. The proposed implementation fits to be considered as an IP core that can be incorporated into a
System On-Chip with other IP cores.

Author Contributions: All authors are involved in developing the concept, simulation and experimental validation
and to make the article error free technical outcome for the set investigation work.
Funding: This research received no external funding.
Conflicts of Interest: The authors declare no conflict of interest.

Nomenclature
V* Reference vector
Vα ,Vβ Voltage vectors stationary reference frame
δVS2 Duty cycle of SV
δVM2 Duty cycle of MV
δVL2 Duty cycle of LV
∆i,j Sub-triangle within the sectors
θ Angle of the reference vector
γ Sector angle
h Vertices height
Vsαo , Vsβo Individual Sub-triangle α, β coordinates
θC Crossover angle
θh Holding angle
PWM Pulse Width Modulation
MLI Multilevel Inverter
SVM Space Vector Modulation
SVD Space Vector Diagram
LM Linear Modulation
OVM Over Modulation
NPC Neutral-Point Clamped
ZV Zero Vector
SV Small Vector
MV Medium Vector
LV Large Vector
IP Intellectual Property
HT Hexagonal Trajectory
CT Circular Trajectory
THD Total Harmonic Distortion
IGBT Insulated-Gate Bipolar Transistor
SCIM Squirrel-Cage Induction Motor
Energies 2019, 12, 4332 22 of 24

SG System Generator
RTL Register transfer level
LUT Lookup Table

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