A B C D E

PCI-Express 4X Gen2
SkyLake

l
PCIE , Port 9~12 Memory BUS (DDRIII)
1DPC DDR3L-SO-DIMM X2
BANK 0, 1, 2, 3

a
Exo Pro 2G DDR3 S3
1.35V DDRIIIL 1333/1600 MT/s Page 22~23
1 Meso XT 2G DDR3 S3 1

it
UP TO 16G
VRAM 256M*16 *4
USB 2.0 , port 7
Intel USB 2.0 , Port 4
Page 24~33
SkyLake-U 2+2 type
Processor

n
eDP , Port 1 USB 2.0 , Port 1&2
eDP Conn. USB 2.0 x 3 USB Left One-Link
Page 42 BGA1356 5V 480MHz
40mm*24mm USB 3.0 Port 4
USB3.0 redriver X2 USB 3.0 Port 1&2

e
USB 3.0 X 3 USB 2.0 Port 1&2 USB 2.0 Port 4
DDI , CH2 PS8713B
5V 5GT/s Page 44 Page 36~38
HDMI Conn. HDMI_redriver Page 45
Page 50 Page 49 USB 3.0 Port 1&2
Page 43

d
USB3.0 redriver
DDI , CH1 PS8713B

if
One Link(DP port) DP_redriver
Page 38 Page 37 PCIe Gen1 , Port 3 USB 3.0 Port 4
2
NGFF Card WLAN page 36 2

+ USB 2.0 , Port 6 USB 2.0 Port 6

PCIe Port 3
page 56
USB 3.0 , Port 3

n
USB 2.0 x 4
Intel USB charger
WGI219V Non Vpro PCIe Gen1, Port4 USB Right
WGI219LM Vpro (AOU)
USB 2.0 Port 3

o
RJ45 Conn. TPS2546RTER USB 3.0 Port 3
Page 52
USB 2.0 Port 3
PCIe , port 4 Page 51
Intel PCH-LP Page 57 Sub/B Page 57

Int. Camera

C
Realtek JCARD Conn. PCIe Gen1 , Port 6
USB 2.0 Port 7
RTS5227S Page 42
PCIe port 6
SD/MMC/XD Page 57
Touch Panel
Sub/B Page 58 USB 2.0 Port 5
3
Finger printer Page 55 3
USB 2.0 Port 9
SPI ROM SPI BUS

C
Page 54
8M+4M Page 21 3.3V 33MHz
Page 5~21 SATA Gen3 , Port 0
TPM SATA HDD
NPCT650LAAYX
Page 60
SATA Port 0
page 41
LPC BUS

F
3.3V 33MHz
HD Audio
3.3V 24MHz

EC Codec SP_OUTR/L
Mirror function SPK Conn.

C
ITE IT8586EX CX11852-11Z
Page 40
Page 39
Page 66

HP_R/L_JACK

L
MIC_CLK/MIC_DATA

4 G-Sensor Touch Pad Thermal Sensor Int. MIC Conn. Ext. MIC Conn. 4

Track Point Int.KBD (JLCD Conn.) HP Conn.

LIS3DHTR F75303M Page 42 Page 57
Page 60 Page 53 Page 55 Page 59 Sub/B

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 BLOCK DIAGRAM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Monday, August 10, 2015 Sheet 2 of 83
A B C D E
 A B C D E

SIGNAL
Voltage Rails ( O --> Means ON , X --> Means OFF ) STATE SLP_A# SLP_S3# SLP_S4# SLP_S5# EC_ON SUSP#

l
S0 HIGH HIGH HIGH HIGH ON ON

Power Plane +5VS S3 (Suspend to RAM) LOW LOW HIGH HIGH ON OFF
+3VS

a
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF
+0.675VS
1 1
+1VALW +VCC_CORE S5 (Soft OFF) LOW LOW LOW LOW ON OFF

i
+VGA_CORE
+1.8VALW +1.35V

t
+3VS_VGA
B+
+1.8VS_VGA
+3VALW
+1.35VS_VGA

State +5VALW +1VS_VGA

USB2 Port USB3 Port PCIE Port SATA Port

S0 O O O O
Port

1
2
3
Device

On Board
On Board
SUB/B
Port

1
2
3
Device

e
On Board
On Board
SUB/B
Port

1
2
3
nDevice

X
WLAN
Port

1
2
3
Device

HDD
X
X

d
4 ONE-Link DOCK 4 ONE-Link DOCK 4 LAN 4 X
5 Touch Panel 5 X

i
S3 O O O X 6 BT 6 CardReader
7 CMOS 7 X

f
2 2

8 FPR 8 X
S5 S4/AC Only O O X X 9 X 9 GPU
10 GPU

n
S5 S4 11 GPU
Battery only O X X X 12 GPU

o
S5 S4
AC & Battery X X X X SMBUS Control Table
don't exist
Main WLAN Thermal CP Seccurity
SOURCE VGA BATT SODIMM WiMAX Sensor PCH Module ROM LAN PHY G-Sensor

C
EC_SMB_CK1
EC_SMB_DA1

EC_SMB_CK3
EC_SMB_DA3
IT8580F
+3VL

IT8580F
+3VS
X

V
+3VS_VGA
V
+3VALW

X
X

X
X

X
X

V
+3VS +3VALW_PCH
X

V
X

X
X

X
X

X
X

V
+3VALW
3

C
PCH_SMB_CLK PCH
PCH_SMB_DATA
+3VALW_PCH
X X V X X X V V X X
+3VS +5VS +3VS

F
PCH_SML0_CLK PCH
X X X X X X X X V
PCH_SML0_DAT
+3VALW_PCH +3VALW X

L C Security Classification
Issued Date 2013/09/07
LC Future Center Secret Data
Deciphered Date 2014/09/07
Title

NOTE LIST
4

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 3 of 83
A B C D E
 5 4 3 2 1

BOM Structure Table

VGA and DDR3 Voltage Rails (JET TOPAZ GPIO)

l
BOM Structure NOTE
GPIO I/O ACTIVE Function Description

GPIO0 OUT N/A EXO@ For GPU_EXO

a
GPIO5 IN - GPIO5_AC_BATT MESO@ For GPU_MESO
D D

it
GPIO6 IN - GPIO6 DIS@ For GPU function
GPIO7 OUT N/A X76@ GPU VRAM Setting
GPIO8 OUT - GPIO8_ROMSO TPM@ Trusted Platform Module(TPM)
GPIO9 OUT - GPIO9_ROMSI DIMM1@ JDIMM1 function

n
GPIO10 OUT - GPIO10_ROMSCK DIMM2@ JDIMM2 function
GPIO11 OUT N/A UMA@ UMA SKU ID

e
GPIO12 OUT N/A DPRE@ DP re-driver function
GPIO13 OUT N/A NODPRE@ Disable DP re-driver

d
GPIO15 IN N/A SVI2_SVD MIRROR@ For mirror function

if
GPIO16 OUT N/A ME@ ME Connector

C
GPIO17 OUT N/A EMC@ For EMC function C

GPIO19 OUT N/A GPIO19_CTF NVPRO@ For Non-VPRO function

GPIO20 IN IN SVI2_SVC VPRO@ For VPRO function

n
GPIO21 OUT N/A U31@ For U3 port1 redriver function
GPIO22 OUT N/A GPIO22_ROMCSB U32@ For U3 port2 redriver function

o
GPIO29 OUT N/A U33@ For U3 port3 redriver function
GPIO30 OUT N/A NU3R@ No U3 redriver function (All port)
RF@ For RF function

C
TS@ For Touch function
+3VS_VGA

+0.95VS_VGA
B B

+1.8VS_VGA

C
+VGA_CORE RV104 RV105

Memory (GDDR3)
+1.35VS_VGA 10us

F
1G SA22225SH30*4 PU 8.45K PD 2K
Samsung
RESET
2G SA000063F00*4 PU 3.4K PD 10K

1G SA00005VS10*4 PU 4.53K PD 2K
1. all power rail ramp up time should be within 20ms
Hynix

C
2G SA00005YL10*4 PU 4.75K NC

1G SA00005M100*4 NC PD 4.75K
Micron
Device ID 2G SA000060I00*4 PU 3.24K PD 5.62K

L
JET-XT 0x6664
A A

TOPAZ XT 0x6900

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 VGA NOTE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 4 of 83
5 4 3 2 1
 5 4 3 2 1

i a l D

[37]
[37]
DOCK_TX0-
DOCK_TX0+
DOCK_TX0-
DOCK_TX0+
E55
F55
UC1A

DDI1_TXN[0]
DDI1_TXP[0]
SKL_ULT ?
@

EDP_TXN[0]
EDP_TXP[0]
C47
C46
CPU_EDP_TX0-
CPU_EDP_TX0+ CPU_EDP_TX0-
CPU_EDP_TX0+
[42]
[42]

n t
e
DOCK_TX1- E58 D46 CPU_EDP_TX1-
DOCKING [37] DOCK_TX1- DOCK_TX1+ F58 DDI1_TXN[1] EDP_TXN[1] C45 CPU_EDP_TX1+ CPU_EDP_TX1- [42] EDP
[37] DOCK_TX1+ F53 DDI1_TXP[1] EDP_TXP[1] A45 CPU_EDP_TX1+ [42]
DDI1_TXN[2]
EDP EDP_TXN[2]
G53 DP B45
F56 DDI1_TXP[2] EDP_TXP[2] A47
G56 DDI1_TXN[3] EDP_TXN[3] B47
DDI1_TXP[3] EDP_TXP[3]

d
H_HDMI_TX2- C50 E45 CPU_EDP_AUX#
[49] H_HDMI_TX2- H_HDMI_TX2+ DDI2_TXN[0] DDI EDP EDP_AUXN CPU_EDP_AUX CPU_EDP_AUX# [42]
D50 F45
[49] H_HDMI_TX2+ H_HDMI_TX1- DDI2_TXP[0] EDP_AUXP CPU_EDP_AUX [42]
C52
[49] H_HDMI_TX1- H_HDMI_TX1+ D52 DDI2_TXN[1] B52

i
For 14" : HDMI [49] H_HDMI_TX1+ H_HDMI_TX0- A50 DDI2_TXP[1]
HDMI EDP_DISP_UTIL
[49] H_HDMI_TX0- H_HDMI_TX0+ B50 DDI2_TXN[2] G50 DOCK_AUXN
[49] H_HDMI_TX0+ H_HDMI_TXC- D51 DDI2_TXP[2] DDI1_AUXN F50 DOCK_AUXP DOCK_AUXN [37]
[49] H_HDMI_TXC- H_HDMI_TXC+ C51 DDI2_TXN[3] DDI1_AUXP E48 DOCK_AUXP [37]
[49] H_HDMI_TXC+ DDI2_TXP[3] DDI2_AUXN

f
C F48 C
DDI2_AUXP G46
DISPLAY SIDEBANDS DDI3_AUXN F46
DP_DDC_CLK L13 DDI3_AUXP
DP_DDC_DAT L12 GPP_E18/DDPB_CTRLCLK L9 DOCKDP_HPD HDMI_HPD:
20141126 GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 L7 HDMI_HPD DOCKDP_HPD [37,38] Re-driver internal pull down
HDMI_CLK GPP_E14/DDPC_HPD1 HDMI_HPD [49]
N7 L6 DOCKDP_HPD:
[49] HDMI_CLK

n
HDMI_DAT N8 GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 N9 have been pulled down on page 38.
[49] HDMI_DAT GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 CPU_EDP_HPD 2014.12.15
L10
20141106 N11 GPP_E17/EDP_HPD CPU_EDP_HPD [42]
N12 GPP_E22/DDPD_CTRLCLK R12 ENBKL
GPP_E23/DDPD_CTRLDATA EDP_BKLTEN R11 PCH_EDP_PWM ENBKL [66]
1 2 24.9_0402_1% EDP_COMP E52 EDP_BKLTCTL U13 PCH_ENVDD PCH_EDP_PWM [42]
+VCC_IO RC344 20141208
EDP_RCOMP EDP_VDDEN PCH_ENVDD [42]

o
[SKL PDG]EDP_RCOMP Pull up to VCCIO via 24.9 ohm resistor SKYLAKE-U_BGA1356
REV = 1 1 OF 20 ?
[SKL PDG]EDP_RCOMP
1. Trace width=20 mils, Spacing=25mil, Max length=100mils
2. RC1 close to MCP

B
DDPB_CTRLDATA,

HDMI_CLK/HDMI_DAT,
DDPC_CTRLDATA Internal PD 20K

C B

C
Re-driver IC has internal pull up through 2.36k.
2014.12.15
ENBKL RC209 1 2 100K_0402_5%

+3VS CPU_EDP_HPD RC159 1 2 100K_0402_5%

[SKL PDG]EDP_HPD Pull down to ground via

RC2771 @ 2 2.2K_0402_5% HDMI_CLK 20141208 100k ohm resistor

F
RC2871 @ 2 2.2K_0402_5% HDMI_DAT

RC1 1 @ 2 2.2K_0402_5% DP_DDC_CLK

DP_DDC_DAT
20150306
RC2 1 2 2.2K_0402_5%

L C Security Classification
Issued Date 2014/05/07
LC Future Center Secret Data
Deciphered Date 2015/05/07
Title

SKL(1/16):DDI/EDP
A

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 5 of 83
5 4 3 2 1
 5 4 3 2 1

+VCC_STG

it al D

1
2
RC294
1K_0402_5%

e n +VCC_STG

d
20150526
@
20150304 SKL_ULT ? XDP_TDO 1 2 51_0402_1%
UC1D RC404

if
1 D63
H_PECI T60 A54 CATERR# +VCC_ST
[66] H_PECI VR_HOT# RC5 1 2 499_0402_1% VR_HOT#_R C65 PECI [SKL PDG]Refer Figure 45-1
[66,71,74] VR_HOT# PROCHOT# JTA G
THRMTRIP# C63 @
C A65 THERMTRIP# B61 XDP_TCLK 1 XDP_TDO RC3 1 2 51_0402_1% C
SKTOCC# PROC_TCK D60 XDP_TDI 1 T5
+VCC_ST [SKL PDG]1 KΩ pull- up t o VCCST CPU MISC
1 2 1K_0402_1% 1 XDP_BPM#0 C55 PROC_TDI A61 XDP_TDO 1 T4 XDP_TDI 1 XDP@ 2 51_0402_1%
RC53 RC31
T15 1 XDP_BPM#1 D55 BPM#[0] PROC_TDO C60 XDP_TMS 1 T6
1 2 0_0402_5% T16 1 XDP_BPM#2 B54 BPM#[1] PROC_TMS B59 XDP_TRST# 1 T3 XDP_TMS 1 XDP@ 2 51_0402_1%
RC54 @ RC34
[25] H_THERMTRIP# T19 1 XDP_BPM#3 C56 BPM#[2] PROC_TRST# T14
[SKL PDG]If THERMTRIP# goes active, the CPU is indicating an overheat T20 BPM#[3] B56 PCH_JTAG_TCK 1

n
condition, and the PCH will immediately transition to an S5 state. CPU_GP can EC_WAKE# RC40 1 2 0_0402_5% EC_WAKE#_L A6 PCH_JTAG_TCK D59 PCH_JTAG_TDI 1 T9
@
be used from external sensors for the thermal management. [25,66] EC_WAKE# A7 GPP_E3/CPU_GP0 PCH_JTAG_TDI A56 PCH_JTAG_TDO 1 T10 XDP_TCLK 1 2 51_0402_1%
RC4
BA5 GPP_E7/CPU_GP1 PCH_JTAG_TDO C59 PCH_JTAG_TMS 1 T11
AY5 GPP_B3/CPU_GP2 PCH_JTAG_TMS C61 PCH_JTAG_TRST# 1 T12 XDP_TRST# 1 2 51_0402_1%
RC6
GPP_B4/CPU_GP3 PCH_TRST# A59 PCH_JTAGX 1 T8
JTAGX T13
RC151 1 2 49.9_0402_1% PROC_POPIRCOMP AT16 PCH_JTAG_TCKRC372 1 2 51_0402_1%
RC55 1 2 49.9_0402_1% PCH_OPIRCOMP AU16 PROC_POPIRCOMP 20150304

o
RC200 1 2 49.9_0402_1% OPCE_RCOMP H66 PCH_OPIRCOMP
1 2 49.9_0402_1% OPC_RCOMP H65 OPCE_RCOMP
RC56
OPC_RCOMP 20150309

SKYLAKE-U_BGA1356 4 OF 20
[SKL PDG]PROC_OPI_RCOMP: Signal should be pulled down to ground with a resistance of 50 ohm ± 1 %. +1VALW_PCH
[SKL PDG]PCH_OPI_RCOMP: Signal should be pulled down to ground with a resistance of 50 ohm ± 1 %. REV = 1 ?

C
‧‧
[SKL PDG]On Package Interface Compensation (OPI) Guidelines
Should be referenced to VSS plane only. VSS reference planes must be continuous PCH_JTAG_TDI RC373 1 XDP@ 2 51_0402_1%
‧ Require low DC resistance routing <0.2 ohm
Avoid routing next to clock pins or noisy signals.
PCH_JTAG_TMS RC374 1 XDP@ 2 51_0402_1%

B B
+3VALW_PCH +3VS

C
RPC26
8 1 VGA_ON
DGPU_HOLD_RST# VGA_ON [14,24,33,79]
7 2
EC_WAKE# DGPU_HOLD_RST# [14,24]
6 3
5 4

10K_0804_8P4R_5%

C F
A

5
L 4
Security Classification
Issued Date 2014/05/07
LC Future Center Secret Data
Deciphered Date 2015/05/07
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3 2
Title

Custom

Date:
SKL(2/16):MISC/JTAG
Size Document Number
BE460_NM-A551
Wednesday, August 05, 2015
1
Sheet 6 of 83
R ev
1.0
A
 5 4 3 2 1

i a l D

t
[22] DDR_A_D[0..63]
[22] DDR_A_DQS#[0..7]
[22] DDR_A_DQS[0..7]
[22] DDR_A_MA[0..15]

DDR_A_D0 AL71
UC1B
SKL_ULT
20141201
?

DDR0_CKN[0]
@

AU53
AT53
SA_CLK_DDR#0
SA_CLK_DDR0

e SA_CLK_DDR#0 [22]

n
d
DDR_A_D1 AL68 DDR0_DQ[0] DDR0_CKP[0] AU55 SA_CLK_DDR#1 SA_CLK_DDR0 [22]
DDR_A_D2 AN68 DDR0_DQ[1] DDR0_CKN[1] AT55 SA_CLK_DDR1 SA_CLK_DDR#1 [22]
DDR_A_D3 AN69 DDR0_DQ[2] DDR0_CKP[1] SA_CLK_DDR1 [22]
DDR_A_D4 AL70 DDR0_DQ[3] BA56 DDRA_CKE0_DIMMA

i
DDR_A_D5 AL69 DDR0_DQ[4] DDR0_CKE[0] BB56 DDRA_CKE1_DIMMA DDRA_CKE0_DIMMA [22]
DDR_A_D6 AN70 DDR0_DQ[5] DDR0_CKE[1] AW56 DDRA_CKE1_DIMMA [22]
DDR_A_D7 AN71 DDR0_DQ[6] DDR0_CKE[2] AY56
DDR_A_D8 AR70 DDR0_DQ[7] DDR0_CKE[3]
DDR0_DQ[8]

f
C DDR_A_D9 AR68 AU45 DDRA_CS0_DIMMA# C
DDR_A_D10 AU71 DDR0_DQ[9] DDR0_CS#[0] AU43 DDRA_CS1_DIMMA# DDRA_CS0_DIMMA# [22]
DDR_A_D11 AU68 DDR0_DQ[10] DDR0_CS#[1] AT45 DDRA_ODT0_DIMMA# DDRA_CS1_DIMMA# [22]
DDR_A_D12 AR71 DDR0_DQ[11] DDR0_ODT[0] AT43 DDRA_ODT1_DIMMA# DDRA_ODT0_DIMMA# [22]
DDR_A_D13 AR69 DDR0_DQ[12] DDR0_ODT[1] DDRA_ODT1_DIMMA# [22]
DDR_A_D14 AU70 DDR0_DQ[13] BA51 DDR_A_MA5
DDR_A_D15 AU69 DDR0_DQ[14] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] BB54 DDR_A_MA9

n
DDR_A_D16 BB65 DDR0_DQ[15] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] BA52 DDR_A_MA6
DDR_A_D17 AW65 DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] AY52 DDR_A_MA8
DDR_A_D18 AW63 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] AW52 DDR_A_MA7
DDR_A_D19 AY63 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AY55 DDR_A_BS2
DDR_A_D20 BA65 DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] AW54 DDR_A_MA12 DDR_A_BS2 [22]
DDR_A_D21 AY65 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] BA54 DDR_A_MA11
DDR_A_D22 BA63 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] BA55 DDR_A_MA15

o
DDR_A_D23 BB63 DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# AY54 DDR_A_MA14
DDR_A_D24 BA61 DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR_A_D25 AW61 DDR0_DQ[24]/DDR0_DQ[40] AU46 DDR_A_MA13
DDR_A_D26 BB59 DDR0_DQ[25]/DDR0_DQ[41] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AU48 DDR_A_CAS#
DDR_A_D27 AW59 DDR0_DQ[26]/DDR0_DQ[42] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] AT46 DDR_A_WE# DDR_A_CAS# [22]
DDR_A_D28 BB61 DDR0_DQ[27]/DDR0_DQ[43] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] AU50 DDR_A_RAS# DDR_A_WE# [22]
DDR_A_D29 AY61 DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] AU52 DDR_A_BS0 DDR_A_RAS# [22]
DDR_A_D30 BA59 DDR0_DQ[29]/DDR0_DQ[45] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] AY51 DDR_A_MA2 DDR_A_BS0 [22]
DDR_A_D31 AY59 DDR0_DQ[30]/DDR0_DQ[46] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] AT48 DDR_A_BS1

C
DDR_A_D32 AY39 DDR0_DQ[31]/DDR0_DQ[47] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] AT50 DDR_A_MA10 DDR_A_BS1 [22]
DDR_A_D33 AW39 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] BB50 DDR_A_MA1
DDR_A_D34 AY37 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] AY50 DDR_A_MA0
DDR_A_D35 AW37 DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] BA50 DDR_A_MA3
DDR_A_D36 BB39 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] BB52 DDR_A_MA4
DDR_A_D37 BA39 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4]
DDR_A_D38 BA37 DDR0_DQ[37]/DDR1_DQ[5] AM70 DDR_A_DQS#0
DDR_A_D39 BB37 DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSN[0] AM69 DDR_A_DQS0
DDR_A_D40 AY35 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSP[0] AT69 DDR_A_DQS#1
B DDR_A_D41 AW35 DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSN[1] AT70 DDR_A_DQS1 B
DDR_A_D42 AY33 DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQSP[1] BA64 DDR_A_DQS#2
DDR_A_D43 AW33 DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQSN[2]/DDR0_DQSN[4] AY64 DDR_A_DQS2
DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSP[2]/DDR0_DQSP[4]

C
DDR_A_D44 BB35 AY60 DDR_A_DQS#3
DDR_A_D45 BA35 DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSN[3]/DDR0_DQSN[5] BA60 DDR_A_DQS3
DDR_A_D46 BA33 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSP[3]/DDR0_DQSP[5] BA38 DDR_A_DQS#4
DDR_A_D47 BB33 DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSN[4]/DDR1_DQSN[0] AY38 DDR_A_DQS4
DDR_A_D48 AY31 DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSP[4]/DDR1_DQSP[0] AY34 DDR_A_DQS#5
DDR_A_D49 AW31 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSN[5]/DDR1_DQSN[1] BA34 DDR_A_DQS5
DDR_A_D50 AY29 DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSP[5]/DDR1_DQSP[1] BA30 DDR_A_DQS#6
DDR_A_D51 AW29 DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSN[6]/DDR1_DQSN[4] AY30 DDR_A_DQS6

F
DDR_A_D52 BB31 DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSP[6]/DDR1_DQSP[4] AY26 DDR_A_DQS#7
DDR_A_D53 BA31 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSN[7]/DDR1_DQSN[5] BA26 DDR_A_DQS7
DDR_A_D54 BA29 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSP[7]/DDR1_DQSP[5]
DDR_A_D55 BB29 DDR0_DQ[54]/DDR1_DQ[38] AW50 DDR0_ALERT#
DDR_A_D56 AY27 DDR0_DQ[55]/DDR1_DQ[39] DDR0_ALERT# AT52
20141201
DDR_A_D57 AW27 DDR0_DQ[56]/DDR1_DQ[40] DDR0_PAR
DDR_A_D58 AY25 DDR0_DQ[57]/DDR1_DQ[41] AY67 SM_DIMM_VREFCA
DDR_A_D59 AW25 DDR0_DQ[58]/DDR1_DQ[42] DDR_VREF_CA AY68 SA_DIMM_VREFDQ SM_DIMM_VREFCA [22]
DDR_A_D60 BB27 DDR0_DQ[59]/DDR1_DQ[43] DDR0_VREF_DQ BA67 SB_DIMM_VREFDQ SA_DIMM_VREFDQ [22]
DDR CH - A

C
DDR_A_D61 BA27 DDR0_DQ[60]/DDR1_DQ[44] DDR1_VREF_DQ SB_DIMM_VREFDQ [23]
DDR_A_D62 BA25 DDR0_DQ[61]/DDR1_DQ[45] AW67 DDR_PG_CTRL
DDR_A_D63 BB25 DDR0_DQ[62]/DDR1_DQ[46] DDR_VTT_CNTL DDR_PG_CTRL [22]
DDR0_DQ[63]/DDR1_DQ[47]

SKYLAKE-U_BGA1356
REV = 1 2 OF 20 ?

5
L
WWW.AliSaler.Com 4
Security Classification
Issued Date 2014/05/07
LC Future Center Secret Data
Deciphered Date 2015/05/07
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3 2
Title

SKL(3/16):DDR3L CH.A
Size Document Number
Custom

Date:
BE460_NM-A551
Wednesday, August 05, 2015
1
Sheet 7 of 83
R ev
1.0
A
 5 4 3 2 1

[23]
[23]
[23]
[23]
DDR_B_D[0..63]
DDR_B_DQS#[0..7]
DDR_B_DQS[0..7]
DDR_B_MA[0..15]

it al D

n
SKL_ULT @
?
UC1C

DDR_B_D13 AF65 AN45 SB_CLK_DDR#0

DDR_B_D9 AF64 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] AN46 SB_CLK_DDR#1 SB_CLK_DDR#0 [23]
DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] SB_CLK_DDR#1 [23]

e
DDR_B_D11 AK65 AP45 SB_CLK_DDR0
DDR_B_D14 AK64 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] AP46 SB_CLK_DDR1 SB_CLK_DDR0 [23]
DDR_B_D12 AF66 DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] SB_CLK_DDR1 [23]
DDR_B_D8 AF67 DDR1_DQ[4]/DDR0_DQ[20] AN56 DDRB_CKE0_DIMMB
DDR_B_D15 AK67 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] AP55 DDRB_CKE1_DIMMB DDRB_CKE0_DIMMB [23]
DDR_B_D10 AK66 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] AN55 DDRB_CKE1_DIMMB [23]
DDR_B_D0 AF70 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] AP53

d
DDR_B_D1 AF68 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3]
DDR_B_D2 AH71 DDR1_DQ[9]/DDR0_DQ[25] BB42 DDRB_CS0_DIMMB#
DDR_B_D3 AH68 DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] AY42 DDRB_CS1_DIMMB# DDRB_CS0_DIMMB# [23]
DDR_B_D5 AF71 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] BA42 DDRB_ODT0_DIMMB# DDRB_CS1_DIMMB# [23]

if
DDR_B_D4 AF69 DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] AW42 DDRB_ODT1_DIMMB# DDRB_ODT0_DIMMB# [23]
DDR_B_D7 AH70 DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1] DDRB_ODT1_DIMMB# [23] 20141202
DDR_B_D6 AH69 DDR1_DQ[14]/DDR0_DQ[30] AY48 DDR_B_MA5
DDR_B_D24 AT66 DDR1_DQ[15]/DDR0_DQ[31] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AP50 DDR_B_MA9
C DDR_B_D25 AU66 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] BA48 DDR_B_MA6 C
DDR_B_D26 AP65 DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] BB48 DDR_B_MA8
DDR_B_D27 AN65 DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] AP48 DDR_B_MA7
DDR_B_D29 AN66 DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AP52 DDR_B_BS2
DDR_B_D28 AP66 DDR1_DQ[20]/DDR0_DQ[52] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] AN50 DDR_B_MA12 DDR_B_BS2 [23]
DDR_B_D30 AT65 DDR1_DQ[21]/DDR0_DQ[53] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AN48 DDR_B_MA11
DDR_B_D31 AU65 DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AN53 DDR_B_MA15

n
DDR_B_D16 AT61 DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# AN52 DDR_B_MA14
DDR_B_D17 AU61 DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR_B_D18 AP60 DDR1_DQ[25]/DDR0_DQ[57] BA43 DDR_B_MA13
DDR_B_D19 AN60 DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] AY43 DDR_B_CAS#
DDR_B_D21 AN61 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] AY44 DDR_B_WE# DDR_B_CAS# [23]
DDR_B_D20 AP61 DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] AW44 DDR_B_RAS# DDR_B_WE# [23]
DDR_B_D22 AT60 DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] BB44 DDR_B_BS0 DDR_B_RAS# [23]

o
DDR_B_D23 AU60 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] AY47 DDR_B_MA2 DDR_B_BS0 [23]
?
DDR_B_D32 AU40 DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] BA44 DDR_B_BS1
DDR_B_D33 AT40 DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] AW46 DDR_B_MA10 DDR_B_BS1 [23]
DDR_B_D34 AT37 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AY46 DDR_B_MA1
DDR_B_D35 AU37 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] BA46 DDR_B_MA0
DDR_B_D36 AR40 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] BB46 DDR_B_MA3
DDR_B_D37 AP40 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[3] BA47 DDR_B_MA4
DDR_B_D38 AP37 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[4]
DDR_B_D39 AR37 DDR1_DQ[38]/DDR1_DQ[22] AH66 DDR_B_DQS#1

C
DDR_B_D40 AT33 DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQSN[0]/DDR0_DQSN[2] AH65 DDR_B_DQS1
DDR_B_D41 AU33 DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQSP[0]/DDR0_DQSP[2] AG69 DDR_B_DQS#0
DDR_B_D42 AU30 DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[1]/DDR0_DQSN[3] AG70 DDR_B_DQS0
DDR_B_D43 AT30 DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[1]/DDR0_DQSP[3] AR66 DDR_B_DQS#3
DDR_B_D44 AR33 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[2]/DDR0_DQSN[6] AR65 DDR_B_DQS3
DDR_B_D45 AP33 DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[2]/DDR0_DQSP[6] AR61 DDR_B_DQS#2
DDR_B_D46 AR30 DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[3]/DDR0_DQSN[7] AR60 DDR_B_DQS2
DDR_B_D47 AP30 DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[3]/DDR0_DQSP[7] AT38 DDR_B_DQS#4
DDR_B_D48 AU27 DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[4]/DDR1_DQSN[2] AR38 DDR_B_DQS4
B DDR_B_D49 AT27 DDR1_DQ[48] DDR1_DQSP[4]/DDR1_DQSP[2] AT32 DDR_B_DQS#5 B
DDR_B_D50 AT25 DDR1_DQ[49] DDR1_DQSN[5]/DDR1_DQSN[3] AR32 DDR_B_DQS5
DDR_B_D51 AU25 DDR1_DQ[50] DDR1_DQSP[5]/DDR1_DQSP[3] AR25 DDR_B_DQS#6
DDR1_DQ[51] DDR1_DQSN[6]

C
DDR_B_D52 AP27 AR27 DDR_B_DQS6
DDR_B_D53 AN27 DDR1_DQ[52] DDR1_DQSP[6] AR22 DDR_B_DQS#7
DDR_B_D54 AN25 DDR1_DQ[53] DDR1_DQSN[7] AR21 DDR_B_DQS7
DDR_B_D55 AP25 DDR1_DQ[54] DDR1_DQSP[7]
DDR_B_D56 AT22 DDR1_DQ[55] AN43 DDR1_ALERT#
DDR_B_D57 AU22 DDR1_DQ[56] DDR1_ALERT# AP43
20141022
DDR_B_D58 AU21 DDR1_DQ[57] DDR1_PAR AT13 DDR3_DRAMRST#
DDR_B_D59 AT21 DDR1_DQ[58] DRAM_RESET# AR18 SM_RCOMP0 DDR3_DRAMRST# [22,23]
RC8 1 2 121_0402_1%

F
DDR_B_D60 AN22 DDR1_DQ[59] DDR_RCOMP[0] AT18 SM_RCOMP1 RC9 1 2 80.6_0402_1%
DDR_B_D61 AP22 DDR1_DQ[60] DDR_RCOMP[1] AU18 SM_RCOMP2 RC10 1 2 100_0402_1%
DDR_B_D62 AP21 DDR1_DQ[61] DDR_RCOMP[2]
DDR_B_D63 AN21 DDR1_DQ[62] DDR CH - B
DDR1_DQ[63]

SKYLAKE-U_BGA1356 3 OF 20
[SKL PDG]for DDR3L
REV = 1 DDR_RCOMP[0] Pull down 121 ohm resistor

C
DDR_RCOMP[1] Pull down 80.6 ohm resistor
DDR_RCOMP[2] Pull down 100 ohm resistor

[SKL PDG]DDR_RCOMP
1. Trace width=12~15 mils, Spacing=20mil, Max length=500mils
2. R close to MCP

5
L 4
Security Classification
Issued Date 2014/05/07
LC Future Center Secret Data
Deciphered Date 2015/05/07
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3 2
Title

SKL(4/16):DDR3L CH.B
Size Document Number
Custom

Date:
BE460_NM-A551
Wednesday, August 05, 2015
1
Sheet 8 of 83
R ev
1.0
A
 5 4 3 2 1

i a l D

[SKL PDG]Manufacturing Mode Jumper

n t
e
1. If strap is sampled low, the security measures def i nedi n t he Fl as h Descri pt or will bei n ef f ect ( def ault)
2. If sampled high, the Flash Descriptor Security will be overridden.

RPC2
20141024

d
PCH_HDA_RST# 1 8 HDA_RST#
[39] PCH_HDA_RST# PCH_HDA_BCLK 2 7 HDA_BCLK
[39] PCH_HDA_BCLK PCH_HDA_SDOUT 3 6 HDA_SDOUT
[39] PCH_HDA_SDOUT PCH_HDA_SYNC 4 5 HDA_SYNC

i
[39] PCH_HDA_SYNC
33_0804_8P4R_5%
SD30000370T @
?
SKL_ULT
UC1G

f
C RC21 1 @ 2 0_0402_5% C
[66] ME_FLASH Close to CPU AUDIO

HDA_SYNC BA22
PCH_HDA_BCLK HDA_BCLK
RC364 1 @ 2 0_0402_5% HDA_BCLK_R AY22 HDA_SYNC/I2S0_SFRM
HDA_SDOUT BB22 HDA_BLK/I2S0_SCLK
SDIO/SDXC
PCH_HDA_SDIN0 BA21 HDA_SDO/I2S0_TXD
1

n
[39] PCH_HDA_SDIN0 AY21 HDA_SDI0/I2S0_RXD AB11
RF_NS@
CC538 HDA_RST# AW22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13
47P_0402_50V8-J J5 HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 AB12
2 AY20 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 W12
AW20 I2S1_SFRM GPP_G3/SD_DATA2 W11
I2S1_TXD GPP_G4/SD_DATA3 W10
AK7 GPP_G5/SD_CD# W8

o
AK6 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK W7
GPP_B14, Internal PD 20K AK9 GPP_F0/I2S2_SCLK GPP_G7/SD_WP
GPP_F2/I2S2_TXD
No Reboot on TCO AK10
GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7
BA9
BB9
Timer expiration GPP_A16/SD_1P8_SEL RC363 20141106
pull-up to VCC3_3 through a 1– 8.2 KΩ ± 5% H5
D7 GPP_D19/DMIC_CLK0 SD_RCOMP
AB7 1 2

resistor to disable this capability GPP_D20/DMIC_DATA0

D8 AF13 200_0402_1%

C
C8 GPP_D17/DMIC_CLK1 GPP_F23
20141202 +3VALW_PCH
20141106 GPP_D18/DMIC_DATA1
PCH_BEEP AW5
[40] PCH_BEEP GPP_B14/SPKR

PCH_BEEP RC95 1 @ 2
8.2K_0402_5%
RC3001 2
20K_0402_5% [SKL PDG] internal SD Card
B 7 OF 20 B
SKYLAKE-U_BGA1356
REV = 1 ?
20141202

C
Processor Strapping
543016_543016_SKL_PDG_UY_1_0_pub
+VCC_IO
P780
PCH_HDA_SDIN0 RC2971 @ 2

F
1K_0402_5%
RC3011 2
@ 20K_0402_5%

RGB( 0,255,128)

20141202

C
+VCC_HDA

HDA_SDOUT RC2991 @ 2
1K_0402_5%
RC3021 2

L
@ 20K_0402_5%
RGB( 0,255,128)
20141202
A A

+3VALW_PCH

HDA_SYNC RC3671 2
Security Classification LC Future Center Secret Data Title
1K_0402_5%
@ Issued Date 2014/05/07 Deciphered Date 2015/05/07 SKL(5/16):HDA/SDIO

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 9 of 83
5 4 3 2 1
 5 4 3 2 1

RTC External Circuit JCMOS, JME Setting, Need Under DDR Door

l
+RTCBATT +RTCVCC +RTCVCC
JCMOS1 @
1 2 1 RC12 2 PCH_RTCRST# 1 2
RC11 @ 0_0402_5%

1 1 20K_0402_5% CC1 1 2 1U_0402_10V6K

a
C8542
+RTCBATT, +RTCVCC CC2
1U_0402_10V6K 0.1U_0402_10V6-K JME1 @
D Trace width = 20mils 2 2 1 RC14 2 PCH_SRTCRST# 1 2 D

it
20K_0402_5% 1 2 1U_0402_10V6K
CC5

UC1J SKL_ULT ?
@

e n
[SKL PDG]Used to set BIAS reference for differential

d
+3VS 20141202 CLOCK SIGNALS
clocks. Connect to a 2.71K ± 0.5% precision resistor to 1.0v.
RC29 1 DIS@ 2 10K_0402_5% D42

if
C42 CLKOUT_PCIE_N0
RC32 1 UMA@ 2 10K_0402_5% DISCRETE_PRESENCE AR10 CLKOUT_PCIE_P0
GPP_B5/SRCCLKREQ0#
B42
C A42 CLKOUT_PCIE_N1 F43 CLKOUT_ITPXDP_N 1 C
AT7 CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N E43 CLKOUT_ITPXDP_P 1 T52
GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P T53 20141126
CLK_PCIE_WLAN# D41 BA17 SUSCLK_32K
[56] CLK_PCIE_WLAN# CLK_PCIE_WLAN C41 CLKOUT_PCIE_N2 GPD8/SUSCLK SUSCLK_32K [56]
[56] CLK_PCIE_WLAN CLKREQ_PCIE2_WLAN# AT8 CLKOUT_PCIE_P2 E37 PCH_XTAL24_IN
WLAN [56] CLKREQ_PCIE2_WLAN# GPP_B7/SRCCLKREQ2# XTAL24_IN PCH_XTAL24_OUT
E35 20150305

n
CLK_PCIE_LAN# D40 XTAL24_OUT RC362
[51] CLK_PCIE_LAN# CLK_PCIE_LAN C40 CLKOUT_PCIE_N3 E42 DIFFCLK_BIASREF 1 2
[51] CLK_PCIE_LAN CLKREQ_PCIE3_LAN# CLKOUT_PCIE_P3 XCLK_BIASREF +1VALW
LAN AT10
[51] CLKREQ_PCIE3_LAN# GPP_B8/SRCCLKREQ3# PCH_RTCX1
AM18
CLK_PCIE_VGA# B40 RTCX1 AM20 PCH_RTCX2 2.7K_0402_1%
[24] CLK_PCIE_VGA# CLK_PCIE_VGA A40 CLKOUT_PCIE_N4 RTCX2 20141126
20141024 [24] CLK_PCIE_VGA CLKREQ_PCIE4_VGA# AU8 CLKOUT_PCIE_P4 AN18 PCH_SRTCRST#
VGA

o
[24] CLKREQ_PCIE4_VGA# GPP_B9/SRCCLKREQ4# SRTCRST# PCH_RTCRST#
AM16
CLK_PCIE_CR# E40 RTCRST#
[57] CLK_PCIE_CR# CLK_PCIE_CR E38 CLKOUT_PCIE_N5
CR [57] CLK_PCIE_CR CLKREQ_PCIE5_CR# CLKOUT_PCIE_P5
+3VS AU7
[57] CLKREQ_PCIE5_CR# GPP_B10/SRCCLKREQ5#
[SKL PDG]External pull-up resistor required if
used for CLKREQ# functionality.

C
UMA@ +3VS
1 2 10K_0402_5% CLKREQ_PCIE4_VGA# 10 OF 20
RC165 RPC200 SKYLAKE-U_BGA1356
1 8 CLKREQ_PCIE2_WLAN#REV = 1 ?
2 7 CLKREQ_PCIE3_LAN# 20141024
DIS@ 3 6
RC166 1 2 10K_0402_5% 4 5 CLKREQ_PCIE5_CR#

10K_0804_8P4R_5%
B B

F C [SKL PDG]
1.Space > 15mils
2.No trace under crystal
3.Place on oppsosit side of MCP for temp inf l uence
4.The exact capacitor values forC1 and C2 must be based on the crystal maker recommendat i ons.
Typical values for C1 and C2 are 18 pF, based on crystal load of 12.5 pF.
RTC Crystal
PCH_RTCX1
[SKL PDG]
1.A 24 MHz crystal with crystal frequency tolerance and stability of +/-30 ppm
2.Two External Load Capacitors (Ce1 and Ce2)
3.A 1-Mohm bias resistor (Rf)
PCH_XTAL24_IN

PCH_XTAL24_OUT 1 RC30 2

C
1 RC13 2 PCH_RTCX2 1M_0402_5%
YC2
10M_0402_5%
YC1 1 3
1 2 1 3
Only Change P/N of YC1 to SJ10000J900
[SKL PDG]Max Crystal ESR = 50k Ohm. GND1 GND2
The Descripton of P/N is 9H03280012 1 1
1 32.768KHZ_12.5PF_9H03200042 1

L
CC6 2 4 CC7
CC3 CC4 12P_0402_50V8-J 12P_0402_50V8-J
5.6P_0402_50V8-D 5.6P_0402_50V8-D 2 2
2 2 24MHZ_10PF_8Y24000011
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/05/07 Deciphered Date 2015/05/07 SKL(6/16):CLOCK SIGNALS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 10 of 83
5 4 3 2 1
 5 4 3 2 1

Functional Strap Definitions

GPP_C2, Internal PD 20K GPP_C5, Internal PD 20K
SPI0_MOSI L:Disable Intel ME Crypto TLS cipher suite (no confidentiality). *L: LPC
*H:Enable Intel ME Crypto Transport Layer Security (TLS) cipher H: eSPI +3VALW_PCH

l
This signal has an internal pull-up. suite (with confidentiality).Support Intel AMT with TLS and Intel
This strap should sample HIGH. There should NOT be any SBA (Small Business Advantage) with TLS. GPP_C5
on-board device driving it to opposite direction during RC83 2 @ 1 1K_0402_5%
strap sampling. RC84 2 1 20K_0402_5%

+3VALW_PCH +3VALW_PCH

a
GPP_C2 RC306 1 2
SPI_SI RC298 1 @ 2 1K_0402_5%
D D
RC307 1 2

i
8.2K_0402_5%
@ 20K_0402_5%

20150305 RGB( 0,255,128)

20141202

SPI_SO RC308 1 @

20150305
2
8.2K_0402_5%
+3VALW_PCH

n t
e
20141202

C
[21,60] SPI_CLK
RC365

[21,60]
[21,60]
[21]
[21]
[21]
[21]
[60]
Close to CPU

1 @
SPI_SO
SPI_SI
SPI_IO2
SPI_IO3
SPI_CS0#_8MB
SPI_CS1#_4MB
SPI_CS2#_TPM
20141202

2 0_0402_5% PCH_SPI_CLK
SPI_SO
SPI_SI
SPI_IO2
SPI_IO3
SPI_CS0#_8MB
SPI_CS1#_4MB
SPI_CS2#_TPM
AV2
AW3
AV3
AW2
AU4
AU3
AU2
AU1
UC1E

SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_IO2
SPI0_IO3
SPI0_CS0#
SPI0_CS1#
SPI0_CS2#
SPI - FLASH
SKL_ULT
?

f
SMBUS, SMLINK

GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C2/SMBALERT#

GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C5/SML0ALERT#
@

R7
R8
R10

R9
W2
W1

i d
PCH_SMB_CLK
PCH_SMB_DATA
GPP_C2

PCH_SML0_CLK
PCH_SML0_DAT
GPP_C5

PCH_SML1CLK
DIMM1, DIMM2, Security EEPROM, Click Pad

PCH_SML0_CLK
PCH_SML0_DAT
[51]
[51]
LAN
C

n
W3
GPP_C6/SML1CLK V3 PCH_SML1DATA
SPI - TOUCH GPP_C7/SML1DATA AM7 GPP_B23 EC,dGPU,Thermal Sensor
M2 GPP_B23/SML1ALERT#/PCHHOT#
M3 GPP_D1/SPI1_CLK
J4 GPP_D2/SPI1_MISO
V1 GPP_D3/SPI1_MOSI
V2 GPP_D21/SPI1_IO2
GPP_D22/SPI1_IO3

o
EC_SCI# M1 LPC AY13
[66] EC_SCI# GPP_D0/SPI1_CS# GPP_A1/LAD0/ESPI_IO0 LPC_AD0 [66]
BA13
GPP_A2/LAD1/ESPI_IO1 LPC_AD1 [66]
BB13
20141106 C LINK GPP_A3/LAD2/ESPI_IO2 AY12 LPC_AD2 [66]
GPP_A4/LAD3/ESPI_IO3 LPC_AD3 [66]
G3 BA12
[56] CL_CLK_WLAN G2 CL_CLK GPP_A5/LFRAME#/ESPI_CS# BA11 SUS_STAT# LPC_FRAME# [66]
RC47 1 @ 2 0_0402_5% 1
[56] CL_DATA_WLAN CL_DATA GPP_A14/SUS_STAT#/ESPI_RESET# T18
G1
[56] CL_RST_WLAN# CL_RST# 20141128
AW9 PCH_PCI_CLK_R RC24 1 EMC@ 2 22_0402_5%
GPP_A9/CLKOUT_LPC0/ESPI_CLK CLK_PCI_EC [66]
KBRST# AW13 AY9
[66] KBRST# GPP_A0/RCIN# GPP_A10/CLKOUT_LPC1 AW11CLKRUN#

C
GPP_A8/CLKRUN# 1
SERIRQ AY11 RF_NS@
[60,66] SERIRQ GPP_A6/SERIRQ +3VS CC537
20141128
47P_0402_50V8-J
5 OF 20 2
SKYLAKE-U_BGA1356 RC52 1 2 8.2K_0402_5%
REV = 1 ?
20141202
[SKL PDG]RCIN# Pull-up to Vcc3_3 with 10 Kohm resistor. [SKL PDG]CLKRUN# Requires an 8.2 KΩ weak pull- up r esi st or t o Vcc3_3

[SKL PDG]SERIRQ uses a 8.2 KΩ pull-up to +V3.3S power-rail.

B [SKL CRB]SERIRQ uses a 10 KΩ pull-up to +V3.3S power-rail. B

+3VS

F C +3VALW_PCH

PCH_SMB_CLK 6
D
SB000013A00
2N7002KDWH_SOT363-6
QC1A
1 +3VS PCH_SML1CLK 6
2N7002KDWH_SOT363-6
QC2A
1
SB000013A00

D
PCH_SML0_CLK PM_SMB_CLK [21,22,23,53] EC_SMB_CK3 [25,37,59,60,66]

S
RC92 1 2 499_0402_1%
PCH_SML0_DAT RC93 1 2 499_0402_1%
RPC22
8 1 SERIRQ +3VS
7 2 EC_SCI# PCH_SMB_CLK RC375 1 2 4.7K_0402_5%
G

G
2

2
6 3 PCH_SMB_DATA RC376 1 2 4.7K_0402_5% +3VS
5 4 KBRST# PCH_SML1CLK RC377 1 2 2.2K_0402_1% RC106 1 2 4.7K_0402_5%
PCH_SML1DATA 1 2

C
RC378 2.2K_0402_1%
10K_0804_8P4R_5%
RC107 1 2 4.7K_0402_5%
5

5
G

G
PCH_SMB_DATA 3 4 PCH_SML1DATA 3 4
S

S
GPP_B23 PM_SMB_DAT [21,22,23,53] EC_SMB_DA3 [25,37,59,60,66]
RC101 2 1 1K_0402_5%
D

D
QC1B QC2B SB000013A00

L
2N7002KDWH_SOT363-6 2N7002KDWH_SOT363-6
SB000013A00

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/05/07 Deciphered Date 2015/05/07 SKL(7/16):LPC/SPI/SMBUS/CL

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 11 of 83
5 4 3 2 1
 5 4 3 2 1

D
[SKL PDG]SYS_RESET#:Connect this signal on PCH directly to the
reset but t on and pull- up t hi s si gnal t o +V3. 3V cor e r ail t hr ough
a weak pull-up resistor (8.2~10 Kohm).

[SKL PDG]PROCPWRGD
1.Indicates that VCCIN, VDDQ power supplies and clocks are stable. This signal
will be asserted only af t er PC H_P WR OK asser t i o.n
2.PROCPWRGD is used only for power sequence debug and is not required to
be connected to anything on the plat f or m . UC1K
SKL_ULT ?
@
Signals driven by the PCH.

it al
[SKL PDG]SLP_S3, SLP_S4, SLP_S5 No pull-up/pull-down resistors needed.

[SKL PDG]SLP_A:No pull-up/pull-down resistors needed. Signals driven by the PCH.

Can be lef t as NC whenI nt el R Ac t i ve Manag ement Technol ogy ( IntelR AM
supported on the plat f or m
. When assert ed ( 0) I nt el R MEi s i n M
- Off
T) is no
t
D

n
SYSTEM POWER MANAGEMENT
+3VS AT11 PM_SLP_S0# 1 T50
20141106
GPP_B12/SLP_S0# AP15 PM_SLP_S3# PM_SLP_S3# 1 TP125
AN10 GPD4/SLP_S3# BA16 PM_SLP_S4# PM_SLP_S3# [66] PM_SLP_S4# 1
PLTRST# TP126
[24] PLTRST# GPP_B13/PLTRST# GPD5/SLP_S4# PM_SLP_S4# [66]
RC108 1 2 10K_0402_5% SYS_RESET# B5 AY16 PM_SLP_S5# PM_SLP_S5# 1 TP127
SYS_RESET# GPD10/SLP_S5# PM_SLP_S5# [66]

e
EC_RSMRST# AY17
[66] EC_RSMRST# RSMRST# AN15
1 H_CPUPWRGD A68 SLP_SUS# AW15 PCH_SLP_LAN# 20141205
VCCST_PG_EC 1 2 T59 VCCST_PWRGD_R B65 PROCPWRGD SLP_LAN# BB17 PCH_SLP_WLAN# PCH_SLP_LAN# [51,66]
VCCST_PWRGD GPD9/SLP_WLAN# PM_SLP_A# PCH_SLP_WLAN# [66] 20150305PM_SLP_A#
RC387 60.4_0402_1% AN16 1 TP128
PCH_SYSPWROK B6 GPD6/SLP_A# PM_SLP_A# [66]
[66] PCH_SYSPWROK SYS_PWROK PBTN_OUT# PBTN_OUT#
RC41 1 @ 2 0_0402_5% PWROK BA20 BA15 1 TP129

d
[66] PCH_PWROK 1 2 EC_DPWROK_R BB20 PCH_PWROK GPD3/PWRBTN# AY15 AC_PRESENT PBTN_OUT# [66]
RC286 @ 0_0402_5%
[66] EC_DPWROK EC_RSMRST# DSW_PWROK GPD1/ACPRESENT AC_PRESENT [66]
RC352 1 @ 2 0_0402_5% AU13 BATLOW#
RC109 1 @ 2 0_0402_5% SUSWARN# AR13 GPD0/BATLOW#
SUSACK# AP11 GPP_A13/SUSWARN#/SUSPWRDNACK +RTCVCC
20141205

if
GPP_A15/SUSACK# AU11 PME# 1 T62
PCIE_WAKE# BB15 GPP_A11/PME# AP16 PCH_INTRUDER# RC16 2 1 1M_0402_5%
AM15 WAKE# INTRUDER#
LANPHYPC AW17 GPD2/LAN_WAKE# AM10 EXT_PWR_GATE# 1 T61
C [51] LANPHYPC AT15 GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# AM11 VRALERT# 1 C
T49
GPD7/RSVD GPP_B2/VRALERT#
20141208 PWROK Connect to Power
GPD7
SKYLAKE-U_BGA1356 11 OF 20 ?
REV = 1 [SKL PDG]EXT_PWR_GATE#(External Power Gate)

n
RC403 1.HSIO Power Control: Used to control power to VCCMPHYGT_1p0, VCCMPHYPLL_1p0
10K_0402_5% +VCC_STG and VCCSRAM_1p0 in S0 & Sx.
[SKL PDG]AC_PRESENT:8.2~10 KΩ pull- up t o DS W well. 2.PCH will drive EXT_PWR_GATE# low when all the high speed IO controllers (xHCI,
@
SATA and PCIe) are idle or have no
1

1
[SKL PDG]BATLOW#:8.2~10 KΩ pull- up t o DS W well. @ devices at t ached.
[SKL PDG]WAKE# :10 KΩ pull- up t o Vcc DS W3_3. RC123

o
@ 10K_0402_5%
[SKL PDG]APWROK :There is no corresponding APWROK signal input to the RC411

2
1 2 VCCST_PWRGD
PCH, but the PCH does have an internally generated version of APWROK [66] VCCST_PG_EC
that is t i med fr o mSL P_A#. 0_0402_5%

+3VALW +VCC_STG

C
RPC18
1 8 AC_PRESENT 20141124
2 7 BATLOW#

2
3 6 PCH_SLP_LAN#
20150304
4 5 RC383
1K_0402_5%
10K_0804_8P4R_5%
SD300002P0T
1
B RPC6 VCCST_PG_EC B
8 1 PCIE_WAKE#
7 2 20150305

C
6 3 PCH_SLP_WLAN#
5 4

10K_0804_8P4R_5%
20141210
@
RC379 1 2 PBTN_OUT#
10K_0402_5%

F
@
RC3511 2 GPD7
10K_0402_5%
@ +3VALW
RC3531 2 EC_DPWROK UC3
10K_0402_5% 1 5
NC VCC RC348 1 2 33_0402_5%
PLTRST# 2 PLTRST_NEAR# [21]
[SKL PDG]RSMRST#:Recommend an 8.2~10 Kohm IN_A

C
pull-down resistor to ground. 3 4 RC48 1 2 33_0402_5%
1 GND OUT_Y PLTRST_FAR# [51,56,57,60,66]
Note: CRB uses 10 KΩ pull- do wn.
1 1
RC27 RC26 TC7SG17FE_SON5
1 2 EC_RSMRST# 100K_0402_5% CC9 CC102
100P_0402_25V8J 100P_0402_25V8J
2

10K_0402_5% 2 2

L
Close to CPU
CC527
EMC_NS@
1 2 PCH_SYSPWROK
5P_0402_50V9-C
A A

CC528
EMC_NS@
1 2 PWROK
5P_0402_50V9-C

CC529
EMC_NS@ Title
1 2 EC_DPWROK_R Security Classification LC Future Center Secret Data
5P_0402_50V9-C Issued Date 2014/05/07 Deciphered Date 2015/05/07 SKL(8/16):SYSTEM PM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 12 of 83
5 4 3 2 1
 D

1.0
R ev

83
of
l

13
a

BE460_NM-A551
Sheet
SKL(9/16):Decoupling

Wednesday, August 05, 2015

1

1
i

Size Document Number

n t 20141126

Custom
Title

Date:
e

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
2015/05/07
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
d

LC Future Center Secret Data

2

2
1U_0201_6.3V6-M
1

Deciphered Date
CC525
1U_0201_6.3V6-M
1

10U_0603_6.3V6-M CC524
1U_0201_6.3V6-M
1 2
1

CC521
f

10U_0603_6.3V6-M CC523
1U_0201_6.3V6-M
1 2
1

CC520
CC522
10U_0603_6.3V6-M 1U_0201_6.3V6-M
n
1

1 2

2014/05/07
CC282 CC292
10U_0603_6.3V6-M 1U_0201_6.3V6-M
1

1 2
CC281 CC291
10U_0603_6.3V6-M 1U_0201_6.3V6-M
1

1 2
o
CC280 CC290
@

10U_0603_6.3V6-M 1U_0201_6.3V6-M
1

1 2

Security Classification
CC279 CC289
@

10U_0603_6.3V6-M 1U_0201_6.3V6-M
1

Issued Date
1 2
3

3
CC278 CC288
@

10U_0603_6.3V6-M 1U_0201_6.3V6-M
C
1

1 2
CC277 CC287
@
[SKL PDG] 10uF x 4, 1uF x 16

10U_0603_6.3V6-M 1U_0201_6.3V6-M
1

1 2
CC276 CC286
@

10U_0603_6.3V6-M 1U_0201_6.3V6-M
1

1 2
CC275 CC285
[SKL PDG]VCCGT

10U_0603_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M

1

1 2
CC274 CC284 CC294
@

10U_0603_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M

1

C
1 2
+VCC_GT

CC273 CC283 CC293

@

F
4

4
1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M
1

WWW.AliSaler.Com
CC246 CC256 CC502
1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M
1

C
CC245 CC255 CC501 CC511
1U_0201_6.3V6-M
1 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M

2
CC244 CC254 CC500 CC510
1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 10U_0603_6.3V6-M

2
1 2
CC243 CC253 CC509 CC519 CC272
10U_0603_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 10U_0603_6.3V6-M

2
1 2 1 2

L
CC241 CC252 CC508 CC518 CC270
[SKL PDG] 10uF x 3 , 1uF x 34.

10U_0603_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 10U_0603_6.3V6-M

2
1 2 1 2
CC240 CC251 CC507 CC517 CC271
10U_0603_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 10U_0603_6.3V6-M

2
1 2 1 2
CC239 CC250 CC506 CC516 CC268
10U_0603_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 10U_0603_6.3V6-M

[SKL PDG]VCC

2
1 2 1 2
CC238 CC249 CC504 CC514 10U_0603_6.3V6-M CC269
10U_0603_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 10U_0603_6.3V6-M
1 2

2
5

5
1 2 CC242 1 2
CC237 CC248 CC505 CC515 CC267
10U_0603_6.3V6-M 10U_0603_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 10U_0603_6.3V6-M

2
+VCC_CORE
1 2 1 2 1 2
CC235 CC236 CC247 CC503 CC512 CC257 CC266

@
D

A
 5 4 3 2 1

l
GPP_B18, Internal PD 20K GPP_B22, Internal PD 20K
*L: Disable “ No Reboot” mode *L: SPI
H: Enable “ No Reboot” mod
e +3VALW_PCH H: LPC +3VALW_PCH

a
GPP_B18 2 1 GPP_B22 2 @ 1
RC97 @ 1K_0402_5% RC99 1K_0402_5% Project ID
D 1 2 1 2 D

it
RC98 @ 20K_0402_5% RC100 20K_0402_5% PLANARID0 (GPP_B5) PLANARID2 DGPU_PWROK
(GPP_C8) (GPP_C10) (GPP_A7)
20150305 L 14" UMA 1(X)
H 15" DIS 1(X)
* * +3VS
Only for 14NM

1
n

10K_0402_5%

RC70
10K_0402_5%

RC67

10K_0402_5%

RC409
@ @
?SKL_ULT
UC1F @

2
2

2
LPSS ISH
PLANARID0

e
RF_OFF# AN8 P2 RC405 PLANARID1
[56] RF_OFF# AP7 GPP_B15/GSPI0_CS# GPP_D9 P3 CP_RESET#_R 2 1 CP_RESET#
AP8 GPP_B16/GSPI0_CLK GPP_D10 P4 CP_RESET# [53,66]
GPP_B18 AR7 GPP_B17/GSPI0_MISO GPP_D11 P1 0_0402_5%
GPP_B18/GSPI0_MOSI GPP_D12 DGPU_PWROK
PCH_CMOS_ON [15,33,79] DGPU_PWROK
AM5 M4

d
[42] PCH_CMOS_ON GPP_B19/GSPI1_CS# GPP_D5/ISH_I2C0_SDA

1
AN7 N3 @
BT_ON GPP_B20/GSPI1_CLK GPP_D6/ISH_I2C0_SCL

10K_0402_5%

RC71

10K_0402_5%

RC410

10K_0402_5%

RC74
AP5
[56] BT_ON 20141211 GPP_B22 AN5 GPP_B21/GSPI1_MISO N1 @
GPP_B22/GSPI1_MOSI GPP_D7/ISH_I2C1_SDA N2

if
PLANARID0 AB1 GPP_D8/ISH_I2C1_SCL

2
CP_BYPASS RC4062 1
0_0402_5% CP_BYPASS_R AB2 GPP_C8/UART0_RXD AD11
[53,66] CP_BYPASS TP_REST TP_REST_R GPP_C9/UART0_TXD GPP_F10/I2C5_SDA/ISH_I2C2_SDA
RC4072 1
0_0402_5% W4 AD12
[53,66] TP_REST DGPU_PWROK RC389 2 10_0402_5% AB3 GPP_C10/UART0_RTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL
@
C GPP_C11/UART0_CTS# C

20150309 1 AD1 U1
TC119 GPP_C20/UART2_RXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
1 AD2 U2
F4_LED# TC120 GPP_C21/UART2_TXD GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
AD3 U3
[55] F4_LED# PCH_TSOFF# AD4 GPP_C22/UART2_RTS# GPP_D15/ISH_UART0_RTS# U4
20150305 [55] PCH_TSOFF# GPP_C23/UART2_CTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT#
AC1 FN_LED#

n
U7 GPP_C12/UART1_RXD/ISH_UART1_RXD AC2 F1_LED# FN_LED# [55]
PLANARID1
U6 GPP_C16/I2C0_SDA GPP_C13/UART1_TXD/ISH_UART1_TXD AC3 F1_LED# [55]
GPP_C17/I2C0_SCL GPP_C14/UART1_RTS#/ISH_UART1_RTS# AB4
VGA_ON U8 GPP_C15/UART1_CTS#/ISH_UART1_CTS#
[6,24,33,79] VGA_ON DGPU_HOLD_RST# U9 GPP_C18/I2C1_SDA AY8
[6,24] DGPU_HOLD_RST# GPP_C19/I2C1_SCL GPP_A18/ISH_GP0 BA8
AH9 GPP_A19/ISH_GP1 BB7

o
AH10 GPP_F4/I2C2_SDA GPP_A20/ISH_GP2 BA7
20141210 GPP_F5/I2C2_SCL
SKYLAKE-U_BGA1356
6 OF 20 GPP_A21/ISH_GP3 AY7
MIC_HW_EN AH11 REV = 1 ? GPP_A22/ISH_GP4 AW7
AH12 GPP_F6/I2C3_SDA GPP_A23/ISH_GP5 AP13 1
GPP_F7/I2C3_SCL GPP_A12/BM_BUSY#/ISH_GP6 TC118
AF11
AF12 GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL
2

C
RC366
@ 0_0402_5%
1

+3VALW_PCH

RC371
1 2 RF_OFF#
20141222
B 10K_0402_5% B

+3VS

8
7
6
5

F C
RPC8
1
2
3
4

10K_0804_8P4R_5%
@
F4_LED#
F1_LED#
FN_LED#

L C 20150309
8
7
6
5
RPC10
1
2
3
4

10K_0804_8P4R_5%

(delete RC349 , CMOS_ON pull high)

BT_ON
CP_BYPASS
PCH_TSOFF#

Security Classification
Issued Date 2014/05/07
LC Future Center Secret Data
Deciphered Date 2015/05/07
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Title

SKL(10/16):GPIO/CPU/MISC
Size Document Number
Custom
BE460_NM-A551
R ev
1.0
A

Date: Wednesday, August 05, 2015 Sheet 14 of 83

5 4 3 2 1
 5 4 3 2 1

i a l D

H13
G13
B17
A17
UC1H

PCIE/USB3/SATA

PCIE1_RXN/USB3_5_RXN
PCIE1_RXP/USB3_5_RXP
PCIE1_TXN/USB3_5_TXN
?
SKL_ULT

3D camera USB3.0 on board

SSIC / USB3
@

USB3_1_RXN
USB3_1_RXP
USB3_1_TXN
USB3_1_TXP
H8
G8
C13
D13

J6
USB3P1_RXN
USB3P1_RXP
USB3P1_TXN
USB3P1_TXP

USB3P2_RXN
USB3P1_RXN
USB3P1_RXP
USB3P1_TXN
USB3P1_TXP
[43]
[43]
[43]
[43] On Board (Right-Front)

n t
e
PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_1_RXN USB3P2_RXP USB3P2_RXN [43]
H6
G11 USB3_2_RXP/SSIC_1_RXP B13 USB3P2_TXN USB3P2_RXP [43]
F11 PCIE2_RXN/USB3_6_RXN USB3_2_TXN/SSIC_1_TXN A13 USB3P2_TXP USB3P2_TXN [43] On Board (Right-Back)
D16 PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_1_TXP USB3P2_TXP [43]
C16 PCIE2_TXN/USB3_6_TXN J10 USB3P3_RXN
PCIE2_TXP/USB3_6_TXP USB3_3_RXN/SSIC_2_RXN USB3P3_RXP USB3P3_RXN [57]
H10
PCIE3_CRX_DTX_N H16 USB3_3_RXP/SSIC_2_RXP B15 USB3P3_TXN USB3P3_RXP [57]
[56] PCIE3_CRX_DTX_N PCIE3_RXN
ChargerPort USB3_3_TXN/SSIC_2_TXN USB3P3_TXN [57] S/B (AOU Port)
PCIE3_CRX_DTX_P G16 A15 USB3P3_TXP

d
WLAN CC18
[56]
1
PCIE3_CRX_DTX_P
2 0.1U_0402_10V7-K PCIE3_CTX_DRX_N D17 PCIE3_RXP
WLAN USB3_3_TXP/SSIC_2_TXP USB3P3_TXP [57] 20141024
[56] PCIE3_CTX_C_DRX_N PCIE3_CTX_DRX_P PCIE3_TXN USB3P4_RE_RXN
CC19 1 2 0.1U_0402_10V7-K C17 E10
[56] PCIE3_CTX_C_DRX_P PCIE3_TXP USB3_4_RXN USB3P4_RE_RXP USB3P4_RE_RXN [36]
Docking F10
PCIE4_CRX_DTX_N G15 USB3_4_RXP C15 USB3P4_TXN USB3P4_RE_RXP [36]
[51] PCIE4_CRX_DTX_N USB3P4_TXN [36] Ddcking

i
PCIE4_CRX_DTX_P PCIE4_RXN USB3_4_TXN USB3P4_TXP
[51] PCIE4_CRX_DTX_P F15
PCIE4_RXP
LAN USB3_4_TXP
D15
USB3P4_TXP [36]
CC92 1 2 0.1U_0402_10V7-K PCIE4_CTX_DRX_N B19 20141024
[51] PCIE4_CTX_C_DRX_N PCIE4_CTX_DRX_P PCIE4_TXN USB20_N0
CC93 1 2 0.1U_0402_10V7-K A19 AB9
LAN [51] PCIE4_CTX_C_DRX_P PCIE4_TXP USB2N_1 AB10 USB20_P0 USB20_N0 [44]
On Board (Right-Front)
F16 USB2P_1 USB20_P0 [44]
PCIE5_RXN USB20_N1

f
C E16
PCIE5_RXP
On board USB2N_2
AD6
USB20_N1 [45]
C
C19 SKYLAKE-U_BGA1356 AD7 USB20_P1
D19 PCIE5_TXN USB2P_2 USB20_P1 [45] On Board (Right-Back)
PCIE5_TXP REV = 1 AH3 USB20_N2
G18 USB2N_3 AJ3 USB20_P2 USB20_N2 [57]
[57] PCIE6_CRX_DTX_N PCIE6_RXN
Sub/B Charger Port USB2P_3 USB20_P2 [57] S/B (AOU Port)
[57] PCIE6_CRX_DTX_P F18
1 2 0.1U_0402_10V7-K PCIE6_CTX_DRX_N D20 PCIE6_RXP 8 OF 20 AD9 USB20_N3
Card Reader [57] PCIE6_CTX_C_DRX_N
CC20
PCIE6_TXN
CR USB2N_4 USB20_N3 [38] USB Port Number
CC21 1 2 0.1U_0402_10V7-K PCIE6_CTX_DRX_P C20 ONE DOCK ? AD10 USB20_P3
DOCKING
[57] PCIE6_CTX_C_DRX_P PCIE6_TXP USB2P_4 USB20_P3 [38]

n
SATA_PRX_DTX_N0 USB20_N4_TPANEL
USB_OC0# Port 0, Port1
F20 AJ1
[41] SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 PCIE7_RXN/SATA0_RXN USB2N_5 USB20_P4_TPANEL USB20_N4_TPANEL [55]
[41] SATA_PRX_DTX_P0 E20
PCIE7_RXP/SATA0_RXP
Touch Panel USB2P_5
AJ2
USB20_P4_TPANEL [55] Touch Panel USB_OC1# Port 2, Port3
SATA_PTX_DRX_N0 B21 HDD
HDD [41] SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 A21 PCIE7_TXN/SATA0_TXN
USB2
AF6 USB20_N5
USB_OC2# Port 4, Port5
[41] SATA_PTX_DRX_P0 PCIE7_TXP/SATA0_TXP USB2N_6 USB20_P5 USB20_N5 [56]
BT AF7
G21 USB2P_6 USB20_P5 [56] BT
PCIE8_RXN/SATA1A_RXN USB20_N6
USB_OC3# Port 6, Port7
F21 AH1
PCIE8_RXP/SATA1A_RXP USB2N_7 USB20_N6 [42]

o
D21 ODD(NGFF) Camera AH2 USB20_P6
ODD, only for 15" C21 PCIE8_TXN/SATA1A_TXN USB2P_7 USB20_P6 [42] CAMERA
PCIE8_TXP/SATA1A_TXP AF8 USB20_N8
PCIE_CRX_GTX_N0 E22 USB2N_8 AF9 USB20_P8 USB20_N8 [54]
[24] PCIE_CRX_GTX_N0 PCIE9_RXN
FPR USB2P_8 USB20_P8 [54] FPR
PCIE_CRX_GTX_P0 E23
[24] PCIE_CRX_GTX_P0 PCIE1_PTX_DRX_N0 PCIE9_RXP
CC86 DIS@ 1 2 0.1U_0402_10V7-K B23 AG1
[24] PCIE_CTX_C_GRX_N0 PCIE1_PTX_DRX_P0 PCIE9_TXN USB2N_9
CC87 DIS@ 1 2 0.1U_0402_10V7-K A23 AG2
[24] PCIE_CTX_C_GRX_P0 PCIE9_TXP USB2P_9
PCIE_CRX_GTX_N1 F25 AH7
[24] PCIE_CRX_GTX_N1 PCIE_CRX_GTX_P1 PCIE10_RXN USB2N_10
[24] PCIE_CRX_GTX_P1 E25
PCIE10_RXP
Smart Card USB2P_10
AH8 SMART CARD (Hub)
CC88 DIS@ 1 2 0.1U_0402_10V7-K PCIE2_PTX_DRX_N1 D23

C
[24] PCIE_CTX_C_GRX_N1 PCIE2_PTX_DRX_P1 PCIE10_TXN
CC89 DIS@ 1 2 0.1U_0402_10V7-K C23 AB6 USBCOMP RC359 1 2 113_0402_1%
[24] PCIE_CTX_C_GRX_P1 PCIE10_TXP USB2_COMP
100_0402_1% AG3 RC385 1 2 1K_0402_5% [SKL PDG]USBCOMP:112.5 ohm ± 1 %connect ed t o GND
1 2 PCIE_RCOMP F5 USB2_ID AG4 RC386 1 2 1K_0402_5%
RC360
PCIE_RCOMPN
GPU USB2_VBUSSENSE
E5 20150519 20141121
PCIE_RCOMPP A9 USB_OC0#
XDP_PRDY_N GPP_E9/USB2_OC0# USB_OC1# USB_OC0# [44]
20141124 TP115 1 D56 C9
XDP_PREQ_N PROC_PRDY# GPP_E10/USB2_OC1# USB_OC2# USB_OC1# [57]
@ TP116 1 D61 D9
RC384 1 2 0_0402_5% DGPU_PWROK_R BB11 PROC_PREQ# GPP_E11/USB2_OC2# B9 USB_OC3#
[14,33,79] DGPU_PWROK GPP_A7/PIRQA# GPP_E12/USB2_OC3#
GPU PCIE_CRX_GTX_N2 E28 J1 HDD_DEVSLP0 TP117 +3VALW_PCH
[24] PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P2 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 SSD_DEVSLP1 HDD_DEVSLP0 [41]
[24] PCIE_CRX_GTX_P2 E27 J2 1
B
CC90 DIS@ 1 2 0.1U_0402_10V7-K PCIE3_PTX_DRX_N2 D24 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 J3 B
[24] PCIE_CTX_C_GRX_N2 PCIE3_PTX_DRX_P2 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2
CC23 DIS@ 1 2 0.1U_0402_10V7-K C24
[24] PCIE_CTX_C_GRX_P2 PCIE_CRX_GTX_N3 PCIE11_TXP/SATA1B_TXP GPP_E0
[24] PCIE_CRX_GTX_N3 E30 H2 RC368
PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0

C
PCIE_CRX_GTX_P3 F30 H3 ONEDOCK_DET# 1 2
[24] PCIE_CRX_GTX_P3 PCIE4_PTX_DRX_N3 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 ONEDOCK_DET#
CC24 DIS@ 1 2 0.1U_0402_10V7-K A25 G4
[24] PCIE_CTX_C_GRX_N3 PCIE4_PTX_DRX_P3 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2 ONEDOCK_DET# [38]
CC91 DIS@ 1 2 0.1U_0402_10V7-K B25 10K_0402_5%
[24] PCIE_CTX_C_GRX_P3 PCIE12_TXP/SATA2_TXP H1
GPP_E8/SATALED#

F
[SKL PDG]PCIE_RCOMP
RPC15
1.100 ohm +/-0.1% external resistor between RCOMPP/RCOMPN USB_OC2# 8 1
USB_OC1# 7 2
USB_OC0#
2.SATA compensat i on ci rcui t i s code s har e wit h USB_OC3#
6 3
5 4
PCIE_RCOMPP/N dif f er ent ial pair. Refer to PCI Express
Design Guidelines chapter for PCIE_RCOMPP/N guideline. 10K_0804_8P4R_5%

3.Width:12~15Mil

C
Space:>12Mil
Length:Both RCOMP & RCOMPN need to matched to less than 1% trace and board [SKL PDG] OC [x] pins require a pull-up to VccSus3_3 with 8.2~10 Kohm resistors

[SKL PCH EDS]no external pull-up or pull-down termination

required when used as DEVSLP
+3VS

L
HDD_DEVSLP0 RC88 2 1 10K_0402_5%
GPP_E0 RC388 2 1 10K_0402_5%

A 20150519 A
DGPU_PWROK_R RC408 2 1 10K_0402_5%

20150714

Security Classification LC Future Center Secret Data Title

Issued Date 2014/05/07 Deciphered Date 2015/05/07 SKL(11/16):PCIE/USB/SATA

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 15 of 83
5 4 3 2 1
 5 4 3 2 1

SKL_ULT ?
UC1L @ +VCC_ST +VCC_ST
+VCC_CORE +VCC_CORE +VCC_ST [SKL PDG]VIDSCK [SKL PDG]VIDALERT# [SKL PDG]VIDSOUT
CPU POWER 1 OF 4

A30 G32 Rpu1 Rpu2

VCC_A30 VCC_G32

1
A34 G33 Rpu1
A39 VCC_A34 VCC_G33 G35 RC20

l
A44 VCC_A39 VCC_G35 G37 @ RC356 56_0402_1% RC355
AK33 VCC_A44 VCC_G37 G38
VCC_AK33 VCC_G38
100_0402_1% Rs1 100_0402_1%
AK35 G40

2
AK37 VCC_AK35 VCC_G40 G42 VR_SVID_CLK VR_SVID_ALRT#_R 1 2 VR_SVID_ALRT# VR_SVID_DAT
AK38 VCC_AK37 VCC_G42 J30 VR_SVID_CLK [74] VR_SVID_ALRT# [74] VR_SVID_DAT [74]
RC19 220_0402_1%
AK40 VCC_AK38 VCC_J30 J33

a
AL33 VCC_AK40 VCC_J33 J37
AL37 VCC_AL33 VCC_J37 J40
VCC_AL37 VCC_J40 20150305 +VCC_CORE 20150305
AL40 K33
D AM32 VCC_AL40 VCC_K33 K35 D

it
VCC_AM32 VCC_K35

1
AM33 K37
AM35 VCC_AM33 VCC_K37 K38 RC120
AM37 VCC_AM35 VCC_K38 K40 100_0402_1%
AM38 VCC_AM37 VCC_K40 K42
G30 VCC_AM38 VCC_K42 K43

2
VCC_G30 VCC_K43
K32 E32 RC121 1 @ 2 0_0402_5%
RSVD_K32 VCC_SENSE E33 1 2 VCC_SENSE [74]
RC142 @ 0_0402_5%
AK32 VSS_SENSE VSS_SENSE [74]
RSVD_AK32

1
B63 VR_SVID_ALRT#_R
VIDALERT#

n
AB62 A63 VR_SVID_CLK 20150309
P62 VCCOPC_AB62 VIDSCK D64 VR_SVID_DAT RC143
V62 VCCOPC_P62 VIDSOUT 100_0402_1%
VCCOPC_V62 G20
+VCC_STG

2
H63 VCCSTG_G20
VCC_OPC_1P8_H63
20141126

e
G61 [SKL PDDG]Package Sensing Recommendations
VCC_OPC_1P8_G61 12 OF 20
SKYLAKE-U_BGA1356
AC63 REV = 1 1.Trace Length
? Match: <25mil
AE63 VCCOPC_SENSE 2.Space: >25mil
VSSOPC_SENSE
AE62
3.Trace impedance:50ohm
AG62 VCCEOPIO_AE62 4.Sense traces should be referenced to a solid ground plane

d
VCCEOPIO_AG62 5.Avoid crossing over plane splits
AL63
AJ62 VCCEOPIO_SENSE
VSSEOPIO_SENSE
[SKL PDG]SVID

if
1.Alert signal must be routed between Clk and Data signals to
minimize Cross-Talk.
C @ +VCC_GT C
SKL_ULT ?
+VCC_GT UC1M
CPU POWER 2 OF 4
Primary side cap +1.35V
N70
A48 VCCGT_N70 N71 +VCC_IO Here were 4 Cap of 1U_0402, directly delete it.
A53 VCCGT_A48 VCCGT_N71 R63 [SKL PDG]VCCIO

n
A58 VCCGT_A53 VCCGT_R63

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M
R64 [SKL PDG]VDDQ [SKL PDG]10uF x2, 1uF x8
A62 VCCGT_A58 VCCGT_R64 R65 [SKL PDG]10uF x6, 1uF x4
A66 VCCGT_A62 VCCGT_R65

1
CC209

CC205

CC206

CC207

CC208

10U_0603_6.3V6-M

10U_0603_6.3V6-M
R66
AA63 VCCGT_A66 VCCGT_R66

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M
R67 1 1 1 1
AA64 VCCGT_AA63 VCCGT_R67

1
CC212

CC211

CC336

CC337

CC338

CC339
R68

2
AA66 VCCGT_AA64 VCCGT_R68 R69
AA67 VCCGT_AA66 VCCGT_R69 R70 ?
UC1N SKL_ULT @

2
AA69 VCCGT_AA67 VCCGT_R70 R71 2 2 2 2
CPU POWER 3 OF 4
AA70 VCCGT_AA69 VCCGT_R71 T62
20141126 AA71 VCCGT_AA70 VCCGT_T62

10U_0603_6.3V6-M
U65 AU23 AK28
AC64 VCCGT_AA71 VCCGT_U65 VDDQ_AU23 VCCIO_AK28

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M
U68 1 1 1 1 AU28 AK30
AC65 VCCGT_AC64 VCCGT_U68 VDDQ_AU28 VCCIO_AK30

1
CC210

CC340

CC341

CC342

CC343
U71 AU35 AL30 +VCC_SA Primary side cap
AC66 VCCGT_AC65 VCCGT_U71 W63 AU42 VDDQ_AU35 VCCIO_AL30 AL42 [SKL PDG]VCCSA
AC67 VCCGT_AC66 VCCGT_W63 W64 BB23 VDDQ_AU42 VCCIO_AL42 AM28 [SKL PDG]10uF x13, 1uF x7

2
AC68 VCCGT_AC67 VCCGT_W64 2 2 2 2 VDDQ_BB23 VCCIO_AM28

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M
W65 BB32 AM30
AC69 VCCGT_AC68 VCCGT_W65 W66 BB41 VDDQ_BB32 VCCIO_AM30 AM42

C
AC70 VCCGT_AC69 VCCGT_W66 VDDQ_BB41 VCCIO_AM42

1
CC213

CC214

CC215

CC216

CC217

CC218

CC219

CC220

CC221

CC222
W67 BB47
+VCC_STG +VCC_ST +VCC_ST AC71 VCCGT_AC70 VCCGT_W67 W68 BB51 VDDQ_BB47 AK23
J43 VCCGT_AC71 VCCGT_W68 W69 VDDQ_BB51 VCCSA_AK23 AK25

2
J45 VCCGT_J43 VCCGT_W69 W70 VCCSA_AK25 G23 @ @ @ @ @ @
J46 VCCGT_J45 VCCGT_W70 W71 AM40 VCCSA_G23 G25
+1.35V
J48 VCCGT_J46 VCCGT_W71 VDDQC VCCSA_G25
1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1 1 1 Y62 G27
J50 VCCGT_J48 VCCGT_Y62 VCCSA_G27
CC68

CC69

CC70

A18 G28
+VCC_ST
J52 VCCGT_J50 VCCST VCCSA_G28

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M
J22
J53 VCCGT_J52 VCCSA_J22

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M
20150309 AK42 A22 J23 1 1 1 1 1 1 1
+VCC_STG
J55 VCCGT_J53 VCCGTX_AK42 AK43 VCCSTG_A22 VCCSA_J23

1
2 2 2

CC223

CC224

CC225

CC329

CC330

CC331

CC332

CC333

CC334

CC335
B J27 B
J56 VCCGT_J55 VCCGTX_AK43 AK45 AL23 VCCSA_J27 K23
VCCGT_J56 13 OFAK46
VCCGTX_AK45 20 +1.35V VCCPLL_OC VCCSA_K23
Primary side cap J58 SKYLAKE-U_BGA1356 K25

2
VCCGT_J58 VCCGTX_AK46 AK48 VCCSA_K25

C
J60 REV K20 K27 2 2 2 2 2 2 2
Primary side cap =1 ? +VCC_ST
[SKL PDG]VCCPLL K48 VCCGT_J60 VCCGTX_AK48 AK50 K21 VCCPLL_K20 VCCSA_K27 K28
[SKL PDG]VCCSTG [SKL PDG]VCCST [SKL PDG]1uF x1 K50 VCCGT_K48 VCCGTX_AK50 AK52 VCCPLL_K21 VCCSA_K28 K30
[SKL PDG]1uF x1 [SKL PDG]1uF x1 Close to K20,K21 K52 VCCGT_K50 VCCGTX_AK52 AK53 VCCSA_K30
K53 VCCGT_K52 VCCGTX_AK53 AK55 VCCIO_SENSE RC192
AM23 1 2 100_0402_1%
+VCC_IO
K55 VCCGT_K53 VCCGTX_AK55 AK56 VCCIO_SENSE VSSIO_SENSE RC189
AM22 1 2 100_0402_1%
+1.35V +1.35V K56 VCCGT_K55 VCCGTX_AK56 AK58 VSSIO_SENSE
K58 VCCGT_K56 VCCGTX_AK58 AK60 H21 RC126 1 @ 2 0_0402_5% VSSSA_SENSE 20141224 VSSSA_SENSE

F
K60 VCCGT_K58 VCCGTX_AK60 AK70 VSSSA_SENSE H20 1 2 VCCSA_SENSE [74]
RC185 @ 0_0402_5%
L62 VCCGT_K60 VCCGTX_AK70 AL43 VCCSA_SENSE VCCSA_SENSE [74]
L63 VCCGT_L62 VCCGTX_AL43 AL46
1U_0402_10V6K

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1 1 1 14 OF 20
L64 VCCGT_L63 VCCGTX_AL46 AL50
CC94

CC344

CC526

SKYLAKE-U_BGA1356 +VCC_SA
L65 VCCGT_L64 VCCGTX_AL50 AL53 20141126 REV = 1 ?
20150309 L66 VCCGT_L65 VCCGTX_AL53 AL56
L67 VCCGT_L66 VCCGTX_AL56 AL60

1
2 2 2
L68 VCCGT_L67 VCCGTX_AL60 AM48 RC370
Primary side cap L69 VCCGT_L68 VCCGTX_AM48 AM50 100_0402_1%

C
+VCC_GT L70 VCCGT_L69 VCCGTX_AM50 AM52
[SKL PDG]VCCPLL L71 VCCGT_L70 VCCGTX_AM52 AM53

2
[SKL PDG]VDDQC [SKL PDG]1uF x1 M62 VCCGT_L71 VCCGTX_AM53 AM56 VCCSA_SENSE
N63 VCCGT_M62 VCCGTX_AM56 AM58
1

[SKL PDG]1uF x1 Close to AL23

RC125 N64 VCCGT_N63 VCCGTX_AM58 AU58
100_0402_1% N66 VCCGT_N64 VCCGTX_AU58 AU63 VSSSA_SENSE
N67 VCCGT_N66 VCCGTX_AU63 BB57
N69 VCCGT_N67 VCCGTX_BB57 BB66

1
L
2

VCCGT_N69 VCCGTX_BB66
RC124 1 @ 2 0_0402_5% J70 AK62 RC369
[74] VCCGT_SENSE
RC183 1 @ 2 0_0402_5% J69 VCCGT_SENSE VCCGTX_SENSE AL61 100_0402_1%
[74] VSSGT_SENSE VSSGT_SENSE VSSGTX_SENSE

2
1

A A

RC184
100_0402_1%
2

Security Classification LC Future Center Secret Data Title

Issued Date 2014/05/07 Deciphered Date 2015/05/07 SKL(12/16):POWER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 16 of 83
5 4 3 2 1
 5 4 3 2 1

85mA
+3VALW _PCH
20150526 20150526

1U_0201_6.3V6

1U_0201_6.3V6

1U_0201_6.3V6
SKL_ULT @ 1 1 1
?

CC530

CC531

CC532
UC1O
20150526
SRAM Primary Well 1.0 V. Dedicated SRAM rail and can CPU POWER 4 OF 4
have on board power down gate control. VccMPHYGT(Mod PHY Externally Gated Primary 1.0 V: Externally gated AB19 2 2 2
primary supply for PCIe/DMI/USB3/SATA/MIPI MPHY logic.) +1VALW_PCH VCCPRIM_1P0_AB19

l
AB20 1100mA AK15
+VCC_MPHYGT +VCC_MPHYGT P18 VCCPRIM_1P0_AB20 VCCPGPPA AG15
2 VCCPRIM_1P0_P18 VCCPGPPB
+VCC_MPHYGT Y16 Near AG15 Near Y16 Near T16
2015/03/12 2015/03/12 20150520 AF18 VCCPGPPC Y15
2015/03/12
CC535 +PCH_CORE
AF19 VCCPRIM_CORE_AF18 VCCPGPPD T16
135mA
CC47 close to AF20 CC58 close to N18 1
47UF_0805_6.3V 2
V20 VCCPRIM_CORE_AF19 VCCPGPPE AF16
161mA +1VALW _PCH
1 600mA +1.8VALW_PCH

1U_0201_6.3V6
CC50 & C194 close to N15 20150520 CC536 V21 VCCPRIM_CORE_V20 VCCPGPPF AD15
1 VCCPRIM_CORE_V21 VCCPGPPG

1U_0201_6.3V6
CC47
[SKL PDG]VccSRAM [SKL PDG]VccMPHYGT 20150520 47UF_0805_6.3V
1

CC52

1U_0201_6.3V6
[SKL PDG]1uF x1 20150526 [SKL PDG]VccAPLLEBB 20150526 [SKL PDG]1uF x1
1 1 +DCPDSW AL1 22mA V19
2 DCPDSW_1P0 VCCPRIM_3P3_V19 +3VALW _PRIM

CC50

47UF_0805_6.3V

C194
[SKL PDG]Close AF20, [SKL PDG]1uF x1 [SKL PDG]Close N15,
Placement type:Edge<10mm(394mil) [SKL PDG]Close N18, 2 Placement type:Edge<3mm(118mil) 20150526 K17 T1

a
Placement type:Edge<3mm(118mil) L1 VCCMPHYAON_1P0_K17 VCCPRIM_1P0_T1
[SKL PDG]47uF x1 2 2 VCCMPHYAON_1P0_L1 AA1
D VCCATS_1P8 +1.8VALW_PCH D
[SKL PDG]Close N15, N15
Placement type:Edge<10mm(394mil) +VCC_MPHYGT VCCMPHYGT_1P0_N15
N16 AK17
VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3 +3VALW _RTCPRIM
N17 1500mA
Mod PHY Always On Primary 1.0 V: Always on primary P15 VCCMPHYGT_1P0_N17 AK19
supply for PCIe/DMI/USB3/SATA/MIPI MPHY logic VCCMPHYGT_1P0_P15 VCCRTC_AK19 +RTCVCC
P16 BB14

i
+1VALW_PCH VCCMPHYGT_1P0_P16 VCCRTC_BB14
+VCC_AMPHYPLL K15 BB10 +DCPRTC
+1VALW_PLL L15 VCCAMPHYPLL_1P0_K15 DCPRTC
CC49 close to K17 VCCAMPHYPLL_1P0_L15 88mA A14
+1VALW_PLL V15 VCCCLK1 0 ohm
RF_NS@
VCCAPLL_1P0 26mA K19 +1VALW _CLK2 LC3

1U_0201_6.3V6

0.1U_0402_10V6-K
1 1 1 @ 2 0_0805_5%
20150520

t
VCCCLK2

CC49
AB17
VCCPRIM_1P0_AB17

CC539
[SKL PDG]VccMPHYAON 20150526 Y18 L21
[SKL PDG]1uF x1 VCCPRIM_1P0_Y18 VCCCLK3 0 ohm
2015/03/12 [SKL PDG]Close K17, 2 2 AD17 N20 +1VALW _CLK4 LC4 1 @ 2 0_0805_5%
20150520
Placement type:Edge<3mm(118mil) +VCC_DSW 3P3 VCCDSW_3P3_AD17 VCCCLK4
LC1 close to K15 AD18 118mA 0 ohm
20150520 AJ17 VCCDSW_3P3_AD18 L19 +1VALW _CLK5 1 2 0_0805_5%
20150520
LC5 @
0 ohm VCCDSW_3P3_AJ17 VCCCLK5
1 +VCC_AMPHYPLL
2 0_0805_5% AJ19 A10
+VCC_MPHYGT LC1 @ +VCC_HDA VCCHDA 68mA VCCCLK6
+VCC_HDA AJ16 AN11 1
+3V_SPI VCCSPI GPP_B0/CORE_VID0 T56
0 ohm 20150520 RF_NS@ AN13
+1VALW _PLL GPP_B1/CORE_VID1

0.1U_0402_10V6-K
LC2 1 @ 2 0_0805_5% AF20
+1VALW _PCH 1 20150526 20141208

n
AF21 VCCSRAM_1P0_AF20
Reserve for Sense Resistor VCCSRAM_1P0_AF21

CC540
Primary Well 1.0 V: For I/O blocks, ungated ISH SRAM T19 565mA [SKL PDG]The CORE_VID[0:1] signal is used by
LC2 close to V15 power, USB AFE Digital Logic, JTAG, Thermal Sensor and T20 VCCSRAM_1P0_T19
+1.8VALW +1.8VALW_PCH MIPI DPHY. 2 VCCSRAM_1P0_T20 external VRs to indicate the final settling
AJ21
voltage for VCCPRIM_CORE rail.
RC173 1
@
2 0_0603_5%
+1VALW_PCH +3VALW_PRIM VCCPRIM_3P3_AJ21 75mA
2015/03/12 AK20 33mA
+3VALW +3VALW _PCH VCCPRIM_1P0_AK20
CC95 close to AB19 N18
+VCC_AMPHYPLL VCCAPLLEBB 33mA

1U_0201_6.3V6
RC341 1 @ 2 0_0805_5% 1

CC95
e
20150526
@ +1VALW +1VALW _PCH SKYLAKE-U_BGA1356 15 OF 20 ?
2
1U_0201_6.3V6

[SKL PDG]VCCPRIM REV = 1

1
CC46

RC176 1 @ 2 0_0805_5% [SKL PDG]1uF x1

20150526
20141205 [SKL PDG]Close AB19,
Placement type:Edge<10mm(394mil)
2 +1VALW +VCC_MPHYGT
JC2
1 2
1 2

JUMP_43X118

d
@
Thermal Sensor Primary Well 1.8 V Deep Sx Well 1.0 V: This rail is generated by on die DSW RTC de-coupling capacitor only. This rail should NOT
20150311 +1.8VALW_PCH low dropout (LDO) linear voltage regulator to supply DSW be driven.
GPIOs, DSW core logic and DSW USB2 logic. Board needs to
connect 1 uF capacitor to this rail and power should NOT
C be driven from the board. When primary well power is up, +DCPRTC C
this rail is bypassed from VCCPRIM_1p0.

1U_0201_6.3V6
1 1

CC61
20150526 +DCPDSW 20150526 C197
0.1U_0201_6.3V6K

1U_0201_6.3V6
[SKL PDG]VccATS [SKL PDG]DcpDSW [SKL PDG]DcpRTC
2 1 2

CC60
[SKL PDG]1uF x1 [SKL PDG]1uF x1 20150526 [SKL PDG]0.1uF x1
[SKL PDG]Close AA1, [SKL PDG]Close AL1, [SKL PDG]Close BB10,
Placement type:Edge<10mm(394mil) Placement type:Edge<3mm(118mil) Placement type:Edge<3mm(118mil)

f
2

Core Logic Primary Well: This rail scales from 0.85 V Primary Well 3.3 V RTC Logic Primary Well 3.3 V. This power supplies the RTC RTC Logic Primary Well 3.3 V. This power supplies
to 1.0 V. internal VRM. It will be off during Deep Sx mode. the RTC internal VRM. It will be off during Deep
+3VALW_PCH Sx mode.
+PCH_CORE +3VALW_PRIM
+1VALW_PCH +3VALW _PCH +3VALW _RTCPRIM
+RTCVCC
20141205 RC326 1 @ 2 0_0402_5% RC333 1 @ 2 0_0402_5%
RC304 1 2 20150526 2015052620150526
0_0805_5%

1U_0201_6.3V6

1U_0201_6.3V6

1U_0201_6.3V6

0.1U_0201_6.3V6K

0.1U_0201_6.3V6K

1U_0201_6.3V6
[SKL PDG]VccPRIM_Core 20150526

n
1 1 1 1 1 1

CC96

CC97

CC58

C200

C201

CC59
[SKL PDG]1uF x1 [SKL PDG]VCCPRIM [SKL PDG]VccRTC
[SKL PDG]Close AF18, [SKL PDG]1uF x1 [SKL PDG]VccRTCPRIM [SKL PDG]1uF x1
Placement type:Edge<10mm(394mil) [SKL PDG]Close V19, [SKL PDG]1uF x1,0.1uF x2 [SKL PDG]Close AK19,
20150526 2 Placement type:Edge<3mm(118mil) 20150526 2 [SKL PDG]Close AK17, 2 2 2 Placement type:Edge<3mm(118mil) 2
Placement type:Edge<3mm(118mil)

HD Audio Power 3.3 V, 1.8 V, 1.5 V. For Intel High Deep Sx Well for GPD GPIOs and USB2
Definition Audio.

+3VALW_PCH

o
+VCC_HDA

+3VL RC1271 @ 2 0_0402_5%

+VCC_DSW 3P3
RC330 1 @ 2 0_0402_5%

+3VALW _PCH RC1321 @ 2 0_0402_5%

1U_0201_6.3V6
[SKL PDG]VccHDA
1

CC99
[SKL PDG]1uF x1
[SKL PDG]Close AJ19, 20150526
Placement type:Edge<10mm(394mil) [SKL PDG]VccDSW
2

C
B B

20141205

F C
C
A A

L
Security Classification LC Future Center Secret Data Title

Issued Date 2014/05/07 Deciphered Date 2015/05/07 SKL(13/16):POWER

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 17 of 83
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

SKL_ULT
UC1P
@
? SKL_ULT
UC1Q
@
?
?

it al D

n
SKL_ULT
UC1R @
GND 1 OF 3 GND 2 OF 3
GND 3 OF 3
A5 AL65 AT63 BA49 F8 L18
A67 VSS_A5 VSS_AL65 AL66 AT68 VSS_AT63 VSS_BA49 BA53 G10 VSS_F8 VSS_L18 L2
A70 VSS_A67 VSS_AL66 AM13 AT71 VSS_AT68 VSS_BA53 BA57 G22 VSS_G10 VSS_L2 L20
AA2 VSS_A70 VSS_AM13 AU10 VSS_AT71 VSS_BA57 G43 VSS_G22 VSS_L20

e
AM21 BA6 L4
AA4 VSS_AA2 VSS_AM21 AM25 AU15 VSS_AU10 VSS_BA6 BA62 G45 VSS_G43 VSS_L4 L8
AA65 VSS_AA4 VSS_AM25 AM27 AU20 VSS_AU15 VSS_BA62 BA66 G48 VSS_G45 VSS_L8 N10
AA68 VSS_AA65 VSS_AM27 AM43 AU32 VSS_AU20 VSS_BA66 BA71 G5 VSS_G48 VSS_N10 N13
AB15 VSS_AA68 VSS_AM43 AM45 AU38 VSS_AU32 VSS_BA71 BB18 G52 VSS_G5 VSS_N13 N19
AB16 VSS_AB15 VSS_AM45 AM46 AV1 VSS_AU38 VSS_BB18 BB26 G55 VSS_G52 VSS_N19 N21
AB18 VSS_AB16 VSS_AM46 AM55 AV68 VSS_AV1 VSS_BB26 BB30 G58 VSS_G55 VSS_N21 N6

d
AB21 VSS_AB18 VSS_AM55 AM60 AV69 VSS_AV68 VSS_BB30 BB34 G6 VSS_G58 VSS_N6 N65
AB8 VSS_AB21 VSS_AM60 AM61 AV70 VSS_AV69 VSS_BB34 BB38 G60 VSS_G6 VSS_N65 N68
AD13 VSS_AB8 VSS_AM61 AM68 AV71 VSS_AV70 VSS_BB38 BB43 G63 VSS_G60 VSS_N68 P17
AD16 VSS_AD13 VSS_AM68 AM71 AW10 VSS_AV71 VSS_BB43 BB55 G66 VSS_G63 VSS_P17 P19

if
AD19 VSS_AD16 VSS_AM71 AM8 AW12 VSS_AW10 VSS_BB55 BB6 H15 VSS_G66 VSS_P19 P20
AD20 VSS_AD19 VSS_AM8 AN20 AW14 VSS_AW12 VSS_BB6 BB60 H18 VSS_H15 VSS_P20 P21
AD21 VSS_AD20 VSS_AN20 AN23 AW16 VSS_AW14 VSS_BB60 BB64 H71 VSS_H18 VSS_P21 R13
AD62 VSS_AD21 VSS_AN23 AN28 AW18 VSS_AW16 VSS_BB64 BB67 J11 VSS_H71 VSS_R13 R6
C AD8 VSS_AD62 VSS_AN28 AN30 AW21 VSS_AW18 VSS_BB67 BB70 J13 VSS_J11 VSS_R6 T15 C
AE64 VSS_AD8 VSS_AN30 AN32 AW23 VSS_AW21 VSS_BB70 C1 J25 VSS_J13 VSS_T15 T17
AE65 VSS_AE64 VSS_AN32 AN33 AW26 VSS_AW23 VSS_C1 C25 J28 VSS_J25 VSS_T17 T18
AE66 VSS_AE65 VSS_AN33 AN35 AW28 VSS_AW26 VSS_C25 C5 J32 VSS_J28 VSS_T18 T2
AE67 VSS_AE66 VSS_AN35 AN37 AW30 VSS_AW28 VSS_C5 D10 J35 VSS_J32 VSS_T2 T21
AE68 VSS_AE67 VSS_AN37 AN38 AW32 VSS_AW30 VSS_D10 D11 J38 VSS_J35 VSS_T21 T4
AE69 VSS_AE68 VSS_AN38 AN40 AW34 VSS_AW32 VSS_D11 D14 J42 VSS_J38 VSS_T4 U10

n
AF1 VSS_AE69 VSS_AN40 AN42 AW36 VSS_AW34 VSS_D14 D18 J8 VSS_J42 VSS_U10 U63
AF10 VSS_AF1 VSS_AN42 AN58 AW38 VSS_AW36 VSS_D18 D22 K16 VSS_J8 VSS_U63 U64
AF15 VSS_AF10 VSS_AN58 AN63 AW41 VSS_AW38 VSS_D22 D25 K18 VSS_K16 VSS_U64 U66
AF17 VSS_AF15 VSS_AN63 AP10 AW43 VSS_AW41 VSS_D25 D26 K22 VSS_K18 VSS_U66 U67
VSS_AF17 VSS_AP10
AF2 SKYLAKE-U_BGA1356 AP18 16 OF 20 VSS_AW43
AW45 SKYLAKE-U_BGA1356 VSS_D26 D30 17 OF 20 K61 VSS_K22 VSS_U67 U69
VSS_AF2
AF4 REV = 1 VSS_AP18 AP20 VSS_AW45
AW47 REV = 1 VSS_D30 D34 K63 SKYLAKE-U_BGA1356 VSS_U69
VSS_K61 U70 18 OF 20
? ?
AF63 VSS_AF4 VSS_AP20 AP23 AW49 VSS_AW47 VSS_D34 D39 VSS_K63
K64 REV = 1 VSS_U70 V16 ?

o
AG16 VSS_AF63 VSS_AP23 AP28 AW51 VSS_AW49 VSS_D39 D44 K65 VSS_K64 VSS_V16 V17
AG17 VSS_AG16 VSS_AP28 AP32 AW53 VSS_AW51 VSS_D44 D45 K66 VSS_K65 VSS_V17 V18
AG18 VSS_AG17 VSS_AP32 AP35 AW55 VSS_AW53 VSS_D45 D47 K67 VSS_K66 VSS_V18 W13
AG19 VSS_AG18 VSS_AP35 AP38 AW57 VSS_AW55 VSS_D47 D48 K68 VSS_K67 VSS_W13 W6
AG20 VSS_AG19 VSS_AP38 AP42 AW6 VSS_AW57 VSS_D48 D53 K70 VSS_K68 VSS_W6 W9
AG21 VSS_AG20 VSS_AP42 AP58 AW60 VSS_AW6 VSS_D53 D58 K71 VSS_K70 VSS_W9 Y17
AG71 VSS_AG21 VSS_AP58 AP63 AW62 VSS_AW60 VSS_D58 D6 L11 VSS_K71 VSS_Y17 Y19
AH13 VSS_AG71 VSS_AP63 AP68 AW64 VSS_AW62 VSS_D6 D62 L16 VSS_L11 VSS_Y19 Y20
AH6 VSS_AH13 VSS_AP68 AP70 AW66 VSS_AW64 VSS_D62 D66 L17 VSS_L16 VSS_Y20 Y21

C
AH63 VSS_AH6 VSS_AP70 AR11 AW8 VSS_AW66 VSS_D66 D69 VSS_L17 VSS_Y21
AH64 VSS_AH63 VSS_AR11 AR15 AY66 VSS_AW8 VSS_D69 E11
AH67 VSS_AH64 VSS_AR15 AR16 B10 VSS_AY66 VSS_E11 E15
AJ15 VSS_AH67 VSS_AR16 AR20 B14 VSS_B10 VSS_E15 E18
AJ18 VSS_AJ15 VSS_AR20 AR23 B18 VSS_B14 VSS_E18 E21
AJ20 VSS_AJ18 VSS_AR23 AR28 B22 VSS_B18 VSS_E21 E46
AJ4 VSS_AJ20 VSS_AR28 AR35 B30 VSS_B22 VSS_E46 E50
AK11 VSS_AJ4 VSS_AR35 AR42 B34 VSS_B30 VSS_E50 E53
AK16 VSS_AK11 VSS_AR42 AR43 B39 VSS_B34 VSS_E53 E56
B AK18 VSS_AK16 VSS_AR43 AR45 B44 VSS_B39 VSS_E56 E6 B
AK21 VSS_AK18 VSS_AR45 AR46 B48 VSS_B44 VSS_E6 E65
AK22 VSS_AK21 VSS_AR46 AR48 B53 VSS_B48 VSS_E65 E71
VSS_AK22 VSS_AR48 VSS_B53 VSS_E71

C
AK27 AR5 B58 F1
AK63 VSS_AK27 VSS_AR5 AR50 B62 VSS_B58 VSS_F1 F13
AK68 VSS_AK63 VSS_AR50 AR52 B66 VSS_B62 VSS_F13 F2
AK69 VSS_AK68 VSS_AR52 AR53 B71 VSS_B66 VSS_F2 F22
AK8 VSS_AK69 VSS_AR53 AR55 BA1 VSS_B71 VSS_F22 F23
AL2 VSS_AK8 VSS_AR55 AR58 BA10 VSS_BA1 VSS_F23 F27
AL28 VSS_AL2 VSS_AR58 AR63 BA14 VSS_BA10 VSS_F27 F28
AL32 VSS_AL28 VSS_AR63 AR8 BA18 VSS_BA14 VSS_F28 F32

F
AL35 VSS_AL32 VSS_AR8 AT2 BA2 VSS_BA18 VSS_F32 F33
AL38 VSS_AL35 VSS_AT2 AT20 BA23 VSS_BA2 VSS_F33 F35
AL4 VSS_AL38 VSS_AT20 AT23 BA28 VSS_BA23 VSS_F35 F37
AL45 VSS_AL4 VSS_AT23 AT28 BA32 VSS_BA28 VSS_F37 F38
AL48 VSS_AL45 VSS_AT28 AT35 BA36 VSS_BA32 VSS_F38 F4
AL52 VSS_AL48 VSS_AT35 AT4 F68 VSS_BA36 VSS_F4 F40
AL55 VSS_AL52 VSS_AT4 AT42 BA45 VSS_F68 VSS_F40 F42
AL58 VSS_AL55 VSS_AT42 AT56 VSS_BA45 VSS_F42 BA41
AL64 VSS_AL58 VSS_AT56 AT58 VSS_BA41

C
VSS_AL64 VSS_AT58

5
L 4
Security Classification
Issued Date 2014/05/07
LC Future Center Secret Data
Deciphered Date 2015/05/07
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3 2
Title

Custom

Date:
SKL(14/16):GND
Size Document Number
BE460_NM-A551
Wednesday, August 05, 2015

1
Sheet 18 of 83
R ev
1.0
A
 5 4 3 2 1

i a l D

n t
e
@
SKL_ULT ?
UC1I

CSI-2

A36 C37
B36 CSI2_DN0 CSI2_CLKN0 D37

d
C38 CSI2_DP0 CSI2_CLKP0 C32
D38 CSI2_DN1 CSI2_CLKN1 D32
C36 CSI2_DP1 CSI2_CLKP1 C29
D36 CSI2_DN2 CSI2_CLKN2 D29

i
A38 CSI2_DP2 CSI2_CLKP2 B26
B38 CSI2_DN3 CSI2_CLKN3 A26
CSI2_DP3 CSI2_CLKP3
C31 E13
CSI2_DN4 CSI2_COMP

f
C D31 B7 C
C33 CSI2_DP4 GPP_D4/FLASHTRIG
D33 CSI2_DN5
A31 CSI2_DP5 EMMC

B31 CSI2_DN6 AP2

A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1
B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3

n
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3
A29 GPP_F16/EMMC_DATA3 AN1
B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4
D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
A27 CSI2_DP9 GPP_F20/EMMC_DATA7
B27 CSI2_DN10 AM2

o
C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
CSI2_DP11 GPP_F12/EMMC_CMD RC361 20141106
AT1 1 2
EMMC_RCOMP
9 OF 20
SKYLAKE-U_BGA1356
REV = 1 ? 200_0402_1%
@

C B

F C
A

L C Security Classification
Issued Date 2014/05/07
LC Future Center Secret Data
Deciphered Date 2015/05/07
Title

SKL(15/16):CSI-2/EMMC
A

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 19 of 83
5 4 3 2 1
 5 4 3 2 1

[SKL EDS]
CFG0 CFG4

l
+VCC_IO +VCC_IO

CFG0 RC105 2 @ 1 1K_0402_5% CFG4 RC104 2 @ 1 1K_0402_5%

RC201 2 @ 1 1K_0402_1% RC144 2 1 1K_0402_1%

a
L:Stall. *L: Embedded DisplayPort Enabled
D D

it
*H:(Default) Normal Operation; No stall. H: Embedded DisplayPort Disabled

20150309
@
(Test point change to 12mil) UC1S
SKL_ULT ? TABLE

n
RESERVED SIGNALS-1

TP36 1 CFG0 E68 BB68 1 TP37

CFG0 : Stall Reset Sequence
CFG[0] RSVD_TP_BB68
TP38 1 CFG1 B67
CFG[1] RSVD_TP_BB69
BB69 1 TP39 after PCU PLL Lock until de-asserted
TP40 1 CFG2 D65
TP41 1 CFG3 D67 CFG[2] AK13 1 TP43
1 : No Stall
CFG[3] RSVD_TP_AK13

e
TP42 1 CFG4 E70
CFG[4] RSVD_TP_AK12
AK12 1 TP45 0 : Stall
TP44 1 CFG5 C68
TP46 1 CFG6 D68 CFG[5] BB2 1 TP49
TP47 1 CFG7 C67 CFG[6] RSVD_BB2 BA3 1 TP51
TP48 1 CFG8 F71 CFG[7] RSVD_BA3
TP50 1 CFG9 G69 CFG[8] CFG4 : eDP Enable
CFG[9]
TP52 1 CFG10 F70 AU5 1 TP59 1 : Disabled

d
TP53 1 CFG11 G68 CFG[10] TP5 AT5 1 TP60
TP55 1 CFG12 H70 CFG[11] TP6 0 : Enabled
TP56 1 CFG13 G71 CFG[12]
TP57 1 CFG14 H69 CFG[13] D5 1 TP22

if
TP58 1 CFG15 G70 CFG[14] RSVD_D5 D4 1 TP23
CFG[15] RSVD_D4 B2 1 TP25
CFG9 : SVID Bus Communication
TP61 1 CFG16 E63
CFG[16]
RSVD_B2
RSVD_C2
C2 1 TP27 1 : Enabled
TP63 1 CFG17 F63
C CFG[17] B3 1 TP64
0 : Disabled C
TP62 1 CFG18 E66 RSVD_B3 A3 1 TP66
1 CFG19 F66 CFG[18] RSVD_A3
[SKL CRB] TP65
CFG[19] AW1 1 TP29
RC152 2 1 49.9_0402_1% CFG_RCOMP E60 RSVD_AW1
CFG_RCOMP E1 1 TP31
RC354 2 1 1.5K_0402_5% ITP_PMODE E8 RSVD_E1 E2 1 TP33
+1VALW_PCH

n
ITP_PMODE RSVD_E2
[SKL EDS]Zero Voltage Mode:VCCOPC is fixed OPC VR output voltage of 1V, the
[SKL PDG]Route HOOK[6] to Skylake ITP_PMODE. TP24 1 AY2 BA4 1 TP34 processor can drive VR to LPM (Low Power Mode) which sets VR output to 0V using
TP26 1 AY1 RSVD_AY2 RSVD_BA4 BB4 1 TP35
Termination: Resistor value from 1K ohm to RSVD_AY1 19 OF 20 RSVD_BB4 ZVM# signal as shown below:
SKYLAKE-U_BGA1356
3K ohm pull up to PCH_V1.0A Rail. TP74 1 D1 REV = 1 A4 ? 1 TP67
TP30 1 D3 RSVD_D1 RSVD_A4 C4 1 TP68
RSVD_D3 RSVD_C4
ZVM# state VCCOPC

o
TP86 1 K46 BB5 1 TP54
TP85 1 K45 RSVD_K46 TP4
RSVD_K45 A69 1
RSVD_A69
TP927 0V 0V
TP88 1 AL25 B69 1 TP928
TP87 1 AL27 RSVD_AL25 RSVD_B69
RSVD_AL27 AY3 1 2
RSVD_AY3
RC296 @ 0_0402_5% 1V 1V
TP90 1 C71
TP89 1 B70 RSVD_C71 D71 1 TP929
RSVD_B70 RSVD_D71 C70 1 TP930

C
TP32 1 F60 RSVD_C70
RSVD_F60 C54 1 TP931
TP91 1 A52 RSVD_C54 D54 1 TP932 20141202
RSVD_A52 RSVD_D54 +VCC_ST
TP92 1 BA70 AY4 1 TP933
1 BA68 RSVD_TP_BA70 TP1 BB3 1
TP93
RSVD_TP_BA68 TP2
TP934 [SKL EDS]Minimum Speed Mode: VCCEOPIO can be connected to OPC VR in this
case VCCEOPIO is fixed to 1V. The processor can drive VR to LPM (Low Power
TP94 1 J71 AY71 RC295 1 @ 2 0_0402_5%
TP95 1 J68 RSVD_J71 VSS_AY71 AR56 1 TP935
Mode) which sets VR output to 0V using ZVM# signal .
B RSVD_J68 ZVM# In order to achieve better power/performance it is recommended to use a B
F65 AW71 1 TP936 separate VR for VCCEOPIO in this case VCCEOPIO is configurable to 0.8V/1V.
G65 VSS_F65 RSVD_TP_AW71 AW70 1 TP937 The processor drives the VR to set VCCEOPIO value(0.8V/1V) using MSM#
VSS_G65 RSVD_TP_AW70

C
signal, based on the required bandwidth for the EOPIO interface as shown
TP96 1 F61 AP56 1 TP938 RC358 below:
TP97 1 E61 RSVD_F61 MSM# C64 2 1
RSVD_E61 PROC_SELECT# 100K_0402_1% ZVM# state MSM# state VCCEOPIO
@

0V X 0V
[SKL CRB]

F
1V 0V 0.8V

@
? 1V 1V 1V
UC1T SKL_ULT

SPARE

C
TP98 1 AW69 F6 1 TP106
TP99 1 AW68 RSVD_AW69 RSVD_F6 E3 1 TP107
TP100 1 AU56 RSVD_AW68 RSVD_E3 C11 1 TP108
TP101 1 AW48 RSVD_AU56 RSVD_C11 B11 1 TP109
TP102 1 C7 RSVD_AW48 RSVD_B11 A11 1 TP110
TP103 1 U12 RSVD_C7 RSVD_A11 D12 1 TP111
TP104 1 U11 RSVD_U12 RSVD_D12 C12 1 TP112
TP105 1 H11 RSVD_U11 RSVD_C12 F52 1 TP113

L
RSVD_H11 RSVD_F52

SKYLAKE-U_BGA1356
A REV = 1 20 OF 20 A

Security Classification LC Future Center Secret Data Title

Issued Date 2014/05/07 Deciphered Date 2015/05/07 SKL(16/16):CFG/RESERVED
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 20 of 83
5 4 3 2 1
 5 4 3 2 1

Security ROM

l
USROM1 @
+3VS M3 Support + Intel LAN PHY / Wireless LAN Solut i on
1 8
2 NC_1 VCC 7
PLTRST_NEAR# NC_2 WP PM_SMB_CLK 1
3 6 CC22 +3V_SPI
[12] PLTRST_NEAR# PROT# SCL PM_SMB_DAT PM_SMB_CLK [11,22,23,53]
4 5 @
PM_SMB_DAT [11,22,23,53]

a
GND SDA 0.1U_0402_10V6-K RC110 1 @ 2 0_0402_5% +3V_SPI
2 +3VS
PCA24S08AD_SO8
SA00004MK00/SA00004ML00 0.085 A
+3VALW RC310 1 @ 2 0_0402_5%
D D

i
2015/03/08
@
SPI_IO3 RC380 1 2 1K_0402_5%

t
[SKL]SPI0_CS0#: SPI FLASH
SPI0_CS1#: SPI FLASH
+3V_SPI
SPI0_CS2#: SPI TPM 8MB(64Mb) 4MB(32Mb) for VPRO SKU

n
RC117 1 2 1K_0402_5% SPI_IO2
RC118 1 2 1K_0402_5% SPI_IO3

+3V_SPI

20150304

e
+3V_SPI
1
UC8M1 CC25 UC4M1 20150304
SPI_CS0#_8MB 1 8 +3V_SPI 0.1U_0402_10V7-K SPI_CS1#_4MB 1 8 +3V_SPI
[11] SPI_CS0#_8MB CS# VCC 2 [11] SPI_CS1#_4MB SPI_SO_4MB CS# VCC SPI_IO3_4MB 1
2 7 CC26
SPI_SO_8MB 2 7 SPI_IO3_8MB SPI_IO2_4MB 3 DO HOLD# 6 SPI_CLK_4MB @
DO HOLD# 4 WP# CLK 5 SPI_SI_4MB 0.1U_0402_10V7-K
SPI_IO2_8MB 3 6 SPI_CLK_8MB GND DI 2

d
WP# CLK W25Q32FVSSIQ_SO8
4 5 SPI_SI_8MB
GND DI @

i
W25Q64FVSSIQ_SO8

RPC24
SPI_IO3_4MB SPI_IO3

f
C 1 8 C
RPC23 SPI_CLK_4MB 2 7 SPI_CLK
SPI_IO3_8MB 1 8 SPI_IO3 SPI_SI_4MB 3 6 SPI_SI
SPI_CLK_8MB SPI_CLK SPI_IO3 [11] SPI_IO2_4MB SPI_IO2
2 7 4 5
SPI_SI_8MB SPI_SI SPI_CLK [11,60]
3 6
SPI_IO2_8MB SPI_IO2 SPI_SI [11,60]
4 5 33_0804_8P4R_5%
SPI_IO2 [11]
Near SPI ROM SD30000370T
33_0804_8P4R_5% @

n
Near SPI ROM SD30000370T
SPI_SO_8MB RC103 1 2 33_0402_5% SPI_SO SPI_SO_4MB RC102 1 2 33_0402_5% SPI_SO
SPI_SO [11,60]
@

B
[66]
[66]
[66]
[66]
FSCE#
SPI_FMOSI#
SPI_FMISO
SPI_FSCK
RC311
RC312
RC313
RC314
Mirror Code

1
1
1
1
@
@
@
@

Close to SPI ROM (UC8M1).

2
2
2
2
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
SPI_CS0#_8MB
SPI_SI_8MB
SPI_SO_8MB
SPI_CLK_8MB

C o B

F C
A

L C Security Classification
Issued Date 2013/09/07
LC Future Center Secret Data
Deciphered Date 2014/09/07
Title

XXXX
A

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 21 of 83
5 4 3 2 1
 5 4 3 2 1

Layout Note:
Place near JDIMM1
+1.35V DDR_A_DQS#[0..7] [7]

l
+1.35V +1.35V
[7] SA_DIMM_VREFDQ DDR_A_DQS[0..7] [7]
JDIMM1 ME@

1
+V_DDR_REFA 1 2
3 VREF_DQ VSS1 4 DDR_A_D4 DDR_A_D[0..31] [7] +1.35V
RD1
DIMM1@ DDR_A_D0 5 VSS2 DQ4 6 DDR_A_D5 DIMM1@ DIMM1@ DIMM1@ DIMM1@ DIMM1@ DIMM1@ DIMM1@
DDR_A_D1 7 DQ0 DQ5 8 DDR_A_MA[0..15] [7]
DIMM1@ 1.8K_0402_1% CD13 CD14 CD15 CD16 CD19 CD20 CD21 CD22

a
9 DQ1 VSS3 10 DDR_A_DQS#0
1 RD2 DDR_A_D[32..63] [7]

2
VSS4 DQS#0 DDR_A_DQS0

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

330U_D2_2V_Y
2 11 12 1
DM0 DQS0 +1.35V

2.2U_0402_6.3V6-K
1 13 14 1 1 1 1 1 1 1
2_0402_1% VSS5 VSS6

1
DDR_A_D2 DDR_A_D6

1.8K_0402_1%

0.1U_0402_10V7-K
D CD2 15 16 + D

it
1 1 DDR_A_D3 DQ2 DQ6 DDR_A_D7

DIMM1@

DIMM1@
DIMM1@ 17 18
DQ3 DQ7

1
RD3

CD3

CD1
0.022U_0402_25V7-K 19 20
2 @ DDR_A_D8 21 VSS7 VSS8 22 DDR_A_D12 RD21 2 2 2 2 2 2 2 2
DQ8 DQ12
1

2 2 DDR_A_D9 23 24 DDR_A_D13

2
RD4 25 DQ9 DQ13 26 470_0402_5%
DIMM1@ DDR_A_DQS#1 27 VSS9 VSS10 28

2
24.9_0402_1% DDR_A_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST#
DQS1 RESET# DDR3_DRAMRST# [8,23]
31 32
2

DDR_A_D10 33 VSS11 VSS12 34 DDR_A_D14

DDR_A_D11 DQ10 DQ14 DDR_A_D15 1 For RF solution.
Close to JDIMM1 35 36
DQ11 DQ15

n
37 38 CD59 DIMM1@ DIMM1@
DDR_A_D16 39 VSS13 VSS14 40 DDR_A_D20 EMC_NS@ 0.1U_0402_10V7-K CD8 CD9 CD10 CD11 CRF1 CRF2
DDR_A_D17 41 DQ16 DQ20 42 DDR_A_D21 2
DQ17 DQ21

1U_0402_6.3VA-K

1U_0402_6.3VA-K

1U_0402_6.3VA-K

1U_0402_6.3VA-K

2200P_0402_50V7-K

47P_0402_50V8-J
43 44 @ @ RF_NS@ RF_NS@
DDR_A_DQS#2 45 VSS15 VSS16 46
DDR_A_DQS2 DQS#2 DM2 1 1 1 1 1 1
47 48
DQS2 VSS17

e
49 50 DDR_A_D22
DDR_A_D18 51 VSS18 DQ22 52 DDR_A_D23
DDR_A_D19 53 DQ18 DQ23 54 2 2 2 2 2 2
55 DQ19 VSS19 56 DDR_A_D28
DDR_A_D24 57 VSS20 DQ28 58 DDR_A_D29
DDR_A_D25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDR_A_DQS#3

d
63 VSS22 DQS#3 64 DDR_A_DQS3
65 DM3 DQS3 66
DDR_A_D26 67 VSS23 VSS24 68 DDR_A_D30
DDR_A_D27 69 DQ26 DQ30 70 DDR_A_D31

if
71 DQ27 DQ31 72
VSS25 VSS26
Layout Note:
Place near JDIMM1.203,204
C DDRA_CKE0_DIMMA 73 74 DDRA_CKE1_DIMMA C
[7] DDRA_CKE0_DIMMA CKE0 CKE1 DDRA_CKE1_DIMMA [7]
75 76
77 VDD1 VDD2 78 DDR_A_MA15 +0.675VS
DDR_A_BS2 79 NC1 A15 80 DDR_A_MA14 DIMM1@ DIMM1@
[7] DDR_A_BS2 BA2 A14
81 82 CD23 CD24 CD25 CD26
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11
DDR_A_MA9 A12/BC# A11 DDR_A_MA7

1U_0402_6.3VA-K

1U_0402_6.3VA-K

1U_0402_6.3VA-K

1U_0402_6.3VA-K
85 86 @ @

n
87 A9 A7 88
DDR_A_MA8 VDD5 VDD6 DDR_A_MA6 1 1 1 1
89 90
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
DDR_A_MA3 95 VDD7 VDD8 96 DDR_A_MA2 2 2 2 2
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
99 A1 A0 100

o
SA_CLK_DDR0 101 VDD9 VDD10 102 SA_CLK_DDR1
[7] SA_CLK_DDR0 SA_CLK_DDR#0 CK0 CK1 SA_CLK_DDR#1 SA_CLK_DDR1 [7]
103 104
[7] SA_CLK_DDR#0 CK0# CK1# SA_CLK_DDR#1 [7]
105 106
DDR_A_MA10 107 VDD11 VDD12 108 DDR_A_BS1
DDR_A_BS0 A10/AP BA1 DDR_A_RAS# DDR_A_BS1 [7] +1.35V
109 110
[7] DDR_A_BS0 BA0 RAS# DDR_A_RAS# [7]
111 112
DDR_A_WE# 113 VDD13 VDD14 114 DDRA_CS0_DIMMA#
[7] DDR_A_WE# WE# S0# DDRA_CS0_DIMMA# [7] All VREF traces should

1
DDR_A_CAS# 115 116 DDRA_ODT0_DIMMA#
[7] DDR_A_CAS#
117 CAS# ODT0 118
DDRA_ODT0_DIMMA# [7]
RD9 have 10 mil trace width

C
DDR_A_MA13 119 VDD15 VDD16 120 DDRA_ODT1_DIMMA#
DDRA_CS1_DIMMA# A13 ODT1 DDRA_ODT1_DIMMA# [7]
121 122 1.8K_0402_1%
[7] DDRA_CS1_DIMMA# S1# NC2
123 124
20141202 1 RD10

2
125 VDD17 VDD18 126 +VREF_CA 2
NCTEST VREF_CA SM_DIMM_VREFCA [7]
127 128 1
VSS27 VSS28 2_0402_1%

1
DDR_A_D32 DDR_A_D36

0.1U_0402_10V7-K

2.2U_0402_6.3V6-K
129 130 CD12
DDR_A_D33 131 DQ32 DQ36 132 DDR_A_D37 RD11
DQ33 DQ37 1 1
DIMM1@
133 134 0.022U_0402_25V7-K
DDR_A_DQS#4 VSS29 VSS30 2

CD17

CD18
135 136 1.8K_0402_1%
DQS#4 DM4

1
B DDR_A_DQS4 137 138 @ B

2
139 DQS4 VSS31 140 DDR_A_D38 2 2 RD12
DDR_A_D34 141 VSS32 DQ38 142 DDR_A_D39 +3V_DDR
DQ34 DQ39

C
DDR_A_D35 143 144 24.9_0402_1%
145 DQ35 VSS33 146 DDR_A_D44

2
DDR_A_D40 147 VSS34 DQ44 148 DDR_A_D45
DDR_A_D41 149 DQ40 DQ45 150 +VREF_CA [23]
DQ41 VSS35

1
151 152 DDR_A_DQS#5
153 VSS36 DQS#5 154 DDR_A_DQS5 RD23
155 DM5 DQS5 156
close to JDDR3L.126
VSS37 VSS38 100K_0402_5%
DDR_A_D42 157 158 DDR_A_D46

F
DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47

2
161 DQ43 DQ47 162
DDR_A_D48 163 VSS39 VSS40 164 DDR_A_D52
DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D53 +1.35V SM_PG_CTRL
167 DQ49 DQ53 168 SM_PG_CTRL [73]
DDR_A_DQS#6 169 VSS41 VSS42 170
DQS#6 DM6

1
DDR_A_DQS6 171 172
173 DQS6 VSS43 174 DDR_A_D54
DDR_A_D50 175 VSS44 DQ54 176 DDR_A_D55 2 QD1

C
DDR_A_D51 177 DQ50 DQ55 178 DTC115TMT2L_VMT3
179 DQ51 VSS45 180 DDR_A_D60
DDR_A_D56 181 VSS46 DQ60 182 DDR_A_D61
20141230

3
DDR_A_D57 183 DQ56 DQ61 184
185 DQ57 VSS47 186 DDR_A_DQS#7 DDR_PG_CTRL
VSS48 DQS#7 DDR_A_DQS7 [7] DDR_PG_CTRL
187 188
189 DM7 DQS7 190
VSS49 VSS50

1
DDR_A_D58 191 192 DDR_A_D62

L
DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63 RD24
195 DQ59 DQ63 196 @
VSS51 VSS52 10K_0402_5%
197 198
199 SA0 EVENT# 200
+3VS PM_SMB_DAT [11,21,23,53]

2
A 201 VDDSPD SDA 202 A
203 SA1 SCL 204 PM_SMB_CLK [11,21,23,53]
+0.675VS VTT1 VTT2 +0.675VS
2.2U_0402_6.3V6-K

0.1U_0402_10V6-K

@ 205 206
G1 G2
2

2
DIMM1@

1 1
CD30

RC316

RC315

LCN_DAN06-K4406-0102
CD29

@ @
2 2 Security Classification LC Future Center Secret Data Title
0_0402_5%

0_0402_5%

Channel A
1

Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 22 of 83
5 4 3 2 1
 5 4 3 2 1

+1.35V
+1.35V +1.35V
JDIMM2 ME@ Layout Note:
DDR_B_DQS#[0..3] [8]

1
+V_DDR_REFB 1 2
RD15 3 VREF_DQ VSS_2 4 DDR_B_D4 Place near JDIMM2

l
DDR_B_D0 5 VSS_1 DQ4 6 DDR_B_D5 DDR_B_DQS[0..3] [8]
DIMM2@
1.8K_0402_1% DDR_B_D1 7 DQ0 DQ5 8
9 DQ1 VSS_4 10 DDR_B_DQS#0 DDR_B_D[0..31] [8] +1.35V
1 RD17

2
2 11 VSS_3 DQS0# 12 DDR_B_DQS0
[7] SB_DIMM_VREFDQ DM0 DQS0 DDR_B_MA[0..15] [8]
1 13 14 DIMM2@ DIMM2@ DIMM2@ DIMM2@ DIMM2@ DIMM2@ DIMM2@
2_0402_1% VSS_5 VSS_6

1
DDR_B_D2 DDR_B_D6

2.2U_0402_6.3V6-K
15 16 CD42 CD43 CD44 CD45 CD46 CD47 CD48

a
DDR_B_D3 DQ2 DQ6 DDR_B_D7 DDR_B_D[32..63] [8]

CD32 DIMM2@
0.022U_0402_25V7-K CD31 RD16 1 1 17 18
DIMM2@ DQ3 DQ7

0.1U_0402_10V7-K
DIMM2@ DIMM2@ 19 20
2 DDR_B_D8 VSS_7 VSS_8 DDR_B_D12 DDR_B_DQS#[4..7] [8]

CD33

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M
1.8K_0402_1% 21 22 1 1 1 1 1 1 1
DQ8 DQ12
1
D @ DDR_B_D9 23 24 DDR_B_D13 D

i
DDR_B_DQS[4..7] [8]

2
2 2 25 DQ9 DQ13 26
24.9_0402_1% RD18 DDR_B_DQS#1 27 VSS_9 VSS_10 28
DIMM2@ DDR_B_DQS1 29 DQS1# DM1 30 DDR3_DRAMRST# 2 2 2 2 2 2 2
DQS1 RESET# DDR3_DRAMRST# [8,22]

t
31 32
2

DDR_B_D10 33 VSS_11 VSS_12 34 DDR_B_D14

DDR_B_D11 DQ10 DQ14 DDR_B_D15 1
35 36 EMC_NS@
37 DQ11 DQ15 38 CD60
Close to JDIMM2 DDR_B_D24 39 VSS_13 VSS_14 40 DDR_B_D28 0.1U_0402_10V7-K
DDR_B_D25 41 DQ16 DQ20 42 DDR_B_D29 2
43 DQ17 DQ21 44
VSS_15 VSS_16

n
DDR_B_DQS#3 45 46
DDR_B_DQS3 DQS2# DM2 For RF solution.
47 48 DIMM2@ DIMM2@
49 DQS2 VSS_18 50 DDR_B_D30 CD38 CD39 CD40 CD41 CRF3 CRF4
DDR_B_D26 51 VSS_17 DQ22 52 DDR_B_D31
DDR_B_D27 53 DQ18 DQ23 54
55 DQ19 VSS_20 56 DDR_B_D20
VSS_19 DQ28

e
DDR_B_D16 DDR_B_D21

1U_0402_6.3VA-K

1U_0402_6.3VA-K

1U_0402_6.3VA-K

1U_0402_6.3VA-K

2200P_0402_50V7-K

47P_0402_50V8-J
57 58 @ @ RF_NS@ RF_NS@
DDR_B_D17 59 DQ24 DQ29 60
DQ25 VSS_22 DDR_B_DQS#2 1 1 1 1 1 1
61 62
63 VSS_21 DQS3# 64 DDR_B_DQS2
65 DM3 DQS3 66
DDR_B_D18 67 VSS_23 VSS_24 68 DDR_B_D22 2 2 2 2 2 2
DDR_B_D19 69 DQ26 DQ30 70 DDR_B_D23

d
71 DQ27 DQ31 72
VSS_25 VSS_26

DDRB_CKE0_DIMMB 73 74 DDRB_CKE1_DIMMB

i
[8] DDRB_CKE0_DIMMB CKE0 CKE1 DDRB_CKE1_DIMMB [8]
75 76
77 VDD_1 VDD_2 78 DDR_B_MA15
DDR_B_BS2 79 NC_1 A15 80 DDR_B_MA14
[8] DDR_B_BS2 BA2 A14
81 82
VDD_3 VDD_4

f
C DDR_B_MA12 83 84 DDR_B_MA11 C
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
Layout Note:
DDR_B_MA8 89 VDD_5 VDD_6 90 DDR_B_MA6 Place near JDIMM2.203,204
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94 +0.675VS
DDR_B_MA3 95 VDD_7 VDD_8 96 DDR_B_MA2

n
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0 DIMM2@ DIMM2@ DIMM2@ DIMM2@ DIMM2@ DIMM2@
99 A1 A0 100 CD51 CD52 CD53 CD54 CD55 CD56
SB_CLK_DDR0 101 VDD_9 VDD_10 102 SB_CLK_DDR1
[8] SB_CLK_DDR0 SB_CLK_DDR#0 CK0 CK1 SB_CLK_DDR#1 SB_CLK_DDR1 [8]

1U_0402_6.3VA-K

1U_0402_6.3VA-K

1U_0402_6.3VA-K

1U_0402_6.3VA-K

10U_0603_6.3V6-M

10U_0603_6.3V6-M
103 104
[8] SB_CLK_DDR#0 CK0# CK1# SB_CLK_DDR#1 [8]
105 106 1 1 1 1 1 1
DDR_B_MA10 107 VDD_11 VDD_12 108 DDR_B_BS1
DDR_B_BS0 A10/AP BA1 DDR_B_RAS# DDR_B_BS1 [8]
109 110

o
[8] DDR_B_BS0 BA0 RAS# DDR_B_RAS# [8]
111 112
DDR_B_WE# 113 VDD_13 VDD_14 114 DDRB_CS0_DIMMB# 2 2 2 2 2 2
[8] DDR_B_WE# DDR_B_CAS# WE# S0# DDRB_ODT0_DIMMB# DDRB_CS0_DIMMB# [8]
115 116
[8] DDR_B_CAS#
117 CAS# ODT0 118 DDRB_ODT0_DIMMB# [8] 20141202
DDR_B_MA13 119 VDD_15 VDD_16 120 DDRB_ODT1_DIMMB#
DDRB_CS1_DIMMB# 121 A13 ODT1 122 DDRB_ODT1_DIMMB# [8]
[8] DDRB_CS1_DIMMB# S1# NC_2
123 124
125 VDD_17 VDD_18 126 +VREF_CA
TEST VREF_CA +VREF_CA [22]
127 128

C
DDR_B_D32 129 VSS_27 VSS_28 130 DDR_B_D36
DDR_B_D33 131 DQ32 DQ36 132 DDR_B_D37
133 DQ33 DQ37 134
DDR_B_DQS#4 VSS_29 VSS_30 1
135 136 CD49
DDR_B_DQS4 137 DQS4# DM4 138 DIMM2@
139 DQS4 VSS_32 140 DDR_B_D38 All VREF traces should
0.1U_0402_10V7-K
DDR_B_D34 141 VSS_31 DQ38 142 DDR_B_D39 2 have 10 mil trace width
DDR_B_D35 143 DQ34 DQ39 144
145 DQ35 VSS_34 146 DDR_B_D44
B DDR_B_D40 147 VSS_33 DQ44 148 DDR_B_D45 B
DDR_B_D41 149 DQ40 DQ45 150
151 DQ41 VSS_35 152 DDR_B_DQS#5
VSS_36 DQS5#

C
153 154 DDR_B_DQS5
155 DM5 DQS5 156
DDR_B_D42 157 VSS_37 VSS_38 158 DDR_B_D46
DDR_B_D43 159 DQ42 DQ46 160 DDR_B_D47
161 DQ43 DQ47 162
DDR_B_D48 163 VSS_39 VSS_40 164 DDR_B_D52
DDR_B_D49 165 DQ48 DQ52 166 DDR_B_D53
167 DQ49 DQ53 168

F
DDR_B_DQS#6 169 VSS_41 VSS_42 170
DDR_B_DQS6 171 DQS6# DM6 172
173 DQS6 VSS_44 174 DDR_B_D54
DDR_B_D50 175 VSS_43 DQ54 176 DDR_B_D55
DDR_B_D51 177 DQ50 DQ55 178
179 DQ51 VSS_46 180 DDR_B_D60
+3VS DDR_B_D56 181 VSS_45 DQ60 182 DDR_B_D61
DDR_B_D57 183 DQ56 DQ61 184
185 DQ57 VSS_48 186 DDR_B_DQS#7

C
VSS_47 DQS7#
1

187 188 DDR_B_DQS7

RD19 189 DM7 DQS7 190
DIMM2@ DDR_B_D58 191 VSS_49 VSS_50 192 DDR_B_D62
10K_0402_5% DDR_B_D59 193 DQ58 DQ62 194 DDR_B_D63
195 DQ59 DQ63 196
2

197 VSS_51 VSS_52 198

199 SA0 EVENT# 200
+3VS VDDSPD SDA PM_SMB_DAT [11,21,22,53]
201 202

L
203 SA1 SCL 204 PM_SMB_CLK [11,21,22,53]
+0.675VS VTT_1 VTT_2 +0.675VS
205 206
GND1 GND2
2.2U_0402_6.3V6-K

0.1U_0402_10V6-K

CD58 DIMM2@

@ 207 208
BOSS1 BOSS2
2

A A
1 1
RC317
CD57

0_0402_5% LCN_DAN06-K4406-0103
@
2 2
Channel B
1

Security Classification LC Future Center Secret Data Title

<Address: SA1:SA0=10> Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX

WWW.AliSaler.Com
DIMM_2 STD H:4mm THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 23 of 83
5 4 3 2 1
 1 2 3 4 5

l
UV3G @

PCIE_CTX_C_GRX_N[0..3]
[15] PCIE_CTX_C_GRX_N[0..3]
PCIE_CTX_C_GRX_P[0..3]
[15] PCIE_CTX_C_GRX_P[0..3]
PCIE_CRX_GTX_N[0..3]

a
[15] PCIE_CRX_GTX_N[0..3]
PCIE_CRX_GTX_P[0..3] PCIE_CTX_C_GRX_P0 AF30 AH30 PCIE_CRX_C_GTX_P0
[15] PCIE_CRX_GTX_P[0..3] PCIE_CTX_C_GRX_N0 PCIE_RX0P PCIE_TX0P PCIE_CRX_C_GTX_N0
AE31 AG31
PCIE_RX0N PCIE_TX0N
A A

it
PCIE_CTX_C_GRX_P1 AE29 AG29 PCIE_CRX_C_GTX_P1
PCIE_CTX_C_GRX_N1 AD28 PCIE_RX1P PCIE_TX1P AF28 PCIE_CRX_C_GTX_N1
PCIE_RX1N PCIE_TX1N

PCIE_CTX_C_GRX_P2 AD30 AF27 PCIE_CRX_C_GTX_P2

PCIE_CTX_C_GRX_N2 AC31 PCIE_RX2P PCIE_TX2P AF26 PCIE_CRX_C_GTX_N2
PCIE_RX2N PCIE_TX2N
DIS@
PCIE_CRX_GTX_P0 CV132 DIS@ 1 2 0.1U_0402_10V7-K PCIE_CRX_C_GTX_P0 PCIE_CTX_C_GRX_P3 AC29 AD27 PCIE_CRX_C_GTX_P3
PCIE_CRX_GTX_N0 CV133 DIS@ 1 2 0.1U_0402_10V7-K PCIE_CRX_C_GTX_N0 PCIE_CTX_C_GRX_N3 AB28 PCIE_RX3P PCIE_TX3P AD26 PCIE_CRX_C_GTX_N3
PCIE_CRX_GTX_P1 CV134 DIS@ 1 2 0.1U_0402_10V7-K PCIE_CRX_C_GTX_P1 PCIE_RX3N PCIE_TX3N

n
PCIE_CRX_GTX_N1 CV135 DIS@ 1 2 0.1U_0402_10V7-K PCIE_CRX_C_GTX_N1
PCIE_CRX_GTX_P2 CV136 DIS@ 1 2 0.1U_0402_10V7-K PCIE_CRX_C_GTX_P2 AB30 AC25
PCIE_CRX_GTX_N2 CV137 DIS@ 1 2 0.1U_0402_10V7-K PCIE_CRX_C_GTX_N2 AA31 PCIE_RX4P PCIE_TX4P AB25
PCIE_CRX_GTX_P3 CV138 DIS@ 1 2 0.1U_0402_10V7-K PCIE_CRX_C_GTX_P3 PCIE_RX4N PCIE_TX4N
PCIE_CRX_GTX_N3 CV139 DIS@ 1 2 0.1U_0402_10V7-K PCIE_CRX_C_GTX_N3
AA29 Y23

e
Y28 PCIE_RX5P PCIE_TX5P Y24
PCIE_RX5N PCIE_TX5N

Y30 AB27
W31 PCIE_RX6P PCIE_TX6P AB26
PCIE_RX6N PCIE_TX6N

d
W29 Y27
V28 PCIE_RX7P PCIE_TX7P Y26
PCIE_RX7N PCIE_TX7N
+3VS_VGA
V30 W24

if
U31 NC_121 NC_137 W23
NC_122 NC_138

1
+3VS U29 V27 RV50
B +3VS_VGA T28 NC_123 NC_139 U26 @ 10K_0402_5% B
NC_124 NC_140

PCI EXPRESS INTERFACE

2
T30 U24 RV49 @
R31 NC_125 NC_141 U23 2 1
NC_126 NC_142 [6,14,33,79] VGA_ON
1

CV140

0.1U_0402_10V7-K
RV43 10K_0402_5%
10K_0402_5% R29 T26 +3VS_VGA

n
NC_127 NC_143 1
5

UV4 @ P28 T27

NC_128 NC_144
VCC

1
@
PLTRST# 1
[12] PLTRST# IN1 PLT_RST_VGA# 2
4 P30 T24 RV52
DGPU_HOLD_RST# OUT PLT_RST_VGA# [25,79] NC_129 NC_145
2 N31 T23 @ 10K_0402_5%
GND

[6,14] DGPU_HOLD_RST# IN2 NC_130 NC_146 @

1

2
QV7

2
o
RV44 N29 P27
3

MC74VHC1G08DFT2G_SC70-5 100K_0402_5% M28 NC_131 NC_147 P26 1 3 CLK_REQ_GPU#

NC_132 NC_148 [10] CLKREQ_PCIE4_VGA# CLK_REQ_GPU# [25]

CV141

0.1U_0402_10V7-K
DIS@

S
1
2

2
M30 P24 2N7002KW_SOT323-3
L31 NC_133 NC_149 P23 RV53
NC_134 NC_150 SB000019400

@
10K_0402_5%
2 1 @ 2 @
L29 M27

1
K30 NC_135 NC_151 N26 RV51 0_0402_5%

C
NC_136 NC_152

CLOCK
CLK_PCIE_VGA AK30
[10] CLK_PCIE_VGA CLK_PCIE_VGA# PCIE_REFCLKP
AK32 +0.95VS_VGA
[10] CLK_PCIE_VGA# PCIE_REFCLKN

CALIBRATION

C Y22 RV47 1 DIS@ 2 1.69K_0402_1% C

PCIE_CALR_TX
RV40 1 DIS@ 2 1K_0402_5% N10 AA22 RV48 1 2 1K_0402_1%
TEST_PG PCIE_CALR_RX DIS@

C
PLT_RST_VGA# AL27
PERSTB

216-0858020-A0_FCBGA631

C F
L
D D

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 Topaz & Jet PCIE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 24 of 83
1 2 3 4 5
 5 4 3 2 1

UV3A @

l
Test_Point_20MIL 1 TPV17 N9 AF2
Test_Point_20MIL 1 TPV18 L9 NC_DBG_DATA16 NC_13 AF4
Test_Point_20MIL 1 TPV19 AE9 NC_DBG_DATA15 NC_14
NC_DBG_DATA14 H_THERMTRIP# [6]
Test_Point_20MIL 1 TPV20 Y11 AG3
Test_Point_20MIL 1 TPV21 AE8 NC_DBG_DATA13 NC_15 AG5
Test_Point_20MIL 1 TPV22 AD9 NC_DBG_DATA12 NC_16 RV87 @
DBG_DATA11 NC_DPA

1
Test_Point_20MIL 1 TPV23 AC10 AH3 C
+3VS_VGA +1.8VS_VGA Test_Point_20MIL 1 TPV24 AD7 DBG_DATA10 NC_17 AH1 GPIO19_CTF RV86 1 @ 2 47K_0402_5% 1 2 2 QV3

a
Test_Point_20MIL 1 TPV25 AC8 DBG_DATA9 NC_18 B MMST3904-7-F_SOT323-3
DBG_DATA8

CV148

0.1U_0402_10V7-K
D Test_Point_20MIL 1 TPV26 AC7 AK3 @ 2.2K_0402_5% E SB000010U00 D

3
DBG_DATA7 NC_19

1
Test_Point_20MIL 1 TPV27 AB9 AK1 DV1 1 @
Test_Point_20MIL 1 TPV28 AB8 DBG_DATA6 NC_20 PLT_RST_VGA# 1 2 RV88
Test_Point_20MIL 1 TPV29 AB7 DBG_DATA5 DBG AK5 [24,79] PLT_RST_VGA#
DBG_DATA4 NC_21 100K_0402_5%

@
Test_Point_20MIL 1 TPV30 AB4 AM3 RB751V-40_SOD323-2

i
DBG_DATA3 NC_22 @ 2
RV54 RV55 Test_Point_20MIL 1 TPV31 AB2 SCS00007P00

2
4.7K_0402_5% 4.7K_0402_5% Test_Point_20MIL 1 TPV32 Y8 DBG_DATA2 AK6
MESO@ MESO@ Test_Point_20MIL 1 TPV33 Y7 DBG_DATA1 NC_23 AM5
Test_Point_20MIL 1 TPV34 AL9 DBG_DATA0 NC_24
NC_DPB

2
NC_DBG_CNTL0 AJ7
Test_Point_20MIL 1 TPV1 U1 NC_25 AH6

t
Test_Point_20MIL 1 TPV2 U3 BP_0 NC_26
BP_1 AK8
AM26 NC_27 AL7
DIECRACKMON NC_28
2
G

QV2A W6
SB000013A00 V6 NC_2 +1.8VS_VGA
NC_3 V4
SMBCLK 1 6 AC6 NC_29 U5 +3VS_VGA
S

EC_SMB_CK3 [11,37,59,60,66] NC_4 NC_30

D

AC5

n
2N7002KDWH_SOT363-6 NC_5 +3VS_VGA

CV150

0.1U_0402_10V7-K
DIS@ AA5 V2
AA6 NC_6 NC_31
NC_7 NC_DPC 1
Y4
NC_32

CV149

0.1U_0402_10V7-K
+3VS_VGA W5
NC_33

@
1
5

2
G

1
QV2B Y2
NC_34

@
RV91 RV92
2

e
SB000013A00 Y6 J8 10K_0402_5% 10K_0402_5%
SMBDAT 4 3 NC_8 NC_35 @ @ UV9 @
S

EC_SMB_DA3 [11,37,59,60,66]

1
D

2
2N7002KDWH_SOT363-6 RV70 RV71 1 8
DIS@ 4.7K_0402_5% @ @ 4.7K_0402_5% VCC(A) VCC(B)
GPIO15 RV89 1 @ 2 33_0402_5% 2 7 RV96 1 @ 2 33_0402_5% SVI2_SVD
PU AT EC SIDE, +3VS AND 4.7K 1A 1B
I2C

2
GPIO20 RV90 1 @ 2 33_0402_5% 3 6 RV97 1 @ 2 33_0402_5% SVI2_SVC
R1 2A 2B
R3 SCL AL25 5 4
SDA NC_G DIR GND

1
d
+3VS_VGA +3VS_VGA RV72 1 DIS@ 2 4.7K_0402_5% RV93 RV94
C AK26 10K_0402_5% 10K_0402_5% 74AVCH2T45GD_XSON8_3X2 C
DIS@ RV73 1 DIS@ 2 4.7K_0402_5% U6
GENERAL PURPOSE I/O NC_AVSSN_1 @ @
RV111 1 2 2.2K_0402_5% GPIO_0 AJ25 +3VS_VGA
RV95

2
NC_AVSSN_2 AH24
NC_B

i
DV2 SMBDAT U8 1 2
VGA_AC_DC# 1 2 GPIO5_AC_BATT SMBCLK U7 SMBDATA
[66] VGA_AC_DC# GPIO5_AC_BATT SMBCLK

CV151

0.1U_0402_10V7-K

10U_0603_6.3V6-M
T9 AG25 10K_0402_5%
GPIO_5_AC_BATT NC_AVSSN_3

CV152
RB751V-40_SOD323-2 GPIO6 T8 1 1 @
T7 GPIO_6_TACH NC_DAC1 AH26
SCS00007P00 1 TPV3 GPIO8_ROMSO P10 NC_GPIO_7 NC_HSYNC
DIS@ Test_Point_20MIL
GPIO9_ROMSI GPIO_8_ROMSO

@
Test_Point_20MIL 1 TPV4 P4
GPIO10_ROMSCK GPIO_9_ROMSI 2 2 +1.8VS_VGA

@
f
Test_Point_20MIL 1 TPV5 P2
N6 GPIO_10_ROMSCK AD22
N5 NC_GPIO_11 NC_RSET
N3 NC_GPIO_12 AG24
RV113 1 @ 2 0_0402_5% NC_GPIO_13 NC_AVDD AE22
SVI2_SVD RV117 1 @ 2 0_0402_5% GPIO15 N1 NC_AVSSQ
+3VS_VGA M4 GPIO_15_PWRCNTL_0 AE23
GPIO_16 NC_VDD1DI

2
R6 AD23
RV74 1 @ 2 10K_0402_5% GPIO_17_THERMAL_INT NC_VSS1DI RV121 RV123 RV125
GPIO19_CTF M2 10K_0402_5% 10K_0402_5% 10K_0402_5%

請B I O S 直直直
SVI2_SVC GPIO_19_CTF
1

RV116 1 @ 2 0_0402_5% GPIO20 P8 AM12 +3VS_VGA @ @ MESO@

n
RV61 P7 GPIO_20_PWRCNTL_1 NC_CEC_1

1
1 TPV6 GPIO22_ROMCSB N8 GPIO_21
10K_0402_5% Test_Point_20MIL
DIS@ AK10 GPIO_22_ROMCSB AK12 RV107 1 MESO@ 2 0_0402_5% SVI2_SVD SVI2_SVD
AM10 GPIO_29 GPIO_SVD AL11 1 MESO@ 2 SVI2_SVT SVI2_SVD [79]
RV108 0_0402_5%
RV62 SVI2_SVT [79]
2

@ RV112 1 @ 2 0_0402_5% N7 GPIO_30 GPIO_SVT AJ11 RV109 1 MESO@ 2 0_0402_5% SVI2_SVC SVI2_SVT
2 0_0402_5% OCP_L [24] CLK_REQ_GPU# CLKREQB GPIO_SVC SVI2_SVC [79]
RV114 1 @ 1 2 GPIO6 RV75 1 DIS@ 2 10K_0402_5%
[66,79] GPU_VR_HOT# JTAG_TRSTB SVI2_SVC

2
Test_Point_20MIL 1 TPV7 L6
1K_0402_1% Test_Point_20MIL 1 TPV8 JTAG_TDI L5 JTAG_TRSTB RV118 RV119 RV120
1 JTAG_TCK JTAG_TDI
Test_Point_20MIL 1 TPV9 L3 10K_0402_5% 10K_0402_5% 10K_0402_5%
JTAG_TMS JTAG_TCK

2
CV142 Test_Point_20MIL 1 TPV10 L1 AL13 @ @ EXO@

MLPS&SVI2
JTAG_TDO JTAG_TMS NC_GENLK_CLK

o
0.1U_0402_10V7-K Test_Point_20MIL 1 TPV11 K4 AJ13 RV122 RV124 RV126

1
2 @ K7 JTAG_TDO NC_GENLK_VSYNC 10K_0402_5% 10K_0402_5% 10K_0402_5%
+3VS_VGA AF24 TESTEN SVI2_SVD DIS@ @ @
NC_9 AG13

1
RV76 1 @ 2 5.11K_0402_1% NC_SWAPLOCKA SVI2_SVT
AC19 PS_0
RV77 1 DIS@ 2 1K_0402_1% W8 PS_0 SVI2_SVC
+3VS_VGA NC_GENERICB
W7 AH12
AD10 NC_GENERICD NC_SWAPLOCKB
NC_GENERICE_HPD4 PS_1 VID CODES
1

B AJ9 AD19 B
RV67 NC_10 PS_1
10K_0402_5% AE17 PS_2
PS_2 SVC SVD Boot Voltage
1

@ Test_Point_20MIL 1 TPV12 RV78 1 @ 2 0_0402_5% AB16

C
RV63 RV64 RV65 RV66 +3VS_VGA PX_EN AE20 PS_3
0 0 1.1V
2

10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% RV79 1 @ 2 0_0402_5% AJ27 PS_3 +1.8VS_VGA +1.8VS_VGA
@ @ @ @ @ WAKEB
RV115 1 2 +3VS_VGA 0 1 1.0V
2

1
@ AC16
JTAG_TRSTB NC_DBG_VREFG 1 0 0.9V(Default)
2

4.7K_0402_5% QV4 RV80 1 2 4.7K_0402_5% RV98 DIS@ @

G

JTAG_TDI @ 8.45K_0402_1% RV100

JTAG_TCK RV140 1 2 0_0402_5% 1 3 10K_0402_1% 1 1 0.8V
JTAG_TMS [6,66] EC_WAKE#
@ MESO@
D

NC_DDC/AUX

2
JTAG_TDO 1 2 4.7K_0402_5% PLL/CLOCK AE6 PS_0 PS_2
RV106 CV153 CV154
2N7002KW_SOT323-3 NC_DDC1CLK AE5
NC_DDC1DATA

0.1U_0402_10V7-K

0.1U_0402_10V7-K
Test_Point_20MIL 1 TPV13 AA1 RV104 RV105
PLL_ANALOG_IN

1
SB000019400 AD2 1 DIS@ 1
MESO@ NC_AUX1P AD4 RV99 RV101
1 2 16.2K_0402_1% AA3 NC_AUX1N
RV81
PLL_ANALOG_OUT 2K_0402_1% DIS@ 4.75K_0402_1% Memory (GDDR3)

@
2 2

2
1G SA22225SH30*4 PU 8.45K PD 2K
RV68 DIS@ XTALIN AM28 AD13 Samsung
XTALIN NC_AUX2P

C
XTALOUT AK28 AD11
1 2 XTALOUT NC_AUX2N
2G SA000063F00*4 PU 3.4K PD 10K
RV82 1 DIS@ 2 10K_0402_5% AC22
1M_0402_5% RV83 1 DIS@ 2 10K_0402_5% AB22 XO_IN
XO_IN2
+1.8VS_VGA +1.8VS_VGA
1G SA00005VS10*4 PU 4.53K PD 2K
YV1 DIS@ AE16 Hynix
4 3 XTALIN NC_36 AD16
NC2 OSC2 NC_37
2G SA00005YL10*4 PU 4.75K NC

1
XTALOUT 1 2 THERMAL AC1
OSC1 NC1 T4 NC_DDCVGACLK AC3 @ RV104
T2 DPLUS NC_DDCVGADATA
1 27MHZ_16PF_7V27000011 1 DMINUS
RV102 3.24K_0402_1% 1G SA00005M100*4 NC PD 4.75K
CV143 CV144 10K_0402_1% X76@ Micron

F
DIS@ DIS@ +1.8VS_VGA

2
22P_0402_50V8-J FDO R5 PS_1 PS_3
2
22P_0402_50V8-J
2 GPIO28_FDO
CV155 CV156 2G SA000060I00*4 PU 3.24K PD 5.62K
CV145 AD17
TSVDD

0.1U_0402_10V7-K

0.1U_0402_10V7-K
AC17
TSVSS

1
DIS@ 1 1
1U_0402_10V6-K

1 AE19 RV103 RV105

TS_A 4.75K_0402_1% 5.62K_0402_1%

@
A X76@ A
2 2
DIS@

216-0858020-A0_FCBGA631

2
2
EXO@
RV84 1 2 FDO

10K_0402_5%

L C 4 3
Security Classification
Issued Date 2013/09/07
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2
LC Future Center Secret Data
Deciphered Date 2014/09/07
Title

Size
Custom

Date:
Topaz & Jet GPIO

Document Number
BE460_NM-A551
Wednesday, August 05, 2015
1
Sheet 25 of 83
Re v
1.0

WWW.AliSaler.Com
 1 2 3 4 5

l
+1.8VS_VGA
TPV14
Test_Point_32MIL CV26 CV27 CV28
UV3B @

10U_0603_6.3V6-M
a

1U_0402_10V6-K

1U_0402_10V6-K
+1.35VS_VGA 1 1 1

1
AM30
MEM I/O PCIE_PVDD

PCIE

DIS@

DIS@

DIS@
A CV1 CV2 CV8 CV3 CV4 CV5 CV6 CV7 H13 AB23 A

it
H16 VMEMIO_1 NC_38 AC23 2 2 2
VMEMIO_2 NC_39
.01U_0402_16V7-K

0.1U_0402_10V7-K

10U_0603_6.3V6-M

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K
H19 AD24
J10 VMEMIO_3 NC_40 AE24
1 1 1 1 1 1 1 1 VMEMIO_4 NC_41
J23 AE25
J24 VMEMIO_5 NC_42 AE26
VMEMIO_6 NC_43
DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

@
J9 AF25 +0.95VS_VGA
2 2 2 2 2 2 2 2 K10 VMEMIO_7 NC_44 AG26
K23 VMEMIO_8 NC_45
K24 VMEMIO_9
K9 VMEMIO_10 L23 CV29 CV30 CV31 CV32 CV33 CV34 CV35 CV36
L11 VMEMIO_11 PCIE_VDDC_1 L24
VMEMIO_12 PCIE_VDDC_2

10U_0603_6.3V6-M

10U_0603_6.3V6-M
L12 L25

n
VMEMIO_13 PCIE_VDDC_3

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K
L13 L26 1 1 1 1 1 1 1 1
L20 VMEMIO_14 PCIE_VDDC_4 M22
L21 VMEMIO_15 PCIE_VDDC_5 N22
VMEMIO_16 PCIE_VDDC_6

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

@
L22 N23
VMEMIO_17 PCIE_VDDC_7 N24 2 2 2 2 2 2 2 2
PCIE_VDDC_8 R22

e
+1.8VS_VGA PCIE_VDDC_9 T22
LEVEL PCIE_VDDC_10 U22
TRANSLATION PCIE_VDDC_11 V22 +VGA_CORE
CV9 AA20 PCIE_VDDC_12
AA21 VDD_GPIO18_1
AB20 VDD_GPIO18_2 AA15 CV37 CV38 CV39 CV40 CV41 CV42 CV43 CV44 CV45 CV46 CV47 CV48 CV49 CV50
VDD_GPIO18_3 CORE VDDC_1
1U_0402_10V6-K

1 AB21 N15
VDD_GPIO18_4 VDDC_2

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M
d
N17
VDDC_3 R13
I/O VDDC_4 1 1 1 1 1 1 1 1 1 1 1 1 1 1
DIS@

R16
2 AA17 VDDC_5 R18
VDD_GPIO33_1 VDDC_6

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

@
AA18 Y21

if
AB17 VDD_GPIO33_2 VDDC_7 T12 2 2 2 2 2 2 2 2 2 2 2 2 2 2
AB18 VDD_GPIO33_3 VDDC_8 T15
VDD_GPIO33_4 VDDC_9 T17
V12 VDDC_10 T20
B
Y12 NC_VDDR4_1 VDDC_11 U13 B
+3VS_VGA U12 NC_VDDR4_2 VDDC_12 U16
NC_VDDR4_3 VDDC_13 U18 CV51 CV52 CV53 CV54 CV55 CV56 CV57 CV58
VDDC_14 V21
VDDC_15

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K
CV10 V15
VDDC_16 V17
VDDC_17 1 1 1 1 1 1 1 1
V20
VDDC_18
1U_0402_10V6-K

Y13

POWER
n
1 VDDC_19

DIS@

DIS@

DIS@

DIS@

@
Y16
VDDC_20 Y18 2 2 2 2 2 2 2 2
VDDC_21
DIS@

AA12
2 VDDC_22 M11
VDDC_23 N12
VDDC_24 U11
VDDC_25 AB13
VDDC_26

o
U10
VDDC_27 W9
PLL
VDDC_28 Y9
VDDC_29 W10
VDDC_30 T10 +0.95VS_VGA
+1.8VS_VGA MPLL_PVDD VDDC_31 AC14
VDDC_32 AB12
LV3 VDDC_33
DIS@ AB11 CV22
1 2 CV17 CV18 CV19
90mA L8 VDDC_34 AC11
MPLL_PVDD VDDC_35

1U_0402_10V6-K
AC13
Only available on TOPAZ, NC balls on JET

C
VDDC_36
10U_0603_6.3V6-M

10U_0603_6.3V6-M

1U_0402_10V6-K

BLM18PG221SN1D_2P SPLL_PVDD 1
1 1 1 TOPAZ_VDDC_SEN
AC20
75mA FB_VDDC TOPAZ_VDDC_RTN

DIS@
H7 AD20
SPLL_PVDD FB_GND_1 2
DIS@

DIS@

DIS@

2 2 2 SPLL_VDDC
R21
BIF_VDDC_1 U21
100mA H8 BIF_VDDC_2
SPLL_VDDC +VGA_CORE
C C
J7 ISOLATED
+1.8VS_VGA SPLL_PVSS
CORE I/O
M13 CV59 CV60 CV61 CV62 CV63 CV64 CV65
VDDCI_1

C
LV4 M15
VDDCI_2

10U_0603_6.3V6-M

10U_0603_6.3V6-M

0.1U_0402_10V7-K

0.1U_0402_10V7-K
1 2 CV20 CV21 M16
VDDCI_3

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K
M17 1 1 1 1 1 1 1
VDDCI_4
10U_0603_6.3V6-M

BLM18PG121SN1D_2P M18
VDDCI_5
1U_0402_10V6-K

1 1 M20
VDDCI_6
DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
DIS@ M21
VDDCI_7 N20 2 2 2 2 2 2 2
VDDCI_8
DIS@

DIS@

2 2 W1

F
FB_VDDCI W3
FB_GND_2

216-0858020-A0_FCBGA631
+0.95VS_VGA

LV5
1 2 CV24 CV25
FOR JET,PUT VIAS UNDER ASIC +VGA_CORE
0.1U_0402_10V7-K

C
BLM18PG121SN1D_2P
1U_0402_10V6-K

DIS@ 1 1 VDDC_SEN RV1 1 EXO@ 2 0_0402_5%

[79] VDDC_SEN
DIS@

DIS@

2 2 VDDC_RTN RV2 1 EXO@ 2 0_0402_5%

[79] VDDC_RTN

L
MESO@
VDDC_SEN RV3 1 2 0_0402_5% TOPAZ_VDDC_SEN

D D
MESO@
VDDC_RTN RV4 1 2 0_0402_5% TOPAZ_VDDC_RTN

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 Topaz & Jet Core Power
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 26 of 83
1 2 3 4 5
 5 4 3 2 1

l
UV3C @ UV3D @ UV3E @

DP POWER NC/DP POWER

a
AG15 AE11 AL15 AA27 A3
AG16 NC_DP_VDDR_1 NC_50 AF11 NC_UPHYAB_TMDPA_TX0N AB24 GND_1 GND_65 A30
AK14
AF16 NC_DP_VDDR_2 NC_51 AE13 NC_UPHYAB_TMDPA_TX0P AB32 GND_2 GND_66 AA13
AG17 NC_DP_VDDR_3 NC_52 AF13 AC24 GND_3 GND_67 AA16
D AH16 D

i
+1.8VS_VGA AG18 NC_DP_VDDR_4 NC_53 AG8 NC_UPHYAB_TMDPA_TX1N AC26 GND_4 GND_68 AB10
AJ15
AG19 NC_DP_VDDR_5 NC_54 AG10 NC_UPHYAB_TMDPA_TX1P AC27 GND_5 GND_69 AB15
CV66 CV67 AF14 NC_DP_VDDR_6 NC_55 AD25 GND_6 GND_70 AB6
AL17
DP_VDDR NC_UPHYAB_TMDPA_TX2N AD32 GND_7 GND_71 AC9
AK16
GND_8 GND_72

t
NC_UPHYAB_TMDPA_TX2P
10U_0603_6.3V6-M
AE27 AD6
GND_9 GND_73

1U_0402_10V6-K
1 1 AH18 AF32 AD8
NC_UPHYAB_TMDPA_TX3N AG27 GND_10 GND_74 AE7
AJ17
AG20 AF6 NC_UPHYAB_TMDPA_TX3P AH32 GND_11 GND_75 AG12
NC_DP_VDDC_1 NC_56 GND_12 GND_76
DIS@

DIS@

AG21 AF7 AL19 K28 AH10

2 2 AF22 NC_DP_VDDC_2 NC_57 AF8 NC_TXOUT_L3P K32 GND_13 GND_77 AH28
AK18
AG22 NC_DP_VDDC_3 NC_58 AF9 NC_TXOUT_L3N L27 GND_14 GND_78 B10
AD14 NC_DP_VDDC_4 NC_59 M32 GND_15 GND_79 B12

n
DP_VDDC NC_TMDP N25 GND_16 GND_80 B14
N27 GND_17 GND_81 B16
P25 GND_18 GND_82 B18
AH20
AG14 AE1 NC_UPHYAB_TMDPB_TX0N P32 GND_19 GND_83 B20
AJ19
+0.95VS_VGA AH14 NC_DP_VSSR_1 NC_60 AE3 NC_UPHYAB_TMDPB_TX0P R27 GND_20 GND_84 B22
AM14 NC_DP_VSSR_2 NC_61 AG1 T25 GND_21 GND_85 B24
AL21

e
CV70 CV71 AM16 NC_DP_VSSR_3 NC_62 AG6 NC_UPHYAB_TMDPB_TX1N T32 GND_22 GND_86 B26
AK20
AM18 NC_DP_VSSR_4 NC_63 AH5 NC_UPHYAB_TMDPB_TX1P U25 GND_23 GND_87 B6
NC_DP_VSSR_5 NC_64 GND_24 GND_88
0.1U_0402_10V7-K

AF23 AF10 AH22 U27 B8

NC_DP_VSSR_6 NC_65 NC_UPHYAB_TMDPB_TX2N GND_25 GND_89
1U_0402_10V6-K

1 1 AG23 AG9 AJ21 V32 C1

AM20 NC_DP_VSSR_7 NC_66 AH8 NC_UPHYAB_TMDPB_TX2P W25 GND_26 GND_90 C32
AM22 NC_DP_VSSR_8 NC_67 AM6 W26 GND_27 GND_91 E28
AL23
NC_DP_VSSR_9 NC_68 NC_UPHYAB_TMDPB_TX3N GND_28 GND_92
DIS@

DIS@

AM24 AM8 AK22 W27 F10

2 2 NC_DP_VSSR_10 NC_69 NC_UPHYAB_TMDPB_TX3P GND_29 GND_93

d
AF19 AG7 Y25 F12
AF20 NC_DP_VSSR_11 NC_70 AG11 Y32 GND_30 GND_94 F14
AK24
AE14 NC_DP_VSSR_12 NC_71 NC_TXOUT_U3P GND_31 GND_95 F16
AJ23
DP_VSSR NC_TXOUT_U3N GND_96 F18
GND_97 F2

i
GND_98 F20
AF17 AE10 M6 GND_99 F22
NC_UPHYAB_DP_CALR NC_72 N13 GND_32 GND_100 F24
216-0858020-A0_FCBGA631 N16 GND_33 GND_101 F26
C GND_34 GND_102 C

f
N18 F6
N21 GND_35 GND_103 F8
GND_36 GND GND_104
216-0858020-A0_FCBGA631 P6 G10
P9 GND_37 GND_105 G27
R12 GND_38 GND_106 G31
R15 GND_39 GND_107 G8
R17 GND_40 GND_108 H14
R20 GND_41 GND_109 H17

n
T13 GND_42 GND_110 H2
T16 GND_43 GND_111 H20
T18 GND_44 GND_112 H6
T21 GND_45 GND_113 J27
T6 GND_46 GND_114 J31
U15 GND_47 GND_115 K11
U17 GND_48 GND_116 K2

o
U20 GND_49 GND_117 K22
U9 GND_50 GND_118 K6
V13 GND_51 GND_119
V16 GND_52
V18 GND_53
ASIC Ball Topaz Jet ASIC Ball Topaz Jet Y10 GND_54
Y15 GND_55
Y17 GND_56
U10,T10 VDDC NC U1 BP_0 NC GND_57
Y20
AB13,W9 R11 GND_58 A32

C
AB11,AB12 U3 BP_1 NC T11 GND_59 VSS_MECH_1 AM1
GND_60 VSS_MECH_2
AC11,AC13 AA11
GND_61 VSS_MECH_3
AM32
AC14,Y9,W10 M12
N11 GND_62
AM26 DIECRACKMON NC GND_63
V11
GND_64
Y11 NC DBG_DATA13
AC20 FB_VDDC NC
216-0858020-A0_FCBGA631
B AE9 NC DBG_DATA14 B
AD20 FB_VSS NC
L9 NC DBG_DATA15

C
W1 FB_VDDCI NC
N9 NC DBG_DATA16
W3 FB_VSS NC
AE8 NC DBG_DATA12
AJ11 GPIO_SVC NC_SVI2
AL9 NC DBG_CNTL0

F
AK12 GPIO_SVD NC_SVI2
H13,H16,H19,J10 VMEMIO VDDR1
AL11 GPIO_SVT NC_SVI2 J23,J24,J9,K10
K23,K24,K9,L11
N6 GPIO_11 NC_GPIO11 L12,L13,L20,L21
L22 Bits5 Bits4 Bits3 Bits2 Bits1

C
N5 GPIO_12 NC_GPIO12
PS0 1 1 0 0 1
AA17,AA18 VDD_GPIO33 VDDR3
N3 GPIO_13 NC_GPIO13 AB17,AB18
PS1 1 1 0 0 0
AJ27 WAKEB NC_VSYNC
AA20,AA21 VDD_GPIO18 VDD_CT PS2 0 0 0 0 0
AB20,AB21

L
T8 PCC/GPIO_6 GPIO_6
PS3 1 1 ? ? ?
A
AA3 PLL_ANALOG_OUT NC A

AA1 PLL_ANALOG_IN NC

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 Topaz & Jet DP Power/GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

WWW.AliSaler.Com
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 27 of 83
5 4 3 2 1
 1 2 3 4 5

[29,30]

[29,30]

[29,30]

[29,30]
FBA_DQS[7..0]

FBA_DQM[7..0]

FBA_DQS#[7..0]

FBA_D[0..63]
FBA_D[0..63]
FBA_MA[15..0]

FBA_BA[2..0]
[29,30]

[29,30]
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
K27
J29
H30
H32
G29
F28
F32
F30
C30
F27
A28
UV3F

GDDR5/DDR3

DQA0_0
DQA0_1
DQA0_2
DQA0_3
DQA0_4
DQA0_5
DQA0_6
DQA0_7
DQA0_8
DQA0_9
GDDR5/DDR3

MAA0_0
MAA0_1
MAA0_2
MAA0_3
MAA0_4
MAA0_5
MAA0_6
MAA0_7
MAA0_8
MAA0_9
@

K17
J20
H23
G23
G24
H24
J19
K19
G20
L17
FBA_MA0
FBA_MA1
FBA_MA2
FBA_MA3
FBA_MA4
FBA_MA5
FBA_MA6
FBA_MA7
FBA_MA13
FBA_MA15

it al A

n
FBA_D11 C28 DQA0_10 J14 FBA_MA8
FBA_D12 E27 DQA0_11 MAA1_0 K14 FBA_MA9
FBA_D13 G26 DQA0_12 MAA1_1 J11 FBA_MA10
FBA_D14 D26 DQA0_13 MAA1_2 J13 FBA_MA11
FBA_D15 F25 DQA0_14 MAA1_3 H11 FBA_MA12
FBA_D16 A25 DQA0_15 MAA1_4 G11 FBA_BA2

e
FBA_D17 C25 DQA0_16 MAA1_5 J16 FBA_BA0
DQA0_17 MAA1_6

MEMORY INTERFACE
FBA_D18 E25 L15 FBA_BA1
FBA_D19 D24 DQA0_18 MAA1_7 G14 FBA_MA14
FBA_D20 E23 DQA0_19 MAA1_8 L16
FBA_D21 F23 DQA0_20 MAA1_9
FBA_D22 D22 DQA0_21 E32 FBA_DQM0
FBA_D23 F21 DQA0_22 WCKA0_0 E30 FBA_DQM1
FBA_D24 DQA0_23 WCKA0B_0 FBA_DQM2

d
E21 A21
FBA_D25 D20 DQA0_24 WCKA0_1 C21 FBA_DQM3
FBA_D26 F19 DQA0_25 WCKA0B_1 E13 FBA_DQM4
FBA_D27 A19 DQA0_26 WCKA1_0 D12 FBA_DQM5
FBA_D28 D18 DQA0_27 WCKA1B_0 E3 FBA_DQM6

if
FBA_D29 F17 DQA0_28 WCKA1_1 F4 FBA_DQM7
+1.35VS_VGA FBA_D30 A17 DQA0_29 WCKA1B_1
FBA_D31 C17 DQA0_30 H28 FBA_DQS0
FBA_D32 E17 DQA0_31 EDCA0_0 C27 FBA_DQS1
B FBA_D33 D16 DQA1_0 EDCA0_1 A23 FBA_DQS2 B
FBA_D34 F15 DQA1_1 EDCA0_2 E19 FBA_DQS3
DQA1_2 EDCA0_3
1
FBA_D35 A15 E15 FBA_DQS4
RV5 FBA_D36 D14 DQA1_3 EDCA1_0 D10 FBA_DQS5
40.2_0402_1% FBA_D37 F13 DQA1_4 EDCA1_1 D6 FBA_DQS6
DIS@ FBA_D38 A13 DQA1_5 EDCA1_2 G5 FBA_DQS7
FBA_D39 C13 DQA1_6 EDCA1_3
2

FBA_D40 E11 DQA1_7 H27 FBA_DQS#0

n
CV72 FBA_D41 A11 DQA1_8 DDBIA0_0 A27 FBA_DQS#1
FBA_D42 C11 DQA1_9 DDBIA0_1 C23 FBA_DQS#2
FBA_D43 F11 DQA1_10 DDBIA0_2 C19 FBA_DQS#3
DQA1_11 DDBIA0_3
1

FBA_D44 FBA_DQS#4

1U_0402_10V6-K
1 A9 C15
RV6 FBA_D45 C9 DQA1_12 DDBIA1_0 E9 FBA_DQS#5
100_0402_5% FBA_D46 F9 DQA1_13 DDBIA1_1 C5 FBA_DQS#6
+1.35VS_VGA FBA_D47 DQA1_14 DDBIA1_2 FBA_DQS#7
DIS@
DIS@ D8 H4

o
2 FBA_D48 E7 DQA1_15 DDBIA1_3
2

FBA_D49 A7 DQA1_16 L18 FBA_ODTA0

FBA_D50 DQA1_17 ADBIA0 FBA_ODTA1 FBA_ODTA0 [29]
C7 K16
FBA_D51 DQA1_18 ADBIA1 FBA_ODTA1 [30]
F7
DQA1_19
1

FBA_D52 A5 H26 FBA_CLKA0

FBA_D53 DQA1_20 CLKA0 FBA_CLKA0# FBA_CLKA0 [29]
RV7 E5 H25
FBA_D54 DQA1_21 CLKA0B FBA_CLKA0# [29]
40.2_0402_1% C3
DIS@ FBA_D55 E1 DQA1_22 G9 FBA_CLKA1
FBA_D56 DQA1_23 CLKA1 FBA_CLKA1# FBA_CLKA1 [30]
G7 H9
FBA_CLKA1# [30]
2

FBA_D57 G6 DQA1_24 CLKA1B

C
CV73 FBA_D58 G1 DQA1_25 G22 FBA_RASA0#
FBA_D59 DQA1_26 RASA0B FBA_RASA1# FBA_RASA0# [29]
G3 G17
FBA_D60 DQA1_27 RASA1B FBA_RASA1# [30]
J6
DQA1_28
1

FBA_D61 FBA_CASA0#
1U_0402_10V6-K

1 J1 G19
FBA_D62 DQA1_29 CASA0B FBA_CASA1# FBA_CASA0# [29]
RV8 J3 G16
FBA_D63 DQA1_30 CASA1B FBA_CASA1# [30]
100_0402_5% J5
DQA1_31 FBA_CSA0#
DIS@

DIS@ H22
2 CSA0B_0 FBA_CSA0# [29]
K26 J22
2

J26 MVREFDA_1 CSA0B_1

MVREFSA_2 G13 FBA_CSA1#
C C
CSA1B_0 FBA_CSA1# [30]
J25 K13
RV14 1 DIS@ 2 120_0402_1% K25 NC_120 CSA1B_1
MEM_CALRP0 K20 FBA_CKEA0
CKEA0 FBA_CKEA1 FBA_CKEA0 [29]

C
J17
CKEA1 FBA_CKEA1 [30]
RV9 DIS@ RV10 DIS@ G25 FBA_WEA0#
FBA_RST# WEA0B FBA_WEA1# FBA_WEA0# [29]
1 2 1 2 L10 H10
[29,30] FBA_RST# DRAM_RST WEA1B FBA_WEA1# [30]
49.9_0402_1% 10_0402_5% K8
L7 CLKTESTA
CLKTESTB
1

1 1
CV74 RV11 CV75 TPV15 1 Test_Point_32MIL

F
120P_0402_50V8-J 5.1K_0402_5% 68P_0402_50V8-J
DIS@ DIS@ @ 216-0858020-A0_FCBGA631
2 2 TPV16 1 Test_Point_32MIL
2

0.1U_0402_10V7-K

0.1U_0402_10V7-K

CV76 1 CV77 1
@

C
2 2
1

RV12 RV13
51.1_0402_1% 51.1_0402_1%
@ @

L
2

D D

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 Topaz & Jet MEM Interface
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 28 of 83
1 2 3 4 5
 1 2 3 4 5

l
Memory Partition A - Lower 32 bits
FBA_MA[15..0] [28,30]
UV6 X76@
UV5 X76@

a
+FBA_VREFD0_L FBA_D17 FBA_BA[2..0] [28,30]
M8 E3
+FBA_VREFC0_U M8 E3 FBA_D2 H1 VREFCA DQL0 F7 FBA_D20
VREFCA DQL0 FBA_D5 VREFDQ DQL1 FBA_D23 FBA_DQS[7..0] [28,30]
H1 F7 F2
VREFDQ DQL1 F2 FBA_D0 FBA_MA0 N3 DQL2 F8 FBA_D21
A Group2 (IN1) FBA_DQM[7..0] [28,30] A

i
FBA_MA0 N3 DQL2 F8 FBA_D4 FBA_MA1 P7 A0 DQL3 H3 FBA_D16
FBA_MA1 P7 A0 DQL3 H3 FBA_D1 FBA_MA2 P3 A1 DQL4 H8 FBA_D18
FBA_MA2 A1 DQL4 FBA_D6 Group0 (IN3) FBA_MA3 A2 DQL5 FBA_D19 FBA_DQS#[7..0] [28,30]
P3 H8 N2 G2
FBA_MA3 N2 A2 DQL5 G2 FBA_D3 FBA_MA4 P8 A3 DQL6 H7 FBA_D22
A3 DQL6 A4 DQL7 FBA_D[0..63] [28,30]

t
FBA_MA4 P8 H7 FBA_D7 FBA_MA5 P2
FBA_MA5 P2 A4 DQL7 FBA_MA6 R8 A5
FBA_MA6 R8 A5 FBA_MA7 R2 A6 D7 FBA_D9
FBA_MA7 R2 A6 D7 FBA_D31 FBA_MA8 T8 A7 DQU0 C3 FBA_D10
FBA_MA8 T8 A7 DQU0 C3 FBA_D27 FBA_MA9 R3 A8 DQU1 C8 FBA_D13
FBA_MA9 R3 A8 DQU1 C8 FBA_D30 FBA_MA10 L7 A9 DQU2 C2 FBA_D12
FBA_MA10 A9 DQU2 FBA_D25 FBA_MA11 A10/AP DQU3 FBA_D8 Group1 (TOP)
L7 C2 R7 A7
FBA_MA11 R7 A10/AP DQU3 A7 FBA_D28 FBA_MA12 N7 A11 DQU4 A2 FBA_D14

n
FBA_MA12 A11 DQU4 FBA_D24 Group3 (BOT) FBA_MA13 A12/BC DQU5 FBA_D15
N7 A2 T3 B8
FBA_MA13 T3 A12/BC DQU5 B8 FBA_D29 FBA_MA14 T7 A13 DQU6 A3 FBA_D11
FBA_MA14 T7 A13 DQU6 A3 FBA_D26 A14 DQU7
A14 DQU7 +1.35VS_VGA
+1.35VS_VGA
FBA_BA0 M2 B2

e
FBA_BA0 M2 B2 FBA_BA1 N8 BA0 VDD_1 D9
FBA_BA1 N8 BA0 VDD_1 D9 FBA_BA2 M3 BA1 VDD_2 G7
FBA_BA2 M3 BA1 VDD_2 G7 BA2 VDD_3 K2 +1.35VS_VGA
BA2 VDD_3 K2 VDD_4 K8
VDD_4 K8 VDD_5 N1
VDD_5 VDD_6

1
N1 FBA_CLKA0 J7 N9
FBA_CLKA0 J7 VDD_6 N9 FBA_CLKA0# K7 CK VDD_7 R1 RV18
[28] FBA_CLKA0 FBA_CLKA0# CK VDD_7 FBA_CKEA0 CK VDD_8

d
K7 R1 K9 R9 4.99K_0402_1%
[28] FBA_CLKA0# FBA_CKEA0 CK VDD_8 CKE VDD_9
K9 R9 DIS@
[28] FBA_CKEA0 CKE VDD_9

2
FBA_ODTA0 K1 A1 CV100 +FBA_VREFC0_U
FBA_ODTA0 K1 A1 FBA_CSA0# L2 ODT VDDQ_1 A8

i
[28] FBA_ODTA0 FBA_CSA0# ODT VDDQ_1 FBA_RASA0# CS VDDQ_2

0.1U_0402_10V7-K
L2 A8 J3 C1
[28] FBA_CSA0# CS VDDQ_2 RAS VDDQ_3

1
FBA_RASA0# J3 C1 FBA_CASA0# K3 C9
[28] FBA_RASA0# FBA_CASA0# RAS VDDQ_3 FBA_WEA0# CAS VDDQ_4 1
K3 C9 L3 D2 RV19
[28] FBA_CASA0# FBA_WEA0# CAS VDDQ_4 WE VDDQ_5
L3 D2 E9 4.99K_0402_1%
B [28] FBA_WEA0# WE VDDQ_5 VDDQ_6 B

DIS@
f
E9 F1 DIS@
VDDQ_6 F1 FBA_DQS2 F3 VDDQ_7 H2 2

2
FBA_DQS0 F3 VDDQ_7 H2 FBA_DQS1 C7 DQSL VDDQ_8 H9
FBA_DQS3 C7 DQSL VDDQ_8 H9 DQSU VDDQ_9
DQSU VDDQ_9
FBA_DQM2 E7 A9
FBA_DQM0 E7 A9 FBA_DQM1 D3 DML VSS_1 B3
FBA_DQM3 D3 DML VSS_1 B3 DMU VSS_2 E1

n
DMU VSS_2 E1 VSS_3 G8
VSS_3 G8 FBA_DQS#2 G3 VSS_4 J2
FBA_DQS#0 G3 VSS_4 J2 FBA_DQS#1 B7 DQSL VSS_5 J8
FBA_DQS#3 B7 DQSL VSS_5 J8 DQSU VSS_6 M1 +1.35VS_VGA
DQSU VSS_6 M1 VSS_7 M9
VSS_7 M9 VSS_8 P1
VSS_8 VSS_9

1
P1 FBA_RST# T2 P9
VSS_9

o
FBA_RST# T2 P9 RESET VSS_10 T1 RV24
[28,30] FBA_RST# RESET VSS_10 VSS_11
T1 L8 T9 4.99K_0402_1%
L8 VSS_11 T9 ZQ VSS_12 DIS@
ZQ VSS_12

2
J1 B1 CV103 +FBA_VREFD0_L
NC1 VSSQ_1
1

1
J1 B1 L1 B9
NC1 VSSQ_1 NC2 VSSQ_2

0.1U_0402_10V7-K
RV15 RV16 L1 B9 RV17 J9 D1
NC2 VSSQ_2 NC3 VSSQ_3

1
10K_0402_5% 243_0402_1% J9 D1 243_0402_1% L9 D8 1
@ DIS@ L9 NC3 VSSQ_3 D8 DIS@ FBA_MA15 M7 NC4 VSSQ_4 E2 RV25
FBA_MA15 M7 NC4 VSSQ_4 E2 NC5 VSSQ_5 E8 4.99K_0402_1%

C
2

2
NC5 VSSQ_5 VSSQ_6

DIS@
E8 F9 DIS@
VSSQ_6 F9 VSSQ_7 G1 2

2
VSSQ_7 G1 VSSQ_8 G9
VSSQ_8 G9 VSSQ_9
VSSQ_9 96-BALL
96-BALL SDRAM DDR3
SDRAM DDR3 K4W4G1646D-BC1A_FBGA96
K4W4G1646D-BC1A_FBGA96

C C

FBA_CLKA0

C
+1.35VS_VGA UV6 SIDE +1.35VS_VGA UV7 SIDE

1
CV78 CV79 CV80 CV81 CV82 CV83 CV89 CV90 CV91 CV92 CV93 CV94 RV26
40.2_0402_1%
10U_0603_6.3V6-M

10U_0603_6.3V6-M

DIS@
1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1 1 1 1 1 1 1 1 1 1 1 1

2
CV104 DIS@
1 2

F
DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

2 2 2 2 2 2 2 2 2 2 2 2 .01U_0402_16V7-K

1
RV27
40.2_0402_1%
DIS@

2
+1.35VS_VGA UV6 SIDE +1.35VS_VGA UV7 SIDE FBA_CLKA0#

C
CV84 CV85 CV86 CV87 CV88 CV95 CV96 CV97 CV98 CV99
0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

1 1 1 1 1 1 1 1 1 1
DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

2 2 2 2 2 2 2 2 2 2

L
D D

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 Topaz & Jet DDR3 VRAM U
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

WWW.AliSaler.Com
Size Document Number Rev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 29 of 83
1 2 3 4 5
 1 2 3 4 5

l
Memory Partition A - Upper 32 bits
UV7 X76@

a
FBA_MA[15..0] [28,29]
UV8 X76@
+FBA_VREFC1_U M8 E3 FBA_D36
VREFCA DQL0 FBA_D34 +FBA_VREFD1_L FBA_D60 FBA_BA[2..0] [28,29]
H1 F7 M8 E3
VREFDQ DQL1 F2 FBA_D37 H1 VREFCA DQL0 F7 FBA_D58
A A
FBA_DQS[7..0] [28,29]

it
FBA_MA0 N3 DQL2 F8 FBA_D35 VREFDQ DQL1 F2 FBA_D63
FBA_MA1 P7 A0 DQL3 H3 FBA_D39 FBA_MA0 N3 DQL2 F8 FBA_D59
FBA_MA2 A1 DQL4 FBA_D32 Group4 (IN1) FBA_MA1 A0 DQL3 FBA_D56 FBA_DQM[7..0] [28,29]
P3 H8 P7 H3 Group7 (IN3)
FBA_MA3 N2 A2 DQL5 G2 FBA_D38 FBA_MA2 P3 A1 DQL4 H8 FBA_D62
FBA_MA4 A3 DQL6 FBA_D33 FBA_MA3 A2 DQL5 FBA_D57 FBA_DQS#[7..0] [28,29]
P8 H7 N2 G2
FBA_MA5 P2 A4 DQL7 FBA_MA4 P8 A3 DQL6 H7 FBA_D61
FBA_MA6 A5 FBA_MA5 A4 DQL7 FBA_D[0..63] [28,29]
R8 P2
FBA_MA7 R2 A6 D7 FBA_D41 FBA_MA6 R8 A5
FBA_MA8 T8 A7 DQU0 C3 FBA_D47 FBA_MA7 R2 A6 D7 FBA_D55
FBA_MA9 R3 A8 DQU1 C8 FBA_D42 FBA_MA8 T8 A7 DQU0 C3 FBA_D51
FBA_MA10 L7 A9 DQU2 C2 FBA_D43 FBA_MA9 R3 A8 DQU1 C8 FBA_D54
FBA_MA11 R7 A10/AP DQU3 A7 FBA_D44 FBA_MA10 L7 A9 DQU2 C2 FBA_D48

n
FBA_MA12 A11 DQU4 FBA_D46 Group5 (TOP) FBA_MA11 A10/AP DQU3 FBA_D52
N7 A2 R7 A7 Group6 (BOT)
FBA_MA13 T3 A12/BC DQU5 B8 FBA_D45 FBA_MA12 N7 A11 DQU4 A2 FBA_D50 +1.35VS_VGA
FBA_MA14 T7 A13 DQU6 A3 FBA_D40 FBA_MA13 T3 A12/BC DQU5 B8 FBA_D53
A14 DQU7 FBA_MA14 T7 A13 DQU6 A3 FBA_D49
A14 DQU7

1
+1.35VS_VGA RV30
+1.35VS_VGA

e
FBA_BA0 M2 B2 4.99K_0402_1%
FBA_BA1 N8 BA0 VDD_1 D9 FBA_BA0 M2 B2 DIS@
FBA_BA2 M3 BA1 VDD_2 G7 FBA_BA1 N8 BA0 VDD_1 D9

2
BA2 VDD_3 K2 FBA_BA2 M3 BA1 VDD_2 G7 CV127 +FBA_VREFC1_U
VDD_4 K8 BA2 VDD_3 K2
VDD_5 VDD_4

0.1U_0402_10V7-K
N1 K8
VDD_6 VDD_5

1
FBA_CLKA1 J7 N9 N1
[28] FBA_CLKA1 FBA_CLKA1# K7 CK VDD_7 FBA_CLKA1 VDD_6 1

d
R1 J7 N9 RV31
[28] FBA_CLKA1# FBA_CKEA1 K9 CK VDD_8 FBA_CLKA1# CK VDD_7
R9 K7 R1 4.99K_0402_1%
[28] FBA_CKEA1 CKE VDD_9 FBA_CKEA1 CK VDD_8

DIS@
K9 R9 DIS@
CKE VDD_9 2

2
FBA_ODTA1 K1 A1

if
[28] FBA_ODTA1 FBA_CSA1# ODT VDDQ_1 FBA_ODTA1
L2 A8 K1 A1
[28] FBA_CSA1# FBA_RASA1# CS VDDQ_2 FBA_CSA1# ODT VDDQ_1
J3 C1 L2 A8
[28] FBA_RASA1# FBA_CASA1# RAS VDDQ_3 FBA_RASA1# CS VDDQ_2
K3 C9 J3 C1
[28] FBA_CASA1# FBA_WEA1# CAS VDDQ_4 FBA_CASA1# RAS VDDQ_3
L3 D2 K3 C9
B [28] FBA_WEA1# WE VDDQ_5 FBA_WEA1# CAS VDDQ_4 B
E9 L3 D2
VDDQ_6 F1 WE VDDQ_5 E9
FBA_DQS4 F3 VDDQ_7 H2 VDDQ_6 F1
FBA_DQS5 C7 DQSL VDDQ_8 H9 FBA_DQS7 F3 VDDQ_7 H2 +1.35VS_VGA
DQSU VDDQ_9 FBA_DQS6 C7 DQSL VDDQ_8 H9
DQSU VDDQ_9

1
FBA_DQM4 E7 A9
FBA_DQM5 D3 DML VSS_1 B3 FBA_DQM7 E7 A9 RV36

n
DMU VSS_2 E1 FBA_DQM6 D3 DML VSS_1 B3 4.99K_0402_1%
VSS_3 G8 DMU VSS_2 E1 DIS@
FBA_DQS#4 G3 VSS_4 J2 VSS_3 G8

2
FBA_DQS#5 B7 DQSL VSS_5 J8 FBA_DQS#7 G3 VSS_4 J2 CV130 +FBA_VREFD1_L
DQSU VSS_6 M1 FBA_DQS#6 B7 DQSL VSS_5 J8
VSS_7 DQSU VSS_6

0.1U_0402_10V7-K
M9 M1
VSS_8 VSS_7

1
P1 M9 1
VSS_9

o
FBA_RST# T2 P9 VSS_8 P1 RV37
[28,29] FBA_RST# RESET VSS_10 FBA_RST# VSS_9
T1 T2 P9 4.99K_0402_1%
VSS_11 RESET VSS_10

DIS@
L8 T9 T1 DIS@
ZQ VSS_12 L8 VSS_11 T9 2

2
ZQ VSS_12
1

J1 B1
NC1 VSSQ_1

1
RV28 L1 B9 J1 B1
243_0402_1% J9 NC2 VSSQ_2 D1 RV29 L1 NC1 VSSQ_1 B9
DIS@ L9 NC3 VSSQ_3 D8 243_0402_1% J9 NC2 VSSQ_2 D1
FBA_MA15 M7 NC4 VSSQ_4 E2 DIS@ L9 NC3 VSSQ_3 D8

C
2

NC5 VSSQ_5 E8 FBA_MA15 M7 NC4 VSSQ_4 E2

2
VSSQ_6 F9 NC5 VSSQ_5 E8
VSSQ_7 G1 VSSQ_6 F9
VSSQ_8 G9 VSSQ_7 G1
VSSQ_9 VSSQ_8 G9 FBA_CLKA1
96-BALL VSSQ_9
SDRAM DDR3 96-BALL

1
K4W4G1646D-BC1A_FBGA96 SDRAM DDR3
K4W4G1646D-BC1A_FBGA96 RV38
C 40.2_0402_1% C
DIS@

2
CV131 DIS@

C
1 2
+1.35VS_VGA UV8 SIDE +1.35VS_VGA UV9 SIDE
.01U_0402_16V7-K

1
CV105 CV106 CV107 CV108 CV109 CV110 CV116 CV117 CV118 CV119 CV120 CV121
RV39
10U_0603_6.3V6-M

10U_0603_6.3V6-M

40.2_0402_1%
1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1 1 1 1 1 1 1 1 1 1 1 1 DIS@

2
F
FBA_CLKA1#
DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

2 2 2 2 2 2 2 2 2 2 2 2

+1.35VS_VGA UV8 SIDE +1.35VS_VGA UV9 SIDE

CV111 CV112 CV113 CV114 CV115 CV122 CV123 CV124 CV125 CV126

C
0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

1 1 1 1 1 1 1 1 1 1
DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

2 2 2 2 2 2 2 2 2 2

L
D D

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 Topaz & Jet DDR3 VRAM L
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 30 of 83
1 2 3 4 5
 5 4 3 2 1

i a l D

n t
i d e
f
C C

o n
B

C B

F C
A

L C Security Classification
Issued Date 2013/09/07
LC Future Center Secret Data
Deciphered Date 2014/09/07
Title

XXXX
A

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 31 of 83
5 4 3 2 1
 5 4 3 2 1

it al D

e n
C

if d C

o n
B

C B

F C
A

L C Security Classification
Issued Date 2013/09/07
LC Future Center Secret Data
Deciphered Date 2014/09/07
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Title

XXXX
Size Document Number
Custom
BE460_NM-A551
R ev
1.0
A

Date: Wednesday, August 05, 2015 Sheet 32 of 83

5 4 3 2 1
 1 2 3 4 5

+1.35V to +1.35VS_VGA +1.8VALW to +1.8VS_VGA

l
+1.35V +1.8VALW
VIN 1.8V (VBIAS=5V),
DIS@
IMAX=6A, Rds=15mohm VIN 1.8V (VBIAS=5V),
DIS@
IMAX=6A, Rds=15mohm
UV11 UV12 Bit
1 5 1 5
MLPS
VIN1 GND +1.35VS_VGA VIN1 GND +1.8VS_VGA
2 6 CV165 1DIS@ 2820P_0402_50V7-K 2 6 CV178 1DIS@ 2820P_0402_50V7-K
5 4 3 2 1
1 1

a
+5VALW VIN2 CT +5VALW VIN2 CT
CV163 3 7 +1.35VS_VGA CV176 18PWRON_R 3 7 +1.8VS_VGA
ON VOUT1 ON VOUT1 PS_0[5:1] 1 1 0 0 1
1U_0402_6.3V6-K 1U_0402_6.3V6-K
A
2@ 4 8 2@ 4 8 A
1 1

i
VBIAS VOUT2 VBIAS VOUT2
9 9
PS_1[5:1] 1 1 0 0 0
1 CV166 1 CV177
THERMALPAD 0.1U_0402_10V7-K THERMALPAD 0.1U_0402_10V7-K
CV164 2@ CV175 2@
PS_2[5:1] 1 1 0 0 0

t
0.1U_0402_10V7-K 0.1U_0402_10V7-K
2 DIS@ 2 DIS@
TPS22965DSGR_WSON8_2X2 TPS22965DSGR_WSON8_2X2
PS_3[5:1] 1 1 X X X
SCS00007P00
From FCH DGPU_PWROK RB751V-40_SOD323-2

n
[14,15,79] DGPU_PWROK
DV6 1 2 DIS@

RV153
VGA_ON 1 2 18PWRON_R

e
22K_0402_5% 1

1
DIS@ CV179
RV152 0.22U_0402_10V6-K
100K_0402_5% DIS@
@ 2

2
d
+1VALW to +1VS_VGA

i
+5VS +1VALW +1VS_VGA
B B

f
QV9 DIS@
AO4430L_SO8 PS_0[1] ROM_CONFIG[0]
8 1
STRAP_BIOS_ROM_EN = 1
7 2 PS_0[2] ROM_CONFIG[1] ROM_CONFIG[2:0] = [001] 256MB
1

+5VALW 6 3
RV129 5 PS_0[3] ROM_CONFIG[2]
10K_0402_5%

n
1 1
DIS@ CV161 CV162
4

2
4.7U_0603_6.3V6-K 0.1U_0402_10V7-K
PS_0[4] N/A 1 (Default)
2

RV141 DIS@ @
1

300_0402_5% 2 2
2

RV143 DIS@
100K_0402_5% RV130 1 (Default)
PS_0[5] N/A

1
DIS@ @ 0_0402_5%

o
2

1
+0.95VS_VGA_GATE D RV142
2 2 1 DGPU_PWREN# PS_1[1] STRAP_BIF_GEN3_EN_A 0 = PCIe GEN3 is not supported
QV11
2N7002KW_SOT323-3 G
3

D 1 SB000019400 S
3 10K_0402_5%
5 QV10B CV160 DIS@ 0 = The CLKREQB power management
G 2N7002KDWH_SOT363-6 DIS@ 0.22U_0402_10V6-K
DIS@
PS_1[2] STRAP_BIF_CLK_PM_EN
DIS@ capability is disabled
S 2

C
4
6

VGA_ON 2
D
QV10A
SB000013A00
G PS_1[3] N/A 0 (Default)
2N7002KDWH_SOT363-6
S DIS@
1

PS_1[4] STRAP_TX_CFG_DRV_FULL_SWING 1 = The transmitter full-swing

SB000013A00 is enabled
C C
+1VS_VGA +0.95VS_VGA
PS_1[5] STRAP_TX_DEEMPH_EN 1 = Tx deemphasis enabled
JV1 @

C
1 2
1 2
PS_2[1] N/A 0 (Default)
JUMP_43X79

+3VS to +3VS_VGA PS_2[2] N/A 0 (Default)

F
PS_2[3] STRAP_BIOS_ROM_EN 0 = Disable the external BIOS ROM device
+5VALW +3VS +3VS_VGA

PS_2[4] N/A 1 (Default)

JV3 @
1

3 1 1 2
RV134 1 2
PS_2[5] N/A 1 (Default)

C
DIS@ 47K_0402_5% QV5 JUMP_43X39
AO3413_SOT23-3
G
2

DIS@ DIS@
2

RV138 PS_3[3..1]
470_0402_5%
PS_3[1] BOARD_CONFIG[0]
101 = Micron 2G
2

RV135 PS_3[2] BOARD_CONFIG[1] 110 = Samsung 2G

1

10K_0402_5% 111 = Hynix 2G

DIS@ PS_3[3] BOARD_CONFIG[2]

L
1

DGPU_PWREN# D RV139
QV8A 2 2 1 DGPU_PWREN#
G PS_3[4] N/A 1 (Default)
2N7002KDWH_SOT363-6
3

D D
D 1 10K_0402_5%
VGA_ON RV136 1 @ 2 0_0402_5% 5 QV8B CV169 DIS@ S
[6,14,24,79] VGA_ON DIS@
1

G 2N7002KDWH_SOT363-6 .01U_0402_16V7-K
PS_3[5] N/A 1 (Default)
1

DIS@ DIS@ SB000013A00

RV137 S 2
4

100K_0402_5% SB000013A00
@
2

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 Topaz & Jet swich power
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

WWW.AliSaler.Com
Size Document Number Rev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 33 of 83
1 2 3 4 5
 5 4 3 2 1

it al D

e n
C

if d C

o n
B

C B

F C
A

L C Security Classification
Issued Date 2013/09/07
LC Future Center Secret Data
Deciphered Date 2014/09/07
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Title

XXXX
Size Document Number
Custom
BE460_NM-A551
R ev
1.0
A

Date: Wednesday, August 05, 2015 Sheet 34 of 83

5 4 3 2 1
 5 4 3 2 1

i a l D

n t
i d e
f
C C

o n
B

C B

F C
A

L C Security Classification
Issued Date 2013/09/07
LC Future Center Secret Data
Deciphered Date 2014/09/07
Title

XXXX
A

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 35 of 83
5 4 3 2 1
 5 4 3 2 1

+3VS

+3VS
+3VS
USB3.0 Repeator Port 3

1
13
U16
VDD1
VDD2
U33@

it al D

n
AAA_EQ1 15 4 BBB_EQ1
AAA_DE0 A_EQ1_SDA_CTL B_EQ1_I2C_ADDR1 BBB_DE0
.01U_0402_16V7-K

16 3
AAA_EQ0 17 A_DE0_SCL_CTL B_DE0_I2C_ADDR0 2 BBB_EQ0
1
C189
1
Close U150 AAA_DE1 18 A_EQ0_NC
A_DE1_NC
B_EQ0_NC
B_DE1_NC
6 BBB_DE1
C184 U33@
USB3P4_TXP USB3P4_TXP_C USB3P4_RE_TXP_R 2 0_0402_5% USB3P4_RE_TXP
@

@ 0.1U_0402_10V7-K C185 1 2 0.1U_0402_10V7-K 19 12 R242 1 U33@

[15] USB3P4_TXP A_INp A_OUTp USB3P4_RE_TXP [38]

e
2 2 USB3P4_TXN C186 1 2 0.1U_0402_10V7-K USB3P4_TXN_C 20 11 USB3P4_RE_TXN_R R243 1 2 0_0402_5% USB3P4_RE_TXN
[15] USB3P4_TXN A_INn A_OUTn USB3P4_RE_TXN [38]
U33@ U33@
U33@
USB3P4_RXP R240 1 U33@ 2 0_0402_5% USB3P4_RXP_C 9 22 USB3P4_RE_RXP_R 0.1U_0402_10V7-K 2 1 C187 USB3P4_RE_RXP
[38] USB3P4_RXP USB3P4_RXN USB3P4_RXN_C B_INp B_OUTp USB3P4_RE_RXN_R USB3P4_RE_RXP [15]
R241 1 2 0_0402_5% 8 23 0.1U_0402_10V7-K 2 1 C188 USB3P4_RE_RXN
[38] USB3P4_RXN B_INn B_OUTn USB3P4_RE_RXN [15]
U33@
U33@

d
U33@ 1 5
R9455 1 2 4.99K_0402_1% TP941 7 PD# 10
TEST_2 14 REXT GND1 21
24 TEST GND2 25

if
I2C_EN GPAD
PS8713BTQFN24GTR2A_TQFN24_4X4

C C

+3VS
+3VS

n
Co-lay 0-ohm
+3VS
NU3R@ NU3R@
USB3P4_TXP R253 1 2 0_0402_5% USB3P4_TXP_R R255 1 2 0_0402_5% USB3P4_RE_TXP

o
AAA_EQ1 R246 1 @ 2 4.7K_0402_5% AAA_DE1 R250 1 @ 2 4.7K_0402_5%
USB3P4_TXN R254 1 2 0_0402_5% USB3P4_TXN_R R256 1 2 0_0402_5% USB3P4_RE_TXN
TEST_2 R244 1 @ 2 4.7K_0402_5%
BBB_EQ1 R248 1 @ 2 4.7K_0402_5% BBB_DE1 R252 1 @ 2 4.7K_0402_5% NU3R@ NU3R@
Normal LFPS mode
Internal PD EQ Default 9.5dB de-emohasis Default 3.5dB R259 R260 close to U16

C
NU3R@ NU3R@
Internal PD Internal PD USB3P4_RXP R257 1 2 0_0402_5% USB3P4_RXP_R R259 1 2 0_0402_5% USB3P4_RE_RXP

USB3P4_RXN R258 1 2 0_0402_5% USB3P4_RXN_R R260 1 2 0_0402_5% USB3P4_RE_RXN

NU3R@ NU3R@

B B

C
+3VS +3VS +3VS +3VS

F
2

2
R245 R249 R247 R251
@ 4.7K_0402_5% @ 4.7K_0402_5% @ 4.7K_0402_5% @ 4.7K_0402_5%
1

1
AAA_EQ0 AAA_DE0 BBB_EQ0 BBB_DE0

C
2

2
R9457 R9458 R9459 R9460
@ 4.7K_0402_5% @ 4.7K_0402_5% @ 4.7K_0402_5% @ 4.7K_0402_5%
1

5
L 4
Security Classification
Issued Date 2013/09/07
LC Future Center Secret Data
Deciphered Date 2014/09/07
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3 2
Title

Custom

Date:
XXXX
Size Document Number
BE460_NM-A551
Wednesday, August 05, 2015
1
Sheet 36 of 83
R ev
1.0
A
 5 4 3 2 1

DOCK_TX0+ DPRE@ CM1 1 2 0.1U_0402_10V7-K DOCK_TX0+_RE

l
[5] DOCK_TX0+ DP_RE_DP0P 1 2 DISP_A0P_L_C
DPRE@ CM13 0.1U_0402_10V7-K
DISP_A0P_L_C [38]
RM2 1 @ 2 0_0402_5% DOCK_TX0+_R
DOCK_TX0+_R NODPRE@ CM14 1 2 0.1U_0402_10V7-K

a
DOCK_TX0- DPRE@ CM2 1 2 0.1U_0402_10V7-K DOCK_TX0-_RE
[5] DOCK_TX0- DP_RE_DP0N 1 2 DISP_A0N_L_C
DPRE@ CM15 0.1U_0402_10V7-K
DISP_A0N_L_C [38]
D RM5 1 @ 2 0_0402_5% DOCK_TX0-_R D

i
DOCK_TX0-_R NODPRE@ CM16 1 2 0.1U_0402_10V7-K

DOCK_TX1+ DOCK_TX1+_RE

t
DPRE@ CM3 1 2 0.1U_0402_10V7-K
[5] DOCK_TX1+ DP_RE_DP1P 1 2 DISP_A1P_L_C
DPRE@ CM17 0.1U_0402_10V7-K
DISP_A1P_L_C [38]
RM8 1 @ 2 0_0402_5% DOCK_TX1+_R
DOCK_TX1+_R NODPRE@ CM18 1 2 0.1U_0402_10V7-K

n
DOCK_TX1- DPRE@ CM4 1 2 0.1U_0402_10V7-K DOCK_TX1-_RE
[5] DOCK_TX1-
One-Link DP Repeater DP_RE_DP1N DPRE@ CM19 1 2 0.1U_0402_10V7-K DISP_A1N_L_C
DISP_A1N_L_C [38]
RM11 1 @ 2 0_0402_5% DOCK_TX1-_R
DOCK_TX1-_R NODPRE@ CM20 1 2 0.1U_0402_10V7-K
+3VS +3VS_DP

e
DOCK_AUXP DPRE@ CM5 1 2 0.1U_0402_10V7-K DOCK_AUXP_RE RM14 1 2
[5] DOCK_AUXP
0_0603_5% DPRE@ R.Pin2 and R.Pin2 Co-lay
RM13 1 @ 2 0_0402_5% DOCK_AUXP_R

d
DOCK_AUXN DPRE@ CM6 1 2 0.1U_0402_10V7-K DOCK_AUXN_RE
[5] DOCK_AUXN

RM15 1 @ 2 0_0402_5% DOCK_AUXN_R DP_RE_AUXN DPRE@ RM16 1 2 0_0402_5% DOCK_AUXN_CONN

i
DOCK_AUXN_CONN [38]

NODPRE@
DOCK_AUXN_R CM7 1 2 0.1U_0402_10V7-K
Cap.Pin1 and R.Pin1 Co-lay

f
C +3VS_DP C

DP_RE_AUXP DPRE@ RM17 1 2 0_0402_5% DOCK_AUXP_CONN

DOCK_AUXP_CONN [38]
DP1201 DPRE@
1 2

n
+3VS_DP DOCK_AUXP_R CM8 1 2 0.1U_0402_10V7-K
CM11
+3VS_DP 2.2U_0402_6.3V6-K NODPRE@
.01U_0402_16V7-K

DPRE@
DPRE@ 1 UM1
DP1201 Cap.Pin2 and R.Pin2 Co-lay

36

12
15
21
25
32
37
43
1

2
6
CM10
CM9 DPRE@

o V3P31
V3P32

VCORE1
VCORE2
VCORE3
VCORE4
VCORE5
VCORE6
VCORE7
VCORE8
VCORE9
0.1U_0402_10V7-K
2 2 DOCK_TX0+_RE 38 23 DP_RE_DP0P
DOCK_TX0-_RE
DOCK_TX1+_RE
39 IN0P
IN0N
OUT0P
OUT0N
22 DP_RE_DP0N
DP_RE_DP1P
DP AUX : From Repeator don't need cap, but PCH.
41 20
DOCK_TX1-_RE 42 IN1P OUT1P 19 DP_RE_DP1N
44 IN1N OUT1N 17
45 IN2P OUT2P 16
47 IN2N OUT2N 14
48 IN3P OUT3P 13

C
IN3N OUT3N

I2C_ADDR 3 40 PS8330_CFG1
OC_1/I2C_ADDR EQ
RM29 1 DPRE@ 2 0_0402_5% SCL_CTL 4 46 DP1201_OC DP1201 DDC_CALL
[11,25,59,60,66] EC_SMB_CK3 OP_0/SCL_CTL OC_0
[11,25,59,60,66] EC_SMB_DA3 RM30 1 2 0_0402_5% SDA_CTL 5
OP_1SDACTL PS8330_RST
Low --> DDC Disable, AUX Enable
DPRE@ 35
AUTO-EQ High --> DDC Enable, AUX Disable
TP69 1 26 10 DOCK_CAL DPRE@ RM18 1 2
B PS8330_REXT 7 ENABLE CAD_SNK 1M_0402_5% B
CNTRL 11 DOCK_HPD_CONN
HPD_SNK DOCK_HPD_CONN [38]

C
TP70 1 PS8330_CAD 8
CAD_SRC
DOCKDP_HPD 9 28 DP_RE_AUXP
[5,38] DOCKDP_HPD HPD_SRC AUX_SNKP 27 DP_RE_AUXN
AUX_SNKN
33
34 SCL_DDC
SDA_DDC

F
DOCK_AUXP_RE 30
DOCK_AUXN_RE 29 AUX_SRCP
AUX_SRCN

+3VS_DP
GND1
GND2
GND3
PAD

C
18
24
31
49

PI3EQXDP1201ZBEX_TQFN48_7X7
1

1
1

@ @ SA00005RG00
DP1201
DPRE@ @ RM21 @ RM23 RM32 RM34 DPRE@
RM20 4.7K_0402_5% @ RM22 4.7K_0402_5% 4.7K_0402_5% 4.99K_0402_1% RM28
DP1201
10K_0402_1% 4.7K_0402_5% 4.7K_0402_5%
2

L
2

DP1201
PS8330_REXT
DP1201_OC
A PS8330_RST DP1201 DP1201 A
SCL_CTL
SDA_CTL
PS8330_CFG1 I2C_ADDR
2015,01,02
1

1 DP1201
1

@ RM24 @ RM25 @ DPRE@

DP1201
@ DPRE@ 4.7K_0402_5% 4.7K_0402_5% @ RM26 RM33 RM19 @ RM27
Security Classification LC Future Center Secret Data Title
RM31 CM12 4.7K_0402_5% 4.7K_0402_5% 4.99K_0402_1% 4.7K_0402_5%
10K_0402_1% 2 2.2U_0402_6.3V6-K
Issued Date 2013/09/07 Deciphered Date 2014/09/07 DP-DOCKING RP
2

2
2

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 37 of 83
5 4 3 2 1
 5 4 3 2 1

l
+3VALW +5VALW

1
ON/OFF# [54,66]

a
R93 R88
100K_0402_5% 100K_0402_5%
@
D @ D

2
it
For Testing (Cap on Docking ) DC IN CONN. ONEDOCK_DET#
ONEDOCK_DET# [15]
If use docking, need change to 0 ohm
JLINK

2
DISP_A0P_L_C 3 2 ON/OFF# R98
[37] DISP_A0P_L_C DISP_A0N_L_C ML_LANE0_P PWR_BOTTON
[37] DISP_A0N_L_C 5 4 0_0402_5%
ML_LANE0_N RETURN/DETECT 6 F1 1 2 1812L110PR 1.1A
DISP_A1P_L_C VBUS +5VALW @
9
[37] DISP_A1P_L_C

1
DISP_A1N_L_C 11 ML_LANE1_P APDIN
[37] DISP_A1N_L_C ML_LANE1_N 26

n
EMC_NS@ POWER1 28
USB20_P3 R114 1 2 0_0402_5% USB20_P3_OD 8 POWER2
[15] USB20_P3 USB20_N3 USB20_P
R115 1 2 0_0402_5% USB20_N3_OD 10 27 DOCK_ID
[15] USB20_N3 USB20_N DETECT DOCK_ID [69]
EMC_NS@
USB3P4_RXP R116 1 2
EMC_NS@ 0_0402_5% USB3_RX4_P_OD 14
[36] USB3P4_RXP USB3P4_RXN USB3_RX4_N_OD USB30_RX_P
R117 1 2
EMC_NS@ 0_0402_5% 16 1
[36] USB3P4_RXN

e
USB3P4_RE_TXP C86 1 2 0.1U_0402_10V7-K USB3_TX4_P_C R103 1 2
EMC_NS@ 0_0402_5% USB3_TX4_P_OD 20 USB30_RX_N GND1 7
[36] USB3P4_RE_TXP USB3P4_RE_TXN USB30_TX_P GND2 1 1
C85 1 2 0.1U_0402_10V7-K USB3_TX4_N_C R104 1 2 0_0402_5% USB3_TX4_N_OD 22 12 @ @
[36] USB3P4_RE_TXN USB30_TX_N GND3
EMC_NS@ 13 C40 C41
GND4 18 .01U_0402_16V7-K 1U_0402_6.3V6-K
DOCK_AUXP_CONN 15 GND5 24 2 2
[37] DOCK_AUXP_CONN DOCK_AUXN_CONN AUX_CH_P GND6
[37] DOCK_AUXN_CONN 17 25
AUX_CH_N GND7 29
GND8

d
Configer1 19
DOCK_CONSUMP 21 CONFIG1 30
[71] DOCK_CONSUMP DOCK_CONSUMP GND9 31
DOCK_HPD_CONN 23 GND10 32
[37] DOCK_HPD_CONN HOT_PLUG_DET GND11
1

33

if
GND12 34
R105 GND13
1M_0402_5%

DRAPH_PJSS0296-MB21H
2

C C
ME@

L16 EMC@
USB3_TX4_P_C 1 2 USB3_TX4_P_OD
1 2
ESD(Close to connector) EMC@
USB3_TX4_N_C 4 3 USB3_TX4_N_OD D17 RCLAMP0524PATCT_SLP2510P8-10-9

n
4 3
EXC24CH900U_4P
EMC@
Close to connector L15 EMC@ 1
D15
6 USB20_N3_OD +5VALW
USB3_RX4_P_OD
USB3_RX4_N_OD
1
2
9
8
USB3_RX4_P_OD
USB3_RX4_N_OD
USB3P4_RXP 1 2 USB3_RX4_P_OD V_I/O1 V_I/O4 USB3_TX4_P_OD 4 7 USB3_TX4_P_OD
1 2 2 5 USB3_TX4_N_OD 5 6 USB3_TX4_N_OD

o
Ground VBUS
USB3P4_RXN 4 3 USB3_RX4_N_OD 3 4 USB20_P3_OD
4 3 V_I/O2 V_I/O3
+3VS EXC24CH900U_4P CM1293A_SC-74
SC300003N00

3
R106 1 2 100K_0402_5% DOCK_AUXN_CONN
L20 EMC@
R107 1 2 100K_0402_5% DOCK_AUXP_CONN USB20_P3 1 2 USB20_P3_OD
1 2

C
USB20_N3 4 3 USB20_N3_OD EMC@ EMC@
4 3 D16 RCLAMP0524PATCT_SLP2510P8-10-9 D18 RCLAMP0524PATCT_SLP2510P8-10-9
EXC24CH900U_4P
+5VS

DOCK_AUXP_CONN 1 9 DOCK_AUXP_CONN DISP_A0P_L_C 1 9 DISP_A0P_L_C

DOCK_AUXN_CONN 2 8 DOCK_AUXN_CONN DISP_A0N_L_C 2 8 DISP_A0N_L_C
ON/OFF# 4 7 ON/OFF# DISP_A1P_L_C 4 7 DISP_A1P_L_C
DOCK_HPD_CONN 5 6 DOCK_HPD_CONN DISP_A1N_L_C 5 6 DISP_A1N_L_C
B B

Q4
2N7002KW_SOT323-3
2
G

C
SB000019400

3
DOCKDP_HPD 3 1 DOCK_HPD_CONN
[5,37] DOCKDP_HPD
S

NODPRE@

NODPRE@ R83
100K_0402_5%

F
2

L C DP HPD
MCP
Repeater
DPREP@

Current
Protect
NODPRE@
Conn

Security Classification
Issued Date 2013/09/07
LC Future Center Secret Data
Deciphered Date 2014/09/07
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Title

DOCKING/ DCIN CONN

Size Document Number
Custom

Date:
BE460_NM-A551
Wednesday, August 05, 2015 Sheet 38 of 83
Rev
1.0
A

5 4 3 2 1
 A B C D E

+3VS

l
+5VS
1
LDO 1V8 VREF 1V65 LDO 3V3 CA1 CA1 close Pin7
RA1 +1.8V_LDO +1.65V_LDO +3V_LDO 0.1U_0402_10V7-K
1 @ 2 CA2 CA3 CA4 CA5 +5VS_CLASSD
2

a
0_0805_5%

4.7U_0603_10V6-K

4.7U_0603_10V6-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K
1 1 1 1

CA6

CA7

CA8

CA9

CA10
CA11

2.2U_0402_6.3V6-M
1 1

i
2 1 1 1 1 1
2 2 2 2

0.1U_0402_10V7-K

4.7U_0603_10V6-K

0.1U_0402_10V7-K

1U_0402_6.3V6-K

0.1U_0402_10V7-K
1 2 2 2 2 2

t
+3VS

RA28 1 @ 2 0_0402_5% +3VS_VDDO

X5R CAP X5R CAP
1
CA12
Close to Pin13,16 0.1U_0402_10V7-K

n
2 CA12 close Pin2
+3VL
RA30 1 @ 2 0_0805_5%

e
+3VALW
+3V_AVDD_HP RA2 1 @ 2 0_0805_5%
12/3 For PH noise

+3VS
UA1 1
RA3 2 @ 1 0_0805_5%
CA13

d
PCH_HDA_RST# 9 3 1U_0402_6.3V6-K
[9] PCH_HDA_RST# RESET# FILT_1.8V +1.8V_LDO 2
7
VDD_IO 2
+3VS_VDDIO CA13 close Pin24
VDDO_3.3 +3VS_VDDO
PCH_HDA_BCLK 5 18 >120mA(peak current)

i
[9] PCH_HDA_BCLK BIT_CLK DVDD_3.3 +3VS_DVDD
PCH_HDA_SYNC 8 27
[9] PCH_HDA_SYNC SYNC AVDD_3.3 +3V_LDO
29
[9] PCH_HDA_SDIN0
PCH_HDA_SDIN0 RA5 1 2 33_0402_5% PCH_HDA_SDIN0_R 6 CX11852 VREF_1.65V 28
+1.65V_LDO
+5VS_AVDD
+3VS_DVDD +3VS
SDATA_IN AVDD_5V

f
2 PCH_HDA_SDOUT 4 2
[9] PCH_HDA_SDOUT SDATA_OUT 1 2 0_0805_5%
RA4 @
PC_BEEP 10 12 SPK_L2+
[40] PC_BEEP SPKR_MUTE# 39 PC_BEEP LEFT+ 14 SPK_L1- SPK_L2+ [40]
SPKR_MUTE# LEFT- SPK_L1- [40] X5R CAP, Please Close Pin18
JSENSE 38 17 SPK_R2+
[40] JSENSE 37 JSENSE RIGHT+ 15 SPK_R1- SPK_R2+ [40]
1

n
GPIO1/PORTC_R_MIC RIGHT- SPK_R1- [40]
36 35 CA14
DMIC_CLK RA7 1 2 33_0402_5% MIC_CLK_R 40 MUSIC_REQ/GPIO0/PORTC_L_MIC MICBIASC 34 1U_0402_6.3V6-K
[42] DMIC_CLK DMIC_DATA DMIC_CLK/MUSIC_REQ/GPIO0 MICBIASB +MICBIASB 2
1
[42] DMIC_DATA DMIC_DAT/GPIO1 33 PORTB_R
PORTB_R_LINE 32 PORTB_L PORTB_R [40]
1 2 0.1U_0402_10V7-K 11 PORTB_L_LINE PORTB_L [40]
CA16

o
+5VS_CLASSD CLASS-D_REF EXT_MIC_A
30
13 PORTD_A_MIC 31 EXT_MIC_B EXT_MIC_A [40] Apple --> EXT_MIC_A, HGNDB
LPWR_5.0 PORTD_B_MIC EXT_MIC_B [40]
W= 80mils 16
RPWR_5.0 25 HGNDA
Nokia --> EXT_MIC_B, HGNDA +5VS_AVDD +5VS
1 2 1U_0402_6.3V6-K 19 HGNDA 26 HGNDA [40,57]
CA17 HGNDB HGNDA/HGNDB trace widths
20 FLY_P HGNDB HGNDB [40,57] 1 2 0_0805_5%
RA6 @
FLY_N 24 should be as wide as possible
AVDD_HP +3V_AVDD_HP
+AVEE 21
+AVEE AVEE HP_OUTR
CA18 23

C
PORTA_R HP_OUTL HP_OUTR [40] 1
2.2U_0402_6.3V6-M

41 22
HP indicate 1 GND PORTA_L HP_OUTL [40]
CA15
+3VS_VDDO 1U_0402_6.3V6-K
Should be 2
2 connect to CX11852-11Z_QFN40_5X5
GND Please Close Pin28

3 3
1

RA29

C
47K_0402_5%
2

DA5
EC_MUTE# 1 2 SPKR_MUTE#
[66] EC_MUTE#
RB751V-40_SOD323-2
W= 300mils +3VS_VDDIO
SCS00007P00 CA19 1 2 0.1U_0402_10V7-K RA25 1 @ 2 0_0402_5%

F
+3VS
EMC_NS@ RA27 1 @ 2 0_0402_5% +3VS_VDDIO
+3VALW_PCH

1
CA42
4.7U_0603_10V6-K
2
GND GNDA

C
CA42 close Pin7
RF, close to RA7
Close to RA7 (as RC filter)
DMIC_CLK

L
1

EMC@
CA40
150P_0402_50V8-J
2

4 4

DMIC_DATA
1
RF_NS@
CA43
47P_0402_50V8-J Title
2 Security Classification LC Future Center Secret Data
Issued Date 2013/09/07 Deciphered Date 2014/09/07 CX11852 & SPEAKER

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 39 of 83
A B C D E
 5 4 3 2 1

[66]
PC Beep

EC Beep
BEEP#
CA22 1
@
2 0.1U_0402_10V7-K
[39]

[39]

[39]
Speaker OUT

SPK_L1-

SPK_L2+

SPK_R1-
SPK_L1-

SPK_L2+

SPK_R1-
RA8

RA9

RA10 1
1

1
EMC@

EMC@

EMC@
SPK CONN.

2 BLM18PG221SN1D_2P SPK_L1-_CON

2 BLM18PG221SN1D_2P SPK_L2+_CON

2 BLM18PG221SN1D_2P SPK_R1-_CON

it al ME update PN
SPK_L1-_CON
SPK_L2+_CON
SPK_R1-_CON
SPK_R2+_CON
1
2
3
4
JSPK
1
2
3
4
D

n
DA1 EMC@ 5
2 SPK_R2+ RA12 1 2 BLM18PG221SN1D_2P SPK_R2+_CON 6 GND1
[39] SPK_R2+ GND2
CA24
1 1 RA11 2 1 2 PC_BEEP 20150520 TYCO_2041180-4
PC_BEEP [39]
PCH Beep ME@
3 33_0402_5%
0.1U_0402_10V7-K
[9] PCH_BEEP

e
BAT54CW_SOT323-3
CA23 1 2 0.1U_0402_10V7-K
EMC@
@ CA25 1 2 470P_0402_50V7-K SPK_L1-_CON

1
EMC@
CA26 1 2 470P_0402_50V7-K SPK_L2+_CON

d
RA13 EMC@
10K_0402_5% CA27 1 2 470P_0402_50V7-K SPK_R1-_CON
EMC@
2

CA28 1 2 470P_0402_50V7-K SPK_R2+_CON

if
20150520

C C

EXT. MIC/LINE IN Apple --> EXT_MIC_A, HGNDB

Nokia --> EXT_MIC_B, HGNDA

o n +3VS

C
1
RA18
EXT_MIC_A RA14 1 2 100_0402_5% CA29 1 2 2.2U_0402_6.3V6-K HGNDB 5.11K_0402_1%
[39] EXT_MIC_A HGNDB [39,57]

2
EXT_MIC_B RA15 1 2 100_0402_5% CA30 1 2 2.2U_0402_6.3V6-K HGNDA JSENSE RA20 2 1 20K_0402_1% JSENSE_CON
[39] EXT_MIC_B HGNDA [39,57] [39] JSENSE JSENSE_CON [57]
RA21 2 1 39.2K_0402_1%
B B
Changed CA29 & CA30 from 1uF to 2.2uF/X5R
to meet Port-D(headset-Mic) THD+N <= -65 dB

HeadPhone/LINE OUT

[39]

[39]
HP_OUTL

PORTB_L
HP_OUTL

PORTB_L 1 RA19 2
CA31
1 2

F C RA16

RA17
1

1
2 3K_0402_5%

2 75_0402_5%
1
SCS00007P00
RB751V-40_SOD323-2

HP_OUTL_CON
DA3

HP_OUTL_CON
+MICBIASB

[57]

C
100_0402_5%
10U_0603_6.3V6-M
SCS00007P00
RB751V-40_SOD323-2
RA22 1 2 3K_0402_5% 1 2 DA4
+MICBIASB

HP_OUTR RA23 1 2 75_0402_5% HP_OUTR_CON

[39] HP_OUTR HP_OUTR_CON [57]

L
CA32
PORTB_R 1 RA24 2 1 2
[39] PORTB_R
A 100_0402_5% A
10U_0603_6.3V6-M

CA31, CA32 change to 10U for Quality requirement

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 HP/MIC JACK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 40 of 83
5 4 3 2 1
 5 4 3 2 1

i a l D

SATA HDD CONN.

+3VS
Close to JHDD

n t
e
1 1
RF_NS@ RF_NS@
C204 C205
2200P_0402_50V7-K 47P_0402_50V8-J
2 2

Close to JHDD

d
+5VS

i
1 1 1 1 1 1 1
@ @ @ @ RF_NS@ RF_NS@
C19 C20 C21 C22 C23 C202 C203
10U_0805_10V6-K 10U_0805_10V6-K 1U_0402_10V6K 0.1U_0402_10V7-K 1000P_0402_50V7-K 2200P_0402_50V7-K 47P_0402_50V8-J
2 2 2 2 2 2 2

f
C C

JHDD ME@

1
SATA_PTX_DRX_P0 C24 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_P0 2 GND1
[15] SATA_PTX_DRX_P0

n
SATA_PTX_DRX_N0 C25 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_N0 3 A+
[15] SATA_PTX_DRX_N0 A-
4
SATA_PRX_DTX_N0 C26 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_N0 5 GND2
[15] SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 C27 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_P0 6 B-
[15] SATA_PRX_DTX_P0 7 B+
GND3

o
8
+3VS 9 VCC_3V3_1
HDD_DEVSLP0 10 VCC_3V3_2
[15] HDD_DEVSLP0 VCC_3V3_3
11
HDD_DETECT# 12 GND4
[66] HDD_DETECT# 13 GND5
14 GND6
+5VS 15 VCC5_1

C
16 VCC5_2
17 VCC5_3
18 GND7
19 RESERVED
Pin18 connect to GND for SATA Gen3 20 GND8 24
21 VCC12_1 GND10
22 VCC12_2
VCC12_3
23
B GND9 B

C
HIGHS_SA2S0226-3201H

C F
A

5
L
WWW.AliSaler.Com 4
Security Classification
Issued Date 2013/09/07
LC Future Center Secret Data
Deciphered Date 2014/09/07
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3 2
Title

Custom

Date:
SATA HDD/ODD
Size Document Number
BE460_NM-A551
Wednesday, August 05, 2015
1
Sheet 41 of 83
R ev
1.0
A
 5 4 3 2 1

l
CMOS Camera

LCDVDD Circuit For A phase test

a
+3VS +3VS_CMOS

D +3VS +LCDVDD_CON D

it
U3
5 1 +LCDVDD_CON R17 1 @ 2 0_0402_5%
IN OUT
2
1 From PCH GND 1
C9 +3VS +3VS_CMOS
C8 PCH_ENVDD 4 3 4.7U_0603_10V6-K U4 @
[5] PCH_ENVDD EN OC 5 1 +3VS_CMOS
2 1U_0402_6.3V6-K 2 IN OUT

1
G524B1T11U_SOT23-5 1 2 1
GND C11

n
R18 @ @ C10 4 3 @ 4.7U_0603_10V6-K
100K_0402_5% 1U_0402_6.3V6-K [14] PCH_CMOS_ON EN OC
2 2

2
G524B1T11U_SOT23-5

if d e eDP CONN.
C

n
B+
2A 80 mil 2A 80 mil
R24 1 @ 2 0_0805_5% +LEDVDD
1
C12

o
4.7U_0805_25V6-K JLCD ME@
2 +LEDVDD 1
+LEDVDD W= 80 mil 1
2
3 2
RF R21 1 2 100K_0402_5% 4 3
R22 1 @ 2 0_0402_5% +3VDMIC 5 4
+3VS 5
6
+3VS_CMOS +LCDVDD_CON 6
W= 60 mil 7
+LCDVDD_CON +3VALW_LOGO +LCDVDD_CON 7
8

C
R25 1 2 2.2K_0402_1% +3VALW_LOGO 9 8
+3VALW LOGO_LED# 9
10
[53,66] LOGO_LED# BKOFF# 11 10
[66] BKOFF# PCH_EDP_PWM 11
1 1 1 1 12
[5] PCH_EDP_PWM 12
RF@ RF@ RF@ RF@ 13
C178 C179 C181 C180 DMIC_DATA 14 13
[39] DMIC_DATA DMIC_CLK 14
47P_0402_50V8-J 2200P_0402_50V7-K 47P_0402_50V8-J 2200P_0402_50V7-K 15
2 2 2 2 [39] DMIC_CLK 16 15
USB20_N6_CMOS 17 16
B USB20_P6_CMOS 18 17 B
19 18
CPU_EDP_AUX# C17 1 2 0.1U_0402_10V7-K CPU_EDP_AUX#_CON 20 19 31
[5] CPU_EDP_AUX# 20 GND1

C
CPU_EDP_AUX C18 1 2 0.1U_0402_10V7-K CPU_EDP_AUX_CON 21 32
[5] CPU_EDP_AUX CPU_EDP_HPD 22 21 GND2 33
[5] CPU_EDP_HPD 23 22 GND3 34
24 23 GND4 35
CPU_EDP_TX1- C13 1 2 0.1U_0402_10V7-K CPU_EDP_TX1-_CON 25 24 GND5 36
[5] CPU_EDP_TX1- CPU_EDP_TX1+ 1 2 CPU_EDP_TX1+_CON 26 25 GND6 37
C14 0.1U_0402_10V7-K
+3VS_CMOS [5] CPU_EDP_TX1+ 27 26 GND7 38
+LEDVDD
CPU_EDP_TX0- C15 1 2 0.1U_0402_10V7-K CPU_EDP_TX0-_CON 28 27 GND8 39

F
[5] CPU_EDP_TX0- CPU_EDP_TX0+ 1 2 CPU_EDP_TX0+_CON 29 28 GND9 40
C16 0.1U_0402_10V7-K
[5] CPU_EDP_TX0+ 30 29 GND10 41
30 GND11
1 1 1 1
RF@ RF@ RF@ RF@ I-PEX_20525-030E-02
C174 C175 C176 C177
47P_0402_50V8-J 2200P_0402_50V7-K 47P_0402_50V8-J 2200P_0402_50V7-K
2 2 2 2
EMC_NS@
USB20_N6 R19 1 2 0_0402_5% USB20_N6_CMOS BKOFF#

C
[15] USB20_N6
EXC24CH900U_4P
4 3
4 3

1
L5 EMC@
1 2 R26
1 2 100K_0402_5%
USB20_P6 R20 1 2 0_0402_5% USB20_P6_CMOS
[15] USB20_P6

2
EMC_NS@

L
ESD request EMC request , Close to JLCD
+3VALW_LOGO
A +LEDVDD +LCDVDD_CON A
LOGO_LED#
1 1
EMC_NS@ EMC_NS@
3

EMC@ C206 C207

D1 2200P_0402_50V7-K 2200P_0402_50V7-K
2 2
PESD5V0U2BT_SOT23-3
Security Classification LC Future Center Secret Data Title
Issued Date 2013/09/07 Deciphered Date 2014/09/07 eDP/CMOS
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 42 of 83
5 4 3 2 1
 5 4 3 2 1

+3VS

+3VS

USB3.0 Repeator Port 1

l
+3VS
+3VS +3VS
1 1
Close U5
C28 C29

@
@ 0.1U_0402_10V7-K .01U_0402_16V7-K U5 U31@
2 2 1

a
13 VDD1
VDD2
2

2
R36 R35
D AA_EQ1 15 4 BB_EQ1 D

i
4.7K_0402_5% 4.7K_0402_5% A_EQ1_SDA_CTL B_EQ1_I2C_ADDR1
AA_DE0 16 3 BB_DE0
AA_EQ0 17 A_DE0_SCL_CTL B_DE0_I2C_ADDR0 2 BB_EQ0
1

1
U31@ AA_DE1 18 A_EQ0_NC B_EQ0_NC 6 BB_DE1
AA_EQ0 AA_DE0 @ A_DE1_NC B_DE1_NC

t
U31@
+3VS C30 1 2 0.1U_0402_10V7-K USB3_TX1+_REIN 19 12 USB3_TX1+_REOUT
[15] USB3P1_TXP 1 2 0.1U_0402_10V7-K USB3_TX1-_REIN 20 A_INp A_OUTp 11 USB3_TX1-_REOUT USB3_TX1+_REOUT [44]
C32
[15] USB3P1_TXN A_INn A_OUTn USB3_TX1-_REOUT [44]
2

2
U31@
R9461 R9462 U31@
R72 1 2 0_0402_5% USB3P1_RXP_R 9 22 0.1U_0402_10V7-K 2 1 C31
4.7K_0402_5% 4.7K_0402_5% [44] PS8713_RX1_C_P B_INp B_OUTp USB3P1_RXP [15]

2
R74 1 2 0_0402_5% USB3P1_RXN_R 8 23 0.1U_0402_10V7-K 2 1 C33
[44] PS8713_RX1_C_N B_INn B_OUTn USB3P1_RXN [15]

n
@ R38 U31@
1

1
@ 4.7K_0402_5% U31@ U31@
U31@ 1 5
R30 1 2 4.99K_0402_1% TP72 7 PD# 10

1
TEST_1 14 REXT GND1 21
@ 24 TEST GND2 25
I2C_EN GPAD

e
TEST_1
+3VS +3VS PS8713BTQFN24GTR2A_TQFN24_4X4
Normal LFPS mode
Internal PD Co-lay 0-ohm
2

NU3R@

d
R41 R40 USB3P1_TXP R27 1 2 0_0402_5%
USB3P1_TXP_R [44]
4.7K_0402_5% 4.7K_0402_5% +3VS +3VS
USB3P1_TXN R33 1 2 0_0402_5%

i
USB3P1_TXN_R [44]
1

BB_EQ0 U31@ BB_DE0 @

NU3R@

R29 R32 close to U5

2

f
C C
R9463 R9464 NU3R@ NU3R@
AA_EQ1 R39 1 @ 2 4.7K_0402_5% AA_DE1 R37 1 @ 2 4.7K_0402_5% USB3P1_RXP R28 1 2 0_0402_5% PS8713_RX1_P_R R29 1 2 0_0402_5% PS8713_RX1_C_P
4.7K_0402_5% 4.7K_0402_5%
1

@ BB_EQ1 R43 1 @ 2 4.7K_0402_5% BB_DE1 R42 1 @ 2 4.7K_0402_5% USB3P1_RXN R31 1 2 0_0402_5% PS8713_RX1_N_R R32 1 2 0_0402_5% PS8713_RX1_C_N
@

n
EQ Default 9.5dB de-emohasis Default 3.5dB NU3R@ NU3R@

Internal PD Internal PD

+3VS

+3VS

C o +3VS
USB3.0 Repeator Port 2
U32@
+3VS +3VS

2
U6
1
@
1
Close U6 1
13 VDD1
R55 R54
C34 C35 4.7K_0402_5% @ 4.7K_0402_5%
VDD2
@

B 0.1U_0402_10V7-K .01U_0402_16V7-K U32@ B

2 2

1
A_EQ1 15 4 B_EQ1 B_EQ0 B_DE0
A_EQ1_SDA_CTL B_EQ1_I2C_ADDR1

C
A_DE0 16 3 B_DE0 @
A_DE0_SCL_CTL B_DE0_I2C_ADDR0

2
A_EQ0 17 2 B_EQ0
A_DE1 18 A_EQ0_NC B_EQ0_NC 6 B_DE1 R9465 R9466
U32@ A_DE1_NC B_DE1_NC @
4.7K_0402_5% 4.7K_0402_5%
C36 1 2 0.1U_0402_10V7-K USB3_TX2+_REIN 19 12 USB3_TX2+_REOUT
[15] USB3P2_TXP 1 2 0.1U_0402_10V7-K USB3_TX2-_REIN 20 A_INp A_OUTp 11 USB3_TX2-_REOUT USB3_TX2+_REOUT [45]
+3VS C37
[15] USB3P2_TXN USB3_TX2-_REOUT [45]

1
A_INn A_OUTn
U32@ U32@

F
R75 1 U32@ 2 0_0402_5% USB3P2_RXP_R 9 22 C38 2 1 0.1U_0402_10V7-K
[45] PS8713_RX2_C_P 1 2 0_0402_5% USB3P2_RXN_R 8 B_INp B_OUTp 23 2 1 USB3P2_RXP [15]
R76
[45] PS8713_RX2_C_N B_INn B_OUTn USB3P2_RXN [15]
U32@ C39 0.1U_0402_10V7-K
TEST R51 1 @ 2 4.7K_0402_5% U32@ +3VS +3VS
1 5
R45 1 2 4.99K_0402_1% TP73 7 PD# 10
Normal LFPS mode REXT GND1

2
U32@ TEST 14 21 U32@ @
24 TEST GND2 25 R50 R49
Internal PD I2C_EN GPAD
4.7K_0402_5% 4.7K_0402_5%

C
PS8713BTQFN24GTR2A_TQFN24_4X4

1
A_EQ0 A_DE0

2
R9467 R9468
Co-lay 0-ohm 4.7K_0402_5% @ 4.7K_0402_5%
+3VS +3VS

L
R29 R32 close to U5 @

1
NU3R@ NU3R@ NU3R@
USB3P2_TXP R44 1 2 0_0402_5% USB3P2_RXP R34 1 2 0_0402_5% PS8713_RX2_P_R R46 1 2 0_0402_5% PS8713_RX2_C_P
A USB3P2_TXP_R [45] A
A_EQ1 R53 1 @ 2 4.7K_0402_5% A_DE1 R52 1 @ 2 4.7K_0402_5%
USB3P2_TXN R62 1 2 0_0402_5% USB3P2_RXN R47 1 2 0_0402_5% PS8713_RX2_N_R R48 1 2 0_0402_5% PS8713_RX2_C_N
USB3P2_TXN_R [45]
NU3R@ NU3R@ NU3R@
B_EQ1 R57 1 @ 2 4.7K_0402_5% B_DE1 R56 1 @ 2 4.7K_0402_5%

EQ Default 9.5dB de-emohasis Default 3.5dB Security Classification LC Future Center Secret Data Title

Internal PD Internal PD Issued Date 2013/09/07 Deciphered Date 2014/09/07 USB30 RP

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 43 of 83
5 4 3 2 1
 5 4 3 2 1

Broadwell Connector (USB+S&C)

For 14" use(14" on board USB don't support S&C

l
,But 15" on board USB support S&C.S&C IC always on MB)

a
+5VALW

D +USB_VCCA D

it
W=80mils
W=80mils
U15 EMC_NS@ For EMI
5 1 C1181 2 1000P_0402_50V7-K
IN OUT
2
GND
USB_ON# 4 3 USB_OC0#
[66] USB_ON# EN OC USB_OC0# [15]
1

n
G524B2T11U_SOT23-5 @ C120
1000P_0402_50V7-K
2
1
@
C119

e
0.1U_0402_10V7-K
2

d
L9 EMC@ L10 EMC@ L11 EMC@
USB3P1_TXP_C 1 2 USB3P1_TXP_CON PS8713_RX1_C_P 1 2 USB3P1_RXP_CON USB20_P0 1 2 USB20_P0_CON

if
1 2 1 2 [15] USB20_P0 1 2

USB3P1_TXN_C 4 3 USB3P1_TXN_CON PS8713_RX1_C_N 4 3 USB3P1_RXN_CON USB20_N0 4 3 USB20_N0_CON

4 3 4 3 [15] USB20_N0 4 3
C EXC24CH900U_4P EXC24CH900U_4P EXC24CH900U_4P C

[43]

[43]
USB3_TX1+_REOUT

USB3_TX1-_REOUT
USB3_TX1+_REOUT

USB3_TX1-_REOUT
U31@
C121 1

C124 1
2 0.1U_0402_10V7-K

U31@
2 0.1U_0402_10V7-K

o n
USB3P1_TXP_C

USB3P1_TXN_C

USB3P1_TXP_CON
+USB_VCCA

9
1
JUSB1
Stda_SSTX+
ME@
+USB_VCCA

Close JUSB1

C
USB3P1_TXN_CON VBUS 1 1
8
[43] PS8713_RX1_C_N USB20_P0_CON 3 Stda_SSTX- + C123 C127
7 D+ 150U_B2_6.3VM_R35M 470P_0402_50V7-K
USB20_N0_CON 2 GND_DRAIN 10 2
USB3P1_RXP_CON 6 D- GND2 11 2
[43] PS8713_RX1_C_P 4 Stda_SSRX+ GND3 12
USB3P1_RXN_CON 5 GND GND4 13
Stda_SSRX- GND5

B SUYIN_020053GR009M283ZL B

C
Co-lay 0-ohm
NU3R@

C122 1 2 0.1U_0402_10V7-K USB3P1_TXP_C

[43] USB3P1_TXP_R

F
C130 1 2 0.1U_0402_10V7-K USB3P1_TXN_C
[43] USB3P1_TXN_R
NU3R@

C
EMC@
D8 D7 RCLAMP0524PATCT_SLP2510P8-10-9
USB20_P0_CON 1 6 USB20_N0_CON
V_I/O1 V_I/O4 +USB_VCCA
2 5
Ground VBUS USB3P1_TXP_CON 1 9 USB3P1_TXP_CON
3 4 USB3P1_TXN_CON 2 8 USB3P1_TXN_CON
V_I/O2 V_I/O3 USB3P1_RXP_CON 4 7 USB3P1_RXP_CON

L
CM1293A_SC-74 USB3P1_RXN_CON 5 6 USB3P1_RXN_CON
SC300003N00
EMC@
A A

3
Security Classification LC Future Center Secret Data Title
Issued Date 2013/09/07 Deciphered Date 2014/09/07 USB3 PORT1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 44 of 83
5 4 3 2 1
 5 4 3 2 1

i a l D

t
Co-layout L15 for EMI test

n
L14 EMC@
L12 EMC@ L13 EMC@ USB20_P1 1 2 USB20_P1_CON
USB3P2_TXP_C 1 2 USB30_TX_P2_CON PS8713_RX2_C_P 1 2 USB30_RX_P2_CON [15] USB20_P1 1 2
1 2 1 2

e
USB20_N1 4 3 USB20_N1_CON
USB3P2_TXN_C 4 3 USB30_TX_N2_CON PS8713_RX2_C_N 4 3 USB30_RX_N2_CON [15] USB20_N1 4 3
4 3 4 3 EXC24CH900U_4P
EXC24CH900U_4P EXC24CH900U_4P

[43] USB3_TX2+_REOUT
USB3_TX2+_REOUT
U32@
C125 1 2 0.1U_0402_10V7-K USB3P2_TXP_C

f i d C

n
USB3_TX2-_REOUT C126 1 2 0.1U_0402_10V7-K USB3P2_TXN_C
[43] USB3_TX2-_REOUT
U32@ +USB_VCCA

+USB_VCCA
JUSB2 ME@
USB30_TX_P2_CON 9
Close JUSB2

o
[43] PS8713_RX2_C_N 1 Stda_SSTX+
USB30_TX_N2_CON 8 VBUS
USB20_P1_CON Stda_SSTX- 1 1
3
7 D+ + C128 C129
USB20_N1_CON 2 GND_DRAIN 10 150U_B2_6.3VM_R35M 470P_0402_50V7-K
[43] PS8713_RX2_C_P USB30_RX_P2_CON 6 D- GND2 11 2
4 Stda_SSRX+ GND3 12 2
USB30_RX_N2_CON 5 GND GND4 13
Stda_SSRX- GND5

C
SUYIN_020053GR009M283ZL

B B

Co-lay 0-ohm

F C USB20_P1_CON 1

3
D9
V_I/O1 V_I/O4

Ground VBUS

V_I/O2 V_I/O3
6

4
USB20_N1_CON
+USB_VCCA
USB30_TX_P2_CON1
USB30_TX_N2_CON2
USB30_RX_P2_CON4
USB30_RX_N2_CON5
D10
EMC@
RCLAMP0524PATCT_SLP2510P8-10-9

9
8
7
6
USB30_TX_P2_CON
USB30_TX_N2_CON
USB30_RX_P2_CON
USB30_RX_N2_CON

C
CM1293A_SC-74
SC300003N00

3
NU3R@ EMC@

C131 1 2 0.1U_0402_10V7-K USB3P2_TXP_C

[43] USB3P2_TXP_R

C132 1 2 0.1U_0402_10V7-K USB3P2_TXN_C

L
[43] USB3P2_TXN_R
NU3R@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 USB3 PORT2

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015
Sheet
JITR1_LA-4141P 45 of 83
5 4 3 2 1
 A B C D E F G H

it al 1

e n
2

if d 2

o n
3

C 3

F C
4

L C Security Classification
Issued Date 2013/09/07
LC Future Center Secret Data
Deciphered Date 2014/09/07
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Title

XXXX
Size Document Number
Custom
BE460_NM-A551
R ev
1.0
4

Date: Wednesday, August 05, 2015 Sheet 46 of 83

A B C D E F G H
 2 1

i a l
B

n t B

i d e
n f
C o
A

F C A

L C Security Classification
Issued Date 2013/09/07
LC Future Center Secret Data
Deciphered Date 2014/09/07
Title

XXXX

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 47 of 83
2 1
 5 4 3 2 1

it al D

e n
C

if d C

o n
B

C B

F C
A

L C Security Classification
Issued Date 2013/09/07
LC Future Center Secret Data
Deciphered Date 2014/09/07
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Title

XXXX
Size Document Number
Custom
BE460_NM-A551
R ev
1.0
A

Date: Wednesday, August 05, 2015 Sheet 48 of 83

5 4 3 2 1
 5 4 3 2 1

l
H_HDMI_TX0+ CRE1 1 2 0.1U_0402_10V7-K HDMI_TX0+_REIN
[5] H_HDMI_TX0+

HDMI Repeater

a
H_HDMI_TX0- CRE3 1 2 0.1U_0402_10V7-K HDMI_TX0-_REIN
[5] H_HDMI_TX0-

D D

i
H_HDMI_TX1+ CRE5 1 2 0.1U_0402_10V7-K HDMI_TX1+_REIN
[5] H_HDMI_TX1+

[5]

[5]
H_HDMI_TX1-

H_HDMI_TX2+
H_HDMI_TX1-

H_HDMI_TX2+
CRE7

CRE9
1

1
2

2
0.1U_0402_10V7-K

0.1U_0402_10V7-K
HDMI_TX1-_REIN

HDMI_TX2+_REIN

n t
e
For 8407 use
+1.35V
H_HDMI_TX2- CRE11 1 2 0.1U_0402_10V7-K HDMI_TX2-_REIN
[5] H_HDMI_TX2-

C
[5] H_HDMI_TXC+
H_HDMI_TXC+ CRE13 1 2 0.1U_0402_10V7-K HDMI_TXC+_REIN

CRE17

f
CRE18 CRE19

i d
CRE20 CRE21 CRE22
RRE32 1 @ 2 0_0402_5%

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

.01U_0402_16V7-K

.01U_0402_16V7-K
H_HDMI_TXC- HDMI_TXC-_REIN 1 1 1 1 1 1
[5] H_HDMI_TXC- CRE14 1 2 0.1U_0402_10V7-K
+3VS
2 2 2 2 2 2

n
11
37

12
40
20
31
19
URE1

VDD33_1
VDD33_2

VDDRX_1
VDDRX_2
VDDTX_1
VDDTX_2
VDDTA
HDMI_TX0+_REIN 6
HDMI_TX0-_REIN 7 IN_D0p
HDMI_TX1+_REIN 4 IN_D0n

o
HDMI_TX1-_REIN 5 IN_D1p
HDMI_TX2+_REIN 1 IN_D1n
HDMI_TX2-_REIN 2 IN_D2p
HDMI_TXC+_REIN 9 IN_D2n
HDMI_TXC-_REIN 10 IN_CKp
IN_CKn 25 HDMI_TX0+_REOUT
1 36 OUT_D0p 24 HDMI_TX0-_REOUT HDMI_TX0+_REOUT [50]
TP71
PD# OUT_D0n 27 HDMI_TX1+_REOUT HDMI_TX0-_REOUT [50]
8 OUT_D1p 26 HDMI_TX1-_REOUT HDMI_TX1+_REOUT [50]

C
I2C_CTL_EN OUT_D1n 30 HDMI_TX2+_REOUT HDMI_TX1-_REOUT [50]
OUT_D2p 29 HDMI_TX2-_REOUT HDMI_TX2+_REOUT [50]
PS8401_DCIN_EN 13 OUT_D2n 22 HDMI_TXC+_REOUT HDMI_TX2-_REOUT [50]
PS8401_DDCBUF 14 DCIN_EN/SCL_CTL OUT_CKp 21 HDMI_TXC-_REOUT HDMI_TXC+_REOUT [50]
DDCBUF/SDA_CTL OUT_CKn HDMI_TXC-_REOUT [50]
PS8401_ISET 34
ISET

HDMI_CLK 38 32 HDMI_CLK_CON
B [5] HDMI_CLK HDMI_DAT 39 SCL_SRC SCL_SNK 33 HDMI_DAT_CON HDMI_CLK_CON [50] B
[5] HDMI_DAT SDA_SRC SDA_SNK HDMI_DAT_CON [50]

C
PS8401_CFG 23
CFG / I2C_ADDR1 28 HDMI_HPD_CON
HPD_SNK HDMI_HPD_CON [50]
+3VS
PS8401_EQ 17
CRE23 CRE24 +3VS PS8401_PRE 16 EQ/I2C_ADDR0
PRE
0.1U_0402_10V7-K

.01U_0402_16V7-K

HDMI_HPD 3

F
1 1 [5] HDMI_HPD HPD_SRC
GND_PAD

18
2 2 REXT
GND1
GND2
1

RRE20 PS8407ATQFN40GTR2A4_TQFN40_5X5
15
35
41

4.99K_0402_1%
+3VS

C
2
1

@ RRE22 @ RRE23 @ RRE24

RRE21 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5%
4.7K_0402_5%

L
2

+3VS PS8401_ISET

PS8401_EQ

A RRE25 2 1 PS8401_CFG PS8401_PRE A

4.7K_0402_5%
PS8401_DDCBUF
@
RRE26 2 1 PS8401_DCIN_EN
1

4.7K_0402_5% @
RRE27 @ RRE28 @ RRE29 @ RRE30
4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% Title
Security Classification LC Future Center Secret Data
By Pass Mode
Issued Date 2013/09/07 Deciphered Date 2014/09/07 HDMI RP
2

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 49 of 83
5 4 3 2 1
 5 4 3 2 1

+5VS +5VS_HDMI_F +5VS_HDMI

l
D24
2 F2
1 1 2
3
RB491D_SOT23-3 0.5A_8V_KMC3S050RY

a
AO3401A_SOT23-3

@ 1 3 Q22

S
D D

it
20121215

G
2
[65] SUSP

L1 EMC@
1 2 HDMI_TX0+_CON
[49] HDMI_TX0+_REOUT 1 2

n
4 3 HDMI_TX0-_CON
[49] HDMI_TX0-_REOUT 4 3
EXC24CH900U_4P
+5VS_HDMI

e
L2 EMC@
1 2 HDMI_TX1+_CON
[49] HDMI_TX1+_REOUT 1 2

1
d
4 3 HDMI_TX1-_CON
[49] HDMI_TX1-_REOUT 4 3 R4 R5 HDMI CONN.
EXC24CH900U_4P 2.2K_0402_5% 2.2K_0402_5%
JHDMI ME@

if
2

2
HDMI_HPD_CON 19
[49] HDMI_HPD_CON 18 HP_DET
+5VS_HDMI +5V
17
L3 EMC@ HDMI_DAT_CON 16 DDC/CEC_GND
C HDMI_TX2+_CON [49] HDMI_DAT_CON HDMI_CLK_CON SDA C
1 2 15
[49] HDMI_TX2+_REOUT 1 2 [49] HDMI_CLK_CON SCL
14
13 Reserved
4 3 HDMI_TX2-_CON HDMI_TXC-_CON 12 CEC 20
[49] HDMI_TX2-_REOUT 4 3 CK- GND1
11 21
EXC24CH900U_4P HDMI_TXC+_CON 10 CK_shield GND2 22
HDMI_TX0-_CON 9 CK+ GND3 23

n
8 D0- GND4
HDMI_TX0+_CON 7 D0_shield
L4 EMC@ HDMI_TX1-_CON 6 D0+
1 2 HDMI_TXC+_CON 5 D1-
[49] HDMI_TXC+_REOUT 1 2 HDMI_TX1+_CON D1_shield
4
HDMI_TX2-_CON 3 D1+
4 3 HDMI_TXC-_CON 2 D2-

o
[49] HDMI_TXC-_REOUT 4 3 HDMI_TX2+_CON D2_shield
1
EXC24CH900U_4P D2+
CONCR_099ATAC19NBLCNF

C B

C
For ESD
EMC@ EMC@ EMC@
D2 RCLAMP0524PATCT_SLP2510P8-10-9 D3 RCLAMP0524PATCT_SLP2510P8-10-9 D11 RCLAMP0524PATCT_SLP2510P8-10-9

F
+5VS_HDMI 1 9 +5VS_HDMI HDMI_TX0+_CON 1 9 HDMI_TX0+_CON HDMI_TX1-_CON 1 9 HDMI_TX1-_CON
HDMI_HPD_CON 2 8 HDMI_HPD_CON HDMI_TX0-_CON 2 8 HDMI_TX0-_CON HDMI_TX1+_CON 2 8 HDMI_TX1+_CON
HDMI_CLK_CON 4 7 HDMI_CLK_CON HDMI_TXC+_CON 4 7 HDMI_TXC+_CON HDMI_TX2-_CON 4 7 HDMI_TX2-_CON
HDMI_DAT_CON 5 6 HDMI_DAT_CON HDMI_TXC-_CON 5 6 HDMI_TXC-_CON HDMI_TX2+_CON 5 6 HDMI_TX2+_CON

C
3

3
A

5
L 4
Security Classification
Issued Date 2013/09/07
LC Future Center Secret Data
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
2014/09/07

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3 2
Title

Custom

Date:
HDMI CONN.
Size Document Number
BE460_NM-A551
Wednesday, August 05, 2015
1
Sheet 50 of 83
R ev
1.0
A
 5 4 3 2 1

2014/12/12
+3VALW 2014/12/12 +3VALW_LAN VPRO SKU :
For Non-Vpro

l
@
RL1 1 2 0_0603_5% +5VALW +3VALW +3VALW_LAN

40 mils 40 mils

1
3 1

D
a
RL22 VPRO@ QL2 VPRO@
47K_0402_5% AO3413_SOT23-3

G
2
RL24 VPRO@

2
D LAN_PWRON# 1 2 D

i
1

1
D
RL25 10K_0402_5%
LAN_PWRON 1 VPRO@ 2 LAN_PWRON_R 2 QL3 VPRO@ CL17 VPRO@
[66] LAN_PWRON

t
G 2N7002WT1G_1N_SC-70-3 .01U_0402_16V7-K

1
0_0402_5% S 2

3
RL23 VPRO@
SB000019400
100K_0402_5%

2
[10]
[12,56,57,60,66]
CLKREQ_PCIE3_LAN#
PLTRST_FAR#
CLKREQ_PCIE3_LAN#
PLTRST_FAR#
48
36
UL1

CLK_REQ_N
PE_RST_N

e
MDI_PLUS[0]
MDI_MINUS[0]
13
14
MDI_0+
MDI_0-

n MDI_0+
MDI_0-
[52]
[52]

d
CLK_PCIE_LAN 44 17 MDI_1+
[10] CLK_PCIE_LAN CLK_PCIE_LAN# 45 PE_CLKP MDI_PLUS[1] 18 MDI_1- MDI_1+ [52]
[10] CLK_PCIE_LAN# PE_CLKN MDI_MINUS[1] MDI_1- [52]

PCIE
MDI
PCIE4_CRX_DTX_P CL1 1 2 0.1U_0402_10V7-K PCIE4_CRX_DTX_P_C 38 20 MDI_2+

i
[15] PCIE4_CRX_DTX_P PCIE4_CRX_DTX_N PCIE4_CRX_DTX_N_C PETp MDI_PLUS[2] MDI_2- MDI_2+ [52]
CL2 1 2 0.1U_0402_10V7-K 39 21
[15] PCIE4_CRX_DTX_N PETn MDI_MINUS[2] MDI_2- [52]
PCIE4_CTX_C_DRX_P 41 23 MDI_3+
[15] PCIE4_CTX_C_DRX_P PCIE4_CTX_C_DRX_N 42 PERp MDI_PLUS[3] 24 MDI_3- MDI_3+ [52]
[15] PCIE4_CTX_C_DRX_N PERn MDI_MINUS[3] MDI_3- [52] +3VALW_LAN

f
C C

PCH_SML0_CLK 28 6
[11] PCH_SML0_CLK PCH_SML0_DAT 31 SMB_CLK SVR_EN_N

SMBUS
[11] PCH_SML0_DAT SMB_DATA 1 1 2
RSVD1_VCC3P3 RL4 4.7K_0402_5%
RL18 1 @ 2 0_0402_5% LAN_WAKE#_R 2 5

n
[66] LAN_WAKE# LANWAKE_N VDD3P3_IN
RL26 1 2 0_0402_5% LANPHYPC 3
20150304 [12,66] PCH_SLP_LAN#
@ LAN_DISABLE_N 4
VDD3P3_4
15 1 2 CL3
RJ45_LINKUP# 26 VDD3P3_15 19
[52] RJ45_LINKUP# RJ45_ACTIVITY# 27 LED0 VDD3P3_19 29
[52] RJ45_ACTIVITY# 25 LED1 VDD3P3_29 1U_0402_6.3V6-K

o
LED
LED2
47 VCC0R9GBE
VDD0P9_47 46
+3VALW_LAN 1 32 VDD0P9_46 37
T23 1 34 JTAG_TDI VDD0P9_37
1 2 10K_0402_5% T24 33 JTAG_TDO 43
RL5

JTAG
1 RL6 2 10K_0402_5% 35 JTAG_TMS VDD0P9_43
JTAG_TCK 11
VDD0P9_11

C
LAN_XTALO 9 40
LAN_XTALI 10 XTAL_OUT VDD0P9_40 22
XTAL_IN VDD0P9_22 16
VDD0P9_16 8
2015/06/30 30 VDD0P9_8
TEST_EN
12 7 VCC0R9GBE_L LL1 1 2 4.7UH_FLF3215T-4R7M_20% CL4 CL5 CL6 VCC0R9GBE
SJ10000MW00 RBIAS CTRL0P9
LAN_XTALO 49
GND
1

0.1U_0402_10V7-K

0.1U_0402_10V7-K

22U_0805_6.3V6M
B B
RL7 RL8 WGI219LM-QREF-A0_QFN48_6X6 1 @1 2
LAN_XTALI
YL1 25MHZ_10PF_8Y25000010 1K_0402_5% 3.01K_0402_1%

C
SA000072Z10 Close to FL1
2

2
1 3 2 2 1
1 3
GND1 GND2
UL1 GBE PHY
1 2 4 1
CL7
15P_0402_50V8-J CL8 vPro Model Non-vPro Model

F
15P_0402_50V8-J
2 2

WGI219LM WGI219V

SA000073000 SA000072Z10
SA000072Z20

L C +3VALW_LAN

ST-1_SWG_SDV-SWG_EC062
Add vPro/Non-vPro table.
1

RL9
10K_0402_5%
A A
2

LANPHYPC
[12] LANPHYPC

Security Classification LC Future Center Secret Data Title

When use Native function, intel recommend pull high 10K ohm
This part is un-mount in Sting.
Issued Date 2013/09/07 Deciphered Date 2014/09/07 GBE LAN PHY

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 51 of 83
5 4 3 2 1
 5 4 3 2 1

TL1 EMC@
MDI_0+ 1 1:1
[51] MDI_0+ TD1+ T1/B 24 RJ45_TXD0P
TX1+

l
MDI_0- 2
[51] MDI_0- TD1-
23 RJ45_TXD0N
TX1-
3 22 MCT1 RL10 2 1 75_0805_5% RJ45_GND

a
TDCT1 T1/A TXCT1

4 21 MCT2 RL11 2 1 75_0805_5%

D MDI_1+ TDCT2 1:1 TXCT2 D
5

it
[51] MDI_1+ TD2+ T1/B RJ45_TXD1P
20
TX2+

MDI_1- 6
[51] MDI_1- TD2- 19 RJ45_TXD1N
TX2-

T1/A

n
MDI_2+ 1:1
7
[51] MDI_2+ TD3+ T1/B
18 RJ45_TXD2P
TX3+

MDI_2- 8
[51] MDI_2- TD3-

e
17 RJ45_TXD2N
TX3-
9 16 MCT3 RL12 2 1 75_0805_5%
TDCT3 T1/A TXCT3

10 15 MCT4 RL13 2 1 75_0805_5%

MDI_3+ TDCT4 1:1 TXCT4
11

d
[51] MDI_3+ TD4+ T1/B RJ45_TXD3P
14
TX4+
1U_0402_10V6K

1 1 EMC_NS@
CL13

CL9 PATTERN MUST BE DL3

if
0.1U_0402_10V7-K MDI_3- 12 MCT1 2 1
2 2 [51] MDI_3- TD4- 13 RJ45_TXD3N SHORT AND WIDE. 2 1
TX4-
BS401N_1206-2
C T1/A EMC_NS@ C

CL9 close to LAN Chip DL4

BOTHHAND-NA69LF MCT2 2 1
2 1

BS401N_1206-2
EMC_NS@

n
DL5
MCT3 2 1
2 1

BS401N_1206-2
EMC_NS@
DL6

o
MCT4 2 1
EMC@ EMC@ 2 1

DL1 RCLAMP0524PATCT_SLP2510P8-10-9 DL2 RCLAMP0524PATCT_SLP2510P8-10-9 BS401N_1206-2

RJ-45 Conn.
MDI_0+ 9 1 MDI_0+ MDI_2+ 9 1 MDI_2+ JRJ451 ME@ LANGND
MDI_0- 8 2 MDI_0- MDI_2- 8 2 MDI_2- RL16 1 2 510_0402_1% GREEN_LED 9

C
MDI_1+ MDI_1+ MDI_3+ MDI_3+ +3VALW_LAN Green_LED+
7 4 7 4
MDI_1- 6 5 MDI_1- MDI_3- 6 5 MDI_3- RJ45_LINKUP# 10
[51] RJ45_LINKUP# Green_LED-
RJ45_TXD0P 1
PR1+
RJ45_TXD0N 2
PR1-
3

RJ45_TXD1P 3
PR2+
B RJ45_TXD2P 4 B
PR3+
RJ45_TXD2N 5
PR3-

C
RJ45_TXD1N 6
PR2- 13
RJ45_TXD3P 7 G1 14
PR4+ G2 15
RJ45_TXD3N 8 G3 16
PR4- G4
RL15 1 2 510_0402_1% YELLOW_LED 11

F
+3VALW_LAN Yellow_LED+
RJ45_ACTIVITY# 12
[51] RJ45_ACTIVITY# Yellow_LED-
SINGA_2RJ3089-108211F

EMC@

C
RJ45_GND CL10 1 2 1000P_1808_3KV7k~D
1 1
EMC_NS@ CL11 EMC@ CL12
0.1U_0402_10V7-K .01U_0402_16V7-K
2 2

L
LANGND

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 RJ45 CONN.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 52 of 83
5 4 3 2 1
 5 4 3 2 1

Click Pad +5VS

Track point

a l
1
D R58 D

i
@ 0_0603_5%
JCP ME@ +5VS +3VS

2
t
12
PM_SMB_CLK 11 12 14 R60 4.7K_0402_5%
[11,21,22,23] PM_SMB_CLK 11 GND2
10 1 2
TP_DATA2 9 10 13 ME@
TP_CLK2 8 9 GND1 JTP
PM_SMB_DAT 7 8 TP_DATA2 1
[11,21,22,23] PM_SMB_DAT 7

n
6 R59 1 @ 2 TP_RESET 2 1
CP_RESET# 5 6 3 2
[14,66] CP_RESET# CP_CLK 4 5 4 3
4.7K_0402_5%
[66] CP_CLK CP_DATA 3 4 5 4
[66] CP_DATA TP_REST 2 3 TP_CLK2 6 5
[14,66] TP_REST BYPASS_PAD 1 2 7 6
1 7

e
1 1 8
8
2
ACES_50506-01201-AT1 9
R61 C44 @ @ C45 10 9
4.7K_0402_5% @ 100P_0402_50V8J 100P_0402_50V8J 11 10 13
2 2 12 11 GND1 14
12 GND2
1

d
JAE_FL10F012HA1R3000

+5VS

R63

R65

R67
1

1
2

2
4.7K_0402_5%

4.7K_0402_5%

100K_0402_5%
TP_CLK2

TP_DATA2

CP_RESET#
TP_REST R64

R66
1

1
@

@
2

2
0_0402_5%

0_0402_5%
TP_RESET

BYPASS_PAD

n f i C

o
R108
1 @ 2
[14,66] CP_BYPASS
0_0402_5%

C B

F C +3VALW

R84 1
[42,66]
2 2.2K_0402_1%
LOGO_LED#
C_COVER_LOGO
LOGO_LED#
Only for Edge 14"

1
2

3
JLOGO
1
2

C
4 GND1
GND2
TE_2041180-2
ME@

WWW.AliSaler.Com 5
L 4
Security Classification
Issued Date 2013/09/07
LC Future Center Secret Data
Deciphered Date 2014/09/07
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3 2
Title

Custom

Date:
CP/TPOINTCONN.
Size Document Number
BE460_NM-A551
Wednesday, August 05, 2015
1
Sheet 53 of 83
R ev
1.0
A
 5 4 3 2 1

FAN CONN.
it al D

+5VS R68 1
@
2 0_0603_5%
40mil
+VCC_FAN1 PWR BTN/LID SW CONN.

e n
d
For 14" on board
For 15" on Sub/B

if
JFAN ME@
5 7
[66] EC_FAN_PWM 4 5 G2 6
3 4 G1
C [66] EC_FAN_SPEED 2 3 ON/OFF switch C
1 2
[66] FAN_ID 1
DRAPH_WS32050-S0471-HF SW1 +3VL
1 3

2 4

1
Power Button
TOP Side NTC010-AK1G-B160T_4P
R71
100K_0402_5%

2
ON/OFF# LID_SW#
J1

o
2

3
Bottom Side 1 2 ON/OFF#
ON/OFF# [38,66]
SHORT PADS
PJSOT24C_SOT23-3 @
D5
EMC_NS@

1
B

C Lid Switch
B

[15]
[15]
FingerPrint CONN.

USB20_P8
USB20_N8
USB20_P8
USB20_N8
+3VS

R70 1 @
0_0402_5%
2

F C
+3VS_FP
8
7

6
5
4
3
ME@

ACES_88514-0060N-071
GND2
GND1

6
5
4
C53
+3VL

1
@
2

1
U8
VDD

OUTPUT

GND
3 LID_SW#
LID_SW# [55,66]

C
3
3

1 2 0.1U_0402_10V7-K AH9246-W-7_SC59-3
EMC_NS@ 1 2 2
3

D4 C52 1
AZC199-02SPR7G_SOT23-3 0.1U_0402_10V7-K JFPB
2
1
1

5
L 4
Security Classification
Issued Date 2013/09/07
LC Future Center Secret Data
Deciphered Date 2014/09/07
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3 2
Title

Custom

Date:
PBTN/LID/FP/FAN CONN.

Size Document Number

BE460_NM-A551
Wednesday, August 05, 2015
1
Sheet 54 of 83
R ev
1.0
A
 5 4 3 2 1

D
[66]

[66]
KSI[0..7]

KSO[0..17]
KSI[0..7]

KSO[0..17]

i a l D

Key Board Signal From EC

KeyBoard CONN.(14")
Touch Panel CONN. For 14"

n t
KSI1
KSI7
KSI6
KSO9
KSI4
1
2
3
4
5
JKB

1
2
3
4
5
ME@

i d e +3VS +3VS

1
KSI5 6 TS@
KSO0 7 6 LID_SW# R113
RTC CONN KSI2 8 7
8
[54,66] LID_SW#
100K_0402_5%

f
C KSI3 9 TS@ C
KSO5 10 9 SCS00006V00
SCS00006V00 TS@ JTOUCH1 ME@

2
KSO1 11 10 D25 RB521CS-30GT2RA_VMN2-2 1
ME@ KSI0 12 11 RB521CS-30GT2RA_VMN2-2 D22 1 2 TS_OFF# 2 1
R112 KSO2 13 12 PCH_TSOFF# 1 2 3 2
D6 JRTC
1 2 1 2 1 KSO4 14 13 [14] PCH_TSOFF# USB20_N4_TPANEL R269 1 2 USB20_N4_TPANEL_C 4 3
+RTCBATT @ 0_0402_5%
2 1 KSO7 15 14 [15] USB20_N4_TPANEL USB20_P4_TPANEL R270 1 2 USB20_P4_TPANEL_C 5 4
@ 0_0402_5%

n
2 16 15 [15] USB20_P4_TPANEL 6 5
RB751V-40_SOD323-2 1K_0603_5% KSO8
3 KSO6 17 16 7 6
SCS00007P00 4 GND1 KSO3 18 17 8 7
GND2 KSO12 19 18 9 8
TE_2041180-2 KSO13 20 19 10 9
KSO14 21 20 10
21 1 1
KSO11 22 @ 11

o
KSO10 23 22 @ C115 C116 12 GND1
KSO15 24 23 0.1U_0402_10V7-K 0.1U_0402_10V7-K GND2
R111 1 2 300_0402_5% 25 24 2 2 ACES_50463-0104A-P01
+3VS FN_LED# 25
26
[14] FN_LED# F1_LED# 27 26
[14] F1_LED# F4_LED# 28 27
[14] F4_LED# KB_FN 29 28
[66] KB_FN 30 29
KSO16 31 30 33

C
KSO17 32 31 GND1 34 L19 EMC_NS@
32 GND2 USB20_P4_TPANEL 1 2 USB20_P4_TPANEL_C
1 2
JAE_FL10F032HA2R3000
USB20_N4_TPANEL 4 3 USB20_N4_TPANEL_C
4 3
EXC24CH900U_4P

B B

F C
A

L C Security Classification
Issued Date 2013/09/07
LC Future Center Secret Data
Deciphered Date 2014/09/07
Title

KB/RTC/TOUCH PAN CONN.

A

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 55 of 83
5 4 3 2 1
 TYPE-A NGFF CCARD FOR WLAN
3.2H CONNECTOR
+3V_WLAN

it al
n
+3V_WLAN

@ JWLBT ME@
R95 1 2 0_0805_5% +3V_WLAN 1 2
+3VALW USB20_P5 GND1 3.3VAUX1
3 4 1
[15] USB20_P5 USB20_N5 5 USB_D+ 3.3VAUX2 6 C67
[15] USB20_N5 USB_D- LED#1

e
R94 1 @ 2 0_0805_5% 7
+3VS GND2 NC 8
10U_0603_6.3V6-M
RF 9
11
NC
NC
NC
NC
10
12 @
2
13 NC NC 14
15 16
+3V_WLAN NC LED#2
17 18
19 MLDIR_SENSE GND16 20 1 R150 2 0_0402_5% BT_ON

d
21 DP_ML3N DP_AUXN 22 @
23 DP_ML3P DP_AUXP 24
25 GND3 GND13 26 1 R151 2 0_0402_5% EC_TX_R
1 1 DP_ML2N DP_ML1N
RF@ RF@ 27 28 @

if
C182 C183 29 DP_ML2P DP_ML1P 30
47P_0402_50V8-J 2200P_0402_50V7-K 31 GND4 GND14 32
2 2 33 DP_HPD DP_ML0N 34
PCIE3_CTX_C_DRX_P 35 GND5 DP_ML0P 36
[15] PCIE3_CTX_C_DRX_P PCIE3_CTX_C_DRX_N 37 PETP0 GND15 38 CL_RST_WLAN#
[15] PCIE3_CTX_C_DRX_N 39 PETN0 RESERVED1 40 CL_DATA_WLAN CL_RST_WLAN# [11]
PCIE3_CRX_DTX_P 41 GND6 RESERVED2 42 CL_CLK_WLAN CL_DATA_WLAN [11]
[15] PCIE3_CRX_DTX_P PCIE3_CRX_DTX_N 43 PERP0 RESERVED3 44 CL_CLK_WLAN [11]
[15] PCIE3_CRX_DTX_N 45 PERN0 COEX3 46
CLK_PCIE_WLAN 47 GND7 COEX2 48
[10] CLK_PCIE_WLAN CLK_PCIE_WLAN# 49 REFCLKP0 COEX1 50 SUSCLK_32K

n
[10] CLK_PCIE_WLAN# 51 REFCLKN0 SUSCLK 52 PLTRST_FAR# SUSCLK_32K [10]
CLKREQ_PCIE2_WLAN# 53 GND8 PERST0# 54 BT_ON_R PLTRST_FAR# [12,51,57,60,66]
Close to Conn. [10] CLKREQ_PCIE2_WLAN# 55 CLKREQ0# RESERVED/W_DISABLE#2 56 RF_OFF#
RF_OFF# [14]
57 PEWAKE0# W_DISABLE#1 58
59 GND9 I2C_DATA 60 R90 1 2 100_0402_1%
PETP1 I2C_CLK EC_RX [66]
61 62
63 PETN1 I2C_ALERT# 64 EC_TX_R R89 1 2 100_0402_1%

o
EC_WLAN_WAKE# 65 GND10 RESERVED4 66 EC_TX [66]
[66] EC_WLAN_WAKE# 67 PERP1 PERST1# 68
PERN1 CLKREQ1#

1
69 70
71 GND11 PEWAKE1# 72 R91
73 REFCLKP1 3.3VAUX4 74
REFCLKN1 3.3VAUX5 100K_0402_5%
75 BT_ON_R 2 1
GND12 BT_ON [14]
R239 1K_0402_5%

2
76 77
PEG1 PEG2

C
TE_2199230-8
+5VALW +3VALW +3V_WLAN
1

3 1
S

R9450
47K_0402_5% Q27
G
2

R9451 AO3413_SOT23-3
2

WLAN_PWRON# 1 2

10K_0402_5%
SB93413000J
1
1

C
D
R9449
WLAN_PWRON 1 @ 2 WLAN_PWRON_R 2 Q26 C75
[66] WLAN_PWRON G 2N7002WT1G_1N_SC-70-3 .01U_0402_16V7-K
1

0_0402_5% 2
S SB000019400
3

R69
100K_0402_5%

F
2

L C Security Classification
Issued Date 2013/09/07
LC Future Center Secret Data
Deciphered Date 2014/09/07
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Title

Custom

Date:
WWAN/WLAN NGFF CONN.

Size Document Number

BE460_NM-A551
Wednesday, August 05, 2015 Sheet 56 of 83
R ev
1.0
 5 4 3 2 1

For 14"

l
CardReader Board : FFC

a
JCR ME@
D PCIE6_CRX_DTX_N 1 D

i
[15] PCIE6_CRX_DTX_N PCIE6_CRX_DTX_P 2 1
[15] PCIE6_CRX_DTX_P 3 2
PCIE6_CTX_C_DRX_N 4 3
[15] PCIE6_CTX_C_DRX_N PCIE6_CTX_C_DRX_P 4

t
5
[15] PCIE6_CTX_C_DRX_P 6 5
CLK_PCIE_CR# 7 6
[10] CLK_PCIE_CR# CLK_PCIE_CR 8 7
[10] CLK_PCIE_CR 9 8
PLTRST_FAR# 10 9
[12,51,56,60,66] PLTRST_FAR# CLKREQ_PCIE5_CR# 11 10
[10] CLKREQ_PCIE5_CR#

n
12 11
+3VS 12
13
14 13
14

15
GND1

e
16
For 14" S&C IC on MB) S&C port on SUB/B GND2
ACES_51530-01401-W01

+5VALW

d
+5V_ALW

i
L17 EMC@
USB3P3_RXP 1 2 USB3P3_RXP_C
[15] USB3P3_RXP 1 2
@

f
C USB3P3_RXN 4 3 USB3P3_RXN_C C
C68 [15] USB3P3_RXN 4 3
2 1 U14 EXC24CH900U_4P
1 12
0.1U_0402_10V7-K IN OUT 10 USB20_P2_C
USB20_P2 3 DP_IN 11 USB20_N2_C L18 EMC@
[15] USB20_P2 USB20_N2 2 DP_OUT DM_IN 14 USB3P3_TXP 1 2 USB3P3_TXP_C

n
[15] USB20_N2 DM_OUT GND [15] USB3P3_TXP 1 2

9 AOU_IFG# USB3P3_TXN 4 3 USB3P3_TXN_C

STATUS# AOU_IFG# [66] [15] USB3P3_TXN 4 3
4 EXC24CH900U_4P
USB_OC1# 13 ILIM_SEL
[15] USB_OC1# AOU_EN 5 FAULT# @

o
[66] AOU_EN EN 15 R1181 2 20K_0402_1%
AOU_CTL1 6 ILIM_LO 16 R1201 2 20K_0402_1%
[66] AOU_CTL1 CLT1 ILIM_HI
7
AOU_CTL3 8 CLT2 17
Max Current 2.5A
[66] AOU_CTL3 CLT3 GND_Pad +3VS +5V_ALW
TPS2546RTER_QFN16_4X4
ME@
JU3AC
EMC_NS@ 1

C
USB20_P2_C R121 1 2 0_0402_5% USB20_P2_CONN 2 1
USB20_N2_C R122 1EMC_NS@ 2 0_0402_5% USB20_N2_CONN 3 2
4 3
USB3P3_TXN_C 5 4
USB3P3_TXP_C 6 5
7 6
USB3P3_RXN_C 8 7
USB3P3_RXP_C 9 8
10 9
B 11 10 B
12 11
TI TPS2546 13 12
13

C
14
15 14
CLT1 CLT2 CLT3 ILIM_SEL MOD 16 15
17 16
18 17
0 0 0 X 19 18
DCH OUT held low
19
HGNDB 20
HGNDA/HGNDB trace widths [39,40] HGNDB 21 20

F
1 1 1 1 CDP Data Connected and Port Power Mgt. Function Active should be as wide as possible HGNDA 22 21
* USB_OC5# to MCP [39,40] HGNDA
JSENSE_CON
23 22
23
24
* 1 1 1 0 SDP2 Data Connected AOU_EN to EC [40]
[40]
JSENSE_CON
HP_OUTR_CON
HP_OUTR_CON
HP_OUTL_CON
25
26
24
25
AOU_CTL1 to EC [40] HP_OUTL_CON 27 26
* 1 1 0 X SDP1 Data Connected
AOU_CTL3 to EC
28 GND1
GND2

C
* 0 1 0 X SDP1 Data Connected AOU_IFG# to EC HIGHS_FC5AF261-1151H

1 0 0 X
GNDA
DCP_Short Device Forced to stay in DCP BC 1.2 charging mode

1 0 1 X DCP_Divider Device Forced to stay in DCP Divider 1 Charging Mode L6 EMC@

USB20_N2_C 1 2 USB20_N2_CONN

L
1 2
0 1 1 X DCP_Auto Data Disconnected and Port Power Mgt. Function Active
* USB20_P2_C 4
4 3
3 USB20_P2_CONN

A 0 0 1 X A
DCP_Auto Data Disconnected and Power Wake Function Active EXC24CH900U_4P

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 SUB CONN.

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 57 of 83
5 4 3 2 1
 5 4 3 2 1

it al D

e n
C

if d C

o n
B

C B

F C
A

L C Security Classification
Issued Date 2013/09/07
LC Future Center Secret Data
Deciphered Date 2014/09/07
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Title

XXXX
Size Document Number
Custom
BE460_NM-A551
R ev
1.0
A

Date: Wednesday, August 05, 2015 Sheet 58 of 83

5 4 3 2 1
 i a l
n t
Thermal Sensor
Thermal Sensor
placed near by VRAM

i d e
f
U1
+3VS

1 10 EC_SMB_CK3
VDD SMCLK EC_SMB_CK3 [11,25,37,60,66]

n
REMOTE1+ 2 9 EC_SMB_DA3
DP1 SMDATA EC_SMB_DA3 [11,25,37,60,66]
1
REMOTE1- 3 8
C1 DN1 ALERT#
0.1U_0402_10V7-K REMOTE2+ 4 7 R3 1 @ 2 10K_0402_5%
2 DP2/DN3 THERM# +3VS
REMOTE2- 5 6

o
DN2/DP3 GND

F75303M_MSOP10

Close to U1

1
REMOTE1+

1
REMOTE2+
Under VRAM

REMOTE1+

C 1

1
Close to +VCC_CORE

REMOTE2+
1
REMOTE2+/-:
Trace width/space:10/10 mil
Trace length:<8"

1
C
C C
C2 C3 C4 @ 2 Q1 C5 @ 2 Q2
2200P_0402_50V7-K 2200P_0402_50V7-K 100P_0402_50V8-J B MMST3904-7-F_SOT323-3 100P_0402_50V8-J B MMST3904-7-F_SOT323-3
2 2 2 E SB000010U00 2 E SB000010U00

3
REMOTE1- REMOTE2-
REMOTE1- REMOTE2-

C F
L
WWW.AliSaler.Com
Security Classification
Issued Date 2013/09/07
LC Future Center Secret Data
Deciphered Date 2014/09/07
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Title

Custom

Date:
THERMAL SENSOR
Size Document Number
BE460_NM-A551
Wednesday, August 05, 2015 Sheet 59 of 83
R ev
1.0
 A B C D E

TABLE
+3VALW +3VALW_GS

APS G-Sensor P/N Mode Selection

l
RG1 1 @ 2 0_0402_5%

3 1 +3VALW_GS

D
H I2C Mode

a
1 QG1 1 1
+3VS +3VALW_GS +3VALW_GS CG1 AO3413_SOT23-3 CG3

G
2
L SPI Mode W=40 mils @ @ CG2 10U_0603_6.3V6-M
1 0.1U_0402_10V6-K .01U_0402_16V7-K @ 1

it
2 2 2

RG4
1 2
[66] EC_GS_ON#
100K_0402_5% 1
2

10U_0402_6.3V
1U_0402_10V6K
RC347 RC350 1 CG4

1
10K_0402_5% 10K_0402_5% .01U_0402_16V7-K
2

CC101

C8527
n
1

2
2

e
UGSEN1

14
1
Vdd_IO

Vdd
8

d
I2C_CLK_GSENSE 4 CS
I2C_DATA_GSENSE 6 SCL/SPC 20150105
ADDR_SEL 7 SDA/SDI/SDO +3VALW_GS
SDO/SA0 11 GSENSE_INT

if
16 INT1 9 GSENSE_INT2 1
15 ADC1 INT2 TG1
13 ADC2 10
ADC3 RES RG2 1 @ 2 0_0402_5% GSENSE_INT
2 2 2

GND_1

GND_2
NC_1
2

3
RC292 NC_2
10K_0402_5%

2
5

12
LIS3DHTR_LGA16_3x3

G1
1

n
I2C_CLK_GSENSE 1 6
S1 D1 EC_SMB_CK3 [11,25,37,59,66]

QV13A
SB000013A00
NTJD5121NT1G_SC88-6

5
o

G2
I2C_DATA_GSENSE 4 3
S2 D2 EC_SMB_DA3 [11,25,37,59,66]

+3VS
SB000013A00
QV13B

Only for UMA SKU 20141128 20150305 20150313

NTJD5121NT1G_SC88-6

20141204
PU AT EC SIDE, +3VS AND 4.7K

C
1 1
+3V_SPI C50
TPM@ C51 TPM@
0.1U_0402_10V6-K 10U_0603_6.3V6-M
20141128 2 2 TABLE
NOTE:
Place 0.1 uF capacitors as close as 1 1 1 1 P/N ADDR_SEL Address
possible to the device power pins.
C8499 C8498 C8497 C8496
2

TPM@ TPM@ TPM@ TPM@ +3V_SPI

+3VS
10U_0603_6.3V6-M

0.1U_0402_10V6-K

0.1U_0402_10V6-K

0.1U_0402_10V6-K

R261
3 2 2 2 2 10K_0402_5% 3
+3V_SPI
H 32h (W) & 33h (R)
TPM@ LIS3DH
L 30h (W) & 31h (R)
1

2
C
R268
22

14

UTPM1
8

TPM@ 10K_0402_5%
20150313 H 3Eh (W) & 3Fh (R)
VDD3

VDD2

VDD1

VSB

@ KX023-1025

1
15 4 PP 1
L 3Ch (W) & 3Dh (R)
TP940
SERIRQ R271 1 @ 2 33_0402_5% SERIRQ_R 18 LAD3 PP 3 1 3

S
F
[11,66] SERIRQ SPI_SI 1 2 SPI_SI_R 21 LAD2/SPI_IRQ GPX/GPIO2 30 1
R263 TPM@ 33_0402_5% GPIO01
[11,21] SPI_SI SPI_SO 1 2 SPI_SO_R 24 LAD1/MOSI SCL/GPIO1
R264 TPM@ 33_0402_5% TP120 Q29
[11,21] SPI_SO SPI_CS2#_TPM 1 2 SPI_CS2_R 20 LAD0/MISO
R265 TPM@ 33_0402_5% AO3413_SOT23-3

G
[11] SPI_CS2#_TPM

2
LFRAME/SCS

2
27 TPM@
SPI_CLK R266 1 TPM@ 2 33_0402_5% SPI_CLK_R 19 SERIRQ 29 R273 TPM@
[11,21] SPI_CLK LCLK/SCLK XOR_OUT/SDA/GPIO0 6 1
GPIO03 TP121 10K_0402_5%
TP124 1 GPIO04 13 GPIO3/BADD 5
PLTRST_FAR# 17 CLKRUN/GPIO04/SINT TEST Q27_G 1 2 SPI_CS2_R
[12,51,56,57,66] PLTRST_FAR#

1
LRESET/SPI_RST/SRESET

C
2

R9456
NOTE: R267 28 2 100_0402_5%
Follow the SPI topology layout guidelines
10K_0402_5% LPCPD NC1 7
in the relevant Intel Platform Design Guide. NC2 TPM@
TPM@ 10
NC3 11
Q29 R268 R273 R9456
1

12 NC4 25
Reserved NC5 26
NC6 31 New silicon
X O X X

L
NC7
NPCT650LB0YX
GND1

GND2

GND3

GND4

33
EX-PAD
Current silicon
4 NPCT650LA0YX_QFN32_5X5 NPCT650LA0YX O X O O 4
9

16

23

32

SA000075L00

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 G SENSOR/TPM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 60 of 83
A B C D E
 5 4 3 2 1

i a l D

n t
i d e
f
C C

o n
B

C B

F C
A

L C Security Classification
Issued Date 2013/09/07
LC Future Center Secret Data
Deciphered Date 2014/09/07
Title

RF
A

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 61 of 83
5 4 3 2 1
 5 4 3 2 1

it al D

e n
C

if d C

o n
B

C B

F C
A

L C Security Classification
Issued Date 2013/09/07
LC Future Center Secret Data
Deciphered Date 2014/09/07
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Title

XXXX
Size Document Number
Custom

Date:
BE460_NM-A551
Wednesday, August 05, 2015 Sheet 62 of 83
R ev
1.0
A

5 4 3 2 1
 i a l
n t
i d e
n f
C o
F C
L C Security Classification
Issued Date 2013/09/07
LC Future Center Secret Data
Deciphered Date 2014/09/07
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Title

XXXX

WWW.AliSaler.Com
Size Document Number R ev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 63 of 83
 5 4 3 2 1

+1VALW to +VCC_IO_AP
3 A
+1VALW
+5VS +1VALW +VCC_IO_AP +VCC_ST

Q23

l
AO4430L_SO8
8 1
7 2

1
+5VALW 6 3
R9446 5
10K_0402_5% 1 1
C8536 C8537

4
4.7U_0603_6.3V6-K 0.1U_0402_10V7-K

2
@ U148

1
2 2

2
R9448

a
100K_0402_5% R9447 A1 A2
@ 0_0402_5% IN OUT
2
D D

2
R9492 1 @ 2 0_0402_5% B1 B2 C8535
[65,66,73] SYSON

1
+VCC_IO_AP_GATE EN GND
0.1U_0402_10V7-K
1

it
SIP32451DB-T2-GE1_WCSP4
20141204

3
D 1

1
5 Q24B C8538

2
G 2N7002KDWH_SOT363-6 0.22U_0402_10V6-K R9494
10K_0402_5% C8534
S 2
20150522 10U_0402_6.3V

1
6

2
SUSP# 2 Q24A
[65,66,73] SUSP#
G 2N7002KDWH_SOT363-6 20150714
S
1

n
+VCC_IO_AP +VCC_IO
+VCC_IO +VCC_STG
JC1 @
1 2
1 2
JUMP_43X79
R272 1 @ 2 0_0805_5%

+3VALW +1VALW
+3VALW

+VCC_STG

d e
0.1U_0402_6.3V7-K
1
C C

C748
if
2
@

1
U149 @
R722

VDD
10K_0402_1%
3 4
Slew Rate=10uS<TR<65us

1
D S
@
2 5
ON CAP

GND
SUSP# 1 2
SLG5NT1533VTR_STDFN8-6_1X1P6

n
6
D23 RB521CM_30

2
@
C749 C747
10U_0402_6.3V 2200P_0402_25V7-K

1
@ @

C o B

F C
C
A A

L
Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 64 of 83
5 4 3 2 1
 +5VALW VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=18mohm +5VS

i a l
t
U11 J5 @
1 14 +5VS_LS 1 2
2 VIN1_1 VOUT1_2 13 1 2
VIN1_2 VOUT1_1 JUMP_43X118
1 1
SUSP# 3 12 C71 1 2 1000P_0402_25V7-K
Load Switch @ C69
[64,66,73]
1U_0402_6.3V6-K
SUSP#
4
ON1 CT1
11
@ C70
0.1U_0402_10V7-K
+5VALW To +5VS +5VALW VBIAS GND

n
2 2
SUSP# 5 10 C72 1 2 100P_0402_50V8-J
+3VALW To +3VS +3VALW
6
ON2 CT2
9 J6 @
+3VS

7 VIN2_1 VOUT2_2 8 +3VS_LS 1 2

VIN2_2 VOUT2_1 1 2

e
1 15 JUMP_43X118 1
GPAD
@ C73 TPS22966DPUR_WSON14_2X3 @ C74
1U_0402_6.3V6-K 0.1U_0402_10V7-K
2 2

+5VS, C159 --> 1.5ms

d
+3VS, C160 --> 2.5ms

+3VALW to +3V_DDR

n f i SUSP# to SUSP

+5VLP +5VALW

1
+3VALW +3V_DDR +0.675VS
U17 R157 R156
5 1 +3V_DDR 100K_0402_5% 100K_0402_5%
IN OUT

1
@

2
2 R159
1 From PCH GND 1
C751 SUSP
@ @
47_0603_5%

C
SYSON 4 3 [50] SUSP
C750 4.7U_0603_10V6-K
[64,66,73] SYSON EN OC

2
2 1U_0402_6.3V6-K 2
G524B1T11U_SOT23-5 @ @ Q28B

3
D D 2N7002KDWH_SOT363-6
SUSP# 2 Q28A 5 SUSP
G G
2N7002KDWH_SOT363-6
S S

4
SB000013A00 SB000013A00

F C
L C Security Classification
Issued Date 2013/09/07
LC Future Center Secret Data
Deciphered Date 2014/09/07
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Title
DC V TO VS/ V-PCH/VM

WWW.AliSaler.Com
Size Document Number R ev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 65 of 83
 5 4 3 2 1

+3VL

1 RE1 2 PECI
Vcc 3.3V +/- 5%
[6] H_PECI
43_0402_5% RE3 100K +/- 1%

2
l
1 RE3 Board ID RE7 VAD_BID min V AD_BID typ VAD_BID max Phase
@
CE1 +3VL 100K_0402_1%
47P_0402_50V8-J All capacitors close to EC 0 0K +/- 5% 0 V 0 V 0 V SDV

1
2
+3VL CE4 CE5 CE8 CE6 CE9 CE10 Board_ID 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V FVT
Intel recommend 2 18K +/- 5% 0.436 V 0.503 V 0.538 V SIT

2
0.1U_0402_25V6-K

0.1U_0402_25V6-K

0.1U_0402_25V6-K

0.1U_0402_25V6-K

0.1U_0402_25V6-K

0.1U_0402_25V6-K
RE7
1 1 1 1
@
1
@
1
33K_0402_1%
3 33K +/- 5% 0.712 V 0.819 V 0.875 V SVT
Close to EC +3VS +3VL_AVCC
4 4.7K +/- 5% 0.141 V 0.148 V 0.155 V
D D

it
CE7

1
1 2 +VCOREVCC 2 2 2 2 2 2
20150724 5 24K +/- 5% 0.612 V 0.638 V 0.664 V
0.1U_0402_25V6-K
+3VL

114
121
127
12

11

26
50
92

74
RE4 minimum trace width 12 mil

3
1 2 WRST# UE1 +3VS
1

VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VCC

AVCC
VBAT

VSTBY(PLL)
VCORE
100K_0402_5%
CE11
ALL_PWRGD 2 1
1U_0402_10V6-K RE41 10K_0402_5%
2 EC_ON2 [80,81]

n
KBRST# 4 24 LOGO_LED#
[11] KBRST# KBRST#/GPB6 PWM0/GPA0 AOU_IFG# LOGO_LED# [42,53] +3VL +3VL_AVCC
SERIRQ 5 25
[11,60] SERIRQ LPC_FRAME# SERIRQ/GPM6 PWM1/GPA1 EC_ON2_R RE40 2 AOU_IFG# [57]EC_ON2
6 28 @ 1 0_0402_5% LE1
+3VALW [11]
[11]
LPC_FRAME#
LPC_AD3
LPC_AD3 7 LFRAME#/GPM5 PWM2/GPA2 29 ALL_PWRGD 20150522 1 2 +3VL_AVCC
LPC_AD2 8 LAD3/GPM3 PWM3/GPA3 30 VR_ON_EC RE53 1 2 0_0402_5% +3VALW
[11] LPC_AD2 LPC_AD1 LAD2/GPM2 PWM PWM4/GPA4 EC_FAN_PWM VR_ON [12,74]
9 31 BLM18PG121SN1D_2P

e
HDD_DETECT# [11] LPC_AD1 LPC_AD0 LAD1/GPM1 PWM5/GPA5 EC_FAN_PWM [54]
RE15 1 2 100K_0402_5% 10 32 BEEP# @ 1 1
[11] LPC_AD0 CLK_PCI_EC 13 LAD0/GPM0 PWM6/SSCK/GPA6 34 VCCST_PG_EC BEEP# [40] 2 1
[11] CLK_PCI_EC LPCCLK/GPM4 LPC PWM7/RIG1#/GPA7 OTP_RESET VCCST_PG_EC [12]
+3VALW WRST# 14 120 RE48 10K_0402_5% CE2 CE3
HDD_DETECT# 15 WRST# TMRI0/GPC4 124 SUSP#_EC 1 OTP_RESET
2 0_0402_5% [69]
RE54 0.1U_0402_25V6-K 1000P_0402_50V7-K
[41] HDD_DETECT# EC_RX ECSMI#/GPD4 TMRI1/GPC6 SUSP# [64,65,73] 2 2
RPE1 16
[56] EC_RX EC_TX PWUREQ#/BBO/SMCLK2ALT/GPC7 GPU_VR_HOT#
1 8 17 66 LE2
2 7 AOU_IFG# [56]
[12,51,56,57,60]
EC_TX
PLTRST_FAR#
PLTRST_FAR# 22 LPCPD#/GPE6 ADC0/GPI0 67 CP_BYPASS_EC 0_0402_5% 1
GPU_VR_HOT# [25,79]
@ 2 RE51 CP_BYPASS
CP_BYPASS [14,53]
20150522 EC_AGND 1 2
3 6 KB_FN EC_SCI# 23 LPCRST#/GPD2 ADC1/GPI1 68 BATT_TEMP

d
EC_WLAN_WAKE# [11] EC_SCI# VGA_AC_DC# ECSCI#/GPD3 ADC2/GPI2 Board_ID BATT_TEMP [70,71] PM_SLP_S3#
4 5 126 ADC 69 2 1 BLM18PG121SN1D_2P
[25] VGA_AC_DC# GA20/GPB5 ADC3/GPI3 FAN_ID
70 D62 @ RB521CM_30
10K_0804_8P4R_5% IT8586E/AX ADC4/GPI4
ADC5/DCD1#/GPI5
71
72
ADP_I
TP_REST_EC 0_0402_5% 1
FAN_ID
ADP_I [71]
@ 2 RE52
[54]
TP_REST
LQFP-128L TP_REST [14,53]

if
RPE2 ADC6/DSR1#/GPI6 73 ADP_ID +5VALW
1 8 KSO1 KSI[0..7] KSI0 58 ADC7/CTS1#/GPI7 ADP_ID [69] 20141205
[55] KSI[0..7] KSI0/STB#
2 7 KSO2 KSI1 59 78 VGATE VGATE [74]
3 6 FAN_ID KSO[0..17] KSI2 60 KSI1/AFD# DAC2/TACH0B/GPJ2 79 MAINPWON_EC USB_ON# RE2 1 2 10K_0402_5%
LAN_WAKE# [55] KSO[0..17] KSI2/INIT# DAC3/TACH1B/GPJ3 H_PROCHOT_EC MAINPWON_EC [69,70,72]
4 5 KSI3 61 DAC 80 2015/03/11
KSI4 62 KSI3/SLIN# DAC4/DCD0#/GPJ4 81 ENBKL
C ENBKL [5] C
10K_0804_8P4R_5% KSI5 63 KSI4 DAC5/RIG0#/GPJ5
+3VS KSI6 64 KSI5 85 AOU_EN +5VS
KSI6 PS2CLK0/TMB0/CEC/GPF0 PBTN_OUT# AOU_EN [57]
RPE3 KSI7 65 86
1 8 LPC_FRAME# 36 KSI7 PS2DAT0/TMB1/GPF1 87 PCH_SLP_LAN# PBTN_OUT# [12] CP_CLK 1 2
KSO0 PCH_SLP_LAN# [12,51] RE5 4.7K_0402_5%
+3VL 2 7 EC_FAN_SPEED KSO1 37 KSO0/PD0 GPF2 88 PCH_SLP_WLAN# CP_DATA RE6 1 2 4.7K_0402_5%
KSO1/PD1 Int. K/B PS2 GPF3 CP_CLK PCH_SLP_WLAN# [12] 20141205
3 6 KSO2 38 Matrix 89
LID_SW# KSO2/PD2 PS2CLK2/GPF4 CP_DATA CP_CLK [53]
4 5 KSO3 39 90
KSO3/PD3 PS2DAT2/GPF5 CP_DATA [53]

n
KSO4 40 +3VS
10K_0804_8P4R_5% KSO5 41 KSO4/PD4 96 EC_DPWROK
KSO5/PD5 EXTERNAL SERIAL FLASH GPH3/ID3 LAN_PWRON EC_DPWROK [12] EC_FAN_PWM
KSO6 42 97 RE8 1 @ 2 10K_0402_5%
KSO7 43 KSO6/PD6 GPH4/ID4 98 ACOFF
LAN_PWRON [51] 20141205
KSO7/PD7 GPH5/ID5 PCH_PWROK ACOFF [71] GPU_VR_HOT#
RPE4 KSO8 44 99 RE9 1 2 10K_0402_5%
SUSP#_EC KSO8/ACK# GPH6/ID6 PCH_PWROK [12]
1 8 KSO9 45
2 7 KSO10 46 KSO9/BUSY 101 FSCE#
KSO10/PE NC1 SPI_FMOSI# FSCE# [21]
3 6 KSO11 51 102 Un-stuff if not necessary.
KSO11/ERR# NC2 SPI_FMOSI# [21]

o
4 5 SYSON_EC KSO12 52 103 SPI_FMISO
KSO12/SLCT SPI Flash ROM NC3 SPI_FSCK SPI_FMISO [21]
KSO13 53 105
KSO13 NC4 SPI_FSCK [21]
100K_0804_8P4R_5% KSO14 54
KSO15 55 KSO14
EMC_NS@ KSO16 56 KSO15 108 ACIN
CE14 2 1 0.1U_0402_25V6-K KSO17 57 KSO16/SMOSI/GPC3 AC_IN# 109 LID_SW#
KSO17/SMISO/GPC5 UART LID_SW# LID_SW# [54,55]
For EMC, close to UE1
ON/OFF# 110 82 PCH_SYSPWROK
[38,54] ON/OFF# PWRSW# EGAD/GPE1 EC_ON PCH_SYSPWROK [12]
111 SM Bus 83 EC_ON [72]
EC_SMB_CK1 115 XLP_OUT EGCS#/GPE2 84 AOU_CTL1 +3VALW

C
+3VL [70,71] EC_SMB_CK1 EC_SMB_DA1 SMCLK1/GPC1 EGCLK/GPE3 AOU_CTL1 [57]
116
[70,71] EC_SMB_DA1 SMDAT1/GPC2 PM_SLP_S5#
RPE5 PECI 117 GPIO 77 RE49
+3VS EC_SMB_CK1 ADAPTER_ID_ON# SMCLK2/PECI/GPF6 GPJ1 EC_MUTE# PM_SLP_S5# [12]
1 8 118 100 2 1
EC_SMB_DA1 [69] ADAPTER_ID_ON# EC_SMB_CK3 SMDAT2/PECIRQT#/GPF7 SSCE0#/GPG2 EC_GS_ON# EC_MUTE# [39]
2 7 94 106
3 6 EC_SMB_DA3 [11,25,37,59,60]
[11,25,37,59,60]
EC_SMB_CK3
EC_SMB_DA3
EC_SMB_DA3 95 CRX1/SIN1/SMCLK3/GPH1/ID1 SSCE1#/GPG0 104 ME_FLASH EC_GS_ON#
ME_FLASH
[60]
[9]
5.1K_0402_1% 20150522
4 5 EC_SMB_CK3 CTX1/SOUT1/GPH2/SMDAT3/ID2 DSR0#/GPG6 107 SYSON_EC RE55 1 2 0_0402_5%
DTR1#/SBUSY/GPG1/ID7 SYSON [64,65,73]
119 BKOFF#
CRX0/GPC0 123 WLAN_PWRON BKOFF# [42] D63
2.2K_0804_8P4R_5% @
CTX0/TMA0/GPB2 PM_SLP_S3# WLAN_PWRON [56] PM_SLP_S4#
+3VL 112 18 PM_SLP_S3# [12] 2 1
LAN_WAKE# 125 VSTBY0 RI1#/GPD0 21 PM_SLP_S4#
[51] LAN_WAKE# GPE4 RI2#/GPD1 PM_SLP_A# PM_SLP_S4# [12]
WAKE UP 76 PM_SLP_A# [12]
B TACH2/GPJ0 48 AOU_CTL3 RB521CM_30 B
TACH1A/TMA1/GPD7 47 EC_FAN_SPEED AOU_CTL3 [57] +3VL
USB_ON# TACH0A/GPD6 EC_WLAN_WAKE# EC_FAN_SPEED [54]
33 19 EC_WLAN_WAKE# [56] MIRROR@
[44] USB_ON# GINT/CTS0#/GPD5 L80HLAT/BAO/GPE0

C
CP_RESET# RE50 2 @ 10_0402_5% CP_RESET#_EC 35 20 KB_FN
[14,53] CP_RESET# EC_RSMRST# RTS1#/GPE5 GPIO L80LLAT/GPE7 KB_FN [55] EC_ON
93 RE39 1 2 10K_0402_5%
+3VS [12] EC_RSMRST# CLKRUN#/GPH0/ID0

EC_WAKE# 2
Please don't place any PU Resistor on GPG[7:2] +3VL
[6,25] EC_WAKE# AC_PRESENT 128 CK32KE/GPJ7
Clock (Reserve hardware strapping)
[12] AC_PRESENT CK32K/GPJ6 MIRROR@
EC_MUTE# RE31 1 2 10K_0402_5%
2

F
RE47 RE32 1 @ 2 10K_0402_5%
@ 10K_0402_5%
AVSS
VSS1

VSS2
VSS3
VSS4
VSS5
VSS6

1. Version CX : Don't Support Mirror Code

1

D59
@ IT8586E-AX_LQFP128_14X14 IT8586E/FX LQFP Version DX/EX/FX : Support Mirror Code
1

27
49
91
113
122

75

PM_SLP_S3# 1 2 VR_ON
SA00005W940
2. For Mirror Code
RB521CM_30 EC_AGND "H" --> Enable
"L" --> Disable (Default)

C
*

AC IN, need to conf i r mt he pi ni s Hi gh or L o w ac t i ve whi le pulg AC IN

+3VL
Close to UE1 For factory EC f l as h

L
ACIN RE33 1 2 10K_0402_5%
1 EC_SMB_CK1 RE34 1 @ 2 0_0402_5%
EC_SMB_DA1 ACPRN [71]
IT1 @1
PROCHOT# IT2 @1 DEV1 @ 2 1 RB751V-40_SOD323-2
For ESD (EC asserts PROCHOT# signal by driving high, IT3
IT4
@1
@1
SCS00007P00
A A
EMC_NS@ the level shif t er must i nvert i t and dri ve t he pr ocess or si de PR OC HOT# l o w.) IT5 @ CE12 1 2 100P_0402_50V8-J
CE13 1 2 220P_0402_50V7-K PLTRST_FAR#

For EMI 1 KSI7

IT6 @1 KSI6
VR_HOT# IT7 @1 WRST#
[6,71,74] VR_HOT# IT8 @
1

D
H_PROCHOT_EC 1
EMC_NS@ 2 CE17
CE16 2 1 100P_0402_50V8-J BATT_TEMP G Title

要要E C 的
QE1 S 47P_0402_50V8-J
Security Classification LC Future Center Secret Data
3

2N7002WT1G_1N_SC-70-3 2
BATT_TEMP ADC p i n Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX
SB000019400 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
BE460_NM-A551
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 66 of 83
5 4 3 2 1
 5 4 3 2 1

D
Screw Hole

i a l D

H17
PAD_CT6P0SHAPEB8P0X6P65D2P5

1
H24
PAD_C8P0D2P5

1
n t
e
H21 H20
PAD_shapeT8P0X10P5CB8P0D2P5 PAD_C6P0D3P3
GPU
H5 H6 H7 @ @

d
1

1
PAD_CT8P0B6P0D3P3 PAD_CT8P0B6P0D3P3 PAD_CT8P0B6P0D3P3

i
1

1
H19 H18 H13 H26 H12
PAD_C5P0D2P3 PAD_C8P0D2P5 PAD_O3P9X2P7D3P9X2P7N PAD_O4P7X3P5D4P7X3P5NPAD_C8P0D2P5

f
C C
@ @ @ @ @

1
H16 H15
PAD_O2P3X3P5D2P3X3P5N PAD_shapeT8P0X10P5CB8P0D2P5
H28

n
PAD_C6P0D2P3
@ @
1

1
H27
PAD_C5P0D2P5

o
CPU @

1
H1 H2 H3 H4
PAD_C6P0D3P2 PAD_C6P0D3P2 PAD_C6P0D3P2 PAD_C6P0D3P2

H10

C
1

PAD_CT8P0B6P0D2P5

1
H25 H11
PAD_C2P3D2P3N PAD_C5P0D2P5
B H14 H8 B
PAD_CT6P0B8P0D2P5 PAD_C8P0D2P5
@ @

1
C
1

C F
A

L
WWW.AliSaler.Com
PCB Fedical Mark PAD
FD1 FD2 FD3 FD4 FD5 FD6
Security Classification
Issued Date 2013/09/07
LC Future Center Secret Data
Deciphered Date 2014/09/07
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Title

PLM/SCREW HOLE
Size Document Number
Custom
BE460_NM-A551
R ev
1.0
A
1

Date: Wednesday, August 05, 2015 Sheet 67 of 83

5 4 3 2 1
 5 4 3 2 1

it al D

e n
C

if d C

o n
B

C B

F C
A

L C Security Classification
Issued Date 2013/09/07
LC Future Center Secret Data
Deciphered Date 2014/09/07
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Title

Size
C
XXXX
Document Number
BE460_NM-A551
Rev
1.0
A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 68 of 83
5 4 3 2 1
 5 4 3 2 1

l
PD1
RB751V-40
PD2
1SS355 PR1 PR2 1 2
100K_0402_1% 10K_0402_1%
VSYSTEM PRT2A
[66,70,72] MAINPWON_EC 2 1 1 2 1 2

a
1 2
B+

2
D PD3 D

i
RB751V-40 0_0402_5%
+3VALW

3
PQ1 UMA@
E
2B PR3

t
MMBT3906_SOT23-3 750K_0402_5%

1
C

1
2
VSYSTEM Charger 1.35VS VGA DIS@
PR4
750_0402_1% 540_0402NEW_30% 540_0402NEW_30% 540_0402NEW_30%

1
C PRT1 PRT3 PRT2
PQ2 2 2 1 2 1 2 1
1

n
1
MMBT3904_SOT23-3 B
PD4 @ PR5 E
2 OTP_RESET [66]

1
D
RB751V-40_SOD323-2 1M_0402_5%
PC1 PQ3 2
G
2N7002KDWH 2N SOT363-6

1U_0603_25V7K2N7002WT1G

2
1 S

3
e
2

D
ADAPTER_ID_ON
PQ4A

@ PR6 2 2 1 2 1 2 1
G

2N7002KDWH 2N SOT363-6
0_0402_5%
S PRT6 PRT5 PRT4
1

540_0402NEW_30% 540_0402NEW_30% 540_0402NEW_30%

1

3
D
PR7

PQ4B
10K_0402_1% PR8 5 ADAPTER_ID_ON# [66] VCCGT VCORE VCCSA

d
1 2 G
[38] DOCK_ID ADP_ID [66]1M_0402_5% S

4
2
680P_0402_50V7-K

i
1
0.1U_0402_6.3V

A/D
1
1
1
PC2

PC3

f
C PD5 C
2

2 AZ5425-01F_DFN1006P2E2
2
2

EMC@

n
PL1
MURATA BLM18KG300TN1D

1 2
EMC@
APDIN PF1
PL2
MURATA BLM18KG300TN1D
VSYSTEM
7A_32V_0437007.WR

o
APDIN2 1 1 2

EMC@ EMC@ EMC@ EMC@

1000P_0402_50V7-K

1000P_0402_50V7-K
100P_0402_50V8-J

100P_0402_50V8J
1

C
2

2
PC4

PC5

PC6

PC7

B B

C
+3VL
2

PR18
1.5K_0402_1%

F
+RTCBATT
1

<10,50> 1 2

PD6
2

RB751V-40
PR19
45.3K_0402_1%
RTC Battery

C
1

WWW.AliSaler.Com 5
L 4
Security Classification
Issued Date 2013/08/05
LC Future Center Secret Data
Deciphered Date 2014/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3 2
Title

Custom

Date:
DCIN / Vin Detector

Size Document Number

AIVL2_NM-A351
Wednesday, August 05, 2015
1
Sheet 69 of 83
R ev
1.0
A
 5 4 3 2 1

PRT7 under CPU botten side :

CPU thermal protection at 93 +-3 degree C
Recovery at 56 +-3 degree C

D
+5VLP
+3VL

it al +3VALW
D

47K_0402_1%
12.7K_0402_1%
PC8

1
@ PR10

@ PR11
0.1U_0603_16V7K

2
PR9
16.5K_0402_1%

PU1

2
n

OTP_N_003
1 8 NTC_V_1
VCC TMSNS1
@ PR13 2 7 OTP_N_002 2 1

100K_0402_1%_NCP15WF104F03RC
0_0402_5% GND RHYST1
[66,69,72] MAINPWON_EC 1 2 3 6 PR12
OT1 TMSNS2

1
20K_0402_1%

e
4 5
OT2 RHYST2

PRT7
G718TM1U_SOT23-8

2
C

PL3 EMC@
MURATA BLM18KG300TN1D

if d C

n
ME@ JBATT1 VMB2 VMB 1 2
PF2
FOX_GS73071-10272-M-7H
12A_32V_0501012.WRS PL4 EMC@
7 2 1 MURATA BLM18KG300TN1D
9 7 6 BATT+
PTH2 6 5 EC_SMCA 1 2

o
5 4 EC_SMDA
4 3
3 EMC@ EMC@

2
8 2
PTH1 2 1 PC9 PC10
1 1000P_0402_50V 0.01U_0402_25V

1
2

PESD5V0U2BT_SOT23-3
1

1
PR15

C
@ PD7

PR14
100_0402_1%
1

100_0402_1%
2

EC_SMB_CK1 [66,71]
B B

EC_SMB_DA1 [66,71]

C
PR16
100K_0402_1%
2 1
+3VALW

1 2
A/D
BATT_TEMP [66,71]

F
PR17
10K_0402_1%

L C Security Classification
Issued Date 2013/08/05
LC Future Center Secret Data
Deciphered Date 2014/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Title
BATTERY CONN/OTP

Size Document Number

Custom
AIVL2_NM-A351
R ev
1.0
A

Date: Wednesday, August 05, 2015 Sheet 70 of 83

5 4 3 2 1
 5 4 3 2 1

VSYSTEM
PQ101
AON7466
3
2
P2
3
2
PQ102
AON7466 P3
EMC@
PL101
1UH_PCMB053T-1R0MS_20%
PR101
0.01_1206_1%
1 2

i a l D

t
5 1 1 5 1 2
B+
EMC@ EMC@

10U_0805_25V6-K

10U_0805_25V6-K
1

2
PC104
1

1
PC102

PC103
PC101 PR102 0.022U_0402_25V

2
n
1

1
4.7_0603_5%
470P_0402_50V 2
PC105

2
0.1U_0402_25V7K PQ104

5
AON7466
2 1
PQ103

e
2N7002WT1G BQ24780_BATDRV 4

1
S

D
3 1 PC107

1
2
3
1U_0603_25V7-K PC106

499K_0402_1%

0.01U_0603_50V7K
2

1
0.1U_0402_25V7K 2

PR103
G
2

1
PR106

PC108
2 1 2 1 10_0402_1%

d
1
PD101 PR107 1

2
RB751V-40 PR104 PR105 VSYSTEM B+ 10_0402_1%
1M_0402_5% 1M_0402_5%

2
1 2 PR108

i
1K_0402_1%

2
2

2
RB751V-40
PD102

RB751V-40
PD103
1 2
DOCK_CONSUMP [38]
1 2 EMC@ RF_NS@ RF_NS@ B+
PR109
2N7002WT1G
1

f
C @ 0_0402_5% @ PC109 C

10U_0805_25V6K

10U_0805_25V6K
1

1
1 2 2 100P_0402_50V8-J
PQ105

2200P_0402_25V7-K
[66] ACOFF

47P_0402_50V8-J
G VSYSTEM 1 1
4.02K_0603_1%

4.02K_0603_1%

68P_0402_50V8-J
1

1
PC111

PC112

PC113

PC114
S

PC110
3
2

ACN
ACP
PR110
PR111

PR112

2
2
10K_0402_1% 2 2

5
PR114
2

1
n
PR115 PR113 10_1206_5% BQ24780_VDD
1

68K_0402_1% 432K_0402_1% PC115 PC116

ACN
ACP
1 2 1U_0603_25V 4.7U_0603_10V6-M

1
2 1 28 24 1 2

2
VCC REGN 4 PQ106
1 2 6 PR116 PC118 AON7408L
ACDET 2.2_0603_5% 0.047U_0603_25V
PC117 0.1U_0402_25V7K 25 BST_CHG1 2 2 1
BTST

o
3
2
1
PL102 PR117
3 26 DH_CHG 4.7UH_PCMB104T-4R7MS 0.01_1206_1%
CMSRC HIDRV 1 2 CHG 1 2 BATT+
4
ACDRV
EMC@

5
27 LX_CHG
PHASE

2
[66] ACPRN

4.7_0603_5%
@ PR118 1 2 0_0402_5% 5
ACOK

PR119
@ PR120 1 2 0_0402_5% 11 PQ107

10U_0805_25V6-K

10U_0805_25V6-K
[66,70] EC_SMB_DA1 SDA PU101 23 DL_CHG 4 AON7408L
LODRV

2
@ PR121 1 2 0_0402_5% 12 BQ24780SRUYR 22
[66,70] EC_SMB_CK1 SCL GND EMC@

PC119

PC120
1
680P_0402_50V7K
3
2
1

1
@ PR122 1 2 0_0402_5% 7 29
[66] ADP_I IADP PAD

PC121
2

1
@ PR123 1 2 0_0402_5% 8 18 BQ24780_BATDRV
IDCHG BATDRV PC122
@ PR124 1 2 0_0402_5% 9 0.1U_0402_25V7K PC123
[74] PSYS

2
PMON 17
B BATSRC 0.1U_0402_25V7K B
PR125 10_0603_5%
PC125

PC126

PC127

20 SRP 2 1
1 2 10 SRP
[6,66,74] VR_HOT# PROCHOT#

1
C
@ PR126 0_0402_5%
2

13 PC124
100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

CMPIN
0.1U_0402_25V7K
BATPRES#

2
TB_STAT#

14 PR128 10_0603_5%
1

CMPOUT 19 SRN 2 1
21 SRN
ILIM
2

@ PR129

F
16

15

0_0402_5%
PR130
1

316K_0402_1% PR131
1 2 1 2
+3VALW BATT_TEMP [66,70]
47K_0402_1%
1
1

PR132
PC128 100K_0402_1%

C
0.1U_0402_25V6
2

WWW.AliSaler.Com 5
L 4 3
Security Classification
Issued Date 2013/08/05
LC Future Center Secret Data
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2
2014/12/31

C
Title

Size

Date:
CHARGER

Document Number

Wednesday, August 05, 2015

AIVL2_NM-A351
1
Sheet 71 of 83
Rev
1.0
A
 5 4 3 2 1

l
+3VALW
FSW=750 KHz
TDC:8A

a
PU201
B+ @ SYX198BQNC_QFN10_3X3
D
2
PJ201
1 EMC@ RF_NS@ +3V_VIN 7 2 +3V_PWRGD
OCP:11A D

2 1 EN2 PG

it
@ PR202 PC203

1
1 0_0603_5% 0.1U_0603_25V7-M

47P_0402_50V8-J

10U_0805_25V6-K
0.1U_0402_25V6-K
+3VALW

1
JUMP_43X79 PR201 8 6 +3VBS 1 2 1 2

PC201
IN BS

PC202
1M_0402_5% PL201

PC230
2.2UH_PCMB063T-2R2MS_8A_20% PJ202
8A
EMC@ EMC@

2
2 9 10 +3VLX 1 2 +3VALW_P 2 1

2
GND LX PR203 2 1
@ 0_0402_5% @ JUMP_43X118
EMC_NS@

2
3V5V_ON 1 4 +3VALW_OUT 1 2 +3VALW_P

2200P_0402_25V7-K
EN1 OUT PR205 PR204

22U_0805_6.3V6-M

22U_0805_6.3V6-M

22U_0805_6.3V6-M

22U_0805_6.3V6-M

0.1U_0402_25V6
@ 0_0402_5% 4.7_0603_5%
100mA 1 1 1 1

1
PR206 +3VALW_FB 3 5 1 2

PC204

PC205

PC206

PC207

PC210

PC211
+3VL

n
2.2K_0402_1% FB LDO

2 1
EC_ON 1 2
[66] EC_ON 1 EMC_NS@

2
PC208 2 2 2 2
4.7U_0603_6.3V6-K PC209
680P_0402_50V7K
+3VL

1
2

1
e
47K_0402_1%
1

2
@ PC213
PR216

PR208
0.1U_0402_25V6-K 1M_0402_5%
47K_0402_1%
1

PR217

1
PC212 PR207

2
0.01U_0402_25V7-K 1K_0402_1%
20150309
2

D 1 2 1 2

d
2
2

G
3

D
S
1

[66,69,70] MAINPWON_EC 5 2N7002KDWH 2N

if
C G C
S PQ201A
4

2N7002KDWH 2N

PQ201B

+3VALW

n
1
@ PR209
100K_0402_5%
@ PR210
0_0402_5% +5VALW

2
+3V_PWRGD 1 2
FSW=750 KHz
TDC:8A

o
PU202
B+ @ SYX198CQNC_QFN10_3X3 @ PR211

2
PJ203
RF_NS@
1 EMC@ +5V_VIN 8 2 +5V_PWRGD
0_0402_5%
1 2
OCP:11A
2 1 IN PG @ PR212 PC217
47P_0402_50V8-J

1 0_0603_5% 0.1U_0603_25V7-M
10U_0805_25V6-K

10U_0805_25V6-K
0.1U_0402_25V6-K

+5VALW
1

JUMP_43X79 9 6 +5VBS 1 2 1 2
PC231

PC215

PC214

PC216

GND BS PL202
PC218 2.2UH_PCMB063T-2R2MS_8A_20% PJ204
8A
EMC@ EMC@ 2
2

2 1 2+5V_VCC 5 10 +5VLX 1 2 +5VALW_P 1

VCC LX 2 1

C
PR213

2
1U_0603_25V6M @ 0_0402_5% @ JUMP_43X118
B 3V5V_ON 1 4 +5VALW_OUT1 2 +5VALW_P EMC_NS@ B

2200P_0402_25V7-K
EN OUT PR214

22U_0805_6.3V6-M

22U_0805_6.3V6-M

22U_0805_6.3V6-M

22U_0805_6.3V6-M

22U_0805_6.3V6-M

22U_0805_6.3V6-M

0.1U_0402_25V6
4.7_0603_5%
100mA 1 1 1 1

1
+5VFB 3 7

PC219

PC220

PC221

PC222

PC223

PC224

PC227

PC228
+5VLP

1
FB LDO
1 EMC_NS@

2
2
PC225 2 2 2 2
4.7U_0603_6.3V6-K PC226
680P_0402_50V7K

1
2

F C PC229
6800P_0402_25V7-K
1 2

6800pf soft start 2ms

47nf soft start 7ms
1
PR215
1K_0402_1%
2

C
A A

L
Security Classification LC Future Center Secret Data Title
Issued Date 2013/08/08 Deciphered Date 2013/08/05 3VALWP/5VALWP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AIVL2_NM-A351
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 72 of 83
5 4 3 2 1
 A B C D

l
PJ301
2 1
2 1
@ JUMP_43X118

PJ302 +1.35V

a
+1.35VP 2 1
2 1
1
@ JUMP_43X118 1

i
+1.35VP PJ303
2 1
+0.675VSP 2 1 +0.675VS

t
PJ304
B+ EMC@ EMC@ RF_NS@ RF_NS@

1
2 1 B+_1.35V
2 1 PC301 @ JUMP_43X39

220K_0402_1%
2200P_0402_25V

47P_0402_50V8-J

68P_0402_50V8J
@ JUMP_43X79 10U_0603_6.3V6M

0.1U_0402_25V6

2
10U_0805_25V6-K

10U_0805_25V6-K
1 1

1
PC302

PC304

PC307

PC305

PC306
PC303

n
+0.675VS
2

2
2
TDC: 1.5A

+0.675VSP
PR301
100K_0402_1% +0.675VSP

+1.35VP
1 2

PR302
1.35V

10U_0603_6.3V6M

0.1U_0402_6.3V7-K
2
TDC: 11 A

1
PC308

PC309
OCP: 15 A

5
Fsw: 300KHz

14

11

13

19

20

2
PQ301

VTT
CS
PGND

VID

VLDOIN
AON7408L PR303 21
2.2_0603_5% PAD
4 1 2 1 2 18 1
BOOT VTTGND

i
PC310
0.22U_0603_25V7K DH_1.35V 17
UGATE VTTSNS
2 +0.675VSP
PL301

1
2
3
2
1UH_PCMC063T-1R0MN_+-20% 2

f
PU301 3 VTTREF_0.675V
EMC@ EMC@ 1 2 LX_1.35V 16 RT8231AGQW
GND
+1.35VP PHASE
VTTREF_0.675V
4
EMC_NS@ VTTREF
2

PR306
2200P_0402_25V7-K

PR304 DL_1.35V 15 5.1_0603_5%

LGATE
1
470P_0402_50V7K

12 2 1
330U_D2_2V_R9M
0.1U_0402_25V6

4.7_0603_5%

n
1 VDD +5VALW

1
PR305

PGOOD
1
1

+
PC312

PC313

PC311

@ PC314

7.87K_0402_1% 5 1 PC315

TON
1

PQ302 VDDQ 0.033U_0402_16V7K

FB

S5

S3

2
AON7534 PC316
2

2 2 1U_0402_10VA-K
EMC_NS@

10
4 2
2

o
PC317

2 TON_1.35V
680P_0402_50V7K

S5_1.35V

S3_1.35V
@ PR308
1
1

100K_0402_1%
1
2
3

PR307 1 2 +3VS
10K_0402_1%

887K_0402_1%
PR310
@ 0_0402_5% SM_PG_CTRL [22]
2

PR309
1 2

C
FB_1.35V

@ PR311

1
B+_1.35V 0_0402_5% SUSP# [64,65,66]
1 2

1 2
[64,65,66] SYSON

1
3
@ PR312 3

0_0402_5% @ PC318

2
0.1U_0402_6.3V7-K

2
1
C
@ PR313 @PC319
47K_0402_5% 0.1U_0402_16V

C F
L
4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/05 Deciphered Date 2014/12/31 +1.35V/+0.675VS

WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AIVL2_NM-A351
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 73 of 83
A B C D
 5 4 3 2 1

B+ +5VALW

l
+VCC_ST

1
1 +3VS

1
PC401 PR401 PR402 PC402
0.01U_0402_25V7-K 1K_0402_5% 2_0402_5% 1U_0402_6.3V6-K
1

2
PC403 2

2
0.1U_0402_6.3V6-K

1
PR403 PR404 2
100_0402_5% 47_0402_5%

2
12

13
PR406

2
D D
10K_0402_1%

VCC
VRMP

1
it
PR407
@ 0_0402_5%
VR_ON 1 2 37 38
[12,66] VR_ON VGATE VGATE [66]
PR408 EN VR_RDY PR409
@ 0_0402_5% 75_0402_5%
VR_SVID_ALRT# 1 2 33 31 1 2 VR_HOT# VR_HOT# [6,66,71]
[16] VR_SVID_ALRT# ALERT# VR_HOT#
PR410
51_0402_5%
VR_SVID_CLK 1 2 34 35
[16] VR_SVID_CLK DRVON DRVON [75,76,77]
PR411 SCLK DRVON
10_0402_5%
VR_SVID_DAT 1 2 32 22 PWM_1A
[16] VR_SVID_DAT SDIO PWM_1A PWM_1A [75]

46 29 SW_1A
[71] PSYS PSYS PR412 1 2 7.5K_0603_1% SW_1A [75]
PSYS CSP_1A

1
2 1 PC441 PR405
PR413 1U_0402_6.3V6-K 12K_0402_1%
PC404 16.5K_0402_1% 1 2

2
n
1000P_0402_25V7-K
VCC_SENSE 1 2 1 2
[16] VCC_SENSE

1
PR414
3.4K_0402_1% PU401 1 PRT401

1
MURAT_NCP15WF104F03RC
1 2 24 NCP81208MNTXG_QFN48_6X6 PC440
PR415 VSP_1A 1000P_0402_50V7-K

2
3.4K_0402_1% PC405 2 PLACE CLOSE TO
2 0.033U_0402_25V7K VCCCPUCORE PL403
PC406
28 CSN_1A

e
1000P_0402_25V7-K
1

CSN_1A CSN_1A [75]

PR416 PR417
910_0402_1% @ 0_0402_5%
1 2 25 23 1 2
VSN_1A TSENSE_1PH
PC407
3300P_0402_50V7-K
VSS_SENSE

1
[16] VSS_SENSE 1 2

2
PRT402
PC408 PR418 MURAT_NCP15WF104F03RC
PC409 1 2 15P_0402_50V8-J 26 0.1U_0402_25V6-K 61.9K_0402_1%

2
COMP_1A

2
PLACE CLOSE TO

d
PR419

1
1 2 1 2 VCCCPUCORE PU402
2.49K_0402_1%
PR420 PC410
53.6K_0402_1% 1500P_0402_50V7-K
C 1 2 27 C
ILIM_1A

if
16 PWM1_2PH
PR421
20150518 97.6K_0402_1% PWM1_2PH PWM1_2PH [76]
2 1 30
IOUT_1A 17
PC411 1 2 270P_0402_50V7-M PWM2_2PH

PR422
PC412 1 21000P_0402_50V7-K 2.05K_0402_1%
10 1 2 CSP1 CSP1 [76]
VCCGT_SENSE 47 CSP1_2PH
[16] VCCGT_SENSE VSP_2PH 9
CSP2_2PH +5VALW
2

1
PC413 PR424 PC414
1000P_0402_25V7-K 1.21K_0402_1% 0.1U_0402_25V6-K PR423
1

2
1 2 48 10_0402_1%
VSN_2PH 8 1 2
CSREF_2PH CSN1 [76]
PC415 PR425

n
3300P_0402_50V7-K 26.1K_0402_1%
VSSGT_SENSE 1 2 1 2 1
[16] VSSGT_SENSE IOUT_2PH
PC416 1
470P_0402_50V8-J PC417
1 2 0.1U_0402_16V7-K
20150518
2
PR426
54.9K_0603_1%
2 7 1 2 CSP1
DIFFOUT_2PH CSSUM_2PH

o
3
20150518 FB_2PH

2
PC418 PC419
PR428 PR429 PC420 100P_0402_50V7-K 1000P_0402_25V7-K

1
510_0402_1% 4.75K_0402_1% 2200P_0402_25V7-K PR427 PR430
1 2 1 2 1 2 4 73.2K_0402_1% 165K_0402_1%
PR431 PC421 PC422 COMP_2PH 6 1 2 1 2
49.9_0402_1% 470P_0402_50V8-J 33P_0402_50V8-J CSCOMP_2PH PR432
1 2 1 2 1 2 12.4K_0402_1%
5 1 2
PC423
1000P_0402_25V7-K
PR433
2.74K_0402_1% ILIM_2PH PLACE CLOSE TO
1 2 1 2
20150518 PRT403 1 2 VCCGT PL406
PR434 MURAT_NCP15WM224J03RC
2.74K_0402_1%
[16] VCCSA_SENSE 1 2 45
VSP_1B

C
PR435
B @ 0_0402_5% B
11 1 2 PRT404 1 2
TSENSE_2PH
2

2
MURAT_NCP15WF104F03RC

1
PC425 PR436
1000P_0402_25V7-K PC424 61.9K_0402_1% PLACE CLOSE TO
1

PR437 0.1U_0402_25V6-K
VCCGT PU403

2
1K_0402_1%

1
[16] VSSSA_SENSE 1 2 44
VSN_1B
36 PWM_1B
PC427
PWM_1B PWM_1B [77]
15P_0402_50V8-J PC426 1 2 3300P_0402_50V7-K
1 2 43 40 SW_1B
PR438 1 2 7.5K_0603_1% SW_1B [77]
PC428 COMP_1B CSP_1B
0.01U_0402_25V6-K 1 2 PRT405 1 2
1 2 1 2 PR441 MURAT_NCP15WF104F03RC
12K_0402_1%
ROSC_COREGT

41.2K_0402_1%
1

1
ADDR_VBOOT

PR440 1 2 42 PR439
PC429 PC439 PLACE CLOSE TO
ICCMAX_2PH
ROSC_SAUS

ILIM_1B
0.018U_0402_50V7-J

3300P_0402_50V7-K
ICCMAX_1A

ICCMAX_1B

1.5K_0402_1%
PR442
20150518 VCCSA PL408
2

2
100K_0402_1%
1 2 39 41 CSB_1B
CSB_1B [77]
TAB

C
IOUT_1B CSN_1B
PC430
270P_0402_50V7-M
14

15

18

19

20

21

49

1 2
48.7K_0402_1%

88.7K_0402_1%

15.8K_0402_1%

PC431
24K_0402_1%

24K_0402_1%

10K_0402_1%

1000P_0402_50V7-K
1 2
2

F
1

1
PR443

PR444

PR445

PR446

PR447

PR448

C
A A

L
Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/05 Deciphered Date 2014/12/31 IMVP8

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AIVL2_NM-A351
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 74 of 83
5 4 3 2 1
 5 4 3 2 1

PL401
BLM18KG300TN1D
EMC@ EMC@ RF_NS@ 1 2
EMC@ B+

l
PC432 PC433 PC434 PC435 PC436 PC437 PL402
BLM18KG300TN1D

47P_0402_50V8-J

33U_D2_25VM_R40M

33U_D2_25VM_R40M

33U_D2_25VM_R40M

33U_D2_25VM_R40M
1

1
1 2

PC438
2200P_0402_25V7-K
10U_0805_25V6-K

10U_0805_25V6-K

10U_0805_25V6-K

10U_0805_25V6-K

0.1U_0402_25V6
1 1 1 1
EMC@ + + + +

PC525

PC526

PC527

PC528
+VCC_CORE

2
2

a
2.2_0603_1%
TDC= 21A

5
PR449 2 2 2 2
2 1 @ @ @ @
D
IccMAX=28A D

i
2
PC442
0.22U_0603_25V7-K
HG_A1
OCP = 36A
PU402 4 PQ401

t
1
NCP81253MNTBG_DFN8_2X2 TPCA8065-H

1 8 PL403
BST DRVH CMLE064T-R15MS0R725-88(0.72mohm+/-5%)

3
2
1
2 7 SW_A1 1 2
[74] PWM_1A PW M SW
+VCC_CORE

n
5

2
3 6
[74,76,77] DRVON EN GND PR450 1

1
4 5

FLAG
4.7_0603_5% @ @
+5VALW VCC DRVL
0_0402_5% 0_0402_5%
+ PC443
EMC_NS@ 330U_D2_2VM_R9M

1 1
1

PC444 LG_A1 4 4 PR451 PR452

e
1U_0402_10V 2

2
PC445
2

680P_0402_50V7K

2
3
2
1

3
2
1
PQ402 PQ403 EMC_NS@
TPCA8057-H TPCA8057-H

d
CSN_1A [74]

SW_1A [74]

n f i C

C o B

F C
A

L C Security Classification
Issued Date 2013/08/05
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
LC Future Center Secret Data
Deciphered Date 2014/12/31
Title
+VCC_CORE
A

WWW.AliSaler.Com
Size Document Number Rev
AIVL2_NM-A351
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 75 of 83
5 4 3 2 1
 5 4 3 2 1

PL404

l
BLM18KG300TN1D
EMC@EMC@RF_NS@ 1 2
B+
EMC@
PC446 PC447 PC448 PC449 PC450 PC451 PL405

a
BLM18KG300TN1D

47P_0402_50V8-J
1

1
1 2

PC452
10U_0805_25V6-K

10U_0805_25V6-K

10U_0805_25V6-K

10U_0805_25V6-K

2200P_0402_25V7-K
0.1U_0402_25V6
D D
EMC@

it
2

2
2
2.2_0603_1%

5
PR453
2 1 PQ404 +VCC_GT
TPCA8065-H
TDC= 18A

2
PC453
0.22U_0603_25V7-K
HG_B1 4 IccMAX=31A

1
PU403
OCP min = 40A

n
NCP81151MNTBG_DFN8_2X2
1 8 PL406
BST DRVH CMLE064T-R15MS0R725-88(0.72mohm+/-5%)

3
2
1
2 7 SW _B1 1 2
[74] PW M1_2PH PWM SW
+VCC_GT

2
3 6

e
[74,75,77] DRVON EN GND 1
PR454 PC454
4 5 4.7_0603_5% +
+5VALW VCC DRVL

FLAG

330U_D2_2VM_R9M
1

1
EMC_NS@ @ @

2 1
1

PC455 LG_B1 4 4 2
1U_0402_10V 0_0402_5% 0_0402_5%

d
9

PC456 PR455 PR456

2

680P_0402_50V7K

2
3
2
1

3
2
1
EMC_NS@

if
C PQ405 PQ406 C
TPCA8057-H TPCA8057-H

CSN1 [74]

CSP1 [74]

o n
C
B B

F C
C
A A

Security Classification LC Future Center Secret Data Title

L
Issued Date 2013/08/05 Deciphered Date 2014/12/31 +VCC_GT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AIVL2_NM-A351
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 76 of 83
5 4 3 2 1
 5 4 3 2 1

l
PL407
EMC@EMC@ RF_NS@ BLM18KG300TN1D
1 2

a
D
B+ D

PC457 PC458 PC459 PC460 EMC@

47P_0402_50V8-J
1

PC461
2200P_0402_25V7-K
10U_0805_25V6-K

10U_0805_25V6-K

0.1U_0402_25V6
t

2
2
2.2_0603_1%

5
PR457

n
2 1

+VCC_SA

2
PC462
0.22U_0603_25V7-K
TDC= 4A

e
PU404 HG_1PH4 PQ407

1
NCP81253MNTBG_DFN8_2X2 AON7408L
IccMAX=5A
1 8 PL408
BST DRVH 0.47UH_PCMB063T-R47MS3R675_18A_20%(DCR+/-5%) OCP = 9A

3
2
1
d
2 7 SW_1PH 1 2
[74] PWM_1B PWM SW
C +VCC_SA C

5
3 6

i
[74,75,76] DRVON EN GND

1
4 5
FLAG

@ @
+5VALW VCC DRVL

2
f
PR458 0_0402_5% 0_0402_5%
1

PC463 LG_1PH 4 PQ408 4.7_0603_5% PR459 PR460

9

1U_0402_10V AON7408L

2
EMC_NS@
2

1 1
3
2
1

n
PC464
680P_0402_50V7K

2
CSB_1B [74]
EMC_NS@

o
SW_1B [74]

B B

C
A

F C
Security Classification LC Future Center Secret Data Title
A

C
Issued Date 2013/08/05 Deciphered Date 2014/12/31 VCCSA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
AIVL2_NM-A351 1.0

L
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 77 of 83
5 4 3 2 1

WWW.AliSaler.Com
 A
B
C
D

+VCC_GT

1
2
1
2
1
2

5
5

PC513 PC488 PC465

+VCC_CORE

+VCC_SA
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

1
2
1
2
1
2
PC514 PC489 PC466
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

1
2
1
2

PC490 PC467
22U_0603_6.3V6M 22U_0603_6.3V6M

1
2
1
2
1
2

PC515

L
22U_0603_6.3V6M PC491 PC468
22U_0603_6.3V6M 22U_0603_6.3V6M

1
2
1
2
1
2

PC516
22U_0603_6.3V6M PC492 PC469
22U_0603_6.3V6M 22U_0603_6.3V6M

1
2
1
2
1
2

PC517
22U_0603_6.3V6M PC493 PC470
22U_0603_6.3V6M 22U_0603_6.3V6M

1
2

C
1
2
1
2

PC518
22U_0603_6.3V6M PC494 PC471
22U_0603_6.3V6M 22U_0603_6.3V6M

1
2
25pcs 22uF for +VCC_GT

12pcs 22uF for +VCCSA

1
2
1
2

PC519
22U_0603_6.3V6M PC495 PC472
22U_0603_6.3V6M 22U_0603_6.3V6M

4
4

1
2
PC520

F
1
2
1
2

22U_0603_6.3V6M
PC496 PC473

1
2
22U_0603_6.3V6M 22U_0603_6.3V6M
PC521
1
2
1
2

22U_0603_6.3V6M
23pcs 22uF for +VCC_CORE

PC497 PC474

1
2
22U_0603_6.3V6M 22U_0603_6.3V6M
PC522
22U_0603_6.3V6M
+VCC_GT

1
2

C 1
2
PC498
PC523 22U_0603_6.3V6M
22U_0603_6.3V6M
1
2

Issued Date
1
2
PC499
PC524 22U_0603_6.3V6M
1
2

22U_0603_6.3V6M

Security Classification
1
2

PC475
+VCC_CORE

PC500 22U_0603_6.3V6M
22U_0603_6.3V6M
1
2

1
2

PC476
PC501 22U_0603_6.3V6M
C 22U_0603_6.3V6M
1
2

1
2

PC477
PC502 22U_0603_6.3V6M

3
3

22U_0603_6.3V6M

2013/08/05
1
2

PC503
22U_0603_6.3V6M
o
1
2
1
2

PC504 PC478
+VCC_CORE
Based on PDDG rev 0.7 Table 5-1.

22U_0603_6.3V6M 22U_0603_6.3V6M
1
2
1
2

PC505 PC479
22U_0603_6.3V6M 22U_0603_6.3V6M
n
1
2

1
2

PC480
PC506 22U_0603_6.3V6M
22U_0603_6.3V6M
Deciphered Date
1
2

if 1
2

PC481
PC507 22U_0603_6.3V6M
22U_0603_6.3V6M
1
2

LC Future Center Secret Data

PC482
22U_0603_6.3V6M
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
+VCC_GT

1
2
1
2

PC508
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

22U_0603_6.3V6M PC483
22U_0603_6.3V6M
1
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

2
2

2014/12/31
1
2

PC509
d

22U_0603_6.3V6M PC484
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

22U_0603_6.3V6M
1
2
1
2

PC510
22U_0603_6.3V6M PC485
22U_0603_6.3V6M
1
2
e

PC511
B
1
2

22U_0603_6.3V6M
PC486
Size

Date:
1
2

22U_0603_6.3V6M
Title

PC512
1
2

22U_0603_6.3V6M
PC487
22U_0603_6.3V6M
n

Document Number
it

Wednesday, August 05, 2015

PROCESSOR DECOUPLING

1
1

Sheet
a

78
l

of
AIVL2_NM-A351
83
Rev
1.0
A
B
C
D
 5 4 3 2 1

ISL62771 Schematic for FT3 solution PL601DIS_EMC@

MURATA BLM18KG300TN1D
+5VALW +5VALW

l
1 2
+VGA_B+
DIS_EMC@

2
PL602
PR601 PR602 DIS_RF_NS@ DIS_EMC@ DIS_EMC@ MURATA BLM18KG300TN1D B+
PR603

2200P_0402_50V7K
0_0603_5% 0_0603_5%
@ 0_0402_5% 1 2
@ @

5
[6,14,24,33] VGA_ON 1 2

10U_0805_25V6K

10U_0805_25V6K
47P_0402_50V8-J

0.1U_0402_25V6
1

1
VDD_62771

PC602
a

PC603
1

1
PC606

PC611

PC607
PC601

2
1

1
+3VS_VGA 0.1U_0402_25V6 PC604 PC605 2
DIS@ 1U_0402_10V 1U_0402_10V VGA_UGATE1 4 PQ601

2
D TPCA8065-H D

i
2

2
DIS@

DIS@

DIS@
2
+VGA_CORE

25

26
@ PR604 DIS@ DIS@ DIS@ PL603

3
2
1
10K_0402_1% .24UH 20% PCME063T-R24MS1R145 35A

VDDP
VDD
t
VGA_PHASE1 1 2

1
PR605 8
@ 0_0402_5% ENABLE
1 2 PG_VDD 20 @ PR614 DIS@ PC612 DIS_EMC_NS@
[14,15,33] DGPU_PWROK
35 PGOOD 0_0603_5% 0.22U_0603_25V PQ602 PQ603 PR607 DIS@ DIS_EMC@

2
PGOOD_NB 21 1 2 1 2 TPCA8057-H TPCA8057-H 4.7_0603_5% PR608 3.65K_0402_1%

0.1U_0402_25V6
330U_D2_2VM_R9M

330U_D2_2VM_R9M
[24,25] PLT_RST_VGA# BOOT1

5
@ PR606 1 2 0_0402_5% 9 DIS@ @ VSUM+ 1 2 1 1
MESO@ PR644 0_0402_5% @ PR609 1 2 0_0402_5% 3 PWROK
[25] SVI2_SVC SVC

1
1 2 @ PR615 1 2 5 22 + +

PC613

PC614

PC615
0_0402_5%

n
+1.8VS_VGA [25] SVI2_SVD
@ PR611 1 2 0_0402_5% 7 SVD UGATE1 ISEN1 1 2
[25] SVI2_SVT

1
@ PR610 1 2 0_0402_5% 4 SVT
[25,66] GPU_VR_HOT# DIS_EMC_NS@

2
VR_HOT_L

2
1 2 6 23 4 4 PR616 10K_0402_1% 2 2
+3VS_VGA VDDIO PHASE1

1
PC616 DIS@

DIS@

DIS@
EXO@ PR612 0_0402_5% 1 2 PC609 DIS@ 680P_0402_50V

1
PR613 DIS@ 100P_0402_50V8-J 24 VGA_LGATE1 PC608

2
42.2K_0402_1% LGATE1 0.22U_0603_25V

3
2
1

3
2
1
DIS@ 1 2 1 2 19 @ PR620 DIS@ PC618 DIS@

e
+VGA_CORE PC617 PR617 COMP 0_0603_5% 0.22U_0603_25V7-K PR618 1_0402_1%
[26] VDDC_SEN 1
470P_0402_50V 2 1 2 PC610 DIS@ 30 1 2 1 2 VSUM- 1 2
DIS@ 499_0402_1% 1 2 150P_0402_50V8-J BOOT2 DIS@
1

@ PR619
2

PR622 1 2 32.4K_0402_1% 18 29
@ PR621 10_0402_1% PC620 FB UGATE2
1

0_0402_5% DIS@ DIS@ PR623 1 2 1 2 @ 680P_0402_50V7-K

PC619 DIS@ 845_0402_1% 28
2

330P_0402_50V7-K @ PR624 2.7K_0402_1% PHASE2 +VGA_B+

d
1

16
VSEN DIS_RF_NS@ DIS_EMC@ DIS_EMC@
1

27
PC621 LGATE2
330P_0402_50V7-K 17 DIS@ PU601
2
2

RTN

i
DIS@

2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
5
@ PR625 DIS@ PC622 ISL62771HRTZ_TQFN40_5X5
PR626 1000P_0402_25V7-K

47P_0402_50V8-J
0_0402_5% 1
2

1
PC623

PC625

DIS@ PC626

DIS@ PC627
10_0402_1% DIS@

PC624
1

36 31 VDD_62771

2
C COMP_NB BOOT_NB VGA_UGATE2 4 2

f
PQ604 C
[26] VDDC_RTN PR627 TPCA8065-H
@ 10K_0402_5% 32 PR628 DIS@
UGATE_NB 10K_0402_1%
1 2 37 DIS@

3
2
1
FB_NB 33 1 2 DIS@ PL604
PHASE_NB .24UH 20% PCME063T-R24MS1R145 35A +VGA_CORE
34 1 2 VGA_PHASE2 1 2
LGATE_NB

n
38
VSEN_NB PR629
10K_0402_1% PQ605 PQ606 DIS_EMC_NS@
DIS_EMC@

2
VGA_LGATE2 TPCA8057-H TPCA8057-H PR630 PR631 3.65K_0402_1%
DIS@

5
DIS@ @ 4.7_0603_5% VSUM+ DIS@ 1 2
VSUM+ 14 13 ISEN1

0.1U_0402_25V6
330U_D2_2VM_R9M

330U_D2_2VM_R9M
ISUMP ISEN1
1 1 +VGA_CORE
DIS@
PR633

12 ISEN2 ISEN2 1 2

1
ISEN2

1
15 + + TDC: 36A

DIS@ PC629

DIS@ PC630

PC631
PR632 10K_0402_1%
ISUMN
1

2
o
4 4 DIS@
DIS_EMC_NS@ OCP: 60A

1
DIS@
PR634

2
2 2
2.61K_0402_1%

PC632 PC628 Fsw: 300KHz

1
1

40 680P_0402_50V7K 0.22U_0603_25V

2
ISUMP_NB
PC633
DIS@

DIS@
PC634

@ PC635

DIS@
2

3
2
1

3
2
1
11K_0402_1%

DIS@
1

@ PR637

1 39 PR636 1_0402_1%
ISUMN_NB
1

2
PR635
DIS@

VSUM- 1 2
2

1
0.1U_0402_25V7K

PR638 100K_0402_1%
2
2

82N_0402_50V

330P_0402_50V

1 DIS@ 1 2
2

2 NTC_NB
@ PR639

CLOSE PL603 11
NTC
0_0402_5%

C
1

649_0402_1%

DIS@ PRT601 10
2

10K_0402_NTC IMON 2
1

IMON_NB
TP
100_0402_1%
2

41

1
DIS@
PR640

DIS@
PC636

DIS@
PR642

DIS@
PR641 27.4K_0402_1%
CLOSE PQ601
1

VSUM- DIS@ PRT602

2

470K_0402NEW_3%
2

100K_0402_1%

0.1U_0402_25V

130K_0402

2
PC637 DIS@
1

B B
0.1U_0402_25V6
1

BOTTOM PAD
CONNECT TO GND
Through 8 VIAs

C
PR643
DIS@
1
10.7K_0402_1%

C F
A

WWW.AliSaler.Com 5
L 4 3
Security Classification
Issued Date 2013/08/05
LC Future Center Secret Data

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2
Deciphered Date 2014/12/31
Title

Size
Custom

Date:
+VGA_CORE

Document Number

Wednesday, August 05, 2015

1
AIVL2_NM-A351
Sheet 79 of 83
Rev
1.0
A
 5 4 3 2 1

[66,81] EC_ON2
1
PR701
@ 0_0402_5%
2

it al D

n
0.1U_0402_6.3V7-K
1

2
PC701

2
0.1U_0402_16V7-K PR702

PC702
210K_0402_1% +3VS

e
1

2
@ PR704

2
PR703 100K_0402_1%

d
24

25

26

27

28

29
210K_0402_1%

1
REFIN2

GND2
REFIN

EN
RA
VREF
if
+V1.00AP

1
+5VALW VDDPALW _PW RGD
23
GSNS PGOOD
1
FSW=800KHz
C
PC703
22
VSNS LP#
2 @ PR705
0_0402_5%
TDC:10A C

@ PR706
0_0402_5%
2 1 21
SLEW MODE
3 1 2 OCP:16A
1 2 0.01U_0402_25V7-K20 4 @ PR707 PC704
TRIP NC 0_0603_5% 0.1U_0603_25V7K
BST_1.00VS

n
PC705 19 PU701 5 1 2 1 2 PL701
2.2U_0603_10V6-K GND1 BST 1UH_PCMC063T-1R0MN_+-20% +V1.00AP
1 2 18 TPS51367RVER SW1 6 SW _1.00VS 1 2 EMC@ EMC@
PJ701 V5
2 1 RF_NS@ EMC@ EMC@ VIN_1.00VS 17 7
B+ 2 1 VIN3 SW2

2
68P_0402_50V8J

10U_0805_25V6-K

10U_0805_25V6-K

2200P_0402_25V7-K

0.1U_0402_25V6

16 8

o
@ JUMP_43X79 PR708

2200P_0402_25V7-K
VIN2 SW3
1

1@ 4.7_0603_5%
PC706

PC707

PC708

PC709

PC710

22U_0805_6.3V6-M

22U_0805_6.3V6-M

22U_0805_6.3V6-M

22U_0805_6.3V6-M

0.1U_0402_25V6
PC714 15 9
VIN1 SW4 EMC_NS@

1
47P_0402_50V8-J

PC716

PC717
PGND5

PGND4

PGND3

PGND2

PGND1
1 1 1 1
2

PC711

PC712

PC713

PC715
2

2
2 2 2 2

14

13

12

11

10

1
PC718

C
680P_0402_50V7K
EMC_NS@

2
B B

F C Mode

GND

Float
Frequency

400KHz

800KHz
+V1.00AP
2

2
PJ702
2
@ JUMP_43X118

PJ703
2
@ JUMP_43X118
1

1
1

1
+1VALW

L C Security Classification
Issued Date 2013/08/01
LC Future Center Secret Data
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
2014/08/01
Title
+V1.00A

Size Document Number

Custom
AIVL2_NM-A351
Rev
1.0
A

Date: Wednesday, August 05, 2015 Sheet 80 of 83

5 4 3 2 1
 5 4 3 2 1

i a l D

n t
e
PL801

4
PJ801 1UH_PH041H-1R0MS_20%
2 1 VIN_+1.8VSP 10 1 1.8VSP_LX 1 2
+5VALW

PG
d
2 1 PVIN2 LX1 +1.8VSP

2
9 2
@ JUMP_43X39 PVIN1 LX2

1
PR803

i
C C

1
PC801 PC802 8 3 4.7_0603_5%
10U_0603_10V 10U_0603_10V SVIN1 LX3 EMC_NS@ PR804 PC805
EMC@

2
PU801 20K_0402_1% 22P_0402_50V

2 1

22U_0805_6.3VAM

22U_0805_6.3VAM

0.1U_0402_25V6
RT8068AZQW

1
5 6 PC804
20141226

GND
EN FB

PC806

PC807

PC808
PR801

NC
[66,80] EC_ON2 @ 0_0402_5% EMC_NS@ 680P_0402_50V

2
1 2 EN_1.8VSP

11

7
+1.8VALW

n
TDC: 1A

2
1 2

1
Fsw: 1MHz

1
@ PR802 @ PC803
@ PD801 1M_0402_5% 0.22U_0402_10V6-K

2
RB751V-40 PR805

o
10K_0402_1%

2
C
B B

PJ802
+1.8VSP 2 1 +1.8VALW
2 1

C
@ JUMP_43X39

C F Security Classification
Issued Date 2013/08/05
LC Future Center Secret Data
Deciphered Date 2014/12/31
Title
+1.8VS_VGA
A

L
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AIVE1_NM-A211
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 81 of 83
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

HW PIR (Product Improve Record)

AIVE1 NM-AXXX SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.1
GERBER-OUT DATE: 2013/10/15

l
NO DATE PAGE MODIFICATION LIST PURPOSE
---------------------------------------------------------------------------------------------------------------------

a
D D

n it
C

if d e C

o n
B

C B

F C
A

L C Security Classification
Issued Date 2013/09/07
LC Future Center Secret Data
Deciphered Date 2014/09/07
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Title

Size
C
XXXX
Document Number
AITE1_NM-A221
Rev
1.0
A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, August 05, 2015 Sheet 83 of 84
5 4 3 2 1
 5 4 3 2 1

l
B+ +5VLP/ 100mA
Power Line SILERGY Richtek
MOSFET SYX198CQNC RT8068A
+5VALW/8A 1.8VALW/1A

a
Adapter PWM FOR 1.8VALW
D
FOR SYSTEM EC_ON2 EN D

i
EC_ON EN PGOOD +5V_PWRGD

t
SILERGY +3VLP/ 100mA
SYX198BQNC
PWM
+3VALW/8A

n
FOR SYSTEM
EC_ON EN PGOOD +3V_PWRGD

e
TI
BQ24780SRUYR Richtek +1.35VP/11A

Battery Charger RT8231A

d
SYSON S5 +0.675VSP/1.5A
FOR DDR3L
Switch Mode SUSP# S3

i
C C

f
Batt. Discharge NCP81253 VCORE/TDC 21A/EDC 28A
ON
MOSFET
SMBus
NCP81208 NCP81151 VCCGT/TDC 18A/EDC 31A
APUPWR_EN EN

n
FOR SKL U22 CPU
NCP81253 VCCSA/TDC 4A/EDC 5A

Main Battery

o
Li-ion
Intersil
ISL62771HRTZ
TQFN40_5X5 +VGA_CORE TDC 36A /EDC 55A

C
SVI2 VIDs
Switch Mode
IGPUPWR_EN EN FOR GPU VDDC

B B

TI V1.00A/10A
TPS51367

C
FOR V1.00A
S5_EN EN PGOOD

C F
L
A A

Security Classification LC Future Center Secret Data Title

Issued Date Block Diagram

Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AIVL2_NM-A351
Date: Wednesday, August 05, 2015 Sheet 84 of 84

WWW.AliSaler.Com
5 4 3 2 1