Stm32h563 MCU DataSheet

STM32H562xx and STM32H563xx
Arm® Cortex®-M33 32-bit MCU+TrusZone® + FPU, 375 DMIPS

250 MHz, 2-Mbyte flash, 640 Kbytes RAM, Math accelerators
Datasheet - production data
Features
Includes ST state-of-the-art patented technology
Core LQFP64 (10 x 10 mm) VFQFPN68 (8 x 8 mm)

LQFP100 14 x 14 mm)
® ® ®
• Arm Cortex -M33 CPU with TrustZone , LQFP144 (20 x 20 mm)
FPU, frequency up to 250 MHz, MPU, 375 LQFP176 (24 x 24 mm)
UFBGA
DMIPS (Dhrystone 2.1)
UFBGA169 (7 x 7 mm)
ART Accelerator UFBGA 176+25 (10 x 10 mm)
• 8-Kbyte instruction cache allowing WLCSP80 (3.50 X 3.27 mm)
0-wait-state execution from flash and external
memories
Clock management
• 4-Kbyte data cache for external memories
• Internal oscillators: 64 MHz HSI, 48 MHz
Benchmarks HSI48, 4 MHz CSI, 32 kHz LSI
• 1.5 DMIPS/MHz (Drystone 2.1) External oscillators: 4-50 MHz HSE, 32.768 kHz
LSE
• 1023 CoreMark® (4.092 CoreMark®/MHz)
Memories General-purpose inputs/outputs

• Up to 139 fast I/Os with interrupt capability
• Up to 2 Mbytes of embedded flash memory
(most 5 V tolerant)
with ECC, 2 banks read-while-write
• Up to 10 I/Os with independent supply down to
• Up to 48-Kbyte per bank with high-cycling
1.08 V
capability (100 K cycles) for DATA flash
• 2-Kbyte OTP (one-time programmable) Low-power consumption
• 640 Kbytes of SRAM (64-Kbyte SRAM2 with • Sleep, Stop and Standby modes
ECC and 320-Kbyte SRAM3 with flexible ECC)
• VBAT supply for RTC, 32x 32-bit backup
• 4 Kbytes of backup SRAM available in the registers
lowest power modes
• Flexible external memory controller with up to Security
16-bit data bus: SRAM, PSRAM, FRAM,
• Arm® TrustZone® with Armv8-M mainline
SDRAM/LPSDR SDRAM, NOR/NAND
security extension
memories
• Up to eight configurable SAU regions
• One Octo-SPI memory interface with support
for serial PSRAM/NAND/NOR, Hyper • TrustZone® aware and securable peripherals
RAM/flash frame formats • Flexible life-cycle scheme with secure debug
• Two SD/SDIO/MMC interfaces authentication
• SFI (secure firmware installation)
March 2023 DS14258 Rev 1 1/275

This is information on a product in full production. www.st.com
• Secure firmware upgrade support with • One I3C interface

TF-M • Up to 12 U(S)ARTS (ISO7816 interface, LIN,
• HASH hardware accelerator IrDA, modem control) and 1x LP UART
• True random number generator, NIST • Up to six SPIs including three muxed with
SP800-90B compliant full-duplex I2S for audio class accuracy via
• 96-bit unique ID internal audio PLL or external clock and up to
five additional SPI from five USART when
• Active tampers configured in Synchronous mode (one
additional SPI with OctoSPI)
Two DMA controllers to offload the CPU
• Two SAI
• Two dual-port DMAs with FIFO
• Two FD-CAN
Mathematical acceleration • One 8- to 14- bit camera interface
• CORDIC for trigonometric functions • One 16-bit parallel slave synchronous-
acceleration interface
• FMAC (filter mathematical accelerator) • One HDMI-CEC
• One Ethernel MAC interface with DMA
Reset and supply management controller
• 1.71 V to 3.6 V application supply and I/O • One USB 2.0 full-speed host and device
• POR, PDR, PVD and BOR • One USB Type-C®/ USB power-delivery r3.1
• Embedded regulator (LDO) or SMPS step-
down converter regulator with configurable Analog
scalable output to supply the digital circuitry • Two 12-bit ADC with up to 5 MSPS in 12-bit
• Two 12-bit D/A converters
Up to 24 timers
• 18x 16-bit (including x6 low-power 16-bit timer Digital temperature sensor
available is Stop mode)
• Two 32-bit timers with up to four IC/OC/PWM Debug
or pulse counter and quadrature (incremental) • Authenticated debug and flexible device life
encoder input cycle
• Two watchdogs • Serial wire-debug (SWD), JTAG, Embedded
• Two SysTick timer Trace Microcell™ (ETM)
Up to 34x communication interfaces ECOPACK2 compliant packages

• Up to four I2C FM+ interfaces (SMBus/PMBus)
Table 1. Device summary
Reference Part numbers
STM32H562AG, STM32H562AI, STM32H562IG, STM32H562II, STM32H562RG,

STM32H562xx
STM32H562RI, STM32H562VG, STM32H562VI, STM32H562ZG, STM32H562ZI
STM32H563AG, STM32H563AI, STM32H563IG, STM32H563II, STM32H563MI,

STM32H563xx STM32H563RG, STM32H563RI, STM32H563VG, STM32H563VI, STM32H563ZG,
STM32H563ZI
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STM32H562xx and STM32H563xx Contents
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1 Arm Cortex-M33 core with TrustZone and FPU . . . . . . . . . . . . . . . . . . . . 19
3.2 ART Accelerator (ICACHE and DCACHE) . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.1 Instruction cache (ICACHE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.2 Data cache (DCACHE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4 Embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4.1 FLASH security and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.4.2 FLASH privilege protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.5 Embedded SRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.5.1 SRAMs TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.5.2 SRAMs privilege protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.6 Security overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.7 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.7.1 STM32H562/H563boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.8 Global TrustZone controller (GTZC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.9 TrustZone security architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.9.1 TrustZone peripheral classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.9.2 Default TrustZone security state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.10 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.10.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.10.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.10.3 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.10.4 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.10.5 PWR TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.11 Peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.12 Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.12.1 RCC TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.13 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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Contents STM32H562xx and STM32H563xx
3.14 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.14.1 GPIOs TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.15 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.16 General purpose direct memory access controller (GPDMA) . . . . . . . . . 35
3.17 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.17.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 37
3.17.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 38
3.18 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 38
3.19 CORDIC co-processor (CORDIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.20 Filter math accelerator (FMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.21 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.21.1 LCD parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.21.2 FMC TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.22 Octo-SPI interface (OCTOSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.22.1 OCTOSPI TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.23 Delay block (DLYB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.24 Analog-to-digital converter (ADC1 and ADC2) . . . . . . . . . . . . . . . . . . . . . 42
3.24.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.24.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.24.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.25 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.26 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.27 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.28 Parallel synchronous slave interface (PSSI) . . . . . . . . . . . . . . . . . . . . . . 44
3.29 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.30 HASH hardware accelerator (HASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.31 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.31.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.31.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16,
TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.31.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.31.4 Low-power timers
(LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPTIM6) . . . . . . . . . . . . 48
3.31.5 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.31.6 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.31.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
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3.32 Real-time clock (RTC), tamper and backup registers . . . . . . . . . . . . . . . 50

3.32.1 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.32.2 Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.33 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.34 Improved inter-integrated circuit (I3C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.35 Universal synchronous/asynchronous receiver transmitter (USART/UART)
and low-power universal asynchronous receiver transmitter (LPUART) . 54
3.35.1 Universal synchronous/asynchronous receiver transmitter
(USART/UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.35.2 Low-power universal asynchronous receiver transmitter (LPUART) . . . 56
3.36 Serial peripheral interface (SPI) / inter-integrated sound interfaces (I2S) 57
3.37 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.38 Secure digital input/output and MultiMediaCards interface (SDMMC) . . . 60
3.39 Controller area network (FDCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.40 USB full speed (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.41 USB Type-C /USB Power Delivery controller (UCPD) . . . . . . . . . . . . . . . 62
3.42 Ethernet MAC interface with dedicated DMA controller (ETH) . . . . . . . . . 63
3.43 High-definition multimedia interface (HDMI)
- consumer electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.44 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.44.1 Serial-wire/JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.44.2 Embedded Trace Macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4 Pinout, pin description and alternate function . . . . . . . . . . . . . . . . . . . 65

4.1 Pinout/ballout schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
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Contents STM32H562xx and STM32H563xx
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

5.3 Operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
5.3.2 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
5.3.3 SMPS step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
5.3.4 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 137
5.3.5 Embedded reset and power control block characteristics . . . . . . . . . . 138
5.3.6 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
5.3.7 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
5.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 152
5.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 158
5.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
5.3.11 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
5.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
5.3.13 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 166
5.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
5.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
5.3.16 Extended interrupt and event controller input (EXTI) characteristics . . 180
5.3.17 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
5.3.18 Octo-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
5.3.19 Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
5.3.20 DCMI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
5.3.21 PSSI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
5.3.22 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
5.3.23 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
5.3.24 Analog temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . 222
5.3.25 Digital temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . 222
5.3.26 VCORE monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
5.3.27 Temperature and VBAT monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
5.3.28 Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
5.3.29 VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
5.3.30 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
5.3.31 Low-power timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
5.3.32 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

6.1 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
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6.2 VFQFPN68 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

6.3 WLCSP80 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
6.4 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
6.6 UFBGA169 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
6.8 UFBGA(176+25) package information . . . . . . . . . . . . . . . . . . . . . . . . . . 267
6.9 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
6.9.1 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
8 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
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List of tables STM32H562xx and STM32H563xx
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2. STM32H56xxx features and peripheral counts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3. STM32H562/H563 / Boot mode when TrustZone is disabled (TZEN=0xC3) . . . . . . . . . . . 24
Table 4. STM32H562/H563 / Boot mode when TrustZone is enabled (TZEN=0xB4) . . . . . . . . . . . 25
Table 5. ADC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 6. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 7. I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 8. I3C peripheral controller/target features versus MIPI v1.1 . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 9. USART, UART and LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 10. SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 11. SAI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 12. SDMMC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 13. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 14. STM32H562xx and STM32H563xx pin/ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 15. Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 16. Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 17. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 18. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 19. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 20. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 21. Maximum allowed clock frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 22. Supply voltage and maximum frequency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 23. Characteristics of SMPS step-down converter external components . . . . . . . . . . . . . . . . 134
Table 24. Operating conditions at power-up/power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 137
Table 25. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 26. Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 27. Internal reference voltage calibration value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 28. Typical and maximum current consumption in run mode, code with data processing
running from flash memory, 2-ways instruction cache ON, PREFETCH ON . . . . . . . . . . 141
running from flash memory, 1-way instruction cache ON, PREFETCH ON . . . . . . . . . . . 142
running from SRAM with cache 1-WAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
running from SRAM with cache 2-WAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 32. Typical consumption in run mode with CoreMark running
from flash memory and SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 33. Typical consumption in run mode with SecureMark running from
flash memory and SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 34. Typical and maximum current consumption in sleep mode . . . . . . . . . . . . . . . . . . . . . . . 145
Table 35. Typical and maximum current consumption in stop mode . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 36. Typical and maximum current consumption in standby mode . . . . . . . . . . . . . . . . . . . . . 146
Table 37. Typical and maximum current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . 147
Table 38. Peripheral current consumption in sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 39. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 40. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 41. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 42. 4-50 MHz HSE oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
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Table 43. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Table 44. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 45. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 46. CSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 47. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 48. PLL characteristics (wide VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 49. PLL characteristics (medium VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 50. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 51. Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 52. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 53. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 54. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 55. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 56. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 57. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 58. Output voltage characteristics for all I/Os except PC13, PC14, PC15, and PI8 . . . . . . . . 169
Table 59. Output voltage characteristics for PC13 and PI8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 60. Output voltage characteristics for PC14 and PC15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 61. Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 62. Output timing characteristics (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 63. Output timing characteristics VDDIO2 1.2 V range (HSLV OFF) . . . . . . . . . . . . . . . . . . . 176
Table 64. Output timing characteristics VDDIO2 1.2 V (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 65. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 66. EXTI input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 67. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 182
Table 68. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 182
Table 69. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 184
Table 70. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 184
Table 71. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 72. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 186
Table 73. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 74. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 187
Table 75. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 76. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 77. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 78. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Table 79. Switching characteristics for NAND flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 80. Switching characteristics for NAND flash write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 81. SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 82. LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 83. SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Table 84. LPSDR SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Table 85. OCTOSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Table 86. OCTOSPI characteristics in DTR mode (no DQS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 87. OCTOSPI characteristics in DTR mode (with DQS)/ hyperbus . . . . . . . . . . . . . . . . . . . . 203
Table 88. Delay block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 89. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 90. PSSI transmit characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 91. PSSI receive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Table 92. 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Table 93. Minimum sampling time versus RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 94. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
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10
List of tables STM32H562xx and STM32H563xx
Table 95. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Table 96. DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Table 97. Analog temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Table 98. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Table 99. Digital temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Table 100. VCORE monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Table 101. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Table 102. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Table 103. Temperature monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Table 104. Voltage booster for analog switch characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Table 105. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Table 106. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Table 107. LPTIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Table 108. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Table 109. USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Table 110. I3C open-drain measured timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Table 111. I3C push-pull measured timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Table 112. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Table 113. I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Table 114. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Table 115. Dynamics characteristics: SD / MMC characteristics,
VDD = 2.7 to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Table 116. Dynamics characteristics: eMMC characteristics
VDD = 1.71V to 1.9V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Table 117. Dynamics characteristics: Ethernet MAC signals for SMI . . . . . . . . . . . . . . . . . . . . . . . . 240
Table 118. Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 241
Table 119. Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 241
Table 120. Dynamics JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Table 121. Dynamics SWD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Table 122. LQFP64 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Table 123. VFQFPN68 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Table 124. WLCSP80 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Table 125. WLCSP80 - Example of PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Table 126. LQFP100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Table 128. UFBGA169 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Table 129. UFBGA169 - Example of PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . 262
Table 131. UFBGA(176+25) - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Table 132. UFBGA(176+25) - Example of PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 268
Table 133. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Table 134. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
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STM32H562xx and STM32H563xx List of figures
List of figures
Figure 1. STM32H562xx and STM32H563xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 2. STM32H562xx and STM32H563xx power supply overview (with SMPS) . . . . . . . . . . . . . 29
Figure 3. STM32H562xx and STM32H563xx power supply overview (with LDO). . . . . . . . . . . . . . . 30
Figure 4. Power-up /down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 5. LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 6. VFQFPN68 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 7. WLCSP80 SMPS ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 8. LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 9. LQFP100 SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 12. UFBGA169 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 13. UFBGA169 SMPS ballout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 16. UFBGA176+25 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 17. UFBGA176+25 SMPS ballout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 18. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 19. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 20. STM32H563 power supply scheme with SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 21. STM32H562/H563 power supply scheme with LDO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 22. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 23. SMPS efficiency versus load current in run, sleep and stop mode
with SVOS3 mode, TJ = 30 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 24. SMPS efficiency versus load current in Run, Sleep and Stop mode
with SVOS3 mode, TJ = 130 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 25. SMPS efficiency versus load current in stop SVOV4, SVOS5, TJ = 30 °C. . . . . . . . . . . . 136
Figure 26. SMPS efficiency versus load current in stop SVOV4, SVOS5, TJ = 130 °C. . . . . . . . . . . 136
Figure 27. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 28. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 29. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 30. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Figure 31. VIL/VIH for all I/Os except BOOT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 32. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 33. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 181
Figure 34. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 183
Figure 35. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 185
Figure 36. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 37. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 38. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 192
Figure 39. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Figure 40. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 41. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 42. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 196
Figure 43. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 196
Figure 44. SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 45. SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 46. OCTOSPI SDR read/write timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
DS14258 Rev 1 11/275

12
List of figures STM32H562xx and STM32H563xx
Figure 47. OCTOSPI timing diagram - DTR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Figure 48. OCTOSPI hyperbus clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 49. OCTOSPI hyperbus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 50. OCTOSPI hyperbus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 51. DCMI timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Figure 52. PSSI transmit timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Figure 53. vPSSI receive timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Figure 54. ADC conversion timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Figure 55. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Figure 56. Typical connection diagram when using the ADC with FT/TT pins
featuring analog switch function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Figure 57. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 217
Figure 58. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 217
Figure 59. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Figure 60. USART timing diagram in Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Figure 61. USART timing diagram in Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Figure 62. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Figure 63. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Figure 64. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Figure 65. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Figure 66. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Figure 67. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Figure 68. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Figure 69. SDIO high-speed/eMMC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Figure 70. SD default speed timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Figure 71. DDR mode timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Figure 72. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Figure 73. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Figure 74. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Figure 75. JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Figure 76. SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Figure 77. LQFP64 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Figure 78. LQFP64 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Figure 79. VFQFPN68 - Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Figure 80. VFQFPN68 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Figure 81. WLCSP80 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Figure 82. WLCSP80 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Figure 83. LQFP100 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Figure 84. LQFP100 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Figure 87. UFBGA169 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Figure 88. UFBGA169 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Figure 91. UFBGA(176+25) - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Figure 92. UFBGA(176+25) - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
12/275 DS14258 Rev 1

STM32H562xx and STM32H563xx Introduction
1 Introduction
This document provides the ordering information and mechanical device characteristics of
the STM32H562xx and STM32H563xx microcontrollers.
For information on the device errata with respect to the datasheet and reference manual,
refer to the STM32H562xx and STM32H563xx errata sheet.
For information on the Arm®(a) Cortex®-M33 core, refer to the Cortex®-M33

Technical Reference Manual, available from the www.arm.com website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
DS14258 Rev 1 13/275

13
Description STM32H562xx and STM32H563xx
2 Description
The STM32H562xx and STM32H563xx devices are a high-performance microcontrollers

family (STM32H5 Series) based on the high-performance Arm® Cortex®-M33 32-bit RISC
core. They operate at a frequency of up to 250 MHz.
The Cortex®-M33 core features a single-precision floating-point unit (FPU), that supports all
the Arm® single-precision data-processing instructions and all the data types.
The Cortex®-M33 core also implements a full set of DSP (digital signal processing)
instructions and a memory protection unit (MPU) that enhances the application security.
The devices embed high-speed memories (2 Mbytes of dual bank flash memory and 640
Kbytes of SRAM), a flexible external memory controller (FMC) (for devices with packages of
100 pins and more), one Octo-SPI memory interface (at least one Quad-SPI available on all
packages) and an extensive range of enhanced I/Os and peripherals connected to three
APB buses, three AHB buses and a 32-bit multi-AHB bus matrix.
The devices offer security foundation compliant with the trusted-based security architecture
(TBSA) requirements from Arm®. It embeds features to implement a secure firmware
update. Besides these capabilities, the devices incorporate a secure firmware installation
feature, that allows the customer to secure the provisioning of the code during its
production. A flexible life cycle is managed thanks to multiple levels of protection and secure
debug authentication. Firmware hardware isolation is supported thanks to securable
peripherals, memories and I/Os, and privilege configuration of peripherals and memories.
The devices feature several protection mechanisms for embedded flash memory and
SRAM: readout protection, write protection, secure and hide protection areas.
The devices embed several peripherals reinforcing security: a HASH hardware accelerator,
and a true random number generator
The devices offer active tamper detection and protection against transient and
environmental perturbation attacks, thanks to several internal monitoring generating secret
data erase in case of attack. This helps to fit the PCI requirements for point of sales
applications.
The devices offer two fast 12-bit ADC, two DAC channels, an internal voltage reference
buffer, a low-power RTC, two 32-bit general-purpose timers, two 16-bit PWM timers
dedicated to motor control, eight 16-bit general-purpose timers, two 16-bit basic timers and
six 16-bit low-power timers.
The devices also feature standard and advanced communication interfaces such as: four
I2Cs, one I3C, six SPIs, three I2Ss, six USARTs, six UARTs and one low-power UART, two
SAIs, one digital camera interface (DCMI), up to two SDMMC, up to two FDCAN, one USB
full-speed, one USB Type-C™ /USB Power Delivery controller, an Ethernet interface
(available only on STM32H563xx device).
The devices operate in the - 40 to + 85 °C (+ 130 °C junction) and - 40 to + 125 °C (+ 130 °C
junction) temperature ranges from a 1.71 to 3.6 V power supply.
A comprehensive set of power-saving modes allow the design of low-power applications.
Some independent power supplies are supported like an analog independent supply input
for ADC, DACs, a 3.3 V dedicated supply input for USB and a dedicated supply input for
some GPIOs and SDMMC. A VBAT input is available for connecting a backup battery in
14/275 DS14258 Rev 1

STM32H562xx and STM32H563xx Description
order to preserve the RTC functionality and to backup 32x 32-bit registers and
4-Kbyte SRAM.
The devices offer eight packages from 64-pin to 176-pin.
All packages are available with two options LDO or SMPS supply for the VCORE (except for
LQFP64 and VFQFPN68 packages which are not available in SMPS and WLCSP80 which
is not available in LDO).
Table 2. STM32H56xxx features and peripheral counts

STM32H563RI/G
STM32H562RI/G
STM32H563AI/G
STM32H562AI/G
STM32H563VI/G
STM32H562VI/G
STM32H563ZI/G
STM32H562ZI/G
STM32H563II/G
STM32H562II/G
STM32H563MI
Peripherals
Flash memory (Mbytes) Up to 2 Mbytes

System
640 (256+64+320)
(Kbytes)
SRAM
Backup
4 Kbytes
(bytes)
Flexible memory controller for
No yes(1) yes(2) yes
external memories (FMC)
OCTOSPI 1
Advanced
2 (16 bits)
control
General
2 (32 bits) and 8 (16 bits)
purpose
Basic 2 (16 bits)
Timers Low power 6 (16 bits)
SysTick timer 2
Watchdog
timers
2
(independent,
window)
DS14258 Rev 1 15/275

18
Table 2. STM32H56xxx features and peripheral counts (continued)
STM32H563RI/G
STM32H562RI/G
STM32H563AI/G
STM32H562AI/G
STM32H563VI/G
STM32H562VI/G
STM32H563ZI/G
STM32H562ZI/G
STM32H563II/G
STM32H562II/G
STM32H563MI
Peripherals
SPI / I2S 4/3 5/3 6/3

I2C 4
I3C 1(3)
USART 5 6
UART 5 6
LPUART 1
SAI 2
FDCAN 2 1 2 1 2 1 2 1 2 1
Communication USB yes

interfaces UCPD yes
SDMMC 1 2 1 2 1 2 1 2 1
Digital
camera
interface yes
(DCMI) /
PSSI(4)
Ethernet
Yes/ NA/ Yes / Yes/ Yes/ Yes
(Legacy / No No No No No
NA Yes No No Yes /Yes
SMPS)
HDMI-CEC Yes
CORDIC co-processor Yes
Filter mathematical accelerator
Yes
(FMAC)
Real time clock (RTC) Yes
Tamper pins (legacy/SMPS) 5 / NA NA / 5 8/8
Active tampers
4 / NA NA / 4 7/7
(legacy/SMPS)(5)
True random number generator Yes
HASH (SHA-512) Yes
80/ 80/ 112/ 112/ 136/ 136/ 140(7) 140
GPIOs (legacy/SMPS) 53 / NA(6) NA / 57 (7)
78 NA 110 NA 134 NA /139
7/ 7/ 8/ 8/
Wakeup pins (legacy/SMPS) 6 / NA(8) NA / 6 7/7 7/7 8/8 8/8
NA NA NA NA
Number of I/Os down to 1.08 V 0/ 10/ 10/ 10/ 10/

0 / NA NA / 0 0/0 10/7 10/7
(legacy/SMPS) NA 10 NA NA NA
16/275 DS14258 Rev 1

STM32H562xx and STM32H563xx Description
Table 2. STM32H56xxx features and peripheral counts (continued)
STM32H563RI/G
STM32H562RI/G
STM32H563AI/G
STM32H562AI/G
STM32H563VI/G
STM32H562VI/G
STM32H563ZI/G
STM32H562ZI/G
STM32H563II/G
STM32H562II/G
STM32H563MI
Peripherals
12-bit ADC 2
Number of
ADC channels 16/ 16/ 20/ 20/ 20/ 20/ 20/ 20/
16/NA NA / 16
(legacy/SMP 14 NA 18 NA 20 NA 20 NA
S)
12-bit DAC
1
controller
DAC Number of
12-bit Dto-A 2
converters
Internal voltage reference
No YES
buffer
Maximum CPU frequency 250 MHz
Operating voltage 1.71 to 3.6 V
Ambient operating temperature: – 40 to 85 °C / – 40 to 125 °C
Operating temperature
Junction temperature: – 40 to 130 °C
LQFP64 LQFP176
Package WLCSP80 LQFP100 LQFP144 UFBGA169
VFQFPN68 UFBGA176
1. 8-bit to interface LCD controller.
2. For the LQFP100 package, only FMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory
using the NE1 chip select.
3. Shares the same IOs than I2C4.
4. DCMI and PSSI cannot be used at the same time as they share the same circuitry.
5. Active tampers in output sharing mode (one output shared by all inputs).
6. 49 for LQFP64.
7. 136 for LQFP176.
8. 5 for VFQFPN68.
DS14258 Rev 1 17/275

18
Figure 1. STM32H562xx and STM32H563xx block diagram

CLK, NE[4:1], NL, NBL[1:0],
NJTRST, JTDI, JTCK/SWCLK, JTAG/ SW MPU A[25:0], D[15:0], NOE,
JTMS/SWDIO, JTDO NWE, NWAIT, NCE, INT,
ETM NVIC SDCLK,SDCLKE[1:0],
Flexible memory controller (FMC): SDNE[1:0], SDNWE,
(8 Kbytes)
TRACECLK, SDRAM, SRAM, PSRAM, NOR Flash, FRAM, NAND Flash
ICACHE
NRAS, NCAS, as AF
TRACED[3:0] Arm Cortex-M33
250 MHz IO[7:0], CLK, NCLK,
C-BUS OCTOSPI1 memory interface NCS. DQS as AF
TrustZone FPU
S-BUS
(4 Kbytes)
DCACHE
AHB bus-matrix
Flash memory RNG
(up to 2 Mbytes)
HASH
D[7:0], D[3:1]dir
FIFO
CMD, CMDdir,CK, CKin SDMMC1 SRAM1 (256 Kbytes)
@VDDA
D0dir, D2dir DAC1_OUT1
SRAM2 (64 Kbytes)
FIFO
ITF DAC1
SDMMC2
SRAM3 (320 Kbytes) DAC1_OUT2
FIFO
MAC ETHERNET
DCMI/PSSI D[15:0], CK, CMD as AF
AHB2 250 MHz

SRAM
4KB
GPDMA1
@VDD
VDD Power management
@VDD
GPDMA2
Voltage regulator LDO or VDD = 1.71 to 3.6 V
HSI48 SMPS 3.3 to 1.2 V VSS
HS64 @VDD
Reset Supply supervision
CSI BOR
@VBAT Int
VDDIO, VDDUSB, VDDA,
LSI PVD, PVM VSSA, VDD, VSS, NRST
PA[15:0] GPIO port A BKPSRAM
(4 Kbytes) @VDD
PB[15:0] GPIO port B PLL 1, 2, 3
AHB1 250 MHz
AHB3 250 MHz

XTAL OSC OSC_IN
PC[15:0] GPIO port C
4- 50 MHz OSC_OUT
PD[15:0] GPIO port D
IWDG
RAMCFG
PE[15:0] GPIO port E
Reset and clock control
PF[15:0] GPIO port F GTZC1 Standby
interface WKUPx (x=1 to 8)
PG[15:0] GPIO port G
CRC
FCLK
HCLKx
PCLKx
PH[15:0] GPIO port H TIM2 32b 4 channels, ETR as AF
PI[7:0] GPIO port I CORDIC TIM3 32b 4 channels, ETR as AF

16 AF EXT IT. WKP
FMAC TIM4 32b 4 channels, ETR as AF
@VDDA CRS
20xIN ADC1 ITF SRAM
TIM5 32b 4 channels, ETR as AF
ADC2 512KB EXTI
3 compl. channels smcard RX, TX, CK, CTS,

(TIM1_CH[1:3]N), AHB/APB2 AHB/APB1 USART2 irDA RTS as AF
TIM1/PWM 16b
6 channels (TIM1_CH[1:4]), smcard RX, TX, CK, CTS,
APB1 250 MHz (max)

ETR, BKIN, BKIN2 as AF USART3 irDA RTS as AF
3 compl. channels UART4 RX, TX, CTS, RTS as AF

(TIM1_CH[1:3]N), TIM8/PWM 16b
6 channels (TIM1_CH[1:4]),
ETR, BKIN, BKIN2 as AF UART5 RX, TX, CTS, RTS as AF
2 channels, TIM15 16b smcard RX, TX, CK, CTS,

APB2 250 MHz
1 compl. channel, BKIN as AF USART6 irDA RTS as AF
1 channel, MOSI, MISO, SCK,

TIM16 16b SPI2/I2S2
1 compl. channel, BKIN as AF NSS as AF
MOSI, MISO, SCK,
1 channel, TIM17 16b SPI3/I2S3
NSS as AF
1 compl. channel, BKIN as AF
smcard DTS I2C1/SMBUS SCL, SDA, SMBA as AF
RX, TX, CK,CTS, RTS as AF USART1
irDA
WWDG I2C2/SMBUS SCL, SDA, SMBA as AF
MOSI, MISO, SCK, SPI1/I2S1
NSS as AF
IWDG TX, RX as AF
MOSI, MISO, SCK, FDCAN1
FIFO
SPI4
NSS as AF
FDCAN2 TX, RX as AF
TIM6 16b
MOSI, MISO, SCK, SPI6
NSS as AF CC1, DBCC1, CC2,
PHY
TIM7 16b UCPD1 DBCC2, FRSCC1,

MCLK_A, SD_A, FS_A,
SCK_A, MCLK_B, SD_B, FRSCC2 as AF
SAI1
FS_B, SCK_B as AF
IN1, IN2, CH1, CH2,
LPTIM2
AUDIOCLK as AF ETR as AF
MCLK_A, SD_A, FS_A, SAI2

TIM12 16b 2 channels, ETR as AF
SCK_A, MCLK_B, SD_B,
FS_B, SCK_B as AF @VDDUSB
TIM13 16b 1 channel, ETR as AF
FIFO
PHY
DP USB FS
DM AHB/APB3 TIM14 16b 1 channel, ETR as AF
Temperature
AHB3 250 MHz
UART7 RX, TX, CTS, RTS as AF

monitoring
@VBAT
RTC_OUT1, RTC_OUT2, XTAL 32k
RTC_REFIN, RTC_TS
RTC
RTC_OUT[8:1],
TAMP
RTC_IN[8:1]
smcard RX, TX, CK, CTS,
@VDDA USART10irDA RTS as AF
VREF+
VREF buffer smcard RX, TX, CK, CTS,
USART11 irDA
APB3 250 MHz
IN1, IN2, CH1, CH2, RTS as AF

LPTIM1
ETR as AF
SCL, SDA, SMBA as AF I2C3/SMBUS

HDMI-CEC CEC
SCL, SDA, SMBA as AF I2C4/SMBUS

I3C1 SCL, SDA
RX, TX, CTS, RTS_DE as
LPUART1
AF
MOSI, MISO, SCK, SPI5
NSS as AF
SBS
IN1, IN2, CH1, CH2,

LPTIM3
ETR as AF
IN1, ETR as AF LPTIM4
IN1, IN2, CH1, CH2,

LPTIM5
ETR as AF
IN1, IN2, CH1, CH2, VDD power VDDUSB power VBAT power VDDA power
LPTIM6 domain domain domain domain
ETR as AF
MSv67308V5
Note: PC[15:13] are in the VBAT domain.
18/275 DS14258 Rev 1

STM32H562xx and STM32H563xx Functional overview
3 Functional overview
3.1 Arm Cortex-M33 core with TrustZone and FPU

The Cortex-M33 with TrustZone and FPU is a highly energy-efficient processor designed for
microcontrollers and deeply embedded applications, especially those requiring efficient
security.
The Cortex-M33 processor delivers a high computational performance with low-power
consumption and an advanced response to interrupts. It features:
• Arm TrustZone technology, using the Armv8-M main extension supporting secure and
non-secure states
• Memory protection units (MPUs), supporting up to 16 regions for secure and
non-secure applications
• Configurable secure attribute unit (SAU) supporting up to height memory regions as
secure or non-secure
• Floating-point arithmetic functionality with support for single precision arithmetic
The processor supports a set of DSP instructions that allows an efficient signal processing
and a complex algorithm execution.
The Cortex-M33 processor supports the following bus interfaces:
• System AHB bus:
The system AHB (S-AHB) bus interface is used for any instruction fetch and data
access to the memory-mapped SRAM, peripheral, external RAM and external device,
or Vendor_SYS regions of the Armv8-M memory map.
• Code AHB bus:
The code AHB (C-AHB) bus interface is used for any instruction fetch and data access
to the code region of the Armv8-M memory map.
Figure 1 shows the general block diagram of the STM32H562xx and STM32H563xx
devices.
3.2 ART Accelerator (ICACHE and DCACHE)
3.2.1 Instruction cache (ICACHE)

The instruction cache (ICACHE) is introduced on C-AHB code bus of Cortex-M33 processor
to improve performance when fetching instruction (or data) from both internal and external
memories.
ICACHE offers the following features:
• Multi-bus interface:
– slave port receiving the memory requests from the Cortex-M33 C-AHB code
execution port
– master1 port performing refill requests to internal memories (flash memory and
SRAMs)
– master2 port performing refill requests to external memories (external flash
memory and RAMs through Octo-SPI and FMC interfaces)
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64
Functional overview STM32H562xx and STM32H563xx
– a second slave port dedicated to ICACHE registers access

• Close to zero wait-states instructions/data access performance:
– 0 wait-state on cache hit
– hit-under-miss capability, allowing to serve new processor requests while a line
refill (due to a previous cache miss) is still ongoing
– critical-word-first refill policy, minimizing processor stalls on cache miss
– hit ratio improved by two-ways set-associative architecture and pLRU-t
replacement policy (pseudo-least-recently-used, based on binary tree), algorithm
with best complexity/performance balance
– dual master ports allowing to decouple internal and external memory traffics, on
fast and slow buses, respectively; also minimizing impact on interrupt latency
– optimal cache line refill thanks to AHB burst transactions (of the cache line size)
– performance monitoring by means of a hit counter and a miss counter
• Extension of cacheable region beyond the code memory space, by means of address
remapping logic that allows four cacheable external regions to be defined
• Power consumption reduced intrinsically (more accesses to cache memory rather to
bigger main memories); even improved by configuring ICACHE as direct mapped
(rather than the default two-ways set-associative mode)
• TrustZone security support
• Maintenance operation for software management of cache coherency
• Error management: detection of unexpected cacheable write access, with optional
interrupt raising
3.2.2 Data cache (DCACHE)

The data cache (DCACHE) is introduced on S-AHB system bus of Cortex-M33 processor to
improve the performance of data traffic to/from external memories.
DCACHE offers the following features:
• Multi-bus interface:
– slave port receiving the memory requests from the Cortex-M33 S-AHB system
port
– master port performing refill requests to external memories (external flash memory
and RAMs through Octo-SPI and FMC interfaces)
– a second slave port dedicated to DCACHE registers access
• Close to zero wait-states external data access performance:
– zero wait-states on cache hit
– hit-under-miss capability, allowing to serve new processor requests to cached
data, while a line refill (due to a previous cache miss) is still ongoing
– critical-word-first refill policy for read transactions, minimizing processor stalls on
cache miss
– hit ratio improved by two-ways set-associative architecture and pLRU-t
replacement policy (pseudo-least-recently-used, based on binary tree), algorithm
with best complexity/performance balance
– optimal cache line refill thanks to AHB burst transactions (of the cache line size)
– performance monitoring by means of two hit counters (for read and write) and two
miss counters (for read and write)
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• Supported cache accesses:

– supports both write-back and write-through policies (selectable with AHB
bufferable attribute)
– read and write-back always allocated
– write-through always non-allocated (write-around)
– supports byte, half-word and word writes
• TrustZone security support
• Maintenance operations for software management of cache coherency:
– full cache invalidation (non interruptible)
– address range clean and/or invalidate operations (background task, interruptible)
• Error management: detection of error for master port request initiated by DCACHE (line
eviction or clean operation), with optional interrupt raising
3.3 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to the memory
and to prevent one task to accidentally corrupt the memory or the resources used by any
other active task. This memory area is organized into up to 20 protected areas (12 secure
and 8 non-secure). The MPU regions and registers are banked across secure and non-
secure states.
The MPU is especially helpful for applications where some critical or certified code must be
protected against the misbehavior of other tasks. It is usually managed by an RTOS
(real-time operating system).
If a program accesses a memory location that is prohibited by the MPU, the RTOS can
detect it and take action. In an RTOS environment, the kernel can dynamically update the
MPU area setting based on the process to be executed.
3.4 Embedded flash memory

The devices feature 2 Mbytes of embedded flash memory that is available for storing
programs and data. The flash memory supports high-cycle data area of up to 100 K cycles.
The flash memory interface features:
• dual-bank operating modes
• read-while-write (RWW)
This allows a read operation to be performed from one bank while an erase or program
operation is performed to the other bank. Each bank contains 128 pages of 8 Kbytes.
The flash memory embeds 2-Kbyte OTP (one-time programmable) for user data and up to
96 Kbytes supporting high cycling capability (100 K cycles) to be used for data (EEPROM
emulation).
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The Options bytes are available to set the flash memory protection mechanisms:
• Different product states for protecting memory content from debug access
• Write protection (WRP) to protect areas against erasing and programming. Two areas
per bank can be selected with 8-Kbyte granularity.
• Sector group write-protection (WRPSG), protecting up to 32 groups of 4 sectors
(32 Kbytes) per bank
• Two secure-only areas (one per user flash memory bank). When enabled, this area is
accessible only if the STM32 device operates in Secure-access mode
• One HDP per area bank providing temporal isolation for startup code
The whole non-volatile memory embeds the error correction code (ECC) feature supporting:
• Single-error detection and correction
• Double-error detection
• ECC fail address report
3.4.1 FLASH security and protections

Sensitive information is stored in the flash memory and it is important to protect the memory
against unwanted operations such as reading confidential areas, illegal programming of
immutable sectors, or malicious flash memory erasing.
For that purpose FLASH implements the following protection mechanisms:
• TrustZone backed watermark and block security protection
• Temporal isolation protection (HDP)
• Configuration protection
• User flash memory write protection
• Device non-volatile security life cycle and application boot state management
• OTP locking
Refer to the product reference manual for a detailed description of all these security
mechanisms.
3.4.2 FLASH privilege protection

Each flash memory sector can be programmed on the fly as privileged or unprivileged.
3.5 Embedded SRAMs

Four SRAMs are embedded in the STM32H562xx and STM32H563xx devices, each with
specific features. SRAM1, SRAM2, and SRAM3 are the main SRAMs.
These SRAMs are made of several blocks that can be powered down in Stop mode to
reduce consumption:
• SRAM1: 256 Kbytes
• SRAM2: 64 Kbytes with ECC
• SRAM3: 320 Kbytes with optional ECC. When ECC is enabled, 64 bytes are reserved
for ECC
• BKPSRAM (backup SRAM): 4 Kbytes with optional ECC. The BKPSRAM can be
retained in all low-power modes and when VDD is off in VBAT mode.
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Note: The ECC is supported by SRAM2, SRAM3, and BKPSRAM when enabled with the
SRAM2_ECC, SRAM3_ECC, and BKPRAM_ECC user option bits.
3.5.1 SRAMs TrustZone security

When the TrustZone security is enabled, all SRAMs are secure after reset. The SRAM1,
SRAM2, SRAM3, can be programmed as secure or non-secure by blocks, using the
MPCBB (block-based memory protection controller).
The granularity of SRAM secure block based is a page of 512 bytes. Backup SRAM regions
can be programmed as secure or non-secure with watermark, using the TZSC (TrustZone
security controller) in the GTZC (global TrustZone controller).
3.5.2 SRAMs privilege protection

The SRAM1, SRAM2, SRAM3, can be programmed as privileged or non-privileged by
blocks, using the MPCBB. The granularity of SRAM privilege block based is a page of
512 bytes. Backup SRAM regions can be programmed as privileged or non-privileged with
watermark, using the TZSC (TrustZone security controller) in the GTZC (global TrustZone
controller).
3.6 Security overview

The STM32H562xx and STM32H563xx security enables the possibility to reopen the debug
mode even if the product is in secure state.
The reopening of the debug mode is controlled with a debug authentication procedure which
permits the authentication of the host.
The sensible assets such as keys or secret codes must be protected when opening the
debug mode. The protection is made via code protection and hardware keys storage
solutions where all root of trust can be protected thanks to hardware mechanisms.
In cases where sensitive information cannot be protected, a partial or a full regression can
be launched in order to allow a debugging. Regressions are enabled by a debug
authentication method.
The STM32H562xx and STM32H563xx design also permits the developers to introduce
their own root of trust solution (OEM-iROT), including their installation in a non-trusted
environment thanks to a secure firmware install (SFI) solution.
The STM32H562xx and STM32H563xx boot stages are isolated via a hardware mechanism
called HDPL (temporal isolation level). The HDPL guarantees isolation of the different boot
stages: ST assets, iROT (immutable root of trust), uROT (updatable root of trust), secure
operating system and non-secure applications.
STM32H562xx and STM32H563xx devices embed a hardware key storage solution with the
following characteristics:
• Feature a dedicated flash memory area per boot stages with access-control based on
HDPL and which can be secure or non-secure.
STM32H562xx and STM32H563xx devices are powered by an Arm Cortex-M33
microcontroller, which is associated with all the TrustZone isolation infrastructure. This
design permits to benefit from a run time isolation to run secure applications.
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3.7 Boot modes

At startup, a BOOT0 pin and NSBOOTADD[31:8]/SECBOOTADD[31:8] option bytes are
used to select the boot memory address that includes:
• Boot from any address in user flash memory
• Boot from system memory
– Bootloader
– ST immutable root of trust (ST-iROT)
– Root security service (RSS)
– Debug authentication library (RSS-DA)
Embedded bootloader
The embedded bootloader is located in the system memory, programmed by ST during
production. It is used to reprogram the flash memory by using USART, I2C, I3C, SPI,
FDCAN, or USB_FS in device mode through the DFU (device firmware upgrade).
Refer to the application note STM32 microcontroller system memory boot mode (AN2606).
Embedded root security services (RSS)

The embedded RSS are located in the secure information block, programmed by ST during
production.
Refer to the application note Overview secure firmware install (SFI) (AN4992).
Embedded immutable root of trust (ST-iROT)

The embedded ST-iROT in the system memory, programmed by ST during production. ST-
iROT is the immutable root of trust managing the secure boot and secure install of the first
updatable level to execute in a boot sequence.
Embedded debug authentication (ST-DA)

The embedded ST-DA in the system memory, programmed by ST during production. ST-DA
is the library that manages the debug authentication protocol by allowing to securely reopen
the debug or to launch regressions on secured products in the field.
3.7.1 STM32H562/H563boot modes

The table below provides the detail of the boot mode when the TrustZone is disabled
(TZEN=0xC3), for the STM32H562/H563 devices.
Table 3. STM32H562/H563 / Boot mode when TrustZone is disabled (TZEN=0xC3)

Boot address option- ST programmed
PRODUCT_STATE BOOT0 pin Boot area
byte selection default value
Boot address defined

Open 0 NSBOOTADD[31:8] by user option byte Flash: 0x0800 0000
NSBOOTADD[31:8]
- 1 NA Bootloader Bootloader
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Table 3. STM32H562/H563 / Boot mode when TrustZone is disabled (TZEN=0xC3) (continued)

Provisioning x NA RSS RSS

Boot address defined
Provisioned, Closed,
x NSBOOTADD[31:8] by user option byte Flash: 0x0800 0000
Locked
NSBOOTADD[31:8]
The below table provides the detail of the boot mode when the TrustZone is enabled
(TZEN=0xB4), for the STM32H562/H563 devices.
Table 4. STM32H562/H563 / Boot mode when TrustZone is enabled (TZEN=0xB4)

Boot address defined by

Open 0 SECBOOTADD[31:8] user option byte Flash: 0x0C00 0000
SECBOOTADD[31:8]
- 1 NA Bootloader Bootloader
Provisioning x NA RSS RSS
Provisioned, Boot address defined by
TZ_Closed, x SECBOOTADD[31:8] user option byte Flash: 0x0C00 0000
Closed, Locked SECBOOTADD[31:8]
When TrustZone is enabled (TZEN=0xB4), the boot space must be in secure area. The
SECBOOTADD0[24:0] option bytes are used to select the boot secure memory address. A
unique boot entry option can be selected by setting the SECBOOT_LOCK option bit.
3.8 Global TrustZone controller (GTZC)

GTZC is used to configure TrustZone and privileged attributes within the full system.
The GTZC includes three different sub-blocks:
• TZSC: TrustZone security controller
This sub-block defines the secure/privilege state of slave/master peripherals. It also
controls the non-secure area size for the watermark memory peripheral controller
(MPCWM). The TZSC block informs some peripherals (such as RCC or GPIOs) about
the secure status of each securable peripheral, by sharing with RCC and I/O logic.
• TZIC: TrustZone illegal access controller
This sub-block gathers all security illegal access events in the system and generates a
secure interrupt towards NVIC.
• MPCBB: MPCBB: block-based memory protection controller
This sub-block controls secure states of all memory blocks (512-byte pages) of the
associated SRAM. This peripheral aims at configuring the internal RAM in a TrustZone
system product having segmented SRAM with programmable-security and privileged
attributes.
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The GTZC main features are:

• Three independent 32-bit AHB interfaces for TZSC, TZIC and MPCBB
• MPCBB and TZIC accessible only with secure transactions
– Enable illegal access events that may trig a secure interrupt
• Secure and non-secure access supported for privileged/non-privileged part of TZSC
• Set of registers to define product security settings:
– Secure/privilege regions for external memories
– Secure/privilege access mode for securable peripherals
– Secure/privilege access mode for securable legacy masters
3.9 TrustZone security architecture

The security architecture is based on Arm TrustZone with the Armv8-M main extension.
The TrustZone security is activated by the TZEN option bit in the FLASH_OPTR register.
When the TrustZone is enabled, the SAU (security attribution unit) and IDAU
(implementation defined attribution unit) define the access permissions based on secure
and non-secure state.
• SAU: up to eight SAU configurable regions are available for security attribution.
• IDAU: It provides a first memory partition as non-secure or non-secure callable
attributes. It is then combined with the results from the SAU security attribution and the
higher security state is selected.
Based on IDAU security attribution, the flash memory, system SRAMs and peripherals
memory space is aliased twice for secure and non-secure states. However, the external
memories space is not aliased.
3.9.1 TrustZone peripheral classification

When the TrustZone security is active, a peripheral can be either securable or TrustZone-
aware type as follows:
• securable: peripheral protected by an AHB/APB firewall gate that is controlled from
TZSC to define security properties
• TrustZone-aware: peripheral connected directly to AHB or APB bus and implementing
a specific TrustZone behavior such as a subset of registers being secure
3.9.2 Default TrustZone security state

The default system security state is detailed below:
• CPU:
– Cortex-M33 is in secure state after reset. The boot address must be in secure
address.
• Memory map:
– SAU is fully secure after reset. Consequently, all memory map is fully secure. Up
to eight SAU configurable regions are available for security attribution.
• Flash memory:
– Flash memory security area is defined by watermark user options.
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– Flash memory block based area is non-secure after reset.

• SRAMs:
– All SRAMs are secure after reset. MPCBB (memory protection block based
controller) is secure.
• External memories:
– FMC, OCTOSPI banks are secure after reset. MPCWMx (memory protection
watermark based controller) is secure.
• Peripherals
– Securable peripherals are non-secure after reset.
– TrustZone-aware peripherals are non-secure after reset. Their secure
configuration registers are secure.
• All GPIOs are secure after reset.
• Interrupts:
– NVIC: All interrupts are secure after reset. NVIC is banked for secure and non-
secure state.
• TZIC: All illegal access interrupts are disabled after reset.
3.10 Power supply management

The power controller (PWR) main features are:
• Power supplies and supply domains
– Core domains (VCORE)
– VDD domain
– Backup domain (VBAT)
– Analog domain (VDDA)
– SMPS power stage (VDDSMPS, available only on SMPS packages)
– VDDIO2 domain
– VDDUSB for USB transceiver
• System supply voltage regulation
– SMPS step down converter
– Voltage regulator (LDO)
• Power supply supervision
– POR/PDR monitor
– BOR monitor
– PVD monitor
• Power management
– Operating modes
– Voltage scaling control
– Low-power modes
• VBAT battery charging
• TrustZone security and privileged protection
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3.10.1 Power supply schemes

The devices require a 1.71 V to 3.6 V VDD operating voltage supply. Several independent
supplies can be provided for specific peripherals:
• VDD = 1.71 V to 3.6 V
VDD is the external power supply for the I/Os, the internal regulator and the system
analog such as reset, power management and internal clocks. It is provided externally
through the VDD pins.
• VDDA = 1.71 V (ADCs, DACs) or 2.1 V (VREFBUF) to 3.6 V
VDDA is the external analog power supply for ADCs, DACs and voltage reference
buffer. The VDDA voltage level is independent from the VDD voltage and must preferably
be connected to VDD when these peripherals are not used.
• VDDSMPS = 1.71 V to 3.6 V
VDDSMPS is the external power supply for the SMPS step down converter. It is provided
externally through VDDSMPS supply pin and must be connected to the same supply
than VDD.
• VLXSMPS is the switched SMPS step down converter output.
Note: The SMPS power supply pins are available only on a specific package with SMPS step
down converter option.
• VDDUSB = 3.0 V to 3.6 V
VDDUSB is the external independent power supply for USB transceivers. VDDUSB
voltage level is independent from the VDD voltage and must preferably be connected to
VDD when the USB is not used.
• VDDIO2 = 1.08 V to 3.6 V
VDDIO2 is the external power supply for 10 I/Os (PD6, PD7, PG9:14, PB8, PB9). The
VDDIO2 voltage level is independent from the VDD voltage and must preferably be
connected to VDD when those pins are not used.
• VBAT = 1.2 V to 3.6 V
VBAT is the power supply for RTC, external clock 32 kHz oscillator and backup registers
(through power switch) when VDD is not present.
• VREF-, VREF+
VREF+ is the input reference voltage for ADCs and DACs. It is also the output of the
internal voltage reference buffer when enabled.
VREF+ can be grounded when ADC and DAC are not active.
VREF- and VREF+ pins are not available on all packages. When not available, they are
bonded to VSSA and VDDA, respectively.
When the VREF+ is double-bonded with VDDA in a package, the internal voltage
reference buffer is not available and must be kept disabled.
VREF- must always be equal to VSSA.
The STM32H562xx and STM32H563xx devices embed two regulators: one LDO or one
SMPS depending on the package, to provide the VCORE supply for digital peripherals,
SRAM1, SRAM2, SRAM3 and embedded flash memory. The SMPS generates this voltage
on VCAP (two pins), with a total external capacitor of 10 μF typical. SMPS requires an
external coil. The LDO generates this voltage on VCAP pin connected to an external
capacitor of 2x 2.2 μF typical.
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Both regulators can provide four different voltages (voltage scaling) and can operate in Stop
modes.
Figure 2. STM32H562xx and STM32H563xx power supply overview (with SMPS)
VDDA domain
A/D converters
VDDA
D/A converters
VSSA
Voltage reference buffer
VDDUSB
USB transceiver
VSS
VDDIO2 domain
VDDIO2 VDDIO2
I/O ring
VSS
VDD domain
VDDIO1 I/O ring
Reset block
Temperature sensor
3 x PLL VCORE domain
Internal RC oscillators
Core
VSS Standby circuitry
(Wakeup logic, IWDG) SRAM1
VDD SRAM2
Voltage regulator SRAM3
VCORE
2x VCAP Digital
VLXSMPS peripherals
SMPS regulator
VDDSMPS
VSSSMPS
Flash memory
Low-voltage detector
Backup domain
LSE crystal 32kHz oscillator
VBAT Backup registers
RCC_BDCR register
RTC
TAMP
BKPSRAM
MSv64010V2
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64
Figure 3. STM32H562xx and STM32H563xx power supply overview (with LDO)

VDDA domain
A/D converters
VDDA
D/A converters
VSSA
Voltage reference buffer
VDDUSB
USB transceiver
VSS
VDDIO2 domain
VDDIO2 VDDIO2
I/O ring
VSS
VDD domain
VDDIO1 I/O ring
VCORE domain
Reset block
Temperature sensor Core
3 x PLL
VSS Internal RC oscillators SRAM1
SRAM2
Standby circuitry SRAM3
VDD (Wakeup logic, IWDG)
VCORE
VCAP Digital
peripherals
LDO regulator
Flash memory
Low-voltage detector
Backup domain
LSE crystal 32kHz oscillator
VBAT Backup registers
RCC_BDCR register
RTC
TAMP
BKPSRAM
MSv64011V1
During power-up and power-down phases, the following power sequence requirements
must be respected:
• When VDD is below 1 V, other power supplies (VDDA, VDDIO2, VDDUSB) must remain
below VDD + 300 mV.
• When VDD is above 1 V, all power supplies are independent.
• During the power-down phase, VDD can temporarily become lower than other supplies
only if the energy provided to the MCU remains below 1 mJ. This allows external
decoupling capacitors to be discharged with different time constants during the power-
down transient phase.
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Figure 4. Power-up /down sequence
3.6
VDDX(1)
VDD
VBOR0
0.3
Power-on Operating mode Power-down time
Invalid supply area VDDX < VDD + 300 mV VDDX independent from VDD
MSv47490V1
1. VDDX refers to any power supply among VDDA, VDDUSB, and VDDIO2.
3.10.2 Power supply supervisor

The devices have an integrated ultra-low-power brownout reset (BOR) active in all modes;
The BOR ensures proper operation of the devices after power on and during power down.
The devices remain in reset mode when the monitored supply voltage VDD is below a
specified threshold, without the need for an external reset circuit.
The lowest BOR level is 1.71 V at power on, and other higher thresholds can be selected
through option bytes.The devices feature an embedded programmable voltage detector
(PVD) that monitors the VDD power supply and compares it to the VPVD threshold.
An interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD
is higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
In addition, the devices embed a peripheral voltage monitor that compares the independent
supply voltages VDDA, VDDUSB and VDDIO2 to ensure that the peripheral is in its functional
supply range.
The devices support dynamic voltage scaling to optimize its power consumption in Run
mode. The voltage from the main regulator that supplies the logic (VCORE) can be adjusted
according to the system’s maximum operating frequency.
The main regulator operates in the following ranges:
• VOS0 (Vcore = 1.35V) with CPU and peripherals running at up to 250 MHz
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Low-power modes
By default, the microcontroller is in Run mode after a system or a power reset. It is up to the
user to select one of the low-power modes described below:
• Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
• Stop modes
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the VCORE domain are stopped, the PLL, the CSI,
the HSI, the HSI48 and the HSE crystal oscillators are disabled. The LSE or LSI is still
running.
The RTC can remain active (Stop mode with RTC, Stop mode without RTC).
The system clock when exiting from Stop mode can be either HSI up to 64 MHz or CSI
(4 MHz), depending on software configuration.
• Standby mode
The Standby mode is used to achieve the lowest power consumption with BOR. The
PLL, the HSI, the CSI, the HSI48 and the HSE crystal oscillators are also switched off.
The RTC can remain active (Standby mode with RTC, Standby mode without RTC).
The BOR always remains active in Standby mode.
The I/Os state during Standby mode can be retained.
After entering Standby mode, SRAMs and register contents are lost except for registers
and backup SRAM in the Backup domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset,
WKUP pin event (configurable rising or falling edge), an RTC event occurs (alarm,
periodic wakeup, timestamp), or a tamper detection. The tamper detection can be
raised either due to external pins or due to an internal failure detection.
The system clock after wakeup is HSI at 32 MHz.
3.10.3 Reset mode

In order to improve the consumption under reset, the I/Os state under and after reset is
“analog state” (the I/O Schmitt trigger is disable).
3.10.4 VBAT operation

The VBAT pin allows the device VBAT domain to be powered from an external battery or an
external super-capacitor.
The VBAT pin supplies the RTC with LSE, anti-tamper detection (TAMP), backup registers
and 4-Kbyte backup SRAM. Eight anti-tamper detection pins are available in VBAT mode.
The VBAT operation is automatically activated when VDD is not present. An internal VBAT
battery charging circuit is embedded and can be activated when VDD is present.
Note: When the microcontroller is supplied from VBAT, neither external interrupts nor RTC
alarm/events exit the microcontroller from the VBAT operation.
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3.10.5 PWR TrustZone security

When the TrustZone security is activated by the TZEN option bit, the PWR is switched in
TrustZone security mode.
The PWR TrustZone security secures the following configuration:
• Low-power mode
• Wake-up (WKUP) pins
• Voltage detection and monitoring
• VBAT mode
Some of the PWR configuration bits security is defined by the security of other peripherals:
• The voltage scaling (VOS) configuration is secure when the system clock selection is
secure in RCC.
• The I/O pull-up/pull-down in Standby mode configuration is secure when the
corresponding GPIO is secure.
• The backup domain write protection is secure when the RTC is secure.
3.11 Peripheral interconnect matrix

Several peripherals have direct connections between them, that allow autonomous
communication between them and support the saving of CPU resources (thus power supply
consumption). In addition, these hardware connections allow fast and predictable latency.
Depending on the peripherals, these interconnections can operate in Run and Sleep modes.
3.12 Reset and clock controller (RCC)

The clock controller distributes the clocks coming from the different oscillators to the core
and to the peripherals. It also manages the clock gating for low-power modes and ensures
the clock robustness. It features:
• Clock prescaler: in order to get the best trade-off between speed and current
consumption, the clock frequency to the CPU and peripherals can be adjusted by a
programmable prescaler.
• Clock security system: clock sources can be changed safely on the fly in Run mode
through a configuration register.
• Clock management: in order to reduce the power consumption, the clock controller
can stop the clock to the core, individual peripherals or memory.
• System clock source: four different clock sources can be used to drive the master
clock SYSCLK:
– 4 to 50 MHz high-speed external crystal or ceramic resonator (HSE), that can
supply a PLL. The HSE can also be configured in bypass mode for an external
clock.
– 64 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can
supply a PLL.
– 4 MHz low-power internal oscillator (CSI), trimmable by software that can supply a
PLL.
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– System PLL that can be fed by HSE, HSI or CSI, with a maximum frequency at
250 MHz.
• RC48 with clock recovery system (HSI48): internal 48 MHz clock source (HSI48),
can be used to drive the USB.
• UCPD kernel clock, derived from HSI clock. The HSI RC oscillator must be enabled
prior to the UCPD kernel clock use.
• Auxiliary clock source: two ultra-low-power clock sources that can be used to drive
the real-time clock:
– 32.768 kHz low-speed external crystal (LSE), supporting four drive capability
modes. The LSE can also be configured in bypass mode for an external clock.
– 32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
• Peripheral clock sources: several peripherals have their own independent clock
whatever the system clock. Three PLLs, each having three independent outputs
allowing the highest flexibility, can generate independent clocks for the ADC, USB,
SDMMC, RNG, FDCAN1, OCTOSPI and the two SAIs.
• Startup clock: after reset, the microcontroller restarts by default with an internal
32 MHz clock (HSIdiv 2). The prescaler ratio and clock source can be changed by the
application program as soon as the code execution starts.
• Clock security system (CSS): this feature can be enabled by software. If a HSE clock
failure occurs, the master clock automatically switches to HSI and a software interrupt
is generated if enabled. LSE failure can also be detected and generates an interrupt.
• Clock-out capability:
– MCO (microcontroller clock output): it outputs one of the internal clocks for
external use by the application.
– LSCO (low-speed clock output): it outputs LSI or LSE in all low-power modes
(except VBAT).
Several prescalers allow AHB and APB frequencies configuration. The maximum frequency
of the AHB and the APB clock domains is 250 MHz.
3.12.1 RCC TrustZone security

When the TrustZone security is activated by the TZEN option bit, the RCC is switched in
TrustZone security mode.
The RCC TrustZone security secures some RCC system configuration and peripheral
configuration clock from being read or modified by non-secure accesses: when a peripheral
is secure, the related peripheral clock, reset, clock source selection and clock enable during
low-power modes control bits are secure.
A peripheral is in secure state:
• when its corresponding SEC security bit is set in the TZSC (TrustZone security
controller), for securable peripherals.
• when a security feature of this peripheral is enabled through its dedicated bits, for
TrustZone-aware peripherals.
3.13 Clock recovery system (CRS)

The devices embed a special block that allows automatic trimming of the internal 48 MHz
oscillator to guarantee its optimal accuracy over the whole device operational range. This
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automatic trimming is based on the external synchronization signal, that is either derived
from USB SOF signalization, from LSE oscillator, from an external signal on CRS_SYNC pin
or generated by user software. For faster lock-in during startup, automatic trimming and
manual trimming action can be combined.
3.14 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions.
After reset, all GPIOs are in analog mode to reduce power consumption.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
10 IOs (PD6, PD7, PG9:14, PB8, PB9) can be independently supplied by a dedicated
VDDIO supply.
3.14.1 GPIOs TrustZone security

Each I/O pin of GPIO port can be individually configured as secure. When the selected I/O
pin is configured as secure, its corresponding configuration bits for alternate function, mode
selection, I/O data are secure against a non-secure access. The associated registers bit
access is restricted to a secure software only. After reset, all GPIO ports are secure.
3.15 Multi-AHB bus matrix

A 32-bit multi-AHB bus matrix interconnects all the masters (CPU, GPDMA1, GPDMA2,
SDMMC1, SDMMC2, Ethernet) and the slaves (flash memory, FMC, OCTOSPI, SRAMs,
AHB and APB) peripherals. It also ensures a seamless and efficient operation even when
several high-speed peripherals work simultaneously.
3.16 General purpose direct memory access controller (GPDMA)

The general purpose direct memory access (GPDMA) controller is a bus master and system
peripheral.
The GPDMA is used to perform programmable data transfers between memory-mapped
peripherals and/or memories via linked-lists, upon the control of an off-loaded CPU.
The GPDMA main features are:
• Dual bidirectional AHB master
• Memory-mapped data transfers from a source to a destination:
– Peripheral-to-memory
– Memory-to-peripheral
– Memory-to-memory
– Peripheral-to-peripheral
• Autonomous data transfers during Sleep mode
• Transfers arbitration based on a four-grade programmed priority at a channel level:
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– One high-priority traffic class, for time-sensitive channels (queue 3)

– Three low-priority traffic classes, with a weighted round-robin allocation for non
time-sensitive channels (queues 0, 1, 2)
• Per channel event generation, on any of the following events: transfer complete or half
transfer complete or data transfer error or user setting error, and/or update linked-list
item error or completed suspension
• Per channel interrupt generation, with separately programmed interrupt enable per
event
• 8 concurrent DMA channels:
– Per channel FIFO for queuing source and destination transfers
– Intra-channel DMA transfers chaining via programmable linked-list into memory,
supporting two execution modes: run-to-completion and link step mode
– Intra-channel and inter-channel DMA transfers chaining via programmable DMA
input triggers connection to DMA task completion events
• Per linked-list item within a channel:
– Separately programmed source and destination transfers
– Programmable data handling between source and destination: byte-based
reordering, packing or unpacking, padding or truncation, sign extension and
left/right realignment
– Programmable number of data bytes to be transferred from the source, defining
the block level
– 12 channels with linear source and destination addressing: either fixed or
contiguously incremented addressing, programmed at a block level, between
successive single transfers
– Four channels with 2D source and destination addressing: programmable signed
address offsets between successive burst transfers (non-contiguous addressing
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within a block, combined with programmable signed address offsets between

successive blocks, at a second 2D/repeated block level)
– Support for scatter-gather (multi-buffer transfers), data interleaving and
deinterleaving via 2D addressing
– Programmable DMA request and trigger selection
– Programmable DMA half-transfer and transfer complete events generation
– Pointer to the next linked-list item and its data structure in memory, with automatic
update of the DMA linked-list control registers
• Debug:
– Channel suspend and resume support
– Channel status reporting including FIFO level and event flags
• TrustZone support:
– Support for secure and non-secure DMA transfers, independently at a first
channel level, and independently at a source/destination and link sub-levels
– Secure and non-secure interrupts reporting, resulting from any of the respectively
secure and non-secure channels
– TrustZone-aware AHB slave port, protecting any DMA secure resource (register,
register field) from a non-secure access
• Privileged/unprivileged support:
– Support for privileged and unprivileged DMA transfers, independently at a channel
level
– Privileged-aware AHB slave port.
3.17 Interrupts and events
3.17.1 Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller that is able to manage 16 priority
levels and to handle up to 125 maskable interrupt channels plus the 16 interrupt lines of the
Cortex-M33.
The NVIC benefits are the following:
• closely coupled NVIC giving low-latency interrupt processing
• interrupt entry vector table address passed directly to the core
• early processing of interrupts
• processing of late arriving higher priority interrupts
• support for tail chaining
• processor state automatically saved
• interrupt entry restored on interrupt exit with no instruction overhead
• TrustZone support: NVIC registers banked across secure and non-secure states
The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.
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3.17.2 Extended interrupt/event controller (EXTI)

The extended interrupts and event controller (EXTI) manages the individual CPU and
system wakeup through configurable event inputs. It provides wakeup requests to the power
control, and generates an interrupt request to the CPU NVIC and events to the CPU event
input. For the CPU an additional event generation block (EVG) is needed to generate the
CPU event signal.
The EXTI wakeup requests allow the system to be woken up from Stop modes.
The interrupt request and event request generation can also be used in Run modes. The
EXTI also includes the EXTI multiplexer IO port selection.
The EXTI main features are the following:
• All event inputs allowed to wake up the system
• Configurable events (signals from I/Os or peripherals able to generate a pulse)
– Selectable active trigger edge
– Interrupt pending status register bit independent for the rising and falling edge
– Individual interrupt and event generation mask, used for conditioning the CPU
wakeup, interrupt and event generation
– Software trigger possibility
• TrustZone secure events
– The access to control and configuration bits of secure input events can be made
secure
• EXTI IO port selection
3.18 Cyclic redundancy check calculation unit (CRC)

The CRC is used to get a CRC code using a configurable generator with polynomial value
and size.
Among other applications, the CRC-based techniques are used to verify data transmission
or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a mean to verify
the flash memory integrity.
The CRC calculation unit helps to compute a signature of the software during runtime, that
can be ulteriorly compared with a reference signature generated at link-time and that can be
stored at a given memory location.
3.19 CORDIC co-processor (CORDIC)

The CORDIC co-processor provides hardware acceleration of certain mathematical
functions, notably trigonometric, commonly used in motor control, metering, signal
processing and many other applications. It speeds up the calculation of these functions
compared to a software implementation, allowing a lower operating frequency, or freeing up
processor cycles in order to perform other tasks.
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The CORDIC main features are:

• 24-bit CORDIC rotation engine
• Circular and hyperbolic modes
• Rotation and vectoring modes
• Functions: sine, cosine, sinh, cosh, atan, atan2, atanh, modulus, square root, natural
logarithm
• Programmable precision
• Low-latency AHB slave interface
• Results can be read as soon as ready without polling or interrupt
• DMA read and write channels
• Multiple register read/write by DMA
3.20 Filter math accelerator (FMAC)

The FMAC performs arithmetic operations on vectors. It comprises a multiplier/accumulator
(MAC) unit, together with address generation logic that allows it to index vector elements
held in local memory.
The unit includes support for circular buffers on input and output, that allows digital filters to
be implemented. Both finite and infinite impulse response filters can be done.
The unit allows frequent or lengthy filtering operations to be offloaded from the CPU, freeing
up the processor for other tasks. In many cases it can accelerate such calculations
compared to a software implementation, resulting in a speed-up of time critical tasks.
The FMAC main features are:
• 16 x 16-bit multiplier
• 24 + 2-bit accumulator with addition and subtraction
• 16-bit input and output data
• 256 x 16-bit local memory
• Up to three areas can be defined in memory for data buffers (two input, one output),
defined by programmable base address pointers and associated size registers
• Input and output buffers can be circular
• Filter functions: FIR, IIR (direct form 1)
• Vector functions: dot product, convolution, correlation
• AHB slave interface
• DMA read and write data channels
3.21 Flexible memory controller (FMC)

The FMC includes three memory controllers:
• NOR/PSRAM memory controller
• NAND memory controller
• SDRAM memory controller
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The main features of the FMC controller are the following:

• Interface with static-memory mapped devices including:
– Static random access memory (SRAM)
– NOR flash memory/OneNAND flash memory
– PSRAM (four memory banks)
– NAND flash memory with ECC hardware to check up to 8 Kbytes of data
– Ferroelectric RAM (FRAM)
• Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
• 8-,16- bit data bus width
• Independent chip select control for each memory bank
• Independent configuration for each memory bank
• Write FIFO
3.21.1 LCD parallel interface

The FMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel® 8080 and Motorola® 6800 modes, and is flexible enough to adapt to
specific LCD interfaces.
This LCD parallel interface capability makes it easy to build cost effective graphic
applications using LCD modules with embedded controllers or high-performance solutions
using external controllers with dedicated acceleration.
3.21.2 FMC TrustZone security

When the TrustZone security is enabled, the whole FMC banks are secure after reset. Non-
secure area can be configured using the TZSC MPCWMx controller.
• The FMC NOR/PSRAM bank:
– Up to two non-secure area can be configured thought the TZSC MPCWM2
controller with a 64-Kbyte granularity
• The FMC NAND bank:
– Can be either configured as fully secure or fully non-secure using the TZSC
MPCWM3 controller
The FMC registers can be configured as secure through the TZSC controller.
3.22 Octo-SPI interface (OCTOSPI)

The OCTOSPI supports most external serial memories such as serial PSRAMs, serial
NAND and serial NOR flash memories, HyperRAMs™ and HyperFlash™ memories, with
the following functional modes:
• Indirect mode: all the operations are performed using the OCTOSPI registers.
• Status-polling mode: the external memory status register is periodically read and an
interrupt can be generated in case of flag setting.
• Memory-mapped mode: the external memory is memory mapped and is seen by the
system as if it were an internal memory supporting read and write operation.
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The OCTOSPI supports the following protocols with associated frame formats:
• the standard frame format with the command, address, alternate byte, dummy cycles
and data phase
• the HyperBus™ frame format
The OCTOSPI offers the following features:
• Three functional modes: Indirect, Status-polling, and Memory-mapped
• Read and write support in Memory-mapped mode
• Supports for single, dual, quad and octal communication
• Dual-quad mode, where eight bits can be sent/received simultaneously by accessing
two quad memories in parallel.
• SDR (single-data rate) and DTR (double-transfer rate) support
• Data strobe support
• Fully programmable opcode
• Fully programmable frame format
• HyperBus support
• Integrated FIFO for reception and transmission
• 8-, 16-, and 32-bit data accesses allowed
• DMA channel for Indirect mode operations
• Interrupt generation on FIFO threshold, timeout, operation complete, and access error
3.22.1 OCTOSPI TrustZone security

When the TrustZone security is enabled, the whole OCTOSPI bank is secure after reset.
Up to two non-secure area can be configured thought the TZSC MPCWM1 controller with a
granularity of 64 Kbytes.
The OCTOSPI registers can be configured as secure through the TZSC controller.
3.23 Delay block (DLYB)

The delay block (DLYB) is used to generate an output clock that is dephased from the input
clock. The phase of the output clock must be programmed by the user application. The
output clock is then used to clock the data received by another peripheral such as an
SDMMC or Octo-SPI interface. The delay is voltage and temperature dependent, that may
require the application to re-configure and recenter the output clock phase with the received
data.
The delay block main features are:
• Input clock frequency ranging from 25 to 250 MHz
• Up to 12 oversampling phases
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3.24 Analog-to-digital converter (ADC1 and ADC2)

The devices embed two successive approximation analog-to-digital converters.
Table 5. ADC features

ADC modes/features ADC1 ADC2
Resolution 12 bit
5 Msps
Maximum sampling speed
(12-bit resolution)
Dual mode operation X
Hardware offset calibration X
Hardware linearity calibration -
Single-end input X
Differential input X
Injected channel conversion X
Oversampling up to x256
Data register 16 bits
Data register FIFO depth 3 stages
DMA support X
Parallel data output to ADF -
Offset compensation X
Gain compensation -
Number of analog watchdog 3
Option register - X
3.24.1 Temperature sensor

The temperature sensor generates a voltage VSENSE that varies linearly with temperature.
The temperature sensor is internally connected to ADC input channel that is used to convert
the sensor output voltage into a digital value.
The sensor provides good linearity but it must be calibrated to obtain a good accuracy of the
temperature measurement. As the offset of the temperature sensor varies from chip to chip
due to process variation, the uncalibrated internal temperature sensor is suitable for
applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by STMicroelectronics in the system memory area, accessible in read-only mode.
3.24.2 Internal voltage reference (VREFINT)

The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for
the ADC. The VREFINT is internally connected to ADC input channel.
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The precise voltage of VREFINT is individually measured for each part by

STMicroelectronics during production test and stored in the system memory area. It is
accessible in read-only mode.
3.24.3 VBAT battery voltage monitoring

This embedded hardware enables the application to measure the VBAT battery voltage using
ADC or input channel. As the VBAT voltage may be higher than the VDDA, and thus outside
the ADC input range, the VBAT pin is internally connected to a bridge divider by four. As a
consequence, the converted digital value is a quarter of the VBAT voltage.
3.25 Digital to analog converter (DAC)

The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be
configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In
12-bit mode, the data may be left- or right-aligned.
The DAC features two output channels, each with its own converter. In dual DAC channel
mode, conversions can be done independently or simultaneously when both channels are
grouped together for synchronous update operations. An input reference pin, VREF+
(shared with others analog peripherals) is available for better resolution. An internal
reference can also be set on the same input.
The DAC_OUTx pin can be used as general purpose input/output (GPIO) when the DAC
output is disconnected from output pad and connected to on chip peripheral. The DAC
output buffer can be optionally enabled to allow a high drive output current. An individual
calibration can be applied on each DAC output channel. The DAC output channels support
a low power mode, the Sample and hold mode.
The digital interface supports the following features:
• One DAC interface, maximum two output channels
• Left or right data alignment in 12-bit mode
• Synchronized update capability
• Noise-wave and triangular-wave generation
• Sawtooth wave generation
• Dual DAC channel for independent or simultaneous conversions
• DMA capability for each channel including DMA underrun error detection
• Double data DMA capability to reduce the bus activity
• External triggers for conversion
• DAC output channel buffered/unbuffered modes
• Buffer offset calibration
• Each DAC output can be disconnected from the DAC_OUTx output pin
• DAC output connection to on chip peripherals
• Sample and Hold mode for low-power operation in Stop mode. The DAC voltage can
be changed autonomously with the DMA while the device is in Stop mode.
• Voltage reference input
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3.26 Voltage reference buffer (VREFBUF)

The devices embed a voltage reference buffer that can be used as voltage reference for
ADCs, DACs and also as voltage reference for external components through the
VREF+ pin.
The internal voltage reference buffer supports three voltages: 1.8 V, 2.048 V and 2.5 V.
An external voltage reference can be provided through the VREF+ pin when the internal
voltage reference buffer is off.
The VREF+ pin is double-bonded with VDDA on some packages. In these packages the
internal voltage reference buffer is not available.
3.27 Digital camera interface (DCMI)

The digital camera is a synchronous parallel interface able to receive a high-speed data flow
from an external 8-, 10-, 12- or 14-bit CMOS camera module. It supports different data
formats: YCbCr4:2:2/RGB565 progressive video and compressed data (JPEG).
This interface is for use with black and white cameras, X24 and X5 cameras, and it is
assumed that all preprocessing such as resizing is performed in the camera module.
The DCMI features are:
• 8-, 10-, 12- or 14-bit parallel interface
• Embedded/external line and frame synchronization
• Continuous or snapshot mode
• Crop feature
• Supports the following data formats:
– 8/10/12/14-bit progressive video: either monochrome or raw bayer
– YCbCr 4:2:2 progressive video
– RGB 565 progressive video
– Compressed data: JPEG
3.28 Parallel synchronous slave interface (PSSI)

The PSSI peripheral and the DCMI (digital camera interface) use the same circuitry. As a
result, these two peripherals cannot be used at the same time: when using the PSSI, the
DCMI registers cannot be accessed, and vice versa. In addition, the PSSI and the DCMI
share the same alternate functions and the same interrupt vector.
The PSSI is a generic synchronous 8-/16-bit parallel data input/output slave interface. It
enables the transmitter to send a data valid signal that indicates when the data is valid, and
the receiver to output a flow control signal that indicates when it is ready to sample the data.
The PSSI peripheral main features are the following:
• Slave mode operation
• 8-bit or 16-bit parallel data input or output
• 4-word (16-byte) FIFO
• Data enable (PSSI_DE) alternate function input and ready (PSSI_RDY) alternate
function output
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When selected, these inputs can either enable the transmitter to indicate when the data is
valid, or allow the receiver to indicate when it is ready to sample the data, or both.
3.29 True random number generator (RNG)

The RNG is a true random number generator that provides full entropy outputs to the
application as 32-bit samples. It is composed of a live entropy source (analog) and an
internal conditioning component.
The RNG is a NIST SP 800-90B compliant entropy source that can be used to construct a
non-deterministic random bit generator (NDRBG).
The true random generator:
• delivers 32-bit true random numbers, produced by an analog entropy source
conditioned by a NIST SP800-90B approved conditioning stage
• can be used as entropy source to construct a non-deterministic random bit generator
(NDRBG)
• produces four 32-bit random samples every 412 AHB clock cycles if fAHB < 77 MHz
(256 RNG clock cycles otherwise)
• embeds start-up and NIST SP800-90B approved continuous health tests (repetition
count and adaptive proportion tests), associated with specific error management
• can be disabled to reduce power consumption, or enabled with an automatic low-power
mode (default configuration)
• has an AMBA AHB slave peripheral, accessible through 32-bit word single accesses
only (else an AHB bus error is generated, and the write accesses are ignored)
3.30 HASH hardware accelerator (HASH)

The HASH is a fully compliant implementation of the secure hash algorithm
(SHA-1, SHA-224, SHA-256, SHA-512) and the HMAC (keyed-hash message
authentication code) algorithm. HMAC is suitable for applications requiring message
authentication.
The HASH computes FIPS (Federal information processing standards) approved digests of
length of 160, 224, 256, 512 bits, for messages of up to (264 – 1).
The HASH main features are:
• Suitable for data authentication applications, compliant with:
– Federal Information Processing Standards Publication FIPS PUB 180-4, Secure
Hash Standard (SHA-1 and SHA-2 family)
– Federal Information Processing Standards Publication FIPS PUB 186-4, Digital
Signature Standard (DSS)
– Internet Engineering Task Force (IETF) Request For Comments RFC 2104,
HMAC: Keyed-Hashing for Message Authentication and Federal Information
Processing Standards Publication FIPS PUB 198-1, The Keyed-Hash Message
Authentication Code (HMAC)
• Fast computation of SHA-1, SHA-224, SHA-256 and SHA-512
– 82 (respectively 66) clock cycles for processing one 512-bit block of data using
SHA-1 (respectively SHA-256) algorithm
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• Corresponding 32-bit words of the digest from consecutive message blocks are added
to each other to form the digest of the whole message
– Automatic 32-bit words swapping to comply with the internal little-endian
representation of the input bit string
– Word swapping supported: bits, bytes, half-words and 32-bit words
• Automatic padding to complete the input bit string to fit digest minimum block size of
512 bits (16 × 32 bits)
• Single 32-bit input register associated to an internal input FIFO of sixteen 32-bit words,
corresponding to one block size
• AHB slave peripheral, accessible through 32-bit word accesses only (else an AHB
error is generated)
• 8 × 32-bit words (H0 to H7) for output message digest
• Automatic data flow control with support of direct memory access (DMA) using one
channel. Single or fixed burst of 4 supported.
• Interruptible message digest computation, on a per-32-bit word basis
– Re-loadable digest registers
– Hashing computation suspend/resume mechanism, including using DMA
3.31 Timers and watchdogs

The devices include two advanced control timers, up to seven general-purpose timers, two
basic timers, six low-power timers, two watchdog timers and two SysTick timers.
The table below compares the features of the advanced control, general-purpose and basic
timers.
Table 6. Timer feature comparison

DMA Capture/
Counter Counter Prescaler Complementary
Timer type Timer request compare
resolution type factor outputs
generation channels
Any integer
Advanced Up, down,
TIM1, TIM8 16 bits between 1 and Yes 4 3
control Up/down
65536
Any integer
General- Up, down,
TIM2, TIM5 32 bits between 1 and Yes 4 No
purpose Up/down
65536
Any integer
General- Up, down,
TIM3, TIM4 16 bits between 1 and Yes 4 No
purpose Up/down
65536
Any integer
General- TIM12,
16 bits Up between 1 and Yes 2 1
purpose TIM15
65536
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Table 6. Timer feature comparison (continued)

DMA Capture/
Counter Counter Prescaler Complementary
Timer type Timer request compare
resolution type factor outputs
generation channels
TIM13,
Any integer
General- TIM14,
16 bits Up between 1 and Yes 1 1
purpose TIM16,
65536
TIM17
Any integer
Basic TIM6, TIM7 16 bits Up between 1 and Yes 0 No
65536
3.31.1 Advanced-control timers (TIM1, TIM8)

The advanced-control timers can each be seen as a three-phase PWM multiplexed on six
channels. They have complementary PWM outputs with programmable inserted dead-
times. They can also be seen as complete general-purpose timers.
The four independent channels can be used for:
• Input capture
• Output compare
• PWM generation (edge or center-aligned modes) with full modulation capability
(0 - 100 %)
• One-pulse mode output
In Debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled in order to turn off any power switches driven by these outputs.
Many features are shared with the general-purpose TIMx timers (described in the next
section) using the same architecture, so the advanced-control timers can work together with
the TIMx timers via the Timer Link feature for synchronization or event chaining.
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3.31.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16,

TIM17)
There are up to seven synchronizable general-purpose timers embedded in the
STM32H562xx and STM32H563xx devices (see Table 6 for differences). Each general-
purpose timer can be used to generate PWM outputs, or act as a simple time base.
• TIM2 and TIM5
They are full-featured general-purpose timers with 32-bit auto-reload up/downcounter
and 32-bit prescaler.
These timers feature four independent channels for input capture/output compare,
PWM or one-pulse mode output. They can work together, or with the other general-
purpose timers via the Timer Link feature for synchronization or event chaining.
The counters can be frozen in Debug mode.
All have independent DMA request generation and support quadrature encoders.
• TIM3 and TIM4
They are full-featured general-purpose timers with 16-bit auto-reload up/downcounter
and 16-bit prescaler.
These timers feature four independent channels for input capture/output compare,
PWM or one-pulse mode output.
They can work together, or with the other general-purpose timers via the Timer Link
feature for synchronization or event chaining.
The counters can be frozen in Debug mode. All have independent DMA request
generation and support quadrature encoders.
• TIM12, 13, 14, 15, 16 and 17
They are general-purpose timers with mid-range features.
They have 16-bit auto-reload upcounters and 16-bit prescalers.
– TIM12 and TIM15 have two channels and one complementary channel
– TIM13, TIM14, TIM16 and TIM17 have one channel and one complementary
channel
All channels can be used for input capture/output compare, PWM or one-pulse mode
output.
The timers can work together via the Timer Link feature for synchronization or event
chaining. The timers have independent DMA request generation.
The counters can be frozen in Debug mode.
3.31.3 Basic timers (TIM6 and TIM7)

The basic timers are mainly used for DAC trigger generation. They can also be used as
generic 16-bit timebase.
3.31.4 Low-power timers

(LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5, LPTIM6)
The devices embed six low-power timers. These timers have an independent clock and are
running in Stop mode if they are clocked by LSE, LSI or an external clock. They are able to
wake up the system from Stop mode.
The low-power timer supports the following features:
48/275 DS14258 Rev 1

• 16-bit up counter with 16-bit autoreload register

• 3-bit prescaler with eight possible dividing factors (1, 2, 4, 8, 16, 32, 64, 128)
• Selectable clock
– Internal clock sources: LSE, LSI, HSI or APB clock
– External clock source over LPTIM input (working with no LP oscillator running,
used by Pulse Counter application)
• 16 bit ARR autoreload register
• 16 bit capture/compare register
• Continuous/One-shot mode
• Selectable software/hardware input trigger
• Programmable digital glitch filter
• Configurable output: pulse, PWM
• Configurable I/O polarity
• Encoder mode (except on LPTIM4)
• Repetition counter
• Up to 2 independent channels (except for LPTIM4) for:
– Input capture
– PWM generation (edge-aligned mode)
– One-pulse mode output
• Interrupt generation on 10 events
• DMA request generation on the following events:
– Update event
– Input capture
3.31.5 Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and an 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC (LSI) and, as it operates independently
from the main clock, it can operate in Stop and Standby modes. It can be used either as a
watchdog to reset the device when a problem occurs, or as a free running timer for
application timeout management. It is hardware or software configurable through the option
bytes. The counter can be frozen in Debug mode.
3.31.6 Window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
Debug mode.
3.31.7 SysTick timer

The Cortex-M33 with TrustZone embeds two SysTick timers.
When TrustZone is activated, two SysTick timer are available:
• SysTick, secure instance
• SysTick, non-secure instance
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When TrustZone is disabled, only one SysTick timer is available. This timer (secure or non-
secure) is dedicated to real-time operating systems, but can also be used as a standard
down counter. It features:
• A 24-bit down counter
• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0
• Programmable clock source.
3.32 Real-time clock (RTC), tamper and backup registers
3.32.1 Real-time clock (RTC)

The RTC supports the following features:
• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), weekday, date,
month, year, in BCD (binary-coded decimal) format
• Binary mode with 32-bit free-running counter
• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month
• Two programmable alarms
• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock
• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision
• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy
• Timestamp feature that can be used to save the calendar content. This function can be
triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode
• 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period
– RTC fully securable
– Alarm A, alarm B, wakeup timer and timestamp individual secure or non-secure
configuration
– Alarm A, alarm B, wakeup timer and timestamp individual privileged protection
The RTC is supplied through a switch that takes power either from the VDD supply when
present or from the VBAT pin.
The RTC clock sources can be one of the following:
• 32.768 kHz external crystal (LSE)
• external resonator or oscillator (LSE)
• internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)
• high-speed external clock (HSE), divided by a prescaler in the RCC.
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in
all low-power modes.
50/275 DS14258 Rev 1

All RTC events (alarm, wakeup timer, timestamp) can generate an interrupt and wakeup the
device from the low-power modes.
3.32.2 Tamper and backup registers (TAMP)

The anti-tamper detection circuit is used to protect sensitive data from external attacks. 32
32-bit backup registers are retained in all low-power modes and also in VBAT mode. The
backup registers, as well as other secrets in the device, are protected by this anti-tamper
detection circuit with height tamper pins and nine internal tampers. The external tamper pins
can be configured for edge detection, or level detection with or without filtering, or active
tamper that increases the security level by auto checking that the tamper pins are not
externally opened or shorted.
TAMP main features:
• A tamper detection can erase the backup registers, backup SRAM, SRAM2, caches
and cryptographic peripherals.
• 32 32-bit backup registers:
– The backup registers (TAMP_BKPxR) are implemented in the Backup domain that
remains powered-on by VBAT when the VDD power is switched off.
• Up to 8 tamper pins for 8 external tamper detection events:
– Active tamper mode: continuous comparison between tamper output and input to
protect from physical open-short attacks
– Flexible active tamper I/O management: from 4 meshes (each input associated to
its own exclusive output) to 7 meshes (single output shared for up to 7 tamper
inputs)
– Passive tampers: ultra-low power edge or level detection with internal pull-up
hardware management
– Configurable digital filter
Note: As a tamper input, only PC13, PI8, PA0, PA1, and PA2 are functional in Standby and VBAT
modes. As a tamper output, only PC13, PA1, and PI8 are functional in Standby and VBAT
modes.
• Internal tamper events to protect against transient or environmental perturbation
attacks
• Each tamper can be configured in two modes:
– Hardware mode: immediate erase of secrets on tamper detection, including
backup registers erase
– Software mode: erase of secrets following a tamper detection launched by
software
• Any tamper detection can generate an RTC time stamp event.
– Tamper secure or non-secure configuration.
– Backup registers configuration in 3 configurable-size areas:
- 1 read/write secure area
- 1 write secure/read non-secure area
- 1 read/write non-secure area
– Secret key, stored in backup registers, protected against read and write access
• Tamper configuration and backup registers privilege protection
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• Monotonic counter
3.33 Inter-integrated circuit interface (I2C)

The device embeds four I2C. Refer to Table 7: I2C implementation for the features
implementation.
The I2C bus interface handles communications between the microcontroller and the serial
I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
• I2C-bus specification and user manual rev. 5 compatibility:
– Slave and Master modes, multimaster capability
– Standard-mode (Sm), with a bit rate up to 100 Kbit/s
– Fast-mode (Fm), with a bit rate up to 400 Kbit/s
– Fast-mode Plus (Fm+), with a bit rate up to 1 Mbit/s and 20 mA output drive I/Os
– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
– Programmable setup and hold times
– Optional clock stretching
• System management bus (SMBus) specification rev 3.0 compatibility:
– Hardware PEC (packet error checking) generation and verification with ACK
control
– Address resolution protocol (ARP) support
– SMBus alert
• Power system management protocol (PMBus) specification rev 1.3 compatibility
• Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming
• Wakeup from Stop capability
• Programmable analog and digital noise filters
• 1-byte buffer with DMA capability
Table 7. I2C implementation

I2C features(1) I2C1 I2C2 I2C3 I2C4
Standard-mode (up to 100 Kbit/s) X X X X

Fast-mode (up to 400 Kbit/s) X X X X
Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s) X X X X
Programmable analog and digital noise filters X X X X
SMBus/PMBus hardware support X X X X
Independent clock X X X X
Wakeup capability X X X X
1. X: supported
52/275 DS14258 Rev 1

3.34 Improved inter-integrated circuit (I3C)

The I3C interface handles communication between this device and others, like sensors and
host processor(s), that are all connected on an I3C bus.
The I3C peripheral implements all the required features of the MIPI I3C specification v1.1. It
can control all I3C bus-specific sequencing, protocol, arbitration and timing, and can be
acting as controller (formerly known as master) or as target (formerly known as slave).
The I3C peripheral, acting as controller, improves the features of the I2C interface still
preserving some backward compatibility: it allows an I2C target to operate on an I3C bus in
legacy I2C fast-mode (Fm) or legacy I2C fast-mode plus (Fm+), provided that this latter
does not perform clock stretching.
The I3C peripheral can be used with DMA in order to off-load the CPU.
Table 8. I3C peripheral controller/target features versus MIPI v1.1

I3C I3C
MIPI
peripheral peripheral
Feature I3C Comments
when when
v1.1
controller target
I3C SDR message X X X -

Mandatory when controller and the I3C bus
Legacy I2C message (Fm/Fm+) X X - is mixed with (external) legacy I2C target(s).
Optional in MIPI v1.1 when target.
HDR DDR message X - - Optional in MIPI v1.1
HDR-TSL/TSP, HDR-BT X - - Optional in MIPI v1.1
Dynamic address assignment X X X -
No (intended) support of I3C peripheral as a
Static address X X -
target on an I2C bus.
Grouped addressing X X - Optional in MIPI v1.1
Mandatory CCCs and some optional CCCs
CCCs X X X
are supported
Error detection and recovery X X X -
In-band interrupt (with MDB) X X X -
Secondary controller X X X -
Hot-join mechanism X X X -
Target reset X X X -
Synchronous timing control X X - Optional in MIPI v1.1
Asynchronous timing control 0 X X - Optional in MIPI v1.1
Asynchronous timing control 1,2, 3 X - - Optional in MIPI v1.1
Device to device tunneling X X - Optional in MIPI v1.1
Multi-lane data transfer X X - Optional in MIPI v1.1
Monitoring device early termination X - - Optional in MIPI v1.1
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3.35 Universal synchronous/asynchronous receiver transmitter

(USART/UART)
and low-power universal asynchronous receiver transmitter
(LPUART)
The devices have six embedded universal synchronous receiver transmitters
(USART1/USART2/USART3/USART6/USART10/USART11), six universal asynchronous
receiver transmitters (UART4/UART5/UART7/UART8/UART9/UART12) and one low-power
universal asynchronous receiver transmitter (LPUART1).
Table 9. USART, UART and LPUART features

USART1/2/3/6/ UART4/5/7/8/9/
USART modes/features(1) LPUART1
10/11 12
Hardware flow control for modem X X X

Continuous communication using DMA X X X
Multiprocessor communication X X X
Synchronous mode (master/slave) X - -
Smartcard mode X - -
Single-wire half-duplex communication X X X
IrDA SIR ENDEC block X X -
LIN mode X X -
(2)
Dual-clock domain and wakeup from Stop mode X X(2) X(2)
Receiver timeout interrupt X X -
Modbus communication X X -
Auto-baud rate detection X X -
Driver enable X X X
USART data length 7, 8 and 9 bits
Tx/Rx FIFO X X X
Tx/Rx FIFO size 8 bytes
1. X = supported.
2. Wakeup supported from Stop mode.
3.35.1 Universal synchronous/asynchronous receiver transmitter

(USART/UART)
The USART offers a flexible means to perform full-duplex data exchange with external
equipments requiring an industry standard NRZ asynchronous serial data format. A very
wide range of baud rates can be achieved through a fractional baud rate generator.
The USART supports both synchronous one-way and half-duplex single-wire
communications, as well as LIN (local interconnection network), Smartcard protocol, IrDA
(infrared data association) SIR ENDEC specifications, and modem operations (CTS/RTS).
Multiprocessor communications are also supported.
54/275 DS14258 Rev 1

High-speed data communications up to 20 Mbauds are possible by using the DMA (direct
memory access) for multibuffer configuration.
The USART main features are:
• Full-duplex asynchronous communication
• NRZ standard format (mark/space)
• Configurable oversampling method by 16 or 8 to achieve the best compromise
between speed and clock tolerance
• Baud rate generator systems
• Two internal FIFOs for transmit and receive data
Each FIFO can be enabled/disabled by software and come with a status flag.
• A common programmable transmit and receive baud rate
• Dual-clock domain with dedicated kernel clock for peripherals independent from PCLK
• Auto baud rate detection
• Programmable data word length (7, 8 or 9 bits)
• Programmable data order with MSB-first or LSB-first shifting
• Configurable stop bits (1 or 2 stop bits)
• Synchronous Master/Slave mode and clock output/input for synchronous
communications
• SPI slave transmission underrun error flag
• Single-wire half-duplex communications
• Continuous communications using DMA
• Received/transmitted bytes are buffered in reserved SRAM using centralized DMA
• Separate enable bits for transmitter and receiver
• Separate signal polarity control for transmission and reception
• Swappable Tx/Rx pin configuration
• Hardware flow control for modem and RS-485 transceiver
• Communication control/error detection flags
• Parity control:
– Transmits parity bit
– Checks parity of received data byte
• Interrupt sources with flags
• Multiprocessor communications: wakeup from Mute mode by idle line detection or
address mark detection
• Autonomous functionality in Stop mode with wakeup from stop capability
• LIN master synchronous break send capability and LIN slave break detection capability
– 13-bit break generation and 10/11 bit break detection when USART is hardware
configured for LIN
• IrDA SIR encoder decoder supporting 3/16 bit duration for Normal mode
• Smartcard mode
– Supports the T=0 and T=1 asynchronous protocols for smartcards as defined in
the ISO/IEC 7816-3 standard
– 0.5 and 1.5 stop bits for Smartcard operation
• Support for Modbus communication
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64
– Timeout feature
– CR/LF character recognition
3.35.2 Low-power universal asynchronous receiver transmitter (LPUART)

The LPUART supports bidirectional asynchronous serial communication with minimum
power consumption. It also supports half-duplex single-wire communication and modem
operations (CTS/RTS). It allows multiprocessor communication.
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to
9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame
while having an extremely low energy consumption. Higher-speed clock can be used to
reach higher baudrates.
The LPUART interface can be served by the DMA controller.
The LPUART main features are:
• Full-duplex asynchronous communications
• NRZ standard format (mark/space)
• Programmable baud rate
• From 300 baud/s to 9600 baud/s using a 32.768 kHz clock source
• Higher baud rates can be achieved by using a higher frequency clock source
• Two internal FIFOs to transmit and receive data
Each FIFO can be enabled/disabled by software and come with status flags for FIFOs
states.
• Dual-clock domain with dedicated kernel clock for peripherals independent from PCLK
• Programmable data word length (7 or 8 or 9 bits)
• Configurable stop bits (1 or 2 stop bits)
• Single-wire half-duplex communications
• Continuous communications using DMA
• Received/transmitted bytes are buffered in reserved SRAM using centralized DMA
• Separate enable bits for transmitter and receiver
• Separate signal polarity control for transmission and reception
• Swappable Tx/Rx pin configuration
• Hardware flow control for modem and RS-485 transceiver
• Transfer detection flags:
– Receive buffer full
– Transmit buffer empty
– Busy and end of transmission flags
• Parity control:
– Transmits parity bit
– Checks parity of received data byte
• Four error detection flags:
– Overrun error
– Noise detection
– Frame error
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– Parity error
• Interrupt sources with flags
• Multiprocessor communications: wakeup from Mute mode by idle line detection or
address mark detection
3.36 Serial peripheral interface (SPI) / inter-integrated sound

interfaces (I2S)
The devices embed six serial peripheral interfaces (SPI) that can be used to communicate
with external devices while using the specific synchronous protocol. The SPI protocol
supports half-duplex, full-duplex and simplex synchronous, serial communication with
external devices.
The interface can be configured as master or slave and can operate in multi-slave or multi-
master configurations. The device configured as master provides communication clock
(SCK) to the slave device. The slave select (SS) and ready (RDY) signals can be applied
optionally just to setup communication with concrete slave and to assure it handles the data
flow properly. The Motorola data format is used by default, but some other specific modes
are supported as well.
The SPI main features are:
• Full-duplex synchronous transfers on three lines
• Half-duplex synchronous transfer on two lines (with bidirectional data line)
• Simplex synchronous transfers on two lines (with unidirectional data line)
• 4-bit to 32-bit data size selection or fixed to 8-bit and 16-bit only
• Multi master or multi slave mode capability
• Dual-clock domain, separated clock for the peripheral kernel that can be independent
of PCLK
• Baud rate prescaler up to kernel frequency/2 or bypass from RCC in Master mode
• Protection of configuration and setting
• Hardware or software management of SS for both master and slave
• Adjustable minimum delays between data and between SS and data flow
• Configurable SS signal polarity and timing, MISO x MOSI swap capability
• Programmable clock polarity and phase
• Programmable number of data within a transaction to control SS and CRC
• Dedicated transmission and reception flags with interrupt capability
• SPI Motorola and TI formats support
• Hardware CRC feature can secure communication at the end of transaction by:
– Adding CRC value in Tx mode
– Automatic CRC error checking for Rx mode
• Error detection with interrupt capability in case of data overrun, CRC error, data
underrun at slave, mode fault at master
• Two 16x or 8x 8-bit embedded Rx and TxFIFOs with DMA capability
• Programmable number of data in transaction
DS14258 Rev 1 57/275

64
• Configurable FIFO thresholds (data packing)

• Configurable behavior at slave underrun condition (support of cascaded circular
buffers)
• Optional status pin RDY signalizing the slave device ready to handle the data flow.
Three standard I2S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available. They
can be operated in Master or Slave mode, in full-duplex communication modes, and can be
configured to operate with configurable resolutions as an input or output channel.
I2S main features:
• Full duplex communication
• Simplex communication (only transmitter or receiver)
• Master or slave operations
• 8-bit programmable linear prescaler
• Data length may be 16, 24 or 32 bits
• Channel length can be 16 or 32 in master, any value in slave
• Programmable clock polarity
• Error flags signaling for improved reliability: Underrun, Overrun and Frame Error
• Embedded Rx and TxFIFOs
• Supported I2S protocols:
– I2S Philips standard
– MSB-Justified standard (Left-Justified)
– LSB-Justified standard (Right-Justified)
– PCM standard (with short and long frame synchronization)
• Data ordering programmable (LSb or MSb first)
• DMA capability for transmission and reception
• Master clock can be output to drive an external audio component. The ratio is fixed at
256 x FWS (where FWS is the audio sampling frequency)
Table 10. SPI features

SPI1, SPI2, SPI3 SPI4, SPI5, SPI6
SPI feature
(full feature set instances) (limited feature set instance)
Data size Configurable from 4 to 32-bit 8/16-bit

CRC polynomial length CRC polynomial length
CRC computation
configurable from 5 to 33-bit configurable from 9 to 17-bit
Size of FIFOs 16x 8-bit 8x 8-bit
Number of transfered data Unlimited, expandable Up to 1024, no data counter
I2S feature Yes No
58/275 DS14258 Rev 1

3.37 Serial audio interfaces (SAI)

The devices embed two SAI. Refer to Table 11: SAI implementation for the features
implementation. The SAI bus interface handles communications between the
microcontroller and the serial audio protocol.
The SAI peripheral supports:
• Two independent audio sub-blocks that can be transmitters or receivers with their
respective FIFO
• 8-word integrated FIFOs for each audio sub-block
• Synchronous or Asynchronous mode between the audio sub-blocks
• Master or slave configuration independent for both audio sub-blocks
• Clock generator for each audio block to target independent audio frequency sampling
when both audio sub-blocks are configured in master mode
• Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit
• Peripheral with large configurability and flexibility allowing to target as example the
following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF
out
• Up to 16 slots available with configurable size and with the possibility to select which
ones are active in the audio frame
• Number of bits by frame may be configurable
• Frame synchronization active level configurable (offset, bit length, level)
• First active bit position in the slot is configurable
• LSB first or MSB first for data transfer
• Mute mode
• Stereo/mono audio frame capability
• Communication clock strobing edge configurable (SCK)
• Error flags with associated interrupts if enabled respectively
– Overrun and underrun detection
– Anticipated frame synchronization signal detection in Slave mode
– Late frame synchronization signal detection in Slave mode
– Codec not ready for the AC’97 mode in reception
• Interruption sources when enabled:
– Errors
– FIFO requests
• DMA interface with two dedicated channels to handle access to the dedicated
integrated FIFO of each SAI audio sub-block.
Table 11. SAI implementation

SAI features(1) SAI1 SAI2
I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 X X

Mute mode X X
Stereo/mono audio frame capability. X X
16 slots X X
DS14258 Rev 1 59/275

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Table 11. SAI implementation (continued)

SAI features(1) SAI1 SAI2
Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit X X

FIFO size X (8 words) X (8 words)
SPDIF X X
PDM X -
1. X: supported
3.38 Secure digital input/output and MultiMediaCards interface

(SDMMC)
The SD/SDIO, embedded MultiMediaCard (e•MMC™) host interface (SDMMC) provides an
interface between the AHB bus and SD memory cards, SDIO cards and e•MMC devices.
The MultiMediaCard system specifications are available through the MultiMediaCard
association website at www.mmca.org, published by the MMCA technical committee.
SD memory card and SD I/O card system specifications are available through the SD card
Association website at www.sdcard.org.
The SDMMC features include the following:
• Compliance with Embedded MultiMediaCard System Specification Version 5.1
Card support for three different databus modes: 1-bit (default), 4-bit and 8-bit
(HS200 SDMMC_CK speed limited to maximum allowed I/O speed) (HS400 is not
supported).
• Full compatibility with previous versions of MultiMediaCards (backward compatibility).
• Full compliance with SD memory card specifications version 6.0
(SDR104 SDMMC_CK speed limited to maximum allowed I/O speed, SPI mode and
UHS-II mode not supported).
• Full compliance with SDIO card specification version 4.0
Card support for two different databus modes: 1-bit (default) and 4-bit
(SDR104 SDMMC_CK speed limited to maximum allowed I/O speed, SPI mode and
UHS-II mode not supported).
• Data transfer up to 208 Mbyte/s for the 8-bit mode
(Depending maximum allowed I/O speed).
• Data and command output enable signals to control external bidirectional drivers
• IDMA linked list support
The MultiMediaCard/SD bus connects cards to the host.
The current version of the SDMMC supports only one SD/SDIO/e•MMC card at any one
time and a stack of e•MMC.
60/275 DS14258 Rev 1

Table 12. SDMMC features

SDMMC modes/features(1) SDMMC1 SDMMC2
Variable delay (SDR104, HS200) X X

SDMMC_CKIN X X
SDMMC_CDIR, SDMMC_D0DIR X -
SDMMC_D123DIR X -
1. X = supported.
When SDMMC peripherals are used simultaneously:

• Only one can be used in e•MMC with 8-bit bus width.
• Usage of SDMMC1 SDIO voltage switch use is mutually exclusive with SDMMC2
e•MMC with 8-bit bus width.
• If SDMMC1 has to support SDIO UHS-I modes (SDR12, SDR25, SDR50, SDR104 or
DDR50), then SDMMC2 cannot support e•MMC with 8-bit bus width.
• If SDMMC2 has to support e•MMC with 8-bit bus width, then SDMMC1 can only
support SDIO Default mode and High-speed mode.
3.39 Controller area network (FDCAN)

The controller area network (CAN) subsystem consists of one CAN module, a shared
message RAM memory and a configuration block.
The modules (FDCAN) are compliant with ISO 11898-1: 2015 (CAN protocol specification
version 2.0 part A, B) and CAN FD protocol specification version 1.0.
A 0.8-Kbyte message RAM implements filters, receives FIFOs, transmits event FIFOs and
transmits FIFOs.
The FDCAN main features are:
• Conform with CAN protocol version 2.0 part A, B and ISO 11898-1: 2015, -4
• CAN FD with maximum 64 data bytes supported
• CAN error logging
• AUTOSAR and J1939 support
• Improved acceptance filtering
• 2 receive FIFOs of three payloads each (up to 64 bytes per payload)
• Separate signaling on reception of high priority messages
• Configurable transmit FIFO / queue of three payload (up to 64 bytes per payload)
• Configurable transmit Event FIFO
• Programmable loop-back test mode
• Maskable module interrupts
• Two clock domains: APB bus interface and CAN core kernel clock
• Power-down support
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3.40 USB full speed (USB)

USB main features
• USB specification version 2.0 full-speed compliant
• Host and device functions
• 2048bytes of dedicated SRAM data buffer memory with 32-bit access
• USB clock recovery
• Configurable number of endpoints from 1 to 8
• Cyclic redundancy check (CRC) generation/checking, non-return-to-zero inverted
(NRZI) encoding/decoding and bit-stuffing
• Isochronous transfers support
• Double-buffered bulk/isochronous endpoint support
• USB suspend/resume operations
• Frame-locked clock pulse generation
• USB 2.0 Link power management support
• Battery charging specification revision 1.2 support in device
3.41 USB Type-C /USB Power Delivery controller (UCPD)

The device embeds one controller (UCPD) compliant with USB Type-C Cable and
Connector Specification release 2.0 and USB Power Delivery Rev. 3.0 specifications.
The controller uses specific I/Os supporting the USB Type-C and USB power delivery
requirements, featuring:
• USB Type-C pull-up (Rp, all values) and pull-down (Rd) resistors
• “Dead battery” support
• USB power delivery message transmission and reception
• FRS (fast role swap) support
The digital controller handles notably:
• USB Type-C level detection with debounce, generating interrupts
• FRS detection, generating an interrupt
• Byte-level interface for USB power delivery payload, generating interrupts (DMA
compatible)
• USB power delivery timing dividers (including a clock pre-scaler)
• CRC generation/checking
• 4b5b encode/decode
• Ordered sets (with a programmable ordered set mask at receive)
• Frequency recovery in receiver during preamble
The interface offers low-power operation compatible with Stop mode, maintaining the
capacity to detect incoming USB power delivery messages and FRS signaling.
62/275 DS14258 Rev 1

3.42 Ethernet MAC interface with dedicated DMA controller (ETH)

The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for
ethernet LAN communications through an industry-standard medium-independent interface
(MII) or a reduced medium-independent interface (RMII). The microcontroller requires an
external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair,
fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals
for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller.
The devices include the following features:
• Supports 10 and 100 Mbit/s rates
• Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM
and the descriptors
• Tagged MAC frame support (VLAN support)
• Half-duplex (CSMA/CD) and full-duplex operation
• MAC control sublayer (control frames) support
• 32-bit CRC generation and removal
• Several address filtering modes for physical and multicast address (multicast and
group addresses)
• 32-bit status code for each transmitted or received frame
• Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the
receive FIFO are both 2 Kbytes.
• Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008
(PTP V2) with the time stamp comparator connected to the TIM2 input
• Triggers interrupt when system time becomes greater than target time
3.43 High-definition multimedia interface (HDMI)

- consumer electronics control (CEC)
The devices embed a HDMI-CEC controller that provides hardware support for the
Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
overhead. It has a clock domain independent from the CPU clock, allowing the HDMI-CEC
controller to wakeup the MCU from Stop mode on data reception.
3.44 Development support
3.44.1 Serial-wire/JTAG debug port (SWJ-DP)

The Arm SWJ-DP interface is embedded and is a combined JTAG and serial-wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using two pins only instead of five required by the JTAG (JTAG pins can
be re-used as GPIO with alternate function): the JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
DS14258 Rev 1 63/275

64
3.44.2 Embedded Trace Macrocell

The Arm Embedded Trace Macrocell (ETM) provides a greater visibility of the instruction
and data flow inside the CPU core by streaming compressed data at a very high rate from
the devices through a small number of ETM pins to an external hardware trace port analyzer
(TPA) device.
Real-time instruction and data flow activity be recorded and then formatted for display on
the host computer that runs the debugger software. TPA hardware is commercially available
from common development tool vendors.
The ETM operates with third party debugger software tools.
64/275 DS14258 Rev 1

STM32H562xx and STM32H563xx Pinout, pin description and alternate function
4 Pinout, pin description and alternate function
4.1 Pinout/ballout schematics

Figure 5. LQFP64 pinout
BOOT0
VCAP
PC12
PC10
PC11
PA15
PA14
VDD
VSS
PD2
PB8
PB7
PB6
PB5
PB4
PB3
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VBAT 1 48 VDD
PC13 2 47 VSS
PC14-OSC32_IN 3 46 PA13
PC15-OSC32_OUT 4 45 PA12
PH0-OSC_IN 5 44 PA11
PH1-OSC_OUT 6 43 PA10
NRST 7 42 PA9
PC0 8 41 PA8
PC1 9 LQFP64 40 PC9
PC2 10 39 PC8
PC3 11 38 PC7
VSSA 12 37 PC6
VDDA 13 36 PB15
PA0 14 35 PB14
PA1 15 34 PB13
PA2 16 33 PB12
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VSS
VDD
PC4
PC5
PB0
PB1
PB2
VSS
PB10
VCAP
VDD
PA3
PA4
PA5
PA6
PA7
MSv67303V2
1. The above figure shows the package top view.
Figure 6. VFQFPN68 pinout

BOOT0
VCAP
PC12
PC10
PC11
PA15
PA14
VDD
VSS
PE0
PB9
PB8
PB7
PB6
PB5
PB4
PB3
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
VBAT 1 51 VDD
PC13 2 50 VSS
PC14-OSC32_IN 3 49 PA13
PH0-OSC_IN 5 47 PA11
PH1-OSC_OUT 6 46 PA10
NRST 7 45 PA9
PC0 8 44 PA8
PC1 9 VFQFPN68 43 PC9
PC2 10 42 PC8
PC3 11 41 PC7
VSSA 12 40 PC6
VDDA 13 39 PD12
PA0 14 38 PD11
PA1 15 37 PB15
PA2 16 36 PB14
PA3 17 35 PB13
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
VSS
VDD
PC4
PC5
PB0
PB1
PB2
PB10
VCAP
VSS
VDD
PB12
PA4
PA5
PA6
PA7
PB11
MSv67302V2
DS14258 Rev 1 65/275

77
Pinout, pin description and alternate function STM32H562xx and STM32H563xx
Figure 7. WLCSP80 SMPS ballout

1 2 3 4 5 6 7 8 9 10
A A1 A3 A5 A7 A9
B B2 B4 B6 B8 B10
C C1 C3 C5 C7 C9
D D2 D4 D6 D8 D10
E E1 E3 E5 E7 E9
F F2 F4 F6 F8 F10
G G1 G3 G5 G7 G9
H H2 H4 H6 H8 H10
J J1 J3 J5 J7 J9
K K2 K4 K6 K8 K10
L L1 L3 L5 L7 L9
M M2 M4 M6 M8 M10
N N1 N3 N5 N7 N9
P P2 P4 P6 P8 P10
R R1 R3 R5 R7 R9
T T2 T4 T6 T8 T10
MSv69915V1
66/275 DS14258 Rev 1

BOOT0
VCAP
PC10
PC12
PC11
PA14
PA15
VDD
VSS
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PE0
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PE2 1 75 VDD
PE3 2 74 VSS
PE4 3 73 VDDUSB
PE5 4 72 PA13
PE6 5 71 PA12
VBAT 6 70 PA11
PC13 7 69 PA10
PC14-OSC32_IN 8 68 PA9
VSS 10 66 PC9
VDD 11 65 PC8
PH0-OSC_IN 12 64 PC7
PH1-OSC_OUT 13 LQFP100 63 PC6
NRST 14 62 PD15
PC0 15 61 PD14
PC1 16 60 PD13
PC2 17 59 PD12
PC3 18 58 PD11
VSSA 19 57 PD10
VREF- 20 56 PD9
VREF+ 21 55 PD8
VDDA 22 54 PB15
PA0 23 53 PB14
PA1 24 52 PB13
PA2 25 51 PB12
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDD
VSS
PB10
VCAP
PE15
PE14
PE13
PE12
PE10
PE8
PE9
PE7
PB1
PB2
PC5
PB0
PC4
VDD
VSS
PE11
PA7
PA5
PA6
PA4
PA3
DS14258 Rev 1 67/275

77
Figure 9. LQFP100 SMPS pinout
BOOT0
VCAP
PC10
PC12
PC11
PA14
PA15
VDD
VSS
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PE0
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PE2 1 75 VDD
PE3 2 74 VSS
PE4 3 73 VDDUSB
PE5 4 72 PA13
PE6 5 71 PA12
VBAT 6 70 PA11
PC13 7 69 PA10
PC14-OSC32_IN 8 68 PA9
VSS 10 66 PC9
VDD 11 65 PC8
PH0-OSC_IN 12 64 PC7
PH1-OSC_OUT 13 LQFP100 63 PC6
NRST 14 62 PD15
PC0 15 61 PD14
PC1 16 60 PD13
PC2 17 59 PD12
PC3 18 58 PD11
VSSA 19 57 PD10
VREF+ 20 56 PD9
VDDA 21 55 PD8
PA0 22 54 PB15
PA1 23 53 PB14
PA2 24 52 PB13
PA3 25 51 VDD
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
VCAP
VSSSMPS
VDDSMPS
VLXSMPS
PB10
PE15
PE14
PE13
PE12
PE10
PE9
PE8
PE7
PB2
PB1
PB0
VDD
VSS
PB11
PE11
PA7
PA6
PA5
PA4
MSv64012V3
68/275 DS14258 Rev 1

VDDIO2
BOOT0
VCAP
PG15
PG14
PG13
PG12
PG10
PC12
PC10
PG11
PC11
PA15
PA14
VDD
VDD
VSS
VSS
PG9
VSS
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PE0
PB9
PB8
PB7
PB6
PB5
PB4
PB3
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
109
119
118
117
116
115
114
113
112
110
111
PE2 1 108 VDD
PE3 2 107 VSS
PE4 3 106 VDDUSB
PE5 4 105 PA13
PE6 5 104 PA12
VBAT 6 103 PA11
PC13 7 102 PA10
PC14-OSC32_IN 8 101 PA9
PF0 10 99 PC9
PF1 11 98 PC8
PF2 12 97 PC7
PF3 13 96 PC6
PF4 14 95 VDD
PF5 15 94 VSS
VSS 16 93 PG8
VDD 17 92 PG7
PF6 18 91 PG6
PF7 19 LQFP144 90 PG5
PF8 20 89 PG4
PF9 21 88 PG3
PF10 22 87 PG2
PH0-OSC_IN 23 86 PD15
PH1-OSC_OUT 24 85 PD14
NRST 25 84 VDD
PC0 26 83 VSS
PC1 27 82 PD13
PC2 28 81 PD12
PC3 29 80 PD11
VDD 30 79 PD10
VSSA 31 78 PD9
VREF+ 32 77 PD8
VDDA 33 76 PB15
PA0 34 75 PB14
PA1 35 74 PB13
PA2 36 73 PB12
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VSS
PG0
PG1
VDD
PC4
PC5
PB0
PB1
PB2
PF12
VSS
VDD
PF13
PF14
PF15
PE7
PE8
PE9
VSS
VSS
VDD
PE10
PE12
PE13
PE14
PE15
PB10
VCAP
VDD
PA3
PA4
PA5
PA6
PA7
PF11
PE11
MSv67305V3
DS14258 Rev 1 69/275

77
VDDIO2
BOOT0
VCAP
PG15
PG14
PG13
PG12
PG10
PC12
PC10
PC11
PA15
PA14
VDD
VDD
VSS
VSS
PG9
VSS
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8
PB7
PB6
PB5
PB4
PB3
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
109
119
118
117
116
115
114
113
112
110
111
PE2 1 108 VDD
PE3 2 107 VSS
PE4 3 106 VDDUSB
PE5 4 105 PA13
PE6 5 104 PA12
VBAT 6 103 PA11
PC13 7 102 PA10
PC14-OSC32_IN 8 101 PA9
PF0 10 99 PC9
PF1 11 98 PC8
PF2 12 97 PC7
PF3 13 96 PC6
PF4 14 95 VDD
PF5 15 94 VSS
VSS 16 93 PG8
VDD 17 92 PG7
PF6 18 91 PG6
PF7 19 LQFP144 90 PG5
PF8 20 89 PG4
PF9 21 88 PG3
PF10 22 87 PG2
NRST 25 84 VDD
PC0 26 83 VSS
PC1 27 82 PD13
PC2 28 81 PD12
PC3 29 80 PD11
VSSA 30 79 PD10
VREF+ 31 78 PD9
VDDA 32 77 PD8
PA0 33 76 PB15
PA1 34 75 PB14
PA2 35 74 PB13
PA3 36 73 VDD
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VSS
VSS
VDD
PB0
PB1
PB2
PF12
PF13
PE8
VSS
VDD
PF14
PF15
PG0
PG1
PE7
PE9
VLXSMPS
VDD
PE10
PE12
PE13
PE14
PE15
PB10
VDDSMPS
VSSSMPS
VCAP
VSS
PA4
PA5
PA6
PA7
PF11
PE11
PB11
MSv64013V3
70/275 DS14258 Rev 1

Figure 12. UFBGA169 ballout
1 2 3 4 5 6 7 8 9 10 11 12 13
A PE2 PI7 VDD PB9 PB6 PB4 VDDIO2 PG10 PD3 VDD PC11 PA14 PI2
PC14-
B OSC32 PE3 VSS VCAP BOOT0 PG15 VSS PD7 PC12 VSS PA15 PI1 PI0
_IN
PC15-
C OSC32 PE5 PI6 PI4 PE0 PB5 PG14 PG12 PD2 PC10 PI3 VSS VDD
_OUT
VDDUS
D VDD VSS PE6 PE4 PE1 PB7 PG13 PD5 PD0 PH14 PH15 PH13
B
E PF1 VBAT PI8 PC13 PB8 PB3 PG11 PD6 PD1 PA10 PA9 PA13 PA12
F PF4 PF2 PF0 PI11 PF3 PF5 PG9 PD4 PC6 PC7 PG8 PA8 PA11
G VDD VSS PF7 PF6 PF8 PF10 PE8 PG7 PG3 PG5 PG6 PC8 PC9
PH1-
PH0-
H OSC_IN
OSC_O PF9 NRST PC3 PC5 PF13 PE10 PD15 PD11 PD14 VSS VDD
UT
J PC0 PC1 PC2 PA0 PA1 PF11 PF15 PE14 PD9 PB15 PD10 PG2 PG4
K VREF- VSSA PH2 PA5 PA7 PB1 PG1 PE12 PB10 PH6 PB12 PD12 PD13
L VDDA VREF+ PA2 PA4 PB0 PB2 PG0 PE9 PE13 PH7 PB13 PD8 VDD
M VDD VSS PH5 VSS PA6 PF14 VSS PE11 PB11 PH8 PH10 VSS PB14
N PH4 PH3 PA3 VDD PC4 PF12 VDD PE7 PE15 VCAP VDD PH11 PH12
MSv68827V2
DS14258 Rev 1 71/275

77
Figure 13. UFBGA169 SMPS ballout
1 2 3 4 5 6 7 8 9 10 11 12 13
A PI7 PI6 VDD VCAP PB4 VDDIO2 PD5 VDD PC11 PC10 VDD PI3 PH15
B VDD VSS PI5 VSS BOOT0 PG15 PD7 VSS PD1 PA15 VSS PI0 PA12
C VBAT PE5 PE2 PI4 PE1 PB6 PG10 PD3 PD0 PA14 PI1 PH13 PA11
PC14-
D OSC32 PE6 PE4 PE3 PE0 PB7 PG12 PD4 PC12 PI2 PH14 PA13 VDD
_IN
PC15-
VDDUS
E OSC32 PF0 PC13 PI8 PB9 PB5 PG9 PD2 PC8 PA8 PA10 VSS
B
_OUT
F PF7 VSS PF1 PF2 PB8 PB3 PD6 PG5 PG7 PC6 PC7 PC9 PA9
G VDD PF9 PF5 PF8 PF4 PF3 PF6 PD13 PG3 PD15 PG4 PG6 PG8
PH0-
H OSC_IN
VSS NRST PF10 PA1 PB1 PF13 PD11 PD9 PB15 PD12 PD14 PG2
PH1-
J OSC_O PC0 PC1 PH2 PA5 PF11 PF15 PE8 PE14 PB14 PD8 VSS VDD
UT
K PC2 PC3 PA0 PA3 PA7 PF12 PG1 PE13 PB10 PH10 PB12 PB13 PD10
L VSSA VREF- PA2 PH5 PC4 PF14 PE7 PE10 PE15 PB11 PH7 PH12 PH11
VSSSM
M VDDA VREF+ VSS PA4 PC5 PG0 VSS PE11 PE12
PS
VSS PH8 PH9
VLXSM VDDSM
N PH4 PH3 VDD PA6 PB0 PB2 VDD PE9
PS PS
VCAP VDD PH6
MSv64014V3
72/275 DS14258 Rev 1

VDDIO2
BOOT0
VCAP
PG13
PG12
PG10
PG11
PG15
PG14
PC12
PC10
PC11
PA15
PA14
VDD
VDD
VDD
PG9
VSS
PD7
PD6
PD5
PD4
PD3
VSS
VSS
PE1
PE0
PD2
PD1
PD0
PB9
PB8
PB7
PB6
PB5
PB4
PB3
PI7
PI6
PI5
PI4
PI3
PI2
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
PE2 1 132 PI1
PE3 2 131 PI0
PE4 3 130 PH15
PE5 4 129 PH14
PE6 5 128 PH13
VBAT 6 127 VDD
PI8 7 126 VSS
PC13 8 125 VDDUSB
PC14-OSC32_IN 9 124 PA13
PC15-OSC32_OUT 10 123 PA12
PI9 11 122 PA11
PI10 12 121 PA10
PI11 13 120 PA9
VSS 14 119 PA8
VDD 15 118 PC9
PF0 16 117 PC8
PF1 17 116 PC7
PF2 18 115 PC6
PF3 19 114 VDD
PF4 20 113 VSS
PF5 21 112 PG8
VSS 22 111 PG7
VDD 23 LQFP176 110 PG6
PF6 24 109 PG5
PF7 25 108 PG4
PF8 26 107 PG3
PF9 27 106 PG2
PF10 28 105 PD15
PH1-OSC_OUT 30 103 VDD
NRST 31 102 VSS
PC0 32 101 PD13
PC1 33 100 PD12
PC2 34 99 PD11
PC3 35 98 PD10
VDD 36 97 PD9
VSSA 37 96 PD8
VREF+ 38 95 PB15
VDDA 39 94 PB14
PA0 40 93 PB13
PA1 41 92 PB12
PA2 42 91 VDD
PH2 43 90 PH12
PH3 44 89 PH11
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
PH4
PH5
VSS
VDD
PC4
PC5
PB0
PB1
PB2
PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10
PE12
PE13
PE14
PE15
PB10
VCAP
VSS
VDD
PH6
PH7
PH8
PH9
PH10
PA3
PA4
PA5
PA6
PA7
PF11
PE11
PB11
MSv67307V3
DS14258 Rev 1 73/275

77
VDDIO2
BOOT0
VCAP
PG13
PG12
PG10
PG11
PG15
PG14
PC12
PC10
PC11
PA15
PA14
VDD
VDD
VDD
PG9
VSS
PD7
PD6
PD5
PD4
PD3
VSS
VSS
PE1
PE0
PD2
PD1
PD0
PB9
PB8
PB7
PB6
PB5
PB4
PB3
PI7
PI6
PI5
PI4
PI3
PI2
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
PE2 1 132 PI1
PE3 2 131 PI0
PE4 3 130 PH15
PE5 4 129 PH14
PE6 5 128 PH13
VBAT 6 127 VDD
PI8 7 126 VSS
PC13 8 125 VDDUSB
PC14-OSC32_IN 9 124 PA13
PC15-OSC32_OUT 10 123 PA12
PI9 11 122 PA11
PI10 12 121 PA10
PI11 13 120 PA9
VSS 14 119 PA8
VDD 15 118 PC9
PF0 16 117 PC8
PF1 17 116 PC7
PF2 18 115 PC6
PF3 19 114 VDD
PF4 20 113 VSS
PF5 21 112 PG8
VSS 22 111 PG7
VDD 23 LQFP176 110 PG6
PF6 24 109 PG5
PF7 25 108 PG4
PF8 26 107 PG3
PF9 27 106 PG2
NRST 30 103 VDD
PC0 31 102 VSS
PC1 32 101 PD13
PC2 33 100 PD12
PC3 34 99 PD11
VDD 35 98 PD10
VSSA 36 97 PD9
VREF+ 37 96 PD8
VDDA 38 95 PB15
PA0 39 94 PB14
PA1 40 93 PB13
PA2 41 92 PB12
PH2 42 91 VDD
PH3 43 90 VSS
PA3 44 89 PH12
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
VSS
VDD
PC4
PC5
PB0
PB1
PB2
PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10
PE12
PE14
PB10
VLXSMPS
PE13
PE15
VDDSMPS
VSSSMPS
VCAP
VSS
VDD
PH6
PH7
PH9
PH10
PA4
PA5
PA6
PA7
PF11
PE11
PB11
PH11
MSv67301V3
74/275 DS14258 Rev 1

Figure 16. UFBGA176+25 ballout
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A PE3 PE2 PE1 PE0 PB8 PB5 PG14 PG13 PB4 PB3 PD7 PC12 PA15 PA14 PA13
B PE4 PE5 PE6 PB9 PB7 PB6 PG15 PG12 PG11 PG10 PD6 PD0 PC11 PC10 PA12
C VBAT PI7 PI6 PI5 VDD VCAP VDD VDDIO2 VDD PG9 PD5 PD1 PI3 PI2 PA11
D PC13 PI8 PI9 PI4 VSS BOOT0 VSS VSS VSS PD4 PD3 PD2 PH15 PI1 PA10
PC14-
E OSC32_ PF0 PI10 PI11 PH13 PH14 PI0 PA9
IN
PC15-
F OSC32_ VSS VDD PH2 VSS VSS VSS VSS VSS VSS VDD PC9 PA8
OUT
PH0-
G OSC_IN
VSS VDD PH3 VSS VSS VSS VSS VSS VSS VDD PC8 PC7
PH1-
VDDUS
H OSC_O PF2 PF1 PH4 VSS VSS VSS VSS VSS VSS
B
PG8 PC6
UT
J NRST PF3 PF4 PH5 VSS VSS VSS VSS VSS VDD VDD PG7 PG6
K PF7 PF6 PF5 VDD VSS VSS VSS VSS VSS PH12 PG5 PG4 PG3
L PF10 PF9 PF8 VSS PH11 PH10 PD15 PG2
M VSSA PC0 PC1 PC2 PC3 PB2 PG1 VSS VSS VCAP PH6 PH8 PH9 PD14 PD13
N VREF- PA1 PA0 PA4 PC4 PF13 PG0 VDD VDD VDD PE13 PH7 PD12 PD11 PD10
P VREF+ PA2 PA6 PA5 PC5 PF12 PF15 PE8 PE9 PE11 PE14 PB12 PB13 PD9 PD8
R VDDA PA3 PA7 PB1 PB0 PF11 PF14 PE7 PE10 PE12 PE15 PB10 PB11 PB14 PB15
MSv67306V3
DS14258 Rev 1 75/275

77
Figure 17. UFBGA176+25 SMPS ballout

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A PI7 PI5 VCAP PB9 BOOT0 PB5 PG15 PG13 PG10 PD7 PD5 PD3 PD1 PI3 PI1
B VBAT PE3 PI4 PE1 PB8 PB6 PB3 PG12 PG9 PD6 PD4 PD0 PA14 PI2 PH13
C VSS PE6 PE4 PI6 PE0 PB7 PB4 PG13 PG11 PD2 PC12 PC11 PA15 PH15 PA12
PC15- PC14-
D OSC32_ OSC32_ PE5 PE2 VDD VSS VDDIO2 VDD VSS VDD VSS PC10 PH14 VSS PA11
OUT IN
E PI9 PI8 PC13 VDD VDD PA13 PA10 PA9
VDD33U
F PF1 PF0 PI11 PI10 VSS VSS VSS VSS VSS
SB
PC9 PC8 PA8
G PF4 PF3 PF2 VSS VSS VSS VSS VSS VSS VSS PC7 PC6 PG8
H PF6 PF8 PF5 VDD VSS VSS VSS VSS VSS VSS PG7 PG3 PG5
PH1-
PH0-
J OSC_IN
OSC_O PF9 PF10 VSS VSS VSS VSS VSS VDD PD15 PG6 PG4
UT
K VSS PF7 NRST PC2 VSS VSS VSS VSS VSS PD10 PD14 PD12 PG2
L PC0 PC1 PA1 VDD PB12 PD9 PD11 PD13
M VDDA VSSA PA2 VSS PA4 VDD VSS VDD VSS PB10 VDD PH9 PH12 PB15 PD8
N VREF+ VREF- PC3 PC4 PA3 PB1 PF12 PF15 PE9 PE14 PE15 PB11 PH8 PH10 PB14
VSSSM
P PH5 PA0 PH3 PC5 PA6 PB2 PF13 PG1 PE8 PE11 PE13
PS
PH6 PH7 PH11
VLXSM VDDSM
R PH4 PH2 PA5 PA7 PB0 PF11 PF14 PG0 PE7 PE10 PE12
PS PS
VCAP PB13
MSv67300V2
76/275 DS14258 Rev 1

4.2 Pin description

Table 13. Legend/abbreviations used in the pinout table
Name Abbreviation Definition
Unless otherwise specified in brackets below the pin name, the pin function during
Pin name
and after reset is the same as the actual pin name
S Supply pin
Pin type I Input only pin
I/O Input/output pin
FT 5V-tolerant I/O
TT 3.6V-tolerant I/O
Bidirectional reset pin with embedded weak pull-up
RST
resistor
Option for TT or FT I/Os(1)
_a I/O, with analog switch function supplied by VDDA
I/O structure _c I/O with USB Type-C power delivery function

_d I/O with USB Type-C power delivery dead battery function
_f I/O, Fm+ capable
_h I/O with high-speed low-voltage mode
_s I/O supplied only by VDDIO2
_t I/O with tamper function functional in VBAT mode
_u I/O, with USB function supplied by VDDUSB
Unless otherwise specified by a note, all I/Os are set as analog inputs during and after
Notes
reset.
Alternate
Functions selected through GPIOx_AFR registers
Pin functions
functions Additional
Functions directly selected/enabled through peripheral registers
functions
1. The related I/O structures in the table below are a concatenation of various options. Examples: FT_hat, FT_fs, FT_u, TT_a.
DS14258 Rev 1 77/275

77
78/275
Table 14. STM32H562xx and STM32H563xx pin/ball definition
Pin number(1)(2)
Pin name (function after
Additional functions
Alternate functions
UFBGA176+25 SMPS
I/O structure
UFBGA169 SMPS
WLCSP80 SMPS
LQFP100 SMPS
LQFP144 SMPS
LQFP176 SMPS
reset)(3)(4)
UFBGA176+25
Pin type
Notes
UFBGA169
VFQFPN68
LQFP100
LQFP144
LQFP176
LQFP64
TRACECLK, LPTIM1_IN2,
SAI1_CK1, SPI4_SCK,
SAI1_MCLK_A, USART10_RX,
- 1 1 C3 1 D4 - 1 1 A1 1 A2 - PE2 I/O FT_h - -
UART8_TX, OCTOSPI1_IO2,
ETH_MII_TXD3, FMC_A23,
DCMI_D3/PSSI_D3, EVENTOUT
DS14258 Rev 1
TRACED0, TIM15_BKIN,
- 2 2 D4 2 B2 - 2 2 B2 2 A1 - PE3 I/O FT_h - SAI1_SD_B, USART10_TX, TAMP_IN6/TAMP_OUT3
FMC_A19, EVENTOUT
TRACED1, SAI1_D2,
TIM15_CH1N, SPI4_NSS,
- 3 3 D3 3 C3 - 3 3 D4 3 B1 - PE4 I/O FT_h - TAMP_IN7/TAMP_OUT8
SAI1_FS_A, FMC_A20,
TRACED2, SAI1_CK2,
TIM15_CH1, SPI4_MISO,

- 4 4 C2 4 D3 - 4 4 C2 4 B2 - PE5 I/O FT_h - TAMP_IN8/TAMP_OUT7
SAI1_SCK_A, FMC_A21,
TRACED3, TIM1_BKIN2,
SAI1_D1, TIM15_CH2,
- 5 5 D2 5 C2 - 5 5 D3 5 B3 - PE6 I/O FT_h - SPI4_MOSI, SAI1_SD_A, TAMP_IN3/TAMP_OUT6
SAI2_MCLK_B, FMC_A22,
A1 - - - - - - - - - - - - VDD S - - - -
B8 - - - - - - - - - - - - VSS S - - - -
B10 6 6 C1 6 B1 1 6 6 E2 6 C1 1 VBAT S - - - -
D2 - - - - - - - - - - - - VSS S - - - -
Table 14. STM32H562xx and STM32H563xx pin/ball definition (continued)

Pin number(1)(2)
Alternate functions
UFBGA176+25 SMPS
I/O structure
UFBGA169 SMPS
WLCSP80 SMPS
LQFP100 SMPS
LQFP144 SMPS
LQFP176 SMPS
reset)(3)(4)
UFBGA176+25
Pin type
Notes
UFBGA169
VFQFPN68
LQFP100
LQFP144
LQFP176
LQFP64
(5) TAMP_IN2/TAMP_OUT3,
- - - E4 7 E2 - - - E3 7 D2 - PI8 I/O FT_t EVENTOUT
RTC_OUT2, WKUP3
TAMP_IN1/TAMP_OUT2/
(5)
C9 7 7 E3 8 E3 2 7 7 E4 8 D1 2 PC13 I/O FT_t EVENTOUT TAMP_OUT3, RTC_OUT1/
RTC_TS, WKUP4
G9 - - - - - - - - - - - - VSS S - - - -
DS14258 Rev 1
PC14-
OSC32_
D10 8 8 D1 9 D2 3 8 8 B1 9 E1 3 I/O FT - EVENTOUT OSC32_IN
IN
(OSC32_IN)
PC15-
OSC32_OU
F10 9 9 E1 10 D1 4 9 9 C1 10 F1 4 T I/O FT - EVENTOUT OSC32_OUT
(OSC32_O
UT)
UART4_RX, FDCAN1_RX,
- - - - 11 E1 - - - - 11 D3 - PI9 I/O FT_h - -
EVENTOUT
FDCAN1_RX, ETH_MII_RX_ER,
- - - - 12 F4 - - - - 12 E3 - PI10 I/O FT_h - -
PSSI_D14, EVENTOUT
- - - - 13 F3 - - - F4 13 E4 - PI11 I/O FT - PSSI_D15, EVENTOUT TAMP_IN4/TAMP_OUT5
- - - B2 14 C1 - - - D2 14 D5 - VSS S - - - -
- - - B1 15 D5 - - - D1 15 C5 - VDD S - - - -
I2C2_SDA, FMC_A0,
- - 10 E2 16 F2 - - 10 F3 16 E2 - PF0 I/O FT_f - -
LPTIM5_CH1, EVENTOUT
79/275
I2C2_SCL, FMC_A1,
- - 11 F3 17 F1 - - 11 E1 17 H3 - PF1 I/O FT_f - -
80/275 Pin number(1)(2)
Alternate functions
UFBGA176+25 SMPS
I/O structure
UFBGA169 SMPS
WLCSP80 SMPS
LQFP100 SMPS
LQFP144 SMPS
LQFP176 SMPS
reset)(3)(4)
UFBGA176+25
Pin type
Notes
UFBGA169
VFQFPN68
LQFP100
LQFP144
LQFP176
LQFP64
LPTIM3_CH2, LPTIM3_IN2,
I2C2_SMBA, UART12_TX,
- - 12 F4 18 G3 - - 12 F2 18 H2 - PF2 I/O FT_h - -
USART11_CK, FMC_A2,
LPTIM5_IN1, EVENTOUT
LPTIM3_IN1, USART11_TX,
- - 13 G6 19 G2 - - 13 F5 19 J2 - PF3 I/O FT_h - FMC_A3, LPTIM5_IN2, -
EVENTOUT
DS14258 Rev 1
LPTIM3_ETR, USART11_RX,
- - 14 G5 20 G1 - - 14 F1 20 J3 - PF4 I/O FT_h - -
FMC_A4, EVENTOUT
LPTIM3_CH1, I2C4_SCL,
I3C1_SCL, UART12_RX,
- - 15 G3 21 H3 - - 15 F6 21 K3 - PF5 I/O FT_fh - USART11_CTS/USART11_NSS, -
FMC_A5, LPTIM3_IN1,
EVENTOUT
H2 10 16 F2 22 G4 - 10 16 G2 22 F2 - VSS S - - - -

A7 11 17 G1 23 E4 - 11 17 G1 23 F3 - VDD S - - - -
TIM16_CH1, SPI5_NSS,
SAI1_SD_B, UART7_RX,
- - 18 G7 24 H1 - - 18 G4 24 K2 - PF6 I/O FT_h - -
OCTOSPI1_IO3, LPTIM5_CH1,
EVENTOUT
TIM17_CH1, SPI5_SCK,
SAI1_MCLK_B, UART7_TX,
- - 19 F1 25 K2 - - 19 G3 25 K1 - PF7 I/O FT_h - -
OCTOSPI1_IO2, LPTIM5_CH2,
EVENTOUT

Pin number(1)(2)
Alternate functions
UFBGA176+25 SMPS
I/O structure
UFBGA169 SMPS
WLCSP80 SMPS
LQFP100 SMPS
LQFP144 SMPS
LQFP176 SMPS
reset)(3)(4)
UFBGA176+25
Pin type
Notes
UFBGA169
VFQFPN68
LQFP100
LQFP144
LQFP176
LQFP64
TIM16_CH1N, SPI5_MISO,
SAI1_SCK_B, UART7_RTS,
- - 20 G4 26 H2 - - 20 G5 26 L3 - PF8 I/O FT_h - -
TIM13_CH1, OCTOSPI1_IO0,
TIM17_CH1N, SPI5_MOSI,
SAI1_FS_B, UART7_CTS,
- - 21 G2 27 J3 - - 21 H3 27 L2 - PF9 I/O FT_h - -
TIM14_CH1, OCTOSPI1_IO1,
DS14258 Rev 1
TIM16_BKIN, SAI1_D3,
PSSI_D15, OCTOSPI1_CLK,
- - 22 H4 - J4 - - 22 G6 28 L1 - PF10 I/O FT_h - -
DCMI_D11/PSSI_D11,
EVENTOUT
PH0-
K10 12 23 H1 28 J1 5 12 23 H1 29 G1 5 OSC_IN(PH I/O FT - EVENTOUT OSC_IN
0)
PH1-
J9 13 24 J1 29 J2 6 13 24 H2 30 H1 6 OSC_OUT( I/O FT - EVENTOUT OSC_OUT
PH1)
F8 14 25 H3 30 K3 7 14 25 H4 31 J1 7 NRST I/O RST - - -

TIM16_BKIN, SAI1_MCLK_A,
SPI2_RDY, SAI2_FS_B,
H8 15 26 J2 31 L1 8 15 26 J1 32 M2 8 PC0 I/O FT_a - ADC12_INP10
FMC_A25, OCTOSPI1_IO7,
FMC_SDNWE, EVENTOUT
81/275
82/275 Pin number(1)(2)
Alternate functions
UFBGA176+25 SMPS
I/O structure
UFBGA169 SMPS
WLCSP80 SMPS
LQFP100 SMPS
LQFP144 SMPS
LQFP176 SMPS
reset)(3)(4)
UFBGA176+25
Pin type
Notes
UFBGA169
VFQFPN68
LQFP100
LQFP144
LQFP176
LQFP64
TRACED0, SAI1_D1,
SPI2_MOSI/I2S2_SDO, ADC12_INP11,
SAI1_SD_A, USART11_RTS, ADC12_INN10,
G7 16 27 J3 32 L2 9 16 27 J2 33 M3 9 PC1 I/O FT_ah -
SAI2_SD_A, SDMMC2_CK, TAMP_IN3/TAMP_OUT5,
OCTOSPI1_IO4, ETH_MDC, WKUP6
EVENTOUT
PWR_CSLEEP, TIM17_CH1,
DS14258 Rev 1
TIM4_CH4,
SPI2_MISO/I2S2_SDI,
ADC12_INP12,
M10 17 28 K1 33 K4 10 17 28 J3 34 M4 10 PC2 I/O FT_a - OCTOSPI1_IO5,
ADC12_INN11
OCTOSPI1_IO2,
ETH_MII_TXD2, FMC_SDNE0,
EVENTOUT
PWR_CSTOP, SAI1_D3,
LPTIM3_CH1,
SPI2_MOSI/I2S2_SDO,
ADC12_INP13,
L9 18 29 K2 34 N3 11 18 29 H5 35 M5 11 PC3 I/O FT_a - OCTOSPI1_IO6,

ADC12_INN12
OCTOSPI1_IO0,
ETH_MII_TX_CLK,
FMC_SDCKE0, EVENTOUT
G1 - - - 35 H4 - - 30 M1 36 G3 - VDD S - - - -
P2 - - H2 - K1 - - - M2 - G2 - VSS S - - - -
N9 19 30 L1 36 M2 12 19 31 K2 37 M1 12 VSSA S - - - -
- - - L2 - N2 - 20 - K1 - N1 - VREF- S - - - -
- 20 31 M2 37 N1 - 21 32 L2 38 P1 - VREF+ S - - - -
P10 21 32 M1 38 M1 13 22 33 L1 39 R1 13 VDDA S - - - -

Pin number(1)(2)
Alternate functions
UFBGA176+25 SMPS
I/O structure
UFBGA169 SMPS
WLCSP80 SMPS
LQFP100 SMPS
LQFP144 SMPS
LQFP176 SMPS
reset)(3)(4)
UFBGA176+25
Pin type
Notes
UFBGA169
VFQFPN68
LQFP100
LQFP144
LQFP176
LQFP64
TIM2_CH1, TIM5_CH1,
TIM8_ETR, TIM15_BKIN,
ADC12_INP0,
SPI6_NSS, SPI3_RDY,
(5) ADC12_INN1,
K8 22 33 K3 39 P2 14 23 34 J4 40 N3 14 PA0 I/O FT_at USART2_CTS/USART2_NSS,
TAMP_IN2/TAMP_OUT1,
UART4_TX, SDMMC2_CMD,
WKUP1
SAI2_SD_B, ETH_MII_CRS,
TIM2_ETR, EVENTOUT
DS14258 Rev 1
TIM2_CH2, TIM5_CH2,
TIM15_CH1N, LPTIM1_IN1,
OCTOSPI1_DQS,
(5) ADC12_INP1,
J7 23 34 H5 40 L3 15 24 35 J5 41 N2 15 PA1 I/O FT_aht USART2_RTS, UART4_RX,
TAMP_IN5/TAMP_OUT4
OCTOSPI1_IO3, SAI2_MCLK_B,
ETH_MII_RX_CLK/ETH_RMII_R
EF_CLK, EVENTOUT
TIM2_CH3, TIM5_CH3,
ADC12_INP14,
(5) TIM15_CH1, LPTIM1_IN2,
M8 24 35 L3 41 M3 16 25 36 L3 42 P2 16 PA2 I/O FT_hat TAMP_IN4/TAMP_OUT3,
USART2_TX, SAI2_SCK_B,
WKUP2
ETH_MDIO, EVENTOUT
LPTIM1_IN2, OCTOSPI1_IO4,
- - - J4 42 R2 - - - K3 43 F4 - PH2 I/O FT_h - SAI2_SCK_B, ETH_MII_CRS, -
FMC_SDCKE0, EVENTOUT
H10 - - - - L4 - - - - - K4 - VDD S - - - -
P8 - - - - M4 - - - - - L4 - VSS S - - - -
OCTOSPI1_IO5, SAI2_MCLK_B,
- - - N2 43 P3 - - - N2 44 G4 - PH3 I/O FT_ah - ETH_MII_COL, FMC_SDNE0, -
EVENTOUT
83/275
84/275 Pin number(1)(2)
Alternate functions
UFBGA176+25 SMPS
I/O structure
UFBGA169 SMPS
WLCSP80 SMPS
LQFP100 SMPS
LQFP144 SMPS
LQFP176 SMPS
reset)(3)(4)
UFBGA176+25
Pin type
Notes
UFBGA169
VFQFPN68
LQFP100
LQFP144
LQFP176
LQFP64
I2C2_SCL, SPI5_RDY,
- - - N1 - R1 - - - N1 45 H4 - PH4 I/O FT_fa - SPI6_RDY, PSSI_D14, -
EVENTOUT
I2C2_SDA, SPI5_NSS,
- - - L4 - P1 - - - M3 46 J4 - PH5 I/O FT_fa - SPI6_RDY, FMC_SDNWE, -
EVENTOUT
DS14258 Rev 1
TIM2_CH4, TIM5_CH4,
OCTOSPI1_CLK, TIM15_CH2,
T10 25 36 K4 44 N5 17 26 37 N3 47 R2 17 PA3 I/O FT_ah - SPI2_NSS/I2S2_WS, ADC12_INP15
SAI1_SD_B, USART2_RX,
ETH_MII_COL, EVENTOUT
- 26 37 M3 45 M7 18 27 38 M4 48 M8 18 VSS S - - - -
R1 27 38 N3 46 M6 19 28 39 N4 49 N8 19 VDD S - - - -
TIM5_ETR, LPTIM2_CH1,
SPI1_NSS/I2S1_WS,

SPI3_NSS/I2S3_WS, ADC12_INP18,
R9 28 39 M4 47 M5 20 29 40 L4 50 N4 20 PA4 I/O TT_a -
USART2_CK, SPI6_NSS, DAC1_OUT1
DCMI_HSYNC/PSSI_DE,
EVENTOUT
TIM2_CH1, TIM8_CH1N,
SPI1_SCK/I2S1_CK, SPI6_SCK, ADC12_INP19,
L7 29 40 J5 48 R3 21 30 41 K4 51 P4 21 PA5 I/O TT_ah - ETH_MII_TX_EN/ETH_RMII_TX ADC12_INN18,
_EN, PSSI_D14, TIM2_ETR, DAC1_OUT2
EVENTOUT

Pin number(1)(2)
Alternate functions
UFBGA176+25 SMPS
I/O structure
UFBGA169 SMPS
WLCSP80 SMPS
LQFP100 SMPS
LQFP144 SMPS
LQFP176 SMPS
reset)(3)(4)
UFBGA176+25
Pin type
Notes
UFBGA169
VFQFPN68
LQFP100
LQFP144
LQFP176
LQFP64
TIM1_BKIN, TIM3_CH1,
TIM8_BKIN,
SPI1_MISO/I2S1_SDI,
H6 30 41 N4 49 P5 22 31 42 M5 52 P3 22 PA6 I/O FT_ah - OCTOSPI1_IO3, USART11_TX, ADC12_INP3
SPI6_MISO, TIM13_CH1,
DCMI_PIXCLK/PSSI_PDCK,
EVENTOUT
DS14258 Rev 1
TIM1_CH1N, TIM3_CH2,
TIM8_CH1N,
SPI1_MOSI/I2S1_SDO,
USART11_RX, SPI6_MOSI, ADC12_INP7,
K6 31 42 K5 50 R4 23 32 43 K5 53 R3 23 PA7 I/O FT_ah -
TIM14_CH1, OCTOSPI1_IO2, ADC12_INN3
ETH_MII_RX_DV/ETH_RMII_CR
S_DV, FMC_SDNWE,
FMC_NWE, EVENTOUT
TIM2_CH4, SAI1_CK1,
LPTIM2_ETR, I2S1_MCK,
M6 - - L5 51 N4 24 33 44 N5 54 N5 24 PC4 I/O FT_a - USART3_RX, ADC12_INP4
ETH_MII_RXD0/ETH_RMII_RXD
0, FMC_SDNE0, EVENTOUT
TIM1_CH4N, SAI1_D3,
PSSI_D15, SAI1_FS_A,
UART12_RTS, ADC12_INP8,
N7 - - M5 52 P4 25 34 45 H6 55 P5 25 PC5 I/O FT_ah -
OCTOSPI1_DQS, ADC12_INN4
ETH_MII_RXD1/ETH_RMII_RXD
1, FMC_SDCKE0, EVENTOUT
T8 - - - - M8 - - - - - - - VDD S - - - -
85/275
86/275 Pin number(1)(2)
Alternate functions
UFBGA176+25 SMPS
I/O structure
UFBGA169 SMPS
WLCSP80 SMPS
LQFP100 SMPS
LQFP144 SMPS
LQFP176 SMPS
reset)(3)(4)
UFBGA176+25
Pin type
Notes
UFBGA169
VFQFPN68
LQFP100
LQFP144
LQFP176
LQFP64
TIM8_CH2N, OCTOSPI1_IO1,
ADC12_INP9,
R7 32 43 N5 53 R5 26 35 46 L5 56 R5 26 PB0 I/O FT_ah - USART11_CK, UART4_CTS,
ADC12_INN5
ETH_MII_RXD2, LPTIM3_CH1,
EVENTOUT
TIM8_CH3N, OCTOSPI1_IO0,
DS14258 Rev 1
P6 33 44 H6 54 N6 27 36 47 K6 57 R4 27 PB1 I/O FT_ah - ADC12_INP5

ETH_MII_RXD3, LPTIM3_CH2,
EVENTOUT
RTC_OUT2, SAI1_D1,
TIM8_CH4N, SPI1_RDY,
LPTIM1_CH1, SAI1_SD_A,
SPI3_MOSI/I2S3_SDO,
L5 34 45 N6 55 P6 28 37 48 L6 58 M6 28 PB2 I/O FT_ah - LSCO
OCTOSPI1_CLK,
OCTOSPI1_DQS,
SDMMC1_CMD, LPTIM5_ETR,
EVENTOUT

SPI5_MOSI, OCTOSPI1_NCLK,
SAI2_SD_B, FMC_NRAS,
- - 46 J6 56 R6 - - 49 J6 59 R6 - PF11 I/O FT_ah - ADC1_INP2
DCMI_D12/PSSI_D12,
FMC_A6, LPTIM6_CH2,
- - 47 K6 57 N7 - - 50 N6 60 P6 - PF12 I/O FT_ah - ADC1_INP6, ADC1_INN2
EVENTOUT
- - 48 M7 58 - - - 51 M7 61 - - VSS S - - - -
- - 49 N7 59 - - - 52 N7 62 N9 - VDD S - - - -
I2C4_SMBA, FMC_A7,
- - 50 H7 60 P7 - - 53 H7 63 N6 - PF13 I/O FT_ah - ADC2_INP2

Pin number(1)(2)
Alternate functions
UFBGA176+25 SMPS
I/O structure
UFBGA169 SMPS
WLCSP80 SMPS
LQFP100 SMPS
LQFP144 SMPS
LQFP176 SMPS
reset)(3)(4)
UFBGA176+25
Pin type
Notes
UFBGA169
VFQFPN68
LQFP100
LQFP144
LQFP176
LQFP64
FMC_A8, LPTIM6_IN2,
- - 51 L6 61 R7 - - 54 M6 64 R7 - PF14 I/O FT_fah - ADC2_INP6, ADC2_INN2
EVENTOUT
I2C4_SDA, I3C1_SDA, FMC_A9,

- - 52 J7 62 N8 - - 55 J7 65 P7 - PF15 I/O FT_fh - -
EVENTOUT
UART9_RX, FMC_A10,
- - 53 M6 63 R8 - - 56 L7 66 N7 - PG0 I/O FT_h - -
DS14258 Rev 1
SPI2_MOSI/I2S2_SDO,
- - 54 K7 64 P8 - - 57 K7 67 M7 - PG1 I/O FT_h - UART9_TX, FMC_A11, -
EVENTOUT
TIM1_ETR, UART12_RTS,
UART7_RX, OCTOSPI1_IO4,
T6 35 55 L7 65 R9 - 38 58 N8 68 R8 - PE7 I/O FT_ah - -
FMC_D4/FMC_AD4,
EVENTOUT
TIM1_CH1N,
UART12_CTS/UART12_NSS,
N5 36 56 J8 66 P9 - 39 59 G7 69 P8 - PE8 I/O FT_ah - UART7_TX, OCTOSPI1_IO5, -
FMC_D5/FMC_AD5,
EVENTOUT
TIM1_CH1, UART12_RX,
UART7_RTS, OCTOSPI1_IO6,
R5 37 57 N8 67 N9 - 40 60 L8 70 P9 - PE9 I/O FT_ah - -
FMC_D6/FMC_AD6,
EVENTOUT
- - 58 - 68 - - - 61 - 71 - - VSS S - - - -
- - 59 - 69 - - - 62 - 72 - - VDD S - - - -
87/275
88/275 Pin number(1)(2)
Alternate functions
UFBGA176+25 SMPS
I/O structure
UFBGA169 SMPS
WLCSP80 SMPS
LQFP100 SMPS
LQFP144 SMPS
LQFP176 SMPS
reset)(3)(4)
UFBGA176+25
Pin type
Notes
UFBGA169
VFQFPN68
LQFP100
LQFP144
LQFP176
LQFP64
TIM1_CH2N, UART12_TX,
UART7_CTS, OCTOSPI1_IO7,
M4 38 60 L8 70 R10 - 41 63 H8 73 R9 - PE10 I/O FT_ah - -
FMC_D7/FMC_AD7,
EVENTOUT
TIM1_CH2, SPI1_RDY,
SPI4_NSS, OCTOSPI1_NCS,
- 39 61 M8 71 P10 - 42 64 M8 74 P10 - PE11 I/O FT_ah - SAI2_SD_B, -
DS14258 Rev 1
FMC_D8/FMC_AD8,
EVENTOUT
TIM1_CH3N, SPI4_SCK,
SAI2_SCK_B,
- 40 62 M9 72 R11 - 43 65 K8 75 R10 - PE12 I/O FT_h - -
FMC_D9/FMC_AD9,
EVENTOUT
TIM1_CH3, SPI4_MISO,
SAI2_FS_B,
- 41 63 K8 73 P11 - 44 66 L9 76 N11 - PE13 I/O FT_h - -
FMC_D10/FMC_AD10,

EVENTOUT
TIM1_CH4, SPI4_MOSI,
SAI2_MCLK_B,
- 42 64 J9 74 N10 - 45 67 J8 77 P11 - PE14 I/O FT_h - -
FMC_D11/FMC_AD11,
EVENTOUT
TIM1_BKIN, TIM1_CH4N,
USART10_CK,
- 43 65 L9 75 N11 - 46 68 N9 78 R11 - PE15 I/O FT_h - -
FMC_D12/FMC_AD12,
EVENTOUT

Pin number(1)(2)
Alternate functions
UFBGA176+25 SMPS
I/O structure
UFBGA169 SMPS
WLCSP80 SMPS
LQFP100 SMPS
LQFP144 SMPS
LQFP176 SMPS
reset)(3)(4)
UFBGA176+25
Pin type
Notes
UFBGA169
VFQFPN68
LQFP100
LQFP144
LQFP176
LQFP64
TIM2_CH3, LPTIM3_CH1,
LPTIM2_IN1, I2C2_SCL,
P4 44 66 K9 76 M10 29 47 69 K9 79 R12 29 PB10 I/O FT_f - SPI2_SCK/I2S2_CK, -
USART3_TX, OCTOSPI1_NCS,
ETH_MII_RX_ER, EVENTOUT
TIM2_CH4, LPTIM2_ETR,
I2C2_SDA, SPI2_RDY,
DS14258 Rev 1
- 45 67 L10 77 N12 - - - M9 80 R13 30 PB11 I/O FT_f - SPI4_RDY, USART3_RX, -

ETH_MII_TX_EN/ETH_RMII_TX
_EN, FMC_NBL1, EVENTOUT
T4 46 68 N9 78 R12 - - - - - - - VLXSMPS S - - - -
R3 47 69 N10 79 R13 - - - - - - - VDDSMPS S - - - -
N3 48 70 M10 80 P12 - - - - - - - VSSSMPS S - - - -

T2 49 71 N11 81 R14 30 48 70 N10 81 M10 31 VCAP S - - - -
- 50 72 M11 82 M9 31 49 71 M12 82 M9 32 VSS S - - - -
- 51 73 N12 83 M11 32 50 72 N11 83 N10 33 VDD S - - - -
TIM8_CH1, I2C2_SMBA,
- - - N13 84 P13 - - - K10 84 M11 - PH6 I/O FT - SPI5_SCK, ETH_MII_RXD2, -
FMC_SDNE1,
I2C3_SCL, SPI5_MISO,
- - - L11 85 P14 - - - L10 85 N12 - PH7 I/O FT_f - -
ETH_MII_RXD3, FMC_SDCKE1,
89/275
90/275 Pin number(1)(2)
Alternate functions
UFBGA176+25 SMPS
I/O structure
UFBGA169 SMPS
WLCSP80 SMPS
LQFP100 SMPS
LQFP144 SMPS
LQFP176 SMPS
reset)(3)(4)
UFBGA176+25
Pin type
Notes
UFBGA169
VFQFPN68
LQFP100
LQFP144
LQFP176
LQFP64
TIM1_CH2N, TIM5_ETR,
TIM8_CH2, I2C3_SDA,
- - - M12 - N13 - - - M10 86 M12 - PH8 I/O FT_fh - SPI5_MOSI, -
DCMI_HSYNC/PSSI_DE,
EVENTOUT
TIM1_CH2, TIM12_CH2,
TIM8_CH2N, I2C3_SMBA,
DS14258 Rev 1
- - - M13 86 M12 - - - - 87 M13 - PH9 I/O FT_h - -

SPI5_NSS, DCMI_D0/PSSI_D0,
EVENTOUT
TIM8_CH3, I2C4_SMBA,
- - - K10 87 N14 - - - M11 88 L13 - PH10 I/O FT_h - -
SPI5_RDY, DCMI_D1/PSSI_D1,
EVENTOUT
TIM1_CH1, TIM5_CH2,
TIM8_CH3N, I2C4_SCL,
- - - L13 88 P15 - - - N12 89 L12 - PH11 I/O FT_fh - -
I3C1_SCL, DCMI_D2/PSSI_D2,

EVENTOUT
TIM8_BKIN, I2C4_SDA,
- - - L12 89 M13 - - - N13 90 K12 - PH12 I/O FT_fh - -
I3C1_SDA, TIM8_CH4N,
- - - - 90 H12 - - - - - - - VSS S - - - -
- - - - 91 J12 - - - L13 91 J12 - VDD S - - - -


Pin number(1)(2)
Alternate functions
UFBGA176+25 SMPS
I/O structure
UFBGA169 SMPS
WLCSP80 SMPS
LQFP100 SMPS
LQFP144 SMPS
LQFP176 SMPS
reset)(3)(4)
UFBGA176+25
Pin type
Notes
UFBGA169
VFQFPN68
LQFP100
LQFP144
LQFP176
LQFP64
TIM1_BKIN, OCTOSPI1_NCLK,
I2C2_SDA, SPI2_NSS/I2S2_WS,
UCPD1_FRSTX, USART3_CK,
L3 - - K11 92 L12 33 51 73 K11 92 P12 34 PB12 I/O FT_fh - -
FDCAN2_RX,
ETH_MII_TXD0/ETH_RMII_TXD
0, UART5_RX, EVENTOUT
TIM1_CH1N, LPTIM3_IN1,
DS14258 Rev 1
LPTIM2_CH1, I2C2_SMBA,
SPI2_SCK/I2S2_CK,
M2 52 74 K12 93 R15 34 52 74 L11 93 P13 35 PB13 I/O FT_c - UCPD1_CC1
USART3_CTS/USART3_NSS,
FDCAN2_TX, SDMMC1_D0,
UART5_TX, EVENTOUT
TIM8_CH2N, USART1_TX,
SPI2_MISO/I2S2_SDI,
N1 53 75 J10 94 N15 35 53 75 M13 94 R14 36 PB14 I/O FT_c - UCPD1_CC2
USART3_RTS, UART4_RTS,
SDMMC2_D0, LPTIM3_ETR,
EVENTOUT
RTC_REFIN, TIM1_CH3N,
USART1_RX,
SPI2_MOSI/I2S2_SDO,
L1 54 76 H10 95 M14 36 54 76 J10 95 R15 37 PB15 I/O FT_h - PVD_IN
UART4_CTS, SDMMC2_D1,
OCTOSPI1_CLK,
1, DCMI_D2/PSSI_D2,
UART5_RX, EVENTOUT
91/275
92/275 Pin number(1)(2)
Alternate functions
UFBGA176+25 SMPS
I/O structure
UFBGA169 SMPS
WLCSP80 SMPS
LQFP100 SMPS
LQFP144 SMPS
LQFP176 SMPS
reset)(3)(4)
UFBGA176+25
Pin type
Notes
UFBGA169
VFQFPN68
LQFP100
LQFP144
LQFP176
LQFP64
USART3_TX,
- 55 77 J11 96 M15 - 55 77 L12 96 P15 - PD8 I/O FT_h - FMC_D13/FMC_AD13, -
EVENTOUT
- - - - - G12 - - - - - - - VSS S - - - -
USART3_RX, FDCAN2_RX,
- 56 78 H9 97 L13 - 56 78 J9 97 P14 - PD9 I/O FT_h - FMC_D14/FMC_AD14, -
DS14258 Rev 1
EVENTOUT
LPTIM2_CH2, USART3_CK,
- 57 79 K13 98 K12 - 57 79 J11 98 N15 - PD10 I/O FT_h - FMC_D15/FMC_AD15, -
EVENTOUT
SAI1_CK1, LPTIM2_IN2,
I2C4_SMBA,
- 58 80 H8 99 L14 - 58 80 H10 99 N14 38 PD11 I/O FT_h - UART4_RX, OCTOSPI1_IO0, -
SAI2_SD_A,

FMC_A16/FMC_CLE,
EVENTOUT
LPTIM1_IN1, TIM4_CH1,
LPTIM2_IN1, I2C4_SCL,
I3C1_SCL, SAI1_D1,
USART3_RTS, UART4_TX,
- 59 81 H11 100 K14 - 59 81 K12 100 N13 39 PD12 I/O FT_fh - -
OCTOSPI1_IO1, SAI2_FS_A,
FMC_A17/FMC_ALE,
DCMI_D12/PSSI_D12,
EVENTOUT

Pin number(1)(2)
Alternate functions
UFBGA176+25 SMPS
I/O structure
UFBGA169 SMPS
WLCSP80 SMPS
LQFP100 SMPS
LQFP144 SMPS
LQFP176 SMPS
reset)(3)(4)
UFBGA176+25
Pin type
Notes
UFBGA169
VFQFPN68
LQFP100
LQFP144
LQFP176
LQFP64
LPTIM1_CH1, TIM4_CH2,
LPTIM2_CH1, I2C4_SDA,
I3C1_SDA, OCTOSPI1_IO3,
- 60 82 G8 101 L15 - 60 82 K13 101 M15 - PD13 I/O FT_fh - SAI2_SCK_A, UART9_RTS, -
FMC_A18,
DCMI_D13/PSSI_D13,
DS14258 Rev 1
- - 83 J12 102 - - - 83 H12 102 H12 - VSS S - - - -
- - 84 J13 103 - - - 84 H13 103 J13 - VDD S - - - -
TIM4_CH3, UART8_CTS,
UART9_RX,
K2 61 85 H12 104 K13 - 61 85 H11 104 M14 - PD14 I/O FT_h - -
FMC_D0/FMC_AD0,
EVENTOUT
TIM4_CH4, UART8_RTS,
J1 62 86 G10 105 J13 - 62 86 H9 105 L14 - PD15 I/O FT_h - UART9_TX, FMC_D1/FMC_AD1, -
EVENTOUT
- - - - - - - - - - - - - VDD S - - - -
- - - - - - - - - - - - - VSS S - - - -
TIM8_BKIN, UART12_RX,
- - 87 H13 106 K15 - - 87 J12 106 L15 - PG2 I/O FT_h - FMC_A12, LPTIM6_ETR, -
EVENTOUT
TIM8_BKIN2, UART12_TX,
- - 88 G9 107 H14 - - 88 G9 107 K15 - PG3 I/O FT_h - FMC_A13, LPTIM5_ETR, -
EVENTOUT
TIM1_BKIN2,
93/275
- - 89 G11 108 J15 - - 89 J13 108 K14 - PG4 I/O FT_h - FMC_A14/FMC_BA0, -
LPTIM4_ETR, EVENTOUT
94/275 Pin number(1)(2)
Alternate functions
UFBGA176+25 SMPS
I/O structure
UFBGA169 SMPS
WLCSP80 SMPS
LQFP100 SMPS
LQFP144 SMPS
LQFP176 SMPS
reset)(3)(4)
UFBGA176+25
Pin type
Notes
UFBGA169
VFQFPN68
LQFP100
LQFP144
LQFP176
LQFP64
TIM1_ETR,
- - 90 F8 109 H15 - - 90 G10 109 K13 - PG5 I/O FT_h - FMC_A15/FMC_BA1, -
EVENTOUT
TIM17_BKIN, I3C1_SDA,
I2C4_SDA, SPI1_RDY,
OCTOSPI1_NCS,
- - 91 G12 110 J14 - - 91 G11 110 J15 - PG6 I/O FT_fh - -
UCPD1_FRSTX, FMC_NE3,
DS14258 Rev 1
DCMI_D12/PSSI_D12,
EVENTOUT
SAI1_CK2, I3C1_SCL,
I2C4_SCL, SAI1_MCLK_A,
USART6_CK, UCPD1_FRSTX,
- - 92 F9 111 H13 - - 92 G8 111 J14 - PG7 I/O FT_fh - -
FMC_INT,
DCMI_D13/PSSI_D13,
EVENTOUT
TIM8_ETR, SPI6_NSS,

- - 93 G13 112 G15 - - 93 F11 112 H14 - PG8 I/O FT_h - USART6_RTS, ETH_PPS_OUT, -
FMC_SDCLK, EVENTOUT
- - 94 - 113 - - - 94 - 113 - - VSS S - - - -
- - 95 - 114 - - - 95 - 114 - - VDD S - - - -
TIM3_CH1, TIM8_CH1,
I2S2_MCK, SAI1_SCK_A,
USART6_TX, SDMMC1_D0DIR,
J3 63 96 F10 115 G14 37 63 96 F9 115 H15 40 PC6 I/O FT_h - -
FMC_NWAIT, SDMMC2_D6,
OCTOSPI1_IO5, SDMMC1_D6,

Pin number(1)(2)
Alternate functions
UFBGA176+25 SMPS
I/O structure
UFBGA169 SMPS
WLCSP80 SMPS
LQFP100 SMPS
LQFP144 SMPS
LQFP176 SMPS
reset)(3)(4)
UFBGA176+25
Pin type
Notes
UFBGA169
VFQFPN68
LQFP100
LQFP144
LQFP176
LQFP64
TRGIO, TIM3_CH2, TIM8_CH2,
I2S3_MCK, USART6_RX,
SDMMC1_D123DIR, FMC_NE1,
K4 64 97 F11 116 G13 38 64 97 F10 116 G15 41 PC7 I/O FT_h - -
SDMMC2_D7, OCTOSPI1_IO6,
SDMMC1_D7,
TRACED1, TIM3_CH3,
DS14258 Rev 1
TIM8_CH3, USART6_CK,
UART5_RTS,
J5 65 98 E9 117 F14 39 65 98 G12 117 G14 42 PC8 I/O FT_h - -
FMC_NE2/FMC_NCE, FMC_INT,
FMC_ALE, SDMMC1_D0,
MCO2, TIM3_CH4, TIM8_CH4,

I2C3_SDA, AUDIOCLK,
F2 66 99 F12 118 F13 40 66 99 G13 118 F14 43 PC9 I/O FT_fh - UART5_CTS, OCTOSPI1_IO0, UCPD1_DB2
FMC_CLE, SDMMC1_D1,
- - - - - - - - - - - G12 - VSS S - - - -
- - - - - - - - - - - G13 - VDD S - - - -
MCO1, TIM1_CH1, TIM8_BKIN2,

I2C3_SCL, SPI1_RDY,
G3 67 100 E10 119 F15 41 67 100 F12 119 F15 44 PA8 I/O FT_fh - USART1_CK, USB_SOF, -
UART7_RX, FMC_NOE,
95/275
96/275 Pin number(1)(2)
Alternate functions
UFBGA176+25 SMPS
I/O structure
UFBGA169 SMPS
WLCSP80 SMPS
LQFP100 SMPS
LQFP144 SMPS
LQFP176 SMPS
reset)(3)(4)
UFBGA176+25
Pin type
Notes
UFBGA169
VFQFPN68
LQFP100
LQFP144
LQFP176
LQFP64
TIM1_CH2, LPUART1_TX,
I2C3_SMBA,
SPI2_SCK/I2S2_CK,
H4 68 101 F13 120 E15 42 68 101 E11 120 E15 45 PA9 I/O FT_d - UCPD1_DB1
USART1_TX, ETH_MII_TX_ER,
FMC_NWE, DCMI_D0/PSSI_D0,
EVENTOUT
TIM1_CH3, LPUART1_RX,
DS14258 Rev 1
LPTIM2_IN2, UCPD1_FRSTX,
G5 69 102 E11 121 E14 43 69 102 E10 121 D15 46 PA10 I/O FT_h - USART1_RX, FDCAN2_TX, -
SDMMC1_D0,
TIM1_CH4, LPUART1_CTS,
SPI2_NSS/I2S2_WS,
UART4_RX,
E1 70 103 C13 122 D15 44 70 103 F13 122 C15 47 PA11 I/O FT_u - -
FDCAN1_RX, USB_DM,
EVENTOUT

TIM1_ETR, LPUART1_RTS,
SPI2_SCK/I2S2_CK,
C1 71 104 B13 123 C15 45 71 104 E13 123 B15 48 PA12 I/O FT_u - UART4_TX, USART1_RTS, -
SAI2_FS_B, FDCAN1_TX,
USB_DP, EVENTOUT
PA13(JTMS (6)
F4 72 105 D12 124 E13 46 72 105 E12 124 A15 49 I/O FT JTMS/SWDIO, EVENTOUT -
/SWDIO)
- 74 107 E12 126 D14 47 74 107 C12 126 F12 50 VSS S - - - -
- 75 108 D13 127 E12 48 75 108 C13 127 F13 51 VDD S - - - -
B2 73 106 E13 125 F12 - 73 106 D13 125 H13 - VDDUSB S - - - -


Pin number(1)(2)
Alternate functions
UFBGA176+25 SMPS
I/O structure
UFBGA169 SMPS
WLCSP80 SMPS
LQFP100 SMPS
LQFP144 SMPS
LQFP176 SMPS
reset)(3)(4)
UFBGA176+25
Pin type
Notes
UFBGA169
VFQFPN68
LQFP100
LQFP144
LQFP176
LQFP64
LPTIM1_IN2, TIM8_CH1N,
UART8_TX, UART4_TX,
- - - C12 128 B15 - - - D12 128 E12 - PH13 I/O FT_h - -
FDCAN1_TX,
TIM8_CH2N, UART4_RX,
- - - D11 129 D13 - - - D10 129 E13 - PH14 I/O FT_h - FDCAN1_RX, -
DS14258 Rev 1
TIM8_CH3N,
- - - A13 130 C14 - - - D11 130 D13 - PH15 I/O FT_h - DCMI_D11/PSSI_D11, -
EVENTOUT
TIM5_CH4,
SPI2_NSS/I2S2_WS,
- - - B12 131 - - - - B13 131 E14 - PI0 I/O FT_h - -
DCMI_D13/PSSI_D13,
EVENTOUT
TIM8_BKIN2,
- - - C11 132 A15 - - - B12 132 D14 - PI1 I/O FT_h - SPI2_SCK/I2S2_CK, -
TIM8_CH4,
- - - D10 133 B14 - - - A13 133 C14 - PI2 I/O FT_h - SPI2_MISO/I2S2_SDI, -
TIM8_ETR,
SPI2_MOSI/I2S2_SDO,
- - - A12 134 A14 - - - C11 134 C13 - PI3 I/O FT_h - -
DCMI_D10/PSSI_D10,
EVENTOUT
- - - B8 135 D9 - - - B10 135 D9 - VSS S - - - -
- - - A8 136 D8 - - - A10 136 C9 - VDD S - - - -

97/275
98/275 Pin number(1)(2)
Alternate functions
UFBGA176+25 SMPS
I/O structure
UFBGA169 SMPS
WLCSP80 SMPS
LQFP100 SMPS
LQFP144 SMPS
LQFP176 SMPS
reset)(3)(4)
UFBGA176+25
Pin type
Notes
UFBGA169
VFQFPN68
LQFP100
LQFP144
LQFP176
LQFP64
PA14(JTCK/ (6)
E3 76 109 C10 137 B13 49 76 109 A12 137 A14 52 I/O FT JTCK/SWCLK, EVENTOUT -
SWCLK)
JTDI, TIM2_CH1, LPTIM3_IN2,

HDMI_CEC,
SPI1_NSS/I2S1_WS,
(6) SPI3_NSS/I2S3_WS,
D4 77 110 B10 138 C13 50 77 110 B11 138 A13 53 PA15(JTDI) I/O FT -
SPI6_NSS, UART4_RTS,
DS14258 Rev 1
UART7_TX, FMC_NBL1,
DCMI_D11/PSSI_D11,
TIM2_ETR, EVENTOUT
LPTIM3_ETR,
SPI3_SCK/I2S3_CK,
USART3_TX, UART4_TX,
C3 78 111 A10 139 D12 51 78 111 C10 139 B14 54 PC10 I/O FT_h - OCTOSPI1_IO1, -
0, SDMMC1_D2,

LPTIM3_IN1,
SPI3_MISO/I2S3_SDI,
E5 79 112 A9 140 C12 52 79 112 A11 140 B13 55 PC11 I/O FT_h - USART3_RX, UART4_RX, -
OCTOSPI1_NCS, SDMMC1_D3,
TRACED3, TIM15_CH1,
SPI6_SCK,
SPI3_MOSI/I2S3_SDO,
F6 80 113 D9 141 C11 53 80 113 B9 141 A12 56 PC12 I/O FT_h - -
USART3_CK, UART5_TX,
SDMMC1_CK,
- - - B11 - D11 - - - - - - - VSS S - - - -


Pin number(1)(2)
Alternate functions
UFBGA176+25 SMPS
I/O structure
UFBGA169 SMPS
WLCSP80 SMPS
LQFP100 SMPS
LQFP144 SMPS
LQFP176 SMPS
reset)(3)(4)
UFBGA176+25
Pin type
Notes
UFBGA169
VFQFPN68
LQFP100
LQFP144
LQFP176
LQFP64
- - - A11 - D10 - - - - - - - VDD S - - - -
TIM8_CH4N, UART4_RX,
FDCAN1_RX, UART9_CTS,
A3 81 114 C9 142 B12 - 81 114 D9 142 B12 - PD0 I/O FT_h - -
FMC_D2/FMC_AD2,
EVENTOUT
UART4_TX, FDCAN1_TX,
DS14258 Rev 1
B4 82 115 B9 143 A13 - 82 115 E9 143 C12 - PD1 I/O FT_h - FMC_D3/FMC_AD3, -
EVENTOUT
TRACED2, TIM3_ETR,
TIM15_BKIN, UART5_RX,
A5 83 116 E8 144 C10 54 83 116 C9 144 D12 - PD2 I/O FT_h - SDMMC1_CMD, WKUP7
DCMI_D11/PSSI_D11,
SPI2_SCK/I2S2_CK,
- 84 117 C8 145 A12 - 84 117 A9 145 D11 - PD3 I/O FT_h - WKUP8
FMC_CLK, DCMI_D5/PSSI_D5,
EVENTOUT
USART2_RTS, OCTOSPI1_IO4,
- 85 118 D8 146 B11 - 85 118 F8 146 D10 - PD4 I/O FT_h - -
FMC_NOE, EVENTOUT
TIM1_CH4N, SPI2_RDY,
USART2_TX, FDCAN1_TX,
- 86 119 A7 147 A11 - 86 119 D8 147 C11 - PD5 I/O FT_h - -
OCTOSPI1_IO5, FMC_NWE,
EVENTOUT
- - 120 - 148 - - - 120 B7 148 D8 - VSS S - - - -
- - 121 A6 149 D7 - - 121 A7 149 C8 - VDDIO2 S - - - -

99/275
100/275 Pin number(1)(2)
Alternate functions
UFBGA176+25 SMPS
I/O structure
UFBGA169 SMPS
WLCSP80 SMPS
LQFP100 SMPS
LQFP144 SMPS
LQFP176 SMPS
reset)(3)(4)
UFBGA176+25
Pin type
Notes
UFBGA169
VFQFPN68
LQFP100
LQFP144
LQFP176
LQFP64
SAI1_D1,
SPI3_MOSI/I2S3_SDO,
SAI1_SD_A, USART2_RX,
- 87 122 F7 150 B10 - 87 122 E8 150 B11 - PD6 I/O FT_sh - OCTOSPI1_IO6, SDMMC2_CK, -
FMC_NWAIT,
DCMI_D10/PSSI_D10,
EVENTOUT
DS14258 Rev 1
SPI1_MOSI/I2S1_SDO,
USART2_CK, OCTOSPI1_IO7,
- 88 123 B7 151 A10 - 88 123 B8 151 A11 - PD7 I/O FT_sh - SDMMC2_CMD, -
FMC_NE1/FMC_NCE,
LPTIM4_OUT, EVENTOUT
- - - - - D6 - - - - - - - VSS S - - - -
SPI1_MISO/I2S1_SDI,
USART6_RX, OCTOSPI1_IO6,
SAI2_FS_B, SDMMC2_D0,

- - 124 E7 152 B9 - - 124 F7 152 C10 - PG9 I/O FT_sh - -
FMC_NE2/FMC_NCE,
DCMI_VSYNC/PSSI_RDY,
EVENTOUT
SPI1_NSS/I2S1_WS,
SAI2_SD_B, SDMMC2_D1,
- - 125 C7 153 A9 - - 125 A8 153 B10 - PG10 I/O FT_sh - -
FMC_NE3, DCMI_D2/PSSI_D2,
EVENTOUT

Pin number(1)(2)
Alternate functions
UFBGA176+25 SMPS
I/O structure
UFBGA169 SMPS
WLCSP80 SMPS
LQFP100 SMPS
LQFP144 SMPS
LQFP176 SMPS
reset)(3)(4)
UFBGA176+25
Pin type
Notes
UFBGA169
VFQFPN68
LQFP100
LQFP144
LQFP176
LQFP64
LPTIM1_IN2,
SPI1_SCK/I2S1_CK,
USART10_RX, USART11_RTS,
- - - - 154 C9 - - 126 E7 154 B9 - PG11 I/O FT_sh - SDMMC2_D2, -
ETH_MII_TX_EN/ETH_RMII_TX
_EN, DCMI_D3/PSSI_D3,
EVENTOUT
DS14258 Rev 1
LPTIM1_IN1, PSSI_D15,
SPI6_MISO, USART10_TX,
USART6_RTS, SDMMC2_D3,
- - 126 D7 155 B8 - - 127 C8 155 B8 - PG12 I/O FT_sh - ETH_MII_TXD1/ETH_RMII_TXD -
1, FMC_NE4,
DCMI_D11/PSSI_D11,
TRACED0, LPTIM1_CH1,
SPI6_SCK,
- - 127 - 156 C8 - - 128 D7 156 A8 - PG13 I/O FT_sh - -
SDMMC2_D6,
0, FMC_A24, LPTIM5_CH2,
EVENTOUT
TRACED1, LPTIM1_ETR,
LPTIM1_CH2, SPI6_MOSI,
USART10_RTS, USART6_TX,
- - 128 - 157 A8 - - 129 C7 157 A7 - PG14 I/O FT_sh - OCTOSPI1_IO7, SDMMC2_D7, -
1, FMC_A25, LPTIM5_IN1,
101/275
EVENTOUT
- - 129 B4 158 - - - 130 - 158 D7 - VSS S - - - -

102/275 Pin number(1)(2)
Alternate functions
UFBGA176+25 SMPS
I/O structure
UFBGA169 SMPS
WLCSP80 SMPS
LQFP100 SMPS
LQFP144 SMPS
LQFP176 SMPS
reset)(3)(4)
UFBGA176+25
Pin type
Notes
UFBGA169
VFQFPN68
LQFP100
LQFP144
LQFP176
LQFP64
- - 130 A3 159 - - - 131 - 159 C7 - VDD S - - - -
SPI4_RDY, USART10_CK,
- - 131 B6 160 A7 - - 132 B6 160 B7 - PG15 I/O FT_h - FMC_NCAS, -
DCMI_D13/PSSI_D13,
EVENTOUT
DS14258 Rev 1
JTDO/TRACESWO, TIM2_CH2,
I2C2_SDA, SPI1_SCK/I2S1_CK,
PB3(JTDO/ SPI3_SCK/I2S3_CK,
C5 89 132 F6 161 B7 55 89 133 E6 161 A10 57 TRACESW I/O FT_fh - UART12_CTS/UART12_NSS, -
O) SPI6_SCK, SDMMC2_D2,
CRS_SYNC, UART7_RX,
NJTRST, TIM16_BKIN,
TIM3_CH1, OCTOSPI1_CLK,
LPTIM1_CH2,

SPI1_MISO/I2S1_SDI,
PB4(NJTRS
B6 90 133 A5 162 C7 56 90 134 A6 162 A9 58 I/O FT_h - SPI3_MISO/I2S3_SDI, -
T)
SPI2_NSS/I2S2_WS,
SPI6_MISO, SDMMC2_D3,
UART7_TX, DCMI_D7/PSSI_D7,
EVENTOUT

Pin number(1)(2)
Alternate functions
UFBGA176+25 SMPS
I/O structure
UFBGA169 SMPS
WLCSP80 SMPS
LQFP100 SMPS
LQFP144 SMPS
LQFP176 SMPS
reset)(3)(4)
UFBGA176+25
Pin type
Notes
UFBGA169
VFQFPN68
LQFP100
LQFP144
LQFP176
LQFP64
OCTOSPI1_NCLK, I2C1_SMBA,
SPI1_MOSI/I2S1_SDO,
I2C4_SMBA,
D6 91 134 E6 163 A6 57 91 135 C6 163 A6 59 PB5 I/O FT_h - SPI3_MOSI/I2S3_SDO, -
SPI6_MOSI, FDCAN2_RX,
ETH_PPS_OUT, FMC_SDCKE1,
DS14258 Rev 1
DCMI_D10/PSSI_D10,
UART5_RX, EVENTOUT
I3C1_SCL, I2C1_SCL,
HDMI_CEC, I2C4_SCL,
USART1_TX, LPUART1_TX,
E7 92 135 C6 164 B6 58 92 136 A5 164 B6 60 PB6 I/O FT_f - -
FDCAN2_TX, OCTOSPI1_NCS,
FMC_SDNE1,
DCMI_D5/PSSI_D5, UART5_TX,
EVENTOUT
I3C1_SDA, I2C1_SDA,
I2C4_SDA, USART1_RX,
LPUART1_RX, FDCAN1_TX,
C7 93 136 D6 165 C6 59 93 137 D6 165 B5 61 PB7 I/O FT_fa - WKUP5
SDMMC2_D5, SDMMC2_CKIN,
FMC_NL,
DCMI_VSYNC/PSSI_RDY,
EVENTOUT
D8 94 137 B5 166 A5 60 94 138 B5 166 D6 62 BOOT0 I B - - -

103/275
104/275 Pin number(1)(2)
Alternate functions
UFBGA176+25 SMPS
I/O structure
UFBGA169 SMPS
WLCSP80 SMPS
LQFP100 SMPS
LQFP144 SMPS
LQFP176 SMPS
reset)(3)(4)
UFBGA176+25
Pin type
Notes
UFBGA169
VFQFPN68
LQFP100
LQFP144
LQFP176
LQFP64
I3C1_SCL, I2C1_SCL,
SPI4_RDY, I2C4_SCL,
E9 95 138 F5 167 B5 61 95 139 E5 167 A5 63 PB8 I/O FT_fh - SDMMC1_CKIN, UART4_RX, -
FDCAN1_RX, SDMMC2_D4,
ETH_MII_TXD3, SDMMC1_D4,
DS14258 Rev 1
I3C1_SDA, I2C1_SDA,
SPI2_NSS/I2S2_WS, I2C4_SDA,
- 96 139 E5 168 A4 - 96 140 A4 168 B4 64 PB9 I/O FT_fh - SDMMC1_CDIR, UART4_TX, -
FDCAN1_TX, SDMMC2_D5,
SDMMC2_CKIN, SDMMC1_D5,
LPTIM1_ETR, TIM4_ETR,
LPTIM2_CH2, LPTIM2_ETR,
SPI3_RDY, UART8_RX,

- 97 140 D5 169 C5 - 97 141 C5 169 A4 65 PE0 I/O FT_h - -
FDCAN1_RX, SAI2_MCLK_A,
FMC_NBL0, DCMI_D2/PSSI_D2,
EVENTOUT
LPTIM1_IN2, UART8_TX,
- - 141 C5 170 B4 - - - D5 170 A3 - PE1 I/O FT_h - FDCAN1_TX, FMC_NBL1, -
A9 98 142 A4 171 A3 62 98 142 B4 171 C6 66 VCAP S - - - -
- 99 143 - - - 63 99 143 B3 - - 67 VSS S - - - -

- 100 144 - 172 - 64 100 144 A3 172 - 68 VDD S - - - -

Pin number(1)(2)
Alternate functions
UFBGA176+25 SMPS
I/O structure
UFBGA169 SMPS
WLCSP80 SMPS
LQFP100 SMPS
LQFP144 SMPS
LQFP176 SMPS
reset)(3)(4)
UFBGA176+25
Pin type
Notes
UFBGA169
VFQFPN68
LQFP100
LQFP144
LQFP176
LQFP64
TIM8_BKIN, SPI2_RDY,
- - - C4 173 B3 - - - C4 173 D4 - PI4 I/O FT_h - SAI2_MCLK_A, -
TIM8_CH1, SAI2_SCK_A,
- - - B3 174 A2 - - - - 174 C4 - PI5 I/O FT_h - DCMI_VSYNC/PSSI_RDY, -
EVENTOUT
DS14258 Rev 1
TIM8_CH2, SAI2_SD_A,
- - - A2 175 C4 - - - C3 175 C3 - PI6 I/O FT_h - -
TIM8_CH3, SAI2_FS_A,
- - - A1 176 A1 - - - A2 176 C2 - PI7 I/O FT_h - -
- - - - - F6 - - - - - F6 - VSS S - - - -
- - - - - F7 - - - - - F7 - VSS S - - - -
- - - - - F8 - - - - - F8 - VSS S - - - -
- - - - - F9 - - - - - F9 - VSS S - - - -
- - - - - F10 - - - - - F10 - VSS S - - - -
- - - - - G6 - - - - - G6 - VSS S - - - -
- - - - - G7 - - - - - G7 - VSS S - - - -
- - - - - G8 - - - - - G8 - VSS S - - - -
- - - - - G9 - - - - - G9 - VSS S - - - -
- - - - - G10 - - - - - G10 - VSS S - - - -
- - - - - H6 - - - - - H6 - VSS S - - - -
105/275
- - - - - H7 - - - - - H7 - VSS S - - - -
- - - - - H8 - - - - - H8 - VSS S - - - -
106/275 Pin number(1)(2)
Alternate functions
UFBGA176+25 SMPS
I/O structure
UFBGA169 SMPS
WLCSP80 SMPS
LQFP100 SMPS
LQFP144 SMPS
LQFP176 SMPS
reset)(3)(4)
UFBGA176+25
Pin type
Notes
UFBGA169
VFQFPN68
LQFP100
LQFP144
LQFP176
LQFP64
- - - - - H9 - - - - - H9 - VSS S - - - -
- - - - - H10 - - - - - H10 - VSS S - - - -
- - - - - J6 - - - - - J6 - VSS S - - - -
- - - - - J7 - - - - - J7 - VSS S - - - -
- - - - - J8 - - - - - J8 - VSS S - - - -
DS14258 Rev 1
- - - - - J9 - - - - - J9 - VSS S - - - -
- - - - - J10 - - - - - J10 - VSS S - - - -
- - - - - K6 - - - - - K6 - VSS S - - - -
- - - - - K7 - - - - - K7 - VSS S - - - -
- - - - - K8 - - - - - K8 - VSS S - - - -
- - - - - K9 - - - - - K9 - VSS S - - - -

- - - - - K10 - - - - - K10 - VSS S - - - -
1. The devices with SMPS correspond to commercial code STM32H53xIxxQ.

2. A non-connected I/O in a given package is configured as an output tied to VSS. When VREF+ pad is not available on a package, the internal voltage reference buffer
(VREFBUF) is not available and must be kept disabled.
3. PC13, PC14 and PC15 are supplied through the power switch (by VSW). Since the switch only sinks a limited amount of current, the use of PC13 to PC15 GPIOs in output
mode is limited: The speed must not exceed 2 MHz with a maximum load of 30 pF. These GPIOs must not be used as current sources (for example to drive a LED).
4. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function depends then on the content of the RTC registers that are not reset by the system
reset. For details on how to manage these GPIOs, refer to the backup domain and RTC register descriptions in the product reference manual.
5. As a tamper input, only PC13, PI8, PA0, PA1, and PA2 are functional in Standby and VBAT mode. As a tamper output, only PC13, PA1, and PI8 are functional in Standby and
VBAT mode.
6. After reset, these pins are configured as JTAG/SW debug alternate functions. The internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are
activated too.
4.3 Alternate functions

Table 15. Alternate function AF0 to AF7(1)
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
I2C4/OCTOSPI/ SDMMC1/SPI2/I
CEC/DCMI/I2C1/
Port LPTIM3/PDM_ I3C1/LPTIM2/3/LP CEC/I3C1/LPTIM1/SPI SAI1/SPI3/I2S3/ 2S2/SPI3/I2S3/S
LPTIM1/TIM1/2/1 2/3/4/LPTIM1/2/
SYS SAI1/TIM3/4/5/ UART1/OCTOSPI/ 1/I2S1/SPI2/I2S2/SPI3/ SPI4/UART4/12/ PI6/UART7/8/12/
6/17 SPI1/I2S1/TIM15
12/15 TIM1/8 I2S3/SPI4/5/6 USART10/USB_ USART1/2/3/6/1
/USART1
PD 0/11
USART2_CTS/U
PA0 - TIM2_CH1 TIM5_CH1 TIM8_ETR TIM15_BKIN SPI6_NSS SPI3_RDY
SART2_NSS
PA1 - TIM2_CH2 TIM5_CH2 - TIM15_CH1N LPTIM1_IN1 OCTOSPI1_DQS USART2_RTS
PA2 - TIM2_CH3 TIM5_CH3 - TIM15_CH1 LPTIM1_IN2 - USART2_TX
PA3 - TIM2_CH4 TIM5_CH4 OCTOSPI1_CLK TIM15_CH2 SPI2_NSS/I2S2_WS SAI1_SD_B USART2_RX
DS14258 Rev 1
SPI3_NSS/I2S3_
PA4 - - TIM5_ETR LPTIM2_CH1 - SPI1_NSS/I2S1_WS USART2_CK
WS
PA5 - TIM2_CH1 - TIM8_CH1N - SPI1_SCK/I2S1_CK - -
PA6 - TIM1_BKIN TIM3_CH1 TIM8_BKIN - SPI1_MISO/I2S1_SDI OCTOSPI1_IO3 USART11_TX
PA7 - TIM1_CH1N TIM3_CH2 TIM8_CH1N - SPI1_MOSI/I2S1_SDO - USART11_RX
Port A
PA8 MCO1 TIM1_CH1 - TIM8_BKIN2 I2C3_SCL SPI1_RDY - USART1_CK

PA9 - TIM1_CH2 - LPUART1_TX I2C3_SMBA SPI2_SCK/I2S2_CK - USART1_TX
PA10 - TIM1_CH3 - LPUART1_RX LPTIM2_IN2 - UCPD1_FRSTX USART1_RX
USART1_CTS/U
PA11 - TIM1_CH4 - LPUART1_CTS - SPI2_NSS/I2S2_WS UART4_RX
SART1_NSS
PA12 - TIM1_ETR - LPUART1_RTS - SPI2_SCK/I2S2_CK UART4_TX USART1_RTS
PA13 JTMS/SWDIO - - - - - - -
PA14 JTCK/SWCLK - - - - - - -
SPI3_NSS/I2S3_
PA15 JTDI TIM2_CH1 LPTIM3_IN2 - HDMI_CEC SPI1_NSS/I2S1_WS SPI6_NSS
WS
107/275
108/275 AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
CEC/DCMI/I2C1/
/USART1
PD 0/11
PB0 - TIM1_CH2N TIM3_CH3 TIM8_CH2N - - OCTOSPI1_IO1 USART11_CK

PB1 - TIM1_CH3N TIM3_CH4 TIM8_CH3N - - OCTOSPI1_IO0 -
SPI3_MOSI/I2S3
PB2 RTC_OUT2 - SAI1_D1 TIM8_CH4N SPI1_RDY LPTIM1_CH1 SAI1_SD_A
_SDO
JTDO/TRACE SPI3_SCK/I2S3_ UART12_CTS/U
PB3 TIM2_CH2 - - I2C2_SDA SPI1_SCK/I2S1_CK
SWO CK ART12_NSS
SPI3_MISO/I2S3 SPI2_NSS/I2S2_
PB4 NJTRST TIM16_BKIN TIM3_CH1 OCTOSPI1_CLK LPTIM1_CH2 SPI1_MISO/I2S1_SDI
_SDI WS
DS14258 Rev 1
SPI3_MOSI/I2S3
PB5 - TIM17_BKIN TIM3_CH2 OCTOSPI1_NCLK I2C1_SMBA SPI1_MOSI/I2S1_SDO I2C4_SMBA
_SDO
PB6 - TIM16_CH1N TIM4_CH1 I3C1_SCL I2C1_SCL HDMI_CEC I2C4_SCL USART1_TX
Port B
PB7 - TIM17_CH1N TIM4_CH2 I3C1_SDA I2C1_SDA - I2C4_SDA USART1_RX

PB8 - TIM16_CH1 TIM4_CH3 I3C1_SCL I2C1_SCL SPI4_RDY I2C4_SCL SDMMC1_CKIN
PB9 - TIM17_CH1 TIM4_CH4 I3C1_SDA I2C1_SDA SPI2_NSS/I2S2_WS I2C4_SDA SDMMC1_CDIR

PB10 - TIM2_CH3 LPTIM3_CH1 LPTIM2_IN1 I2C2_SCL SPI2_SCK/I2S2_CK - USART3_TX
PB11 - TIM2_CH4 - LPTIM2_ETR I2C2_SDA SPI2_RDY SPI4_RDY USART3_RX
PB12 - TIM1_BKIN - OCTOSPI1_NCLK I2C2_SDA SPI2_NSS/I2S2_WS UCPD1_FRSTX USART3_CK
USART3_CTS/U
PB13 - TIM1_CH1N LPTIM3_IN1 LPTIM2_CH1 I2C2_SMBA SPI2_SCK/I2S2_CK -
SART3_NSS
PB14 - TIM1_CH2N TIM12_CH1 TIM8_CH2N USART1_TX SPI2_MISO/I2S2_SDI - USART3_RTS
USART11_CTS/
PB15 RTC_REFIN TIM1_CH3N TIM12_CH2 TIM8_CH3N USART1_RX SPI2_MOSI/I2S2_SDO -
USART11_NSS

CEC/DCMI/I2C1/
/USART1
PD 0/11
PC0 - TIM16_BKIN - - - - SAI1_MCLK_A SPI2_RDY

PC1 TRACED0 - SAI1_D1 - - SPI2_MOSI/I2S2_SDO SAI1_SD_A USART11_RTS
PWR_CSLEE
PC2 TIM17_CH1 TIM4_CH4 - - SPI2_MISO/I2S2_SDI OCTOSPI1_IO5 -
P
PC3 PWR_CSTOP - SAI1_D3 LPTIM3_CH1 - SPI2_MOSI/I2S2_SDO OCTOSPI1_IO6 -
PC4 - TIM2_CH4 SAI1_CK1 LPTIM2_ETR - I2S1_MCK - USART3_RX
PC5 - TIM1_CH4N SAI1_D3 - PSSI_D15 - SAI1_FS_A UART12_RTS
DS14258 Rev 1
PC6 - - TIM3_CH1 TIM8_CH1 - I2S2_MCK SAI1_SCK_A USART6_TX

PC7 TRGIO - TIM3_CH2 TIM8_CH2 - - I2S3_MCK USART6_RX
Port C
PC8 TRACED1 - TIM3_CH3 TIM8_CH3 - - - USART6_CK

PC9 MCO2 - TIM3_CH4 TIM8_CH4 I2C3_SDA AUDIOCLK - -
SPI3_SCK/I2S3_
PC10 - - LPTIM3_ETR - - - USART3_TX
CK
SPI3_MISO/I2S3
PC11 - - LPTIM3_IN1 - - - USART3_RX
_SDI
SPI3_MOSI/I2S3
PC12 TRACED3 - TIM15_CH1 - - SPI6_SCK USART3_CK
_SDO
PC13 - - - - - - - -
PC14 - - - - - - - -
PC15 - - - - - - - -
109/275
CEC/DCMI/I2C1/
/USART1
PD 0/11
PD0 - - - TIM8_CH4N - - - -
PD1 - - - - - - - -
PD2 TRACED2 - TIM3_ETR - TIM15_BKIN - - -
USART2_CTS/U
PD3 - - - - - SPI2_SCK/I2S2_CK -
SART2_NSS
PD4 - - - - - - - USART2_RTS
PD5 - TIM1_CH4N - - - SPI2_RDY - USART2_TX
DS14258 Rev 1
PD6 - - SAI1_D1 - - SPI3_MOSI/I2S3_SDO SAI1_SD_A USART2_RX

PD7 - - - - - SPI1_MOSI/I2S1_SDO - USART2_CK
Port D
PD8 - - - - - - - USART3_TX
PD9 - - - - - - - USART3_RX
PD10 - - - LPTIM2_CH2 - - - USART3_CK
USART3_CTS/U
PD11 - - SAI1_CK1 LPTIM2_IN2 I2C4_SMBA - -
SART3_NSS

PD12 - LPTIM1_IN1 TIM4_CH1 LPTIM2_IN1 I2C4_SCL I3C1_SCL SAI1_D1 USART3_RTS
PD13 - LPTIM1_CH1 TIM4_CH2 LPTIM2_CH1 I2C4_SDA I3C1_SDA - -
PD14 - - TIM4_CH3 - - - - -
PD15 - - TIM4_CH4 - - - - -

CEC/DCMI/I2C1/
/USART1
PD 0/11
PE0 - LPTIM1_ETR TIM4_ETR LPTIM2_CH2 LPTIM2_ETR - SPI3_RDY -

PE1 - LPTIM1_IN2 - - - - - -
PE2 TRACECLK LPTIM1_IN2 SAI1_CK1 - - SPI4_SCK SAI1_MCLK_A USART10_RX
PE3 TRACED0 - - - TIM15_BKIN - SAI1_SD_B USART10_TX
PE4 TRACED1 - SAI1_D2 - TIM15_CH1N SPI4_NSS SAI1_FS_A -
PE5 TRACED2 - SAI1_CK2 - TIM15_CH1 SPI4_MISO SAI1_SCK_A -
PE6 TRACED3 TIM1_BKIN2 SAI1_D1 - TIM15_CH2 SPI4_MOSI SAI1_SD_A -
DS14258 Rev 1
PE7 - TIM1_ETR - - - - UART12_RTS UART7_RX

Port E
UART12_CTS/U
PE8 - TIM1_CH1N - - - - UART7_TX
ART12_NSS
PE9 - TIM1_CH1 - - - - UART12_RX UART7_RTS
PE10 - TIM1_CH2N - - - - UART12_TX UART7_CTS
PE11 - TIM1_CH2 - - SPI1_RDY SPI4_NSS OCTOSPI1_NCS -
PE12 - TIM1_CH3N - - - SPI4_SCK - -
PE13 - TIM1_CH3 - - - SPI4_MISO - -
PE14 - TIM1_CH4 - - - SPI4_MOSI - -
PE15 - TIM1_BKIN - TIM1_CH4N - - - USART10_CK
111/275
CEC/DCMI/I2C1/
/USART1
PD 0/11
PF0 - - - - I2C2_SDA - - -
PF1 - - - - I2C2_SCL - - -
PF2 - - LPTIM3_CH2 LPTIM3_IN2 I2C2_SMBA - UART12_TX USART11_CK
PF3 - - LPTIM3_IN1 - - - - USART11_TX
PF4 - - LPTIM3_ETR - - - - USART11_RX
USART11_CTS/
PF5 - - LPTIM3_CH1 - I2C4_SCL I3C1_SCL UART12_RX
USART11_NSS
DS14258 Rev 1
PF6 - TIM16_CH1 - - - SPI5_NSS SAI1_SD_B UART7_RX

Port F
PF7 - TIM17_CH1 - - - SPI5_SCK SAI1_MCLK_B UART7_TX

PF8 - TIM16_CH1N - - - SPI5_MISO SAI1_SCK_B UART7_RTS
PF9 - TIM17_CH1N - - - SPI5_MOSI SAI1_FS_B UART7_CTS
PF10 - TIM16_BKIN SAI1_D3 - PSSI_D15 - - -
PF11 - - - - - SPI5_MOSI - -

PF12 - - - - - - - -
PF13 - - - - I2C4_SMBA - - -
PF14 - - - - - - - -
PF15 - - - - I2C4_SDA I3C1_SDA - -

CEC/DCMI/I2C1/
/USART1
PD 0/11
PG0 - - - - - - - -
SPI2_MOSI/I2S2
PG1 - - - - - - -
_SDO
PG2 - - - TIM8_BKIN - - - UART12_RX
PG3 - - - TIM8_BKIN2 - - - UART12_TX
PG4 - TIM1_BKIN2 - - - - - -
PG5 - TIM1_ETR - - - - - -
DS14258 Rev 1
PG6 - TIM17_BKIN - I3C1_SDA I2C4_SDA SPI1_RDY - -

PG7 - - SAI1_CK2 I3C1_SCL I2C4_SCL - SAI1_MCLK_A USART6_CK
Port G
PG8 - - - TIM8_ETR - SPI6_NSS - USART6_RTS

PG9 - - - - - SPI1_MISO/I2S1_SDI - USART6_RX
PG10 - - - - - SPI1_NSS/I2S1_WS - -
PG11 - LPTIM1_IN2 - - - SPI1_SCK/I2S1_CK USART10_RX USART11_RTS
PG12 - LPTIM1_IN1 - - PSSI_D15 SPI6_MISO USART10_TX USART6_RTS
USART10_CTS/ USART6_CTS/U
PG13 TRACED0 LPTIM1_CH1 - - - SPI6_SCK
USART10_NSS SART6_NSS
PG14 TRACED1 LPTIM1_ETR - - LPTIM1_CH2 SPI6_MOSI USART10_RTS USART6_TX
USART6_CTS/U
PG15 - - - - - SPI4_RDY USART10_CK
SART6_NSS
113/275
CEC/DCMI/I2C1/
/USART1
PD 0/11
PH0 - - - - - - - -
PH1 - - - - - - - -
PH2 - LPTIM1_IN2 - - - - - -
PH3 - - - - - - - -
PH4 - - - - I2C2_SCL SPI5_RDY - SPI6_RDY
PH5 - - - - I2C2_SDA SPI5_NSS - SPI6_RDY
PH6 - TIM1_CH3N TIM12_CH1 TIM8_CH1 I2C2_SMBA SPI5_SCK - -
DS14258 Rev 1
PH7 - TIM1_CH3 - TIM8_CH1N I2C3_SCL SPI5_MISO - -

Port H
PH8 - TIM1_CH2N TIM5_ETR TIM8_CH2 I2C3_SDA SPI5_MOSI - -

PH9 - TIM1_CH2 TIM12_CH2 TIM8_CH2N I2C3_SMBA SPI5_NSS - -
PH10 - TIM1_CH1N TIM5_CH1 TIM8_CH3 I2C4_SMBA SPI5_RDY - -
PH11 - TIM1_CH1 TIM5_CH2 TIM8_CH3N I2C4_SCL I3C1_SCL - -
PH12 - TIM1_BKIN TIM5_CH3 TIM8_BKIN I2C4_SDA I3C1_SDA - -

PH13 - LPTIM1_IN2 - TIM8_CH1N - - - UART8_TX
PH14 - - - TIM8_CH2N - - - -
PH15 - - - TIM8_CH3N - - - -

CEC/DCMI/I2C1/
/USART1
PD 0/11
PI0 - - TIM5_CH4 - - SPI2_NSS/I2S2_WS - -

PI1 - - - TIM8_BKIN2 - SPI2_SCK/I2S2_CK - -
PI2 - - - TIM8_CH4 - SPI2_MISO/I2S2_SDI - -
PI3 - - - TIM8_ETR - SPI2_MOSI/I2S2_SDO - -
PI4 - - - TIM8_BKIN - - - SPI2_RDY
PI5 - - - TIM8_CH1 - - - -
Port I
PI6 - - - TIM8_CH2 - - - -
DS14258 Rev 1
PI7 - - - TIM8_CH3 - - - -
PI8 - - - - - - - -
PI9 - - - - - - - -
PI10 - - - - - - - -
PI11 - - - - - - - -
1. Refer to the next table for AF8 to AF15.
115/275
FDCAN1/2/FMC[
NAND16)/FMC[ CRS/FMC[NAN ETH[MII/RMII)/FM FMC[NAND16)/FMC
Port LPUART1/SAI2 DCMI/FMC[NAND16)/
NORmux)/FMC[ D16)/OCTOSPI/ C[NAND16)/OCT [NORmux)/FMC[NO LPTIM3/4/5/6/T
/SDMMC1/SPI6 FMC[NORmux)/FMC[ SYS
NOR_RAM)/OC SAI2/SDMMC2/T OSPI/SDMMC2/U R_RAM)/FMC[SDRA IM2/UART5
/UART4/5/8 NOR_RAM)/LPTIM5
TOSPI/SDMMC2 IM8/USB_ ART7/9/USB_PD M_16bit)/SDMMC1
/TIM13/14
PA0 UART4_TX SDMMC2_CMD SAI2_SD_B ETH_MII_CRS - - TIM2_ETR EVENTOUT

ETH_MII_RX_CLK
PA1 UART4_RX OCTOSPI1_IO3 SAI2_MCLK_B /ETH_RMII_REF_ - - - EVENTOUT
CLK
PA2 SAI2_SCK_B - - ETH_MDIO - - - EVENTOUT
PA3 - - - ETH_MII_COL - - - EVENTOUT
DCMI_HSYNC/PSSI_
DS14258 Rev 1
PA4 SPI6_NSS - - - - - EVENTOUT

DE
ETH_MII_TX_EN/
PA5 SPI6_SCK - - - PSSI_D14 TIM2_ETR EVENTOUT
ETH_RMII_TX_EN
DCMI_PIXCLK/PSSI_
PA6 SPI6_MISO TIM13_CH1 - - - - EVENTOUT
PDCK
Port A
ETH_MII_RX_DV/
PA7 SPI6_MOSI TIM14_CH1 OCTOSPI1_IO2 ETH_RMII_CRS_ FMC_SDNWE FMC_NWE - EVENTOUT
DV

PA8 - - USB_SOF UART7_RX FMC_NOE DCMI_D3/PSSI_D3 - EVENTOUT
PA9 - - - ETH_MII_TX_ER FMC_NWE DCMI_D0/PSSI_D0 - EVENTOUT
PA10 - FDCAN2_TX - - SDMMC1_D0 DCMI_D1/PSSI_D1 - EVENTOUT
PA11 - FDCAN1_RX USB_DM - - - - EVENTOUT
PA12 SAI2_FS_B FDCAN1_TX USB_DP - - - - EVENTOUT
PA13 - - - - - - - EVENTOUT
PA14 - - - - - - - EVENTOUT
PA15 UART4_RTS - - UART7_TX FMC_NBL1 DCMI_D11/PSSI_D11 TIM2_ETR EVENTOUT
Table 16. Alternate function AF8 to AF15(1) (continued)

FDCAN1/2/FMC[
/TIM13/14
PB0 UART4_CTS - - ETH_MII_RXD2 - - LPTIM3_CH1 EVENTOUT

PB1 - - - ETH_MII_RXD3 - - LPTIM3_CH2 EVENTOUT
OCTOSPI1_DQ
PB2 - OCTOSPI1_CLK - SDMMC1_CMD LPTIM5_ETR - EVENTOUT
S
PB3 SPI6_SCK SDMMC2_D2 CRS_SYNC UART7_RX - - LPTIM6_ETR EVENTOUT
PB4 SPI6_MISO SDMMC2_D3 - UART7_TX - DCMI_D7/PSSI_D7 - EVENTOUT
DS14258 Rev 1
PB5 SPI6_MOSI FDCAN2_RX - ETH_PPS_OUT FMC_SDCKE1 DCMI_D10/PSSI_D10 UART5_RX EVENTOUT

PB6 LPUART1_TX FDCAN2_TX OCTOSPI1_NCS - FMC_SDNE1 DCMI_D5/PSSI_D5 UART5_TX EVENTOUT
DCMI_VSYNC/PSSI_
PB7 LPUART1_RX FDCAN1_TX SDMMC2_D5 SDMMC2_CKIN FMC_NL - EVENTOUT
RDY
Port B
PB8 UART4_RX FDCAN1_RX SDMMC2_D4 ETH_MII_TXD3 SDMMC1_D4 DCMI_D6/PSSI_D6 - EVENTOUT

PB9 UART4_TX FDCAN1_TX SDMMC2_D5 SDMMC2_CKIN SDMMC1_D5 DCMI_D7/PSSI_D7 - EVENTOUT
PB10 - OCTOSPI1_NCS - ETH_MII_RX_ER - - - EVENTOUT
ETH_MII_TX_EN/
PB11 - - - FMC_NBL1 - - EVENTOUT
ETH_RMII_TX_EN
ETH_MII_TXD0/E
PB12 - FDCAN2_RX - - - UART5_RX EVENTOUT
TH_RMII_TXD0
PB13 - FDCAN2_TX - - SDMMC1_D0 - UART5_TX EVENTOUT
PB14 UART4_RTS SDMMC2_D0 - - - - LPTIM3_ETR EVENTOUT
ETH_MII_TXD1/E
PB15 UART4_CTS SDMMC2_D1 OCTOSPI1_CLK - DCMI_D2/PSSI_D2 UART5_RX EVENTOUT
TH_RMII_TXD1
117/275
FDCAN1/2/FMC[
/TIM13/14
PC0 SAI2_FS_B FMC_A25 OCTOSPI1_IO7 - FMC_SDNWE - - EVENTOUT

PC1 SAI2_SD_A SDMMC2_CK OCTOSPI1_IO4 ETH_MDC - - - EVENTOUT
PC2 - OCTOSPI1_IO2 - ETH_MII_TXD2 FMC_SDNE0 - - EVENTOUT
PC3 - OCTOSPI1_IO0 - ETH_MII_TX_CLK FMC_SDCKE0 - - EVENTOUT
ETH_MII_RXD0/E
PC4 - - - FMC_SDNE0 - - EVENTOUT
TH_RMII_RXD0
DS14258 Rev 1
OCTOSPI1_DQ ETH_MII_RXD1/E
PC5 - - FMC_SDCKE0 - - EVENTOUT
S TH_RMII_RXD1
SDMMC1_D0D
PC6 FMC_NWAIT SDMMC2_D6 OCTOSPI1_IO5 SDMMC1_D6 DCMI_D0/PSSI_D0 - EVENTOUT
IR
SDMMC1_D12
Port C
PC7 FMC_NE1 SDMMC2_D7 OCTOSPI1_IO6 SDMMC1_D7 DCMI_D1/PSSI_D1 - EVENTOUT

3DIR
FMC_NE2/FMC_
PC8 UART5_RTS FMC_INT FMC_ALE SDMMC1_D0 DCMI_D2/PSSI_D2 - EVENTOUT
NCE

PC9 UART5_CTS OCTOSPI1_IO0 - FMC_CLE SDMMC1_D1 DCMI_D3/PSSI_D3 - EVENTOUT
ETH_MII_TXD0/E
PC10 UART4_TX OCTOSPI1_IO1 - SDMMC1_D2 DCMI_D8/PSSI_D8 - EVENTOUT
TH_RMII_TXD0
PC11 UART4_RX OCTOSPI1_NCS - - SDMMC1_D3 DCMI_D4/PSSI_D4 - EVENTOUT
PC12 UART5_TX - - - SDMMC1_CK DCMI_D9/PSSI_D9 - EVENTOUT
PC13 - - - - - - - EVENTOUT
PC14 - - - - - - - EVENTOUT
PC15 - - - - - - - EVENTOUT

FDCAN1/2/FMC[
/TIM13/14
PD0 UART4_RX FDCAN1_RX - UART9_CTS FMC_D2/FMC_AD2 - - EVENTOUT

PD1 UART4_TX FDCAN1_TX - - FMC_D3/FMC_AD3 - - EVENTOUT
PD2 UART5_RX - - - SDMMC1_CMD DCMI_D11/PSSI_D11 LPTIM4_ETR EVENTOUT
PD3 - - - - FMC_CLK DCMI_D5/PSSI_D5 - EVENTOUT
PD4 - - OCTOSPI1_IO4 - FMC_NOE - - EVENTOUT
PD5 - FDCAN1_TX OCTOSPI1_IO5 - FMC_NWE - - EVENTOUT
DS14258 Rev 1
PD6 - - OCTOSPI1_IO6 SDMMC2_CK FMC_NWAIT DCMI_D10/PSSI_D10 - EVENTOUT

FMC_NE1/FMC_NC
PD7 - - OCTOSPI1_IO7 SDMMC2_CMD - LPTIM4_OUT EVENTOUT
E
Port D
FMC_D13/FMC_AD1
PD8 - - - - - - EVENTOUT
3
FMC_D14/FMC_AD1
PD9 - FDCAN2_RX - - - - EVENTOUT
4
FMC_D15/FMC_AD1
PD10 - - - - - - EVENTOUT
5
PD11 UART4_RX OCTOSPI1_IO0 SAI2_SD_A - FMC_A16/FMC_CLE - - EVENTOUT
PD12 UART4_TX OCTOSPI1_IO1 SAI2_FS_A - FMC_A17/FMC_ALE DCMI_D12/PSSI_D12 - EVENTOUT
PD13 - OCTOSPI1_IO3 SAI2_SCK_A UART9_RTS FMC_A18 DCMI_D13/PSSI_D13 LPTIM4_IN1 EVENTOUT
PD14 UART8_CTS - - UART9_RX FMC_D0/FMC_AD0 - - EVENTOUT
PD15 UART8_RTS - - UART9_TX FMC_D1/FMC_AD1 - - EVENTOUT
119/275
FDCAN1/2/FMC[
/TIM13/14
PE0 UART8_RX FDCAN1_RX SAI2_MCLK_A - FMC_NBL0 DCMI_D2/PSSI_D2 - EVENTOUT

PE1 UART8_TX FDCAN1_TX - - FMC_NBL1 DCMI_D3/PSSI_D3 - EVENTOUT
PE2 UART8_TX OCTOSPI1_IO2 - ETH_MII_TXD3 FMC_A23 DCMI_D3/PSSI_D3 - EVENTOUT
PE3 - - - - FMC_A19 - - EVENTOUT
PE4 - - - - FMC_A20 DCMI_D4/PSSI_D4 - EVENTOUT
PE5 - - - - FMC_A21 DCMI_D6/PSSI_D6 - EVENTOUT
DS14258 Rev 1
PE6 - - SAI2_MCLK_B - FMC_A22 DCMI_D7/PSSI_D7 - EVENTOUT

PE7 - - OCTOSPI1_IO4 - FMC_D4/FMC_AD4 - - EVENTOUT
Port E

PE11 - - SAI2_SD_B - FMC_D8/FMC_AD8 - - EVENTOUT

PE12 - - SAI2_SCK_B - FMC_D9/FMC_AD9 - - EVENTOUT
FMC_D10/FMC_AD1
PE13 - - SAI2_FS_B - - - EVENTOUT
0
FMC_D11/FMC_AD1
PE14 - - SAI2_MCLK_B - - - EVENTOUT
1
FMC_D12/FMC_AD1
PE15 - - - - - - EVENTOUT
2

FDCAN1/2/FMC[
/TIM13/14
PF0 - - - - FMC_A0 LPTIM5_CH1 - EVENTOUT

PF1 - - - - FMC_A1 LPTIM5_CH2 - EVENTOUT
PF2 - - - - FMC_A2 LPTIM5_IN1 - EVENTOUT
PF3 - - - - FMC_A3 LPTIM5_IN2 - EVENTOUT
PF4 - - - - FMC_A4 - - EVENTOUT
PF5 - - - - FMC_A5 - LPTIM3_IN1 EVENTOUT
DS14258 Rev 1
PF6 - - OCTOSPI1_IO3 - - LPTIM5_CH1 - EVENTOUT

PF7 - - OCTOSPI1_IO2 - - LPTIM5_CH2 - EVENTOUT
Port F
PF8 - TIM13_CH1 OCTOSPI1_IO0 - - LPTIM5_IN1 - EVENTOUT

PF9 - TIM14_CH1 OCTOSPI1_IO1 - - LPTIM5_IN2 - EVENTOUT
PF10 - OCTOSPI1_CLK - - - DCMI_D11/PSSI_D11 - EVENTOUT
OCTOSPI1_NCL
PF11 - SAI2_SD_B - FMC_NRAS DCMI_D12/PSSI_D12 LPTIM6_CH1 EVENTOUT
K
PF12 - - - - FMC_A6 - LPTIM6_CH2 EVENTOUT
PF15 - - - - FMC_A9 - - EVENTOUT
121/275
FDCAN1/2/FMC[
/TIM13/14
PG0 - - - UART9_RX FMC_A10 - LPTIM4_IN1 EVENTOUT

PG1 - - - UART9_TX FMC_A11 - - EVENTOUT
PG2 - - - - FMC_A12 - LPTIM6_ETR EVENTOUT
PG3 - - - - FMC_A13 LPTIM5_ETR - EVENTOUT
PG4 - - - - FMC_A14/FMC_BA0 - LPTIM4_ETR EVENTOUT
PG5 - - - - FMC_A15/FMC_BA1 - - EVENTOUT
DS14258 Rev 1
PG6 - - OCTOSPI1_NCS UCPD1_FRSTX FMC_NE3 DCMI_D12/PSSI_D12 - EVENTOUT

PG7 - - - UCPD1_FRSTX FMC_INT DCMI_D13/PSSI_D13 - EVENTOUT
PG8 - - - ETH_PPS_OUT FMC_SDCLK - - EVENTOUT
Port G
FMC_NE2/FMC_NC DCMI_VSYNC/PSSI_
PG9 - OCTOSPI1_IO6 SAI2_FS_B SDMMC2_D0 - EVENTOUT
E RDY
PG10 - - SAI2_SD_B SDMMC2_D1 FMC_NE3 DCMI_D2/PSSI_D2 - EVENTOUT
ETH_MII_TX_EN/

PG11 - - SDMMC2_D2 - DCMI_D3/PSSI_D3 - EVENTOUT
ETH_RMII_TX_EN
ETH_MII_TXD1/E
PG12 - - SDMMC2_D3 FMC_NE4 DCMI_D11/PSSI_D11 LPTIM5_CH1 EVENTOUT
TH_RMII_TXD1
ETH_MII_TXD0/E
PG13 - - SDMMC2_D6 FMC_A24 LPTIM5_CH2 - EVENTOUT
TH_RMII_TXD0
ETH_MII_TXD1/E
PG14 - OCTOSPI1_IO7 SDMMC2_D7 FMC_A25 LPTIM5_IN1 - EVENTOUT
TH_RMII_TXD1
PG15 - - - - FMC_NCAS DCMI_D13/PSSI_D13 - EVENTOUT

FDCAN1/2/FMC[
/TIM13/14
PH0 - - - - - - - EVENTOUT
PH1 - - - - - - - EVENTOUT
PH2 - OCTOSPI1_IO4 SAI2_SCK_B ETH_MII_CRS FMC_SDCKE0 - - EVENTOUT
PH3 - OCTOSPI1_IO5 SAI2_MCLK_B ETH_MII_COL FMC_SDNE0 - - EVENTOUT
PH4 - - - - - PSSI_D14 - EVENTOUT
PH5 - - - - FMC_SDNWE - - EVENTOUT
DS14258 Rev 1
PH6 - - - ETH_MII_RXD2 FMC_SDNE1 DCMI_D8/PSSI_D8 - EVENTOUT

PH7 - - - ETH_MII_RXD3 FMC_SDCKE1 DCMI_D9/PSSI_D9 - EVENTOUT
Port H
DCMI_HSYNC/PSSI_
PH8 - - - - - - EVENTOUT
DE
PH9 - - - - - DCMI_D0/PSSI_D0 - EVENTOUT
PH12 - - TIM8_CH4N - - DCMI_D3/PSSI_D3 - EVENTOUT
PH13 UART4_TX FDCAN1_TX - - - DCMI_D3/PSSI_D3 - EVENTOUT
PH14 UART4_RX FDCAN1_RX - - - DCMI_D4/PSSI_D4 - EVENTOUT
123/275
FDCAN1/2/FMC[
/TIM13/14
PI0 - - - - - DCMI_D13/PSSI_D13 - EVENTOUT

PI4 - - SAI2_MCLK_A - - DCMI_D5/PSSI_D5 - EVENTOUT
DCMI_VSYNC/PSSI_
PI5 - - SAI2_SCK_A - - - EVENTOUT
DS14258 Rev 1
Port I
RDY
PI6 - - SAI2_SD_A - - DCMI_D6/PSSI_D6 - EVENTOUT
PI7 - - SAI2_FS_A - - DCMI_D7/PSSI_D7 - EVENTOUT
PI8 - - - - - - - EVENTOUT
PI9 UART4_RX FDCAN1_RX - - - - - EVENTOUT
PI10 - FDCAN1_RX - ETH_MII_RX_ER - PSSI_D14 - EVENTOUT
PI11 - - - - - PSSI_D15 - EVENTOUT

1. Refer to the previous table for AF0 to AF7.
STM32H562xx and STM32H563xx Electrical characteristics
5 Electrical characteristics
5.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.
5.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TJ = 25 °C and TJ = TJmax (given by the
selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes, and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3σ).
5.1.2 Typical values

Unless otherwise specified, typical data are based on TJ = 25 °C, VDD = VDDA = 3.3 V (for
the 1.71 ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2σ).
5.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 18.
5.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 19.
Figure 18. Pin loading conditions Figure 19. Pin input voltage
MCU pin MCU pin
C = 50 pF VIN
MS19210V MS19211V
DS14258 Rev 1 125/275

244
Electrical characteristics STM32H562xx and STM32H563xx
5.1.6 Power supply scheme
Figure 20. STM32H563 power supply scheme with SMPS

STM32H5
SMPS disabled
SMPS packages
VDDSMPS VDDSMPS
SMPS
ȝ) 4.7 ȝ) ȝ+
VLXSMPS Switched Mode
floating 100 pF or 200 pF
Power Supply
ȝ) ȝ) step down
converter
VSSSMPS
VCAP1/2
Core domain
100 nF
SMPS enabled LDO
Voltage VDDLDO
VDDIO2 VDDIO2 regulator
ȝ)
100 nF VDDIO2
IOs
Two different possible use cases VDD

100 nF VDD
IOs
VDD
VDD
ȝ)
100 nF VDD
domain
VSS Power switch
Two different possible use cases

Backup
VBAT domain
Battery ȝ) 100 nF
BKUP
IOs
VDD
VDDUSB VDDUSB
ȝ) 100 nF USB FS

IOs
VDDA VDDA
Analog domain
ȝ) 100 nF

VREF+
VREF+ 100 nF VREF-
ȝ)
VSSA
Three different possible use cases ȝ) Defines different use case options
Internal VREFBUF
enabled Define power domaines
MSv71967V3
126/275 DS14258 Rev 1

Figure 21. STM32H562/H563 power supply scheme with LDO
STM32H5
LDO packages
VDDSMPS
SMPS
VLXSMPS Switched Mode
Power Supply
step down
VSSSMPS converter
VCAP1/2
[ȝ) 100 nF
Core domain
LDO enabled LDO disabled LDO
Voltage
VDDLDO
regulator
VDDIO2 VDDIO2
ȝ) 100 nF
VDDIO2
IOs
Two different possible use cases VDD

100 nF
VDD
IOs
VDD
VDD
ȝ) 100 nF
VDD
domain
VSS Power switch

Backup
VBAT
domain
ȝ) 100 nF
Battery
BKUP
IOs
VDD
VDDUSB VDDUSB
ȝ) 100 nF
USB FS
IOs
VDDA VDDA
ȝ) 100 nF

VREF+ Analog domain
100 nF
VREF+ VREF-
ȝ) VSSA
ȝ)
Three different possible use cases
Defines different use case options
Internal VREFBUF
enabled
Define power domaines
MSv71966V3
Note: Refer to “Getting started with STM32H5 Series hardware development” (AN5711) for more
details.
DS14258 Rev 1 127/275

244
Caution: Each power supply pair must be decoupled with filtering ceramic capacitors as shown
above. These capacitors must be placed as close as possible to, or below, the appropriate
pins on the underside of the PCB to ensure the good functionality of the device.It is not
recommended to remove filtering capacitors to reduce PCB size or cost. This might cause
incorrect operation of the device.
5.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 17: Voltage characteristics,
Table 18: Current characteristics and Table 19. Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and the functional operation
of the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. Device mission profile (application conditions)
is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are
available on demand.
Table 17. Voltage characteristics(1)

Symbol Ratings Min Max Unit
External main supply voltage (including

VDDx - VSS VDDSMPS(2), VDDA, VDDUSB, VDDIO2(2)(3)(4), -0.3 4.0 V
VBAT, and VREF+)
VDDIOx(4)- I/O supply when HSLV(2) = 0 -0.3 4.0

V
VSS I/O supply when HSLV (2)
=1 -0.3 2.75
min (min(VDD, VDDA, VDDUSB,
Input voltage on FT_xxx pins except FT_c pins VSS-0.3 V
VDDIO2) + 4.0, 6.0 V)(6)(7)
min (min(VBAT, VDDA, VDDUSB,
Input voltage on FT_t in VBAT mode VSS-0.3
VDDIO2) + 4.0V, 6.0 V)
VIN(5) Input voltage on TT_xx pins VSS-0.3 4.0

min (min(VDD, VDDA, VDDUSB,
Input voltage on BOOT0 pin VSS V
VDDIO2) + 4.0, 6.0 V)(6)
Input voltage on FT_c pins VSS-0.3 5.5
Input voltage on any other pins VSS-0.3 4.0
VREF+-VDDA Allowed voltage difference for VREF+ > VDDA - 0.4
Variations between different VDDX power pins
|∆VDDx| - 50.0
of the same domain mV
|VSSx-VSS| Variations between all the different ground pins - 50.0
1. All main power (VDD, VDDAVDDUSB, VDDIO2, VREF+, VDDSMPS, VBAT) and ground (VSS, VSSA) pins must always be
connected to the external power supply, in the permitted range.
2. HSLV = High-speed low-voltage mode. Refer to General-purpose I/Os (GPIO) section of RM0481.
3. If HSLV = 0.
4. VDDIO1 or VDDIO2. VDDIO1 = VDD.
5. VIN maximum must always be respected. Refer to the maximum allowed injected current values.
6. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
7. This formula has to be applied on power supplies related to the I/O structure described by the pin definition table.
128/275 DS14258 Rev 1

Table 18. Current characteristics

Symbol Ratings Max Unit
∑IVDD Total current into sum of all VDD power lines (source)(1) 350
∑IVSS Total current out of sum of all VSS ground lines (sink)(1) 350
IVDD Maximum current into each VDD power pin (source)(1) 100
IVSS Maximum current out of each VSS ground pin (sink)(1) 100
IIO(PIN) Output current sourced by any I/O and control pin 20 mA
(2)
Total output current sunk by sum of all I/Os and control pins 140
∑IIO(PIN)
(2)
Total output current sourced by sum of all I/Os and control pins 140
IINJ(PIN)(3)(4) Injected current on FT_xxx, TT_xx, NRST pins -5 / 0
∑|IINJ(PIN)| Total injected current (sum of all I/Os and control pins)(5) ±25
1. All main power (VDD, VDDA, VDDIO2, and VBAT) and ground (VSS, VSSA) pins must always be connected to
the external power supplies, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
LQFP packages.
3. Positive injection (when VIN > VDDIOx) is not possible on these I/Os and does not occur for input voltages
lower than the specified maximum value.
4. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 17:
Voltage characteristics for the minimum allowed input voltage values.
5. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of
the negative injected currents (instantaneous values).
Table 19. Thermal characteristics

Symbol Ratings Value Unit
TSTG Storage temperature range -65 to +150 °C

TJ Maximum junction temperature 130(1) °C
1. The junction temperature is limited to 105 °C in the VOS0 voltage range.
5.3 Operating condition
5.3.1 General operating conditions

Table 20. General operating conditions
Symbol Parameter Operating conditions Min Typ Max Unit
HSLV(1) = 0 1.71(2) - 3.6 V

Standard operating
VDD
voltage
HSLV(1) = 1 1.71(2) - 2.7 V
Supply voltage for the

VDDSMPS internal SMPS step- VDD VDD - VDD V
down converter
DS14258 Rev 1 129/275

244
Table 20. General operating conditions (continued)

At least one I/O in PB8, PB9, PD6, PD7,

1.08 - 3.6
PG[9:14] is used, HSLV(1) = 0
PB8, PB9, PD6, PD7,
At least one I/O in PB8, PB9, PD6, PD7,
VDDIO2 PG[9:14] I/Os supply 1.08 - 2.7 V
PG[9:14] is used, HSLV(1) = 1
voltage
PB8,PB9, PD6,PD7, PG[9:14] not use 0 3.6
USB used 3.0 - 3.6

VDDUSB USB supply voltage V
USB not used 0 - 3.6
ADC is used 1.62 -
DAC is used 1.8 -

VDDA Analog supply voltage 3.6 V
VREFBUF is used 2.1 -
ADC, DAC, and VREFBUF are not used 0 -

Backup domain supply
VBAT - 1.2 - 3.6 V
voltage
min (min
(VDD,
VDDA,
VDDUSB,
All I/O except FT_c and TT_xx -0.3 -
VDDIO2)
+ 3.6V,
5.5
V)(3)(4)
min (min
VIN I/O input voltage (VBAT, V
VDDA,
VDDUSB,
Input voltage on FT_t in VBAT mode -0.3 -
VDDIO2)
+ 3.6 V,
5.5 V)(3)(
4)
FT_c I/O -0.3 - 5.0

VDDIOx +
TT_xx I/O -0.3 -
0.3
130/275 DS14258 Rev 1


(5)
VOS0 (max frequency for AHB and APB:
1.30 1.35 1.40
250 MHz)
VOS1 (max frequency for AHB and APB: 200
1.15 1.20 1.26
MHz)
Internal regulator ON V
1.05 1.10 1.15
MHz)
0.95 1.00 1.05
MHz)
VCORE Regulator OFF: VOS0(5) 1.32 1.35 1.40
external VCORE
VOS1 1.17 1.20 1.26
voltage must be
V
supplied from external VOS2 1.07 1.10 1.15
regulator on VCAP
pins. VOS3 0.97 1.00 1.05
SVOS3 - 1.0 -
Stop mode SVOS4 - 0.9 - V
SVOS5 - 0.74 -
(5)
VOS0 - - 250
VOS1 - - 200
fHCLK AHB clock frequency MHz
VOS2 - - 150
VOS3 - - 100
VOS0(5) - - 250
fPCLKx APB1, APB2, APB3 VOS1 - - 200

MHz
(x=1,2,3) clock frequency VOS2 - - 150
VOS3 - - 100
LQFP64 See Table 19: Thermal
characteristics for
LQFP100
application appropriate
LQFP144 thermal resistance and
package. Power
Power dissipation at LQFP176 dissipation is then
PD TA = 85 °C for suffix mW
UFBGA169 calculated according to
6(6)
ambient temperature
UFBGA176 (TA), maximum junction
VFQFPN68 temperature (TJ) and
selected thermal
WLCSP80 resistance.
DS14258 Rev 1 131/275

244

LQFP64 See Table 19: Thermal

characteristics for
LQFP100
application appropriate
LQFP144 thermal resistance and
package. Power
Power dissipation at LQFP176 dissipation is then
PD TA = 125 °C for suffix mW
UFBGA169 calculated according to
3(6)
ambient temperature
UFBGA176 (TA), maximum junction
VFQFPN68 temperature (TJ) and
selected thermal
WLCSP80 resistance.
Ambient temperature
Maximum power dissipation -40 - 125 °C
for the suffix 3 version
TA
Ambient temperature
Maximum power dissipation -40 - 85 °C
for the suffix 6 version
Junction temperature VOS0 -40 - 105

TJ °C
range VOS1, VOS2, and VOS3 -40 - 130
1. HSLV = High-speed low-voltage mode. Refer to General-purpose I/Os (GPIO) section of RM0481.
2. When RESET is released functionality is guaranteed down to BOR level 0 minimum voltage.
3. This formula has to be applied on power supplies related to the IO structure described by the pin definition table. Maximum
I/O input voltage is the smallest value between min (VDD, VDDA, VDDIO2) + 3.6 V and 5.5 V.
4. For operation with voltage higher than min (VDD, VDDA, VDDIO2) +0.3V, the internal pull-up and pull-down resistors must
be disabled.
5. In VOS0 mode the max TJ is 105 °C.
6. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 19: Thermal characteristics).
132/275 DS14258 Rev 1

Table 21. Maximum allowed clock frequencies

(1)(2) VOS1
Symbol Parameter VOS0 VOS2 VOS3 Unit
fCPU CPU 250 200 150 100

fHCLK AHB 250 200 150 100
fPCLK APB 250 200 150 100
- FMC 250 200 150 100
foctospi_ker_ck OCTOSPI[1:2] 250 200 150 100
fsdmmc_ker_ck SDMMC[1:2] 250 200 150 100
- HDMI_CEC 4 4 4 4
ffdcan_ker_ck FDCAN 250 200 150 100
fI2C_ker_ck I2C[1:4] 250 200 150 100
fI3C_ker_ck I3C 250 200 150 100
flptim_ker_ck LPTIM[1:6] 250 200 150 100
TIM[1:8] TIM[12:17] 250 200 150 100
ftim_ker_ck
TIM6/17 64 64 64 64
MHz
frng_clk RNG 50 50 50 50
fsai_a_ker_ck
SAI1/2 250 200 150 100
fsai_b_ker_ck
SPI(I2S)1,2,3 125 100 75 50
fspi_ker_ck
SPI 4,5,6 125 100 75 50
flpuart_ker_ck LPUART1 250 200 150 100
fusart_ker_ck USART/UART 250 200 150 100
fusb_ker_ck USB2FS 50 50 50 50
fadc_ker_ck ADC/DAC 125 100 75 50
fdac_pclk DAC 250 200 150 100
fusb_ker_ck USBPD 64 64 64 64
frtc_ker_ck RTC 1 1 1 1
- DCMI 250 200 150 100
1. Specified by design - Not tested in production.
2. The maximum kernel clock frequencies can be limited by the maximum peripheral clock frequency
(refer to each peripheral electrical characteristics).
DS14258 Rev 1 133/275

244
5.3.2 VCAP external capacitor

Stabilization for the embedded LDO regulator is achieved by connecting an external
capacitor CEXT to the VCAPx (one or two pins depending on the packages). CEXT is
specified in Table 25. VCAP operating conditions. Two external capacitors must be
connected to VCAP pins (refer to STM32H5 Series hardware development (AN5711).
Figure 22. External capacitor CEXT

C
ESR
R Leak
MS19044V2
1. Legend: ESR is equivalent series resistance.
Table 22. Supply voltage and maximum frequency configuration

Symbol Parameter Conditions
CEXT External capacitor for LDO enabled 2.2 μF(1)

ESR ESR of external capacitor < 100 mΩ
1. This value corresponds to CEXT typical value. A variation of ±20% is tolerated
5.3.3 SMPS step-down converter

The devices embed a high power efficiency SMPS step-down converter requiring external
components.
Table 23. Characteristics of SMPS step-down converter external components

Capacitance of external capacitor on VDDSMPS 4.7 µF

Cin
ESR of external capacitor 100 mΩ
Cfilt Capacitance of external capacitor on VLXSMPS pin 220 pF
Capacitance of external capacitor on VCAP pin 10 µF
COUT
ESR of external capacitor 20 mΩ
L Inductance of external Inductor on VLXSMPS pin 2.2 µH
- Serial DC resistor 150 mΩ
DC current at which the inductance drops 30% from
ISAT 1.7 A
its value without current.
Average current for a 40 °C rise: rated current for
IRMS which the temperature of the inductor is raised 40°C 1.4 A
by DC current
134/275 DS14258 Rev 1

The SMPS current consumption can be determined using the following formula based on
the maximum LDO current consumption provided in Section 5.3.7: Supply current
characteristics:
IDDSMPS=IDDLDO×(VCORE÷(VDD×efficency))
Where: IDDLDO is the current in LDO configuration given in the following tables, VCORE is
the digital core supply (VCAP), and efficiency is defined in the following curves.
Figure 23. SMPS efficiency versus load current in run, sleep and stop mode
with SVOS3 mode, TJ = 30 °C
Efficiency (%)
100
90
VDDSMPS = 1.8V, VOS0

80 VDDSMPS = 1.8V, VOS1
60
50
40
30
Current (mA)
1 10 100 1000
MSv71968V1
Note: SVOS3 is equivalent to VOS3 in run and sleep mode.
Figure 24. SMPS efficiency versus load current in Run, Sleep and Stop mode
with SVOS3 mode, TJ = 130 °C
Efficiency (%)
100
90

60
50
40
30 Current (mA)
1 10 100 1000 MSv71969V1
Note: SVOS3 is equivalent to VOS3 in run and sleep mode.
DS14258 Rev 1 135/275

244
Figure 25. SMPS efficiency versus load current in stop SVOV4, SVOS5, TJ = 30 °C
Figure 26. SMPS efficiency versus load current in stop SVOV4, SVOS5, TJ = 130 °C
136/275 DS14258 Rev 1

5.3.4 Operating conditions at power-up / power-down

Subject to general operating conditions for TA.
Operating conditions at power-up / power-down (regulator ON)
v
Table 24. Operating conditions at power-up/power-down (regulator ON)

Symbol Parameter Min Max Unit
VDD rise time rate 0 ∞

TVDD
VDD fall time rate 10 ∞
VDDA rise time rate 0 ∞

TVDDA
VDDA fall time rate 10 ∞
TVDDUSB rise time rate 0 ∞

TVDDUSB μs/V
TVDDUSB fall time rate 10 ∞
TVDDIO2 rise time rate 0 ∞

TVDDIO2
TVDDIO2 fall time rate 10 ∞
TVBAT rise time rate 0 ∞

TVBAT
TVBAT fall time rate 10 ∞
DS14258 Rev 1 137/275

244
5.3.5 Embedded reset and power control block characteristics

The parameters given in Table 25: Embedded reset and power control block characteristics
are derived from tests performed under ambient temperature and VDD supply voltage
conditions summarized in Table 20: General operating conditions.
Table 25. Embedded reset and power control block characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit
Reset temporization after BOR0 is

tRSTTEMPO(2) VDD rising - 377 550 μs
detected
Power-on/power-down reset threshold Rising edge 1.62 1.67 1.71

VPOR/PDR
(BORH_EN =0) Falling edge 1.58 1.62 1.68
Brownout reset threshold 1 Rising edge 2.04 2.10 2.15

VBOR1

VBOR2

VBOR3
Programmable voltage detector (PVD) Rising edge 1.90 1.96 2.01

VPVD0
threshold 0 Falling edge 1.81 1.86 1.91

VPVD1 V

VPVD2

VPVD3

VPVD4

VPVD5

VPVD6
Hysteresis for power-on/power-down Hysteresis in run
VPOR/PDR - 43 -
reset mode
mV
Hysteresis voltage of BOR (unless
Vhyst_BOR_PVD - - 100 -
BORH_EN = 0) and PVD
IDD_BOR_PVD(2) BOR and PVD consumption from VDD - - - 0.630
µA
IDD_POR_PDR POR and PDR consumption from VDD - 0.8 - 1.2
138/275 DS14258 Rev 1

Table 25. Embedded reset and power control block characteristics(1) (continued)
Rising edge 1.66 1.71 1.76

VAVD0 VDDA voltage monitor 0 threshold
Falling edge 1.56 1.61 1.66
Rising edge 2.06 2.12 2.19
VAVD1 VDDA voltage monitor 1threshold
V
Rising edge 2.42 2.50 2.58
Rising edge 2.74 2.83 2.91
VIO2VM VDDIO2 voltage monitor threshold - - 0.9 - V
Vhyst_AVD Hysteresis of VDDA voltage monitor - - 100 - mV
Power voltage detector consumption
IDD_AVD_IO2VM(2) - - - 0.25
from VDD (AVD, IO2VM)
VDDA analog voltage detector µA
IDD_AVD_A (2) consumption from VDDA (resistor - - - 0.25
bridge)
1. Evaluated by characterization and not tested in production, unless otherwise specified.
2. Specified by design - not tested in production
5.3.6 Embedded reference voltage

The parameters given in the table below are derived from tests performed under the
ambient temperature and supply voltage conditions summarized in Table 26.
Table 26. Embedded reference voltage

VREFINT(1) Internal reference voltage -40 °C < TJ < +130 °C 1.180 1.216 1.255 V
ADC sampling time when reading the
tS_vrefint(2)(3) - 4.3 - -
internal reference voltage
VBAT sampling time when reading the
tS_vbat 9 - - µs
internal VBAT voltage
Start time of reference voltage buffer
tstart_vrefint(3) - - - 4.4
when the ADC is enabled
Irefbuf(3) Reference buffer consumption for ADC VDD = 3.3 V 9 13.5 23 µA
Internal reference voltage spread
∆VREFINT(3) -40°C < TJ < +130 °C - 5 15 mV
over the temperature range
Average temperature
TCoeff Average temperature coefficient - 20 70 ppm/°C
coefficient
VDDcoeff Average voltage coefficient 3.0 V < VDD < 3.6 V - 10 1370 ppm/V
DS14258 Rev 1 139/275

244
Table 26. Embedded reference voltage (continued)

(3)
VREFINT_DIV1 1/4 reference voltage - 25 -
%
VREFINT_DIV2(3) 1/2 reference voltage - - 50 -
VREFINT
VREFINT_DIV3(3) 3/4 reference voltage - 75 -
1. VREFINT does not take into account package and soldering effects.
2. The shortest sampling time for the application can be determined by multiple iterations.
3. Specified by design - not tested in production
Table 27. Internal reference voltage calibration value

Symbol Parameter Memory address
VREFINT_CAL Raw data acquired at temperature of 30 °C, VDDA = 3.3 V 0x08FF F810 - 0x08FF F811
5.3.7 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
All the run-mode current consumption measurements given in this section are performed
with a CoreMark code.
Typical and maximum current consumption

The MCU is placed under the following conditions:
• All I/O pins are in analog input mode.
• All peripherals are disabled except when explicitly mentioned.
• The flash memory access time is adjusted with the minimum wait-state number,
depending on the fHCLK frequency (refer to the tables “FLASH recommended number
of wait states and programming delay” available in the reference manual).
• When the peripherals are enabled, the AHB clock frequency is the CPU frequency and
the APB clock frequency is AHB frequency.
The parameters given in the below tables are derived from tests performed under supply
voltage conditions summarized in Table 20: General operating conditions and unless
otherwise specified at ambient temperature.
The maximum current consumptions provided in the following tables are given for LDO
regulator ON.
140/275 DS14258 Rev 1

running from flash memory, 2-ways instruction cache ON, PREFETCH ON
Parameter Max(1)(2)
Symbol
fHCLK Typ Typ

Conditions Unit
(MHz) LDO SMPS TJ = TJ = TJ = TJ =
25°C 85°C 105°C 130°C
250 32.1 17.5 41 89 124 -

VOS0 215 27.9 15.0 37 84 119 -
200 25.7 13.8 35 84 120 -
200 22.1 11.0 28 63 92 140
180 20.3 10.1 26 58 84 134
VOS1
All peripherals 168 18.8 9.3 24 60 86 136
disabled
150 16.9 8.5 22 59 84 134
150 15.4 7.4 19 47 70 111
VOS2
100 10.8 5.2 15 41 62 104
100 9.8 4.5 13 33 50 83
VOS3 60 6.4 3.0 9 30 46 79
IDD Supply current
25 3.2 1.7 6 26 42 75 mA
(Run) in run mode
250 100.8 55.7 110 164 203 -
VOS0 215 87.1 46.7 96 151 190 -
200 80.8 43.3 90 147 188 -
200 70.5 34.5 76 116 147 203
VOS1 180 63.8 31.4 69 106 135 192
All peripherals
150 53.2 27.0 58 100 129 184
enabled
150 48.9 23.1 52 85 108 154
VOS2
100 32.8 15.6 37 67 90 137
100 29.8 13.3 33 55 74 113
VOS3 60 18.4 8.0 21 44 63 103
25 8.2 3.8 12 35 54 92
1. Evaluated by characterization - Not tested in production.
2. The maximum values are given for LDO regulator ON. Refer to Section 5.3.3: SMPS step-down converter for the SMPS
maximum current consumption.
DS14258 Rev 1 141/275

244
running from flash memory, 1-way instruction cache ON, PREFETCH ON
Parameter Max(1)(2)
Symbol
fHCLK Typ Typ

Conditions Unit
25°C 85°C 105°C 130°C
250 29.2 15.9 38 86 121 -

VOS0
200 23.3 12.5 32 81 117 -
200 20.1 10.0 26 61 86 136
VOS1 180 18.5 9.2 24 57 82 133
IDD Supply current All peripherals
150 15.4 7.8 21 55 81 132 mA
(Run) in run mode disabled
150 14.0 6.7 18 45 66 108
VOS2
100 9.8 4.8 14 40 61 104
100 8.9 4.2 12 32 49 82
VOS3
25 3.0 1.6 6 26 42 75
running from SRAM with cache 1-WAY
Max(1)(2)
Parameter
Symbol
fHCLK Typ Typ

Conditions Unit
25°C 85°C 105°C 130°C
250 27.8 15.5 37 85 120 -

VOS0 215 24.1 13.4 33 81 116 -
200 22.1 12.3 32 80 115 -
200 19.1 9.9 25 60 85 135
VOS1 180 17.6 9.1 23 56 81 133
IDD Supply current All peripherals
150 14.6 7.6 25 60 85 135 mA
(Run) in run mode disabled
150 13.3 6.6 20 54 79 131
VOS2
100 9.4 4.7 13 40 61 103
100 8.5 4.1 11 32 49 82
VOS3 60 5.6 2.8 8 29 45 78
25 2.9 1.6 6 26 42 75
142/275 DS14258 Rev 1

running from SRAM with cache 2-WAY
Parameter Max(1)(2)
Symbol
fHCLK Typ Typ

Conditions Unit
25°C 85°C 105°C 130°C
250 30.8 17.2 40 88 123 -

VOS0 215 26.7 14.4 36 84 119 -
200 24.6 13.3 34 84 119 -
200 21.2 10.5 27 62 90 139
180 19.5 9.7 25 58 83 134
VOS1
IDD Supply current All peripherals 168 18.0 9.0 24 59 86 135
mA
(Run) in run mode disabled 150 16.2 8.4 22 58 83 134
150 14.8 7.2 19 47 69 110
VOS2
100 10.3 5.1 14 40 62 104
100 9.4 4.5 12 32 50 83
VOS3 60 6.1 2.9 9 29 46 79
25 3.2 1.7 6 26 42 75
DS14258 Rev 1 143/275

244
Table 32. Typical consumption in run mode with CoreMark running

from flash memory and SRAM(1)
Parameter
Conditions
Symbol
fHCLK Typ Typ Typ Typ

Unit Unit
(MHz) LDO SMPS LDO SMPS
Peripheral code
250 32.1 17.5 128.6 70.1

All peripherals
200 22.1 10.97 110.7 54.8
disabled,
instruction cache FLASH 168 18.8 9.3 111.8 55.6
2-WAY,
150 15.4 8.5 102.7 56.9
prefetch ON
100 9.8 4.5 97.9 45.3
All peripherals 250 29.2 15.9 116.6 63.8

disabled, 200 20.1 12.5 100.4 62.7
instruction cache FLASH
1-WAY, 150 14.0 10.0 93.3 66.4
prefetch ON 100 8.9 4.2 88.9 41.7
IDD Supply current
mA μA/MHz
(Run) in run mode 250 30.8 17.2 123.3 68.7
All peripherals 200 21.2 10.5 106.2 52.6
disabled,
SRAM 168 18.0 9.0 107.3 53.4
instruction cache
2-WAY 150 14.8 7.2 98.5 48.2
100 9.4 4.5 94.1 44.6
250 27.8 15.5 111.1 61.9
All peripherals
disabled, 200 19.1 9.9 95.4 49.3
SRAM
instruction cache 150 13.3 6.6 88.9 43.8
1-WAY
100 8.5 4.1 84.9 40.7
144/275 DS14258 Rev 1

Table 33. Typical consumption in run mode with SecureMark running from
flash memory and SRAM(1)
Parameter
Conditions
Symbol
fHCLK Typ Typ Typ Typ

Unit Unit
(MHz) LDO SMPS LDO SMPS
Peripheral code
250 34.1 17.9 136.3 71.8

180 21.8 10.6 120.9 58.8
All peripherals disabled,
instruction cache 2- FLASH 168 20.1 9.8 119.7 58.5
WAY, prefetch ON
150 24.9 7.7 166.2 51.2
Supply 100 10.6 4.8 106.0 47.6
IDD
current in mA μA/MHz
(Run) run mode 250 31.3 16.6 125.2 66.3
180 20.1 9.8 111.6 54.5
All peripherals disabled,
instruction cache 1- FLASH 168 18.5 9.1 110.4 54.2
WAY, prefetch ON
150 18.8 7.2 125.1 47.7
100 9.8 4.5 98.3 44.5
Table 34. Typical and maximum current consumption in sleep mode

Max(1) (2)
Parameter
Symbol
fHCLK Typ Typ

Conditions Unit
25°C 85°C 105°C 130°C
250 7.3 4.2 17 64 100 -

VOS0
200 5.8 3.3 15 63 99 -
200 4.8 2.6 11 44 70 121
180 4.8 2.6 10 44 70 121
VOS1
IDD Supply current All peripherals 168 4.3 2.3 10 44 70 120
mA
(sleep) in sleep mode disabled 150 3.9 2.2 10 43 69 120
150 3.5 1.9 8 34 54 95
VOS2
100 2.8 1.6 7 33 54 94
100 2.5 1.4 6 25 42 74
VOS3
60 2.0 1.2 5 25 41 74
DS14258 Rev 1 145/275

244
Table 35. Typical and maximum current consumption in stop mode
Max(1) (2)
Parameter
Symbol
Typ Typ
Conditions Unit
LDO SMPS TJ = TJ = TJ = TJ =
25°C 85°C 105°C 130°C
SVOS3 0.37 0.09 3.1 20.8 35.1 63.5

Flash memory in
low power mode, SVOS4 0.27 0.07 2.1 15.5 26.8 49.6
SRAMs ON
SVOS5 0.19 0.06 1.3 10.2 18.3 35.2
Flash memory in SVOS3 0.38 0.10 3.1 20.8 35.2 63.7
normal mode,
SRAMs SVOS4 0.29 0.09 2.2 15.6 26.9 49.8
IDD Supply current
Flash memory in SVOS3 0.34 0.09 3.0 19.9 33.5 60.6 mA
(stop) in stop
low power mode,
SVOS4 0.25 0.07 2.1 14.7 25.5 46.9
all SRAMs OFF except
SRAM2 16 Kbytes ON SVOS5 0.17 0.05 1.2 9.4 16.7 32.1
Flash memory in SVOS3 0.35 0.10 3.0 20.1 33.9 61.3
low power mode,
SVOS4 0.26 0.08 2.1 14.9 25.7 47.5
SRAMs OFF except
SRAM2 ON SVOS5 0.17 0.08 1.2 9.6 17.1 33.8
vv
Table 36. Typical and maximum current consumption in standby mode
Conditions Typ(1) Max(1)

Parameter
Symbol
Unit
RTC
Backup TJ = TJ = TJ = TJ =
and 1.8 V 2.4 V 3V 3.3 V
RAM 25 (°C) 85 (°C) 105 (°C) 130 (°C)
LSE(2)
Supply OFF OFF 2.58 2.78 3.01 3.19 4.3 8.8 16.5 42.6
current in ON OFF 3.79 4.05 4.38 4.63 6 17 30 75
IDD
standby μA
(standby) mode, OFF ON 2.91 3.15 3.47 3.67 - - - -
IWDG OFF ON ON 4.16 4.46 4.85 5.12 - - - -
2. LSE is in medium-low drive mode.
146/275 DS14258 Rev 1

Table 37. Typical and maximum current consumption in VBAT mode
Conditions Typ(1) (V) Max(1) (°C)
Parameter
Symbol
Unit
RTC
Backup TJ = TJ = TJ = TJ =
and 1.62 2 3 3.3
RAM 25 85 105 130
LSE(2)
OFF OFF 0.01 0.01 0.02 0.02 0.2 2.0 4.9 14.9
IDD Supply current ON OFF 1.11 1.14 1.17 1.29 3 14 27 62

μA
(VBAT) in VBAT mode OFF ON 0.45 0.46 0.48 0.59 - - - -
ON ON 1.56 1.57 1.62 1.84 - - - -
2. LSE is in medium-low drive mode.
I/O system current consumption

I/O static current consumption
All the I/Os used as inputs with pull-up generate a current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 65. I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
An additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid a current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption (see Table 44. Peripheral current
consumption in run mode), the I/Os used by an application also contribute to the current
consumption. When an I/O pin switches, it uses the current from the MCU supply voltage to
supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external)
connected to the pin:
I SW = V DDx × f SW × C L
DS14258 Rev 1 147/275

244
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDDx is the MCU supply voltage
fSW is the I/O switching frequency
CL is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
On-chip peripheral current consumption

The MCU is placed under the following conditions:
• At startup, all I/O pins are in analog input configuration.
• All peripherals are disabled unless otherwise mentioned.
• The I/O compensation cell is enabled.
• fHCLK is the CPU clock. fPCLK = frcc_cpu_ck, and fHCLK = frcc_cpu_ck.
The given value is calculated by measuring the difference of current consumption:
• with all peripherals clocked off
• with only one peripheral clocked on
• frcc_cpu_ck = 250 MHz (Scale 0), frcc_cpu_ck = 200 MHz (Scale 1), frcc_cpu_ck = 150 MHz
(Scale 2), frcc_cpu_ck= 100 MHz (Scale 3)
• the ambient operating temperature is 25 °C and VDD=3.0 V
Table 38. Peripheral current consumption in sleep mode

IDD (typ)
BUS Peripheral Unit
VOS0 VOS1 VOS2 VOS3
SRAM1 0.9 0.85 0.78 0.7

BKPRAM 0.95 0.89 0.82 0.74
CORDIC 0.5 0.45 0.42 0.4
CRC 0.22 0.21 0.18 0.18
DCACHE 0.66 0.59 0.55 0.51
ETH 11.33 10 9.13 8.32
FLASH 10.19 8.87 8.09 7.35
AHB1 μA/MHz
FMAC 2.07 1.84 1.68 1.56
GPDMA1 0.62 0.55 0.51 0.45
GPDMA2 0.45 0.43 0.38 0.35
GTZC1 1.19 1.05 0.97 0.9
ICACHE 0.86 0.81 0.75 0.67
RAMCFG 0.88 0.79 0.71 0.67
AHB1 1.09 0.94 0.86 0.79
148/275 DS14258 Rev 1

Table 38. Peripheral current consumption in sleep mode (continued)

IDD (typ)
BUS Peripheral Unit
VOS0 VOS1 VOS2 VOS3
ADC12 2.35 2.1 1.9 1.74

DAC1 1.35 1.19 1.07 0.98
DCMI 3.49 3.09 2.83 2.55
GPIOA 0.1 0.08 0.07 0.08
GPIOB 0.07 0.06 0.05 0.05
GPIOC 0.08 0.05 0.04 0.04
GPIOD 0.09 0.06 0.05 0.04
GPIOE 0.09 0.09 0.08 0.05
GPIOF 0.06 0.08 0.08 0.05
AHB2 μA/MHz
GPIOG 0.07 0.07 0.06 0.04
GPIOH 0.07 0.07 0.05 0.06
GPIOI 0.07 0.07 0.06 0.04
HASH1 1.37 1.2 1.1 1
PKA 5.43 4.78 4.37 3.98
RNG1 1.12 0.99 0.9 0.82
SRAM2 1.33 1.18 1.06 0.96
SRAM3 1.5 1.33 1.22 1.1
AHB2 1.59 1.39 1.29 1.16
FMC 9.73 8.48 7.69 6.95
OSPI1 2.88 2.54 2.29 2.08
AHB4 SDMMC1 8.71 7.64 6.98 6.36 uA/MHz
SDMMC2 8.46 7.45 6.82 6.2
AHB4 0.36 0.32 0.32 0.28
DS14258 Rev 1 149/275

244

IDD (typ)
BUS Peripheral Unit
VOS0 VOS1 VOS2 VOS3
CEC 0.15 0.15 0.14 0.11

CRS 0.22 0.23 0.2 0.19
FDCAN1 6.37 5.63 5.14 4.7
I2C1 0.57 0.5 0.49 0.42
I2C2 0.57 0.52 0.5 0.46
I3C1 0.28 0.27 0.28 0.25
LPTIM2 0.91 0.81 0.75 0.69
SPI2 1.04 0.93 0.89 0.78
SPI3 1 0.92 0.85 0.76
TIM12 1.41 1.26 1.18 1.06
TIM13 0.92 0.82 0.77 0.7
TIM14 0.89 0.78 0.75 0.66
TIM2 2.86 2.51 2.3 2.11
TIM3 2.52 2.21 2.03 1.87
TIM4 2.43 2.15 1.96 1.79
TIM5 2.79 2.48 2.26 2.06
APB1 μA/MHz
TIM6 0.54 0.49 0.45 0.42
TIM7 0.56 0.5 0.48 0.43
UART12 1.17 1.06 0.95 0.88
UART4 1.12 0.98 0.93 0.83
UART5 1.09 0.99 0.93 0.84
UART7 1.28 1.14 1.05 0.93
UART8 1.17 1.06 0.94 0.86
UART9 1.12 1 0.9 0.84
UCPD1 1.1 1 0.9 0.84
USART10 1.35 1.22 1.14 1.02
USART11 1.24 1.11 1.04 0.94
USART2 1.42 1.29 1.19 1.07
USART3 1.35 1.24 1.14 1.02
USART6 1.19 1.08 1.02 0.92
WWDG1 0.39 0.35 0.35 0.3
APB1 1.85 1.61 1.49 1.34
150/275 DS14258 Rev 1


IDD (typ)
BUS Peripheral Unit
VOS0 VOS1 VOS2 VOS3
SAI1 1.13 0.99 0.93 0.82

SAI2 1.06 0.9 0.85 0.75
SPI1 1.03 0.91 0.85 0.75
SPI4 1.03 0.89 0.83 0.73
SPI6 1.03 0.9 0.85 0.74
TIM1 4.35 3.86 3.52 3.2
APB2 TIM15 2.08 1.84 1.69 1.54 μA/MHz
TIM16 1.43 1.26 1.16 1.05
TIM17 1.44 1.25 1.17 1.05
TIM8 4.33 3.82 3.5 3.18
USART1 1.24 1.11 1.02 0.91
USBFS 2.53 2.22 2.04 1.84
APB2 1.04 0.92 0.84 0.77
I2C3 2.43 2.14 1.93 1.76
I2C4 2.37 2.08 1.89 1.73
LPTIM1 0.92 0.82 0.75 0.67
LPTIM3 0.88 0.77 0.71 0.65
LPTIM4 0.49 0.45 0.41 0.37
LPTIM5 0.84 0.76 0.69 0.63
APB3 LPTIM6 0.93 0.82 0.76 0.7 uA/MHz
LPUART1 0.84 0.74 0.66 0.63
RTCAPB 1.93 1.7 1.54 1.38
SBS 0.45 0.41 0.38 0.34
SPI5 1.05 0.93 0.84 0.75
VREFBUF 0.08 0.08 0.07 0.05
APB3 0.64 0.57 0.53 0.48
Wakeup time from low-power modes

The wakeup times given in Table 39: Low-power mode wakeup timings are measured
starting from the wakeup event trigger up to the first instruction executed by the CPU:
• for Stop or Sleep modes: the wakeup event is WFE.
• WKUP (PA1) pin is used to wakeup from Standby, Stop and Sleep modes.
All timings are derived from tests performed under ambient temperature and VDD=3.0 V.
DS14258 Rev 1 151/275

244
Table 39. Low-power mode wakeup timings(1)

Symbol Parameter Conditions Typ Max Unit
Instruction cache enabled 15 16 CPU

Wakeup time from
tWUSLEEP clock
sleep Instruction cache disabled 15 16 cycles
SVOS3, HSI 64MHz, flash memory in normal mode 4.0 4.8
SVOS3, HSI 64MHz, flash memory in low-power mode 7.9 11.5
SVOS4, HSI 64MHz, flash memory in normal mode 13.8 16.0
SVOS4, HSI 64MHz, flash memory in low-power mode 17.7 21.9
Wakeup time from SVOS5, HSI 64MHz, flash memory in low-power mode 31.4 36.8
tWUSTOP
stop mode SVOS3, CSI 4MHz, flash memory in normal mode 25.5 31.0 µs
SVOS3, CSI 4MHz, flash memory in low power mode 27.7 34.2
SVOS4, CSI 4MHz, flash memory in normal mode 35.3 40.8
SVOS4, CSI 4 MHz, flash memory in low-power mode 37.5 44.0
SVOS5, CSI 4 MHz, flash memory in low-power mode 51.2 58.9
Wakeup time from
tWUSTBY VCAP capacitors discharged 506.0 653.6
standby mode
5.3.8 External clock source characteristics

High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the Table 40: High-speed external user clock
characteristics in addition to Table 65. I/O static characteristics. The external clock can be
low-swing (analog) or digital. In case of a low-swing analog input clock, the clock squarer
must be activated (refer to RM0481).
Table 40. High-speed external user clock characteristics(1)

User external clock External digital/analog

fHSE_ext 4 25 50 MHz
source frequency clock
Digital OSC_IN input
VHSEH 0.7 VDD - VDD
high-level voltage
External digital clock V
VHSEL VSS - 0.3 VDD
low-level voltage
tw(HSEH)/tw(HSEL) (2) External digital clock 7 - - ns
high or low time
152/275 DS14258 Rev 1

Table 40. High-speed external user clock characteristics(1) (continued)

Analog low-swing
Visw(HSEH)
OSC_IN peak-to- 0.2 - 2/3 VDD V
(VHSEH -VHSEH)(3) External analog low
peak amplitude
swing clock
Analog low-swing
DuCyHSE 45 50 55 %
OSC_IN duty cycle
Analog low-swing
External analog low
tr(HSE)/tf(HSE) OSC_IN rise and fall 0.05 / fHSE_ext - 0.3 / fHSE_ext ns
swing clock, 10% to 90%
times
2. The rise and fall times for a digital input signal are not specified. However the VHSEH and VHSEL conditions must be
fulfilled.
3. The DC component of the signal must ensure that the signal peaks are located between VDD and VSS.
Figure 27. High-speed external clock source AC timing diagram
VHSEH
90 %
10 %
VHSEL
tr(HSE) tf(HSE) tW(HSE) tW(HSE) t
THSE
External fHSE_ext
IL
clock source OSC_IN
STM32
ai17528b
Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the Table 41: Low-speed external user clock
characteristics in addition to Table 57: I/O static characteristics. The external clock can be
low-swing (analog) or digital. In case of a low-swing analog input clock, the clock squarer
must be activated (refer to RM0481).
DS14258 Rev 1 153/275

244
Table 41. Low-speed external user clock characteristics(1)

User external clock source

fLSE_ext External digital/analog clock - 32.768 1000 kHz
frequency
Digital OSC32_IN input
VLSEH 0.7 VDD - VDD
high-level voltage
External digital clock V
Digital OSC32_IN input
VLSEL VSS - 0.3 VDD
low-level voltage
Digital OSC_IN input high
tw(LSEH)/tw(LSEL) External digital clock 250 - - ns
or low time
Analog low-swing OSC_IN
Visw_H 0.6 - 1.225
high-level voltage
Visw_L 0.35 - 0.8 V
low-level voltage External analog low swing
ViswLSE Analog low-swing OSC_IN clock
0.5 - 0.875
(VLSEH -VLSEL) peak-to-peak amplitude
DuCyLSE 45 50 55 %
duty cycle
Analog low-swing OSC_IN External analog low swing

tr(LSE)/tf(LSE) - 100 200 ns
rise and fall times clock, 10% to 90%
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 28. Low-speed external clock source AC timing diagram
VLSEH
90%
10%
VLSEL
tr(LSE) tf(LSE) tW(LSE) tW(LSE) t
TLSE
External fLSE_ext
OSC32_IN IL
clock source
STM32
ai17529b
154/275 DS14258 Rev 1

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 50 MHz crystal/ceramic
resonator oscillator.
All the information given in this paragraph are based on characterization results obtained
with typical external components specified in Table 42. In the application, the resonator and
the load capacitors have to be placed as close as possible to the oscillator pins in order to
minimize output distortion and startup stabilization time. Refer to the crystal resonator
manufacturer for more details on the resonator characteristics (frequency, package,
accuracy).
Table 42. 4-50 MHz HSE oscillator characteristics(1)

Operating
Symbol Parameter Min Typ Max Unit
conditions(2)
F Oscillator frequency - 4 - 50 MHz

RF Feedback resistor - - 200 - kΩ
(3)
During startup - - 10
VDD = 3 V,
Rm = 20 Ω, - 0.44 -
CL = 10 pF at 4 MHz
VDD = 3 V,
Rm = 20 Ω, - 0.44 -
CL = 10 pF@8 MHz
IDD(HSE) HSE current consumption VDD = 3 V, mA

Rm = 20 Ω, - 0.55 -
CL = 10 pF@16 MHz
VDD = 3 V,
Rm = 20 Ω, - 0.67 -
CL = 10 pF@32 MHz
VDD = 3 V,
Rm = 20 Ω, - 1.17 -
CL = 10 pF@48 MHz
Gmcritmax Maximum critical crystal gm Startup - - 1.5 mA/V
tSU(HSE)(4) Startup time VDD is stabilized - 2 - ms
1. Evaluated by design - Not tested in production.
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 29). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
DS14258 Rev 1 155/275

244
Figure 29. Typical application with an 8 MHz crystal
Resonator with
integrated capacitors
CL1
OSC_IN fHSE
Bias
8 MHz RF controlled
resonator
gain
REXT(1) OSC_OU T STM32

CL2
ai17530b
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
obtained with typical external components specified in Table 43. In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
156/275 DS14258 Rev 1

Table 43. Low-speed external user clock characteristics(1)

Symbol Parameter Conditions(2) Min Typ Max Unit
F Oscillator frequency - - 32.768 - kHz

LSEDRV[1:0] = 00
- 246 -
Low drive capability
LSEDRV[1:0] = 01
- 333 -
Medium low drive capability
IDD LSE current consumption nA
LSEDRV[1:0] = 10
- 462 -
Medium high drive capability
LSEDRV[1:0] = 11
- 747 -
High drive capability
LSEDRV[1:0] = 00
- - 0.5
Low drive capability
LSEDRV[1:0] = 01
- - 0.75
Maximum critical crystal Medium low drive capability
Gmcritmax µA/V
gm LSEDRV[1:0] = 10
- - 1.7
Medium high drive capability
LSEDRV[1:0] = 11
- - 2.7
High drive capability
tSU(LSE)(3) Startup time VDD is stabilized - 2 - s
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator
design guide for ST microcontrollers”.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly
with the crystal manufacturer
Figure 30. Typical application with a 32.768 kHz crystal

Resonator with
integrated capacitors CL1
OSC32_IN fHSE
Bias
32.768 kHz
RF controlled
resonator
gain
OSC32_OUT
STM32
CL2
ai17531c
Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
DS14258 Rev 1 157/275

244
5.3.9 Internal clock source characteristics

The parameters given in Table 44: HSI48 oscillator characteristics to Table 47: LSI oscillator
characteristics are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in Table 20: General operating conditions.
48 MHz high-speed internal RC oscillator (HSI48)
Table 44. HSI48 oscillator characteristics

fHSI48 (1) (1)

HSI48 frequency VDD=3.3 V, TJ=30 °C 47.5 48 48.5 MHz
TRIM(3) User trimming step - - 0.175 0.250
USER TRIM %
User trimming coverage ± 32 steps ±4.70 ±5.6 -
COVERAGE(2)
DuCy(HSI48)(3) Duty cycle - 45 - 55 %
Accuracy of the HSI48
ACCHSI48_REL(3) oscillator over temperature TJ= -40 to 130 °C -4.5 - 4 %
(reference is 30 °C)
HSI48 oscillator frequency VDD= 3.0 to 3.6 V - 0.025 0.05 %
∆VDD(HSI48) drift with VDD (reference is
3.3 V) VDD= 1.71 to 3.6 V - 0.05 0.1 %
tsu(HSI48)(3) HSI48 oscillator start-up time - - 2.1 4.0 μs
HSI48 oscillator power
IDD(HSI48)(3) - - 350 400 μA
consumption
Next transition jitter
NT jitter(3) accumulated jitter on 28 - - ±0.15 - ns
cycles
Paired transition jitter
PT jitter(3) accumulated jitter on 56 - - ±0.25 - ns
cycles(4)
1. Calibrated during manufacturing tests.
2. Evaluated by characterization not tested in production.
3. Specified by design - not tested in production.
4. Jitter measurements are performed without clock sources activated in parallel.
158/275 DS14258 Rev 1

64 MHz high-speed internal RC oscillator (HSI)
Table 45. HSI oscillator characteristics(1)

fHSI HSI frequency VDD=3.3 V, TJ=30 °C 63.7(2) 64(2) 64.3(2) MHz

Trimming is not a
- 0.24 0.32
multiple of 32(3)
Trimming is 128, 256
-5.2 -1.8 -
and 384(3)
TRIM User trimming step Trimming is 64, 192, %

-1.4 -0.8 -
320 and 488(3)
Other trimming are a
multiple of 32 (not
-0.6 -0.25 -
including multiple of 64
and 128)(3)
DuCy(HSI) Duty Cycle - 45 - 55 %
HSI oscillator frequency drift
∆VDD(HSI) VDD= 1.71 to 3.6 V -0.12 - 0.03 %
with VDD (reference is 3.3 V)
HSI oscillator frequency drift TJ= 20 to 105 °C -1(4) - 1(4) %
∆TEMP(HSI) with VDD (reference is 64
MHz) TJ= -40 to 130 °C -2(4) - 1(4) %
tsu(HSI) HSI oscillator start-up time - - 1.4 2 μs
at 1% of target
- 4 8
HSI oscillator stabilization frequency
tstab(HSI) μs
time at 1% of target
- - 4
frequency
HSI oscillator power
IDD(HSI) - - 300 450 μA
consumption
1. Specified by design - Not tested in production, unless otherwise specified.
3. Trimming value of HSICAL[8:0.]
4. Guaranteed by characterization - not tested n production.
DS14258 Rev 1 159/275

244
4 MHz low-power internal RC oscillator (CSI)
Table 46. CSI oscillator characteristics(1)

fCSI CSI frequency VDD=3.3 V, TJ=30 °C 3.96(2) 4 4.04(2) MHz

Trimming is not a
- 0.40 0.75
multiple of 16
Trimming is not a
-4.75 -2.75 0.75
multiple of 32
TRIM User trimming step %
Other trimming are a
multiple of 32 (not
-0.43 0.00 0.75
including multiple of 64
and 128)
DuCy(CSI) Duty Cycle - 45 - 55 %
CSI oscillator frequency drift TJ= 0 to 85 °C -3.7(3) - 4.5(3) %

∆TEMP(CSI)
over temperature TJ= -40 to TJ = 130 °C -11(3) - 7.5(3) %
CSI oscillator frequency drift
∆VDD(CSI) VDD= 1.71 to 3.6 V -0.06 - 0.06 %
over VDD
tsu(CSI) HSI oscillator start-up time - - 1 2 μs
CSI oscillator stabilization
tstab(CSI) - - - 4 Cycle
time (to reach ± 3% of fCSI)
CSI oscillator power
IDD(CSI) - - 23 30 μA
consumption
1. Specified by design - not tested in production, unless otherwise specified.
3. Evaluated by characterization - not tested in production.
Low-speed internal (LSI) RC oscillator
Table 47. LSI oscillator characteristics

VDD=3.3 V, TJ= 25 °C 31.4(1) 32 32.6(1)

fLSI LSI frequency TJ= -40 to 110 °C, VDD=1.71 to 3.6 V 29.76(2) - 33.6(2) kHz
TJ= -40 to 130 °C, VDD=1.71 to 3.6 V 29.4(2) - 33.6(2)
tsu(LSI)(3) LSI oscillator start-up time - - 80 130
LSI oscillator stabilization μs
tstab(LSI)(3) - - 120 170
time (5% of final value)
LSI oscillator power
IDD(LSI)(3) - - 130 280 μA
consumption
160/275 DS14258 Rev 1

5.3.10 PLL characteristics

The parameters given in Table 48 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 20: General operating conditions.
Table 48. PLL characteristics (wide VCO frequency range)(1)

PLL input clock - 2 - 16 MHz

fPLL_IN
PLL input clock duty cycle - 10 - 90 %
VOS0 1 - 250(2)
PLL multiplier output clock VOS1 1 - 200(2)

fPLL_P_OUT
P, Q, R VOS2 1 - 150(2) MHz
VOS3 1 - 100(2)
fVCO_OUT PLL VCO output - 128 - 560(2)
Normal mode - 45 100(3) μs
tLOCK PLL lock time
Sigma-delta mode (fPLL_IN ≥ 8 MHz) - 60 120(3)
fVCO_OUT = 128 MHz - 60 -
Cycle-to-cycle jitter ±ps
Normal mode (f PLL_IN = 2 MHz),
- ±0.2 -
Jitter fVCO_OUT = 560 MHz
Normal mode (f PLL_IN = 16 MHz),
- ±0.8 -
fVCO_OUT = 560 MHz
Long term jitter %
Sigma-delta mode (f PLL_IN = 2 MHz),
- ±0.2 -
fVCO_OUT = 560 MHz
Sigma-delta mode (f PLL_IN = 16 MHz),
- ±0.8 -
fVCO_OUT = 560 MHz
VDD - 330 420
fVCO_OUT = 560 MHz
PLL power consumption on VCORE - 630 -
IDD(PLL) μA
VDD VDD - 155 230
fVCO_OUT = 128 MHz
VCORE - 170 -
2. This value must be limited to the maximum frequency due to the product limitation.
DS14258 Rev 1 161/275

244
Table 49. PLL characteristics (medium VCO frequency range)

Symbol Parameter Conditions Min(1) Typ(1) Max(1) Unit
PLL input clock - 1 - 2 MHz

fPLL_IN
PLL input clock duty cycle - 10 - 90 %
VOS0 1.17 - 210
PLL multiplier output clock VOS1 1.17 - 210

fPLL_OUT
P, Q, R VOS2 1.17 - 160(2) MHz
(2)
VOS3 1.17 - 88
fVCO_OUT PLL VCO output - 150 - 420
Normal mode - 45 80(3)
tLOCK PLL lock time μs
Sigma-delta mode forbitten
fVCO_OUT = 150 MHz - - 60 -
fVCO_OUT = 200 MHz - - 40 -
Cycle-to-cycle jitter
fVCO_OUT = 400 MHz - - 18 -
±ps
Jitter fVCO_OUT = 420 MHz - - 15 -
fVCO_OUT = 150 MHz fPLL_OUT = - 75 -
Period jitter
fVCO_OUT = 400 MHz 50 MHz - 25 -
Long term jitter Normal mode fVCO_OUT = 400 MHz - ±0.2 - %
VDD - 275 360
fVCO_OUT = 420 MHz
PLL power consumption on VCORE - 450 -
IDD(PLL) μA
VDD VDD - 160 240
fVCO_OUT = 150 MHz
VCORE - 165 -
2. This value must be limited to the maximum frequency due to the product limitation.
5.3.11 Memory characteristics

Flash memory
The characteristics are given at TJ = -40 to 130 °C unless otherwise specified.
The devices are shipped to customers with the flash memory erased.
Table 50. Flash memory characteristics

Symbol Parameter Conditions Min Typ Max(1) Unit
Word program(2) - 2.5 3.6

IDD Supply current Sector erase - 1.8 4 mA
Mass erase - 2.0 4
1. Specified by design - Not tested in production
162/275 DS14258 Rev 1

2. Data is evaluated with a write of 50% of the programmed bits equals to '0' .
Table 51. Flash memory programming(1)

Symbol Parameter Conditions Min(2) Typ Max(2) Unit
128 bits (user area) - 31 -

tprog Word program time µs
16 bits (OTP area) - 31 -
tERASE Sector erase time (8 Kbytes) - - 2 10.5 ms
tME Mass erase time - 2 2.68 s
Vprog Programming voltage 1.71 - 3.6 V
1. Data are valid for program memory and high-cycling data memory.
Table 52. Flash memory endurance and data retention

Symbol Parameter Conditions Min(1) Unit
Endurance
NPEND TJ = -40 to +130 °C 10 kcycles
program memory
Endurance
NDEND TJ = -40 to +130 °C 100 kcycles
data memory
Program memory,
1 kcycle at TA = 125 °C 10
Data retention
tPRET Years
- 1 kcycles at TA = 85 °C 30
Data retention for
100 kcycle at TA = 125 °C 1
data memory
tDRET Years
1. Evaluated by characterization - Not tested in production, unless otherwise specified.
DS14258 Rev 1 163/275

244
5.3.12 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 53. They are based on the EMS levels and classes
defined in application note AN1709 “EMC design guide for STM8, STM32 and Legacy
MCUs”.
Table 53. EMS characteristics

Level/
Class
Voltage limits to be applied on any I/O pin to

VFESD 3B
induce a functional disturbance VDD = 3.3 V, TA = 25 °C,
Fast transient voltage burst limits to be LQFP144, frcc_cpu_ck = 250 MHz,
VFTB applied through 100 pF on V and V pins conforms to IEC 61000-4-2
DD SS 5A
to induce a functional disturbance
As a consequence, it is recommended to add a serial resistor (1 kΏ) located as close as

possible to the MCU to the pins exposed to noise (connected to tracks longer than 50 mm
on PCB).
Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical data corruption (control registers...)
164/275 DS14258 Rev 1

Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015 “Software
techniques for improving microcontrollers EMC performance”).
Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application,
executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2
standard which specifies the test board and the pin loading.
Table 54. EMI characteristics

Max vs.
Monitored [fHSE/fCPU]
Symbol Parameter Conditions Unit
frequency band
8/250 MHz
0.1 to 30 MHz 8
30 to 130 MHz 0
Peak VDD = 3.6 V, TA = 25 °C, LQFP144 package, dBµV
SEMI 130 MHz to 1 GHz 24
level(1) conforming to IEC61967-2
1 GHz to 2 GHz 19
EMI level 4 -
1. Refer to the EMI radiated test chapter of application note AN1709 “EMC design guide for STM8, STM32 and Legacy
MCUs” available from the ST website www.st.com.
DS14258 Rev 1 165/275

244
5.3.13 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse) are applied to the pins of each
sample according to each pin combination. This test conforms to the ANSI/ESDA/JEDEC
JS-001 and ANSI/ESDA/JEDEC JS-002 standards.
Table 55. ESD absolute maximum ratings

Maximum
Symbol Ratings Conditions Packages Class Unit
value(1)
Packages with
Electrostatic discharge 1C 1000(2)
TA = 25 °C conforming to SMPS
VESD(HBM) voltage (human body
ANSI/ESDA/JEDEC JS-001 Packages
model) 2 2000
without SMPS
All LQFP V
Electrostatic discharge packages and C1 250
TA = +25 °C conforming to WLCSP
VESD(CDM) voltage (charge device
ANSI/ESDA/JEDEC JS-002
model) All BGA
C2a 500
packages
2. The electrostatic discharge is 2000 V for all pins, except VFBSMPS, for which the test fails at 2000 V and passes at 1600 V.
Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
• A supply overvoltage is applied to each power supply pin
• A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with JESD78 IC latchup standard.
Table 56. Electrical sensitivities

Symbol Parameter Conditions Class
LU Static latchup class TJ = 130 °C, conforming to JESD78, II level A
5.3.14 I/O port characteristics

General input/output characteristics
Unless otherwise specified, the parameters given in Table 57: I/O static characteristics are
derived from tests performed under the conditions summarized in Table 20: General
operating conditions. All I/Os are CMOS and TTL compliant (except for BOOT0).
Note: For information on GPIO configuration, refer to application note AN4899 “STM32 GPIO
configuration for hardware settings and low-power consumption”, available from the ST
website www.st.com.
166/275 DS14258 Rev 1

Table 57. I/O static characteristics(1)

Symbol Parameter Condition Min Typ Max Unit
I/O input low level voltage

- 0.3VDDIOx(2)
except BOOT0
I/O input low level voltage
VIL 1.08 V<VDD<3.6 V - 0.14VDDIOx-0.1(3) V
except BOOT0
BOOT0 I/O input low level
- 0.19VDDIOx + 0.1(3)
voltage
I/O input high level
0.7VDDIOx(2)
voltage except BOOT0
I/O input high level
VIH 1.08 V<VDD<3.6 V 0.52VDDIOx+0.18(3) V
voltage except BOOT0
BOOT0 I/O input high
0.17VDDIOx+0.6(3)
level voltage
TT_xx, FT_xxx and NRST
1.08 V< VDD <3.6 V - 250
I/O input hysteresis
VHYS(3) mV
BOOT0 I/O input
1.71 V< VDD <3.6 V - 200
hysteresis
0< VIN ≤
- - ±200
Max(VDDXXX)(7)
Max(VDDXXX) <
FT_xx Input leakage
VIN ≤ Max(VDDXXX)+ - - 2500
current(3)
1 V) (5)(7)
Ileak(4) nA
Max(VDDXXX) < VIN ≤
- - 750
5.5 V (5)(7)
TT_xx Input leakage 0< VIN ≤ Max(VDDXXX)
(7) - - ±200
current
BOOT0 0< VIN ≤ VDDOX - - 15
Weak pull-up equivalent
RPU VIN=VSS 30 40 50
resistor(6)
kΩ
Weak pull-down
RPD VIN=VDD(7) 30 40 50
equivalent resistor(6)
CIO I/O pin capacitance - - 5 - pF
1. VDDIOx represents VDD or VDDIO2.
2. Compliant with CMOS requirements.
4. This parameter represents the pad leakage of the I/O itself. The total product pad leakage is provided by the following
formula: ITotal_Ieak_max = 10 μA + [number of I/Os where VIN is applied on the pad] ₓ Ilkg(Max).
5. VIN must be less than Max(VDDXXX) + 3.6 V.
6. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
7. Max(VDDXXX) is the maximum value of all the I/O supplies.
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All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements for FT I/Os is shown in Figure 31.
Figure 31. VIL/VIH for all I/Os except BOOT0
Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed VOL/VOH).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Table 5.2: Absolute maximum ratings. In
particular:
• The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 18: Current characteristics).
• The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
ΣIVSS (see Table 18: Current characteristics).
168/275 DS14258 Rev 1

Output voltage levels

Unless otherwise specified, the parameters given in Table 58: Output voltage characteristics
for all I/Os except PC13, PC14, PC15, and PI8 and Table 59: Output voltage characteristics
for PC13 and PI8 are derived from tests performed under ambient temperature and VDD
supply voltage conditions summarized in Table 20: General operating conditions. All I/Os
are CMOS and TTL compliant.
Table 58. Output voltage characteristics for all I/Os except PC13, PC14, PC15, and PI8
Symbol Parameter Conditions(1) Min Max Unit
CMOS port(2)
VOL Output low level voltage IIO = 8 mA - 0.4
2.7 V≤ VDD ≤3.6 V
CMOS port(2)
VOH Output high level voltage IIO = -8 mA VDD−0.4 -
2.7 V≤ VDD ≤3.6 V
TTL port(2)
VOL(3) Output low level voltage IIO = 8 mA - 0.4
2.7 V≤ VDD ≤ 3.6 V
TTL port(2)
VOH (3) Output high level voltage IIO = -8 mA 2.4 -
2.7 V≤ VDD ≤ 3.6 V
IIO = 20 mA
VOL(3) Output low level voltage - 1.3
2.7 V≤ VDD ≤ 3.6 V
IIO = -20 mA
VOH(3) Output high level voltage VDD - 1.3 - V
2.7 V≤ VDD ≤ 3.6 V
IIO = 4 mA
1.71 V≤ VDD ≤ 3.6 V
IIO = -4 mA
VOH (3) Output high level voltage VDD - 0.4 -
1.71 V≤VDD <3.6 V
IIO = 2 mA
VOL(3) Output low level voltage - 0.3 x VDDIO2
1.08 V≤ VDD ≤ 1.32 V
IIO = -2 mA
VOH (3) Output high level voltage 0.7 x VDDIO2 -
1.71 V≤VDD < 1.32 V
IIO = 20 mA
- 0.4
2.3 V≤ VDD ≤3.6 V
Output low level voltage for an IIO = 10 mA
VOLFM+(3) - 0.4
FTf I/O pin in (FT I/O with “f” option) 1.71 V≤ VDD ≤ 3.6 V
IIO = 4.5 mA
- 0.4
1.08 V≤ VDD ≤ 3.6 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 17:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
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Table 59. Output voltage characteristics for PC13 and PI8(1)

CMOS port(2) IIO = 3 mA

VOL Output low level voltage - 0.4
2.7 V≤ VDD ≤3.6 V
CMOS port(2) IIO = -3 mA
VOH Output high level voltage VDD - 0.4 -
2.7 V≤ VDD ≤3.6 V
TTL port(2) IIO = 3 mA
2.7 V≤ VDD ≤3.6 V
V
TTL port(2) IIO = -3 mA
VOH(3) Output high level voltage 2.4 -
2.7 V≤ VDD ≤3.6 V
IIO = 1.5 mA
1.71 V≤ VDD ≤ 3.6 V
IIO = −1.5 mA
VOH(3) Output high level voltage VDD - 0.4 -
1.71 V≤ VDD ≤ 3.6 V
Table 60. Output voltage characteristics for PC14 and PC15(1)

CMOS port(2) IIO = 0.5 mA

VOL Output low level voltage - 0.4
2.7 V≤ VDD ≤3.6 V
CMOS port(2) IIO = -0.5 mA
VOH Output high level voltage VDD - 0.4 -
2.7 V≤ VDD ≤3.6 V
TTL port(2) IIO = 0.5 mA
2.7 V ≤ VDD ≤3.6 V
V
TTL port(2) IIO = -0.5 mA
VOH(3) Output high level voltage 2.4 -
2.7 V ≤ VDD ≤3.6 V
IIO = 0.25 mA
1.71 V ≤ VDD ≤ 3.6 V
IIO = -0.25 mA
VOH(3) Output high level voltage VDD - 0.4 -
1.71 V ≤ VDD ≤ 3.6 V
170/275 DS14258 Rev 1

Output buffer timing characteristics (HSLV option disabled)

The HSLV bit of GPIOx_HSLVR register can be used to optimize the I/O speed when the
product voltage is below 2.7 V.
Table 61. Output timing characteristics (HSLV OFF)(1)

Speed Symbol Parameter conditions Min Max Unit
C = 50 pF, 2.7 V≤ VDD ≤ 3.6 V - 8

C = 50 pF, 1.71 V≤VDD ≤ 2 V - 5
C = 40 pF, 2.7 V≤VDD ≤ 3.6 V - 10
C = 40 pF, 1.71 V≤VDD≤ 2 V - 5
C = 30 pF, 2.7 V≤VDD≤ 3.6 V - 12
Fmax(2)(3) Maximum frequency MHz
C = 30 pF, 1.71 V≤VDD≤ 2 V - 5
C = 20 pF, 2.7 V≤VDD≤ 3.6 V - 14
C = 20 pF, 1.71 V≤VDD≤ 2 V - 5
C = 10 pF, 2.7 V≤VDD≤ 3.6 V - 16
C = 10 pF, 1.71 V≤VDD≤ 2 V - 5
00
C=50 pF, 2.7 V≤ VDD≤3.6 V - 18.0
C = 50 pF, 1.71 V≤VDD ≤ 2 V - 36.0
C = 40 pF, 2.7 V≤VDD ≤ 3.6 V - 17.0
C = 40 pF, 1.71 V≤VDD≤ 2 V - 34.0
Output high to low level C = 30 pF, 2.7 V≤VDD≤ 3.6 V - 15.5
tr/tf(4)(5) fall time and output low ns
to high level rise time C = 30 pF, 1.71 V≤VDD≤ 2 V - 32.0
C = 20 pF, 2.7 V≤VDD≤ 3.6 V - 14.2
C = 20 pF, 1.71 V≤VDD≤ 2 V - 30.0
C = 10 pF, 2.7 V≤VDD≤ 3.6 V - 12.2
C = 10 pF, 1.71 V≤VDD≤ 2 V - 27
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Table 61. Output timing characteristics (HSLV OFF)(1) (continued)

C =50 pF, 2.7 V≤ VDD≤3.6 40

C = 50 pF, 1.71 V≤VDD ≤ 2 V - 12
C = 40 pF, 2.7 V≤VDD ≤ 3.6 V - 45
C = 40 pF, 1.71 V≤VDD≤ 2 V - 14
C = 30 pF, 2.7 V≤VDD≤ 3.6 V - 50
C = 30 pF, 1.71 V≤VDD≤ 2 V - 16
C = 20 pF, 2.7 V≤VDD≤ 3.6 V - 55
C = 20 pF, 1.71 V≤VDD≤ 2 V - 18
C = 10 pF, 2.7 V≤VDD≤ 3.6 V - 60
C = 10 pF, 1.71 V≤VDD≤ 2 V - 20
01
C=50 pF, 2.7 V≤ VDD≤3.6 V - 6.2
C = 50 pF, 1.71 V≤VDD ≤ 2 V - 11.4
C = 40 pF, 2.7 V≤VDD ≤ 3.6 V - 5.7
C = 40 pF, 1.71 V≤VDD≤ 2 V - 10.5
C = 20 pF, 2.7 V≤VDD≤ 3.6 V - 4.5
C = 20 pF, 1.71 V≤VDD≤ 2 V 8.4
C = 10 pF, 2.7 V≤VDD≤ 3.6 V 3.7
C = 10 pF, 1.71 V≤VDD≤ 2 V 7.0
172/275 DS14258 Rev 1


C =50 pF, 2.7 V≤ VDD≤3.6 - 80

C = 50 pF, 1.71 V≤VDD ≤ 2 V - 30
C = 40 pF, 2.7 V≤VDD ≤ 3.6 V - 90
C = 40 pF, 1.71 V≤VDD≤ 2 V - 35
C = 30 pF, 2.7 V≤VDD≤ 3.6 V - 100
C = 30 pF, 1.71 V≤VDD≤ 2 V - 40
C = 20 pF, 2.7 V≤VDD≤ 3.6 V - 110
C = 20 pF, 1.71 V≤VDD≤ 2 V - 45
C = 10 pF, 2.7 V≤VDD≤ 3.6 V - 133
C = 10 pF, 1.71 V≤VDD≤ 2 V - 50
10
C=50 pF, 2.7 V≤ VDD≤3.6 V - 3.8
C = 50 pF, 1.71 V≤VDD ≤ 2 V - 7.5
C = 40 pF, 2.7 V≤VDD ≤ 3.6 V - 3.4
C = 40 pF, 1.71 V≤VDD≤ 2 V - 6.6
C = 20 pF, 2.7 V≤VDD≤ 3.6 V - 2.5
C = 20 pF, 1.71 V≤VDD≤ 2 V - 4.7
C = 10 pF, 2.7 V≤VDD≤ 3.6 V - 1.9
C = 10 pF, 1.71 V≤VDD≤ 2 V - 3.7
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C =50 pF, 2.7 V≤ VDD≤3.6 - 100

C = 50 pF, 1.71 V≤VDD ≤ 2 V - 40
C = 40 pF, 2.7 V≤VDD ≤ 3.6 V - 120
C = 40 pF, 1.71 V≤VDD≤ 2 V - 50
C = 30 pF, 2.7 V≤VDD≤ 3.6 V - 140
C = 30 pF, 1.71 V≤VDD≤ 2 V - 60
C = 20 pF, 2.7 V≤VDD≤ 3.6 V - 166
C = 20 pF, 1.71 V≤VDD≤ 2 V - 70
C = 10 pF, 2.7 V≤VDD≤ 3.6 V - 200
C = 10 pF, 1.71 V≤VDD≤ 2 V - 80
11
C=50 pF, 2.7 V≤ VDD≤3.6 V - 3.3
C = 50 pF, 1.71 V≤VDD ≤ 2 V - 6.3
C = 40 pF, 2.7 V≤VDD ≤ 3.6 V - 2.8
C = 40 pF, 1.71 V≤VDD≤ 2 V - 5.5
C = 20 pF, 2.7 V≤VDD≤ 3.6 V - 1.9
C = 20 pF, 1.71 V≤VDD≤ 2 V - 3.7
C = 10 pF, 2.7 V≤VDD≤ 3.6 V - 1.4
C = 10 pF, 1.71 V≤VDD≤ 2 V - 3
2. The maximum frequency is defined with the following conditions:
(tr+tf) ≤ 2/3 T
Skew ≤ 1/20 T
45%<Duty cycle<55%
3. When 2 V < VDD < 2.7 V maximum frequency is between values given for Vdd=1.98V and Vdd=2.7V
4. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.
5. When 2 V < VDD < 2.7 V maximum trise/tfall is between values given for Vdd=1.98V and VDD = 2.7 V
174/275 DS14258 Rev 1

Output buffer timing characteristics (HSLV option enabled)
Table 62. Output timing characteristics (HSLV ON)(1)

C =50 pF, 1.71 V≤VDD≤2 V - 8

C =40 pF, 1.71 V≤VDD≤2 V - 10
Fmax (2) Maximum frequency C =30 pF, 1.71 V≤VDD≤2 V - 12 MHz
C =20 pF, 1.71 V≤VDD≤2 V - 14
C =10 pF, 1.71 V≤VDD≤2 V - 16
00
C =50 pF, 1.71 V≤VDD≤2.7 V - 17.8
C =40 pF, 1.71 V≤VDD≤2 V - 15.8
Output high to low level
tr/tf(3) fall time and output low C =30 pF, 1.71 V≤VDD≤2 V - 14.4 ns
to high level rise time
C =20 pF, 1.71 V≤VDD≤2 V - 13.1
C =10 pF, 1.71 V≤VDD≤2 V - 11.4
C = 50 pF, 1.71 V≤VDD≤2.7 V - 40
C = 40 pF, 1.71 V≤VDD≤2 V - 45
Fmax(2) Maximum frequency C = 30 pF, 1.71 V≤VDD≤2 V - 50 MHz
C = 20 pF, 1.71 V≤VDD≤2 V - 55
C =10 pF, 1.71 V≤VDD≤2 V - 60
01
C = 50 pF, 1.71 V≤VDD≤2.7 V - 7.2
C = 40 pF, 1.71 V≤VDD≤2 V - 6.5
tr/tf(3)(4) fall time and output low C = 30 pF, 1.71 V≤VDD≤2 V - 5.6 ns
C = 20 pF, 1.71 V≤VDD≤2 V - 4.8
C =10 pF, 1.71 V≤VDD≤2 V - 3.8
C = 50 pF, 1.71 V≤VDD≤2.7 V - 60
C = 40 pF, 1.71 V≤VDD≤2 V - 70
(2)(4)
Fmax Maximum frequency C = 30 pF, 1.71 V≤VDD≤2 V - 90 MHz
C = 20 pF, 1.71 V≤VDD≤2 V - 110
C =10 pF, 1.71 V≤VDD≤2 V - 140
10
C = 50 pF, 1.71 V≤VDD≤2.7 V - 5.3
C = 40 pF, 1.71 V≤VDD≤2 V - 4.6
(3)(4)
tr/tf fall time and output low C = 30 pF, 1.71 V≤VDD≤2 V - 3.8 ns
C = 20 pF, 1.71 V≤VDD≤2 V - 3.0
C =10 pF, 1.71 V≤VDD≤2 V - 2.2
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Table 62. Output timing characteristics (HSLV ON)(1) (continued)

C=50 pF, 1.71 V≤VDD≤2 V - 67

C = 40 pF, 1.71 V≤VDD≤2 V - 100
(2)(4)
Fmax Maximum frequency C = 30 pF, 1.71 V≤VDD≤2 V - 120 MHz
C = 20 pF, 1.71 V≤VDD≤2 V - 155
C=10 pF, 1.71 V≤VDD≤2 V - 200
11
C = 50 pF, 1.71 V≤VDD≤2.7 V - 5.0
C = 40 pF, 1.71 V≤VDD≤2 V - 4.1
tr/tf(3)(4) fall time and output low C = 30 pF, 1.71 V≤VDD≤2 V - 3.3 ns
C = 20 pF, 1.71 V≤VDD≤2 V - 2.5
C=10 pF, 1.71 V≤VDD≤2 V - 1.8
(tr+tf) ≤ 2/3 T
Skew ≤ 1/20 T
45%<Duty cycle<55%
4. Compensation system enabled.
Table 63. Output timing characteristics VDDIO2 1.2 V range (HSLV OFF)(1)
C =50 pF, 1.08 V≤VDDIO2≤1.32 V - 1

C =40 pF, 1.08 V≤VDDIO2≤1.32 V - 1
Fmax(2) Maximum frequency C =30 pF, 1.08 V≤VDDIO2≤1.32 V - 1 MHz
C =20 pF, 1.08 V≤VDDIO2≤1.32 V - 1
C =10 pF, 1.08 V≤VDDIO2≤1.32 V - 1
00
C =50 pF, 1.08 V≤VDDIO2≤1.32 V - 83.0
C =40 pF, 1.08 V≤VDDIO2≤1.32 V - 79.0
tr/tf(3) fall time and output low C =30 pF, 1.08 V≤VDDIO2≤1.32 V - 46.0 ns
C =20 pF, 1.08 V≤VDDIO2≤1.32 V - 72.0
C =10 pF, 1.08 V≤VDDIO2≤1.32 V - 68.0
176/275 DS14258 Rev 1

Table 63. Output timing characteristics VDDIO2 1.2 V range (HSLV OFF)(1) (continued)
C =50 pF, 1.08 V≤VDDIO2≤1.32 V - 5

C =40 pF, 1.08 V≤VDDIO2≤1.32 V - 5
(2)
Fmax Maximum frequency C =30 pF, 1.08 V≤VDDIO2≤1.32 V - 5 MHz
C =20 pF, 1.08 V≤VDDIO2≤1.32 V - 5
C =10 pF, 1.08 V≤VDDIO2≤1.32 V - 5
01
C =50 pF, 1.08 V≤VDDIO2≤1.32 V - 24.5
C =40 pF, 1.08 V≤VDDIO2≤1.32 V - 22.2
C =20 pF, 1.08 V≤VDDIO2≤1.32 V - 17.8
C =10 pF, 1.08 V≤VDDIO2≤1.32 V - 15.0
C =50 pF, 1.08 V≤VDDIO2≤1.32 V - 10
C =40 pF, 1.08 V≤VDDIO2≤1.32 V - 10
Fmax (2) Maximum frequency C =30 pF, 1.08 V≤VDDIO2≤1.32 V - 10 MHz
C =20 pF, 1.08 V≤VDDIO2≤1.32 V - 10
C =10 pF, 1.08 V≤VDDIO2≤1.32 V - 10
10
C =50 pF, 1.08 V≤VDDIO2≤1.32 V - 16.2
C =40 pF, 1.08 V≤VDDIO2≤1.32 V - 14.3
C =20 pF, 1.08 V≤VDDIO2≤1.32 V - 10.0
C =10 pF, 1.08 V≤VDDIO2≤1.32 V - 7.9
C =50 pF, 1.08 V≤VDDIO2≤1.32 V - 20
C =40 pF, 1.08 V≤VDDIO2≤1.32 V - 23
(2)(4)
C =20 pF, 1.08 V≤VDDIO2≤1.32 V - 28
C =10 pF, 1.08 V≤VDDIO2≤1.32 V - 30
11
C =50 pF, 1.08 V≤VDDIO2≤1.32 V - 14.0
C =40 pF, 1.08 V≤VDDIO2≤1.32 V - 12.0
tr/tf(3)(4) fall time and output low C =30 pF, 1.08 V≤VDDIO2≤1.32 V - 10.0 ns
C =20 pF, 1.08 V≤VDDIO2≤1.32 V - 8.0
C =10 pF, 1.08 V≤VDDIO2≤1.32 V - 6.0
(tr+tf) ≤ 2/3 T
Skew ≤ 1/20 T
45%<Duty cycle<55%
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Table 64. Output timing characteristics VDDIO2 1.2 V (HSLV ON)(1)

C =50 pF, 1.08 V≤VDDIO2≤1.32 V - 5

C =40 pF, 1.08 V≤VDDIO2≤1.32 V - 5
Fmax (2)
Maximum frequency C =30 pF, 1.08 V≤VDDIO2≤1.32 V - 5 MHz
C =20 pF, 1.08 V≤VDDIO2≤1.32 V - 5
C =10 pF, 1.08 V≤VDDIO2≤1.32 V - 5
00
C =50 pF, 1.08 V≤VDDIO2≤1.32 V - 32.5
C =40 pF, 1.08 V≤VDDIO2≤1.32 V - 30.0
C =20 pF, 1.08 V≤VDDIO2≤1.32 V - 25.0
C =10 pF, 1.08 V≤VDDIO2≤1.32 V - 22.5
C =50 pF, 1.08 V≤VDDIO2≤1.32 V - 15.0
C =40 pF, 1.08 V≤VDDIO2≤1.32 V - 17.5
(2)
Fmax Maximum frequency C =30 pF, 1.08 V≤VDDIO2≤1.32 V - 20.0 MHz
C =20 pF, 1.08 V≤VDDIO2≤1.32 V - 22.5
C =10 pF, 1.08 V≤VDDIO2≤1.32 V - 25.0
01
C =50 pF, 1.08 V≤VDDIO2≤1.32 V - 14.6
C =40 pF, 1.08 V≤VDDIO2≤1.32 V - 12.9
C =20 pF, 1.08 V≤VDDIO2≤1.32 V - 9.3
C =10 pF, 1.08 V≤VDDIO2≤1.32 V - 7.3
C =50 pF, 1.08 V≤VDDIO2≤1.32 V - 25
C =40 pF, 1.08 V≤VDDIO2≤1.32 V - 30
Fmax (2)(4)
Maximum frequency C =30 pF, 1.08 V≤VDDIO2≤1.32 V - 33 MHz
C =20 pF, 1.08 V≤VDDIO2≤1.32 V - 44
C =10 pF, 1.08 V≤VDDIO2≤1.32 V - 55
10
C =50 pF, 1.08 V≤VDDIO2≤1.32 V - 11.6
C =40 pF, 1.08 V≤VDDIO2≤1.32 V - 9.7
C =20 pF, 1.08 V≤VDDIO2≤1.32 V - 6.1
C =10 pF, 1.08 V≤VDDIO2≤1.32 V - 4.3
178/275 DS14258 Rev 1

Table 64. Output timing characteristics VDDIO2 1.2 V (HSLV ON)(1) (continued)
C =50 pF, 1.08 V≤VDDIO2≤1.32 V - 30

C =40 pF, 1.08 V≤VDDIO2≤1.32 V - 35
(2)(4)
C =20 pF, 1.08 V≤VDDIO2≤1.32 V - 55
C =10 pF, 1.08 V≤VDDIO2≤1.32 V - 77
11
C =50 pF, 1.08 V≤VDDIO2≤1.32 V - 11.1
C =40 pF, 1.08 V≤VDDIO2≤1.32 V - 9.2
C =20 pF, 1.08 V≤VDDIO2≤1.32 V - 5.4
C =10 pF, 1.08 V≤VDDIO2≤1.32 V - 3.6
(tr+tf) ≤ 2/3 T
Skew ≤ 1/20 T
45%<Duty cycle<55%
5.3.15 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 57: I/O static characteristics).
Unless otherwise specified, the parameters given in Table 65 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 20: General operating conditions.
Table 65. NRST pin characteristics

Weak pull-up equivalent

RPU(2) VIN = VSS 30 40 50 ㏀
resistor(1)
VF(NRST)(2) NRST Input filtered pulse 1.71 V < VDD < 3.6 V - - 50
ns
VNF(NRST)(2) NRST Input not filtered pulse 1.71 V < VDD < 3.6 V 350 - -
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum (~10 % order).
DS14258 Rev 1 179/275

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Figure 32. Recommended NRST pin protection
VDD
External
reset circuit (1)
RPU
NRST (2) Internal Reset
Filter
0.1 μF
STM32
ai14132d
1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 57. Otherwise the reset is not taken into account by the device.
5.3.16 Extended interrupt and event controller input (EXTI) characteristics

The pulse on the interrupt input must have a minimal length in order to guarantee that it is
detected by the event controller.
Table 66. EXTI input characteristics(1)

PLEC Pulse length to event controller - 20 - - ns
5.3.17 FMC characteristics

Unless otherwise specified, the parameters given in Table 67 to Table 80 for the FMC
interface are derived from tests performed under the ambient temperature, fHCLK frequency
and VDD supply voltage conditions summarized in Table 20: General operating conditions,
with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Measurement points are done at CMOS levels: 0.5 VDD
• IO Compensation cell activated.
• HSLV activated when VDD ≤ 2.7 V
• VOS level set to VOS0.
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics.
180/275 DS14258 Rev 1

Asynchronous waveforms and timings

Figure 33 through Figure 35 represent asynchronous waveforms and Table 67 through
Table 74 provide the corresponding timings. The results shown in these tables are obtained
with the following FMC configuration:
• AddressSetupTime = 0x1
• AddressHoldTime = 0x1
• DataSetupTime = 0x1 (except for asynchronous NWAIT mode , DataSetupTime = 0x5)
• BusTurnAroundDuration = 0x0
• Capacitive load CL = 30 pF
In all timing tables, the Tfmc_ker_ck is the fHCLK clock period.
Figure 33. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
tw(NE)
FMC_NE
tv(NOE_NE) t w(NOE) t h(NE_NOE)
FMC_NOE
FMC_NWE
tv(A_NE) t h(A_NOE)
FMC_A[25:0] Address
tv(BL_NE) t h(BL_NOE)
FMC_NBL[1:0]
t h(Data_NE)
t su(Data_NOE) th(Data_NOE)
t su(Data_NE)
FMC_D[15:0] Data
t v(NADV_NE)
tw(NADV)
FMC_NADV (1)
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32753V1
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
DS14258 Rev 1 181/275

244
Table 67. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)

tw(NE) FMC_NE low time 3Tfmc_ker_ck - 1 3Tfmc_ker_ck+1

tv(NOE_NE) FMC_NEx low to FMC_NOE low 0 0.5
tw(NOE) FMC_NOE low time 2Tfmc_ker_ck - 1 2Tfmc_ker_ck+1
FMC_NOE high to FMC_NE high
th(NE_NOE) Tfmc_ker_ck - 0.5 -
hold time
tv(A_NE) FMC_NEx low to FMC_A valid - 1
Address hold time after
th(A_NOE) 2Tfmc_ker_ck-1.5 -
FMC_NOE high
Data to FMC_NEx high setup ns
tsu(Data_NE) Tfmc_ker_ck+10 -
time
Data to FMC_NOEx high setup
tsu(Data_NOE) 9 -
time
Data hold time after FMC_NOE
th(Data_NOE) 0 -
high
Data hold time after FMC_NEx
th(Data_NE) 0 -
high
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0.5
tw(NADV) FMC_NADV low time - Tfmc_ker_ck+1
Table 68. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT

timings(1)(2)
tw(NE) FMC_NE low time 8Tfmc_ker_ck–1 8Tfmc_ker_ck+1

tw(NOE) FMC_NOE low time 7Tfmc_ker_ck–1 7Tfmc_ker_ck +1
tw(NWAIT) FMC_NWAIT low time Tfmc_ker_ck– 0.5 -
ns
FMC_NWAIT valid before FMC_NEx
tsu(NWAIT_NE) 5Tfmc_ker_ck +10 -
high
FMC_NEx hold time after
th(NE_NWAIT) 4Tfmc_ker_ck+10 -
FMC_NWAIT invalid
2. NWAIT pulse width is equal to 1 fmc_ker_ck cycle.
182/275 DS14258 Rev 1

Figure 34. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms

tw(NE)
FMC_NEx
FMC_NOE
tv(NWE_NE) tw(NWE) t h(NE_NWE)
FMC_NWE
tv(A_NE) th(A_NWE)
FMC_A[25:0] Address
tv(BL_NE) th(BL_NWE)
FMC_NBL[1:0] NBL
tv(Data_NE) th(Data_NWE)
FMC_D[15:0] Data
t v(NADV_NE)
tw(NADV)
FMC_NADV (1)
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32754V1
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
DS14258 Rev 1 183/275

244
Table 69. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)

tw(NE) FMC_NE low time 3Tfmc_ker_ck - 1 3Tfmc_ker_ck + 1

tv(NWE_NE) FMC_NEx low to FMC_NWE low Tfmc_ker_ck - 1 Tfmc_ker_ck+0.5
tw(NWE) FMC_NWE low time Tfmc_ker_ck –1 Tfmc_ker_ck+1
FMC_NWE high to FMC_NE high
th(NE_NWE) Tfmc_ker_ck - 1 -
hold time
tv(A_NE) FMC_NEx low to FMC_A valid - 0.5
Address hold time after FMC_NWE
th(A_NWE) Tfmc_ker_ck + 1 -
high ns
tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5
FMC_BL hold time after FMC_NWE
th(BL_NWE) Tfmc_ker_ck -1 -
high
tv(Data_NE) Data to FMC_NEx low to Data valid - Tfmc_ker_ck + 1
th(Data_NWE) Data hold time after FMC_NWE high Tfmc_ker_ck -
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0.5
tw(NADV) FMC_NADV low time - Tfmc_ker_ck + 1
Table 70. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT

timings(1)(2)
tw(NE) FMC_NE low time 8Tfmc_ker_ck –1 8Tfmc_ker_ck+1

tw(NWE) FMC_NWE low time 6Tfmc_ker_ck –1 6Tfmc_ker_ck+1
FMC_NWAIT valid before FMC_NEx ns
tsu(NWAIT_NE) 5Tfmc_ker_ck+10 -
high
th(NE_NWAIT) 4Tfmc_ker_ck+10 -
FMC_NWAIT invalid
184/275 DS14258 Rev 1

Figure 35. Asynchronous multiplexed PSRAM/NOR read waveforms

tw(NE)
FMC_ NE
tv(NOE_NE) t h(NE_NOE)
FMC_NOE
t w(NOE)
FMC_NWE
tv(A_NE) th(A_NOE)
FMC_ A[25:16] Address

tv(BL_NE) th(BL_NOE)
FMC_ NBL[1:0] NBL

th(Data_NE)
tsu(Data_NE)
t v(A_NE) tsu(Data_NOE) th(Data_NOE)
FMC_ AD[15:0] Address Data
t v(NADV_NE) th(AD_NADV)
tw(NADV)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32755V1
DS14258 Rev 1 185/275

244
Table 71. Asynchronous multiplexed PSRAM/NOR read timings(1)


tv(NOE_NE) FMC_NEx low to FMC_NOE low 2Tfmc_ker_ck - 1 2Tfmc_ker_ck +0.5
ttw(NOE) FMC_NOE low time Tfmc_ker_ck - 1 Tfmc_ker_ck+ 1
FMC_NOE high to FMC_NE high hold
th(NE_NOE) Tfmc_ker_ck - 0.5 -
time
tv(A_NE) FMC_NEx low to FMC_A valid - 1
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 1
tw(NADV) FMC_NADV low time Tfmc_ker_ck - 0.5 Tfmc_ker_ck + 1
ns
FMC_AD(address) valid hold time
th(AD_NADV) Tfmc_ker_ck + 0.5 -
after FMC_NADV high)
Address hold time after FMC_NOE
th(A_NOE) 2Tfmc_ker_ck - 0.5 -
high
tsu(Data_NE) Data to FMC_NEx high setup time Tfmc_ker_ck +10 -
tsu(Data_NOE
Data to FMC_NOE high setup time 9 -
)
th(Data_NE) Data hold time after FMC_NEx high 0 -

th(Data_NOE) Data hold time after FMC_NOE high 0 -
Table 72. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1) (2)

tw(NE) FMC_NE low time 9Tfmc_ker_ck –1 9Tfmc_ker_ck +1

tw(NOE) FMC_NWE low time 7Tfmc_ker_ck –1 7Tfmc_ker_ck +1
FMC_NWAIT valid before ns
tsu(NWAIT_NE) 4Tfmc_ker_ck +10 -
FMC_NEx high
th(NE_NWAIT) 3Tfmc_ker_ck +10 -
FMC_NWAIT invalid
186/275 DS14258 Rev 1

Table 73. Asynchronous multiplexed PSRAM/NOR write timings(1)

tw(NE) FMC_NE low time 4Tfmc_ker_ck -1 4Tfmc_ker_ck +1

tv(NWE_NE) FMC_NEx low to FMC_NWE low Tfmc_ker_ck - 1 Tfmc_ker_ck +0.5
tw(NWE) FMC_NWE low time 2Tfmc_ker_ck - 1 2Tfmc_ker_ck + 1
FMC_NWE high to FMC_NE high hold
th(NE_NWE) Tfmc_ker_ck - 0.5 -
time
tv(A_NE) FMC_NEx low to FMC_A valid - 0.5
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 1
tw(NADV) FMC_NADV low time Tfmc_ker_ck - 1 Tfmc_ker_ck + 1
ns
FMC_AD(adress) valid hold time after
th(AD_NADV) Tfmc_ker_ck - 1 -
FMC_NADV high)
Address hold time after FMC_NWE
th(A_NWE) Tfmc_ker_ck - 1 -
high
FMC_BL hold time after FMC_NWE
th(BL_NWE) Tfmc_ker_ck - 1 -
high
tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5
tv(Data_NADV) FMC_NADV high to Data valid - Tfmc_ker_ck + 0.5
th(Data_NWE) Data hold time after FMC_NWE high Tfmc_ker_ck - 0.5 -
Table 74. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)(2)


tw(NWE) FMC_NWE low time 7Tfmc_ker_ck -1 7Tfmc_ker_ck + 1
FMC_NWAIT valid before FMC_NEx ns
tsu(NWAIT_NE) 5Tfmc_ker_ck + 10 -
high
th(NE_NWAIT) 4Tfmc_ker_ck + 10 -
FMC_NWAIT invalid
DS14258 Rev 1 187/275

244
Synchronous waveforms and timings

Figure 36 through Figure 39 represent synchronous waveforms and Table 75 through
Table 78 provide the corresponding timings. The results shown in these tables are obtained
with the following FMC configuration:
• BurstAccessMode = FMC_BurstAccessMode_Enable
• MemoryType = FMC_MemoryType_CRAM
• WriteBurst = FMC_WriteBurst_Enable
• CLKDivision = 1
• DataLatency = 1 for NOR flash, DataLatency = 0 for PSRAM.
• With capacity load CL = 30 pF
In all the timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period, with the following
FMC_CLK maximum values:
• For 2.7 V<VDD<3.6 V: maximum FMC_CLK = 100 MHz at CL = 20 pF
• For 1.71 V<VDD<1.8 V: maximum FMC_CLK = 95 MHz at CL = 20 pF
• For 1.71 V<VDD<1.8 V: maximumFMC_CLK = 100 MHz at CL = 15 pF
Figure 36. Synchronous multiplexed NOR/PSRAM read timings
tw(CLK) tw(CLK) BUSTURN = 0
FMC_CLK
Data latency = 0
td(CLKL-NExL) td(CLKH-NExH)
FMC_NEx
t d(CLKL-NADVL) td(CLKL-NADVH)
FMC_NADV
td(CLKL-AV) td(CLKH-AIV)
FMC_A[25:16]
td(CLKL-NOEL) td(CLKH-NOEH)
FMC_NOE
td(CLKL-ADIV) th(CLKH-ADV)
t d(CLKL-ADV) tsu(ADV-CLKH) tsu(ADV-CLKH) th(CLKH-ADV)
FMC_AD[15:0] AD[15:0] D1 D2
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV)
MS32757V1
188/275 DS14258 Rev 1

Table 75. Synchronous multiplexed NOR/PSRAM read timings(1)

tw(CLK) FMC_CLK period 2Tfmc_ker_ck - 0.5 -

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 1
td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x= 0…2) Tfmc_ker_ck - 1 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1.5
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0.5 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 1
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) Tfmc_ker_ck- 1 -
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - 1
ns
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high Tfmc_ker_ck + 0.5 -
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 3.5
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0.5 -
tsu(ADV-CLKH) FMC_A/D[15:0] valid data before FMC_CLK high 3.5 -
th(CLKH-ADV) FMC_A/D[15:0] valid data after FMC_CLK high 1.5 -
tsu(NWAIT-
FMC_NWAIT valid before FMC_CLK high 2.5 -
CLKH)
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 1.5 -

DS14258 Rev 1 189/275

244
Figure 37. Synchronous multiplexed PSRAM write timings
tw(CLK) tw(CLK) BUSTURN = 0
FMC_CLK
Data latency = 0
FMC_NEx
td(CLKL-NADVL) td(CLKL-NADVH)
FMC_NADV
FMC_A[25:16]
td(CLKL-NWEL) td(CLKH-NWEH)
FMC_NWE
td(CLKL-ADIV) td(CLKL-Data)
td(CLKL-ADV) td(CLKL-Data)
FMC_AD[15:0] AD[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV)
td(CLKH-NBLH)
FMC_NBL
MS32758V1
190/275 DS14258 Rev 1

Table 76. Synchronous multiplexed PSRAM write timings(1)

tw(CLK) FMC_CLK period, VDD = 2.7 to 3.6 V 2Tfmc_ker_ck - 0.5 -

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x =0..2) - 1
FMC_CLK high to FMC_NEx high
td(CLKH-NExH) Tfmc_ker_ck - 1 -
(x = 0…2)
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x =16…25) - 1
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x =16…25) Tfmc_ker_ck - 1 -
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 1 ns
t(CLKH-NWEH) FMC_CLK high to FMC_NWE high Tfmc_ker_ck + 0.5 -
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 3.5
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 1 -
td(CLKL-DATA) FMC_A/D[15:0] valid data after FMC_CLK low - 1
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 1
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high Tfmc_ker_ck -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2.5 -
DS14258 Rev 1 191/275

244
Figure 38. Synchronous non-multiplexed NOR/PSRAM read timings
tw(CLK) tw(CLK)
FMC_CLK
Data latency = 0
FMC_NEx
FMC_NADV
FMC_A[25:0]
td(CLKL-NOEL) td(CLKH-NOEH)
FMC_NOE
tsu(DV-CLKH) th(CLKH-DV)
tsu(DV-CLKH) th(CLKH-DV)
FMC_D[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
tsu(NWAITV-CLKH) t h(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
MS32759V1
Table 77. Synchronous non-multiplexed NOR/PSRAM read timings(1)

tw(CLK) FMC_CLK period 2Tfmc_ker_ck –0.5 -

t(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 1
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) Tfmc_ker_ck- 1 -
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) Tfmc_ker_ck- 1 - ns
td(CLKL-NOEL) FMC_CLK ow to FMC_NOE low - 1
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high Tfmc_ker_ck + 0.5 -
tsu(DV-CLKH) FMC_D[15:0] valid data before FMC_CLK high 3.5 -
th(CLKH-DV) FMC_D[15:0] valid data after FMC_CLK high 1.5 -
t(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2.5 -
192/275 DS14258 Rev 1

Figure 39. Synchronous non-multiplexed PSRAM write timings

tw(CLK) tw(CLK)
FMC_CLK
Data latency = 0
FMC_NEx
FMC_NADV
FMC_A[25:0]
td(CLKL-NWEL) td(CLKH-NWEH)
FMC_NWE
td(CLKL-Data) td(CLKL-Data)
FMC_D[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) td(CLKH-NBLH)
th(CLKH-NWAITV)
FMC_NBL
MS32760V1
DS14258 Rev 1 193/275

244
Table 78. Synchronous non-multiplexed PSRAM write timings(1)

t(CLK) FMC_CLK period 2Tfmc_ker_ck - 0.5 -

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 1
t(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) Tfmc_ker_ck - 0.5 -
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) Tfmc_ker_ck + 0.5 -
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 1 ns
td(CLKH-NWEH) FMC_CLK high to FMC_NWE high Tfmc_ker_ck+ 0.5 -

td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low - 3.5
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 1.5
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high Tfmc_ker_ck - 0.5 -
tsu(NWAIT-
FMC_NWAIT valid before FMC_CLK high 2.5 -
CLKH)

NAND controller waveforms and timings

Figure 40 through Figure 43 represent synchronous waveforms, and Table 79 and Table 80
provide the corresponding timings. The results shown in this table are obtained with the
following FMC configuration and a capacitive load (CL) of 30 pF:
• COM.FMC_SetupTime = 0x01
• COM.FMC_WaitSetupTime = 0x03
• COM.FMC_HoldSetupTime = 0x02
• COM.FMC_HiZSetupTime = 0x01
• ATT.FMC_SetupTime = 0x01
• ATT.FMC_WaitSetupTime = 0x03
• ATT.FMC_HoldSetupTime = 0x02
• ATT.FMC_HiZSetupTime = 0x01
• Bank = FMC_Bank_NAND
• MemoryDataWidth = FMC_MemoryDataWidth_16b
• ECC = FMC_ECC_Enable
• ECCPageSize = FMC_ECCPageSize_512Bytes
• TCLRSetupTime = 0
• TARSetupTime = 0
In all timing tables, the Tfmc_ker_ck is the HCLK clock period.
194/275 DS14258 Rev 1

Figure 40. NAND controller waveforms for read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NWE
td(ALE-NOE) th(NOE-ALE)
FMC_NOE (NRE)
tsu(D-NOE) th(NOE-D)
FMC_D[15:0]
MS32767V1
Figure 41. NAND controller waveforms for write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NWE) th(NWE-AL
FMC_NWE
FMC_NOE (NRE)
tv(NWE-D) th(NWE-D)
FMC_D[15:0]
MS327
DS14258 Rev 1 195/275

244
Figure 42. NAND controller waveforms for common memory read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NOE) th(NOE-ALE)
FMC_NWE
tw(NOE)
FMC_NOE
tsu(D-NOE) th(NOE-D)
FMC_D[15:0]
MS32769V1
Figure 43. NAND controller waveforms for common memory write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NOE) tw(NWE) th(NOE-ALE)
FMC_NWE
FMC_N OE
td(D-NWE)
tv(NWE-D) th(NWE-D)
FMC_D[15:0]
MS32770V1
Table 79. Switching characteristics for NAND flash read cycles(1)

tw(N0E) FMC_NOE low width 4Tfmc_ker_ck - 0.5 4Tfmc_ker_ck+0.5

FMC_D[15-0] valid data before
tsu(D-NOE) 11 -
FMC_NOE high
FMC_D[15-0] valid data after ns
th(NOE-D) 0 -
FMC_NOE high
td(ALE-NOE) FMC_ALE valid before FMC_NOE low - 3Tfmc_ker_ck +0.5
th(NOE-ALE) FMC_NWE high to FMC_ALE invalid 4Tfmc_ker_ck - 1.5 -
196/275 DS14258 Rev 1

Table 80. Switching characteristics for NAND flash write cycles(1)

tw(NWE) FMC_NWE low width 4Tfmc_ker_ck – 0.5 4Tfmc_ker_ck +0.5

FMC_NWE low to FMC_D[15-0]
tv(NWE-D) 0 -
valid
FMC_NWE high to FMC_D[15-0]
th(NWE-D) 2Tfmc_ker_ck + 0.5 -
invalid
FMC_D[15-0] valid before ns
td(D-NWE) 5Tfmc_ker_ck - 2.5 -
FMC_NWE high
FMC_ALE valid before FMC_NWE
td(ALE-NWE) - 3Tfmc_ker_ck +0.5
low
FMC_NWE high to FMC_ALE
th(NWE-ALE) 2Tfmc_ker_ck - 1 -
invalid
DS14258 Rev 1 197/275

244
SDRAM waveforms and timings

In all timing tables, the tfmc_ker_ck is the fHCLK clock period, with the following FMC_SDCLK
maximum values:
• For 2.7 V<DD<3.6 V: maximum FMC_SDCLK = 95 MHz at 20 pF (100 MHz for
VDD > 3.0V)
• For 1.71 V<VDD<1.8 V: maximum FMC_SDCLK = 95 MHz at 15 pF
• For 1.71 V<VDD<1.8 V: maximum FMC_SDCLK = 90 MHz at 20 pF
Figure 44. SDRAM read access waveforms (CL = 1)
FMC_SDCLK
td(SDCLKL_AddC)
td(SDCLKL_AddR) th(SDCLKL_AddR)
FMC_A[12:0] Row n Col1 Col2 Coli Coln
th(SDCLKL_AddC)
td(SDCLKL_SNDE) th(SDCLKL_SNDE)
FMC_SDNE[1:0]
td(SDCLKL_NRAS) th(SDCLKL_NRAS)
FMC_SDNRAS
td(SDCLKL_NCAS) th(SDCLKL_NCAS)
FMC_SDNCAS
FMC_SDNWE
tsu(SDCLKH_Data) th(SDCLKH_Data)
FMC_D[31:0] Data1 Data2 Datai Datan
MS32751V2
198/275 DS14258 Rev 1

Table 81. SDRAM read timings(1)

tw(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck – 0.5 2Tfmc_ker_ck +0.5

tsu(SDCLKH _Data) Data input setup time 3 -
th(SDCLKH_Data) Data input hold time 0.5 -
td(SDCLKL_Add) Address valid time - 1.5
td(SDCLKL- SDNE) Chip select valid time - 1.5
ns
th(SDCLKL_SDNE) Chip select hold time 0 -
td(SDCLKL_SDNRAS) SDNRAS valid time - 1.5
th(SDCLKL_SDNRAS) SDNRAS hold time 0 -
td(SDCLKL_SDNCAS) SDNCAS valid time - 1
th(SDCLKL_SDNCAS) SDNCAS hold time 0 -
Table 82. LPSDR SDRAM read timings(1)

tW(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck – 0.5 2Tfmc_ker_ck+0.5

tsu(SDCLKH_Data) Data input setup time 3 -
th(SDCLKH_Data) Data input hold time 0.5 -
td(SDCLKL_Add) Address valid time - 1.5
td(SDCLKL_SDNE) Chip select valid time - 1.5
ns
th(SDCLKL_SDNE) Chip select hold time 0 -
td(SDCLKL_SDNRAS SDNRAS valid time - 1.5
th(SDCLKL_SDNCAS) SDNCAS hold time 0 -
DS14258 Rev 1 199/275

244
Figure 45. SDRAM write access waveforms
FMC_SDCLK
td(SDCLKL_AddC)
td(SDCLKL_AddR) th(SDCLKL_AddR)
FMC_A[12:0] Row n Col1 Col2 Coli Coln
th(SDCLKL_AddC)
td(SDCLKL_SNDE) th(SDCLKL_SNDE)
FMC_SDNE[1:0]
td(SDCLKL_NRAS) th(SDCLKL_NRAS)
FMC_SDNRAS
td(SDCLKL_NCAS) th(SDCLKL_NCAS)
FMC_SDNCAS
td(SDCLKL_NWE) th(SDCLKL_NWE)
FMC_SDNWE
td(SDCLKL_Data)
FMC_D[31:0] Data1 Data2 Datai Datan
td(SDCLKL_NBL) th(SDCLKL_Data)
FMC_NBL[3:0]
MS32752V2
Table 83. SDRAM write timings(1)

tw(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck – 0.5 2Tfmc_ker_ck+0.5

td(SDCLKL _Data) Data output valid time - 1
th(SDCLKL _Data) Data output hold time 0 -
td(SDCLKL_Add) Address valid time - 2
td(SDCLKL_SDNWE) SDNWE valid time - 1
th(SDCLKL_SDNWE) SDNWE hold time 0 -
ns
td(SDCLKL_ SDNE) Chip select valid time - 1
th(SDCLKL-_SDNE) Chip select hold time 0 -
td(SDCLKL_SDNRAS) SDNRAS valid time - 1.5
td(SDCLKL_SDNCAS) SDNCAS hold time 0 -
200/275 DS14258 Rev 1

Table 84. LPSDR SDRAM Write timings(1)

tw(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck – 0.5 2Tfmc_ker_ck+0.5

td(SDCLKL _Data) Data output valid time - 1
th(SDCLKL _Data) Data output hold time 0. -
td(SDCLKL_Add) Address valid time - 2
td(SDCLKL-SDNWE) SDNWE valid time - 1
th(SDCLKL-SDNWE) SDNWE hold time 0 -
ns
td(SDCLKL- SDNE) Chip select valid time - 1.5
th(SDCLKL- SDNE) Chip select hold time 0 -
td(SDCLKL-SDNRAS) SDNRAS valid time - 1.5
th(SDCLKL-SDNRAS) SDNRAS hold time 0 -
td(SDCLKL-SDNCAS) SDNCAS valid time - 1
td(SDCLKL-SDNCAS) SDNCAS hold time 0 -
5.3.18 Octo-SPI interface characteristics

Unless otherwise specified, the parameters given in Table 85: OCTOSPI characteristics in
SDR mode and Table 86: OCTOSPI characteristics in DTR mode (no DQS) for OCTOSPI
are derived from tests performed under the ambient temperature, fHCLK frequency and VDD
supply voltage conditions summarized in Table 20: General operating conditions, with the
following configuration:
• Measurement points are done at CMOS levels: 0.5VDD
• HSLV activated when VDD ≤ 27 V
• VOS level set to VOS0
function characteristics.
Table 85. OCTOSPI characteristics in SDR mode(1)(2)

1.71 V < VDD < 1.9 V,

- - 110
CL = 15 pF
F(CLK) OCTOSPI clock frequency MHz
1.7 V < VDD < 3.6 V,
- - 150
CL =15 pF
DS14258 Rev 1 201/275

244
Table 85. OCTOSPI characteristics in SDR mode(1)(2) (continued)

tw(CLKH) OCTOSPI clock high and PRESCALER[7:0] = n t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5
tw(CLKL) low time, even division = 0,1,3,5.3... 255 t(CLK)/2 - 0.5 - t(CK)/2 + 0.5
(n/2)*t(CLK)/ (n/2)*t(CLK)/
tw(CLKH) -
OCTOSPI clock high and PRESCALER[7:0] = n (n+1)-0.5 (n+1) + 0.5
low time, odd division = 2,4,6,....254 (n/2+1)*t(CLK)/ (n/2+1)*t(CLK)/
tw(CLKL) - ns
(n+1)-0.5 (n+1) + 0.5
ts(IN) Data input setup time - 4 - -
th(IN) Data input hold time - 1 - -
tv(OUT) Data output valid time - - 0.5 1
th(OUT) Data output hold time - 0 - -
1. All values apply to Octal and Quad-SPI mode.
3. At VOS1, these values are degraded by up to 5%.
Figure 46. OCTOSPI SDR read/write timing diagram

tr(CLK) t(CLK) tw(CLKH) tw(CLKL) tf(CLK)
Clock
tv(OUT) th(OUT)
Data output D0 D1 D2
ts(IN) th(IN)
Data input D0 D1 D2
MSv36878V3
Table 86. OCTOSPI characteristics in DTR mode (no DQS)(1)(2)(3)

1.71 V < VDD < 3.6 V,

- - 100(4)
CL = 15 pF
FCLK OCTOSPI clock frequency MHz
1.7 V < VDD < 3.6 V,
- - 125
CL = 15 pF
tw(CLKH) OCTOSPI clock high and PRESCALER[7:0] = n t(CLK)/2-0.5 - t(CLK)/2+0.5
tw(CLKL) low time = (0,1,3,5, ..255) t(CLK)/2-0.5 - t(CLK)/2+0.5
(n/2)*t(CLK)/ (n/2)*t(CLK)/
tw(CLKH) - ns
(n+1)-0.5 (n+1)+0.5
OCTOSPI clock high and PRESCALER[7:0] = n
low time = (2,4,6,8, ...254) (n/2+1)*
(n/2+1)*t(CLK)
tw(CLKL) - t(CLK)/(n+1)
/(n+1) - 0.5
+0.5
tv(CLK) Clock valid time - - - t(CLK) +0.5
202/275 DS14258 Rev 1

Table 86. OCTOSPI characteristics in DTR mode (no DQS)(1)(2)(3) (continued)

tsr(IN),
Data input setup time - 4 - -
tsf(IN)
thr(IN),
Data input hold time - 1.5 - -
thf(IN)
DHQC = 0 - 2.5 3.5
tvr(OUT) DHQC = 1,
Data output valid time - t(CLK)/4 ns
tvf(OUT) Prescaler[7 - t(CLK)/4+1
+0.5
:0] = 1,2...
DHQC = 0 1.5 - -
thr(OUT) DHQC = 1,
Data output hold time -
thf(OUT) Prescaler[7 t(CLK)/4 - 1 - -
:0] = 1,2...
1. All values apply to Octal and Quad-SPI mode.
2. Evaluated by characterization not tested in production.
3. Delay block bypassed.
4. DHQC must be set to reach the mentioned frequency.
Table 87. OCTOSPI characteristics in DTR mode (with DQS)/ hyperbus(1)(2)

1.71 V < VDD < 3.6 V,

- - 125(3)(4)
CL = 15 pF
FCLK OCTOSPI clock frequency MHz
1.7 V < VDD < 3.6 V, (3)(5)
- - 125
CL = 15 pF
tw(CLKH) OCTOSPI clock high and PRESCALER[7:0] = n t(CLK)/2-0.5 - t(CLK)/2+0.5
tw(CLKL) low time = (0,1,3,5, ..255) t(CLK)/2-0.5 - t(CLK)/2+0.5
(n/2)*t(CLK)/ (n/2)*t(CLK)/
tw(CLKH) -
(n+1)-0.5 (n+1)+0.5
OCTOSPI clock high and PRESCALER[7:0] = n
(n/2+1)* ns
low time = (2,4,6,8, ...254) (n/2+1)*t(CLK)
tw(CLKL) - t(CLK)/(n+1)
/(n+1) - 0.5
+0.5
tv(CLK) Clock valid time - - - t(CLK) +2
th(CLK) Clock hold time - t(CLK)/2-1 - -
tODr(CLK) CLK, NCLK crossing level
(5) VDD=1.8 V 890 - 1300
on CLK rising edge
mV
tODf(CLK) CLK, NCLK crossing level
(5) VDD=1.8 V 790 - 1080
on CLK falling edge
tw(CS) Chip select high time - 3 * t(CLK) - -
tv(DQ) Data input valid time - 3 - -
tv(DS) Data strobe input valid time - 1 - -
th(DS) Data strobe input hold time - 0 - -
DS14258 Rev 1 203/275

244
Table 87. OCTOSPI characteristics in DTR mode (with DQS)/ hyperbus(1)(2) (continued)
tv(RWDS) Data strobe output valid time - - - 3 * t(CLK)

tsr(DQ),
Data input setup time - -0.5 - -
tsf(DQ)
thr(DQ),
Data input hold time - 2 - -
thf(DQ)
DHQC = 0 - 2.5 3.5
DHQC = 1,
tvr(OUT) All
Data output valid time - t(CLK)/4
tvf(OUT) prescaler - t(CLK)/4+1
+0.5 ns
value
(except 0)
DHQC = 0 1.5 - -
DHQC = 1,
thr(OUT) All
Data output hold time -
thf(OUT) prescaler t(CLK)/4 - 1 - -
value
(except 0)
2. Delay block activated.
3. Maximum frequency value are given for a RWDS to DQ skew of maximum ± 1.0 ns.
4. DHQC must be set to reach the mentioned frequency.
5. Crossing results are in line with specification except for PA3/PF11 CLK/NCLK which exceeds specification.
Figure 47. OCTOSPI timing diagram - DTR mode

Clock
tvf(OUT) thr(OUT) tvr(OUT) thf(OUT)
Data output D0 D1 D2 D3 D4 D5
tsf(IN) thf(IN) tsr(IN) thr(IN)
Data input D0 D1 D2 D3 D4 D5
MSv36879V4
204/275 DS14258 Rev 1

Figure 48. OCTOSPI hyperbus clock

tf(NCLK) t(NCLK) tw(NCLKL) tw(NCLKH) tr(NCLK)
NCLK
VOD(CLK)
CLK
MSv47732V3
Figure 49. OCTOSPI hyperbus read
tw(CS)
NCS
tv(CLK) t ACC= Initial access th(CLK)
CLK, NCLK
tv(RWDS) tv(DS) th(DS)
RWDS
tv(OUT) th(OUT) Latency count tv(DQ) ts(DQ) th(DQ)
47:40 39:32 31:24 23:16 15:8 7:0 Dn Dn Dn+1 Dn+1

DQ[7:0] A B A B
Command address
Memory drives DQ[7:0] and RWDS.
Host drives DQ[7:0] and the memory drives RWDS. MSv47733V3
Figure 50. OCTOSPI hyperbus write
tw(CS)
NCS
Read write recovery Access latency

tv(CLK) th(CLK)
CLK, NCLK
tv(RWDS) High = 2x latency count tv(OUT) th(OUT)

Low = 1x latency count
RWDS
Latency count
tv(OUT) th(OUT) tv(OUT) th(OUT)
Dn Dn Dn+1 Dn+1
DQ[7:0] 47:40 39:32 31:24 23:16 15:8 7:0
A B A B
Command address Host drives DQ[7:0] and RWDS.

Host drives DQ[7:0] and the memory drives RWDS.
MSv47734V3
DS14258 Rev 1 205/275

244
5.3.19 Delay block (DLYB) characteristics

Unless otherwise specified, the parameters given in Table 88 for Delay Block are derived
from tests performed under the ambient temperature, fHCLK frequency and VDD supply
voltage summarized in Table 20: General operating conditions, with the following
configuration:
Table 88. Delay block characteristics

tinit Initial delay - 750 1100 1700 ps

t∆ Unit delay - 38 44 54 ps
5.3.20 DCMI interface characteristics

Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature, fHCLK frequency and VDD supply voltage
summarized in Table 89, with the following configuration:
• DCMI_PIXCLK polarity: falling.
• DCMI_VSYNC and DCMI_HSYNC polarity: high
• Data formats: 14 bits
• Measurement points done at CMOS levels: 0.5 * VDD
• I/O compensation cell activated.
• Voltage scaling VOS0 selected
Table 89. DCMI characteristics(1)

- Frequency ratio DCMI_PIXCLK/fHCLK - 0.4 -

DCMI_PIXCLK Pixel clock input - 100 MHz
DPIXEL Pixel clock input duty cycle 30 70 %
tsu(DATA) Data input setup time 2.5 -
th(DATA) Data hold time 2 -
tsu(HSYNC) ns
DCMI_HSYNC and DCMI_VSYNC input setup times 2.5 -
tsu(VSYNC)
th(HSYNC)
DCMI_HSYNC and DCMI_VSYNC input hold times 1.5 -
th(VSYNC)t∆
206/275 DS14258 Rev 1

Figure 51. DCMI timing diagrams

1/DCMI_PIXCLK
DCMI_PIXCLK
tsu(HSYNC) th(HSYNC)
DCMI_HSYNC
tsu(VSYNC) th(HSYNC)
DCMI_VSYNC
tsu(DATA) th(DATA)
DATA[0:13]
MS32414V2
5.3.21 PSSI interface characteristics

Unless otherwise specified, the parameters given in Table 89: DCMI characteristics and
Table 90: PSSI transmit characteristics for PSSI are derived from tests performed under the
ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 20:
General operating conditions and Section 5.3.1: General operating conditions, with the
• PSSI_PDCK polarity: falling
• PSSI_RDY and PSSI_DE polarity: low
• Bus width: 16 lines
• DATA width: 32 bits
• Capacitive load CL=30 pF
• I/O compensation cell activated
• Voltage scaling VOS0 selected
Table 90. PSSI transmit characteristics(1)

Symbol Parameter Conditions Min Max Unit
Frequency ratio
- - - 0.4 -
PSSI_PDCK/fHCLK
2.7 V≤VDD ≤3.6 V. - 90(2)
PSSI_PDCK PSSI Clock input MHz
1.71 V≤VDD ≤3.6 V. - 86
Dpixel PSSI Clock input duty cycle 30 70 %
DS14258 Rev 1 207/275

244
Table 90. PSSI transmit characteristics(1) (continued)

Data output valid time 2.7 V≤VDD ≤3.6 V. - 11

tov(DATA)
- 1.71 V≤VDD ≤3.6 V. - 11.5
toh(DATA) Data output hold time 5.5 -
tov((DE) DE output valid time - 11.5 ns
toh(DE) DE output hold time 1.71 V≤VDD ≤3.6 V. 5.5 -
tsu(RDY) RDY input setup time 0.5 -
th(RDY) RDY input hold time 0.5 -
2. This maximal frequency does not consider receiver setup and hold timings.
Table 91. PSSI receive characteristics(1)

Frequency ratio
- - 0.4 -
PSSI_PDCK/fHCLK
PSSI_PDCK PSSI Clock input 1.71 V≤VDD ≤3.6 V. - 100 MHz
Dpixel PSSI Clock input duty cycle - 30 70 %
tsu(DATA) Data input setup time 2 -
th(DATA) Data input hold time 2.5 -
tsu((DE) DE input setup time 1.5 -
1.71 V≤VDD ≤3.6 V. ns
th(DE) DE input hold time 2 -
tov(RDY) RDY output valid time - 16.5
toh(RDY) RDY output hold time 5.5 -
208/275 DS14258 Rev 1

Figure 52. PSSI transmit timing diagram
tc(PDCK)
tw(PDCKH) tw(PDCKL)
tf(PDCK) tr(PDCK)
PSSI_PDCK
CKPOL = 0
(input)
CKPOL = 1
tov(DATA) toh(DATA)
PSSI D[15:0]
Invalid data OUT Valid data OUT Invalid data OUT
(output)
PSSI_DE
(output)
DEPOL = 0
tov(DE) toh(DE)
DEPOL = 1
PSSI_RDY
RDYPOL = 0
(input)
tsu(RDY) th(RDY)
RDYPOL = 1
MSv65388V1
Figure 53. PSSI receive timing diagram

v
tc(PDCK)
tw(PDCKH) tw(PDCKL)
tf(PDCK) tr(PDCK)
PSSI_PDCK
CKPOL = 0
(input)
CKPOL = 1
tsu(DATA)
thDATA)
PSSI D[15:0]
Invalid data IN Valid data IN Invalid data IN
(input)
tsu(DE)
th(DE)
PSSI_DE
DEPOL = 0
(output)
DEPOL = 1
tov(RDY) toh(RDY)
PSSI_RDY
RDYPOL = 0
(input)
RDYPOL = 1
DS14258 Rev 1 209/275

244
5.3.22 12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 92 are derived from tests
performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 20: General operating conditions.
Table 92. 12-bit ADC characteristics(1)(2)

Analog
supply
VDDA - 1.62 - 3.6 V
voltage for
ADC ON
Positive
VREF+ reference - 1.62 - VDDA
voltage
V
Negative
VREF- reference - VSSA
voltage
ADC clock
fADC 1.62V ≤ VDDA ≤ 3.6 V 1.5 - 75 MHz
frequency
fADC=
1.8V≤VDDA≤3.6V - 5.00 -
75MHz
Continuous
Mode fADC=
1.6V≤VDDA≤3.6V 70 MH 4.66
z
Resolution SMP
-40°C ≤ TJ ≤ 130°C
= 12 bits =2.5
fADC=
2.4V≤VDDA≤3.6V 4.00 -
Single or 60MHz
Discontinuous
Mode fADC=
1.6V≤VDDA≤3.6V 3.33 -
50MHz
Sampling
rate for fast Continuous fADC=
1.6V≤VDDA≤3.6V - 5.77 -
channels Mode 75MHz
(VIN[0:5])
Resolution fADC= SMP
2.4V≤VDDA≤3.6V -40°C ≤ TJ ≤ 130°C 5.77 -
= 10 bits Single or 75MHz =2.5
Discontinuous
fS(3)
with
Mode fADC=
RAIN=47Ω 1.6V≤VDDA≤3.6V 5.00 -
65MHz MSPS
and
CPCB=22pF
Resolution fADC=
All Modes 1.6V≤VDDA≤3.6V -40°C ≤ TJ ≤ 130°C - 6.82 -
= 8 bits 75MHz
SMP
=2.5
Resolution fADC=
All Modes 1.6V≤VDDA≤3.6V -40°C ≤ TJ ≤ 130°C - 8.33 -
= 6 bits 75MHz
Resolution fADC=
- 2.30 -
= 12 bits 35MHz
Resolution fADC=
- 2.70 -
Sampling = 10 bits 35MHz
(4) SMP
rate for slow All modes 1.6V≤VDDA≤3.6V -40°C ≤ TJ ≤ 130°C
=2.5
channels Resolution fADC=
- 4.50 -
= 8 bits 50MHz
Resolution fADC=
- 5.50 -
= 6 bits 50MHz
External
tTRIG Resolution = 12 bits - - 15 1/fADC
trigger period
210/275 DS14258 Rev 1

Table 92. 12-bit ADC characteristics(1)(2) (continued)

Conversion
VAIN(2) voltage - 0 - VREF+
range
V
Common
VREF/2− VREF/2+
VCMIV mode input - VREF/2
10% 10%
voltage
Resolution = 12 bits, TJ = 130°C (Tolerance 4 LSBs) - - 321
Resolution = 12 bits, TJ = 125°C - - 220
External Resolution = 10 bits, TJ = 125°C - - 2100

RAIN(5) input Ω
impedance Resolution = 8 bits, TJ = 130°C - - 6327
Internal
sample and
CADC - - 3 - pF
hold
capacitor
tADCVREG_ ADC LDO

- - 5 10 µs
STUP startup time
ADC
conversion
tSTAB power-up LDO already started 1 - -
cycle
time
Offset
tOFF_CAL calibration - 1335
time
Trigger CKMODE = 00 1.5 2 2.5

conversion
latency for CKMODE = 01 - - 2.5
regular and
tLATR injected CKMODE = 10 2.5
channels
without
aborting the CKMODE = 11 2.25
conversion
Trigger CKMODE = 00 2.5 3 3.5

conversion
latency for CKMODE = 01 - - 3.5
regular and 1/fADC
injected CKMODE = 10 - - 3.5
tLATRINJ
channels
when a
regular
CKMODE = 11 - - 3.25
conversion is
aborted
Sampling
tS - 2.5 - 640.5
time
Total
conversion
time tS + 0.5
tCONV N-bits resolution
(including +N
sampling
time)
DS14258 Rev 1 211/275

244
Table 92. 12-bit ADC characteristics(1)(2) (continued)

ADC fs= 5MSPS - 600 -

consumption
on fs= 1MSPS - 190 -
IDDA_D(ADC) VDDA and
VREF,
Differential fs= 0.1MSPS - 50 -
mode
ADC fs= 5MSPS - 500 -

consumption
IDDA_SE(ADC) on VDDA and fs= 1MSPS - 150 -
VREF Single-
ended mode fs= 0.1MSPS - 50 - µA
fADC=75MHz - 265 -
fADC=50MHz 175 -
ADC fADC=25MHz - 90 -
IDD(ADC) consumption
on VDD fADC=12.5MHz - 45 -
fADC=6.25MHz - 22 -
fADC=3.125MHz - 11 -

2. The voltage booster on ADC switches must be used for VDDA < 2.7 V (embedded I/O switches).
3. These values are valid on BGA packages.
4. Depending on the package, VREF+ can be internally connected to VDDA and VREF- to VSSA.
5. The tolerance is 2 LSBs for 12-bit, 10-bit and 8-bit resolutions, otherwise specified.
Table 93. Minimum sampling time versus RAIN(1)(2)

Minimum sampling time (s)
Resolution RAIN (Ω)
Fast channel Slow channel(3)
47 3.75E-08 6.12E-08
68 3.94E-08 6.25E-08
100 4.36E-08 6.51E-08
150 5.11E-08 7.00E-08
12 bits
220 6.54E-08 7.86E-08
330 8.80E-08 9.57E-08
470 1.17E-07 1.23E-07
680 1.60E-07 1.65E-07
212/275 DS14258 Rev 1

Table 93. Minimum sampling time versus RAIN(1)(2) (continued)

47 3.19E-08 5.17E-08
68 3.35E-08 5.28E-08
100 3.66E-08 5.45E-08
150 4.35E-08 5.83E-08
220 5.43E-08 6.50E-08
330 7.18E-08 7.89E-08
10 bits
470 9.46E-08 1.00E-07
680 1.28E-07 1.33E-07
1000 1.81E-07 1.83E-07
1500 2.63E-07 2.63E-07
2200 3.79E-07 3.76E-07
3300 5.57E-07 5.52E-07
47 2.64E-08 4.17E-08
68 2.76E-08 4.24E-08
100 3.02E-08 4.39E-08
150 3.51E-08 4.66E-08
220 4.27E-08 5.13E-08
330 5.52E-08 6.19E-08
470 7.17E-08 7.72E-08
680 9.68E-08 1.00E-07
8 bits
1000 1.34E-07 1.37E-07
1500 1.93E-07 1.94E-07
2200 2.76E-07 2.74E-07
3300 4.06E-07 4.01E-07
4700 5.73E-07 5.62E-07
6800 8.21E-07 7.99E-07
10000 1.20E-06 1.17E-06
15000 1.79E-06 1.74E-06
DS14258 Rev 1 213/275

244
Table 93. Minimum sampling time versus RAIN(1)(2) (continued)

47 2.14E-08 3.16E-08
68 2.23E-08 3.21E-08
100 2.40E-08 3.31E-08
150 2.68E-08 3.52E-08
220 3.13E-08 3.87E-08
330 3.89E-08 4.51E-08
470 4.88E-08 5.39E-08
680 6.38E-08 6.79E-08
6 bits
1000 8.70E-08 8.97E-08
1500 1.23E-07 1.24E-07
2200 1.73E-07 1.73E-07
3300 2.53E-07 2.49E-07
4700 3.53E-07 3.45E-07
6800 5.04E-07 4.90E-07
10000 7.34E-07 7.11E-07
15000 1.09E-06 1.05E-06
2. Data valid up to 130 °C, with a 22 pF PCB capacitor, and VDDA = 1.6 V.
3. Slow channels correspond to all ADC inputs except for the fast channels.
Figure 54. ADC conversion timing diagram
CLK
Mux Sampling(1) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1/2 SMP Number of CLK clock cycles = ADC resolution / 2
Total conversion time: 0.5 +Tsamp + N/2
1. The sampling time defines the minimum sampling clock cycles (SMP) to be programmed in the ADC (refer to the product reference manual for details).
214/275 DS14258 Rev 1

Table 94. ADC accuracy(1)(2)

Fast and Single ended - ±3.5 ±12

ET Total unadjusted error slow
channels Differential - ±2.5 ±7.5
- Single ended - ±3 ±5.5

EO Offset error
- Differential - ±2 ±3.5
- Single ended - ±3.5 ±11
EG Gain error LSB
- Differential ±2.5 ±7
- Single ended - ±0.75 +2/-1
ED Differential linearity error
- Differential - ±0.75 +2/-1
Fast and Single ended - ±2 ±6.5
EL Integral linearity error slow
channels Differential - ±1 ±4
Single ended - 10.8 -

ENOB Effective number of bits Bits
Differential - 11.5 -
Signal-to-noise and Single ended - 68 -

SINAD
distortion ratio Differential - 71 -
Single ended - 70 -
SNR Signal-to-noise ratio dB
Differential - 72 -
Single ended - -70 -
THD Total harmonic distortion
Differential - -80 -
1. Evaluated by characterization for BGA packages. The values for LQFP package might differ. - Not tested in production.
2. ADC DC accuracy values are measured after internal calibration in continuous mode.
Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog
input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to
ground) to analog pins which may potentially inject negative currents.
DS14258 Rev 1 215/275

244
Figure 55. ADC accuracy characteristics
VREF+ VDDA
[1LSB = (or )]
Output code 2n 2n
EG
(1) Example of an actual transfer curve
2n-1 (2) Ideal transfer curve
2n-2 (3) End-point correlation line
2n-3 (2)
n = ADC resolution
ET = total unadjusted error: maximum deviation
(3) between the actual and ideal transfer curves
ET
7 (1) EO = offset error: maximum deviation between the first
actual transition and the first ideal one
6
EL EG = gain error: deviation between the last ideal
5 EO
transition and the last actual one
4 ED = differential linearity error: maximum deviation
ED between actual steps and the ideal one
3
2 EL = integral linearity error: maximum deviation between
1 any actual transition and the end point correlation line
1 LSB ideal
0 VREF+ (VDDA)
(1/2n)*VREF+
(2/2n)*VREF+
(3/2n)*VREF+
(4/2n)*VREF+
(5/2n)*VREF+
(6/2n)*VREF+
(7/2n)*VREF+
(2n-3/2n)*VREF+
(2n-2/2n)*VREF+
(2n-1/2n)*VREF+
(2n/2n)*VREF+
VSSA
MSv19880V6
1. Example of an actual transfer curve.

2. Ideal transfer curve.
3. End point correlation line.
4. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
5. EO = Offset Error: deviation between the first actual transition and the first ideal one.
6. EG = Gain Error: deviation between the last ideal transition and the last actual one.
7. ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.
8. EL = Integral Linearity Error: maximum deviation between any actual transition and the end point
correlation line.
Figure 56. Typical connection diagram when using the ADC with FT/TT pins
featuring analog switch function
VDDA(4) VREF+(4)
I/O Sample-and-hold ADC converter

analog
RAIN(1) switch RADC
Converter
Cparasitic(2) Ilkg(3) CADC

VAIN Sampling
switch with
multiplexing
VSS VSS VSSA
MSv67871V3
1. Refer to Table 92: 12-bit ADC characteristics for the values of RAIN, and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (refer to Table 57: I/O static characteristics). A high Cparasitic value downgrades
conversion accuracy. To remedy this, fADC should be reduced.
3. Refer to Table 57: I/O static characteristics for the value of Ilkg.
4. Refer to Figure 20: STM32H563 power supply scheme with SMPS.
216/275 DS14258 Rev 1

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 57 or Figure 58,
depending on whether VREF+ is connected to VDDA or not. The 100 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 57. Power supply and reference decoupling (VREF+ not connected to VDDA)
STM32
VREF+(1)
1 μF // 100 nF
VDDA
1 μF // 100 nF
VSSA/VREF-(1)
MSv50648V2
1. VREF+ input is not available on all package (refer to Table 14: STM32H562xx and STM32H563xx pin/ball
definition) whereas VREF- is available only on UFBGA176+25, UFBGA169 with SMPS, LQFP100,
UFBGA169, and UFBGA176+25. When VREF- is not available, it is internally connected to VSSA.
Figure 58. Power supply and reference decoupling (VREF+ connected to VDDA)
STM32
VREF+/VDDA(1)
1 μF // 100 nF
VREF-/VSSA(1)
MSv50649V1
1. VREF+ input is not available on all package (refer to Table 14: STM32H562xx and STM32H563xx pin/ball
definition) whereas VREF- is available only on UFBGA176+25, UFBGA169 with SMPS, LQFP100,
UFBGA169, and UFBGA176+25. When VREF- is not available, it is internally connected to VSSA.
DS14258 Rev 1 217/275

244
5.3.23 DAC characteristics
Table 95. DAC characteristics(1)

VDDA Analog supply voltage - 1.8 3.3 3.6

VREF+ Positive reference voltage - 1.80 - VDDA
V
Negative reference
VREF- - - VSSA -
voltage
connected
5 - -
DAC output buffer to VSSA
RL Resistive Load
ON connected kΩ
25 - -
to VDDA
RO Output Impedance DAC output buffer OFF 10.3 13 16
Output impedance VDD = 2.7 V - - 1.6
DAC output buffer
RBON sample and hold mode, kΩ
ON VDD = 2.0 V - - 2.6
output buffer ON
Output impedance VDD = 2.7 V - - 17.8
DAC output buffer
RBOFF sample and hold mode, kΩ
OFF VDD = 2.0 V - - 18.7
output buffer OFF
CL DAC output buffer OFF - - 50 pF
Capacitive Load
CSH Sample and Hold mode - 0.1 1 µF
VDDA
Voltage on DAC_OUT DAC output buffer ON 0.2 -
VDAC_OUT −0.2 V
output
DAC output buffer OFF 0 - VREF+
±0.5 LSB - 2.05 3
Settling time (full scale:
for a 12-bit code transition Normal mode, DAC ±1 LSB - 1.97 2.87
between the lowest and output buffer ON,
±2 LSB - 1.67 2.84
the highest input codes CL ≤ 50 pF,
tSETTLING RL ≥ 5 ㏀ ±4 LSB - 1.66 2.78 µs
when DAC_OUT reaches
the final value of ±0.5LSB, ±8 LSB - 1.65 2.7
±1LSB, ±2LSB, ±4LSB,
±8LSB) Normal mode, DAC output buffer
- 1.7 2
OFF, ±1LSB CL=10 pF
Wakeup time from off Normal mode, DAC output buffer
- 5 7.5
state (setting the ENx bit ON, CL ≤ 50 pF, RL = 5 ㏀
tWAKEUP(2) in the DAC Control µs
register) until the final Normal mode, DAC output buffer
- 2 5
value of ±1LSB is reached OFF, CL ≤ 10 pF
DC VDDA supply rejection Normal mode, DAC output buffer

PSRR - -80 -28 dB
ratio ON, CL ≤ 50 pF, RL = 5 ㏀
218/275 DS14258 Rev 1

Table 95. DAC characteristics(1) (continued)

Sampling time in Sample MODE<2:0>_V12=100/101

- 0.7 2.6
and Hold mode (BUFFER ON)
CL=100 nF ms
MODE<2:0>_V12=110
(code transition between - 11.5 18.7
tSAMP (BUFFER OFF)
the lowest input code and
the highest input code MODE<2:0>_V12=111(3)
when DAC_OUT reaches - 0.3 0.6 µs
(INTERNAL BUFFER OFF)
the ±1LSB final value)
(4)
Ileak Output leakage current - - - nA
Internal sample and hold
CIint - 1.8 2.2 2.6 pF
capacitor
Middle code offset trim Minimum time to verify the each
tTRIM 50 - - µs
time code
Middle code offset for 1 VREF+ = 3.6 V - 850 -

Voffset µV
trim code step VREF+ = 1.8 V - 425 -
No load,
middle code - 360 -
DAC output buffer (0x800)
ON No load,
worst code - 490 -
(0xF1C)
DAC quiescent
IDDA(DAC) No load,
consumption from VDDA
DAC output buffer middle/
- 20 -
OFF worst code
(0x800)
360*TON/
Sample and Hold mode,
- (TON+TOFF) -
CSH=100 nF (5)
No load,
middle code - 170 - µA
DAC output buffer (0x800)
ON No load,
worst code - 170 -
(0xF1C)
No load,
DAC consumption from DAC output buffer middle/
IDDV(DAC) - 160 -
VREF+ OFF worst code
(0x800)
170*TON/
Sample and Hold mode, Buffer
- (TON+TOFF) -
ON, CSH=100 nF (worst code) (5)
160*TON/
Sample and Hold mode, Buffer
- (TON+TOFF) -
OFF, CSH=100 nF (worst code) (5)
DS14258 Rev 1 219/275

244
2. In buffered mode, the output can overshoot above the final value for low input code (starting from the minimum value).
3. DACx_OUT pin is not connected externally (internal connection only).
4. Refer to Table 57: I/O static characteristics.
5. TON is the refresh phase duration, while TOFF is the hold phase duration. Refer to the product reference manual for more
details.
Table 96. DAC accuracy(1)

Differential non DAC output buffer ON −2 - 2

DNL LSB
linearity(2) DAC output buffer OFF −2 - 2
- Monotonicity 10 bits - - - -
DAC output buffer ON, CL ≤ 50 pF,
−4 - 4
RL ≥ 5 ㏀
INL Integral non linearity(3) LSB
DAC output buffer OFF,
−4 - 4
CL ≤ 50 pF, no RL
DAC output VREF+ = 3.6 V - - ±12
buffer ON,
Offset error at code CL ≤ 50 pF, VREF+ = 1.8 V - - ±25
Offset RL ≥ 5 ㏀ LSB
0x800 (3)
- - ±8
CL ≤ 50 pF, no RL
Offset error at code DAC output buffer OFF,
Offset1 - - ±5 LSB
0x001(4) CL ≤ 50 pF, no RL
DAC output VREF+ = 3.6 V - - ±5
Offset error at code buffer ON,
OffsetCal 0x800 after factory LSB
CL ≤ 50 pF, VREF+ = 1.8 V - - ±7
calibration
RL ≥ 5 ㏀
DAC output buffer ON,CL ≤ 50 pF,
- - ±1
RL ≥ 5 ㏀
Gain Gain error(5) %
- - ±1
CL ≤ 50 pF, no RL
- - ±30
RL ≥ 5 ㏀
TUE Total unadjusted error
DAC output buffer OFF, CL ≤
±12 LSB
50 pF, no RL
Total unadjusted error DAC output buffer ON, CL ≤ 50 pF,
TUECal - - ±23
after calibration RL ≥ 5 ㏀
DAC output buffer ON,CL ≤ 50 pF,
- 67.8 -
RL ≥ 5 ㏀ , 1 kHz, BW = 500 KHz
SNR Signal-to-noise ratio(6) DAC output buffer OFF, dB
CL ≤ 50 pF, no RL,1 kHz, BW = - 67.8 -
500 KHz
220/275 DS14258 Rev 1

Table 96. DAC accuracy(1) (continued)

- −78.6 -
Total harmonic RL ≥ 5 ㏀ , 1 kHz
THD dB
distortion(6) DAC output buffer OFF,
- −78.6 -
CL ≤ 50 pF, no RL, 1 kHz
- 67.5 -
Signal-to-noise and RL ≥ 5 ㏀ , 1 kHz
SINAD dB
distortion ratio(6) DAC output buffer OFF,
- 67.5 -
DAC output buffer ON,
- 10.9 -
Effective number of CL ≤ 50 pF, RL ≥ 5 ㏀ , 1 kHz
ENOB bits
bits DAC output buffer OFF,
- 10.9 -
2. Difference between two consecutive codes minus 1 LSB.
3. Difference between the value measured at Code i and the value measured at Code i on a line drawn between Code 0 and
last Code 4095.
4. Difference between the value measured at Code (0x001) and the ideal value.
5. Difference between the ideal slope of the transfer function and the measured slope computed from code 0x000 and 0xFFF
when the buffer is OFF, and from code giving 0.2 V and (VREF+ - 0.2 V) when the buffer is ON.
6. Signal is −0.5dBFS with Fsampling=1 MHz.
Figure 59. 12-bit buffered /non-buffered DAC
Buffered/Non-buffered DAC
Buffer(1)
RL
12-bit DAC_OUTx
digital to
analog
converter
CL
ai17157V3
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
DS14258 Rev 1 221/275

244
5.3.24 Analog temperature sensor characteristics
Table 97. Analog temperature sensor characteristics

VSENSE linearity with temperature (from VSENSOR voltage) - - 3

TL(1) °C
VSENSE linearity with temperature (from ADC counter) - - 3
Average slope (from VSENSOR voltage) - 2 -
Avg_Slope(2) mV/°C
Average slope (from ADC counter) - 2 -
V30(3) Voltage at 30°C ± 5 °C - 0.62 - V
tstart_run Startup time in Run mode (buffer startup) - - 25.2
µs
(1)
tS_temp ADC sampling time when reading the temperature 9 - -
Isens(1) Sensor consumption - 0.18 0.31
µA
Isensbuf(1) Sensor buffer consumption - 3.8 6.5
3. Measured at VDDA = 3.3 V ± 10 mV. The V30 ADC conversion result is stored in the TS_CAL1 bytes.
Table 98. Temperature sensor calibration values

Symbol Parameter Memory address
Temperature sensor raw data acquired value at

TS_CAL1 0x08FF F814 -0x08FF F815
30 °C, VDDA=3.3 V
Temperature sensor raw data acquired value at
TS_CAL2 0x08FF F818 - 0x08FF F819
130 °C, VDDA=3.3 V
5.3.25 Digital temperature sensor characteristics
Table 99. Digital temperature sensor characteristics(1)

fDTS(2) Output Clock frequency - 500 750 1150 kHz

Hz/°
TLC(2) Temperature linearity coefficient VOS2 1660 2100 2750
C
TJ = −40°C to
-13 - 4
TTOTAL_ERROR Temperature offset 30°C
(2) °C
measurement, all VOS TJ = 30°C to
-7 - 2
Tjmax
VOS2 0 - 0
Additional error due to supply
TVDD_CORE VOS0, VOS1, °C
variation -1 - 1
VOS3
tTRIM Calibration time - - - 2 ms
222/275 DS14258 Rev 1

Table 99. Digital temperature sensor characteristics(1) (continued)

Wake-up time from off state until

tWAKE_UP - - 67 116.00 μs
DTS ready bit is set
DTS consumption on
IDDCORE_DTS - 8.5 30 70.0 μA
VDD_CORE
1. Specified by design - not tested in production, unless otherwise specified.
5.3.26 VCORE monitoring characteristics
Table 100. VCORE monitoring characteristics(1)

TS_VCORE ADC sampling time when reading the VCORE voltage 1 - - μs

5.3.27 Temperature and VBAT monitoring
Table 101. VBAT monitoring characteristics

R Resistor bridge for VBAT - 4 x 26 - KΩ

Q Ratio on VBAT measurement - 4 - -
Er(1) Error on Q -10 - +10 %
tS_vbat(1) ADC sampling time when reading VBAT input 9 - - µs
VBAThigh High supply monitoring 3.5 3.575 3.63
V
VBATlow Low supply monitoring - 1.36 -
IVBATbuf Sensor buffer consumption - 3.8 6.5 µA
Table 102. VBAT charging characteristics

VBRS in PWR_CR3= 0 - 5 -
RBC Battery charging resistor KΩ
VBRS in PWR_CR3= 1 1.5 -
Table 103. Temperature monitoring characteristics

TEMPhigh High temperature monitoring - 126 -

°C
TEMPlow Low temperature monitoring - -37 -
DS14258 Rev 1 223/275

244
5.3.28 Voltage booster for analog switch
Table 104. Voltage booster for analog switch characteristics(1)

VDD Supply voltage - 1.71 2.6 3.6 V

tSU(BOOST) Booster startup time - - - 50 µs
1.71 V ≤ VDD ≤ 2.7 V - - 125
IDD(BOOST) Booster consumption µA
2.7 V < VDD < 3.6 V - - 250
5.3.29 VREFBUF characteristics
Table 105. VREFBUF characteristics(1)

VRS = 000 2.8 3.3 3.6

Normal mode
VRS = 001 2.4 - 3.6
VDDA = 3.3V
Analog supply VRS = 010 2.1 - 3.6
VDDA V
voltage VRS = 000 1.62 - 2.80
Degraded mode(2) VRS = 001 1.62 - 2.40
VRS = 010 1.62 - 2.10
VRS = 000 2.498(3) 2.5000 2.5035(3)
Normal mode
VRS = 001 2.0460 2.0490 2.0520
at 30°C, ILOAD=100µA
VREFBUF_ Voltage reference VRS = 010 1.8010 1.8040 1.8060
V
OUT Buffer Output VRS = 000 VDDA − 150 mV - 2.5035
Degraded mode(2) VRS = 001 VDDA − 150 mV - 2.0520
VRS = 010 VDDA − 150 mV - 1.806
Trim step
TRIM - - - ±0.05 ±0.1 %
resolution
CL Load capacitor - - 0.5 1 1.50 uF
Equivalent serial
esr - - - - 2 Ω
resistor of CL
Iload Static load current - - - - 4 mA
ppm/
Iload = 500 µA - 200 -
V
Iline_reg Line regulation 2.8 V ≤ VDDA ≤ 3.6 V
Iload = 4 mA - 100 -
ppm/
Iload_reg Load regulation 500 µA ≤ Iload ≤ 4 mA Normal Mode - 50 -
mA
224/275 DS14258 Rev 1

Table 105. VREFBUF characteristics(1) (continued)

Tcoeff
Temperature ppm/
Tcoeff -40 °C < TJ < +130 °C - - - VREFINT
coefficient °C
+ 100
Power supply DC - - 60 - dB
PSRR
rejection 100 KHz - - 40 -
CL=0.5 µF - - 300 - µs
tSTART Start-up time CL=1 µF - - 500 -
CL=1.5 µF - - 650 -
Control of
maximum DC
current drive on
IINRUSH - - 8 - mA
VREFBUF_OUT
during startup
phase(4)(4)
ILOAD = 0 µA - - 15 25 µA
VREFBUF
IDDA(VREF
consumption from ILOAD = 500 µA - - 16 30
BUF) VDDA
ILOAD = 4 mA - - 32 50

2. In degraded mode, the voltage reference buffer cannot accurately maintain the output voltage (VDDA−drop voltage).
4. To properly control VREFBUF IINRUSH current during the startup phase and the change of scaling, VDDA voltage should be in
the range of 2.1 V - 3.6 V, 2.4 V -3.6 V and 2.8 V - 3.6 V for VRS = 010, 001, and 000, respectively.
5.3.30 Timer characteristics

The parameters given in Table 106 are guaranteed by design.
Refer to Section 5.3.14: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 106. TIMx characteristics(1)(2)

AHB/APBx prescaler=1
or 2 or 4, fTIMxCLK = 1 - tTIMxCLK
250 MHz
tres(TIM) Timer resolution time
AHB/APBx
prescaler>4, fTIMxCLK = 1 - tTIMxCLK
125 MHz
DS14258 Rev 1 225/275

244
Table 106. TIMx characteristics(1)(2) (continued)

Timer external clock

fEXT 0 fTIMxCLK/2 MHz
frequency on CH1 to CH4 f
TIMxCLK = 250 MHz
ResTIM Timer resolution - 16/32 bit
Maximum possible count 65536 ×
tMAX_COUNT - - tTIMxCLK
with 32-bit counter 65536
1. TIMx is used as a general term to refer to the TIM1 to TIM17 timers.
3. The maximum timer frequency on APB1 or APB2 is up to 250 MHz, by setting the TIMPRE bit in the
RCC_CFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = rcc_hclk1,
otherwise TIMxCLK = 4 x Frcc_pclkx1 or TIMxCLK = 4 x Frcc_pclkx2.
5.3.31 Low-power timer characteristics
Table 107. LPTIMx characteristics(1)(2)

tres(TIM) Timer resolution time 1 - tTIMxCLK
fLPTIMxCLK Timer kernel clock 0 250

Timer external clock frequency on Input1 and MHz
fEXT 0 fLPTIMxCLK/2
Input2
ResTIM Timer resolution - 16 bit
tMAX_COUNT Maximum possible count - 65536 tTIMxCLK
1. LPTIMx is used as a general term to refer to the LPTIM1 to LPTIM6 timers.

5.3.32 Communication interfaces

I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual revision 03 for:
• Standard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The I2C timings requirements are specified by design, not tested in production, when the I2C
peripheral is properly configured (refer to the product reference manual - RM0481)
The SDA and SCL I/O requirements are met with the following restrictions:
• The SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain,
the PMOS connected between the I/O pin and VDD is disabled, but still present. Only
FT_f I/O pins support Fm+ low level output current maximum requirement. Refer to
Section 5.3.14: I/O port characteristics for the I2C I/Os characteristics
All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog fil-
226/275 DS14258 Rev 1

ter characteristics:
Table 108. I2C analog filter characteristics(1)(2)

tAF Maximum pulse width of spikes that are suppressed by analog filter 50(3) 160(4) ns
2. Measurement points are done at 50% VDD.
3. Spikes with widths below tAF(min) are filtered.
4. Spikes with widths above tAF(max) are not filtered.
USART interface characteristics

Unless otherwise specified, the parameters given in Table 109 for USART are derived from
tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 20: General operating conditions, with the following
configuration:
• IO compensation cell activated
• HSLV activated when VDD≤ 2.7 V
function characteristics (NSS, CK, TX, RX for USART).
Table 109. USART characteristics(1)

Master receiver
31
1.71 V < VDD < 3.6 V
Master transmitter
31/6(2)
1.71 V < VDD < 3.6 V
Master transmitter
31/6(2)
2.7 V < VDD < 3.6 V
fCK USART clock frequency - - MHz
Slave receiver
83
1.71 V < VDD < 3.6 V
Slave transmitter
32/6(2)
1.71 V < VDD < 3.6 V
Slave transmitter
35/6(2)
2.7 V < VDD < 3.6 V
DS14258 Rev 1 227/275

244
Table 109. USART characteristics(1) (continued)

(3)
tsu(NSS) NSS setup time Slave mode tker + 3.5 - -
th(NSS) NSS hold time Slave mode 2.5 - -
tw(SCKH)
CK high and low time Master mode 1/fck/2 -1 1/fck/2 1/fck/2 +1
tw(SCKL)
Master mode 13 - -
tsu(RX) Data input setup time
Slave mode 3.5 - -
Master mode 0.5 - -
th(RX) Data input hold time
Slave mode 1.5 - -
Slave mode, ns
- 15.5/71(2)
1.71 V < VDD < 3.6 V
11.5
Slave mode,
- 14/35(2)
2.7 V < VDD < 3.6 V
tv(TX) Data output valid time
Slave mode,
- 3/52(2)
1.71 V < VDD < 3.6 V
2.5
Slave mode,
- 3/22(2)
2.7 V < VDD < 3.6 V
Slave mode 7.5 - -
th(TX) Data output hold time
Master mode 0 - -
2. For PB14 with OSPEEDRy[1:0] = 01.
3. Tker is the usart_ker_ck_pres clock period.
Figure 60. USART timing diagram in Master mode
1/fCK
CK output
CPHA = 0
CPOL = 0
CPHA = 0
CPOL = 1
CK output
CPHA = 1
CPOL = 0
CPHA = 1
CPOL = 1
tw(CKH)
tsu(RX) tw(CKL)
RX
INPUT MSB IN BIT6 IN LSB IN
th(RX)
TX
OUTPUT MSB OUT BIT1 OUT LSB OUT
tv(TX) th(TX)
MSv65386V4
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
228/275 DS14258 Rev 1

Figure 61. USART timing diagram in Slave mode
NSS
input
1/fCK th(NSS)
tsu(NSS) tw(CKH)
CPHA = 0
CK input
CPOL = 0
CPHA = 0
CPOL = 1
tw(CKL) tv(TX) th(TX)
TX output First bit OUT Next bits OUT Last bit OUT
th(RX)
tsu(RX)
RX input First bit IN Next bits IN Last bit IN

MSv65387V4
I3C interface characteristics

The I3C interface meets the timings requirements of the MIPI® I3C specification v1.1.
The I3C peripheral supports:
• I3C SDR-only as controller
• I3C SDR-only as target
• I3C SCL bus clock frequency up to 12.5 MHz
The parameters given in Table 110: I3C open-drain measured timing are obtained with the
• I/O Compensation cell activated.
• VOS level set to VOS 0.
The I3C timings are in line with MIPI specification except for the ones given in Table 110:
I3C open-drain measured timing and Table 111: I3C push-pull measured timing. For tSU_OD
and tSU_PP this can be mitigated by increasing the corresponding SCL low duration in the
I3C_TIMINGR0 register. For tSCO this can be mitigated by enabling and adjusting the clock
stall time both on the address ACK phase and on the data read Tbit phase in the
I3C_TIMINGR2 register. This can also be mitigated by increasing the SCL low duration in
the I3C_TIMINGR0 register. For further details refer to the AN5879.
DS14258 Rev 1 229/275

244
Table 110. I3C open-drain measured timing

I3C open drain mode
(specification) Timing
measurements
Min Max
SDA data setup time Controller

tSU_OD 3 - 16.5 ns
during open drain mode 1.71 V < VDD < 3.6 V
Table 111. I3C push-pull measured timing

I3C open drain mode
(specification) Timing
measurements
Min Max
SDA signal data setup in Controller

tSU_PP 3 - 12 ns
push-pull mode 1.71 V < VDD < 3.6 V
SPI interface characteristics

Unless otherwise specified, the parameters given in Table 112 for SPI are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
configuration:
function characteristics (NSS, SCK, MOSI, MISO for SPI).
Table 112. SPI characteristics(1)

Master receiver mode

- - 135/3(2)
2.7 V < VDD < 3.6 V
- - 120/3(2)
1.71 V < VDD < 2.7 V
- - 120/3(2)
fSCK 1.71 V < VDD < 3.6 V
SPI clock frequency MHz
1/tSCK Slave receiver mode
- - 120
1.71V < VDD < 2.7 V
Slave transmitter mode
- - 43/6(3)
2.7 V < VDD < 3.6V
Slave transmitter mode
- - 41/6(3)
1.71V < VDD < 2.7 V
230/275 DS14258 Rev 1

Table 112. SPI characteristics(1) (continued)

tsu(NSS) NSS setup time Slave mode 3.5 - -

th(NSS) NSS hold time Slave mode 4.5 - -
ns
tw(SCKH)
SCK high and low time Master mode (tSCK/2) - 1 (tSCK/2) (tSCK/2) + 1
tw(SCKL)
tsu(MI) Master mode 3.5 - - ns
Data input setup time
tsu(SI) Slave mode 2 - -
th(MI) Master mode 1 - -

Data input hold time
th(SI) Slave mode 1.5 - -
ta(SO) Data output access time Slave mode 6.5 - 15
tdis(SO) Data output disable time Slave mode 7.5 - 18
Slave mode,
- 8.5/25(3) 11.5/33(3)
2.7 V < VDD < 3.6 V
tv(SO)
Data output valid time Slave mode,
- 10/59(3) 12/76(3)
1.71 V < VDD < 3.6 V
tv(MO) Master mode - 1.5 2
Slave mode,
th(SO) 6.5/20.5(3) - -
1.71 V < VDD < 3.6 V
Data output hold time
th(MO) Master mode 0 - -

2. When using PB13.
3. When using PB14.
DS14258 Rev 1 231/275

244
Figure 62. SPI timing diagram - master mode(1)
High
NSS input
tc(SCK)
SCK Output
CPHA=0
CPOL=0
CPHA=0
CPOL=1
SCK Output
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH) tr(SCK)
tsu(MI) tw(SCKL) tf(SCK)
MISO
INPUT MSB IN BIT6 IN LSB IN
th(MI)
MOSI
OUTPUT MSB OUT BIT1 OUT LSB OUT
tv(MO) th(MO)
ai14136c
Figure 63. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK) th(NSS)
tsu(NSS) tw(SCKH) tr(SCK)

CPHA=0
SCK input
CPOL=0
CPHA=0
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tf(SCK) tdis(SO)
MISO output First bit OUT Next bits OUT Last bit OUT
th(SI)
tsu(SI)
MOSI input First bit IN Next bits IN Last bit IN
MSv41658V1
232/275 DS14258 Rev 1

Figure 64. SPI timing diagram - slave mode and CPHA = 1(1)
NSS input
tc(SCK)
tsu(NSS) tw(SCKH) tf(SCK) th(NSS)

CPHA=1
SCK input
CPOL=0
CPHA=1
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tr(SCK) tdis(SO)
MISO output First bit OUT Next bits OUT Last bit OUT
tsu(SI) th(SI)
MOSI input First bit IN Next bits IN Last bit IN
MSv41659V1
I2S Interface characteristics

Unless otherwise specified, the parameters given in Table 113 for I2S are derived from tests
configuration:
function characteristics (CK,SD,WS).
Table 113. I2S dynamic characteristics(1)

fMCK I2S main clock output - - 50

Master transmitter - 50
MHz
fCK I2S clock output Slave transmitter (TX) - 21
Slave receiver (RX) - 50
DS14258 Rev 1 233/275

244
Table 113. I2S dynamic characteristics(1) (continued)

tv(WS) WS valid time - 2

Master mode
th(WS) WS hold time 0.5 -
tsu(WS) WS setup time 3 -
Slave mode
th(WS) WS hold time 1.5 -
tsu(SD_MR) Master receiver 4 -
tsu(SD_SR) Slave receiver 2 -
th(SD_MR) Master receiver 1 -
th(SD_SR) Slave receiver 1.5 - ns
Slave transmitter
tv(SD_ST) - 14
(after enable edge)
Data output valid time
Master transmitter
tv(SD_MT) - 1
(after enable edge)
Slave transmitter
th(SD_ST) 5.5 -
(after enable edge)
Data output hold time
Master transmitter
th(SD_MT) 0 -
(after enable edge)
Figure 65. I2S slave timing diagram (Philips protocol)(1)
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
234/275 DS14258 Rev 1

Figure 66. I2S master timing diagram (Philips protocol)(1)
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
SAI characteristics
Unless otherwise specified, the parameters given in Table 114 for SAI are derived from tests
configuration:
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output
alternate function characteristics (SCK,SD,WS).
DS14258 Rev 1 235/275

244
Table 114. SAI characteristics(1)

fMCK SAI Main clock output - - 50

Master transmitter, 2.7 V ≤ VDD ≤ 3.6 V - 38
Master transmitter, 1.71 V ≤ VDD ≤ 3.6 V - 38
Master receiver, 1.71 V ≤ VDD ≤ 3.6 V - 38 MHz
fCK SAI clock frequency
Slave transmitter, 2.7 V ≤ VDD ≤ 3.6 V - 34
Slave transmitter, 1.71 V ≤ VDD ≤ 3.6 V - 33
Slave receiver, 1.71 V ≤ VDD ≤ 3.6 V - 50
Master mode, 2.7 V ≤ VDD ≤ 3.6 V - 13
tv(FS) FS valid time
Master mode, 1.71 V ≤ VDD ≤ 3.6 V - 13
tsu(FS) FS setup time Slave mode 3 -
Master mode 5 -
th(FS) FS hold time
Slave mode 2 -
tsu(SD_A_MR) Master receiver 4 -
tsu(SD_B_SR) Slave receiver 3.5 -
th(SD_A_MR) Master receiver 1.5 -
th(SD_B_SR) Slave receiver 0.5 -
ns
Slave transmitter (after enable edge),
- 14.5
2.7 V ≤ VDD ≤ 3.6 V
tv(SD_B_ST) Data output valid time
Slave transmitter (after enable edge),
- 15
1.71 V ≤ VDD ≤ 3.6 V
th(SD_B_ST) Data output hold time Slave transmitter (after enable edge) 7 -
Master transmitter (after enable edge),
- 13
2.7 V ≤ VDD ≤ 3.6 V
tv(SD_A_MT) Data output valid time
Master transmitter (after enable edge),
- 13
1.71 V ≤ VDD ≤ 3.6 V
th(SD_A_MT) Data output hold time Master transmitter (after enable edge) 5.5 -
236/275 DS14258 Rev 1

Figure 67. SAI master timing waveforms

1/fSCK
SAI_SCK_X
th(FS)
SAI_FS_X
(output) tv(FS) tv(SD_MT) th(SD_MT)
SAI_SD_X
Slot n Slot n+2
(transmit)
tsu(SD_MR) th(SD_MR)
SAI_SD_X Slot n
(receive)
MS32771V1
Figure 68. SAI slave timing waveforms

1/fSCK
SAI_SCK_X
tw(CKH_X) tw(CKL_X) th(FS)
SAI_FS_X
(input) tsu(FS) tv(SD_ST) th(SD_ST)
SAI_SD_X
Slot n Slot n+2
(transmit)
tsu(SD_SR) th(SD_SR)
SAI_SD_X Slot n
(receive)
MS32772V1
SD/SDIO MMC card host interface (SDMMC) characteristics

Unless otherwise specified, the parameters given in Table 115 and Table 116 for SDIO are
derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage summarized in Table 20: General operating conditions, with the following
configuration:
characteristics.
DS14258 Rev 1 237/275

244
Table 115. Dynamics characteristics: SD / MMC characteristics,

VDD = 2.7 to 3.6 V(1)
Clock frequency in data transfer

fPP - 0 - 130(2) MHz
mode
tW(CKL) Clock low time 8.5 9.5 -
fPP =52MHz ns
tW(CKH) Clock high time 8.5 9.5 -
CMD, D inputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(3)/DDR(3) mode
tISU Input setup time HS - 3 - -

tIH Input hold time HS - 1 - - ns
tIDW (4) Input valid window (variable window) - 4.5 - -
CMD, D outputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(3)/DDR(3) mode
tOV Output valid time HS - - 5 5.5

ns
tOH Output hold time HS - 3 - -
CMD, D inputs (referenced to CK) in SD default mode
tISUD Input setup time SD - 2.5 -

ns
tIHD Input hold time SD - 1.5 -
CMD, D outputs (referenced to CK) in SD default mode
tOVD Output valid default time SD - - 0.5 1

ns
tOHD Output hold default time SD - 0 - -
2. CL applied is 20 pF.
3. For SD 1.8V support, an external voltage converter is needed.
4. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.

VDD = 1.71V to 1.9V(1)
fPP Clock frequency in data transfer mode - 0 - 110(2) MHz

tW(CKL) Clock low time 8.5 9.5 -
fPP =52 MHz ns
tW(CKH) Clock high time 8.5 9.5 -
CMD, D inputs (referenced to CK) in eMMC mode
tISU Input setup time HS - 1.5 - -

tIH Input hold time HS - 1.5 - - ns
tIDW(3) Input valid window (variable window) - 4 - -
CMD, D outputs (referenced to CK) in eMMC mode
238/275 DS14258 Rev 1


VDD = 1.71V to 1.9V(1) (continued)
tOV Output valid time HS - - 5.5 6

ns
tOH Output hold time HS - 3 - -
2. CL = 20 pF.
3. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.
Figure 69. SDIO high-speed/eMMC timing
MSv72345V1
Figure 70. SD default speed timings
CK
tOV tOH
D, CMD output MSv69710V1
DS14258 Rev 1 239/275

244
Figure 71. DDR mode timings
D input Valid data Valid data
tISU tIH tISU tIH
tW(CKH)
CK
tW(CKL)
tOV tOV
tOH tOH
D output Valid data Valid data
MSv69158V1
Ethernet interface characteristics

Unless otherwise specified, the parameters given in Table 117, Table 118 and Table 119 for
SMI, RMII and MII are derived from tests performed under the ambient temperature,
frcc_c_ck frequency and VDD supply voltage conditions summarized in Table 20: General
operating conditions, with the following configuration:
characteristics:
Table 117. Dynamics characteristics: Ethernet MAC signals for SMI (1)
tMDC MDC cycle time( 2.5 MHz) 400 400 403

Td(MDIO) Write data valid time 0 0.5 1
ns
tsu(MDIO) Read data setup time 12.5 - -
th(MDIO) Read data hold time 0 - -
240/275 DS14258 Rev 1

Table 118. Dynamics characteristics: Ethernet MAC signals for RMII (1)
tsu(RXD) Receive data setup time 3 - -

tih(RXD) Receive data hold time 1 - -
tsu(CRS) Carrier sense setup time 2 - -
ns
tih(CRS) Carrier sense hold time 1 - -
td(TXEN) Transmit enable valid delay time 7.5 9.5 15
td(TXD) Transmit data valid delay time 7.5 10 15.5
Table 119. Dynamics characteristics: Ethernet MAC signals for MII (1)
tsu(RXD) Receive data setup time 3 - -

tih(RXD) Receive data hold time 1.5 - -
tsu(DV) Data valid setup time 2 - -
tih(DV) Data valid hold time 1 - -
ns
tsu(ER) Error setup time 3 - -
tih(ER) Error hold time 1 - -
td(TXEN) Transmit enable valid delay time 7.5 10 16
td(TXD) Transmit data valid delay time 8 10.5 16.5
Figure 72. Ethernet RMII timing diagram
RMII_REF_CLK
td(TXEN)
td(TXD)
RMII_TX_EN
RMII_TXD[1:0]
tsu(RXD) tih(RXD)
tsu(CRS) tih(CRS)
RMII_RXD[1:0]
RMII_CRS_DV
ai15667b
DS14258 Rev 1 241/275

244
Figure 73. Ethernet MII timing diagram
MII_RX_CLK
tsu(RXD) tih(RXD)
tsu(ER) tih(ER)
tsu(DV) tih(DV)
MII_RXD[3:0]
MII_RX_DV
MII_RX_ER
MII_TX_CLK
td(TXEN)
td(TXD)
MII_TX_EN
MII_TXD[3:0]
ai15668b
Figure 74. Ethernet SMI timing diagram

tMDC
ETH_MDC
td(MDIO)
ETH_MDIO(O)
tsu(MDIO) th(MDIO)
ETH_MDIO(I)
MS31384V1
JTAG/SWD interface characteristics

Unless otherwise specified, the parameters given in Table 120 and Table 121 for
JTAG/SWD are derived from tests performed under the ambient temperature, frcc_c_ck
frequency and VDD supply voltage summarized in Table 20: General operating conditions,
with the following configuration:
characteristics:
242/275 DS14258 Rev 1

Table 120. Dynamics JTAG characteristics

Fpp 2.7V <VDD< 3.6 V - - 50

TCK clock frequency
1/tc(TCK) 1.71 V < VDD < 3.6 V - - 45
MHz
tisu(TMS) TMS input setup time - 2 - -
tih(TMS) TMS input hold time - 1.5 - -
tisu(TDI) TDI input setup time - 1.5 - - -
tih(TDI) TDI input hold time - 1.5 - - -
2.7V <VDD< 3.6 V - 8 10 -
tov(TDO) TDO output valid time
1.71 <VDD< 3.6 V - 8 11 -
toh(TDO) TDO output hold time - 6.5 - - -
Table 121. Dynamics SWD characteristics

Fpp 2.7V <VDD< 3.6 V - - 80

SWCLK clock frequency MHz
1/tc(SWCLK) 1.71 <VDD< 3.6 V - - 71
tisu(SWDIO) SWDIO input setup time - 1.5 - - -
tih(SWDIO) SWDIO input hold time - 1.5 - - -
2.7V <VDD< 3.6 V - 10.5 12.5 -
tov(SWDIO) SWDIO output valid time
1.71 <VDD< 3.6 V - 10.5 14 -
toh(SWDIO) SWDIO output hold time - 8.5 - - -
Figure 75. JTAG timing diagram

tc(TCK)
TCK
tsu(TMS/TDI) th(TMS/TDI)
tw(TCKL) tw(TCKH)
TDI/TMS
tov(TDO) toh(TDO)
TDO
MSv40458V1
DS14258 Rev 1 243/275

244
Figure 76. SWD timing diagram
tc(SWCLK)
SWCLK
tsu(SWDIO) th(SWDIO) twSWCLKL) tw(SWCLKH)

SWDIO
(receive)
tov(SWDIO) toh(SWDIO)
SWDIO
(transmit)
MSv40459V1
244/275 DS14258 Rev 1

STM32H562xx and STM32H563xx Package information
6 Package information
In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
DS14258 Rev 1 245/275

270
Package information STM32H562xx and STM32H563xx
6.1 LQFP64 package information

This LQFP is 64-pin, 10 x 10 mm low-profile quad flat package.
Note: See list of notes in the notes section.
Figure 77. LQFP64 - Outline(15)

BOTTOM VIEW
2 1
(2)
R1
H
R2
B
B-
N
O
TI
C
SE
B GAUGE PLANE
D 1/4
0.25
(6)
S
B
L
4x N/4 TIPS
E 1/4 3
(L1)
aaa C A-B D (1) (11)
bbb H A-B D 4x
SECTION A-A
(13) (N – 4)x e
C
A
0.05
A2 A1 (12)
b
ddd C A-B D ccc C
D (4)
(5) (2) D1 (9) (11)
(10)
D (3) b WITH PLATING
N (4)
1 E 1/4 (11) (11)

2
3 c c1
(3) A (6) B (3) (5)
D 1/4 (2)
E1 E b1 BASE METAL
(11)
A A SECTION B-B
(Section A-A)
TOP VIEW 5W_LQFP64_ME_V1
246/275 DS14258 Rev 1

Table 122. LQFP64 - Mechanical data

millimeters inches(14)
Symbol
Min Typ Max Min Typ Max
A - - 1.60 - - 0.0630
A1(12) 0.05 - 0.15 0.0020 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0570
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0091
c(11) 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 12.00 BSC 0.4724 BSC
(2)(5)
D1 10.00 BSC 0.3937 BSC
E(4) 12.00 BSC 0.4724 BSC
(2)(5)
E1 10.00 BSC 0.3937 BSC
e 0.50 BSC 0.1970 BSC
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 REF 0.0394 REF
N(13) 64
θ 0° 3.5° 7° 0° 3.5° 7°
θ1 0° - - 0° - -
θ2 10° 12° 14° 10° 12° 14°
θ3 10° 12° 14° 10° 12° 14°
R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
(1)
aaa 0.20 0.0079
(1)
bbb 0.20 0.0079
(1)
ccc 0.08 0.0031
ddd(1) 0.08 0.0031
DS14258 Rev 1 247/275

270
Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.
Figure 78. LQFP64 - Footprint example
48 33
0.30
49 0.5 32
12.70
10.30
10.30
64 17
1.20
1 16
7.80
12.70
5W_LQFP64_FP_V2
1. Dimensions are expressed in millimeters.
248/275 DS14258 Rev 1

6.2 VFQFPN68 package information

This VFQFPN is a 68 pins, 8 x 8 mm, 0.4 mm pitch, very thin fine pitch quad flat package
Figure 79. VFQFPN68 - Outline

PIN 1 IDENTIFIER
LASER MARKING ddd C
D
A
A1
68 67 A2
1
2
E E
(2X) 0.10 C
SEATING
C PLANE
TOP VIEW SIDE VIEW

L
D2
E2
2
1
PIN 1 ID
C 0.30 X 45'
68 67 b
e
EXPOSED PAD AREA
BOTTOM VIEW B029_VFQFPN68_ME_V1
1. VFQFPN stands for Thermally Enhanced Very thin Fine pitch Quad Flat Packages No lead. Sawed
version. Very thin profile: 0.80 < A ≤ 1.00mm.
2. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other
feature of package body. Exact shape and size of this feature is optional.
DS14258 Rev 1 249/275

270
Table 123. VFQFPN68 - Mechanical data

Symbol
A 0.80 0.90 1.00 0.0315 0.0354 0.0394

A1 0 0.02 0.05 0 0.0008 0.0020
A3 - 0.20 - - 0.0008 -
b 0.15 0.20 0.25 0.0059 0.0079 0.0098
D 7.85 8.00 8.15 0.3091 0.3150 0.3209
D2 6.30 6.40 6.50 0.2480 0.2520 0.2559
E 7.85 8.00 8.15 0.3091 0.3150 0.3209
E2 6.30 6.40 6.50 0.2480 0.2520 0.2559
e - 0.40 - - 0.0157 -
L 0.40 0.50 0.60 0.0157 0.0197 0.0236
ddd - - 0.08 - - 0.0031
Figure 80. VFQFPN68 - Recommended footprint

8.30
7.00
6.65
0.15 6.40
6.65
7.00
8.30
6.40
0.25
0.82
0.65
0.40
B029_VFQFPN68_FP_V2
250/275 DS14258 Rev 1

6.3 WLCSP80 package information

This WLCSP is a 80 ball, 3.50 x 3.27 mm, 0.35 mm pitch, wafer level chip scale package.
Figure 81. WLCSP80 - Outline

F e1
G (DETAIL A)
(DETAIL B)
K e e
e
e2
DETAIL B
BACKSIDE CODE
BOTTOM VIEW
A
bbb C
A3 A2 SIDE VIEW
SIDE VIEW
DETAIL A
BUMP
D
A1
eee Z
E
b (80x)
ccc Z X Y
ddd Z
A1 Orientation SEATING
ref DETAIL A PLANE
4x aaa C ROTATED 90
TOP VIEW
B0D4_WLCSP80_ME_V1

2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
3. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
4. Bump position designation per JESD 95-1, SPP-010. The tolerance of position that controls the location of
the pattern of balls with respect to datums X and Y. For each ball there is a cylindrical tolerance zone ccc
perpendicular to datum Z and located on true position with respect to datums X and Y as defined by e. The
axis perpendicular to datum Z of each ball must lie within this tolerance zone.
DS14258 Rev 1 251/275

270
Table 124. WLCSP80 - Mechanical data

Symbol
A(2) - - 0.58 - - 0.228

A1 - 0.17 - - 0.0067 -
A2 - 0.38 - - 0.0150 -
(3)
A3 - 0.025 - - 0.0098 -
b 0.22 0.24 0.27 0.0087 0.0094 0.0106
D 3.47 3.50 3.52 0.1366 0.1378 0.1386
E 3.25 3.27 3.30 0.1279 0.1287 0.1299
e - 0.35 - - 0.138 -
e1 - 2.73 - - 0.1075 -
e2 - 2.45 - - 0.0964 -
F(4) - 0.384 - - 0.0151 -
G(4) - 0.484 - - 0.0190 -
H - 0.1025 - - 0.0040 -
aaa - - 0.10 - - 0.0039
bbb - - 0.10 - - 0.0039
(5)
ccc - - 0.10 - - 0.0039
(6)
ddd - - 0.05 - - 0.0020
eee - - 0.05 - - 0.0020
2. The maximum total package height is calculated by the RSS method (Root Sum Square) using nominal
and tolerances values of A1 and A2.
3. Back side coating. Nominal dimension is rounded to the 3rd decimal place resulting from process
capability.
4. Calculated dimensions are rounded to the 3rd decimal place
5. Bump position designation per JESD 95-1, SPP-010. The tolerance of position that controls the location of
the pattern of balls with respect to datums X and Y. For each ball there is a cylindrical tolerance zone ccc
perpendicular to datum Z and located on true position with respect to datums X and Y as defined by e. The
axis perpendicular to datum Z of each ball must lie within this tolerance zone.
6. The tolerance of position that controls the location of the balls within the matrix with respect to each other.
For each ball there is a cylindrical tolerance zone ddd perpendicular to datum Z and located on true
position as defined by e. The axis perpendicular to datum Z of each ball must lie within this tolerance zone.
Each tolerance zone ddd in the array is contained entirely in the respective zone ccc above. The axis of
each ball must lie simultaneously in both tolerance zones.
252/275 DS14258 Rev 1

Figure 82. WLCSP80 - Footprint example
Dpad
Dsm
BGA_WLCSP_FT_V1
Table 125. WLCSP80 - Example of PCB design rules

Dimension Values
Pitch 0.35 mm
Dpad 0.225 mm
Dsm 0.290 mm typ. (depends on soldermask registration tolerance)
Stencil opening 0.235 mm
Stencil thickness 0.080 mm

This LQFP is 100 lead, 14 x 14 mm low-profile quad flat package.
DS14258 Rev 1 253/275

270
ș2 ș
(2)
R1
H
R2
B
B-
N
O
(6)
TI
C
SE
D1/4 B GAUGE PLANE
S
E1/4
B ș
4x N/4 TIPS
ș L
4x (L1)
aaa C A-B D
bbb H A-B D (1) (11)
BOTTOM VIEW SECTION A-A
(N-4) x e (13)
C
A (9) (11)
0.05
ccc C b WITH PLATING
A2 A1 b aaa C A-BD
(12)
SIDE VIEW
D (4)
(11) c
(2) (5) D1 c1 (11)
D (3)
(10) (4)
N
b1 BASE METAL
1 (11)
2
3 E1/4 SECTION B-B
D1/4 (6) (2)

A B
(5)
E1 E
SECTION A-A
A A
TOP VIEW 1L_LQFP100_ME_V3

Symbol
A - 1.50 1.60 - 0.0590 0.0630

A1(12) 0.05 - 0.15 0.0019 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0570
254/275 DS14258 Rev 1

Table 126. LQFP100 - Mechanical data (continued)

Symbol
b(9)(11) 0.17 0.22 0.27 0.0067 0.0087 0.0106

b1(11) 0.17 0.20 0.23 0.0067 0.0079 0.0090
(11)
c 0.09 - 0.20 0.0035 - 0.0079
(11)
c1 0.09 - 0.16 0.0035 - 0.0063
D(4) 16.00 BSC 0.6299 BSC
(2)(5)
D1 14.00 BSC 0.5512 BSC
(4)
E 16.00 BSC 0.6299 BSC
E1(2)(5) 14.00 BSC 0.5512 BSC
e 0.50 BSC 0.0197 BSC
L 0.45 0.60 0.75 0.177 0.0236 0.0295
(1)(11)
L1 1.00 - 0.0394 -
(13)
N 100
θ 0° 3.5° 7° 0° 3.5° 7°
θ1 0° - - 0° - -
θ2 10° 12° 14° 10° 12° 14°
θ3 10° 12° 14° 10° 12° 14°

R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
(1)
aaa 0.20 0.0079
bbb(1) 0.20 0.0079
(1)
ccc 0.08 0.0031
ddd(1) 0.08 0.0031
DS14258 Rev 1 255/275

270
Notes:
as 0.15 mm.
from the lead tip.
body.

75 51
76 50
0.5
0.3
16.7 14.3
100 26
1.2
1 25
12.3
16.7
1L_LQFP100_FP_V1
256/275 DS14258 Rev 1


This LQFP is a 144-pin, 20 x 20 mm low-profile quad flat package.
BOTTOM VIEW
2 1
(2)
R1
H
R2
B
B-
N
O
TI
C
SE
(6) B GAUGE PLANE
0.25
D 1/4
S
B
L
3
E 1/4 (L1)
(1) (11)
4x N/4 TIPS
aaa C A-B D SECTION A-A
bbb H A-B D 4x
(N-4)x e
C
A
0.05 (12) ddd C A-B D
A2 A1 b ccc C
D (4)
D1 (2) (5)
(10) (3) D (9) (11)
N (4)
b WITH PLATING
1
2
3 E 1/4
(11) (11)
c c1
(6)
D 1/4 (2)
(3) A B (3) (5)
E1 E b1 BASE METAL
(11)
SECTION B-B
A A
(Section A-A)
TOP VIEW
1A_LQFP144_ME_V2
DS14258 Rev 1 257/275

270

Symbol
A - - 1.60 - - 0.0630
(12)
A1 0.05 - 0.15 0.0020 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0090
(11)
c 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 22.00 BSC 0.8661 BSC
(2)(5)
D1 20.00 BSC 0.7874 BSC
E(4) 22.00 BSC 0.8661 BSC
E1(2)(5) 20.00 BSC 0.7874 BSC
e 0.50 BSC 0.0197 BSC
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 REF 0.0394 REF
N(13) 144
θ 0° 3.5° 7° 0° 3.5° 7°
θ1 0° - - 0° - -
θ2 10° 12° 14° 10° 12° 14°
θ3 10° 12° 14° 10° 12° 14°

R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
aaa 0.20 0.0079
bbb 0.20 0.0079
ccc 0.08 0.0031
ddd 0.08 0.0031
258/275 DS14258 Rev 1

Notes:
as 0.15 mm.
from the lead tip.
body.
DS14258 Rev 1 259/275

270
108 73
1.35
109 0.35 72
0.50
19.90 17.85
22.60
144 37
1 36
19.90
22.60
1A_LQFP144_FP
260/275 DS14258 Rev 1

6.6 UFBGA169 package information

This UFBGA is a 169-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package.
Figure 87. UFBGA169 - Outline
Z Seating plane
A2 A4
ddd Z
A
A3 A1
b
SIDE VIEW A1 ball A1 ball
identifier index area X
E
E1
e F
A
F
D1 D
e
Y
N
13 1
BOTTOM VIEW Øb (169 balls) TOP VIEW

Ø eee M Z X Y
Ø fff M Z
A0YV_ME_V2
Table 128. UFBGA169 - Mechanical data

Symbol
Min. Typ. Max. Min. Typ. Max.
A 0.460 0.530 0.600 0.0181 0.0209 0.0236

A1 0.050 0.080 0.110 0.0020 0.0031 0.0043
A2 0.400 0.450 0.500 0.0157 0.0177 0.0197
A3 - 0.130 - - 0.0051 -
A4 0.270 0.320 0.370 0.0106 0.0126 0.0146
b 0.230 0.280 0.330 0.0091 0.0110 0.0130
D 6.950 7.000 7.050 0.2736 0.2756 0.2776
D1 5.950 6.000 6.050 0.2343 0.2362 0.2382
E 6.950 7.000 7.050 0.2736 0.2756 0.2776
E1 5.950 6.000 6.050 0.2343 0.2362 0.2382
e - 0.500 - - 0.0197 -
F 0.450 0.500 0.550 0.0177 0.0197 0.0217
DS14258 Rev 1 261/275

270
Table 128. UFBGA169 - Mechanical data (continued)

Symbol
ddd - - 0.100 - - 0.0039

eee - - 0.150 - - 0.0059
fff - - 0.050 - - 0.0020
Figure 88. UFBGA169 - Footprint example
Dpad
Dsm
BGA_WLCSP_FT_V1
Table 129. UFBGA169 - Example of PCB design rules (0.5 mm pitch BGA)
Dimension Values
Pitch 0.5 mm
Dpad 0.27 mm
0.35 mm typ. (depends on the soldermask
Dsm
registration tolerance)
Solder paste 0.27 mm aperture diameter.
Note: Non-solder mask defined (NSMD) pads are recommended.

Note: 4 to 6 mils solder paste screen printing process.
262/275 DS14258 Rev 1


This LQFP is a 176-pin, 24 x 24 mm, 0.5 mm pitch, low profile quad flat package.
ș2 ș1
(2) R1
H R2
B(See SECTION B-B)

(6) GAUGE PLANE
0.25
D1/4
S
B ș
L
E1/4 ș
4x N/4 TIPS 4x (L1)
(1) (11)
bbb H A-B D
aaa C A-B D
BOTTOM VIEW SECTION A-A
A2 0.05
(N-4) x e
C
A
A1 (12) ddd C A-BD ccc C
b
SIDE VIEW
D (4)
(2) (5) D1
D (9) (11)
(10) N
(4) b WITH PLATING
E1/4
(11) c c1 (11)
D1/4 (6) (5)

A B (2)
E1 E b1 BASE METAL
(11)
SECTION A-A
A A
SECTION B-B
TOP VIEW 1T_LQFP176_ME_V2
DS14258 Rev 1 263/275

270

Symbol
A - - 1.600 - - 0.0630
A1(12) 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
(9)(11)
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
(11)
b1 0.170 0.200 0.230 0.0067 0.0079 0.0091
c(11) 0.090 - 0.200 0.0035 - 0.0079
(11)
c1 0.090 - 0.160 0.0035 - 0.063
(4)
D 26.000 1.0236
(2)(5)
D1 24.000 0.9449
E(4) 26.000 0.0197
(2)(5)
E1 24.000 0.9449
e 0.500 0.1970
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1(1)(11) 1 0.0394 REF
N(13) 176
θ 0° 3.5° 7° 0° 3.5° 7°
θ1 0° - - 0° - -
θ2 10° 12° 14° 10° 12° 14°
θ3 10° 12° 14° 10° 12° 14°
R1 0.080 - - 0.0031 - -
R2 0.080 - 0.200 0.0031 - 0.0079
S 0.200 - - 0.0079 - -
(1)
aaa 0.200 0.0079
(1)
bbb 0.200 0.0079
(1)
ccc 0.080 0.0031
ddd(1) 0.080 0.0031
264/275 DS14258 Rev 1

Notes:
as 0.15 mm.
from the lead tip.
body.
DS14258 Rev 1 265/275

270
1.2
176 133
1 0.5 132
0.3
26.7
21.8
44 89
45 88
1.2
21.8
26.7
1T_FP_V1
266/275 DS14258 Rev 1

6.8 UFBGA(176+25) package information

This UFBGA is a 176+25-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array
package
Figure 91. UFBGA(176+25) - Outline

Seating plane
C A4
ddd C
A
A2 A3 b A1
A1 ball A
A1 ball index E
identifier area
E1
e F
A
F
D1 D
e
B
R
15 1
Øb (176 + 25 balls)
BOTTOM VIEW TOP VIEW
Ø eee M C A B
Ø fff M C
A0E7_ME_V10
Table 131. UFBGA(176+25) - Mechanical data

Symbol
A - - 0.600 - - 0.0236
A1 0.050 0.080 0.110 0.0020 0.0031 0.0043
A2 - 0.450 - - 0.0177 -
A3 - 0.130 - - 0.0051 -
A4 - 0.320 - - 0.0126 -
b 0.240 0.290 0.340 0.0094 0.0114 0.0134
D 9.850 10.000 10.150 0.3878 0.3937 0.3996
D1 - 9.100 - - 0.3583 -
E 9.850 10.000 10.150 0.3878 0.3937 0.3996
E1 - 9.100 - - 0.3583 -
e - 0.650 - - 0.0256 -
F - 0.450 - - 0.0177 -
ddd - - 0.080 - - 0.0031
DS14258 Rev 1 267/275

270
Table 131. UFBGA(176+25) - Mechanical data (continued)

Symbol
eee - - 0.150 - - 0.0059

fff - - 0.050 - - 0.0020
Figure 92. UFBGA(176+25) - Footprint example
Dpad
Dsm
BGA_WLCSP_FT_V1
Table 132. UFBGA(176+25) - Example of PCB design rules (0.65 mm pitch BGA)
Dimension Values
Pitch 0.65 mm
Dpad 0.300 mm
0.400 mm typ. (depends on the soldermask
Dsm
registration tolerance)
Stencil opening 0.300 mm
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.100 mm
268/275 DS14258 Rev 1

6.9 Package thermal characteristics

The maximum chip-junction temperature, TJmax, in degrees Celsius, may be calculated
using the following equation:
TJmax = TAmax + (PDmax × ΘJA)
Where:
• TAmax is the maximum ambient temperature in °C,
• ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
• PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax),
• PINTmax is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/Omax represents the maximum power dissipation on output pins where:
• PI/Omax = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Table 133. Package thermal characteristics

Symbol Definition Parameter Value Unit
LQFP64 (10 x 10 mm) 48.1

VFQFPN68 (8 x 8 mm) 24.2
WLCSP80 (3.50 X 3.27 mm) 47.3
Thermal resistance LQFP100 (14 x 14 mm) 35.9

ΘJA °C/W
junction-ambient LQFP144 (20 x 20 mm) 37.5
LQFP176 (24 x 24 mm) 38.3
UFBGA169 (7 x 7 mm) 40.6
UFBGA176 (10 x 10 mm) 39.1
LQFP64 (10 x 10 mm) 24.1
VFQFPN68 (8 x 8 mm) 9.4
WLCSP80 (3.50 X 3.27 mm) 23.0

ΘJB °C/W
junction-board LQFP144 (20 x 20 mm) 26.3
LQFP176 (24 x 24 mm) 28.3
UFBGA169 (7 x 7 mm) 26.4
UFBGA176 (10 x 10 mm) 27.0
DS14258 Rev 1 269/275

270
Table 133. Package thermal characteristics (continued)

Symbol Definition Parameter Value Unit
LQFP64 (10 x 10 mm) 10.3

VFQFPN68 (8 x 8 mm) 10.8
WLCSP80 (3.50 X 3.27 mm) 2.3

ΘJC °C/W
junction-case LQFP144 (20 x 20 mm) 8.6
LQFP176 (24 x 24 mm) 9.1
UFBGA169 (7 x 7 mm) 11.2
UFBGA176 (10 x 10 mm) 10.9
6.9.1 Reference documents

• JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
• For information on thermal management, refer to application note “Thermal
management guidelines for STM32 32-bit Arm Cortex MCUs applications” (AN5036)
available from www.st.com.
270/275 DS14258 Rev 1

STM32H562xx and STM32H563xx Ordering information
7 Ordering information
Example: STM32 H 563 V I T 6 Q TR

Device family
STM32 = Arm based 32-bit microcontroller
Product type
H = high performance
Device subfamily
563 = STM32H563xx devices

562 = STM32H562xx devices without Ethernet
Pin count
R = 64 pins / 68 pins
M = 80 pins
V = 100 pins
Z = 144 pins
A = 169 balls
I = 176 pins
Flash memory size
G = 1 Mbyte
I = 2 Mbytes
Package
V = VFQFPN
T = LQFP
I = UFBGA (7 x 7 mm)
K= UFBGA (10 x 10)
Y = WLCSP
Temperature range
6 = Temperature range, -40 to 85 °C (130 °C junction)
3 = Industrial temperature range, -40 to 125 °C (130 °C junction)
Dedicated pinout
Q = Dedicated pinout supporting SMPS step-down converter
Packing
TR = tape and reel
xxx = programmed parts
DS14258 Rev 1 271/275

272
Ordering information STM32H562xx and STM32H563xx
For a list of available options (such as speed or package) or for further information on any
aspect of this device, contact the nearest ST sales office.
272/275 DS14258 Rev 1

STM32H562xx and STM32H563xx Important security notice
8 Important security notice
The STMicroelectronics group of companies (ST) places a high value on product security,
which is why the ST product(s) identified in this documentation may be certified by various
security certification bodies and/or may implement our own security measures as set forth
herein. However, no level of security certification and/or built-in security measures can
guarantee that ST products are resistant to all forms of attacks. As such, it is the
responsibility of each of ST's customers to determine if the level of security provided in an
ST product meets the customer needs both in relation to the ST product alone, as well as
when combined with other components and/or software for the customer end product or
application. In particular, take note that:
• ST products may have been certified by one or more security certification bodies, such
as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation
standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST
product(s) referenced herein have received security certification along with the level
and current status of such certification, either visit the relevant certification standards
website or go to the relevant product page on www.st.com for the most up to date
information. As the status and/or level of security certification for an ST product can
change from time to time, customers should re-check security certification status/level
as needed. If an ST product is not shown to be certified under a particular security
standard, customers should not assume it is certified.
• Certification bodies have the right to evaluate, grant and revoke security certification in
relation to ST products. These certification bodies are therefore independently
responsible for granting or revoking security certification for an ST product, and ST
does not take any responsibility for mistakes, evaluations, assessments, testing, or
other activity carried out by the certification body with respect to any ST product.
• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open
standard technologies which may be used in conjunction with an ST product are based
on standards which were not developed by ST. ST does not take responsibility for any
flaws in such cryptographic algorithms or open technologies or for any methods which
have been or may be developed to bypass, decrypt or crack such algorithms or
technologies.
• While robust security testing may be done, no level of certification can absolutely
guarantee protections against all attacks, including, for example, against advanced
attacks which have not been tested for, against new or unidentified forms of attack, or
against any form of attack when using an ST product outside of its specification or
intended use, or in conjunction with other components or software which are used by
customer to create their end product or application. ST is not responsible for resistance
against such attacks. As such, regardless of the incorporated security features and/or
any information or support that may be provided by ST, each customer is solely
responsible for determining if the level of attacks tested for meets their needs, both in
relation to the ST product alone and when incorporated into a customer end product or
application.
• All security features of ST products (inclusive of any hardware, software,
documentation, and the like), including but not limited to any enhanced security
features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT
PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the
applicable written and signed contract terms specifically provide otherwise.
DS14258 Rev 1 273/275

273
Revision history STM32H562xx and STM32H563xx
9 Revision history
Table 134. Document revision history

Date Revision Changes
06-Mar-2023 1 Initial release
274/275 DS14258 Rev 1

IMPORTANT NOTICE – READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgment.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product
or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2023 STMicroelectronics – All rights reserved
DS14258 Rev 1 275/275

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STM32H562xx and STM32H563xx

Arm® Cortex®-M33 32-bit MCU+TrusZone® + FPU, 375 DMIPS

Core LQFP64 (10 x 10 mm) VFQFPN68 (8 x 8 mm)

DMIPS (Dhrystone 2.1)

Memories General-purpose inputs/outputs

March 2023 DS14258 Rev 1 1/275

• Secure firmware upgrade support with • One I3C interface

Up to 34x communication interfaces ECOPACK2 compliant packages

STM32H562AG, STM32H562AI, STM32H562IG, STM32H562II, STM32H562RG,

STM32H563AG, STM32H563AI, STM32H563IG, STM32H563II, STM32H563MI,

2/275 DS14258 Rev 1

DS14258 Rev 1 3/275

3.14 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 35

4/275 DS14258 Rev 1

3.32 Real-time clock (RTC), tamper and backup registers . . . . . . . . . . . . . . . 50

4 Pinout, pin description and alternate function . . . . . . . . . . . . . . . . . . . 65

5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

DS14258 Rev 1 5/275

5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

6/275 DS14258 Rev 1

6.2 VFQFPN68 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

8 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

DS14258 Rev 1 7/275

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

8/275 DS14258 Rev 1

Table 43. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

DS14258 Rev 1 9/275

Table 95. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

10/275 DS14258 Rev 1

Figure 1. STM32H562xx and STM32H563xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

DS14258 Rev 1 11/275

Figure 47. OCTOSPI timing diagram - DTR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

12/275 DS14258 Rev 1

For information on the Arm®(a) Cortex®-M33 core, refer to the Cortex®-M33

DS14258 Rev 1 13/275

The STM32H562xx and STM32H563xx devices are a high-performance microcontrollers

14/275 DS14258 Rev 1

Table 2. STM32H56xxx features and peripheral counts

Flash memory (Mbytes) Up to 2 Mbytes

DS14258 Rev 1 15/275

Table 2. STM32H56xxx features and peripheral counts (continued)

SPI / I2S 4/3 5/3 6/3

Communication USB yes

Number of I/Os down to 1.08 V 0/ 10/ 10/ 10/ 10/

16/275 DS14258 Rev 1

Table 2. STM32H56xxx features and peripheral counts (continued)

DS14258 Rev 1 17/275

Figure 1. STM32H562xx and STM32H563xx block diagram

AHB2 250 MHz

AHB3 250 MHz

PI[7:0] GPIO port I CORDIC TIM3 32b 4 channels, ETR as AF

3 compl. channels smcard RX, TX, CK, CTS,

APB1 250 MHz (max)

3 compl. channels UART4 RX, TX, CTS, RTS as AF

2 channels, TIM15 16b smcard RX, TX, CK, CTS,

1 compl. channel, BKIN as AF USART6 irDA RTS as AF