Archer Semiconductor Reference Guide 1988
Archer Semiconductor Reference Guide 1988
Archer Semiconductor Reference Guide 1988
2
minal arrangement of the original device. If these ar- observe this precaution can result in damage in the
rangements are different, and the original transistor is device. Transistor substitution in tuned circuits will
a "plug in" type, bend the leads of the ARCHER device often require realignment of the circuit.
so that the base, emitter and collector leads will mate
with the original transistor leads. Trim the leads after SILICON VS SELENIUM RECTIFIERS
soldering in place. Silicon rectifiers are inherently more efficient than
CAUTION: Be particularly careful about "pin-cir- selenium or other metallic-oxide type rectifiers. When
cle" and "in-line" lead break-out type transistors. a silicon rectifier is used to replace a selenium rectifier
Often one manufacturer makes a type with "in-line" in the power supply of a typical line-operated radio or
leads, while another may make the same type with TV receiver, the silicon rectifier will frequently deliver
"pin-circle" configuration. Doublecheck both the orig- higher DC output voltage than the original device.
inal and the replacement device before soldering or In some cases, this higher supply voltage may im-
plugging in transistors. prove the performance of the equipment. However, in
BOTTOM VIEW many other cases, it may immediately or eventually
damage filter capacitors and/or other components
PIN-CIRCLE IN-LINE which were designed to withstand only the voltage
delivered by the original selenium rectifier. To prevent
such damage, it is generally advisable to insert a power
lr (max) Vf (max)
Catalog PIV (min) If @ Vr @ If Case
Number v A p.A v Style BRIDGE RECTIFIERS
276-1101 50 1.000 10 1.6 0041 Catalog PIV (min) If (max) Case
276-1102 200 1.000 10 1.6 0041 Number v A Style
5
BIPOLAR TRANSISTORS
Direct Power Dlss. fr Iceo
Catalog Commercial @25 oc Typlcel Veao Veeo Veao le Ia @Vee@ le at max Case
Number Equivalent Mat. Appll. Polarity Free Air MHz V V V Max Max V mA Yea Style
NOTE: All ratings given are for 25°C except where otherwise noted . #-Archer-Pack :j:With heat sink
MATERIAL:
$-Silicon ; G-Germanium
APPLICATION:
5-Switch P-Power amp/switch • -High Gain Darlington LL-Low Level
G.P .-General Purpose RF/IF-RF/IF frequency UHF-Ultrahigh frequency SW-TVSweep
USEFUL INFORMATION
ASSUME LOW / RL
"•• COMPARED TO rc
\
INPUT
'• I
OUTPUT
'• OUTPUT
'
'~ rl r -:'
Parameters of Common-Base Circuit Parameters of Common - Collector Circuit Parameters of Common-Emitter Circuit
Input Impedance Input Impedance Z;n = ({3 + 1)ZL Input Impedance Z;n = htertr
where , Load Impedance ZL = RL in parallel with input
Load Impedance ZL = RL in parallel with input ZL is RL in parallel with RE . impedance of next stage .
impedance of following stage .
Rs ~~c
Current Gain A;= "' = ,--h Output Impedance Zout = "/3+1 Current Gain A;= Ai;=hte
Power Gain
6
SPECIAL TRANSISTOR {FET)
~
ABSOLUTE MAXIMUM RATINGS
(T A = 25 o C unless otherwise noted)
Drain-Source Voltage .... .... ......... ........ . ......· ........... 25 V
Drain-Gate Voltage ............................................. 25 V
Gate-Source Voltage ........................................... . 25 V
Gate Current ........... . ................. . ... . .............. 10 rnA
Total Device Dissipation ....... ... ............... . ............ 310 mW
Operating Junction Temperature . ....... . ..... ........ ........ . .. 125 °C
Storage Temperature Range . . ....... . ....... . . . .... .. .. - 65 to + 150°C
0
DRAIN SOURCE GATE
FEATURES
• Fast switching
• Low drive current
• Ease of paralleling
• No second breakdown
• Excellent temperature stability
APPLICATIONS
• Switching power supplies
• Motor controls
• Inverters
• Choppers
• Audio amplifiers
• High energy pulse circuits
7
SPECIAL TRANSISTORS (FET)
IRF511 21s-2o12
TEST CIRCUITS
v, e,
Vos
PULSE
GENERATOR
;-------- --~
''
E1
'---- i =~ 5011
0.10
HIGH FREO
SHUNT
Figure 1-Ciamped Inductive Test Circuit and Waveform Figure 2-Switching Time Test Circuit
TYPICAL CHARACTERISTICS
!z
5.6
4.8 v 05 "' 7V
~
.!z
5.6
4.8
25'c,
lllV
~
.!z
5.6
4.8 ~ v v 05 -7V
-55'~
VJ ::! ~v
~ 4.0 ~ 4.0 4.0
a: /} a:
~ !L'
B a.2 5 1l
z
;;: .4
6V
z
:ca:
3.2
2.4
1(/ z
:
3.2
2.4
l.oiilll v 6V
.,__ ~
a:
Q
.6 Q 1.8
) Q
.6
.§ .§ 5v l--
~
.§ 5V
.8 0.8 .8
~
4V 4V
0 0 oil'
10 20 30 40 50 0 2 4 6 810 0 1.0 2.0 3.0 4.0 5.0
V 05, DRAIN-TO-SOURCE VOLTAGE- VOLTS v0 5 , GATE-TO-SOURCE VOLTAGE- VOLTS v 05, DRAIN-TO-SOURCE VOLTAGE-VOLTS
w 1.25 4.0 5
~ "'~ 3.6 1-- t-- ~JtS IPUL~E r1esr
0 v 05 = 25V
> us :- p ! 3.2 0
v
iii
~ 2. 8
~ 2.4 ~55'C- r- ./
v ;:
g
TJ= 5
v
v
/ Q
~ 1.
2.0
• //
25°C
125°C 0
.......
v
..
0
~ 1. 2//, / z
""""' VGs=10V
5 ~ 0. 8y ~
Q
o.5c""'""' 'o i 1.5~ - -
~
5
- 40 40 80 120
0.4
0 l 0
- 40
..*
0 0.8 1.6 2.4 3.2 4.0 4.8 5.6 6.4 7.2 8.0 40 80 120
> TJ. JUNCTION TEMPERATURE-°C 10, DRAIN CURRENT- AMPERES TJ• JUNCTION TEMPERATURE-°C
8
SPECIAL TRANSISTORS (FET)
em
frequency figure of merit. It achieves a low noise figure and good power gain with
low crossmodulation and intermodulation.
TYPICAL CHARACTERISTICS
COMMON SOURCE
10 10 • 1.0
v08 • 15
Yos • o ~E
+ g,,
I
i,; v ~ ./ J! b 0 . . (x 10~/
/
ct 1.0 ~
;...-~
~
E
I 1.0
....
/ ~b,, ..
~ 0. 1
/"" /.~.
w ;; z
0
z ..!. ~
,.cg
t--1>,,.
~ "cz
...."
c /
.... / Yos= 1SV
Yas"" o
..
8 V 08 • 15V
Yos .. o
~
! 1V0.
100 200 500 1000
o.1
100 200 500 1000
!;
0 0.01
100 200 500 1000
FREQUENCY f - MHz FREQUENCY f - MHz FREQUENCY f - MHz
COMMON GATE
100 0 i 1.0
IE
v08
Yos • o
• 1SV
- - g,,
~
I
i
I
/
i.!,.1.
b...lx10)./
/
l,;.
: 10 0
+btl v w
~ 0.1 / v ....v
~
0 .i!i
z r--....
g,. .:!;
lI "cz
.. v
0
c
/
~ ... v
./
..
0
0
Vos ""' 15Y
~ ~ Vas = o
!
1
1000
0.1
200 500 1000
" o.o1
0
100 200 500 100 100 200 500 1000
FREQUENCY f - MHz FREQUENCY f - MHz FREQUENCY t-MHz
9
SPECIAL TRANSISTORS (FEn
GENERAL DESCRIPTION
This TMOS FET is designed for high-voltage, high-speed switching applica·
tions such as line drivers, relay drivers, CMOS logic, microprocessor or TTL- PIN CONNECTION
to-high voltage interface and high voltage display drivers.
FEATURES
• Fast Switching Speed-ton t 0 ff =
6.0 ns Typ =
• Low On-Resistance-5.0 Ohms Max
• Low Drive Requirement, Vcs(thJ = 3.0 V Max
• Inherent Current Sharing Capability Permits Easy Paralleling of Many
PIN 1. DRAIN
Devices 2. GATE
3. SOURCE
TYPICAL APPLICATIONS
+ 25 v - t..u-
v,.
90%
Output 10%
Inverted
Input V1n
(V1n Amplitude 10 Volts)
- - - w i dPulse
th_ _ _
Vos = Vos /
..--
w 1.6 ~ 1.6 9.0V
10 = 1.0mA
~ ~
~
JL
-r--
8.0V
--
0
6 1.2 112
5
~
I'
!
> 0.4
0.8
0
-50 50
-- "z
~
~
t
0.8
0.4
Ill
II/
U/_.,
,_
/If
Ill 7.0V
6.0V
s.ov-
•.ov -
·100 10 20 30
T), JUNCTION TEMPERATURE V05, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Vas = 10V
VGs = OV
~ 1.6
...,..--
--
8()
~ ~
a.ov- 0::
r-
i
~
~
/ sw 1\
60
1.2 j;!
~ F- g \.\
7.0V
-
~ 0.8 40
;.....-
~ ~ <
"u
~
-
.. - 1---
j 0.4 ~ :::::::-- s.ov
20
..........
c~
~~ eM,
.---
1.0 ~0
4.0
' 10 20 30
V05, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
50
c.,
60
10
SPECIAL PURPOSE DEVICES (VARISTOR)
ERZ-C14DK201 U
276-570
GENERAL DESCRIPTION
ZNR varistors are zinc oxide resistors whose resistance changes as a func- PIN CONNECTION
tion of the applied voltage. The ZNR has a bilateral and symmetrical V-I char-
acteristic curve and can therefore be used in circuits in place of back-to-hack
zener diodes. This gives your circuit clamping protection in either direction.
The ZNR provides a highly reliable and economical way to protect against
repeated high voltage transients and surges such as those produced by light-
ning, switching surges and noise spikes.
FEATURES
• Excellent clamping voltage characteristic and fast response time ( < 50 nsec.)
when subjected to impulse surges. Eliminates the discharge lag that is indic-
ative of gap-type arrestors.
• Bilateral and symmetrical V-I characteristic curve. The ZNR can, therefore,
be used both in AC and in DC circuits, for protection of either positive or
negative transients.
ABSOLUTE MAXIMUM RATING
Varistor Voltage (V-I@ lmA DD) (185V 225V) ..... . . .. .............. . 200V
Applied Voltage ACRMs) . . . ...... . ...... .... .. .. . . .. . . ......... . .. . .. 130V
(DC) ......... ... ... . ........ . . . ............ . ....... 170V
Clamping Voltage@ Test Current (8 X 20 1-1sec) Vc(V) ..... .. . . .. . . . ... . . 340V
IP (A) (276-568) ... . . . ... . lOOA
IP (A) (276-570) ....... . . .. 50A
Peak Pulse Current (8 X 20 1-1s) 1 Time (276-568) ....... . .. . .. ... . . . ... 6500A
(276-570) ... . . .. . . . . ........ . .. 4500A
Energy (Jl (276-568) .... . ..... . .. . ....... . ....... . .. . .................. 70J VOLTAGE~
(276-570) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35J
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Power (276-568) . . . ... .. . . . ... .. . .... . ............. . . .. .. . .. . ..... . .. lW V-1 Characteristic Curve
(276-570) .... . .................. ... . . . . ..... .. . ... . . . ... .... 0.60W
Capacitance (PF@ 1kHz) (276-568) . . .. . . . .. . .. .. . .. . . . . . .. . .. . ..... 2000PF
(276-570) . . . ... . . ....... . .. . . .. _. .... . . . . . lOOOPF
Operating Ambient Temperature . ... . .. .. . . . .. . .. . . . . .. . . . . .. -40° + 85 ° C
Storage Temperature . . .. . ..... .... . . .......... . ............ -40° +125°C
...
TYPICAL APPLICATIONS ~
0
EQUIPMENT
>
PROTECTED
-H- TIME~
11
SPECIAL PURPOSE DEVICES (SCR) (TRIAC)
276-1000 THYRISTORS
276-1020
276-1067
GENERAL DESCRIPTION
Thyristors and their trigger devices can take numerous forms. but they share these qharacteristics:
• They are "open circuits." capable of withstanding rated voltage until triggered.
• They become low-impedance current paths when triggered. and remain so. even after the trigger source is removed. until current
through that path stops. or is reduced below a minimum "holding" level. ·
SCRs TRIACs
Silicon-Controlled Rectifiers (SCRs) are Thyristors intended Triacs are bidirectional Thyristors. in which a single trigger
to switch load currents in one direction only. making them use- source turns the device on for load current in either direction.
ful for DC and ha lf-wave AC applications as well as full-wave Because they do not require a bridge rectifier in order to handle
app lications. in which bidirectional current is routed in one di- full-wave AC. Triacs are useful in AC power applications that
rection through the SCR via a bridge rectifier. require full source power control capability to be applied to the
load.
OPTOELECTRONIC INDEX BY
FUNCTION
12
OPTOELECTRONIC CLEO)
LED INDICATORS
Max DC
Direct Peak Forward Reverse Forward Max Pwr
Catalog Commercial Wave Length Voltage Voltage Current Diss Fig.
Number Equivalent nM Color VF (V) VR (V) IF (MA) Po (MW) No.
276·018 PR5534S 700 RED 2.5 4 100 75 4
276-021 SLP-2368 565 YELLOW 2.8 3 30 70 5
276-022 SLP-2368 565 GREEN 2.8 3 30 70 5
276·025 R9-56 RED/GREEN 2.0 3.0 10 7
276-026 650 RED 3 50 100 2
276-033 TLR-147 700 RED 2.1 4 35 100 1
276-037 SLP-2358 565 GREEN 2.8 3 30 70 4
276-041 700 RED 1.75 3 70 140 3
276-065 369HHD 697 RED 1.8 5 20 75 8
276-066A SLA-591LT3 660 RED 2.5 (@20 MA) 4 50 100 9
276-068 700 RED 1.9 30 6
276-069 560 GREEN 2.1 30 6
276-088 SLP-888A 660 RED 2.2 (@2 MA) 3 20 70 10
G
CATHODE ANODE
(jJ
ANODE CATHODE
FIGURE 4
8
ANODE CATHODE
FIGURE 5
CATHODE ANODE
FIGURE 6
Subminiature LED with diffused lens. Th is This is a frame type solid state LED with a This is a subminiature LED indicator with
device has solid state reliability and is diffused lens. polished chrome reflective holder.
compatible with most TTL and transistor
circuits.
(1)
(3)
(2) ANODE
ANODE
I CATHODE
LONG LEAD IS CATHODE
FIGURE 7
This is a three terminal LED. The light col· FIGURES FIGURE9
or radiates " red " when terminals 2 and 3 This is a jumbo red LED. It consists of two This is a high-brightness red LED. It is
are used. Green light radiates when ter· LED elements connected cathode to cath· many times brighter than ordinary LEOs,
minals 1 and 2 are used. ode in a 10mm diameter housing. yet still runs cool.
13
OPTOELECTRONIC (EMITTER)
d)
compatible with silicon sensors and has a high power output with a zoo beam
w
angle.
FEATURES 0.0 1
1~$ 10~-tS 100p.S 1m$
• High power output With a zoo beam angle tw - PULSE WIDTH
16
TA= 25" C
""\
0.9
14
J
./
;t
E / >
t:: 0.8
"'~ I \
TA = - 40"C
v ~
e
12
/ ~
0.7
rT \
/ 25"C /
v ::>
0
10
Po/ z
0.6
/ Vt:-- /
a:
w
~...
8
v ~
~
:
o.5
0 .4
3
2
v .,...-::v 75" C
....c
z
6
4 / ~/
w
>
i= 0.3
:l
I 1\
'/.:; 1:;:/
w 0. 2
1
o/ ~
a: 2
0~
/./ a:
0.1
0
'
0 10 20 30 40 50 60 70 80 90 100 20 40 60 80 100 20" 10" 0" 10" 20"
IF-FORWA RD CURRENT - m A IF- FORWARD CURRENT - mA 8 -ANGULAR DISPLACEMENT
'•='•·;c; I r;
100
[/ fos•c I
/I/ I/ 40"C
/J I
0
1.0 1.1
/ w
1.2 1.3
VF- FORWARD VOLTAGE-V
1.4 1.5 1.8
Forward Conduction
Characteristics
14
OPTOELECTRONIC (DISPLAY) (LED)
B1001R
276-081 HIGH EFFICIENCY RED BAR GRAPH DISPLAY -
GENERAL DESCRIPTION
The B1001R is a 10 segment bar graph display with separate anodes and
cathodes for each light segment. The packages are end stackable. PIN CONNECTION
TOP VIEW
FEATURES
• Large segments, closely spaced BAR 1 ANODE BAR 1 CATHODE
• End st ackable
• Fast switching, excellent for multiplexing BAR 2 ANODE BAR 2 CATHODE
ELECTRO-OPTICAL CHARACTERISTICS
Forward Voltage ................... . .... . ...... .. . . .. . .... . . . . .. . . . 1.6 V
Peak emission wavelength ................. .. ...... . ... ... .. .... . . .. 655nm
F336GD
276-030 BLINKING LED
F336HD
276-036
FEATURES
• Built-in IC chip, flashes LED on and off to attract attention
• Pulse rate l .OHZ
• Tl 3/4 size
• Larger full flood radiating area
• l-inch leads
• 1 .2mcd @ VF = 3.0V
• IC compatible
15
OPTOELECTRONIC (DRIVER)
TRIAC
INFRARED EMITTING DIODE MAXIMUM RATINGS CATHODE DRIVER SUBSTRATE
5 (DO NOT CONNECT)
Reverse Voltage ...... .. . . ..... ................... .. ............. 3.0 volts
Forward Current-Continuous ........ . ..... . ..... . ... . . . ... .. .. ... . 50 rnA
Total Power Dissipation@ TA = 25•c .. .............. ... .. . ....... 100 mW
NC
....____ _,
'---+--4.,- ~:::~INAL
<
E
1800 I
MOC3010
120V
60Hz .ffi
::
1l
~ -400
Resistive Load Z-800~~~~~~-L~~~•
0 -12 -8 -4 12
ON-STATE VOLTAGE VrM - V
~ 1.1 r---t-'"'"-1=-+---+-+--+--1
::;
~ 0.9 r---+--l-+---+"""---io---+--1
• 1800 a:
0
z 0.7f--+-l-+---+-+--+~
MOC3010 C1
o.s'---L.-....I_....L.___j__ _J_-L--'
-40 -20 20 40 60 80 100
AMBIENT TEMPERATURE TA- oc
16
OPTOELECTRONIC (DISPLAY)
APPLICATIONS
• Instruments
• Test Equipment
• Office Machines
• Computers
• Automobiles
• Clocks/Radios
• Communication Equipment
• Calculators
• CB Radios
PIN CONNECTION
GENERAL DESCRIPTION 12 11 10 9 •
The 276-064 is a 0.79" diameter hi-efficiency Red LED. This device is ideal for
a variety of applications where a large bright source is required.
17
OPTOELECTRONIC (DISPLAY) (PHOTOCELL)
FEATURES
• Fits 14 pin DIP socket
• Excellent character appearance-continuous uniform segments; wide viewing
angle; high contrast
• IC compatible-1.6 V per segment
• Standard 0.3" DIP lead configuration; PC board or standard socket mountable
• Both left and right decimal points
APPLICATIONS
• Electronic calculators • Frequency counters
• TVs • Digital clocks
• Radios
RADIANT CHARACTERISTICS (IF=20mA) TA=25•c
ALTERNATE
Luminous Intensity .... . ..... ..... ..... . ............ . .. . ... ... .... 250 mcd COMMON ANODE CONNECTION
PIN FUNCTION
Wavelength (Peak) . . ..................................... ..... ... 655 nM PIN FUNCTION
1 CATHODE a 1 NO PIN
2 CATHODE t 2 ANODE
3 ANODE 3 CATHODE· f
ABSOLUTE MAXIMUM RATINGS 4
5
NO PIN
NO PIN
4
5
CATHODE· g
CATHODE·e
Power Dissipation T A=25•c . . .. . .. .. . . .. . .. .. . ...... .. .. . .. . . ... . .. 400 mW 6
7
CATHODE dp
CATHODE e '
7
CATHODE· d
NO PIN
Average Forward Current/Segment or Decimal Pt. TA = 25°C . . ........ .. 25 rnA 8
9
CATHODE d
NO CONNECTION '
9
NO PIN
ANODE
CATHODE c CATHODE-dp
Peak Forward Current/Segment or Decimal Pt. T A=12°C 10
11 CATHODE g
10
11 CATHODE-c
(Pulse Duration 500f'S) . .... ............... . ................... . ... 150 rnA 12
13
NO PIN
CATHODE b
12
13
CATHODE-b
CATHODE-a
Reverse Voltage per Segment or Decimal Pt. .... . . .. .... . .... . ....... . . . 6 V 14 ANODE 14 NO PIN
APPLICATIONS
•
•
•
•
Night light
Light control
Burglar alarm
Relay
0
SPECIFICATIONS
• Shape ... . . ...... .... ... . . .. .. . ... ..... .. . ... ... .... . ... . . . ..... Round
• Sensitive Area .... .. ..... .. . . ....... . ....... .. . ... ........ . .. .07 sq. in.
• Weight . . . . . .... . . . ...................... . .... . . . .. . ... . ..... 1.56 gms.
• Resistance at 1 Ftc (2870oK) . .... ....... . . .. ...... .... .. . 1.7k Ohms . 40%
• Typical Resistance 100 Ftc (2870°K) .. . . . ... . . .... . .. .... .. .. . . . 100 Ohms
• Resistance Dark Minimum (1 Minute) . ... ....... . .... . . . . .. . 0.5 Megohms
18
OPTOELECTRONIC . (LED) (PHOTOTRANSISTOR)
'"'"'moo~"'~
applied current. the LED will emit red or green light while an AC voltage results
in yellow light. The chips used in the XC-5491 are brightness matched so that the
light output is uniform. This eliminates the necessity for the special drive circuits
previously required with tri-state lamps.
These lamps provide the designer with the capability of efficiently displaying
three functions with one indicator. This reduces the number of front panel
indicators and simplifies design.
FEATURES
•
•
•
3 States-red. green. and yellow
Equal brightness in all three colors
Popular T 1'V.. size package
~
GREEN
am,. ill
• Wire wrappable leads
SHORT LONG 'fl
ABSOLUTE MAXIMUM RATINGS
Forward Current ................... ... ............................ 25 rnA
Peak Reverse Voltage .......... . ................. . .... . .. ............. 5V
Power Dissipation .. .............................................. 100 mW
LEAD
Red Cathode
Green Anode
LEAD
Red Anode
Green Cathode J
0~ I
Operating Temperature Range ... ... .................... . .... -55 to +85°C 1.000
MIN
Lead Solder Temperature ............ .. .... . ........................ 260°C
o.o•• I
----..;..
Jo.,oL
--r-
e
The TIL414 is an NPN silicon phototransistor in A T-1 3/4 style case. It pro-
vides high speed and high photosensitivity. suitable for IR switching applications. BOTTOM VIEW
CATHOOE
ABSOLUTE MAXIMUM RATINGS NOICATOR
Collector-Emitter Voltage ............ ... .. ........................... 50 V
Emitter-Collector Voltage .................. . .... .. ............... . .. . . 7 V EMITTER OLLECTOR
TYPICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS (Typical)
Dark Current (V CE = 30 V) ..... . ................................ . .... 25 nA
Light Current (VeE= 5 V•E. = 20mW/cm2) ............................ 7 rnA
Collector-Emitter Saturation ...................... . ........... ....... 0.4 V
Rise Time ......................................... . ..... . ........... 8 ,.,s
Fall Time ................................... .. ...................... 6 ,.,s
30
IRAADIANCE
50
e_ -
70
mWicm2
.
Collector-Emitter Saturation Voltage
vs lrradlance
19
OPTOELECTRONIC (EMITTER)(SOLAR CELL)
FEATURES
Infrared-Emitting Diode
Reverse Voltage ... . . . ..... .... .... . ... . ... . . . . ... . . . . .. . ..... . ....... 2V
Continuous Forward Current . ... ....... . ............... . ...... . .. . .. 40mA
Radiant Power Output . ... .. . . . . . . .. . . . . . .. . ... .. .. . . . ... .. .. 0.5mW
Wavelength at Peak Emission ...... .. . . ... .... .. ... ... . ........ . ... 915mm
TYPICAL CHARACTERISTICS
0.25
0.20
0.15
-\
0.10
1\
0.05
\
0
100 200 300 400 500
\ 600
VOLTAGE- mV
Current vs Voltage
20
DIGITAL (CMOS)
FEATURES
• Quiescent current = 0.5 nA typ/pkg @ 5 Vdc
• Noise immunity= 45% ofV00 typical v..
• Diode protection on all inputs
• Supply voltage range = 3.0 Vdc to 16 Vdc
• Single supply operation-positive or negative
• High fanout > 50
• Input impedance = 1012 ohms typical
• Logic swing independent of fanout
Voo
14
INPUT
l r J
20ns l- 20ns
J~%~"',"4:;-----,\I.. ______ :: 0
INPUT
t---<>--r---<> OUTPUT IPlHr _ _ __
INVERTING
I/ VoH
4001 OUTPUT
1--'-,;_--f--'
J 't--1!-_ ,-TL-H_ _ _ Vol
tPHL F VoH
Vss
•An unused Inputs of OR, NOR gates must be connected to v 55.
NON·INVERTING
OUTPUT
Jl\_[ ITHL
Vol
TYPICAL APPLICATIONS
+ 9V
Voo
811
SPEAKER
1MII 100K
21
DIGITAL (CMOS)
FEATURES
• Quiescent current= 0.5 nA typ/pkg@ 5 Vdc
• Noise immunity = 45% of VDD typical
• Supply voltage range = 3.0 Vdc to 16 Vdc
• Double diode protection on all inputs
Yoo
INPUT
-,~ ~
r~:•• J
r--
[20ns Yoo
14 ~0~·¥ I\___ ov
INPUT
IPLH~----
.., 1----<>-----<0 OUTPUT
INVERTING
~-ITLH
OUTPUT
VoL
J
NON· INVERTING
OUTPUT
Vss
•An unused Inputs of AND, NAND gates must be connected to v 00.
TYPICAL APPLICATIONS
TO PIN 3
OF 550240
CLOCK
TO PINS 1 & 2
OF 850240
Display flashes once per second when E is high. ClOCK
This produces bagpipe and other unusual sounds.
Adjust R1 to vary interruption rate.
22
DIGITAL (CMOS)
FEATURES
• Static operation
• Quiescent current = 2.0 nA/package typical @ 5 Vdc v,
• Noise immunity = 45% of V00 typical
• Diode protection on all inputs
• Supply voltage range = 3.0 Vdc to 16 Vdc
• Single supply operation
• Toggle rate= 4 MHz typical @ 5 Vdc
• Logic edge-clocked flip-flop design-logic state is retained indefinitely with
clock level either high or low; information is transferred to the output only on TRUTH TABLE
the positive-going edge of the clock pulse.
• Capable of driving two-low-power TTL loads, one low-power schottky TTL INPUTS OUTPUTS
load or two HTL loads over the rated temperature range. Clockt Data Reset Set Q Q
- L L L L H
ABSOLUTE MAXIMUM RATINGS - H L L H L
(Voltages referenced to V88) - X L L
DC Supply Voltage ... . ....... .. .. .. ... .. ....... , .. ....... - 0.5to + 16 Vdc
Input Voltage. All Inputs .. .. .. . .... ... ... . .. . .. .. .. . . - 0.5 to V00 + 0.5 Vdc
X
X
X
X
H
L
L
H H L
NoLT:'J'
DC Current Drain per Pin ....... . ..... . . . ... . .... . . .. . .. .. .. ..... 10 mAde X X H H H H
Operating Temperature Range ... . .... .. ..... . .... .. ... .. .... - 40 to + 85°C X = Don't Care H = High Level
Storage Temperature Range ............... . ............... .. - 65 to + 150°C L = Low Level t = Level Change
TYPICAL APPLICATIONS SYNC TIMING WAVEFORMS
1 2 nth .
ll-20ns \[20ns
~"AJ cO
Voo
Q Q DATA(O) __j,f~%
..J ~
10%
Vss
c
-1'
lj
~-lo<>tH) -~ ~- 20ns V
90% DO
CLOCK
CLOCK (C) SO%10%
J··~
Vss
n-Stage Shift Register
•'"
0 at-- - - , Q
OUTPUT(Q)
'"'"It ...: '·"r
So%
VoH
_xo~~ fL--- DO
OUTPUT(Q)
___/ov 70
\______ VoL
23
DIGITAL (CMOS)
FEATURES
• Fully static operation
• DC clock input circuit allows slow rise times
•
•
Carry out output for cascading
12 MHz (typical) operation @ Voo = 10 Vdc ...
• Quiescent current = 5.0 nA/package typical @ 5 Vdc
• Supply voltage range = 3.0 Vdc to 16 Vdc TRUTH TABLE (Positive Logic)
• Capable of driving two low-power TTL loads, one low-power schottky TTL
load or two HTL loads over the rated temperature range Clock Decode
Clock Enable
Reset Output= n
ABSOLUTE MAXIMUM RATINGS L X L n
(Voltages referenced to Vss) X H L n
DC Supply Voltage . . ... .. . ...... .. . .. .. ............. .. .. . -0.5 to + 16 Vdc X X H QL
Input Voltage, All Inputs ........ ......... . ..... . .. .... - 0.5 to V00 + 0.5 Vdc ~ L L n+ 1
DC Current Drain per Pin . . ....... . .. ......... . .... . .... . ... . . . .. 10 mAde "'-- X L n
X _r- L
Operating Temperature Range . . ............ . .. . ... ... .. . . .. . - 40 to + 85•C n
Storage Temperature Range ..... . .... . . . . . . ... .. . .. . . . .... . . - 65 to + 15o·c 1 """\..._ L n + 1
X = Don't Care If n <5 Carry = "H",
Otherwise = "L"
L = Low Level H = High Level
TYPICAL APPLICATIONS
4017 4017
15 14 13 13 14
16 15
CLOCK . TON
24
DIGITAL (CMOS)
version using only one supply voltage, Vee- The input-signal high level (VIH) NC NC
can exceed the Vee supply voltage for logic-level conversions. Two TTL/DTL
loads can be driven when the devices are used as CMOS-to-TTL/DTL convert-
ers £Vee= 5.0 V, VoL ::5 0.4 V, IoL~ 3.2 rnA). Note that pin 16 is not connected
internally on this device; consequently connections to this terminal will not
affect circuit operation.
FEATURES
• High source and sink currents
• High-to-low level converter
• Quiescent current = 2.0 nA/package typical @ 5 Vdc
• Supply voltage range = 3.0 Vdc to 16 Vdc
~...
Vss
~·.. - Yss
- YoH- Voo
Yos- Vos-Y
- OL
~ 18 ~ 0 ~ 180
~ ~ 5~ !..#'
I ..ffi I
.f,L ~
1 Yos=SV Vas=15V-=
g I
1
~ -1 0
r/ I
w I
-- -ssoc
- +125°C
a:
a:
B
1~~--- a:
a:
120
....r
"~ 10
- 20
v "0 80
1..; 10V
I
v
..~ L
w
0
> I
I
§
g
- 30
f-. +- --- /
I/1SV
-I MAXIMUM=
"'z
iii
.. 40
L
/
r-
CAUTION:MAXIMUM
~ACKiGe...oiSSPATiON
I
~
0
~ IV"
"~ : I I v V- - _lc.!!;"!!.iTJ-l!L MU~T Bl OBiER~ED
I - 4 SV
10 15 18 5 -SO -10 -8 -6 -4 -2
"0 ~
0~
0 2 4 6 8 10
~ Y1N,INPUT VOLTAGE -VOLTS ~ 1v
05,DRAIN-TO-SOURCE VOLTAGE-VOLTS
.9 V05, DRAIN-TO-SOURCE VOLTAGE-VOLTS
TYPICAL APPLICATIONS
Voo
R2
Voo
C1 R1
IN <>---j I-->'-M.-_._--J
0.01JlF 1 M!! 7
25
DIGITAL (CMOS)
FEATURES
• Wide supply voltage range-3V to 15V
• High noise immunity-0.45 V00 typ
• Wide range of digital and analog switching-±7.5 VPEAK
• "ON" resistance for 15V operation-BOO typ 8 IN/OUT
~--+--
Modulator/Demodulator
Commutating switch
• Digital signal switching/multiplexing LOGIC DIAGRAM
• CMOS logic implementation 114 OF 4066
• ·Analog-to-digital/digital-to-analog conversion
• Digital control of frequency. impedance. phase. and analog-signal gain
ABSOLUTE MAXIMUM RATINGS OUT/IN
TYPICAL APPLICATIONS
o YouT
Input Voltage
26
DIGITAL (CMOS)
PIN CONNECTION
GENERAL DESCRIPTION
The UM3482A is a mask-ROM-programmed multi-instrument melody gener-
ator, implemented in the CMOS technology. It is designed to play the melody
according to the previously programmed information and· is programmed with
12 songs with 3 instrument sounds, the piano, the organ and the mandolin.
The UM3482A will play the following songs: AMERICAN PATROL, RAB-
BITS, OH, MY DARLING CLEMENTINE, BUTTERFLY, LONDON BRIDGE
IS FALLING DOWN, ROW, ROW, ROW YOUR BOAT, ARE YOU SLEEPING,
HAPPY BIRTHDAY, JOY SYMPHONY , HOME SWEET HOME,
WIEGENLIED, and MELODY ON PURPLE BAMBOO.
The device also includes a pre-amplifier which provides simple interface to
the driver circuit.
FEATURES APPLICATIONS
• Powered by a 1.5V battery • Toys
• Low stand-by current • Doorbells
• 512 notes memory, up to 16 songs • Music Boxes
• Play all the songs repeatedly or auto stop • Melody/Clock Timers
• Play one song only, repeatedly or auto stop • Telephones
• Every song starts from the first note
• Any song can be present
• 3 timbres-piano, organ and mandolin
• 5 tempos available through mask setting
• On chip envelope modulator and pre-amplifier
~~~------~--=-----------------------------,
sw,
MT1
----, I UM3482A
I
I
I
I
I
OP1
OP2
I
I
I
---, I
I
I
I r - - ---...1
I I
CEXS LP SL I I
I I
I I
I I
I I
I I
I I
I I
I I
I I
I
I
I
I
I
L______ _________ _______ _______ ____J
27
DIGITAL (CMOS)
UM3482
TYPICAL APPLICATIONS
276-1797
16 12 11 10 9
v., MT1 OP2 OP1 MTO
UM3482A PIN
TSP CE LP SL liS NC NAMES FUNCTION
1 2 3 4 5 6
1(TSP) Output flag of melody
i SW1
R,
180 K
auto stop
In normal operating
this pin should be
open
Melody door bell 2(CE) Chip enable if
connected to Voo
Chip disable if
connected to Vss
3(LP) The melody plays only
one song if this pin
connected to Voo
16
v., The melody plays all
songs if this pin
TSP CE LP NC ENV v,
1 2 3 6 7 8 connected to Vss
4(SL) A positive going edge
c, R, applied to this pin the
4.7uf 180K
v,. melody will change to
the next song
5(AS) The melody will be
repeated if this pin
Low cost applications connected to Von
The melody will be
v, auto stop if this pin
connected to Vss
6(NC) No connection
C1
47pF 7(ENV) Envelope circuit
12 11 10 terminal
UM3482A
8(Vssl Negative supply
power
9(MTO) Modulated tone signal
output
10(0P1) Pre-amplifier output 1
11(0P2) Pre-amplifier outout 2
12(MT1) Modulated tone signal
input to the pre~
~~~------------_,
SW1
amplifier
13(0SC3)
Pin 13-15 can be
connected as an RC
14 (OSC2) oscillator
External oscillating
signal can be input to
Pin 15
15(0SC1)
16(Vool Positive oower suoolv
28
DIGITAL (MEMORY)
used. The HYB4164 uses single transistor dynamic storage cells and dynamic
control circuitry to achieve high speed at very low power dissipation. Multi- NC Vss
plexed address inputs permit the HYB4164 to be packaged in an industry
01 CAS
standard 16-pin dual-in-line package.
System oriented features include single power supply with ±10% tolerance, We DO
on-chip address and data latches which eliminate the need for interface regis-
ters and fully TTL compatible inputs and outputs, including clocks. RAS Ae
FUNCTIONAL DESCRIPTIONS
Addressing (A0 - A1)
For selecting one of the 65536 memory cells, a total of 16 address bits are
required. First 8 row-address bits are setup on pins Ao through A7 and latched
onto the row address latches by the Row Address Strobe (RAS). Then the 8
column-address bits are set-up on pins A0 through A 7 and latched onto the col-
umn address latches by the Column Address Strobe (CAS). All input addresses
must be stable on or shortly after the falling edge ofRAS and CAS respectively.
CAS is internally gated by RAS to permit triggering of column address latches
as soon as the Row Address Hold Time (tRAHl specification has been satisfied
and the address inputs have been changed from row-address to column-
address.
It should be noted that RAS is similar to a chip enable in that it activates the
sense amplifiers as well as the row decoder. CAS is used as a chip-select acti-
vating the column decoder and the input and output buffers.
29
DIGITAL (MEMORY)
HYB4164 21e-2506
iiAs-----l
·-
Current Consumption During Po-r
Up <Vee Rlsetlme 10,..s)
Ao
A,
A,
DUMMY CELLS
32K
MEMORY ARRAY
Vee
t :
:1 VI '
~~~~ [J tjJ
Aa
256 DO
SENSE REFRESH AMPS
A,
As
...
32K
MEMORY ARRAY
I
-·
0 100 200 300 400 500j.LS
A, DUMMY CELLS
The read or write mode is selected with the WE input. A logic high (VIH) on
WE dictates read mode; logic low (V 1d dictates write mode. The data input is
t 0
I
/
2
disabled when the read mode is selected. When WE goes low prior to CAS,
data output (DO) will remain in the high-impedance state for the entire cycle
permitting common I/0 operation. 5
-·
4 MHz
set-up and hold times referenced to this signal.
Power ON
lcc 3 (AVERAGE) vs. CYCLE RATE
An initial pause of 200 f.LS is required after power-up followed by a minimum Vcc=S.SV
of eight (8) initialization cycles (any combination of cycles containing a RAS RiS ONLY REFRESH CYCLE
mATA=25°C
clock such as RAS-only refresh) prior to normal operation. The current 25
requirement of the HYB4164 during power on is, however, dependent upon
the input levels 'RAS, CAS and the rise time of Vee. as shown in the (Current
Consumption During Power Up) diagram. t 2
0
-·
write or read-modify-write cycle, the output will follow the sequence for the 4 MHz
read cycle.
30
DIGITAL (MEMORY)
HYB4164 276-2506
0
-40 -20 0 20 40 60 80 100°C
-r
lcc2
ADDRESSES VIH
t '
r--... 1"'--.
vll
-....I'
2 1'-....
1
DO
Read Cycle 0
-40 -20 0 20 40 60 80 100°C
-T
v," lcAC
ADDRESSES
r 2
1. 1
1\
2
1.1
\
1.0
~ 1.0
1\
~ I'.. 1\
.9 0. 9
Dl
1'\
0. 8 o.8
3.5 4.5 5.5 6V 3.5 5.5 6V
DO VoH - - - - - - - - - O P E N - - - - - - - - - - -
-----. vee
31
DIGITAL (MEMORY)
HYB4164 276-2so6
v,"
ADDRESSES Read-Write/Read-Modify-Write Cycle
v,"
W.
v"
VoH
DO
VoL
v,H
Dl
v"
RAS
v,"----~
-IRAS
----J~f.--------- ... 3 "RAS-ONLY" REFRESH CYCLE
NOTE CAS= V1H; WE= DON'T CARE
VoH
DO --------OPEN---------
v,H
CAS
v,L.
v,"
ADDRESSES Hidden Refresh
DO
32
DIGITAL (MEMORY)
HYB4164 276-2so6
33
DIGITAL (MEMORY)
HYB4164 2re-2506
[)o-Ro
A3 R1 R255 R255
C255 co
A7
EXTERNAL INTERNAL
ROW [)o-R2 ROW
ADDRESS ADDRESS
AS R3 (PIN 5) AO RAs' (PIN 4)
A4 R4 (PIN 6) A2
DATA STORED=Di
WE (PIN3)
A2 RS (PIN 7)A1 Dl (PIN 2)
A1 R6 (PIN 8) Vee
AD R7 (PIN 9) A7 Vss (PIN 16)
(PIN 10) AS ffi(PIN15)
DATA STORED=DI
2D--::
A6 (PIN 11)A4 00 (PIN 14)
(PIN 12) A3 A6 (PIN 13)
A3------------------------------~~----------
A7------------------------------------------ C2 INTERNAL
EXTERNAL AS----------------------------------------------- C3 , COLUMN
;g~~~S~ A4----------------------------------------------- C4 ADDRESS RO RO
C255 co
A2--------------------------------------------- cs
A1------------------------------------------ C6
AO--------------------------------------------- C7 Internal Topology
INTERNAL DATA POLARITY
DATA STORED= Dl EllAo (ROW)
NOTE: The logic symbol ~exclusive nor~ Is used
solely to Indicate the Jogic function.
Topology Description
The evaluation and incoming testing of RAMs normally requires a description
of the internal topology of the device in order to check for "worst case"
pattern.
34
DIGITAL (MEMORY)
The MSM2764RS is manufactured using the N channel double silicon gate A12
MOS technology. NC
A7
A6 A6
FEATURES
• + 5V single power supply Ag
..
As
• 8192 words X 8 bits configuration
A11
• Access time: MAX 250ns
• Powei; consumption: A3 CiE
MAX 525 mW (during operation)
MAX 184 mW (during stand-by) A10
....,_____ Vee
..,.__ Vpp
. . . _ _ . GND
Ao A1 - - - - - - - - - A 12
35
DIGITAL (MEMORY)
GENERAL DESCRIPTION
The 4256 is a high-speed, 262,144-bit dynamic random-access memory, PIN CONNECTION
organized as 262,144 words of one bit each. It employs state-of-the-art SMOS
(scaled MOS) N-channel double-level polysilicon/polycide gate technology for
very high performance combined with low cost and improved reliability.
This device features maximum RAS access times of 150ns. Typical power
dissipation is as low as 275 mW operating and 12.5 mW standby.
New SMOS technology permits operation from a single 5-V supply, reducing
system power supply and decoupling requirements, and easing board layout.
Inn peaks are 125 rnA typical, and - 1-V input voltage undershoot can be toler-
ated, minimizing system noise considerations.
All inputs and outputs, including clocks, are compatible with Series 74 TTL.
All address and data-in lines are latched on chip to simplify system design.
Data out is unlatched to allow greater system flexibility.
FEATURES
• 262,144 X 1 organization
• Single 5 V supply
TRUTH TABLE
• Access time row address 150ns (Max.)
PIN
• Access time column address 75ns (Max.)
NAMES FUNCTION
• Read or write cycle 260ns (Min.)
• Long refresh period 4ms (Max.) AO-A8 Address Inputs
• Low refresh overhead time CAS Column-Address
• On-chip substitute bias generator Strobe
• All inputs, outputs, and clocks fully TTL compatible
• . RAS-only refresh mode D Data In
• Hidden refresh mode _Q Data Out
• CAS-before-RAS refresh mode RAS Row-Address Strobe
Von 5-V Supply
ABSOLUTE MAXIMUM RATINGS Vss Ground
Voltage range for any pin including Von supply (see Note 1) .. . . . . - 1 V to 7 V w Write Enable
Short circuit output current ... . .. . . . ..... . . .. . . ..... . .. . .. . . . .... . . 50 rnA
Power dissipation . . . .. .. . ... ... . . ... . ..... . .... . . . . ... . .. . . . . . .. . . . . 1 W
Operating free-air temperature range ... ... . . . . ... . .. . . ... .. . .. . 0°C to 70°C
Storage temperature range ... . ......... . .. . .. . . . ..... . .... - 65°C to 150°C
NOTES: 1. All voltage values are with respect to V55•
BLOCK DIAGRAM
! !
~~l~J~~~-~-~~=T-IM=ING~·=·~·J~NTR-
OL -~~~
J2K A RRAY
R
O
W
DECODE 32K ARRAY
A6 --+1----~
AI ---+-----~
256 SEN SE AMP S
32K ARRAY
ROW
DECODE
256 SENSE AMPS
32 K AR RAY
1"1
rl-C_O.!:_~M_N_J
As ------+--~i_~R~o~
w~}-'--------------------~
36
DIGITAL (MEMORY)
refresh
A refresh operation must be performed at least once every four milliseconds
to retain data. This can be achieved by strobing each of the 256 rows (AO-A7).
A normal read or write cycle will refresh all bits in each row that is selected. A
RAS-only operation can be used by holding CAS at the high (inactive) level,
thus conserving power as the output buffer remains in the high-impedance
state.
CAS-before-RAS refresh
The CAS-before-RAS refresh is utilized by bringing CAS low earlier than
RAS (see parameter tcRL) and holding it low after RAS falls (see parameter
tcLRd· For successive CAS-before-RAS refresh cycles, CAS can remain low
while cycling RAS. The external address is ignored and the refresh address is
generated internally.
hidden refresh
Hidden refresh may be performed while maintaining valid data at the output
pin. This is accomplished by holding CAS at V1L after a read operation and
cycling RAS after a specified precharge period, similar to a "RAS-only"
refresh cycle. The external address is also ignored during the hidden refresh
cycles.
page mode
Page-mode operation allows effectively faster memory access by keeping the
same row address and strobing random column addresses onto the chip. Thus,
the time required to setup and strobe sequential row addresses for the same
page is eliminated. The maximum number of columns that can be addressed is
determined by tw(RL)• the maximum RAS low pulse duration. ·
power-up
To achieve proper device operation, an initial pause of 200 /J-S is required
after power up followed by a minimum of eight initialization cycles.
37
DIGITAL (MEMORY)
~ r--VIH
\_____/ VIL
\ _ VIH
VIL
AD-A7
0----------------------------------------H•z-------------------------------------------VOH
VOL
VIH
VIL
VIH
VIL
VIH
VIL
'h(RHrd)
VIH
VIL
VOH
DATA
VOL
VOH
Q --------------- Hl-z-------------------..,VOL
38
DIGITAL (TTL)
A B OUT A B OUT
OUT l l H OUT
l l l
OUT
H H l H l
H l H H l l
H H l H H H
v.. 7400
Vee
1/• 7400
Vee
Vee
A
A
B
OUT OUT OUT
A B OUT 0 OUT
Vee
v. 7400
A
39
DIGITAL (TTL)
7404
276-1802
HEX INVERTER
GENERAL DESCRIPTION PIN CONNECTION
This device employs TTL logic to achieve high speed at moderate power dis-
sipatiorr. This hex in:verter provides the basic functions used in the implementa-
tion of digita'l integrated circuit systems. TOP VIEW
For b~st noise immunity and switching speed, unused inputs should not be left AI YS AS Y5 A4 Y4
floating, but should be held between 2.4 V and the absolute maximum input
voltage.
Two possible ways of handling unused inputs are:
(1] Connect unused inputs to Vee· For all multi-emitter t:onventional TTL inputs,
A 1 to 10K ohm !':ur.rent limiting series resistor is recommended, to protect
against Vee trai)slents that exceed 5.5 V.
(2] Connect the unused input to the output of an unused gate that is forced high.
Vee
Vee
270!.1
4.7K
IN 8!1
SPEAKER
4.7K
Output follows switch position. Allows one signal to control two or more Inputs.
This circuit steers the Input bit to the output selected by the address.
1-of-2 Demultiplexer
40
DIGITAL (TTL)
voltage.
Two possible ways at handling unused inputs are:
(1) Connect unused inputs to Vee. For all multi-emitter conventional TTL inputs,
a 1 to lOK ohm current limiting series resistor is recommended, to protect
against Vee transients that exoeed 5.5 V.
(2) Connect the unused input to the output of an unused gate that is forced high.
TRUTH TABLE
TYPICAL APPLICATIONS I Y=AB I
Vee
A A
c c
Vee Vee
A 8 OUT
A
OUT L L H A c
L H H A C D OUT
H L H
H H L H H H
X X L
Vee Vee
A
8
Vee
OUT
A c
A 8 OUT 0
L L H
OUT L H L
IN E OUT
H L L
H H L L L L
L H L
H L L A C 0 OUT
H H H
H H H l
X X X H
E - ENABLE
41
DIGITAL (TTL)
GENERAL DESCRIPTION
This versatile binary-coded-decimal 7-segment display driver fulfills a wide
variety of requirements for most a ctive high [common cathode) and active low
[common a node) light emitting diodes [LED) or lamp displays. It fully decodes a
PIN CONNECTION
4-bit BCD input into a number from 0 through 9 in the standard 7-segment
TOP VIEW
display format, and BCD numbers above 9 into unique patterns that verify
operation. All circuits operate off of a single 5.0V supply. The output will with- Vee
stand 15 Volts at a maximum leakage current of 250~ . 12 11 10 9
J'"
15 14 13
FEATURES
• Lamp-test input
• Leading trailing zero suppression (RBI and RBO)
• Blanking input that may be used to modulate lamp intensity or inhibit output
• -TTL and DTL compatible
• Input clamping diodes
• Open collector outputs drive indicators directly
TRUTH TABLE
DECIMAL INPUTS OUTPUTS
OR BI/ RBOt NOTE
FUNCTION LT RBI D c B A a b c d e f g
0 H H L L L L H L L L L L L H
1 H X L L L H H H L L H H H H
2 H X L L H L H L L H L L H L
3 H X L L H H H L L L L H H L
4 H X L H L L H H L L H H L L
5 H X L H L H H L H L L H L L
6 H X L H H L H H H L L L L L
7 H X L H H H H L L L H H H H
8 H X H L L L H L L L L L L L 1
9 H X H L L H H L L L H H L L
10 H X H L H L H H H H L L H L
11 H X H L H H H H H L L H H L
12 H X H H L L H H L H H H L L
13 H X H H L H H L H H L H L L
14 H X H H H L H H H H L L L L
15 H X H H H H H H H H H H H H
BI X X X X X X L H H H HH H H 2
RBI H L L L L L L H H H HH H H 3
LT L X X X X X LH L L L L L L 4
H = H1gh Level. L = Low Level. X = Irrelevant
Notes: 1. The blanking input (BI) must be open or held at a high logic level when output functions 0 thru 15 are desired.
The ripple-blanking input (RBI) must be open or high , if blanking of a decimal zero is not desired.
2. When a low logic level is applied directly to the blanking input (BI), all segment outputs are H regardless of the
level of any other input.
3. When ripple-blanking input (RBI) and inputs A, B, C, and Dare at a low level with the lamp-test input high, all
segment outputs go H and the ripple-blanking output (RBO) goes to a low level (response condition).
4. When the blanking input/ripple blanking output (BI/RBO) is open or held high and a low is applied to the lamp
test input, all segment outputs are L.
t Bl/RBO is w ire-AND logic serving as blanking input (BI) and/or ripple-blanking output (RBO).
~I -
I I 1_1 I I
I I I I I I_ I_
10 11 12 13 14 15
42
DIGITAL (TTL)
7447 276-1805
2.4K BK
NOMINAL NOMINAL
811R81-------'
TYPICAL APPLICATIONS
Vee
t5 f,. R3
13
R1~---4--, D D 330!1
1Mil
.f14 11
• 12
R4
330!1
R5
c c
• 2 11 330!1
R2
555
----. 7490 7447
10
R6
330!1
1K
---. 8
9 1
8
9
R7
330!1
RB
6 15 330!1
A A
I
12 7 R9
~
r
14 330!1
C1. O.H OOp F
43
DIGITAL (TTL)
GENERAL DESCRIPTION
This monolithic BCD counter contains four master-slave flip-flops and addi-
tional gating to provide a divide-by-two counter and a three-stage binary counter
for which the count cycle length is divide-by-five. PIN CONNECTION
This counter has a gated zero reset and gated set-to-nine inputs for use in BCD INPUT
TOP VIEW
FEATURES
• Low power consumption 1 2 3 6 7
• High count rates ... typically 50MHz INPUT R0(1) R0(2)
8
R9(1) R9(2)
rL I"
K K K at-<c-
8 H L H H
nl 9
L =Low Level
H H L L
H = High Level
Notes:
(A) Output QA is connected to input B for
BCD count.
6 7 1 2 3 (B) Output Qo is connected to input A for bi-
A9(1) R9(2) INPUT 8 R0(1) R0(2) quinary count.
44
INTERFACE (DRIVER)
FEATURES
• Cur rent Limited Output
±10 MA typ
• Power-Off Source Impedance
300 Ohms min
• Simple Slew Rate Control with External Capacitor
• Flexible Operating Supply Range
INTERNAL CIRCUIT
Vee 1 4 0 - - - - - T - - - - - - - - , - - - r - - - - ,
(% of Circuit Shown)
PINS 4, 9, 12 OR 2 8.2K
INPUT o---f4---f
INPUTo---f+-4
PINS 5, 10, 13
70
OUTPUT
t--~+---t-'\M.---oPINS 6, 8, 11 OR 3
300
3.6K
GNO~~
10K
7K 70
v•• ,o----~--+----~--~-~
TYPICAL CHARACTERISTICS
~ +6.0
Vcc=Yee
- ·•v"" "...0 +6.0
I I r-
~ +3.0 5 +3.0
I I
E9.S
!::; .:--Vee -Vee
r~-
0
- =±6V
0
"'
~
>
~ -3.or- Yo JK -3.0 .
"~ -6.
of- I
0
:z:
-6.0
0 - 9.
I I I """
en -9.0 I I
~ -1 ~0 0.2I I I I
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
~ -12
los
- 55 0 +25 + 75 + 125
Yin• I NPUT VOLTAGE (VOLTS) T, TEMPERATURE (° C)
Figure 1 -Slew Rate vs Capacitance Figure 3-Transfer Characteristics Figure 4-Short-Circuit Output Current
for lsc = 10mA vs Power-Supply Voltage vs Temperature
45
L
INTERFACE (DRIVER)
M C 1488 216-2s2o
·~~k+=+=+1
+20
<i" ~ 4~
.§. +1 :~
+1
3KO LOAD LINE c.- Vee I !-....
~ +8.0 r- t-- ~~ 12 r- 914-+--1-+-IP'-...t-r-....-t-1
ffi !E_ 10 1- ..__j.(3;_.v3<:;....._+---t-+,_H
~ +4.0
a:
::0 0 \. 1-"" ~~ S.O r--- 6 3K
~ -~ £l. c(
'":; s.o 1-
8 31(
1 '23\M.·-+---t-+-H
1-!1~
e - 4. 0 1.9V los
._: g: t-
!00~
-8. 4.0 ,AA
-~ ~vo
~ ·~ r- ~ I
::0 -1
0~ -1
.9_20 Vcc =Yee=:!:9V..J$,-
-16 -12 -8.0-4.0 0 +4.0 +8.0 + 12 +16 -55 0 +25 +75 +125
V0 , OUTPUT VOLTAGE {VOLTS) T, TEMPERATURE (0 C)
Figure 5-0utput Slew Rate vs Figure 6-0utput Voltage and Figure 7-Maximum Operating
load Capacitance Current-limiting Characteristic:s Temperature vs Power-Supply
Voltage
··~··
·:fr·
Vo
tTHL--
- SO%
-tTLH
Switching Response
TEST CIRCUITS
+1.9V
VJ
+0.8V
VEE
46
INTERFACE (DRIVER)
MC1488 21s-2s2o
tor to each drive output. The required capacitor can be easily determined by r---,:•.---i
using the relationship C = los X il.T/il. V from which Figure 1 is derived. o-~--!'- ..)>-~-o
Accordingly, a 330-pF capacitor on each output will guarantee a worst case i '-· i
slew rate of 30 volts per microsecond. o- ~--:-- ·p-~ -o
The interface driver is also required to withstand an accidental short to any o-;-~-' :
other conductor in an interconnecting cable. The worst possible signal on any o-L_ __. _, :
conductox would be another driver using a plus or minus 15-volt, 500-mA o--l- - .:. _ ,t>--i -o
source. The 1488 is designed to indefinitely withstand such a short to all four : :
outputs in a package as long as the power-supply voltages are greater than 9.0 o-~-~- 'p.. - ~ 0
volts (i.e., Vcc;:,: 9.0 V; VEE s -9.0 V). In some power-supply designs, a loss of o-r--,. -· :
system power causes a low impedance on the power-supply outputs. When ~--;- ;- ---l
this occurs, a low impedance to ground would exist at the power inputs to the 1'i' ~ '
1488 effectively shorting the 300-ohm output resistors to ground. If all four out- ___________! _L _____ _
puts were then shorted to plus or minus 15 volts, the power dissipation in •••
these resistors would be excessive. Therefore, if the system is designed to per-
Figure 2-Power Supply Protection
mit low impedances to ground at the power-supplies of the drivers, a diode
should be placed in each power-supply lead to prevent overheating in this fault to Meet Power-Off Fault Conditions
condition. These two diodes, as shown in Figure 2, could be used to decouple
all the driver packages in a system. (These same diodes will allow the 1488 to + 12V
withstand momentary shorts to the ±25-volt limits specified in the earlier
Stam!ard RS232B.) The addition of the diodes also permits the 1488 to with-
stand faults with power-supplies of less than the 9.0 volts stated above.
The maximum short-circuit current allowable under fault conditions is more 1K
than guaranteed by the previously mentioned 10 rnA output current limiting. 10K
The 1488 is an extremely versatile line driver with a myriad of possible appli-
cations. Several features of the drivers enhance this versatility: Figure 14-MDTL/MTTL-to- MOS
Translator
1. Output Current Limiting-this enables the circuit designer to define the
output voltage levels independing of power-supplies and can be accom-
plished by diode clamping of the output pins. Figure 14 shows the 1488 used
as a DTL to MOS translator where the high-level voltage output is clamped
one diode above ground. The resistor divider shown is used to reduce the
output voltage below the 300 mV above ground MOS input level limit:
2. Power-Supply Range- as can be seen from the schematic drawing of the
drivers, the postive and negative driving elements of the device are essen-
tially independent and do not require matching power-supplies. In fact, the
positive supply can vary from a minimum seven volts (required for driving
the negative pulldown section) to the maximum specified 15 volts. The nega-
tive supply can vary from approximately -2.5 volts to the minimum speci-
fied -15 volts. The 1488 will drive the output to within 2 volts of the postive
or negative supplies as long as the current output limits are not exceeded.
The combination of the current-limiting and supply-voltage features allow a
wide combination of possible outputs within the same quad package. Thus if
- 12V + 12V
only a portion of the four drivers are used for driving RS232C lines, the
remainder could be used for DTL to MOS or even DTL or DTL translation.
Figure 15 shows one such combination. Figure 15-Logic Translator
Applications
47
INTERFACE (RECEIVER)
FEATURES RESPONSE
CONTROL A--+---,
• Input Resistance-3 .0 k to 7.0 K ohms
• Input Signal Range-±30 Volts RESPONSE
• Input Threshold Hysteresis Built In OUTPUT A CONTROL D
• Response Control
a) Logic Threshold Shifting
b) Input Noise Filtering
RESPONSE
Supply Voltage (Vee) . .. ... ..... . . .... .. .. ...... . ........ .. . . ... . ... . 10 V OUTPUT 8
RESPONSE
CONTROL C
Input Voltage Range (VIR) . . . .. ...... . ... . .... . ... . .. . .. . . . . .. .... . ±30 V
Output Load Current (II.) ...... ... . . . . ...... . . . .... ... .. . . .. ....... 20 rnA
Power Dissipation (Po) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W GROUND OUTPUT C
INTERNAL CIRCUIT
(% of Circuit Shown) TEST CIRCUITS
14
.----t---...,----ovcc' +5Vdc
RESPONSE RF OK SK 1.6K
CONTROL 2o-----~"""".rv-or-~
INPUT 1 C>-""""olv-~--+--l
3.55K
10K
7
'---+--~>----...__- ·-+---<GROUND
Input Currenl
Vee
Vee
48
INTERFACE (RECEIVER)
MC1489 21s-2s21
TYPICAL CHARACTERISTICS
+5Ydc
I
1-- r--sv
=
r--v,h _
~ 1.0~~~~~~~~.!L~-·-.--~~-
Eo measured
ITHL tTLH 10%-90%
1.5V 1.SV ! - 6-0bo--'f--+--+--+-+
0 0 ., '
.: -a.of-t-+--+--+-+ ~ f-- -j--VILH VIHL
C1 = 15pF =total parasitic capacitance, - ~o2.L,5--:L20- -...J.15,..._...,1c,o_...,5-:L.o,--...J.o- +-=5'=-.o-+ -':10_+...J.15,...+-'20':--:'+25 -3.0-2.0-1.0 0+1 .0+2.0+3.0
which Includes probe and wiring
capacitances Yin INPUT VOLTAGE (VOLTS) V1 1NPUT VOLTAGE (Vdc)
\ \
::~t=l=E=t=t~:=E=t=l~
iii
~ 51\
9~u 1.s
fa~ 1.6
~W 1.4f-_--f-t--f---l--1489 VIHL 1-----
0
2:
g
w 4
~10pF \',rf
1\\\
~ ~~ ~:~~
12
- ~Il;j~~i~=:E::E~
\ 100pf '
1:-
1 ,.<~ 3
1--\ .~y500pF
~> ~::~=t=l~EE~~·~v~=:'":l_3_3
146 2
r-- '-..._~
""'
> 0.2~ w
_06·Lo---'-"---'o'-.L_-'-_+..J.60,---"--...J..._+_j120 oo~--'---74.0~~--...,.~.0~~--~12 1
10 100 1000 10,000
T, TEMPERATURE (°C) Vee• POWER SUPPLY VOLTAGE (Vdc) PW, INPUT PULSE WIDTH (ns}
Figure 3-lnput Threshold Voltage Figure 4-lnput Threshold vs Figure 5-Turn-on Threshold vs
vs Temperature Power-Supply Voltage Capacitance from Response
Control Pin to Gnd
used. The 1488 quad driver and its companion circuit, the 1489 quad receiver,
provide a complete interface system between DTL or TTL logic levels and the
RS-232C defined levels. The RS-232C requirements as applied to receivers are
~->--6-_l-0~::Jo-
discussed here. The required input impedance is defined as between 3000 INTERCONNECTING
ohms and 7000 ohms for input voltages between 3.0 and 25 volts in magnitude; : CAiLE :
and any voltage on the receiver input in an open circuit condition must be less MOTL LOGIC INPUT : ~ MOTL LOGIC INPUT
than· 2.0 volts in magnitude. The 1489 circuits meet these requirements with a I I
---1
L - ....-'
DTL OR TTL
,--"I
11 1
-Yoo -Yeo
+5Yde -...
+5VJr
49
LINCMOS (A TO D CONVERTER)
- GENERAL DESCRIPTION
8-BIT ANALOG TO DIGITAL
CONVERTER
REF+- r-vcc
REF - - - D A T A OUT
FEATURES
• Versatile control logic GND- -cs
• An on-chip sample-and-hold circuit that can operate automatically or under
microprocessor control
• A high-speed converter with differential high-impedance reference voltage
inputs that facilitate ratiometric conversion and scaling, while isolating the
conversion circuitry from logic and supply noises. BLOCK DIAGRAM
• The TLC548 provides low-error conversion of ± 0.5 least-significant bit
(LSB) in less than 17 microseconds. REF + ~I'~l-------------1
REF - -"(3,_)--------------1 ANA8l~1~-TO- -
DIGITAL
ABSOLUTE MAXIMUM RATINGS ANALOG (2)
SAMPLE
AND 1-------1 ~so;,~~~l~
Supply Voltage, Vee (See Note 1) ...... ... . .... . . .... . ........ . . . ... . . 6.5 V INPUT HOLD CAPACITORS)
Input Voltage Range (Any Input) . .. . . . ... . .. . . . .. . . . .. -0.3 V to Vee+ 0.3 V
Output Voltage Range .. .. .. . .... . ... . .. . . . .... . . . ... - 0.3 V to Vee+ 0.3 V I
Operating free-air Temperature Range . .... . .... . . . ......... - 40°C to 85°C
NOTES: 1. All voltage values are with respect to network ground terminal with the REF- and GND ter- I INTERNAL
SYSTEM
CLOCK
r IL I
I
CONTROL
t
I
minal pins connected together, unless otherwise noted. LOGIC
cs -::1'~>---------------1 o~~T
1/0 CLOCK m COUNTER
Overview of Operation
The TLC548 is a complete data acquisition system and it includes such func-
tions as an internal System Clock, Sample-and-hold, 8-bit AID converter, Data
register, Control logic, 1/0 Clock, and a Chip Select (CS).
These control inputs and a 3-state data output facilitate serial communica-
tions with a microprocessor or minicomputer. A conversion can be completed
OUTPUT
in a maximum of 17 microseconds, while total access and conversion time is a DATA
REGISTER
maximum of 25 microseconds. ·
The internal System Clock and I/0 Clock are used independently and require
no special speed or phase relationship. This simplifies the hardware and soft-
ware control tasks for the device. Because of this independence and the inter- --~
nal generation of the System Clock, the microprocessor and software need 4!'
'-----', /.,-j 8-T0-1 DATA
only read the previous conversion result and start the conversion with the 1/0 I SELECTOR
AND
(6) DATA
OUTPUT
Clock. The internal System Clock drives the "conversion-crunching" circuitry. DRIVER
50
LINCMOS (A TO D CONVERTER)
Operating Sequence
A7 87
- - PREVIOUS CONVERSION DATA A - - - - - CONVERSION DATA 8 - -- -
MSB LSB MSB LSB
(See Note B)
NOTES: A. The conversion cycle is initiated with the trailing edge of the Bth 110 Clock pulse after CS'
goes low. ·
B. The most-significant bit (MSB) is then placed on the DATA OUT pin after CS' is brought low.
The remaining seven bits (A6-AO) are shifted out on the first seven 110 Clock {ailing edges.
C. To minimize errors caused by noise on the CS signal, the internal circuitry waits for two ris-
ing edges and then one falling edge of the Internal System Clock (1.4 p.s at 2 MHz) after a
Chip Select transition before responding to control input signals. Therefore, no attempt
should be made to shift out conversion data until the minimum Chip Select setup time has
elapsed.
51
LINCMOS (A 1'0 D CONVERTER)
microprocessor.
The serial port's Mode 0 state is used to permit 8-bit transmission and recep- lntel8051152
tion. The TLC548 sends the most-significant bit of the conversion result first; Family
the serial buffer receives this bit as the least-significant bit. The software then
reverses the conversion bits and places them in the proper order.
The timing consists of the following three major phases:
1. After CS goes low, eight I/0 Clock cycles access and sample the new ana-
log input. At the same time, I/0 Clock falling edges bring out the previous
conversion result.
2. Conversion begins when the eighth I/0 Clock goes low. Conversion
requires 36 internal System Clock cycles after the eighth I/0 Clock goes
low. The maximum conversion time is 17 microseconds.
3. Eight falling edges of the I/0 Clock bring out the previous conversion
result.
Interface Control Software
; Subroutine ACALL
SR549D CLR Pt.6 ; Lower Chip Select
ORL SCON ,#lOH ; Set REN
ANL SCON,#FEH ; Reset R1
JNB SCON.O,RCV ; R1 flag not set; branch
; until reception is complete.
CPL P1.6 ; Raise Chip Select
RET ; Conversion is in SBUF
END
52
LINCMOS (A TO D CONVERTER)
Conversion occurs
during this time interval
1/0
CLOCK
~------------------------ 79 ,s --------------------------~
--H-
~---- 21 ·· --------~
DATA
OUT
TLC548
Z80A Interface
The Z80A interface is an economical solution, offering efficient control soft-
ware and communications with the TLC548.
Required Software
A simple program segment that reads in a previous conversion result and
starts a conversion is shown below. Placing this program segment in a loop
makes it possible to initiate a conversion and read previous conversion results
in 111 microseconds.
53
LINCMOS (TIMER)
TLC555 TIMER
276-1718
FEATURES 0.1p.F:b
GNO
(1i I''
Power Dissipation (mW) ........ . . ........ . .... . ................. 600mW Circuit for Astable Operation
Operating Temperature Range ................. . .. . ..... .. ... o•c To 70°C
Storage Temperature Range .................. . .......... -65°C To 150°C
NOTES: 1. All voltage values are with respect to network ground terminal.
BLOCK DIAGRAM
Vee RESET
THRESHOLD
OUTPUT
TRIGGER
DISCHARGE
54
LINEAR (AUDIO)
[?I I
tected. The 383 comes in a 5-pin T0-220 package. SSUPPLYVOLTAGE
4 OUTPUT
FEATURES : 3GROUND
21NVERTING INPUT
• High peak current capability (3.5A) • Low distortion 1 NON·INVERTING INPUT
• Large output voltage swing • High input impedance
• Externally programmable gain • No turn-on transients
• Wide supply voltage range (5V -ZOV) • Low noise
• Few external parts required • Short circuit protected
• Pin for pin compatible with TDA2002
INTERNAL CIRCUIT 0
20 50 100 200 500 1K
!=:':'1'
2K SK 10K 20K
FREQUENCY -Hz
Distortion vs
Frequency
0
/
R,l= ~~
~
~
6
_L_ 40 17"
_L
>
I / [/"'
"z 1
2
/ v
...~ L: /
.....
~
~
8
/;:;
~
0
4
0
12 16 20
+INPUT -INPUT VsuPPLv-VOLTS
Output Swing vs
TYPICAL APPLICATIONS Supply Voltage
Vs Vs
14.4V 14.4V
2~~4!1
2.2!.1 2.211 2.211
220H
I 0.2p:F 1
~ -:;:-
55
LINEAR (AUDIO)
GND
FEATURES
• Battery operation • Ground referenced input
• Minimum externa l parts • Self-centering output quiescent
• Wide supply voltage range 4-12 volts voltage
• Low quiescent current drain 3 rnA • Low distortion
• Voltage gains from 20 to 200 • Eight pin dual-in-line package
APPLICATIONS
INTERNAL CIRCUIT
• AM-FM radio amplifiers • Line drivers
• Portable tape player amplifiers • Ultrasonic drivers - INPUT BYPASS GAIN GAIN + INPUT
2 7 8 1 3
• Intercoms • Small servo drivers
• TV sound systems • Power converters
TYPICAL CHARACTERISTICS
~
~ 2.0r~::-:~:""':b""+T- -+ ' -j·---~;--+T-j
T_- +- -,
l
~ 10 RL
i=
Ya "= SVHI-i+ftttt!H-tltf#tll
80
ii; 1.0
s! JA~t-
5 0.5
~ 1.6 PoUT " 12SmW-t-+--t-H a 1kHzilt-1+ftttt!H-IIH#tll v.~ yl--' ! o.• H--;lo''++-H ,.ct-+-1
co~;~
u: t "' 0.8
~ Av = 26dB(Cu = 0 ) _
~ ;~~T
a 1.2!-H-+-++-t-++-11 c ·~+Hffit-H~~~~ i
z
0.6
~v~
I
- z
2 o.3 1-tl-;;-i:±+::H-,t."f--+-1
:
"~ o.a!-H-+-++-t-++-1 "~ ·~+Hffit-H~~tt~ fg 0.4
I 1oz;:~~r jg 0.2 lh+-h.f-:,1"'++
I c c
~ 0.4 P"-kl-t-+-++:..t--+-1 "
a:
c
:J: ~ 0.2 ~ 0.2
....r
r/ Vs =6V 3~ 01~1+ ~ 0.1 .... <+--+-+
~ r--t---f---j---H---j ~ -(•yc ~
~ 0 20 100 1k
FREQUENCY (Hz)
10k e~ o~~~~titt®;~~
o.oo1 0.01 0.1 1.0
OUTPUT POWER (WATTS)
0 0~0--0~
.•~0~.•~~
0.~
3 --0.~4~
0.5
OUTPUT POWER (WATTS)
0 0
0.2 0.4
OUTPUT POWER (WATTS)
0.6 0.6 1.0
0
TYPICAL APPLICATIONS
56
LINEAR (AUDIO)
FEATURES
• Low distortion 0
THD=0.15o/o (Typ.) (@PouT=1W, Gv=55dB)
THD=0.07o/o (Typ.) (@P0 m=1W, Gv=44dB) •
• Operating supply voltage range: Vcc=9-18V
• 'PCT' process to insure low noise characteristic •
• Current limiting for short-circuit protection
• Built in thermal shut-down circuit
• Built in surge voltage protection circuit
PIN FUNCTION
ABSOLUTE MAXIMUM RATINGS 1 V+
2 BOOTSTRAP
Operating Supply Voltage(Vcd ........................................ 18V 3 DECOUPLING
Quiescent Supply Voltage (VccQ) ...................................... 25V •
5
PHASE COMPENSATION
PHASE COMPENSATION
Output Peak Current (Io) ................ . ......... .. ................. 4.5A I INPUT
7 NEGATIVE FEEDBACK
Quiescent Current (!ceQ) ......... .. ................ ... .............. 80mA I PHASE COMPENSATIOM
•
,
13.2V
-
4
I .,........
18V
j 18Y
2
~
13i2V1
0
8 10 12 14
OUTPUT POWER Pouy-W
Power Dissipation
vs Output Power
v!,
....
z
~ 20
....
ffi
0 2
1-
lfc~ - t-r-
-
Ill ..
5
0 0
~ 0
8 10 12 14 18 18
TYPICAL APPLICATION SUPPLY VOLTAGE Ycc-V
OUTPUT
...
;!: 8
~
t- I'..
I.'-
0.047~F 2 r-~Err s.~~i I'::
0
25 50 75 100 125 150 175
AMBIENT TEMPERATURE TA
57
LINEAR (AUDIO)
FEATURES
• Low input offset voltage
• Output stage with low cross-over distortion
•A.C. short-circuit protected
• Very low internal thermal resistance
• Thermal protection
• Very low intermodulation distortion
• Very low transient intermodulation distortion
BLOCK DIAGRAM
PIN FUNCTION
1 Non-inverting input
2 Input ground
(substrate)
3 Compensation
4 Negative supply
(ground)
5 Output
6 Positive supply (Vp)
7 Not connected
8 Ripple rejection
9 Investing input
(feedback)
r .
58
LINEAR (AUDIO)
'
TDA1520A 21s-1aos
TYPICAL APPLICATION
Vp Rsupply
, - - ~--- Vsupply(va)
6
~·l
·:4: I
. , 2.2mF
150~F ± 8 TDA1520A
+
i
7 - n.c .
20
KO !"-~OAR & THERMA
PROTECTION
Rsoutce 1ttF 1
r - """"'"--ji• + 5 2.2 f . r D J
~
AM PL.
• RL
~rFt""""~·~
::ho.1~F,
9
I
+680 20
KO 2
PROTECTION
2.1n
10/LF t + ..!,. 3
4
Test Circuit
I 680pF
270!1
25 / (% )
40 1
I I
20
I I 0.4
80
15
J I
I /
10
I / 0.2
I /
J /
v/
-
5
I
0
v 0
I- /
0 10 20 30 40 Vp(V) 50 0.1 1 10 Po(W) 100
Output power (P0 ) versus supply voltage (Vp) Total harmonic distortion (d101} versus output
at f =
1 kHz, d101 =
0.5%, G, 30 dB. = power (P.) at v. 33 V, RL =
4 !l, f =
1 kHz. =
50 0.3
Ptot
,,
(W)
dtot
40 (%)
30
1'-, '1\ 0.2
\
20
' ~' \
\ J
1/
"'~' ~,
0.1
'..,' .\
/
10
v
0 "\ ,.
150 0
- 25 0 50 100 0.1 1 10 f(kHz) 100
lamb (°C)
Power derating curves. Total harmonic distortion (d1• 1) versus operat·
--- mounted on Infinite heatsink. ing frequency (f) at v. 33 V, RL= 4 0, =
--- mounted on heatsink of 2,3 K/W. P. =
10 W (constant).
59
LINEAR (OP AMP)
They require low supply current yet maintain a large gain bandwidth product
and fast slew rate. In addition, well matched high voltage JFET input devices
provide very low input bias and offset currents. OUTPUT A-;1 ;-f---,
These amplifers may be used in applications such as high speed integrators,
fast D/A converters, sample and hold circuits and many other circuits requir- INVERTING
INPUT A 2
..---+--,-
7 OUTPUT B
ing low input offset voltage, low input bias current, high input impedance,
high slew rate and wide bandwidth. The devices also exhibit low noise and off- NON-INVERTING INVERTING
INPUT A 3 I INPUT B
set voltage drift.
FEATURES .
• Internally trimmed offset voltage = 2 mV
• Low input bias current = 50pA
• Low input noise voltage= 16nV/vHz
• Low input noise current= 0.01 pA/vHz
• Wide gain bandwidth = 4 MHz
• High slew rate = 13 V/p.s
• Low supply current = 3.6 rnA
• High input impedance= 1012(!
TYPICAL CHARACTERISTICS
• Low total harmonic distortion Av = 10,
RL = 10k, Vo = 20 Vp-p, BW =20Hz-20kHz= <0.02% 5.0
r--...
Ys=: 15V
A,•2K
Cl-= 100pF
.- ~
Supply Voltage ...... . ... . .......... . .. . ....... . .... .. ...... . .... . . ±18V
~z •.0
!'---
Power Dissipation . . ...... . ..... . ............... . .... .. ......... . 500 mW ::!
z
I'--
['. ........
Differnetial Input Voltage ........................................... ±30V
Input Voltage Range .. . ...... . .. ... ........... . . ...... . . .. ........ . ±15V ~ 3.5
z
Output Short Circuit Duration .. .. .............. ... .. . . .. ..... . Continuous "
THMAXJ ...... .... .......... . . .. .. ... . ......... .. . . ............. . ... 11s•c 3.0
20 60
Operating Temperature Range .. . . . . ..... . .... . ...... ... . .... .... 0 to 70 o C TEMPERATURE -•C
Storage Temperature Range . ........ ...................... -65 to +1so•c
Lead Temperature (Soldering, 10 seconds) ............................ 3oo•c
Unity Gain Bandwidth
vs Temperature
TYPICAL APPLICATIONS
Cl
Yon_
>-"--<>Yo '8: ~kH• ••
lOOK 0 '·
loUT Av • 2
AI
IMO
+ A2
HIGH Z1N
LOWZour YR A
•Htgh It 100 nA
IMO
Yo • v,.
60
LINEAR (OP AMP)
353 276-1715
R1 R2
1MO
390K
c,.
i·- R4
f~
6.2K
l_l Vo
R3 620K
R4
V+
v,. 100K
Ay=1+R21R1
~ C2 I'""F
Av = 11 (As shown)
V+
R1
c,. R1 C1
10K
v,. o---1 f--4----H--.-----:c-1
0.001
··f R2
100K
C1 I 100K
10"F Av '"'RtiR1
Ay = 10 (As shown)
R2
100K
51K
R/2 50K
For R1fR2 '"' R41R3 (CMRR dependa on thla re1lator ratio match)
V0 = 1 + R41R3(V 2 - V1) 100K
As shown Yo =2(V2 - Y,)
61
LINEAR (OP AMP)
TYPICAL APPLICATIONS
R2 +9V
+V
Sto 18V
v,.
Your
GAIN R1 R2 BW
-V
-Sto -18V
10 1K 9K 100kHz 400M!!
100 100~! 9.9K 10kHz 280M!! Your = YtN (1 + R2/R1)
1000 100!! 99.9K 1kHz 80M!! *At sets the voltage detection threshold (up to +9V).
When V1N exceeds the threshold (reference), the LED glows.
R2' R3'
R2
1M!! 1M!!
+V
:~,H
S to18V
Your Your
~~3
v,. R1
0.001Jl F 0.001JtF
- V -v
- Sto - 18V -Sto -18Y
Your = - YtN (R2/R1) Your = YtN
.02 ~F
Sl' Electronic Bell
1: 0-10.0p.A CAUTION:
THIS IS
2: 0- 1.0p.A
3: 0- 0.1 p.A AVERY
SENSITIVE PC1
CIRCUIT! 276·116
TOO MUCH CdS PHOTOCELL
LIGHT WILL
SLAM THE
METER R4
NEEDLE.
R1 1K
470!!
8\!
SK SPEAKER
- 9V
R2 100K
PC2
276·11 6
CdS PHOTOCELL
62
LINEAR (OP AMP)
TYPICAL APPLICATIONS
R2
R2 R4
C1'
Your
v,.
R3 R6
10K 1K
-=:=- 100p.F
AS 10K
C1 stores the peak voltage at V1N· •c1 FREQUENCY
0.001 ~t F 5872Hz
0.01011 F 660Hz
0.100JLF 51Hz
1.000p.F r 8Hz Pulses are DC when C1 = 0.1JcF
Amplitude i s 5 volts.
R1 RS R8
FREQUENCY = 1kHz
100K 100K 100K
C2 C3 R11
C1
Function Generator
63
LINEAR (OP AMP)
FEATURES
• Internally frequency compensated for unity gain
• Large de voltage gain 100 dB
• Wide bandwidth (unity gain) 1 MHz (temperature compensated)
• Wide power supply range :
Single supply 3 Voc to 30 Voc
or dual supplies ±1 .5 Voc to ±15 Voc
• Very low supply current drain (BOO !LA) -essentially independent of supply
voltage (1 mW/op amp at +5 Vocl
• Low input biasing current 45 nAoc (temperature compensated)
• Low input offset voltage 2m Voc and offset current 5 nAoc INTERNAL CIRCUIT
• Input common-mode voltage range includes ground (Each Amplifier)
• Differential input voltage range equal to the power supply voltage
• Large output voltage swing 0 Voc to V+ -1.5 Voc
TYPICAL APPLICATIONS
+v~
4
Your
TV IN
1M
R1 R1 1N914 R2 1N914
JOK
100K
R2 R4 RJ R4 RJ
V+~~~4---~~~ AS
100K 100K V+ o--"",o"o"'K---i---,"oo"'K----' V+ ~~~-t------'V'.tv-----'
100K 100K
R3 100K
AS 100K R4 100K
64
LINEAR (TIMER)
TIMER 555
276-1723
APPLICATIONS
• Precision timing • Time delay generation • Pulse position TRUTH TABLE
• Pulse generation • Pulse width modulation
• Sequential timing modulation • Linear ramp generator PIN 2 PIN 6 PIN 4 PIN 3
TRIGGER THRESHOLD RESET OUTPUT
ABSOLUTE MAXIMUM RATINGS H X H L
Supply Voltage ........................................ . ... . ....... +16V L X H H
Power Dissipation . . .................... . ......................... 600 mW H L H L
Operating Temperature Range ............... . . . ....... . ... . .... 0 to +70°C X X L L
Storage Temperature Range ....... . .................... . .... -65 to +150°C
Lead Temperature (Soldering. 10 seconds) ....... . . . ........ . ......... 300oC X = Don't Care L = Low Level H = High Level
TYPICAL CHARACTERISTICS
..."-
1
u
w The charge time (output high) is given by: t 1 = 0.693 (RA + R8 ) C
u The discharge lime (output low) Is given by: 12 = 0.693 (Ra) C
z Thus the total period Is: T= 11 + t 2= 0.693 (RA + 2R 8 ) C
~ The frequency of oscillation Is: f = 1fT = 1.44 I (RA + 2R 8 ) C
~
"
u
FREE-RUNNING FREQUENCY t - Hz
TYPICAL APPLICATIONS
Capacitance vs
Free-Running Frequency
_jL
0.1"F LI. 1M
7
4
1M
1
555
01 5 8
TO
+15V NORMALLY 0.01j..!F
1N4001 ON LOAD 3
100K
~
~ ..
C1
R1 4.7K
IGNITION
-_1$ 10~F
10K
~LI·
SWITCH TO
NORMALLY 33K 33K
START a OFF LOAD
ON ~
~
5J
5000
555
]
4
12V
1 8
~
3
2200
R2 n 450
SPEAKER
65
LINEAR (TIMER)
APPLICATIONS
• Precision timing • Pulse width modulation
• Pulse generation • Pulse position modulation
• Sequential timing • Linear ramp generator
• Time delay generation
TYPICAL CHARACTERISTICS
1.2
Vc~ = lsv
• 1.0
... "I T~ = lm·~ V
"I ~ 0.8 f I "- LL
"w
";!z
The charge time (output high) is ginn by:
t1 = 0.693 (RA + Re) C
The discharge time (output low) is given by:
t 2 = 0.693 (R 8 ) c
i
~ 0.6
v_,
2slc ~
N rL'
u Thus the total period Is: ~ -sl•c _
~ T = t 1 + t2 = 0.693 (RA + 2R 8 ) C
10
y
>
I
5
f-J. j IJc b.....-
'• ='-s~·c
, ~v
~1. 6
"EI 8 ~ +25°C
0
v ~s•c /
1- 0
ffi ~
-
1. 2
~
/
6
"~ +125°C 1--
V- ~ v ~25"C
::>
" g
~
0.8
4
p ~
ii:
2~ ~
0 0. 4
:z: 5V '" Vcc :!i> 15V
0 ":;: 0 Jj
10 15
SUPPLY VOLTAGE - V 1 10 100
OUTPUT SOURCE CURRENT lsouRCE - mA
66
LINEAR (VOLT REG)
GENERAL DESCRIPTION
The 317T is an adjustable 3-terminal positive voltage regulator capable of
supplying in excess of 1.5 A over a 1.2 V to 37 V output range. This device is PIN CONNECTIONS
exceptionally easy to use and requires only two external resistors to set the
output voltage. FRONT VIEW
• In addition to higher performance than fixed regulators, the 317T offers full
overload protection available only in IC's. Included on the chip are current
limit, thermal overload protection and safe area protection. All overload pro-
tection circuitry remains fully functional even if the adjustment terminal is dis-
connected.
Normally, no capacitors are needed unless the device is situated far from the
input filter capacitors in which case an input bypass is needed. An optional
output capacitor can be added to improve transient response. The adjustment
terminal can be bypassed to achieve very high ripple rejection ratios which are
difficult to achieve with standard 3-terminal regulators.
Besides replacing fixed regulators, the 317T is useful in a wide variety of
other applications. Since the regulator is "floating" and sees only the input-to-
output differential voltage, supplies of several hundred volts can be regulated
as long as the maximum input to output differential is not exceeded. 317T
It will also serve as a simple adjustable switching regulator, programmable
output regulator, or by connecting a fixed resistor between the adjustment and
output, the 317T can be used as a precision current regulator. Supplies with TYPICAL APPLICATIONS
electronic shutdown can be achieved by clamping the adjustment terminal to
ground which programs the output to 1.2 V where most 'oads draw little v,. Your
current.
FEATURES
, • Adjustable output down to 1.2V • 100% electrical burn-in R2 "'
Your=1 .2SY{1+fi;")
• Guaranteed 1.5A outpput current • Eliminates the need to stock many v,N > Your + 1.25
• Line regulation typically 0.01%/V voltages VOLTAGE REGULATOR
• Load regulation typically 0.1% • Standard 3-lead transistor package
• Current limit constant with • 80 dB ripple rejection
temperature
R
YIN lour
Power Dissipation .. .. . ...... .... . ... . . ..... ..... . .. . .... Internally limited
Input-Output Voltage Differential. ............. . . ... ..... . ..... .. ....... 40V lour= 1:1s
Operating Junction Temperature Range ... . ..... . . . .. . ........ . . 0 to + 125°C
CURRENT LIMITER
Storage Temperature ............ ........ .. .. .. . ......... . .. -65 to +150°C
Lead Temperature (Soldering. 10 seconds) . . ... .. ... . . .. . . . .. ..... .. . . 300°C
INTERNAL CIRCUIT
R1 R2 R3 R4 R5
3100 3100 100!1 82!1 5.6K
R8
200K
01
S.3Y C1
30pf
C2
R10 R12 R13 30pf
4.1K 72!1 5.1K
Rt
11100 R11 R14 R28
5.8K 12K 0.10
Your
ADJ
67
LINEAR (VOLT REG)
317T 276-1778
TYPICAL APPLICATIONS
01
2N37t2
L1 v,.
600JA.H*
R2
18-32Y
0.250 R2 2.4K
R3
C1 • C2
0.011-lF C4 100JA.Ft 12V Battery Charger
50"F
01
1N3810
300pF
tSoaid Tantalum
•core-Arnold A·264111-2 10 tum•
1200
1200
AC Voltage Regulator
0.2!1
68
LINEAR (VOLT REG)
FEATURES
• 150 rnA output current without external pass transistor
• Output currents in excess of lOA possible by adding external transistors
• Input voltage 40V max
• Output voltage adjustable from 2V to 37V
• Can be used as either a linear or a switching regulator
The 723 is also useful in a wide range of other applications such as a shunt reg-
ulator. a current regulator or a temperature controller.
TYPICAL CHARACTERISTICS
+0.I
...
1.2
Vout • +5V
v,N .. +12V
1-
LU 1.0 Rsc z 100-1-
~
5 o.8
>
,.J 0
""'!,... ....... r.., .. o•c
I
I
c,.,
1 R2
+12V
5
~ - 0.I
r • ro•c
-~=:::~
)'-...
r--.
I' TYPICAL PERFORMANCE
Regulae.d Output YoU11ge SV
~v.,. = 3Y)
5~ 0.2 Your .. +SV
Une R-..lauon (
LNCI Regulation ( AIL " SOmA) 1.5mV
O.SmV
Rsc • 100
Note: R3 "' R~\R:a tor minimum tempen~ture drift.
0 I -0.2
20 80 80 100 0 10 20 30
OUTPUT CURRENT-mA OUTPUT CURRENT-mA
Basic Low Voltage Regulator
Relative Output Voltage
vs Output Current
Load Regulation vs
Output Current
.,.
200
TJMAX • 12S•C~ ~
RrH • 111• CIW
180
h
~.:6·~::;S~Ne:~ -
R3
~ 120
I
:!
1\
"
.=' 80
\
40
f-r\ N- =,25"~ TYPICAL PERFORMANCE
1'+-
rrcN
Regulated Output Voltage 15V
0
T"t •
10
I
20 30
(VIN - Your) - VOLTS
.. 50
LlneRegulatlon(A Y 1N
Note: R3 ::z:
3V)
R 1R~R~2
=
1.5mV
Load Regulation {.lll ::z: 50mA) 4.5mV
69
LINEAR (VOLT REG)
SV VOLTAGE REGULATOR
12V VOLTAGE REGULATOR
15V VOLTAGE REGULATOR
TYPICAL APPLICATIONS
YouT
OUTPUT CURRENT : R'f"
4.7K
0.50
Current Regulator
2N4398
1...,.
High Output Current, Short Circuit Protected Positive and Negative Regulator
70
LINEAR (MISCELLANEOUS)
designed specifically to operate from a single power supply over a wide range of
voltages. Operation from split power supplies is also possible and the low power ,...---+--,1:-:-4 OUTPUT 3
1- ! - - - ,
OUTPUT 2--,.
supply current drain is independent of the magnitude of the power supply
voltage. These comparators also have a unique characteristic in that the input
common-mode voltage range includes ground. even though operated from a
single power supply voltage.
FEATURES
• Wide single supply:
Voltage range 2 Voc to 32 Voc or dual supplies ±:1 Voc to ±:16 Voc
• Very low supply current drain (0.8 rnA) -independent of supply voltage
(1 roW/comparator at +5 Voc)
• Input common-mode voltage range includes ground
• Differential input voltage range equal to the power supply voltage
• Low output 1 mV at 5 ~;saturation voltage 70 mV at 1 rnA
• Output voltage compatible with TTL (fanout of 2). DTL. ECL. MOS and CMOS
logic systems
TYPICAL APPLICATIONS
5 VOLT GROUP
15V GROUP
Y+
Y+ Y+
+v1,.
39K 200K
YouT 3K 3K
+VREF
Basic Comparator
. Y+
c
vo~ _[ 100K
1K
:·c s 100K
1K I == A+B +C
Y+ Y+
1M
:1. 15K
100K
Driving CMOS 10K
Y+ •• ,. o--l rr---+---t
100pF
1NJ14 100K
YouT
R 0-"Nv--+--!
Y+ 100K
0 ___jl_
1M
1N914
71
LINEAR (MISCELLANEOUS)
FEATURES
TIMING
• 20 to 1 frequency range with an external resisfor I CAPACITOR
• Logic compatible output with 100 rnA current sinking capability
• Bandwidth adjustable from 0 to 14% V+ 4
TIMING
5 RESISTOR
• High rejection of out of band signals and noise
• Immunity to false signals
• Highly stable center frequency
• Center frequency adjustable from 0.01 Hz to 500 kHz
APPLICATIONS +Y
• Touch tone decoding
• Precision oscillator
• Frequency monitoring and control
• Wide band FSK demodulation
• Ultrasonic controls
• Carrier current remote controls
• Communications paging decoders
TYPICAL APPLICATIONS
BW - 1070 ~ ln % offo-
'Jt;C2
Where: V1N """ Input voltage (volta rms), V1N .s 200mV.
ComPGMnt .,,,.,..
IIJI>)
R1 1.1 to 15K
+Y R2 4.7K
•• 20K
C1 0.10~F
C2 1.0~&F
C3 2.2pF
t_,_ _;::~...,...r--.1-t---' C4 2SOJlF IV
200mVrma
72
LINEAR (MISCELLANEOUS)
FEATURES
• Operation over one year from one C size flashlight cell •
• Bright. high current LED pulse
• Minimum external parts
NC Y-
~ Low voltage operation. from just over 1 V to 5V 3K FAST RC OUT
• Low current drain. averages under 0.5 rnA during battery life
• Powerful; as an oscillator directly drives an 80 speaker
Peak LED Current .... . o ••••• o •••••• • o ••••• • ••••• 45 rnA • ••••••• • •• • ••••••
••
•••
Drain Current vs
Battery Voltage
AA 3 MONTHS 6 MONTHS
c 7 MONTHS 15 MONTHS
0 1.3 YEARS 2.6 YEARS
1.5V Note: Estimates are made from our testa and manu·
3909 tacturers data. Conditions are fresh baHerles and
room temperature. Clad or " leak-proof" batteries
are recommended for any application of live months
3909 -=..3Y or more. Nickel Cadmium cells are not recommended.
V+
NORMAL
FLASH Hz
c, Rs 1W ... V+RAHQE
300pF Note: Normal flash rate: 1Hz. Nominal flash rata: 1.3Hz Avaraga loRAIN • 2mA. 6V 2 400pF 1K 1.5K 5-25V
3V Average I OAAIN = 0. 77mA 15Y 2 180J,.tF 3.9K 1K 13-SOV
1DDY 1.7 180J..LF 43K 1K 85-200Y
3V Flasher Parallel LED's
73
MOS(CMOS)
additional receivers. The SSI 202 uses a monolithic integrated circuit fabri- IN1833 15 CLRDY
and analog functions on the same CMOS chip using a standard digital semi- ONO 12 XIN
conductor process. The analog input is pre-processed by 60-Hz reject and
XEN 11 XOUT
band splitting filters and then hard-limited to provide AGC. Eight bandpass fil-
ters detect the individual tones. The digital post-processor times the tone dura- ANALOG IN ONO
tions and provides the correctly coded digital outputs. Outputs interface
directly to standard CMOS circuitry, and are three-state enabled to facilitate
bus-oriented architectures.
FEATURES
• NO front-end band-splitting filters required
• Single, low-tolerance, 5-volt supply
• Detects either 12 or 16 standard DTMF digits
• Uses inexpensive 3.579545-MHz crystal for reference
v, v,
• Excellent speech immunity
• Output in either 4-bit hexadecimal code or binary coded 2 of 8
• Synchronous or handshake interface
• Three-state outputs
VIN<Vp VIN>V,
ABSOLUTE MAXIMUM RATINGS*
.01~F
Supply Voltage (DC) . .. ...... . .. . ..... ... .............. . ............... 7V )----1 9
-l!---o --11--o
Input Voltage (All Inputs Except Analog In) .................. - .5V to + .5V ANALOG 10pF
ANALOG
10pF
Analog In Voltage .... ................ . . . . .. . .......... ... . - 10V to + .5V IN IN
ANALOG IN Flg.1
This pin accepts the analog input. It is internally biased so that the input sig-
nal may be AC coupled. The input may be DC coupled as long as it does not
exceed the positive supply. Proper input coupling is illustrated in Fig. 1.
The SSI 202 is designed to accept sinusoidal input wave forms but will oper-
ate satisfactorily with any input that has the correct fundamental frequency
with harmonics greater than 20 dB below the fundamental. r--JDf-
v,
CRYSTAL OSCILLATOR XIN XOUT
The SSI 202 contains an onboard inverter with sufficient gain to provide 12 11
oscillation when connected to a low-cost television "color-burst" crystal. The
8~
ATB
crystal oscillator is enabled by tying XEN high. The crystal is connected 13 $51202
between XIN and XOUT. A 1 MO 10% resistor is also connected between these
pins. In this mode, ATB is a clock frequency output. Other SSI 202's may use
the same frequency reference by tying their ATB pins to the ATB of a crystal-
connected device. XIN and XEN of the auxiliary devices must then be tied
high and low respectively. Ten devices may run off a singltl crystal-connected
1 XIN CONNECTED TO V,
SSI 202. •
12
'11
13 SSI202
UP TO 10 DEVICES
74
MOS(CMOS)
SSI202 21s-13o3
Block Diagram
BANDPASS FILTERS
TIMING
CIRCUITRY ED
CLRDV
15
DV
14
HEX
DATA STROBE ,..-----+-----+'-828
:0
01
02
18
04
17
DB
18
EN
V, 5 GNO 10 GND 7
HEX/B28
This pin selects the format of the digital output code. When HEX/B28 is tied
high, the output is hexadecimal. When tied low, the output is binary coded 2 of
8. The table below describes the two output codes.
75
MOS(CMOS)
SSI202 216-1aoa
IN1633
When tied high, this pin inhibits detection of tone pairs containing the
1633-Hz component. For detection of all 16 standard digits, IN1633 must be
tied low.
DVandCLRDV
DV signals a detection by going high after a valid tone pair is sensed and
decoded at the output pins Dl, D2, D4, DB. DV remains high until a valid pause
occurs or the CLRDV is raised high, whichever is earlier.
N/C PINS
These pins have no internal connection and may be left floating.
DETECTION FREQUENCY
CLROV
'"
22ms
ED
76
MICROCOMPUTER (8 BIT)
...... .
37
allophones (speech sounds) and five pauses are stored.
The CTS256A-AL2 is a device whose on-board ROM is masked with code-to-
speech algorithm. This algorithm converts English text (in the form of stand- 07
31
..
..
user's program running in this CTS256A-AL2 from off-chip Rom. Such user D2
programs are written in PIC7001 assembly language which is 100% compatible
with TMS7001 assembly language. 01
FEATURES: AI
• Unlimited vocabulary
"
vee
• Utilizes letter-to-sound rules "
...
17 A10
• Serial or parallel interface
• Microprocessor available for user code 11
..
11 A12
Refer to TABLE 1.
INPUT INTERFACE -Serial port & baud rate vs. Parallel port
INPUT BUFFER -Internal RAM vs. External RAM
DELIMITER -Any-delimeter vs Carriage-return-only
UART PARAMETERS -Program defaults vs 74LS373 selectable (or eprom
definable)
FIRMWARE (EXCEPTION-WORD/USER EPROM)
CONTROLLED CODE-TO-SPEECH OPTIONS: (optional)
Refer to TABLE 2.
n
l
MICROCOMPUTER (8-BIT)
CTS256AL2 276-1786
CODE-TO-SPEECH ALGORITHM (Cont'd)
NOTE: The program default address decode of the SP0256A-AL2's ALD*
input is 2000H. It is re-definable via the EXCEPTION-WORD or USER
eprom. Refer to TABLE 2.
NOTE: MSnibble means most significant nibble, where a nibble is half a byte.
MSB means most significant byte; LSB means least significant byte.
'X' stands for the MSnibble of the MSB of the two byte address, and
can be 1,2,3,4,5,6,7,8,9,A,B,C,D, or E because an eprom may reside
from 1000H to EOOOH.
78
MICROCOMPUTER (8-BIT)
User-Eprom(s): (optional)
If a USER eprom is accompanied by an EXCEPTION-WORO eprom, it may
reside anywhere. If no EXCEPTION-WORD eprom accompanies it then it may
reside anywhere from 1000H to EOOOH providing its start address falls on a 4K
boundary; and it must then begin with the sequence SOH, 48H, 28H, 58H, 85H;
and also contain other reserved locations. If an EXCEPTION-WORD eprom is
present, the USER's program can even reside in an unused portion of the
EXCEPTION-WORD eprom. Refer to APPENDIX-D,E for the applicable USER
EPROM MEMORY MAP.
Interaction between a USER program and the code-to-speech algorithm must
be controlled in an orderly manner, ie; the user must save the processor status
before taking control of the processor for execution of any USER code (except
for character string loading operations, which is described next:)
To prepare the code-to-speech algorithm to process and speak, the USER
program passes the character string it wants spoken into the Accumulator one
character at a time, then calls the routine @SAVE which transfers it into the
input buffer. After the character string loading has been completed, the USER
code can initiate the speech by calling the @SPEAK routine; assuming that a
delimiter followed that character string. After the loaded character string· is
processed and spoken, program control resumes in the hands of the USER pro-
gram by the Branch @ USERCODE instruction.
No registers used by the code-to-speech algorithm may be disturbed by the
USER code during character string loading, (except for the Accumulator).
Prior to the USER code executing anything other than character string load-
ing, all registers used by the code-to-speech algorithm as well as the Stack
Pointer and STATUS register are to be saved. These registers must be recov-
ered prior to future character string loading operations; or prior to initiating
speech.
Because of masked code-to-speech restrictions within the CTS256A-AL2,
Interrupt-1* and Interrupt-3* are not USER accessible. Also, input from the
serial port into the USER code can be obtained, but restrictions apply.
Refer to APPENDIX-F for a discussion of the sequence of events and subrou-
tines necessary for USER/CODE-TO-SPEECH interactions as described above.
79
MICROCOMPUTER (8-BIT)
CTS256AL2 276-1786
TABLE 1.
Hardware selectable option pin-outs of CTS256A-AL2:
PIN 6 7 8
J
0 1 0 BAUD 110
0 1 1 BAUD 300
1 0 0 BAUD 1200 SERIAL INPUT MODE
1 0 1 BAUD 2400
1 1 0 BAUD 4800
1 1 1 BAUD 9600
PIN 9
0 +-PROGRAM DEFAULT UART VALUES (Asynchronous, 7 bits/
character, 2 stop bits, no parity).
1 +-HARDWARE (or FIRMWARE) SELECTED UART VALUES.
PIN 10
0 +- INTERNAL-RAM BUFFERS, (20 BYTE INPUT/26 BYTE OUT-
PUT).
1+- EXTERNAL-RAM BUFFERS, (1792 BYTE INPUT/256 BYTE OUT-
PUT WITH A 2-KBYTE RAM).
80
MICROCOMPUTER (8-BIT)
CTS256AL2 276·1786
TABLE 1. Con't.
PIN 11
0 +- CARRIAGE·RETURN-ONL Y DELIMITER.
1 +- ANY DELIMITER.
PIN 03 "BUSY$" (Input buffer flag is a TTL level output); for RS232
compatibility use MC1488 Line Driver or equiv.
0 _, INPUT BUFFER IS > = 87.5% FULL.
1-> INPUT BUFFER IS < = 50.0% EMPTY.
PIN 16 _, UART RECEIVER (Serial input is a TTL level input); for RS232
compatibility use MC1489 Line Receiver or equiv.
81
MICROCOMPUTER (8-BIT)
CTS256AL2 276·1786
NOTE 2.1 THESE LOCATIONS MUST BE FF, (THEY ARE NOT USER
DEFINABLE).
NOTE 2.2 TO MAINTAIN ANY PARAMETER AT ITS DEFAULT VALUE,
LOAD THAT LOCATION WITH FFH.
NOTE 2.3 IF ANY OF THE EXTERNAL RAM BUFFER PARAMETERS
ARE REDEFINED HERE, ALL OF THEM MUST BE REDE-
FINED HERE.
NOTE 2.4 NO MATTER WHAT ADDRESS IS CHOSEN FOR ALD$, THAT
ADDRESS THRU THAT ADDRESS + 3FH IS RESERVED FOR
SP0256A-AL2 ADDRESSING.
NOTE 2.5 IF ANY OF THE SERIAL PORT PARAMETERS ARE REDE-
FINED HERE, ALL OF THEM MUST BE REDEFINED HERE.
NOTE 2.6 H , AS IN 100H REFERS TO HEXADECIMAL NOTATION.
NOTE 2.7 A NIBBLE IS HALF OF A BYTE, OR 4 BITS.
82
MJCROCOMPUTER (8-BIT)
CTS256AL2 276·1786
TABLE 3. (Cont'd)
XOBC lB LSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "M"
XOBD X2 MSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "N"
XOBE lC LSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "N"
XOBF X2 MSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "0"
xoco 1D LSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "0"
XOCl X2 MSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "P"
xocz lE LSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "P"
XOC3 X2 MSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH " Q"
XOC4 2D LSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "Q"
XOC5 X2 MSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "R"
XOC6 2E LSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "R"
XOC7 X2 MSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "S"
XOCB 2F LSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "S"
XOC9 X2 MSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "T"
XOCA 30 LSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "T"
XOCB X2 MSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "U"
xocc 3D LSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "U"
XOCD X2 MSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "V"
XOCE 5A I:SB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "V"
XOCF X2 MSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "W"
XODO 5B LSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "W"
XODl X2 MSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "X"
XOD2 64 LSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "X"
XOD3 X2 MSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "Y"
XOD4 65 LSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "Y"
XOD5 X2 MSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "Z"
XOD6 6F LSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "Z"
XOD7 X2 MSB OF POINTER TO START EXCEPTION-WORD
BEGINNING WITH "NUMBER OF PUNCTUATION"
XODB 70 LSB OF POINTER TO START EXCEPTION-WORD
L
BEGINNING WITH "NUMBER OF PUNCTUATION"
L The least significant nibble of the MSB and the entire LSB
address locations will vary with a different set of exception
words; X= 1,2,3,4,5,6,7,8,9,A,B,C,D,or E.
83
MICROCOMPUTER (8-BIT)
CTS256AL2 276·1786
XlB4 13 E9 13 6: DB 19,Z33,19,74,7,11,51,6Z,O,lZ,ll,55,13,39,31,16,7,11,Z,141
X1B7 4A 07 OB 33 3E 00 OC OB 37 OD
XlClZ71Fl0070BOZBD
;<(GI]< = (JH EH NNl ERl EL PAl IM NNl SS TTZ RRZ UWZ MM EH NNl PA3 TTZ]
;GENERAL INSTRUMENT
X1C8 13 E9 ZD DB 19,Z33,45,33,41,44,19,74,7,11,51,6Z,O,lZ,l1,55,13,39,31,16,7,ll,Z,141
XlCB Zl Z9 ZC 13 4A 07 OB 33 3E 00
XlD5 OC OB 37 OD Z7 lF 10 07 OB OZ
XlDF 8D
;<[GI][MAIL< = [JH EH NNl ERl EL PAl IH NNl SS TTZ RRZ UWZ MM EH NNl PA3 TT2]
XlEO FF DB Z55
XlEl FF H: DB Z55
XZOD FF J: DB Z55
XZOE FF
.
K: DB Z55
.
XZOF 13 69 36 L: DB 19,105,54,37,164,19,109,1Z,35,3,149; <[LIVED]<= [LL IH VV PA4 DDl] LIVED
XZ1Z Z5 A4 13 6D OC Z3 03 95
XZlA FF DB Z55
XZ1B FF M: DB Z55
XZlC FF N: DB Z55
XZlD FF 0: DB Z55
XZZD FF Q: DB Z55
XZZE FF R: DB Z55
XZZF FF
.
S: DB Z55
84
MICROCOMPUTER (8-BIT)
CTS256AL2 276-1786
TABLE 4. (Cont'd)
XZ30 13 6F 34 T: DB 19,111,5Z,33,172,19,77,53,13,0,15,190;<[TOTAL]< = [TTZ OW TTl PAl AXEL]
XZ33 Zl AC 13 40 35 OD 00 OF BE
XZ3C FF DB Z55
'
XZ3D 13 73 Z5 U: DB 19,115,37,50,41,164,19,113,ZZ,43,51,1,6,0,33,7,11,Z,13,1Z,40,1Z,Z,4Z,Z0,37
XZ40 3Z Z9 A4 13 71 16 ZB 33 01 06
XZ4A 00 Zl 07 OB OZ OD OC ZB OC OZ
XZ54 ZA 14 Z5
XZ57 OF BB DB 15,139;<[USERID]< = [YYl UMl ZZ ERl PAl AY PAl DDZ EH NNl PA3 TTZ IH FF IH
;PA3 KKl EY SH AX NNl]
XZ59 FF DB Z55
XZ5A FF
' DB Z55
V:
85
MICROCOMPUTER (8·BIT)
CTS256AL2 276·1786
TABLE 5. SERI.t}~lORT MODE REGISTER u
l4t>
r-MSIY-
17 I 1.J JJ q 7 ., 5
LSB -
7 6 5 4 3 2 1 0
l
STOP SIO PEVEN PEN CHAR1 CHARO COMM MULTI
I I L 0 =MOTOROLA PROTOCOL
1 = INTEL PROTOCOL
0 = ISOSYNCHRONOUS COMMUNICATION
1 =ASYNCHRONOUS COMMUNICATION
00 = 5 BITS/CHARACTER
01 = 6 BITS/CHARACTER
10 = 7 BITS/CHARACTER
'- 11 = 8 BITS/CHARACTER
1 =PARITY ENABLED
.._ 0 =PARITY DISABLED
1 = EVEN PARITY
'- 0 =ODD PARITY
Example: To program the serial port to operate at 300 baud in the asyn·
chronous mode, the prescaler value is set to 0, and the timer
latch value to 81H.
2 I 1 I L~B -
86
MICROCOMPUTER (8·BIT)
CTS256AL2 276·1786
HOLD OFF TIME, FROM DATA STROBE HI TO LOW TO HI, UNTIL NEXT DATA STROBE HI TO LOW: MIN.
450 uS. ·
NOTE: The addition of an 74LS74 Flip-Flop as shown on the schematic can be used for parallel port latch
handshaking using the Active-LO LATCH-BUSY$ output. LATCH-BUSY$ is LO when the latch is full,
and it is HI when the latch is empty and available for the next character to be strobed in.
87
MICROCOMPUTER (8-BIT)
CTS256AL2 276·1786
APPENDIX-A
Exception-Word Eprom Map (For use without USER eprom present)
NOTE: ENCAPSULATED SEQUENCES ARE USER-DEFINED, REFER TABLES 2,3, AND 4.
XOEO BE F7 4B 8E F7 OF 77 01 OA 05 74 80 OB EO 03 73
XOFO 7F OB BE F3 AF 76 20 OA OE 52 34 AA XO A3 DO 14 The MSnibble of the following locations
X100 AAXO A4 DO 15 EO OF C5 2A 41 2C 02 AAXO A3 DO from the EXCEPTION-WORD ROUTINE are user
X110 14 AAXO A4 DO 15 52 01 BE F4 88 8E F4 C2 76 10 defined also: XOFC,X101,X10D,and X112;
X120 OA 4D 2D FF E2 60 98 11 1D 73 BF OA BE F5 64 76 where X= 1,2,3,4,5,6,7,8,9,A,B,C,D,or E.
X130 10 OA 3C BE F4 7E 74 40 OA 8E F5 64 76 10 OA 42
X140 48 37 34 79 00 35 D5 37 73 FD OB 52 02 8E F4 88
X150 8E F4 9E 98 OF 03 98 03 11 8E F7 4B 77 80 OB OA
X160 DB 39 8E F3 47 C9 C9 8C F1 36 C9 C9 8C F3 F4 D3
X170 15 E7 02 D3 14 52 02 BE F4 88 72 01 37 73 FD OB
X180 EO 99 52 03 EO F1 D9 03 D9 02 D5 37 73 FD OB BC
88
MICROCOMPUTER (8-BIT)
CTS256AL2 276·1786
APPENDIX·B
Exception-Word Eprom Map (For use without USER eprom present)
NOTE: ENCAPSULATED SEQUENCES ARE USER-DEFINED, REFER TABLES 2,3, AND 4.
XOEO BE F7 4B BE F7 OF 77 01 OA 05 74 80 OB EO 03 73
XOFO 7F OB BE F3 AF 76 20 OA OE 52 34 AA 80 A3 DO 14 The MSnibble of the following locations
X100 AA80 A4 DO 15 EO OF C5 2A 41 2C 02 AA80 A3 DO from the EXCEPTION-WORD ROUTINE are user
X110 14 AABO A4 DO 15 52 01 BE F4 88 BE F4 C2 76 10 defined also: XOFC,X101,X10D,and X112;
X1~0 OA 4D 2D FF E2 60 98 11 1D 73 BF OA BE F5 64 76 where X= 1,2,3,4,5,6,7,8,9,A,B,C,D,or E.
X130 10 OA 3C BE F4 7E 74 40 OA BE F5 64 76 10 OA 42
X140 48 37 34 79 00 33 D5 37 73 FD OB 52 02 BE F4 88
X150 BE F4 9E 98 OF 03 98 03 11 BE F7 4B 77 80 OB OA
X160 DB 39 BE F3 47 C9 C9 BC F1 36 C9 C9 BC F3 F4 D3
X170 15 E7 02 D3 14 52 02 BE F4 88 72 01 37 73 FD OB
X180 EO 99 52 03 EO F1 D9 03 D9 02 D5 37 73 FD OB BC
89
MICROCOMPUTER (8-BIT)
CTS256AL2 276-1786
APPENDIX-C
Exception-Word Encoding Scheme
To store a unique word or symbol and its corresponding allophone address string in an efficient and flexible manner, the
following encoding format was derived:
The first and last byte is 13H. This informs the code-to-speech algorithm that the word or symbol is not a prefix or suffix.
If the word or symbol is an individual letter, then the representation of it between the brackets is an FFH; this includes the value of
the left and right brackets.
Otherwise:
(1) The first letter in the word or symbol is always to be ignored.
(2) The next letter in the word is represented by the value of the letter from TABLE-7, plus the value of the left bracket "[" which is
40H.
(3) The following letter(s), if and only if it is not the last letter in the word or symbol, is represented solely by its value from
TABLE-7.
(4) The last letter in the word or symbol is represented by the value of the letter from TABLE-7, plus the value of the right bracket
"]" which is SOH.
If only one allophone is used for the pronunciation, it is represented by its value from T ABLE-6, plus the value of the right " ["
and left "]" brackets which are 40H and SOH respectively.
Otherwise:
(1) The first allophone is represented by its value from TABLE-8, plus the value of the left bracket "[" which is 40H.
(2) The following allophone(s), if and only if it is not the last allophone in the string, is represented by its value from TABLE-8.
(3) The last allophone is represented by its value from T ABLE-8 plus the·value of the right bracket "]" which is SOH.
APPENDIX-D
User Eprom Map (For use without EXCEPTION-WORD eprom)
NOTE: ENCAPSULATED SEQUENCES ARE USER-DEFII'{ED, REFER TABLES 2,3, AND 4.
90
MICROCOMPUTER ( 8-BIT)
CTS256AL2 276-1786
APPENDIX-D (Cont'd)
XOAO LS 8C F3 F4 , . . . - - - - - - - - - - - - - - - - - ,
....------'1 User code may start at XOA4,
Ibut must contain the MAIN-CONTROL-PROGRAM
somewhere within, refer to APPENDIX·:f.
NOTE A. Place the immediate address of the origin of the MAIN-CONTROL-PROGRAM (see APPENDIX-F) in these locations; so
that program control will transfer to the user's code at the appropriate time.
APPENDIX-E
USER EPROM MAP (For use with EXCEPTION-WORD eprom)
NOTE 1. Contains no reserved locations, except for the MAIN-CONTROL-PROGRAM. (See APPENDIX-F).
NOTE 2. A user's code does not have to reside in a second eprom (USER eprom). It may reside in an unused portion of an
EXCEPTION-WORD eprom which is for use where "USER eprom is present". Refer APPENDIX-B.
APPENDIX-F .
USER's MAIN CONTROL PROGRAM (For residency anywhere within USER eprom).
NOTE: ENCAPSULATED AREAS ARE USER DEFINED UNLESS OTHERWISE NOTED.
9000 ORG > 9000 ;This is the origin of the Main Control Program which is defined by the user.
;Here it is arbitrarily chosen to be 9000H. Remember to place this immediate
;address in the "MS","LS" locations of the EXCEPTION-WORD eprom ("for use
;with USER eprom"), see APPENDIX-B. (MS = MSB = 90 and the LS = LSB = 00 in
;this example.)
9000 BEFlAC MESSAGE: CALL @AUDIBLE
+ - - - - - - - THIS ENCAPSULATED AREA IS NOT USER DEFINED - - - - - - - - - +
I The following two lines are placed here only if the user code wishes to gain I
I access to the serial port. I (The XXXX XXXX here does
xxxxxxxx ANDP % > FE,IOCNTl ;DISABLE INTERRUPT-4 (SERIAL not have the same meaning
PORT). as the X from the previous
appendices and tables.)
xxxxxxxx ANDP %FE,PORTB ;SET BUSY* LO.
+------------------------------------------------+
9003 EOOE JMP ANYSTART
91
MICROCOMPUTER (8·BIT)
CTS256AL2 276-1786
APPENDIX-F (Cont'd)
900B 76010B07 SPEAK: BTJO %>0l,F2,ANYSTART
900C 73EFOB AND%>EF,F2
900F 77100BFC CRWAIT: BTJZ %10,F2,CRWAIT
9013 4D0305 ANYSTART: CMP FlLO,RlLO
9016 E607 JNE HOLEWORD
9018 4D0204 CMP FlHI,RlHI
901B E602 JNE HOLEWORD
901D EOE6 JMPCRSTART
901F 7D0038 HOLEWORD:CMP o/o > OO,WORDCNTH
9022 E605 JNE BFULTEST
9024 7D0039 CMP %>00,WORDCNTL
9027 E2F6 JEQ HOLEWORD
9029 770BOB09 BFULTEST: BTJZ o/o > 08,F2,PROCESS
902D 7D0132 LOCKUP: CMP %>01,BUFBVALU
9030 E211 JEQ ESC
9032 760BOBFC BFULHOLD: BTJO o/o > 08,F2,BFULHOLD
9036 BEF3D7 PROCESS: CALL @GISPEECH
9039 4D0709 MAINROUT: CMP F2LO,R2LO
903C E205 JEQ ANYSTART
903E A40100 DRP %>01,10CNTO
9041 EODO JMP ANYSTART
9043 BCFlFO ESC: BR @ESCAPE
9046 00 USERCODE: NOP ;FROM THIS POINT IT IS THE USER CODES RESPONSIBILITY
;TO EXECUTE ITS OWN CODE OR TO LOAD A CHARACTER
;STRING INTO THE INPUT BUFFER.
;THE TWO EXAMPLES SHOWN BELOW DEMONSTRATE THE
;RECOMMENDED SEQUENCE OF EVENTS FOR EACH MODE.
;MODE 1 IS USED WHEN THE USER CODE HAS PREVIOUSLY
;PREPARED THE CHARACTER STRING IT WISHES TO HAVE
;SPOKEN; MODE 2 IS USED WHEN THE USER CODE WISHES
;TO EXECUTE ANYTHING ELSE.
IMODEl: I '
;LOADING
'
INPUT BUFFER OF CODE-TO-SPEECH ALGORITHM:
NOTE: Once "SPEAK" is initiated, control does ' not return to the USERCODE until the last word or phrase that is in the input
buffer has been processed by the code-to-speech algorithm. NOTE: Because of masked code-to-speech restrictions, the USER can
not intercept input from the serial port while speech processing is in progress. During this interval, handshaking (BUSY*) shall
hold off additional serial communication. This is accomplished by the two encapsulated lines shown above.
'
;THE FOLLOWING EXAMPLE WILL LOAD THE LETTER "A" AND
;SPEAK IT:
92
MICROCOMPUTER (8-BIT)
CTS256AL2 276-1786
APPENDIX-F (Cont'd)
.
;THE CHARACTER RECEIVED BY SERIAL PORT IS IN THE ACCUMULATOR,
;SO THE USER MAY EVALUATE IT HERE .
MOV%>08,A
.
;LOAD A "BACKSPACE" INTO ACCUMULATOR IN ORDER TO TELL
CALL @SAVE ;THE CODE-TO-SPEECH INPUT BUFFER TO IGNORE THE CHARACTER
;WHICH ARRIVED VIA THE SERIAL PORT.
;EVALUATE:
;JUMP TO LOOP TO WAIT FOR NEXT SERIAL PORT INTERRUPT (JMP LOOP) .
.
;OTHERWISE: ENABLE INTERRUPT-4 (DRP %>01,IOCNT1), SET BUSY$ LO
;(ANDP %>FE,PORTB),
;THEN FALL THRU TO REST OF USER CODE.
NOTE: To successfully incorporate a USER program with the code-to-speech algorithm requires a thorough understanding of the
concepts described in this application note, and an in-depth working knowledge of PIC7001 assembly language.
.. :~
93
,..
II)
~
><
0 / -3:
(')
"l:j -4 ::0
00-07
.....
""lf
CJ) 0
~
C"J N (')
j100KO
" - [ "ffi"'_,
AO- A7
>
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·~
~-;
...._ '·~ ' i>'
19" '·~ . J .,,
'
t""'
>
"l:j
U1
en
)>
0
3:
"'0
I~ ''•'
74 LS14 +5 l "l:j r- c:
~
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' . " ' - ' t""'
.....
C"J r.)
-4
m
~" -
.....
J
' '" " ~• •,_ "" > ~ ::0
~•m
1-- ~ .....
"~.
' .. - ""' ''•" •, qI Z ,."
... ....~ .....
oO Y"' "' ' " L.:23_ _ _ _
·~rl~
3 2 v, J Cl> co
oo • " • '5 17 " 0 "' a,
-~~
'··' "7 '• "• ',.,• z
s
u
=
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m
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I
-.
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d
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_]-
-
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GR .... +l 00 • ' 4 • •M ·' • " • ' "
12 04 ' 1 d5 16 h T 10 lJi OSC1'-=--r---
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• .... • • " " oco j -'·
lf R
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0 . .. 1.-1'
311 ' 0000' " 1"-i • • """ =·
lt13c~(~~~H-~2F~~~-------~---1j-------~;;-:
p40 v., 38 11 c " LRQ• Cr,s1al (J A . "
r1~2~(~~·~~--------i-------1----~200=H~_,.,~
''
- 12
•
6 A12 22 ~ B
• ••• -
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FFH) 9 300DH_,.,6 1\1-il/)
·~·-·~'·
f
" ~·-·•
_- 1 Voo Y, 3000H 3FFFH) I•
~~. ~ -~'"
"---------.8' A14 ·,
~-9
0 • -' "' .. ..
oo ,: "' "• ',- ''L "' • _ _.m, Wit
0 " 39 • "' '·
0
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o- ENABLE.() Y, 6000H-6FFFH
u
00
"
00
INT3#
_ , rn:_, ,! V.,
...->loa -•m• ::
I ~-------+-~,J,.·~-L=-=-=-=-=-=-=-=-=-=-=-=-=-=--::_
Lk 1 o 26 ~3
1
A9
A10 24 A9
A10 INT2· I _____________
.2.-K R/W1 1 RJW:_,..,8
~~·".
. 23
q~i---=j )
~':' ,. ,
22pF
1Fi ,~.
·-"' 1- - r~ __',":'__
6 LM386
~
~Kn ~5
1 -·H-j I 4~
0.1.1 .......... 8 100.1
VOLUME 3 +
,- 0~
10Kn
\ 2 -
I I ~
.f .f
. 4c
~N
7 100 --
~. ~ K
}.~
r-
AO-A11
D0-07
1K t-:l
-<
....
"'=
n
->
~r:-'
m>
:II-=
., B
~
01
1
!6-=
::!r:-'
02
zn
O""
03 Aa 5 .,.;
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14 I 2732A-30
04 A4 4
~
::_ ....
t-:l
~
0
6
OS
06
... ., 3
. ~
0: z
1
07 . ,, - - MSB
I oc·
PARALLEL
PORT (optional)
3:
0
'-"' ::tJ
~('\
0
('"' ,-·--{_ ~ flv-Cl 0 0
r '\ EXTERNAL
~ ~XPROM - TERNAL ~ ~ ~
~-'', 4-- -1 0
en
,c
RAM (optional) (opllonal) •
~ ~ " EXCEPTION-W? RO :;_ ~ •
.,.
• i) ...... EX: 2K Byte
AND/OR ~ usER ,......,., ,
N 3:
EX' 4K Byle ~ CV U U1
~ -~ en
" ~
~ .....,
"' "'r;-'
- .... 'l:..ct- ,.,..,
:)"-,;. l
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r-
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.
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-
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~ ~ '~<;....__ .......
~
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I
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" Ql
-
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ID
":'1---""
' l " "' =i
Ul
~
~
N-CHANNEL MOS (AUDIO)
GENERAL DESCRIPTION
The SP0256 (Speech Processor) is a single chip N-Channel MOS LSI device
that is able, using its stored program to synthesize speech or complex sounds.
PIN CONNECTION
The achievable output is equivalent to a flat frequency response ranging TOP VIEW
from 0 to 5KHz, a dynamic range of 42dB, and a signal to noise ratio of Yss
approximately 35 dB.
The SP0256 incorporates four basic functions:
A. A software programable digital filter that can be made to model a VOCAL
\ ROM DISABLE
TRACT.
B. A 16K ROM which stores both data and instructions (THE PROGRAM). ~ C1
C. A MICROCONTROLLER which controls the data flow from the ROM to
the digital filter, the assembly of the "word settings" necessary for linking \ C2
FEATURES
• Natural Speech
• Wide Operating Voltage
• Simple Interface to Most Microcomputers or Microprocessors
• Supports L.P.C. Synthesis: Formant Synthesis: Allophone
Synthesis
STANDARD CONDITIONS
Clock-Crystal Frequency 3.120 MHz
OUTPUT!-----! Alii
0.022p.~
SP0256 10K
INPUT I+-----1SBY
INPUTI(;:-----!Dffi
+SV
96
N-CHANNEL MOS (AUDIO)
SP0256 276-1784
BLOCK DIAGRAM C1
C2
C3
SER
OUT
SERIAL COEFFICIENT TRANSFER
97
N-CHANNEL MOS (AUDIO)
SP0256 21s-11s4
PIN FUNCTIONS
PIN NUMBER NAME FUNCTION
1 Vss Ground
2 RESET A logic 0 resets that portion of the SP powered by Vo0 . Must be returned to a logic 1
for normal operation.
3 ROM DISABLE For use with an external serial speech ROM, a logic 1 disables the external ROM.
4,5,6 C1, C2, C3 Output control lines for use,with an external serial speech ROM.
7 Voo Power supply for all portions of the SP except the microprocessor interface logic.
8 SBY STANDBY. A logic 1 output indicates that the SP is inactive and V00 can be pow-
ered down externally to conserve power. When the SP is reactivated by an address
being loaded, SBY will go to a logic 0.
9 LRQ LOAD REQUEST. LRQ is a logic 1 output whenever the input buffer is full. When
LRQ goes to a logic 0, the input port may be loaded by placing the 8 address bits on
A1-A8 and pulsing the ALD output.
10, 11, 13, 14, A8, A7, A6, A5, 8 bit address which defines any one of 256 speech entry points.
15, 16, 17, 18, A4, A3, A2, A1
12 SEROUT SERIAL ADDRESS OUT. This output transfers a 16-bit address serially to an exter-
nal speech ROM.
19 SE STROBE ENABLE. Normally held in a logic 1 state. When tied to ground, ALD is
disabled and the SP will automatically latch in the address on the input bus approxi-
mately 11-'s after detecting a logic 1 on any address line.
20 ALD ADDRESS LOAD. A negative pulse on this input loads the 8 address bits into the
input port. The negative edge of this pulse causes LRQ to go high.
21 SERIN SERIAL IN. This is an 8-bit serial data input from an external speech ROM.
22 TEST This pin should be grounded for normal operation.
23 VD1 Power supply for the microprocessor interface logic and controller.
24 DIGITAL OUT Pulse width modulated digital speech output which, when filtered by a 5KHz low
pass filter and amplified, will drive a loudspeaker.
25 SBYRESET STAND BY RESET. A logic 0 resets the microprocessor interface logic and the
address latches. Must be returned to a logic 1 for normal operation.
26' ROM CLOCK This is a 1.56MHz clock output used to drive an external serial speech ROM.
27 OSC1 XTAL IN. Input connection for a 3.12MHz crystal.
28 OSC2 XTAL OUT. Output connection for a 3.12MHz crystal
INTRODUCTION
The allophone speech synthesis technique provides the user with the ability
to synthesize an unlimited vocabulary at a very low bit rate. Fifty-nine discrete
speech sounds (called allophones) and five pauses are stored at different
addresses in the SP0256 internal ROM. Each speech sound was excised from
a word and analyzed using linear predictive coding (LPC). Any English word
or phrase can be created by addressing the appropriate combination of allo-
phones and pauses. Since there is ·a total of 64 address locations each requires
a 6 bit address. Assuming that speech contains 10 to 12 sounds per second,
allophone synthesis requires addressing less than 100 bits per second.
LINGUISTICS
A few basic linguistic concepts will help you start your own library of "allo-
phone words". (See Table 1 for Allophone Dictionary). First, there is no one-
to-one correspondence between written letters and speech sounds; secondly,
speech sounds are acoustically different depending upon their position within
98
N-CHANNEL MOS (AUDIO)
SP0256 276-1784
LINGUISTICS (Continued)
a word; and lastly, the human ear may perceive the same acoustic signal differ-
ently in the context of differe.n t sounds.
The first point compares to the problem that a child encounters when learn-
ing to read. Each sound in a language may be represented by more than one
letter and, conversely each letter may represent more than one sound. (See the
examples in Table 2.) Because of these spelling irregularities, it is necessary to
think in terms of sounds, not letters, when using allophones.
The second, and equally important, point to understand, is that the acoustic
signal of a speech sound may differ depending upon its position within a
word. For example, the initial K sound in coop will be acoustically different
from the K's in keep and speak. The K's in coop and keep differ due to the influ-
ence of the vowels which follow them, and the final K in speak is usually not as
loud as initial K's.
Finally, a listener may identify the same acoustic signal differently depend-
ing on the context in which it is perceived. Don't be surprised, therefore, if an
allophone word sounds slightly different when used in various phrases.
PHONEMES OF ENGLISH
The sounds of a language are called phonemes, and each language has a set
which is slightly different from that of other languages. Table 3 contains a
chart of all the consonant phonemes of English, table 4 all the vowel pho-
nemes.
Consonants are produced by creating an occlusion or constriction in the
vocal tract which produces an aperiodic sound source. If the vocal cords are
vibrating at the same time, as in the case of the voiced fricatives VV, DH, ZZ,
and ZH, (See Table 5) there are two sound sources: one which is aperiodic and
one which is periodic.
Vowels are usually produced with a relatively open vocal tract and a peri-
odic sound source provided by the vibrating vocal cords. They are classified
according to whether the front or back of the tongue is high or low (See Table
4) whether they are long or short, and whether the lips are rounded or
unrounded. In English all rounded vowels are produced in or near the back of
the mouth (UW, UH, OW, AO, OR, AW).
Speech sounds which have features in common behave in similar ways. For
example, the voiceless stop consonants PP, TT and KK (See Table 3) should be
preceded by 50-80 msec of silence, and the voiced stop consonants BB, DD,
and GG by 10-30 msec of silence.
ALLOPHONES
Phoneme is the name given to a group of similar sounds in a language.
Recall that a phoneme is acoustically different depending upon its position
within a word. Each of these positional variants is an allophone of the same
phoneme. An allophone, therefore, is the manifestation of a phoneme in the
speech signal. It is for this reason that our inventory of English speech sounds
is called an allophone set.
99
N-CHANNEL MOS (AUDIO)
SP0256 21s-11s4
100
N-CHANNEL MOS (AUDIO)
SP0256 21s-11a4
101
N-CHANNEL MOS (AUDIO)
SP0256 27&-1784
ALLOPHONE DICTIONARY
DICTIONARY (Continued)
legislating LL EH EH PAZ JH JH SS SS LL EY sweat SS SS WW EH EH PA3 TTZ
PAZ PA3 TT Z IH NG sweated SS SS WW EH EH PA3 TTZ IH PA3
legislature LL EH EH PAZ JH JH SS SS LL EY DD1
PAZ PA3 CH ER1 sweater SS SS WW EH EH PA3 TTZ ER1
letter LL EH EH PA3 TTZ ER1 sweaters SS SS WW EH EH PA3 TTZ ER1 ZZ
litter LL IH IH PA3 TTZ ER1 sweating SS SS WW EH EH PA3 TTZ IH NG
little LL IH IH PA3 TTZ EL sweats SS SS WW EH EH PA3 TTZ SS
memory MM EH EH MM ERZ IY switch SS SS WH IH IH PA3 CH
memories MM EH EH MM ERZ IY ZZ switched SS SS WH IH IH PA3 CH PA3 TTZ
minute MM 1H NN1 IH PA3 TTZ switches SS SS WH IH IH PA3 CH IH ZZZ
month MMAXNN1 TH switching SS SS WH IH IH PA3 CH IH NGZ
nip NN1 IH IH PAZ PA3 PP system SS SS IH IH SS SS PA3 TTZ EH MM
nipped NNZ IH IH PAZ PA3 PP PA3 TTZ systems SS SS IH IH SS SS PA3 TTZ EH MM
nipping NN1 IH IH PAZ PA3 PP IH NG zz
nips NN1 IH IH PAZ PA3 PP SS talk TTZ AO AO PAZ KKZ
no NNZAXOW talked TTZ AO AO PA3 KKZ PA3 TTZ
physical FF FF IH ZZ IH PA3 KK1 AXEL talker TTZ AO AO PA3 KK1 ER1
pin PP IH IH NN1 talkers TTZ AO AO PA3 KK1 ER1 ZZ
pinned PP IH IH NN1 PAZ DD1 talking TTZ AO AO PA3 KK1 IH NG
pinning PP IH IH NN1 IH NG1 talks TTZ AO AO PAZ KKZ SS
pins PP IH IH NN1 ZZ thread TH RR1 EH EH PAZ DD1
pledge PP LL EH FH PA3 JH threaded TH RR1 EH EH PAZ DDZ IH PAZ
pledged PP LL EH EH PA3 JH PAZ DD1 DD1
pledges PP LL EH EH PA3 JH IH ZZ threader TH RR1 EH EH PAZ DDZ ER1
pledging PP LL EH EH PA3 JH IH NG threaders TH RR1 EH EH PAZ DDZ ER1 ZZ
plus PP LL AX AX SS SS threading TH RR1 EH EH PAZ DDZ IH NG
ray RR1 EH EY threads TH RR1 EH EH PAZ DDZ ZZ
rays RR1 EH EYZZ then DH1 EH EH NN1
ready RR1 EH EH PAl DDZ IY time TTZAAAYMM
red RR1 EH FH PAl DD1 times TTZ AA AY MM ZZ
robot RR1 OW PAZ BBZ AA PA3 TTZ uncle AX NG PA3 KK3 EL
robots RR1 OW PAZ BBZ AA PA3 TTl SS whale WWEYEL
score SS SS PA3 KK3 OR whaler WWEYLLER1
second SS SS EH PA3 KK1 IH NN1 PAZ DD1 whalers WW EY LL ER1 ZZ
sensitive SS SS EH EH NN1 SS SS IH PAZ whales WWEYELZZ
PA3 TTZ IH VV whaling WWEYLLTHNG
sensitivity SS SS EH EH NN1 SS SS IH PAZ year YYZYR
PA3 TTZ IH VV IH PAZ PA3 TTZ IY yes YYS EH EH SS SS
sincere SS SS IH IH NN1 SS SS YR
sincerely SS SS IH IH NN1 SS SS YR LL IY
sincerity SS SS IH IH NN1 SS SS EH EH RR1
IH PAZ PA3 TTZ IY
sister SS SS IH IH SS PA3 TTZ ER1
speak SS SS PA3 IY PA3 KKZ
spell SS SS PA3 PP EH EH EL
spelled SS SS PA3 PP EH EH EL PA3 DD1
speller SS SS PA3 PP EH EH EL ERZ
spellers SS SS PA3 PP EH EH EL ERZ ZZ
spelling SS SS PA3 PP EH EH EL IH NG
spells SS SS PA3 PP EH EH EL ZZ
start SS SS PA3 TTZ AR PA3 TTZ
started SS SS PA3 TTZ AR PA3 TTZ IH PAl
DDZ
starter SS SS PA3 TTZ AR PA3 TTZ ER1
starting SS SS PP3 TTZ AR PA3 TTZ IH NG
starts SS SS PP3 TTZ AR PA3 TTl SS
stop SS SS PA3 TTl AA AA PA3 PP
stopped SS SS PA3 TTl AA AA PA3 PP PA3
TTZ
stopper SS SS PA3 TTl AA AA PA3 PP ER1
stopping SS SS PA3 TTl AA AA PA3 PP IH
NG
stops SS SS PA3 TTl AA AA PA3 PP SS
subject (noun) SS SS AX AX PAZ BB1 PAZ JH EH
PA3 KKZ PA3 TTZ
subject (verb) SS SS AX PAZ BB1 PAZ JH EH EH
PA3 KKZ PA3 TTZ
102
N-CHANNEL MOS (AUDIO)
SP0256 21s-11a4
TABLE3-CONSONANTPHONEMESOFENGLISH
LABIO- INTER- ALVEO-
LABIAL DENTAL DENTAL LAR PALATAL VELAR GLOTTAL
Stops: Voiceless pp TT KK
Voiced BB DD GG
Fricatives: Voiceless WH FF TH ss SH HH
Voiced vv DH zz ZH*
Affricates: Voiceless CH
Voiced JH
Nasals Voiced MM NN NG*
Resonants Voiced ww RR,LL yy
TABLE4-VOWELPHONEMESOFENGLISH
FRONT CENTRAL BACK
High YR
IY UW#
IH* UH*#
Mid EY ER OW#
EH* AX* OY#
XR
Low AE* AW# AO*#
AY OR#
AR
AA*
*SHORT VOWELS
#ROUNDED VOWELS
103
N-CHANNEL MOS (AUDIO)
SP0256 276·1784
104
N-CHANNEL MOS (AUDIO)
SP0256 21s-11a4
105
N·CHANNEL ION IMPLANT (SOUND GENERATOR)
GENERAL DESCRIPTION
The AY-3-8910A Programable Sound Generator (PSG) is an LSI circuit which
can produce a wide variety of complex sounds under software controL The PIN CONNECTION
AY-3-8910A is manufactured in the Microelectronics N-Channel Ion Implant TOP VIEW
FEATURES
• Full software control of sound generation
• Interfaces to most 8-bit and 16-bit microprocessors
.. Three independently programmable analog outputs
• One or two 8-bit I/0 ports
• Full 0° to 70°C operation
PIN FUNCTIONS
DA7-DAO (Input/Output/High Impedance)
Data/Address Bits 7-0: Pins 30-37
These 8 lines comprise the 8-bit bidirectional bus used by the microproces-
sor to send both data and addresses to the PSG, and to receive data from the
PSG. In the address mode, DA3- DAO select the internal register address
(0- 17s) and DA7-DA4 in conjunction with address inputs A9 and A8, form the
chip select function. When the high order address bits are "incorrect," the
bidirectional buffers are forced to a high impedance state.
Address 9, Address 8
A8 (input): Pin 25
A9 (input): Pin 24
High order address bits A9 and A8 are fixed to recognize a "01" code. They
may be left unconnected, as each is provided with either an on-chip pull-down
(A9) or pull-up (A8) resistor. In noisy environments, however, it is recom-
mended the A9 and A8 be tied to external ground and + 5V respectively, if
they are not to be used.
RESET (Input): Pin 23
For initialization/power-on purposes, applying a low level input to the
RESET pin will reset all registers to 08 • The RESET pin is provided with an
on-chip pull-up register.
CLOCK (Input): Pin 22
This TTL compatible input supplies the timing reference for the Tone,
Noise, and Envelope Generators.
BDIR, BC2, BC1 (Inputs): Pins 27, 28, 29
BUS Direction, BUS Control 2, Bus Control 1
These bus control signals are generated directly by a microprocessor to
control all bus operations internal and external to the PSG.
106
N·CHANNEL ION IMPLANT (SOUND GENERATOR)
AV-3-891 OA 276·1787
PSG
BDIR BC2 BCt FUNCTION PSG
-- -- - - --
0 1 0 INACTIVE.
1 1 READ FROM PSG.
>-- BDIR
0
1 1 0 WRITE TO PSG.
1 1 1 LATCH ADDRESS. FROM +5- BC2
PROCESSOR
> - BC1
~
Pins 2, 5, 26, 39
These pins are for test purposes only and should be left open. Do not tt'se as
tie-points.
Vee: Pin40
Nominal + 5 Volt power supply to the PSG.
Vss: Pin 1
Ground reference for the PSG.
ARCHITECTURE:
The AY·3·8910A is a register oriented Programable Sound Generator (PSG).
Communication between the processor and the PSG is based on the concept of
memory-mapped I/0. Control ·commands are issued to the PSG by writing to
16 memory-mapped registers. Each of the 16 registers within the PSG is also
readable so that the microprocessor can determine, if necessary, present states
or stored data values. All functions of the PSG are controlled through the 16
registers which, once programmed, generate and sustain the sounds, thus
freeing the system processor for other tasks.
REGISTER ARRAY:
The principal element of the PSG is the array of 16 read/write control regis·
ters. These 16 registers look to the CPU as a block of memory and, as such,
occupy a 16-word block out of 1,024 possible addresses. The 10 address bits (8
bits on the common data/address bus, and 2 separate address bits) are decoded
as follows:
HIGH LOW
ORDER ORDER
(Chip Select) (Register No.)
The four low order address bits select one of the 16 registers (RO-R17 8 ). The
six high order address bits function as chip selects to control the tri-state bidi·
rectional buffers (when the high order address bits are incorrect, the bidirec·
tional buffers are forced to a high impedance state). High order address bits
A9, A8 are fixed in the PSG design to recognize a "01" code; high order
address bits DA7-DA4 are programmed to recognize only a "0000" code. All
addresses are latched internally. This internally latched address is updated and
modified on every latch address signal presented to the PSG via the BDIR,
BC2, and BC1 inputs. A latched address will remain valid until the receipt of a
new address, enabling multiple reads and writes of the same register contents
without the need for redundant re-addressing.
Conditioning of the Register Address Latch/Decoder and the Bidirectional
Buffers to recognize the bus function required (Inactive, Latch Address, Write
Data), is accomplished by the Bus Control Decode block.
107
N-CHANNEL ION IMPLANT (SOUND GENERATOR)
AV-3-8910A 276-1787
OPERATION
Since all PSG functions are processor controlled by writing to the internal
registers, a detailed description of the PSG operation may best be accom-
plished by relating each PSG function to control of the corresponding register.
The function of creating or programming a specific sound effect logically fol-
lows the control sequence listed:
108
N·CHANNEL ION IMPLANT (SOUND GENERATOR)
AY-3-8910A 276·1787
I B7 I B6 I B5 I B4 I B3 I B2 I B1 I BO I
Not Used 5·bit Noise Period (NP)
to Noise Generator
I B7 B6 B5 I B4 I B3 B2 I B1 I BO
I
Input
/
Function: · Enable
Port: B IA
109
N·CHANNEL ION IMPLANT (SOUND GENERATOR)
AY-3-891 OA 276-1787
NOISE ENABLE TRUTH TABLE TONE ENABLE TRUTH TABLE I/0 PORT TRUTH TABLE
R7 Bits Noise Enabled R7 Bits Tone Enabled R7 Bits I/0 Port Status
B5 B4 B2 on Channel B2 B1 BO on Channel B7 B6 IIOB I/OA
0 0 0 c B A 0 0 0 c B A 0 0 Input Input
0 0 1 c B - 0 0 1 c B - 0 1 Input Output
0 1 0 c - A 0 1 0 c - A 1 0 Output Input
c - - 1 1 Output Output
0 1 1 c - - 0 1 1
1 0 0 - B A 1 0 0 - B A
1 0 1 - B - 1 0 1 - B -
1 1 0 - - A 1 1 0 - - A
1 1 1 - - - 1 1 1 - - -
NOTE: Disabling noise and tone does not turn off a channel. Turning a chan-
nel off can only be accomplished by writing all zeros into the corresponding
Amplitude Control Register.
Amplitude Control
(Registers R10, R11, R12)
The amplitude of the signals generated by each of the three D/A Converters
(one each for Channels A, B, and C) is determined by the content of the lower
bits (B4-BO) ofregisters R10, R11, and R12 as illustrated.
These five bits consists of a 1-bit mode select ("M" bit) and a 4-bit "fixed"
amplitude level (L3-LO). When the M bit is low, the output level of the analog
channel is defined by the 4-bit "fixed" amplitude level of the Amplitude Con-
trol Register. This amplitude level is fixed in the sense that the amplitude level
is under direct control of the system processor. When the M bit is high, the
output level of the analog channel is defined by the 4-bits of the Envelope
Generator (bits E3-EO). The amplitude mode bit can also be thought of as an
"envelope enable" bit.
I B7 I B6 I B5 I B4 I B3 I B2 I B1 I BO l
" Not used /\} '\.'\.
M I L3 I L2 I L1 I LO I
Amplitude 4 bit fixed
Mode Amplitude Level
0 0 0 0 0 Amplitude Defined
' ' ' ByLO-L3
' ' '
' ' '
0 1 1 1 1
1 X X X X Amplitude Defined
By EO-E3
110
N-CHANNEL ION IMPLANT (SOUND GENERATOR)
AY-3-8910A 276·1787
Envelope Envelope
Coarse Tune Fine Tune
Register R14 Register R13
NOTE: If the Coarse and Fine Tune registers are both set to 0008 , the
resulting period will be minimum, i.e., the generated tone period will
be as if the Coarse Tune register was set to 000 8 and the Fine Tune
register set to 001 8 •
Envelope Shape/Cycle
Control Register (R15)
Alternate To
Envelope
Attack Generator
L---------+ Continue
Bit 0: HOLD When this is set high (logic 1) the envelope is limited to
one cycle, the value of the envelope at the end of the
cycle being held.
Bit 1: ALTERNATE When set high (logic 1) the envelope counter reverses
direction at end of each cycle (i.e. performs as an up/
down counter).
Bit 2: ATTACK When set high (logic 1) the envelope counter will count
up (attack). When set low (logic 0) the counter will count
down (decay).
Bit 3: CONTINUE When set high (logic 1) the cycle pattern will be defined
by the HOLD bit. When set low (logic O) the envelope
counter will reset to 0000 after one cycle, and hold that
value.
111
N-CHANNEL ION IMPLANT (SOUND GENERATOR)
AY-3-8910A 276-1787
D/A CONVERTER OPERATION
Since the primary use of the PSG is to produce sound for the non-linear
amplitude detection mechanism of the human ear, the D/A conversion is per-
formed in logarithmic steps with a normalized voltage range from 0 to 1 volt.
The specific amplitude control of each of the three D/A Converters is accom-
plished by the three sets of 4 bit outputs of the Amplitude Control block, while
the Mixer outputs provide the base signal frequency (Noise and/or Tone).
(See Fig. 3).
NORMALIZED
VOLTAGE
1V 15 15
0 0 X X
13 13
0 1
-- DECIMAL VALUE
12 _..- OFE3E2E1 EO
1 0
1 0
EP ENVELOPE PERIOD
• I I
•
• ~ I I
GRAPHIC REPRESENTATION OF
THE DECIMAL VALUES OF
ENVELOPE GENERATOR
·- ... r
I
OUTPUT E3 E2 E1 EO
' lJ 1. . . . . ~
112
N-CHANNEL ION IMPLANT (SOUND GENERATOR)
AY-3-8910A 276·1787
STATE TIMING
While the state flow for many microprocessors can be somewhat involved
for certain operations, the sequence of events necessary to control the PSG is
simple and straightforward. Each of the three major state sequences (Latch
Address, Write to PSG, and Read from PSG) consists of several operations
(indicated below by rectangular blocks), defined by the pattern of bus control
signals (BDIR, BCl).
OUTPUT
ADDRESS
INACTIVE
1 - - - - - - - - - - - Ad~;;~~~n:e~~=~~ata
The functional operation and relative timing of the PSG control sequences
are described in the following paragraphs.
BDIR
I
BC1
I
I
BUS
CONTROL
NACT
~ INTAK
~ NACT
DA7-DAO
DON'T
CARE
X OUTPUT
ADDRESS
X DON'T
CARE
"'I- 1••
Reset Timing
~/,....--- : ::
BUS
CONTROL
DECODE
INACTIVE ~ LATCH
ADDRESS
wa
~
INACTIVE
AliAB ADDRESS•
DA7-DAO
'-------v"
~ BUS CONTROL
~ SIGNALS CHANGING "BDIR BC1
1 1
113
N·CHANNEL ION IMPLANT (SOUND GENERATOR)
AY-3-891 OA 21s-11s7
BDIR
BOlA
BC1
I BC1
I
I I
BUS
CONTROL
NACT
~ DWS
~ NACT BUS
CONTROL
NACT
~ DTB
~ NACT
~---------- v,
' - - - - - - - - - - - v"
~-iA------- v,
~~·- - - - - - - v"
BOIR/
BC1
BUS
CONTROL
INACTIVE ~ READ FROM PSG· ~ INACTIVE
DECODE
-1,,.1 --LI~
DA7-0AO
--~-~-~-~O-U-S-----,xr--R-EA-0V-A-l-ID-D-AT-A---,x;--T-R-IS-TA_T_E - - V,
BUS
CONTROL
Voc DECODE
AWE -----.._
r--·,.~ r---- v,
"'-------~/
1 PREVIOUS
VAllO DATA
STATE
~
BUS CONTROL *BOlA BC1 ~ BUS CONTROL
SIGNALS CHANGING 0 1 ~ SIGNALS CHANGING
---l 1-- SOns MAX, Including Skew ~ ~ SOns MAX, Including Skew
BC1
114
FM RECEIVER
FM RECEIVER
TDA7000
276-1304
PIN CONNECTION
GENERAL DESCRIPTION
TOP VIEW
The TDA7000 is a monolithic integrated circuit for mono FM portable
radios, where a minimum on peripheral components is important (small
dimensions and low costs).
The IC has an FLL (Frequency-Locked-Loop) system with an intermediate
frequency of 70 kHz. The i.f. selectivity is obtained by active RC filters. The
only function which needs alignment is the resonant circuit for the oscillator,
thus selecting the reception frequency. Spurious reception is avoided by
means of a mute circuit, which also eliminates too noisy input signals. Special
precautions are taken to meet the radiation requirements.
The TDA7000 includes the R.F. input stage, mixer, local oscillator, l.F.
amplifier/limiter, phase demodulator, mute detector and mute switch.
TYPICAL APPLICATIONS
AUDIO AMPLIFIER AND DETUNING INDICATOR
CIRCUITS
Audio output stages suitable for use with the TDA7000 are shown in Fig. E
and F. Figure G shows how the muting .s ignal can be used to operate a LED to
give an indication of detuning.
470k0
80
Frain pin 1 of the
TDA7000 (Fig. A)
115
FM RECEIVER
TDA7000 276-1304
TYPICAL APPLICATION
C18 C17
330pF
220pF
18 17 12 11 10
4.7k0
I
I I
I I
I
: CORRELATOR _______________
F.M. DEMODULATOR .JI
L----------
C1
C4
150nF
10nF
a.t. output
Fig. A The TOA7000 as a variable c1pacitor tuned f.m. broadcast monitor.
C 7 to C 12 , C, 7 and C18:
Filter and demodulator capacitors. The values shown are for an i.f. of 70 kHz.
For other intermediate frequencies, the values of these capacitors must be
changed in inverse proportion to the i.f. change.
c,4:
Decouples the reverse r.f. input. It must be connected to the common return
via a good quality short connection to ensure a low-impedance path. Inductive
or capacitive coupling between C14 and the local-oscillator circuit or i.f. output
components must be avoided.
C,s:
Decouples the d.c. feedback for i.f. limiter/amplifier LAl.
C 19 and'C21 :
Local-oscillator tuning capacitors. Their values depend on the required tuning
range and on the value of tuning capacitor C20 •
Rz:
The load for the audio output current source. It determines the audio output
level, but its value must not exceed 22 kO for VP =4.5 V, or 47 kO for VP =9 V.
116
FM RECEIVER
TDA7000 21s-13o4
TYPICAL APPLICATIONS
100kO 8211
BZX79·
3VO 56nH TOA7000
(Fig. A)
BC558
300k0
1.5kl1
ov---4--------4----------------- pin 16
Fig. B Variable-capacitance diode tuning for the local-ocillator. Additional
measures must be taken to ensure temperature stability.
117
FM RECEIVER
TDA7000 21s-13o4
TYPICAL CHARACTERISTICS
+20
2
20(1og)~) +10
Ptot
..
1'\
(W}
(dB) 0
1.5
-10
"- ""'-~ 25dB
"' \ ~
I
-20
\ -30 I
1 I
-40 I
I
I
r\
-50
I
0.5 -60
' t\. 0
Fig. D
5 10 15 f(kHz)
0
-50 0 50 100
\ 150
Power derating curve. lamb (oC)
v,
(dB}
S+N
(75mV)
I"'"
/.
-20
~ r-.. II'
..__ li t'
THO
1 (%}
-40
"' ....... 10
~-;:, ~ THO
Vrl
.,.
pf
1---- 14
TOA 7000
-60
NOI E
v 5
0
10 ' 10 5 10 4 1o-3 1o-2 10 1 1
Vrt(e.m.f.)
118
QUICK CASE REFERENCE
~=D== 0
o.o34 o.1 o7 I- !
0.028 0.080 ~
May show color bands to denote polarlly.
~~f ioI I ::
Positive: Red or Square Lead
-'--+-------+-- 0 312
0 450
0 250 I I I MIN
0.161
0.151
or~
MAX
-
1
?I
0043
0038
-~:
~
.210
~[J.@jt=I'""
.500
t+
SEATING PLANE -1 SEATI~ANE-j /%~~
.018
.016
0.210
0.170
rr-------t-I
I
0.500
MIN --
1--- 0.625 --j--- 0.562
0.147
o;.~o .5so I o.soo
l 0.230
0.270
~ MAX
Tl
0.650
l- l 0.580
MAX
[J
o.o21
0.016 ~
=3
"""""2
! <=>1
I
' 0.125
SEATING PLANE
j~ 65
0
0
o.2o5
-
0.175
I
0.405
0.395
L
0.210 j___J o.25oL _
I 0.035
0.020
3
2
1
1
~rlpll U
0.139
0.161
0.250
MAX
0.020
0.045
,:
0.230 I I MAX '
119
QUICK CASE REFERENCE
ll•fiN-!:11
0.255 0.365
o.23s,----r-D.36o- r o.soo
0.582l
ils\1 1
0.147
0.142
0.130
0.110
u~; o.o3s
0.025
at:J
i__l_o,oo
' 0.140
1·BASE
2·COLLECTOR :1
13·EMITIER
4-COLLECTOR
120
QUICK INDEX
PAGE
CATEGORY NUMBER
121
MASTER INDEX BY CATALOG NUMBER
122
IMPORTANT SUGGESTIONS ON THE USE
AND REPLACEMENT OF TRANSISTORS
You can use various styles and sizes of transistors in Caution: It may be necessary in some cases to adjust
any given circuit application, as long as the electrical bias values to achieve required operation. With tuned
characteristics of the device are within the required circuits, it is a good practice to check alignment after
range of operation. Thus, a tab-type device can be used replacing any transistor.
to replace a T0-3 or T0-66 case device; or a small When replacing power transistors, always check
epoxy-type device can be used in place of T0-5 or driver devices to be sure they are OK. Also, check
other size transistor. other circuit components to be sure they were not
shorted (or otherwise defective) when the original
Generally speaking, you must observe the following
device failed. If you fail to correct such problems
maximum characteristics of a transistor when con-
before applying power to the circuit once again, there-
templating substitution or selection:
placement transistor could easily be permanently
Power dissipation
damaged. Be sure to use proper heat-sink precautions
Maximum collector current
and use silicon grease to reduce the thermal resistance
Maximum collector-to-emitter voltage
between the case of the transistor and the heat-sink.
Maximum collector-to-base voltage
Always observe temperature limitations as specified
Maximum emitter-to-base voltage
with transistor ratings.
Also, it is useful to consider the following charac- It almost goes without saying, but let us remind you
teristics for actual circuit operation: anyway-
Gain Always observe voltage polarity with all semicon-
Frequency limitations ductor devices.
CROSS-REFERENCE/SUBSTITUTION LISTING
Most users of semiconductors realize that it is al- when making exact replacements (junction capaci-
most impossible to guarantee absolute equivalents (as tances normally vary between devices even from the
in the case of tubes). Thus, the only way to create re- same production run).
placement or cross-reference listings is by carefully
evaluating each characteristic of both devices (original
transistor and the possible alternate). This is how the Information contained in this guide is based on the
Technical Staff of Radio Shack went about preparing latest available data and is believed to be accurate.
the following cross-reference/replacement lists. Every care has been taken to assure technical ac-
curacy. However, Radio Shack does not assume re-
IMPORTANT NOTE sponsibility for any contingencies of the use of this
We caution you that in many cases the listed cross information. Nor does Radio Shack assume any re-
reference ARCHER device may be different in sponsibility for any infringements of patents or other
appearance, size or mounting style. Thus, before rights of third parties which may result from its use.
beginning replacement or installation procedures,
check to be sure you have enough room for proper
mounting. When you are looking for a specific number and it
does not show up in the following listing- refer to the
Also, when making substitutions or replacements in technical data provided for our line of ARCHER
radio or high frequency circuitry, it may be necessary devices. With this information you probably will be
to realign tunable circuit elements. This is true even able to make a suitable substitution.
123
MAJOR SEMICONDUCTOR COMPONENTS
I I
1
COMMONLY USED ROUGHLY
NAME OF CIRCUIT MAX RATINGS MAJOR
DEVICE
I SYMBOL
I JUNCTIO!j
SCHEMATIC I ELECTRICAL CHARACTERISTICS AVAILABLE APPLICATIONS
ANALOGOUS
TO:
Diode ANODE ANODE I 1 Conducts easily in 1500 Amps Rectification Check valve
ANODE
$
3000 Volts
t
or one direction, blocks Blocking Diode tube
VANODE (-) in the other
Rectifier
Detecting Gas diode
CATHODE
CATHODE
f VANODE (+)
Steering
$
CATHODE
$CATHODE
VANODE (-)
f
VANOOE ( +)
negative quadrant
Clipping
~
Voltage IR desired V 21 by regulator Diode
R,~::l]j
100 rnA
~
Regulator n two resistors Y2
Reference element
0.4 Watts
(IVR)
3 , .) Error modifier
Tunnel POSITIVE POSITIVE Displays negative Peak point UHF converter None
rJ
Diode ELECTRODE ELECTRODE resistance when current =
,¢
Logic circuits
(-)I~
Diode characteristics to mixers and
$ $
400 mV
VANOOE conventional diode low power
except very low oscillators
(
VANODE ( •)
forward voltage
CATHODE drop
CATHODE
~ r+J.
Thyrector Rapidly increasing 70 A peak Transient Thy rite
,~.
n-p-n COLLECTOR COLLECTOR Constant collector 300 Volts Amplification Pent ode
~·' ..~
Transistor Is, current for given Tube
25 Watts Switching
base drive
lo,
BAS
Oscillation
lo2
B
lo,
EMITTER EMITTER 0 VcoLLECTOR t. J
"'~ ~~
I COLLECTOR
Transistor as base current of
0.25 Amps Card readers
the photo transistor
r--H4 0.6 Wa tts Position sensor
H3
H2 Tachometers
I I;;-,
H1
EMITTER EMITTER VeE
Unijunction
Transistor
[UJT)
~~
BASE 2
EMITTER
BASE 1
~n
..L_ffi~
3:"'
t-<
.,,.
"'"'
"'a:
v.
Unijunction emitter
blocks until its
voltage reaches
Vp; then
35 Volts
0.450 Watts
Interval timing
Oscillation
Level Detector
None
BASE 1
l.t ""'
..:,...
~!::::
conducts SCR Trigger
BASE 2 ~~ 0 EMITTER I,
.
124
MAJOR SEMICONDUCTOR COMPONENTS
NAME OF
DEVICE
I
CIRCUIT
SYMBOL
I
COMMONLY USED
JUNCTION
SCHEMATIC I ELECTRICAL CHARACTERISTICS I MAX RATINGS
AVAILABLE
I MAJOR
APPLICATIONS
I ROUGHLY
ANALOGOUS
TO:
BASE 1
Comple- v, Functional com- 30 Volts High stability None
BASE 1
~
·~~
mentary plement to UJT timers
~~
Unijunction 0.30 Watts
Transistor
~ POINT 0.15 Amps Oscillators and
f---p-1- level detectors
(CUJT) r-;;- VALLEY
·POINT
BASE 2 EMITTER le
BASE 2
~
Program- ANODE t. Programmed by 40 Volts Low cost timers UJT
ANODE
,.,,],,,~1!...
[_ __~
Controlled I (+), SCR can be 1800 Volts thyratron or
~~
Rectifier Phase control
triggered by lg, ignitron
(SCR) VANOOE H remaining in con- Inverters
duction until anode I Choppers
CATHODE
t,
( VA,NODE (·)
is reduced to zero
00
ment to SCR
cfr ~~
I 0.25 Amps Low speed logic
Silicon
Controlled 0.45 Watts Lamp driver
VAc t-1 ~---
Rectifier
(CSCR)
CATHODE
( VAc t · J
CATHODE
,:W
scR• 200 Volts
also be triggered
Position controls
(LASCR) VANOOE (·) ---:;? into conduction by
light falling on Photoelectri c
CATHODE
( VANODE ( · J
junctions applications
Slave flashes
'
•••
Silicon w ANODE w ANOD~ Operates similar to 100 Volts Logic applications Complementary
11
~_{Jj~
Controlled SCR except can also transistor pair
be triggered on by a 200 rnA Counters
~
Switch• < p "
(SCS) "w 0w (.!) n ~ VANOOE (·) ---::J negative signal on Nixie drivers
0 0 ~ p ~ anode-gate. Also
0
X
~ CATHODE
z
< ~
....
<
n <C ( VANODE (·)
several other
specialized modes
Lamp drivers
u u CATHODE of operation
~ r~ ,
Unilateral GATE zener added to anode 0.200 Amps Counters 4-layer
Switch
(SUS) ~"¢ Ror- ~
~
~
gate to trigger device
into conduction at
- 8 volts. Can also be
10 Volts SCR Trigger
Oscillator
diode
n
triggered by negative
CAT~ ODE
CATHODE
pulse at gate lead.
"'n$ .r-"-11$-"-J'·
Switch
(SBS)
~ ~
VANOOE 2(·) (_= of the SUS . Breaks
down in both
10 Volts TRIAC Phase
Control
diodes
~
ANODE 2
to SCR except can 500 Volts in inverse
Phase control
,.,.$
ANODE 1
n
VANOOE
C---1
2(!) [ ___
VANOOE 2( · )
be triggered into
conduction in either
direction by(+) or
(-)gate signal
Relay replacement
parallel
GATE ANODE 1
«-
Diac When voltage 40 Volts Triac and Neon lamp
Trigger reaches trigger 2 Amps peak SCR trigger
c¢ E$3
level (about 35
volts), abruptly
switches down
about 10 volts.
Oscillator
126
hoe( real) -Real part of common-emitter small-signal open- lm(hie)-Imaginary part of common-emitter small-signal
circuit output admittance short-circuit input impedance
hrb -Common-base small-signal open-circuit reverse ' lm(hoe)-Imaginary part of common-emitter small-signal
voltage transfer ratio open-circuit output admittance
h,c -Common-collector small-signal open-circuit re- 10 -Average forward current, 180° conduction angle,
verse voltage transfer ratio 60-Hz half sine wave
h,. -Common-emitter small-signal open-circuit re- (p -Peak-point current
verse voltage transfer ratio IR -For voltage-regulator and voltage-reference di-
Ia -Base-terminal de current odes: de reverse current. For signal diodes and
h -Alternating component (rms value) of base-ter- rectifier diodes: de reverse current (no alternat-
minal current ing component)
i8 -Instantaneous total value of base-terminal current I, -Alternating component of reverse current (rms
laEv -Base- cutoff current, de value)
lsz(modJ -Interbase modulated curren~ iR -Instantaneous total reverse current
Ic -Collector-terminal de current hrAVJ -Reverse current, de (with alternating component)
Ic -Alternating component (rms value) of collector- IRM -Maximum (peak) total reverse current
terminal current IRRM -Maximum (peak) reverse current, repetitive
ic -Instantaneous total value of collector-terminal hrRMSJ-Total rms reverse current
current IRsM -Maximum (peak) surge reverse current
Icso -Collector cutoff current (de), emitter open Is -Source current, de
lcEO -Collector cutoff current (de), base open lsos -Zero-gate-voltage source current
leER -Collector cutoff current (de), specified resistance lsroHJ -Source cutoff current
between base and emitter lv -Valley-point current
IcEs -Collector cutoff current (de), base shorted to lz -Regulator current, reference current (de)
emitter lzK -Regulator current, reference current (de near
lcEv -Collector cutoff current (de), specified voltage breakdown knee)
between base and emitter lzM -Regulator current, reference current (de maxi-
lcEx -Collector cutoff current (de), specified circuit mum rated current)
between base and emitter K, k -Cathode
lo -Drain current, de Lc -Conversion loss
lo(olfJ -Drain cutoff current M -Figure of merit
lo(on) -On-state drain current NFo -Overall noise figure
loss -Zero-gate-voltage drain current NRo -Output noise ratio
IE -Emitter-terminal de current PsE -Power input (de) to base, common emitter
1. -Alternating component (rms value) of emitter- PBE -Instantaneous total power input to base, com-
terminal current mon emitter
iE -Instantaneous total Vdlue of emitter-terminal Pes -Power input (de) to collector, common base
current pes -Instantaneous total power input to collector,
hso -Emitter cutoff current (de), collector open common base
hszo -Emitter reverse current PeE -Power input (de) to collector, common emitter
IEqofsJ -Emitter-collector offset current PeE -Instantaneous total power input to collector,
common emitter
lEes -Emitter cutoff current (de), base short-circuited PEs -Power input (de) to emitter, common base
to collector PEB -Instantaneous total power input to emitter, com-
IE1EZ(of[J-Emitter cutoff current mon base
IF -For voltage-regulator and voltage- reference di- PF -Forward power dissipation, de (no alternating
odes: de forward current. For signal diodes and component)
rectifier diodes: de forward current (no alternat- PF -Instantaneous total forward power dissipation
ing component) PFrAv 1-Forward power dissipation, de (with alternating
Ir -Alternating component of forward current (rms component)
value) PFM -Maximum (peak) total forward power dissipation
iF -Instantaneous total forward current P 18 -Common-base large-signal input power
IFrAVJ -Forward current, de (with alternating component) Pib -Common-base small-signal input power
IFM -Maximum (peak) total forward current P,c -Common-collector large-signal input power
IFrovJ -Forward current, overload Pic -Common-collector small-signal input power
IFRM -Maximum (peak) forward current, repetitive P 1E -Common-emitter large-signal input power
hrRMSJ -Total rms forward current Pie -Common-emitter small-signal input power
IFsM -Maximum (peak) forward current, surge Pos -Common-base large-signal output power
lc -Gate current, de Pob -Common-base small-signal output power
lcF -Forward gate current Poe -Common-collector large~signal output power
lcR -Reverse gate current Poe -Common-collector small-signal output power
less -Reverse gate current, drain short-circuited to PoE -Common-emitter large-signal output power
source Poe -Common-emitter small-signal output power
lcssF -Forward gate current, drain short-circuited to PR -Reverse power dissipation, de (no alternating
source comp,onent)
lcssR -Reverse gate current, drain short-circuited to PR -Instantaneous total reverse power dissipation
source PRIAVJ-Reverse power dissipation, de (with alternating
11 -Inflection-point current component)
127
\
\
PRM -Maximum (peak) total reverse power dissipation Vcb -Instantaneous value of alternating component
PT -Total nonreactive power input to all terminals of collector-base voltage
PT -Nonreactive power input, instantaneous total, to Ve 81 n1 -Collector-base de open-circuit voltage (floating
all terminals potential)
Qs -Stored charge Vcso -Collector-base voltage, de, emitter open
rss -Interbase resistance Vee -Collector supply voltage (de)
rbCc ~Collector-base time constant VeE -Average or de voltage, collector to emitter
reE(satJ -Saturation resistance, collector-to-emitter Vee -Instantaneous value of alternating component
ros(on) -Static drain-source on-state resistance of collector-emitter voltage
f ds(on) ~Small-signal drain-source on-state resistance VcE 1n1-Collector-emitter de open-circuit voltage (floating
Re(h;e) -Real part of common-emitter small-signal short- potential)
circuit input impedance Vcw -Collector-emitter voltage (de), base open
Re(hoe)-Real part of common-emitter small-signal open- VcEtofsl -Collector-emitter offset voltage
circuit output admittance VeER -Collector-emitter voltage (de), resistance be-
rele2(oni-Small-signal emitter-emitter on-state resistance tween base and emitter
r; -Dynamic resistance at inflection point VeEs -Collector-emitter voltage (de), base shorted to
Ra -Thermal resistance emitter
RaeA -Thermal res is lance, case to ambient VcEtsatJ -Collector-emitter de saturation voltage
RaJA -Thermal resistance, junction to ambient VcEv -Collector-emitter voltage (de), specified voltage
Ra1e -Thermal resistance, junction to case between base and emitter
S , s -Source VeEx -Collector-emitter voltage (de), specified circuit
TA -Ambient temperature or free-air temperature between base and emitter
Te -Case temperature Voo -Drain supply voltage (de)
td -Delay time Vor. -Drain-gate voltage
l d(offl -Turn-off delay time Vos -Drain-source voltage
ld(on) -Turn-on delay time VostunJ -Drain-source on-state voltage
tr -Fall time Vou -Drain-substrate voltage
t r, -Forward recovery time VEs -Average or de voltage, emitter to base
Ti -Junction temperature Veb -Instantaneous value of alternating component
l urr -Turn-off time of emitter-base voltage
t on -Turn-on time VEBi fiJ-Emitter-base de open-circuit voltage (floating
tp -Pulse time potential)
t, -Rise time VEso -Emitter-base voltage (de), collector open
trr -Reverse recovery time VEBllsatJ-Emitter saturation voltage
t. -Storage time VEe -Average or de voltage, emitter to collector
TSS -Tangential signal sensitivity Vee -Instantaneous value of alternating component
Tstg -Storage temperature of emitter-collector voltage
lw -Pulse average time VEC( ri)-Emitter-collector de open-circuit voltage (float-
U, u -Bulk (substrate) ing potential)
Vss -Base supply voltage (de) VEC(ofsJ -Emitter-collector offset voltage
Vse -Average or de voltage, base to collector VEE -Emitter supply voltage (de)
Vbc -Instantaneous value of alternating component Vr -For voltage-regulator and voltage-reference di-
of ba se-collector voltage odes: de forward voltage. For signal diodes and
VuE -Average or de voltage, base to emitter rectifier diodes: de forward voltage (no alternat-
Vbe -Instantaneous value of alternating component ing component)
of base-emitter voltage Vr -Alternating component of forward voltage (rms
ViBRi -Breakdown voltage (de ) value)
VJBRI -Breakd own voltage (instantaneous total) Vr -Instantaneous total forward voltage
ViBR)eBo -Collector-base breakdown voltage, emitter VFIAVJ-Forward voltage, de (with alternating component)
open VrM -Maximum (peak) total forward voltage
ViBR)eEO -Collector-emitter breakdown voltage, base open VrtRMSJ-Total rms forward voltage
VIBRieER -Collector-emitter breakown voltage, resistance Vee -Gate supply voltage (de)
between base and emitter Vcs -Gate-source voltage
ViBR)eEs -Collector-emitter breakdown voltage, base Vcsr -Forward gate-source voltage
shorted to emitter Vc stoffl -Gate-source cutoff voltage
ViBR)eEv -Collector-emitter breakdown voltage, specified VcsR -Reverse gate-source voltage
voltage between base and emitter Vc sph) -Gate-source threshold voltage
ViBR)eEx -Collector-emitter breakdown voltage, specified Vcu -Gate-substrate voltage
c ircuit between base and emitter v, -Inflection-point voltage
VIBRJEBO -Emitter-base breakdown voltage, collector Vos1 -Base-1 peak voltage
open
Vp -Peak-point voltage
ViBRJEeO -Emitter-collector breakdown voltage, base Vpp -Projected peak-point voltage
VIBRJEJE2 -Emitter-emitter breakdown voltage VR -For voltage-regulator and voltage-reference di-
VIBRJGSs -Gate-source breakdown voltage iodes: de reverse voltage. For signal diodes and
VIBRJGssr-Forward gate-source breakdown voltage rectifier diodes: de reverse voltage (no alternat-
VIBRJGSSR-Reverse gate-source breakdown voltage ing component)
Vs2B1 -Interbase voltage V, -Alternating component of reverse voltage (rms
Vcs -Average or de voltage, collector to base value)
128
VR -Instantaneous total reverse voltage Yob -Common-base small-signal short-circuit out-
VR(AV} -Reverse voltage, de (with alternating component) put admittance
VRM -Maximum (peak) total reverse voltage Yoc -Common- collector small- signal short- circuit
VRRM -Repetitive peak reverse voltage output admittance
VR(RMS}- Total rms reverse voltage Yoe -Common-emitter small-signal short-circuit out-
VRsM -Nonrepetitive peak reverse voltage put admittance
VRT -Reach-through voltage Yoe(imag}-Imaginary part of small-signal short-circuit out-
VRwM -Working peak reverse voltage put admittance (common-emitter)
Vss -Source supply voltage (de) Yoe(real} -Real part of small-signal short-circuit output
Vsu -Source-substrate voltage admittance (common-emitter)
V1To) -Threshold voltage Yos -Common-source small-signal short-circuit out-
Vv -Valley-point voltage put admittance
Vz -Regulator voltage, reference voltage (de) Yos(imag}-Common-source small-signal output suscep-
VzM -Regulator voltage, reference voltage (de at max- tance
imum rated current) Yos(real} -Common-source small-signal output conduc-
Yrb -Common-base small-signal short-circuit forward tance
transfer admittance Yrb -Common-base small-signal short-circuit reverse
Yrc -Common-collector small-signal short-circuit for- transfer admittance
ward transfer admittance Yrc -Common-collector small-signal short-circuit re-
yr. -Common-emitter small-signal short-circuit for- verse transfer admittance
ward transfer admittance Yre -Common-emitter small-signal short-circuit re-
Yrs -Common-source small-signal short-circuit for- verse transfer admittance
ward transfer admittance Yrs -Common-source small-signal short-circuit re-
Yfs(imag)-Common-source small-signal forward transfer verse transfer admittance
susceptance Yrs(imag}-Common-source small-signal reverse transfer
Yfs(real} -Common-source small-signal forward transfer susceptance
conductance Yrs(real} -Common-source small-signal reverse transfer
Yib -Common-base small-signal short-circuit input conductance
admittance Zif -Intermediate-frequency impedance
Yic -Common-collector small-signal short-circuit in- Zm -Modulator-frequency load impedance
put admittance Zrr -Radio-frequency impedance .
Yie -Common-emitter small-signal short-circuit input Za!A(t}- Junction-to-ambient transient thermal impedance
admittance Za!Cit}- Junction-to-case transient thermal impedance
Yie(imag}-Imaginary part of small-signal short-circuit in- Zatt} -Transient thermal impedance
put admittance (common-emitter) Zv -Video impedance
Yie(real} -Real part of small-signal short-circuit input ad- z, -Regulator impedance, reference impedance
mittance (common-emitter) (small-signal at lz)
Yis -Common-source small-signal short-circuit in- Zzk -Regulator impedance , reference impedance
put admittance (small-signal at l zK)
Yis(imag)-Common-source small-signal input susceptance Zzm -Regulator impedance, reference impedance
y is( real} -Common-source small-signal input conduc- (small-signal at lzM)
tance
129
ARCHER SEMICONDUCTOR REPLACEMENT GUIDE
DEVICE 276· DEVICE 276· DEVICE 276· DEVICE 276· DEVICE 276· DEVICE 276· DEVICE 276·
OOOOOOOFR1 1104 000073230 1617 001.0163-02 565 001-044674-001 2009 1104 1104 01-201.0 2009
OOOOOOOFR2 1104 000073231 1617 001.0163-15 562 001-044676-001 1122 2020 1104 01-9011-5/2221-3 2009
OOOOOOOFRI 1104 000073280 2017 001.01501-0 1123 001-044677.001 2016 1617 1104 01-9013-712221-3 2009
OOOOOOOMV4 1122 000073290 1617 001-02101.0 1617 001-21011 1617 2020 1122 01-9014-212221-3 2009
0000000515 1104 0000733JO 1617 001.0_ll01-1 1617 001-22393!.., 564 2041 2016_ 01-9016.412221~
0000001N60 1123 000073320 2017 001-02102-0 1617 001-226030 1104 180l 2009 01-9018-6/2221-3 2009
0000001001 1104 000073332 1617 001-02103-0 1617 002-006500 1617 2035 2009 01-30828 2058
0000000517 1104 000073333 1617 001-02104-0 1617 002-008300 2016 2023 2023 01-30829 2009
0000000518 1104 000073351 2016 001-02105-0 1617 002-009500 1617 2030 2023 01-57291 2020
00000005-38 1104 000073361 2016 001-02106-0 1617 002-009502 1617 2030 2009 01-117005 2016
0000000538 1104 000073370 2009 001-02107-0 1617 002-0095112-12 1617 2020 104 lll-117006 2016
OOOOOOSD1AB 1104 000073380 2017 001-02108-0 1617 002-009600 2016 2020 1104 01-349418 2009
OOOOOOS01Y 1104 000073390 1617 001-02109.0 1617 002-009601 2016 2035 1123 01-349423 1617
0000005046 1123 000073391 1617 001-02110.0 1617 002-009601-12 2016 2035 1122 01-349426 2058
0000015188 1123 OOOODS410R 1122 001-0211h.9 .2009 002-00980L 2023 2035 11Da 01~9634 2009,
0000015334 562 OOOOFR202 1104 001-02111-1 1617 002-009800A 2023 1801 1122 01-349681 2023
0000015990 1122 OOOOR51542 1104 001-02113-2 1617 002-009900 1617 1802 1104 01-472814 2009
0000010DC1 1104 000050-1AUF 1122 001-02113-3 1617 002-03 1617 1822 1104 01-571591 2023
0000015330A 565 000-04 1617 001-02113-4 1617 002-010300 2023 2041 2016 01-571751 2023
000000518 1101 00015188 1123 001-02113-5 1617 002-010300A 2023 2055 2027 01-571794 2016
0000005-38 1114 00015188AM 1123 001-02119-0 2030 002-010400 1617 2009 2023 01-571804 2009
0000005131 1104 00015188FM 1123 001-02121.0 1617 002.010500 2023 2023 2023 01-571811 2009
0000005410 1122 0002SC373 1617 001-02201.0 2023 002.010500A 2023 0020-0191 2009 2023 01-571821 2009
0000051801 1104 0002SC373W 2009 001-02303-0 565 002.010600 2030 0020-0191(,2SC945) 2023 01-571941 1617
OOOOOWZ090 562 0002SC458B 2009 001-02303-3 561 002-010800 !J1l... 2009 01-5}1588
2QU ~
0000-04 2009 00025C458C 2009 001-02303-4 564 002-010900 2023 0020-0250 2009 2023 01-572631 2055
0000-0141 2023 00025C537F 2009 001-02405-0 1104 002-010900A 2023 0020.0330 2009 2023 01-572774 2027
0000-0150 2023 00025C644Q 2016 001-02405-1 1104 002-011400 2016 0020-0332 2009 2023 01-572784 2020
0000-0300 2023 00025C6445,R,Q 2016 001-02405-2 1104 002-011500 2016 0020-0351 2009 2009 01-572791 2020
000015155_ 1122 00025C710B 2009 001-02406-0 1114 002-012000 1617 0020-0521 2058 2016 01-572811 2023
000015188 1123 0002SC710C 2009 00~1 1114 002-0123cio 2027 -0020-0531 2016 2058 o1-m8t4 2oo7
000015330A 565 0002SC772C 2016 001-02601-0 1104 002-012400 2020 0020-0630 2009 2009 01-572861 2020
0000151555 1122 0002SC828 2009 001-02603-0 1104 002.012500 2030 0030-0091 2020 2009 01-680815 2009
0000151849 1104 0002SC828H 2009 001-02701-1 2035 002.012800 2023 0036-001 2023 2009 01-690733 2023
0000152076 1122 00025C828Q 2009 001-02702,.0 2035 002-012800~ 2!113 OOSQ:O.Qil 1123 2009 01-69094§
0000154460 1123 00025C930D
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2016 001-02703-0 2035 002-9501 2016 0050-0021 1123 2009 01-691187 2058
000025A550 2023 00025C930E 2016 001-015010 1123 002-9502 2016 0050-0032 1123 2009 01-691674 2016
0000258435 2027 00025C968P 2009 001-015011 1123 002-9502-12 2016 0050-0070 1122 2009 01-700542 2023
0000258460 2016 00025C1023 2016 001-021010 2009 002-9601 2016 0050-0250 1122 2055 01 ST-MPS9700D 2009
0000258968 2009 0002SC1026 2016 001-021011 2009 002-9601-12 2016 0050-0300 1122 2016 01K-4.6E 565
00002SC373
00002SC460
2009
2009
0002SC1026A
00025C1026B
2016-
2016
. 001-021020
001-021030
20o9 002-mo:A
2009 002-12000
2023 0050-0301 1122- 2016 01K-5.0E w·
1617 0050-0302 1122 2009 01K-5.2E 565
00002SC460A 2016 0002SC1026Ci 2016 001-021040 2009 002D235RY 2020 0051.0010 1104 2009 01K5.4E 565
00002SC460B 2016 00025C1032 2016 001-021050 2009 002SB435RY 2027 0051.0070 1104 2023 01K-6.5E 561
00002SC460C 2016 00025C1032A 2016 !!!11-021P60. 2011! 002Sc;~Q 2016 !!!15Y1!!!1 1104 2016 011(6.5(, 561
00002SC461 2009 0002SC1032B 2016 001-021070 2016 002SC735-0Y 2009 0051-0110 1104 2023 01ST-MPS9700D 2009
00002SC535 2016 0002SC1032C 2016 001-021080 2009 002SC7350Y 2009 0051-0130 1104 2009 02-004558 038
00002SC536 2009 00025C1061 2020 001-021090 2009 0025C1061 2017 0051-0160 1104 2009 02-25C458LGC 2009
00002SC537 2009 0002SC1061A 2020 001-021110 2030 002SC1209C 2009 0051-0290 1104 N1 2016 02-1001-112221-3 1123
000025C606 2016 00025C1061B 2020 001-021JIJ 2030 002SC735QY 2QOt_ 0051-0291 1104N2 2058 02-1006-2/2221-3 1122
00002SC644 2016 00025C1061C 2020 001.021130 2009 0025D235RY 2020 0051-0340 1104 20ft- 02-1006-22221-3 1122
00002SC668 2016 0003-009700 563 001.021131 2009 003 1123 0051-0400 1020 2009 02-3002-212221-3 1104
00002SC735 2009 000157GN 1123 001-021132 2009 003-00 2058 0054-0020 565 2009 02-3002-22221-3 1104
00002SC772 2058 000188GN 1123 001-021133 2009 003-00200 1123 0054-0191 565 2016 02-33379-6 2030
00002SC828 2009 000546-1 1617 001,0lll34 2009 003-004toe! 1J23 00.54,0240 563 2016 02-124422 lO,\
00002SC829 2016 000704 2009 001-021135 2009 003-005400 1123 0054-0240(,RD-12EB) 2009 02-257205 705
00002SC838 2009 0001849 1104 001-021136 2016 003-006700 1123 563 2016 02-437205 705
00002SC858 2016 0001849R 1104 001-021172 2023 003-007500 1123 0054-0250 1122 2009 02-455804 038
00002SC870 1617 00023645 2009 001-021180 2041 003-009000 1123 0099-1030 1101 2020 02 RECT-UG-1 004 1173
00002SC870A 1617 00031011049 2009 001-021190 2030 003-009100 564 0099-1040
02iZ4:7-- . tOOt
1122 2009 02 5T-2SC1815Y
00002SC870B 1617 00031013045 2009 001::ci21200 2041 003-009200 1123 001422 2009 2009 565
00002SC870C 1617 00031014021 1123 001-021210 1617 003-009400 1104 003002 1123 2016 02P1B
00002SC929 2016
2023
00031014022 1122 001-021218 1617 003-009600 1123 003007 1104 2009 02RECT-UG-1004 1173
00002SC930 2016 OOOWG1010 1122 001-021270.1 2041 003-009700 563 003008 2009 025T-2SC1815
000025C945 2009 00
2009
2016 001-021290 2030 003-009900 1104 ootQ11 2Q16 Q2ST-2SCD1
00002SC968 1617 001-0000-00 2009
1123 001-022010 2023 003-0 1067 003016 2009 02ST-2SC1875 2055
00002SC1 023 2009 001-00 1617 001-022020 2023 003-01 2058 003017 2016 02Z-6.2A 561
00002SC1026 2016 001-007-00 1104 001-023030 565 003-02000 1123 003023 2009 02Z6.2A 561
00002SC1032 2016 001-0010-00 1123 001-023033 561 003-010000 563 003102 2016 02Z6.2W 561
00002SC1061 2020 001-0020-00 1123 001-023034 564 004-00 1617 003111 2009 0219.1 562
0000250235 2020 001-0020.0 1123 001.023037 565 004-0027.00 1104 003113 2009 02Z-9.1A 562
000071150 2023 001-0022.00 1123 001-024010 1104 004-00900 1122 003114 2058 02Z9.1A 562
000071151 2023 001.0072.00 1104 001-024020 1104 004-002000 1104 003307 2058 02Z12A 563
000072020 1104 001.0077.00 1104 001-024030 1104 004-002700 ~104 003449
000072050 1104
2058 02Z12GR 563
001-0081 1123 001-024050 1104 Q04-002800 1J04 003460 2009
000072090 1123 001-0082-00 561 001-024051 1104 004-003000
02.%1.$ ....56.ot
1104 003461 2058 02Z1.5A 564
000072150 562 001-0095-00 1122 001-024052 1104 004-003300 1104 004567 2016 02Z62A 561
000072160 1123 001-0095-02 1122 001-024060 1143 004-003400 1104 004746 2058 03-0018-0 1104
000072190 562 001-02 2023 001-024061 1143 004-003600 1104 004763 2058 03-160 1123
000073070 2016 001-03 2023 001-024080 2009 004-003700 1101 004792 2009 03-460C 2016
000073080 2016 001-04 2023 001-026010 11~ 004-1103900 1104 '104881 ~20 -o~JI 2016
000073090 1617 001.0101.01 562 001-026030 1122 004-004000 1114 0023645
000073100 2020 03-535A 2016
1617 001.0112.00 1122 001-026060 1122 004-004100 1104 0023828 2020
000073110 03-1585/G 1617
2030 001.0125-00 1122 001-027030 2035 004-009200 1123 0023829 2020
000073120 03-3016 1104
1617 001.0151.00 1122 001-044272-002 2009 004-03300 1104 0044028-014 2020 03-931051
000073130 1123
1617 001.0151.01 1122 001-044273-002 2030 004-03500 1104 0044028-14 2035 03-931601
000073140 1104
2058 001.0153-00 1104 001-044277-002 1104 004-03600 1104 0099201-325 2016 03-931609 1104
130
ALPHABETICAL/NUMERICAL INDEX
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PRINTED IN U.S.A.