Archer Semiconductor Reference Guide 1988

INTEGRATED CIRCUITS INDEX BY GENERIC NUMBER
GENERIC CATALOG DESCRIPTION PAGE GENERIC CATALOG DESCRIPTION PAGE

NUMBER NUMBER NUMBER NUMBER NUMBER NUMBER
AY-3-8910A 276-1787 PROG SND GEN 106 555 276-1723 TIMER 65

CTS256AL2 276-1786 CODE-TO-SPCH 77 556 276-1728 DUAL TIMER 66
HYB4164-P2 276-2506 MEMORY (RAM) 29 567 276-1721 TONE DECODER 72
MC1488 276-2520 QUAD LINE DRV 45 723 276-1740 ADJ REG 69
MC1489 276-2521 QUAD LINE RCVR 48 741 276-007 OPAMP 62
MSM2764RS 276-1251 MEMORY (EPROM) 35 1458 276-038 DUAL OP AMP 63
SP0256 276-1784 SPCH PROC 96 3909 276-1705 LED FLASHER/OSC 73
SSI202 276-1303 DTMF RCVR 74 4001 276-2401 NOR GATE 21
TA7205AP 276-705 AUD AMP 57 4011 276-2411 NAND GATE 22
TDA 1520A 276-1305 AUD AMP 58 4013 276-2413 DUAL FLIP-FLOP 23
TDA7000 276-1304 FM RADIO 115 4017 276-2417 DECADE CNT 24
TLC548 276-1796 A-D CONV 50 4049 276-2449 INV HEX BUFFER 25
TLC555 276-1718 TIMER 54 4066 276-2446 QUAD BILATERAL SW 26
TMS4256 276-1252 MEMORY (RAM) 36 7400 276-1801 NAND GATE 39
UM3482 276-1797 MELODY GEN 27 7404 276-1802 HEXINV 40
317T 276-1778 ADJ REG 67 7408 276-1822 AND GATE 41
324 276-1711 QUAD OP AMP 64 7447 276-1805 BCD DECODER/DRV 42
339 276-1712 COMPARATOR 71 7490 276-1808 BCD COUNTER 44
353 276-1715 WD BAND AMP 60 7805 276-1770 5V REG 70
383 276-703 AUD PWR AMP 55 7812 276-1771 12V REG 70
386 276-1731 AUD PWR AMP 56 7815 276-1772 15V REG 70
INTEGRATED CIRCUITS INDEX BY CATALOG NUMBER
GENERIC CATALOG DESCRIPTION PAGE CATALOG GENERIC DESCRIPTION PAGE

NUMBER NUMBER NUMBER NUMBER NUMBER NUMBER
276-007 741 OP AMP 62 276-1772 7815 15V REG 70

276-038 1458 DUAL OP AMP 63 276-1778 317T ADJ REG 67
276-703 383 AUD PWR AMP 55 276-1784 SP0256 SPCH PROC 96
276-705 TA7205AP AUD AMP 57 276-1786 CTS256AL2 CODE-TO-SPCH 77
276-1251 MSM2764RS MEMORY (EPROM) 35 276-1787 AY-3-8910A PROG SND GEN 106
276-1252 TMS4256 MEMORY (RAM) 36 276-1796 TLC548 A-D CONV 50
276-1303 SSI202 DTMF RCVR 74 276-1797 UM3482 MELODY GEN 27
276-1304 TDA7000 FM RADIO 115 276-1801 7400 NAND GATE 39
276-1305 TDA1520A AUD AMP 58 276-1802 7404 HEX INV 40
276-1705 3909 LED FLASHER/OSC 73 276-1805 7447 BCD DECODER/DRV 42
276-1711 324 QUAD OP AMP 64 276-1808 7490 BCD COUNTER 44
276-1712 339 COMPARATOR 71 276-1822 7408 AND GATE 41
276-1715 353 WD BAND AMP 60 276-2401 4001 NOR GATE 21
276-1718 TLC555 TIMER 54 276-2411 4011 NAND GATE 22
276-1721 567 TONE DECODER 72 276-2413 4013 DUAL FLIP-FLOP 23
276-1723 555 TIMER 65 276-2417 4017 DECADECNT 24
276-1728 556 DUAL TIMER 66 276-2449 4049 INV HEX BUFFER 25
276-1731 386 AUD PWR AMP 56 276-2466 4066 QUAD BILATERAL SW 26
276-1740 723 ADJ REG 69 276-2506 HYB4164-P2 MEMORY (RAM) 29
276-1770 7805 5V REG 70 276-2520 MC1488 QUAD LINE DRV 45
276-1771 7812 12V REG 70 276-2521 MC1489 QUAD LINE RCVR 48
TABLE OF CONTENTS
INTRODUCTION .. .. ............. . ............................. . ........................... 2
HOW TO USE THE BOOK ..... . ....................... . .............. . . . ........... . ......... 2
CARE AND HANDLING OF TRANSISTORS ........................................ . ......... . .. 2
SILICON OR GERMANIUM? ... . ......... . ................................................... 2
OPERATING CONSIDERATIONS ............................ . .. . ........................... 2, 3
SILICON vs SELENIUM RECTIFIERS ....................... . ... . ..... .. ....................... 3
SOLDERING PRECAUTIONS ............. . . . .................... . . . ...... . .. . .. . ............ 3
ABOUT CASE DIMENSIONS . ...... . ................ . ................. . ........... . ........ 3, 4
GENERAL PRECAUTIONS ........ . .......................................... . .............. 4
TESTING A TRANSISTOR ..... . .................................. . ........................ 4, 5
HANDLING OF INTEGRATED CIRCUITS ..... . .... . .................... . .............. . ....... . 5
DIODES, RECTIFIERS AND ZENERS .................. . ....... L ••••••••••••••••• •5 •••••••••••• • •
BIPOLAR TRANSISTORS . ....... . ....................... . .............. . .......... . ..... . . . 6

SPECIAL TRANSISTOR (FET) ........................................................... . .. 7-10
SPECIAL PURPOSE DEVICES (VARISTOR)(SCR)(TRIAC) ............... . ............ . ....... . 11, 12
OPTOELECTRONIC INDEX BY FUNCTION ........................... . ............... . .... . . . . 12
OPTOELECTRONICS . .... . .............................. . ....... . ..... . .......... . ..... 12-20
INTEGRATED CIRCUITS (See index inside front cover)
Digital (CMOS) .. . . .. ... . ...... . .................. . ............. .. ................ 21-28
Digital (Memory) . . ... . ......................................... . ........... . ..... 29-38
Digital (TTL) . . ............ . ..................................... . ................ 39-44
Interface (Driver) ........ . ...... . ..... . ......................... . ....... . .. . ...... 45, 47
Interface (Receiver) ....................................................... . ...... 48, 49
LinCMOS (A to D converter) .... . ........... . ................................ . ...... 50-53
LinCMOS (Timer) .......... . ......................................... . .............. 54
Linear (Audio) ..... . ..... . ... . ............................ . ... . .................. 55-59
Linear (OP Amp) ..... . ..... . ............................... . ...... . . . .. . ......... 60-64
Linear (Timer) .. . ......................... . ............. . . . ............... . ...... 65, 66
Linear(Volt Reg) ......................................... . ...... . ................ 67-70
Linear (Miscellaneous) .............. . .... . ........................................ 71-73
MOS (CMOS) . ......... . ....... . .......................... . ...................... 74-76
MICROCOMPUTER (8-BIT) . .............................. . ....................... . . 77-95
N-Channel MOS (Audio) . . . . . ........................... .' .................... . .... 96-105
N-ChanneiiON Implant (P Sound Generator) . ....................................... 106-114
FM RECEIVER . . . . . . .......... . ................ . ..................................... 115-118
QUICK CASE REFERENCE .... . ........................................... . . ....... . .. 119, 120
SEMICONDUCTOR CROSS REFERENCE NOTES ..... . ....... . ............ . .......... .· . . ..... 120
QUICK INDEX . ..... . ............. . ......................... . ............... . .... .. ...... 121
MASTER INDEX BY CATALOG NUMBER .. . ... . . . ................................ .. ......... 122
IMPORTANT SUGGESTIONS ON THE USE
AND REPLACEMENT OF TRANSISTORS ............. . .................. .. .. .. . . . ..... . . . .. 123
CROSS REFERENCE/SUBSTITUTION LISTING ............................... . ... . . . ..... . ... 123
MAJOR SEMICONDUCTOR COMPONENTS ........................................ . .... . 124,125
GLOSSARY OF WORDS, SYMBpLS AND ABBREVIATIONS ............ . .................... 126-129
ARCHER SEMICONDUCTOR REPLACEMENT GUIDE ............... . .... . ........... . ..... 130-286
ALPHABETICAL/NUMERIC INDEX (Inside back cover) ................ . .............. . ....... . . 289
Although great care has been taken in the preparation of this Reference Guide to ensure the technical correctness, no responsibility
is assumed by -Radio Shack for any consequences of the use of items listed. Nor does Radio Shack assume any responsibility for
any infringements of patents or other rights of third parties which may result from its use.
© Copyright 1987, Radi o Shack, A Division of Tandy Corporation, Fort Worth, TX 76102
All Rights Reserved .
ARCHER and Radio Shack are trademarks of Tandy Corporation.
INTRODUCTION
This SEMICONDUCTOR REFERENCE HANDBOOK is intended to be just that-a reference handbook. It is not
a definitive text book on semiconductors. It is a compilation of data on Radio Shack's line of prime-quality
ARCHER®semiconductors. Every ARCHER device covered in this Handbook is guaranteed prime-they are not
"fall-outs" or "seconds"; all are top-quality, with known JEDEC, EIA or manufacturer's numbers.
At the back of the book is a cross-reference listing for replacement of Transistors, Diodes and other inter-
changeable semiconductor devices. The total number of cross-referenced devices exceeds 94,000. These
cross-reference/replacement listings are computer-selected and are based on careful analysis of important
parameters of the listed devices. ·
NOTE: If you can't find a replacement listing for a device you require, refer to the specification listings of the ap-
propriate ARCHER family device. Often you will be able to make suitable replacements based on the information
presented.
Each ARCHER replacement should meet or exceed the required parameters. However, due to differences in
Quality Control and Manufacturing procedures (which often allow for or result in broad parameter variations), and
because many of the ARCHER devices are capable of better performance than the original, Radio Shack does not
guarantee, nor does it imply, that the listed items will provide an exact replacement in every instance. Therefore
we recommend that you check the voltage and current requirements of the circuit (and other pertinent specifica-
tions) before replacement and compare with the specifications listed for that particular ARCHER device.
When cutting transistor leads, use scissor-type cut-

HOW TO USE THIS BOOK ting tools (rather than diagonal cutting tools which use
This book has been prepared to aid in BOTH re- a crimping action). Crimp-type cutting tools produce a
placement and original applications of Semiconductor mechanical shock along the lead which when trans-
devices. The information included will be invaluable mitted to the semiconductor chip or material can cause
for the service technician as well as the circuit de- fracture. Consider the force with which the cut lead
signer (whether he be an engineer, hobbyist, student or flies off the crimp-type cutting . tool and you have a
electronics experimeter). good idea of the intensity of the equal and opposite·
We have included hints on handling Semiconductor force which acts on the lead going into the device.
devices. operating considerations, and some simple It is always a good practice to use a heat-sink tool
tests t~ aid you in evaluating the quality of the device on a transistor lead when soldering (use a low-wattage
in existing equipment (and thus the need for replace- iron-30-watts or less). Heat from soldering can cause
ment). Also, a complete section on the specifications problems (especially with certain types of semicon-
for each of the ARCHER devices is included; if there is ductor devices). Thus. to be sure, always use a heat-
any question in your mind about replacement equiva- sink on the lead when soldering. Gripping the lead
lents or original use. refer to the appropriate category with long nose pliers between the solder connection
in the book. You will find the important characteristics and the case of the device makes a good heat-sink; or
specified there. use a tool designed for such use.
The next to last section is an extensive listing of
replacement and cross reference between other manu- SILICON OR GERMANIUM?
facturer's numbers (both JEDEC/EIA 2N- numbers and The quickest way to determine if a transistor is ger-
in-house designations) and the ARCHER devices. This manium or silicon type. is to check the normal emitter-
listing provides for the substitution of over 94,000 semi- base voltage drop. With NPN devices, if the base is ap-
conductors with ARCHER devices. proximately 0.25 volts positive with respect to the
The final section includes case style drawings and emitter. it is a germanium type. If the voltage is about
some handy reference notes. a comprehensive glossary 0.65 volts. it is a silicon type. For PNP devices. the
of commonly used words. plus symbols and abbrevia- voltage will be the same value. but opposite in polarity
tions. (0.25 volts for germanium and 0.65 for silicon).
CARE AND HANDLING OF TRANSISTORS OPERATING CONSIDERATIONS
Most modern transistors are somewhat immune Before replacing an original-equipment device with
from mechanical shock; however. it is always a good the recommended Archer Type:
idea to keep them from excessive mechanical shocks. (A) Compare the lead or terminal arrangement of
especially the metal-case type (avoid dropping. etc). the Archer replacement device with the lead or ter-
2
minal arrangement of the original device. If these ar- observe this precaution can result in damage in the
rangements are different, and the original transistor is device. Transistor substitution in tuned circuits will
a "plug in" type, bend the leads of the ARCHER device often require realignment of the circuit.
so that the base, emitter and collector leads will mate
with the original transistor leads. Trim the leads after SILICON VS SELENIUM RECTIFIERS
soldering in place. Silicon rectifiers are inherently more efficient than
CAUTION: Be particularly careful about "pin-cir- selenium or other metallic-oxide type rectifiers. When
cle" and "in-line" lead break-out type transistors. a silicon rectifier is used to replace a selenium rectifier
Often one manufacturer makes a type with "in-line" in the power supply of a typical line-operated radio or
leads, while another may make the same type with TV receiver, the silicon rectifier will frequently deliver
"pin-circle" configuration. Doublecheck both the orig- higher DC output voltage than the original device.
inal and the replacement device before soldering or In some cases, this higher supply voltage may im-
plugging in transistors. prove the performance of the equipment. However, in
BOTTOM VIEW many other cases, it may immediately or eventually
damage filter capacitors and/or other components
PIN-CIRCLE IN-LINE which were designed to withstand only the voltage
delivered by the original selenium rectifier. To prevent
such damage, it is generally advisable to insert a power
~ type resistor in series with the silicon rectifier either

on the input side, between the AC supply and the rec-
~ tifier, or on the output side between the rectifier and

the first filter capacitor. The value of this resistor will
qepend on the required reduction in the DC output
(B) Certain considerations are involved whenever voltage and on the DC load current of the equipment.
an original equipment transistor is replaced by one This value may be determined experimentally or cal-
having a different type designation. When an culated from the equation:
ARCHER series transistor is used to replace an origi-
R = E._
nal equipment device in an untuned amplifier stage I
operating at a low signal level such as the untuned RF-
amplifier (antenna) stage of a radio receiver, or a low- where R is the required resistance in ohms, E the
level AF amplifier stage, it is generally unnecessary to required reduction in DC output voltage in volts
and I the DC load current in amperes.
make any circuit adjustment to assure proper perform-
ance of the equipment. However, when a replacement The wattage rating of the resistor should be at least
2 X EI (in no case less than 10 watts).
is made in a turned RF amplifier stage, it is always
advisable to check the alignment of the associated SOLDERING PRECAUTIONS
tuned circuits to assure proper tracking and to achieve
the required gain without loss of stability. . Extreme ' care should always be used in making
(C) When replacements are made in stages operat- solder connections to semiconductors. Momentary ap-
ing at relatively high power levels, such as Class A and plication of excessive heat, or even prolonged applica-
Class B AF output stages of automobile radio re- tion of a properly heated soldering tool to a semicon-
ceivers, phonographs and AF-amplifier systems, the ductor .lead or terminal, can permanently damage the
transistor bias should be checked and adjusted, if nec- device. Observe the following precautions in soldering
essary, to protect the ARCHER replacement transis- a semiconductor lead or terminal :
tors against excessive dissipation and to minimize dis- 1. Solder as far as possible from the body of the
tortion. Means for making adjustments are generally semiconductor.
provided in the equipment, and the necessary instruc- 2. Never, apply heat or molten solder to a lead or
tions are · usually given in the equipment manufac- terminal for longer than 10 seconds or at a point closer
turer's service data. than 1/16 inch to the body of the device.
(D) When installing an ARCHER transistor as a 3. Use a low voltage iron (30 watts or less) specifi-
substitute for an original equipment type in an FM cally intended for use with transistors or miniature cir-
tuner, TV tuner, or other circuits operating at frequen- cuit components. '
cies in the VHF or UHF regions, it is extremely impor- 4. Keep the surfaces to be soldered clean and the tip
tant not to ch_ange any of the lead lengths or position of of the soldering tool adequately tinned so that the con-
the original circuit. Before removing the original tran- nection can be made as quickly as possible.
sistor, carefully note its position with respect to other 5. Always use a heat sink on the lead when solder-
circuit components as well as the lengths and place- ing. Gripping the lead or terminal with longnose pliers
ment of the transistor leads, and duplicate these details between the solder connection and case or body allows
as closely as possible with the ARCHER replacement the pliers to act as a heat sink, conducting heat away
transistor. Failure to observe this precaution can result from the internal elements of the device.
in improper tuning or circuit instability. The same
holds true for any replacement of Integrated Circuits. ABOUT CASE DIMENSIONS
specially in FM radios and TV Receivers. Failure to In some instances, the case of an ARCHER Semi-
3
conductor may be slightly taller or thicker than that of forward-biased. An NPN transistor should show
the original device or have a slightly different shape, the base 0.2 to 0.65 volts positive with respect to
particularly if the original device is a foreign type not the emitter (approximately 0.25 volts for a ger-
made to U.S.A. EIA (JEDEC) standards. These manium type and 0.6 volts for silicon). A PNP
mechanical differences should not affect the perform- transistor should show the base 0.2 to 0.65 volts
ance of the equipment in which the replacement is negative with respect to the emitter (0.25 volts for
made and normally will not prevent or complicate the germanium and 0.6 volts for silicon).
installation of the ARCHER replacement device. B. Check to see if the device is functioning as an
You should realize that cross-reference substitution amplifier. Short the emitter-base junction to re-
listings are created based on electrical parameters move forward bias. Voltage at the collector lead
(not necessarily on mechanical size or type). Thus, should rise to approximately the potential of the
when you make substitutions based on our listings, collector supply buss line. Any difference is caused
check for physical/mechanical compatibility. If space by ICES (collector-to-base leakage current). The
is limited, it would be a good idea to check physical closer the collector voltage approaches the buss
dimensions as well as electrical specs before making line, the lower ICES is and the better the transistor.
substitution.
II. Out-of-Circuit Testing
GENERAL PRECAUTIONS Again, for the best indication of transistor quality,
ARCHER transistor and ARCHER semiconductors use a good transistor checker. However, an ohmmeter
should not be inserted or withdrawn from circuits can be used as described here.
with the power on, because transient currents may Before using the ohmmeter, find out which polarity
cause permanent damage to the device. In some cases of the internal ohmmeter battery is connected to
ARCHER semiconductors are in metal cans and thus which test lead (not all ohmmeters have the + battery
could possibly become shock hazards if they are polarity connected to the red lead and the - battery
allowed to operate at a voltage appreciably above or polarity connected to the black lead). To determine the
below ground potential. polarity of the leads when using the ohmmeter func-
For the most effective protection, a power'transistor tion, use an external voltmeter or study the schematic
should be operated with an adequate heat sink and of your VOM.
with the lowest value of resistance or impedance in Also, remember that in most transistor circuits you
the emitter-to-base circuit consistent with driving sig- are dealing with low voltages and currents (in some
nal considerations. The transistor should be protected cases, very low). Therefore, NEVER use RX1 scale
against extremely high collector voltage pulses which (extensive currents can flow through a junction, per-
may be generated when the device is operated with manently damaging the transistor). It is best to deter-
inductive loads particularly when current transients mine the maximum amount of current available in
are present. each resistance range before using an ohmmeter for
When replacing a power transistor or rectifier which testing semiconductor junctions.
is attached to the equipment chassis, or to a special After you have evaluated your VOM for the above
heat sink, observe the following precautions: and are sure you will not damage a transistor (with ex-
A. In the case of oxide coated metal washers or cessive current or voltage in any given ohmmeter
wafers, which are frequently used as electrical insula- range), proceed as follows :
tors between the cases of power transistors and the
chassis or heat sink, it is important not to scratch, chip A. Small Signal PNP Germanium Transistors
or otherwise damage the oxide surface. 1. Connect the positive lead of your ohmmeter to
B. When installing an ARCHER power transistor, the emitter. Connect the negative lead to the
where a mica or oxide coated metal washer was used base. You should read 200-500 ohms.
to insulate the case of the original device electrically 2. Connect the negative lead to the collector. You
from the case, apply a thin coating of Heat Sink Com- should read 10K-100K. Shorting collector base,
pound (Radio Shack Number 276-1372) between the the resistance should decrease.
washer and the chassis or heat sink. B. Small Signal NPN Germanium Transistors
Reverse the polarity of the leads; the readings
TESTING A TRANSISTOR should be approximately the same.
C. Power PNP Germanium Transistors
Before replacing a transistor you want to be sure it 1. Connect the positive lead to the emitter. Con-
needs to be replaced. Always check the entire circuitry nect the negative lead to the base. The reading
to be sure the transistor requires replacement. should be 35-50 ohms.
The best method for checking transistors is to use a 2. Connect the negative lead to the collector The
good transistor checker (dynamic in-circuit and out- reading should be several hundred ohms. Short-
of-circuit type). However, a sensitive VOM can give ing collector to base, the resistance should de-
you a good indication of the quality of the device. crease.
I. In-Circuit Testing D. Power NPN Germanium Transistors
Reverse the polarity of the leads; , the reading
A. First, check to see if the emitter-base junction is should be approximately the same.
4
E. Small Signal PNP Silicon Transistors
1. Connect the positive lead to the emitter. Con- HANDLING OF INTEGRATED CIRCUITS
nect the negative lead to the base. The reading Because MOS devices have extremely high input re-
should be 1K-3K. sistance, they are susceptible to damage when exposed
2. Connect the negative lead to the collector. The to static electrical charges (even electrical charges that
readin~ should be very high (may show as an normally build up on the human body can cause
"open"). damage). To avoid possible damage to the devices dur-
F. Small Signal NPN Silicon Transistors ing handling, testing, or actual operation, the following
Reverse the polarity of the leads; the readings procedures should be observed:
should be approximately the same. 1. Except when being tested or in actual operation,
G. Power PNP Silicon Transistors the leads of devices should be in contact with a con-
1. Connect the positive lead to the emitter. Con- ductive material, to avoid build-up of static char_ge.
nect the negative lead to the base. The reading 2. Soldering iron tips, tools, metal parts of fixtures
should be 200-1K. and handling facilities should be grounded.
2. Connect the negative lead to the collector. The 3. Transient voltages may cause permanent dam-
reading should be about 1 megohm or more. age to the device if it is removed or inserted with the
H. Power NPN Silicon Transistors power on.
Reverse the polarity of the leads; the readings 4. Do not apply signals to the input with the power
should be approximately the same. supply off.
The resistance readings noted above can only be ap- 5. All unused input leads must be connected to
proximate; as long as you obtain somewhat propor- either Vss or Voo lwhichever is appropriate for the
tionate readings lemitter-base readings as compared logic circuit involved).
to emitter-collector) , you can safely assume the trans-
istor is OK.
ZENER DIODES-1 Watt

DIODES AND Catalog Vz lz Zz @ lz Case
RECTIFIERS Number Volts ±10% @ mA ohms max Style
276-565 5.1 49 7 0041

276-561 6.2 41 2 0041
276-562 9.1 25 7 0041
GENERAL PURPOSE DIODES RATINGS@ 276-563 12.0 21 9 0041
25°C 276-564 15.0 17 14 0041
lr (max) Vf (max)
Catalog PIV (min) If @ Vr @ If Case
Number v A p.A v Style BRIDGE RECTIFIERS
276-1101 50 1.000 10 1.6 0041 Catalog PIV (min) If (max) Case
276-1102 200 1.000 10 1.6 0041 Number v A Style
276-1103 400 1.000 10 1.6 0041 276-1146 50 4 M532a

276-1104 600 1.000 10 1.6 0041 276-1151 50 1.4 M548
276-1114 1000 2.500 200 1.0 A1vm 276-1152 100 1.4 M548
276-1122 75 0.010 250nA 1.0 A1 276-1161 50 1 Y1
276-1123* 60 0.085 15 1.0 A1 276-1171 100 4 M532a
276-1141 50 3.000 500 1.2 A3q 276-1173 400 4 M532a
276-1143 200 3.000 500 1.2 A3q 276-1180 50 6 M532a
276-1144 400 3.000 500 1.2 A3q 276-1181 250 6 M532a
276-1165t 40 1.000 5mA 0.55 A1 276-1185 50 25
*GERMANIUM
tSCHOTIKY
5
BIPOLAR TRANSISTORS
Direct Power Dlss. fr Iceo
Catalog Commercial @25 oc Typlcel Veao Veeo Veao le Ia @Vee@ le at max Case
Number Equivalent Mat. Appll. Polarity Free Air MHz V V V Max Max V mA Yea Style
276-1604# 2N3906 S G.P. PNP 350mW 250 40 40 5 200mA 60 0.1 T092

276-1617# 2N2222 S G.P. NPN 500mW 250 60 30 5 800mA 35 10 0.1 T018
276-2009 MPS2222A S G.P. NPN 625mW 300 75 40 6 800mA 50 10 10nA T092

276-2016 MPS3904 s s NPN 625mW 300 60 40 6 200mA 100-300 10 50nA T092
276-2017 TIP31 s p NPN 40W:t: 3 40 40 5 3A 1A 10-50 4 3A 300,..A T0220AB-2
276-2020 Tl P3055 s p NPN 90W:t: 3 100 70 7 15A 7A 20-70 4 4A 1mA T0220
276-2023 MPS2907 s s PNP 625mW 200 60 40 5 600mA 50 10 20nA T092
276-2027 MJ E34 s p PNP 90W:t: 3 40 40 5 10A 3A 20-100 4 3A 220,..A T0220
276-2030 2N3053 s p NPN 5W 100 60 40 5 700mA 50-250 10 150 T039
276-2041 2N3055 S P NPN 115W:t: 2.5 100 60 7 15A 7A 20-70 4 1A T03
276-2043 MJ2955 S P PNP 150W:t: 4 100 60 7 15A ?A 70 10 0.5 0.7mA T03
276-2055 2SC1308 S SW NPN 50W:t: 1500 400 6 7A 0.8A 3 2 4A 100,..A T03
276-2058 2N4401 S G.P. NPN 625mW 250 m in. 40 60 6 600mA 500 10 0. 1~tA T092
276-2068 TIP120 s p• NPN 65W:t: 0.1 60 60 5 SA 120mA 2500 3 500 0.2mA T0220AB-2
NOTE: All ratings given are for 25°C except where otherwise noted . #-Archer-Pack :j:With heat sink
MATERIAL:
$-Silicon ; G-Germanium
APPLICATION:
5-Switch P-Power amp/switch • -High Gain Darlington LL-Low Level
G.P .-General Purpose RF/IF-RF/IF frequency UHF-Ultrahigh frequency SW-TVSweep
USEFUL INFORMATION
ASSUME LOW / RL
"•• COMPARED TO rc
\
INPUT
'• I
OUTPUT
'• OUTPUT
'
'~ rl r -:'
Parameters of Common-Base Circuit Parameters of Common - Collector Circuit Parameters of Common-Emitter Circuit
Input Impedance Input Impedance Z;n = ({3 + 1)ZL Input Impedance Z;n = htertr
where , Load Impedance ZL = RL in parallel with input
Load Impedance ZL = RL in parallel with input ZL is RL in parallel with RE . impedance of next stage .
impedance of following stage .
Rs ~~c
Current Gain A;= "' = ,--h Output Impedance Zout = "/3+1 Current Gain A;= Ai;=hte
(In practice , a is 0 .95 to where , where,

0 .995 , or approximately 1.) R5 is the output imped , lc "'
hte = i3 = I;;"=~
ZL ance of the signal source .
Voltage Gain Av = ~ = gmZL Current Amplification A;= {3 AVe ZL
Voltage Gain Av = - - = -=gmZL
AVs rtr
Voltage Amplification Av = Less than unity
Power Gain
6
SPECIAL TRANSISTOR {FET)
SILICON N-CHANNEL JUNCTION MPF102

FIELD EFFECT TRANSISTOR 276-2062
GENERAL DESCRIPTION PIN CONNECTION

The MPF102 is designed for small signal applications. These include VHF
amplifiers and mixers.
BOTTOM VIEW
~
ABSOLUTE MAXIMUM RATINGS
(T A = 25 o C unless otherwise noted)
Drain-Source Voltage .... .... ......... ........ . ......· ........... 25 V
Drain-Gate Voltage ............................................. 25 V
Gate-Source Voltage ........................................... . 25 V
Gate Current ........... . ................. . ... . .............. 10 rnA
Total Device Dissipation ....... ... ............... . ............ 310 mW
Operating Junction Temperature . ....... . ..... ........ ........ . .. 125 °C
Storage Temperature Range . . ....... . ....... . . . .... .. .. - 65 to + 150°C
0
DRAIN SOURCE GATE
Drain and source may be interchanged 1

N-CHANNEL MOSFET TRANSISTOR IRF511
276-2072

The efficient geometry and unique proces~ing of the HEXFET design
achieve very low on-state resistance combined with high transconductance
FRONT VIEW
and great device ruggedness.
This transistor also features all of the well established advantages of
MOSFETs such as voltage control, freedom from second breakdown, very fast
switching, ease of paralleling, and temperature stability of the electrical
parameters.
FEATURES
• Fast switching
• Low drive current
• Ease of paralleling
• No second breakdown
• Excellent temperature stability
APPLICATIONS
• Switching power supplies
• Motor controls
• Inverters
• Choppers
• Audio amplifiers
• High energy pulse circuits

Drain-Source Voltage, Vos .. .. . .. . . ..... ...... . . .. ........ .. . .. ..... . . 60V
Drain-Gate Voltage (RGs = 1 M!l), VoGR· .. . . .. .. .. . .... ....... . . .... .. .. 60V
Gate-Source Voltage, VGs .. ....... . ........ . .. . .. . .. . .. .... ... . ..... ±20V
Continuous Drain Current, 10 @ Tc = 86°C .. ...... ... ... .......... ·..... 3A
Pulsed Drain Current, 1oM ........ . . .. ............ ... . .. .......... . .. . . BA
Maximum Power Dissipation, Po 1 • •• •• ••••• ••• ••••••• • • •••• • •••••• • • 20W \
Linear Derating Factor . .... . . ..... . ... . ....... .. . .. . ... ......... 0.16WiK
Inductive Current, Clamped, hM (See Fig. 1} L = 100 JLH . . ... . . . . ...... . .. 8A
Operating Temperature Range, T1 . . ........ . .. . ..••.... .•... -55 to +150 ° C
Storage Temperature Range, Tstg . .... .. ..... . ... ... .. . ..... -55 to +150°C
7
SPECIAL TRANSISTORS (FET)
IRF511 21s-2o12
TEST CIRCUITS
v, e,
Vos
PULSE
GENERATOR
;-------- --~
''
E1
'---- i =~ 5011
0.10
HIGH FREO
SHUNT
Figure 1-Ciamped Inductive Test Circuit and Waveform Figure 2-Switching Time Test Circuit
TYPICAL CHARACTERISTICS
8.O 10V 8.0

7.2
ov BO~ts PULSE TEST 80~ts PULSE TEST
7. 2r-Yos==25V 1/
8.0
7. 2
80/(& PULSE TEST 10V v
:3ffi 8~ :3 /I/ :3 /V 9V
6. 4 ~ 6.4
TJ=125°C
J
~ 6. 4
I~ v )...-- ~
..
~
!z
5.6
4.8 v 05 "' 7V
~
.!z
5.6
4.8
25'c,
lllV
~
.!z
5.6
4.8 ~ v v 05 -7V
-55'~
VJ ::! ~v
~ 4.0 ~ 4.0 4.0
a: /} a:
~ !L'
B a.2 5 1l
z
;;: .4
6V
z
:ca:
3.2
2.4
1(/ z
:
3.2
2.4
l.oiilll v 6V
.,__ ~
a:
Q
.6 Q 1.8
) Q
.6
.§ .§ 5v l--
~
.§ 5V
.8 0.8 .8
~
4V 4V
0 0 oil'
10 20 30 40 50 0 2 4 6 810 0 1.0 2.0 3.0 4.0 5.0
V 05, DRAIN-TO-SOURCE VOLTAGE- VOLTS v0 5 , GATE-TO-SOURCE VOLTAGE- VOLTS v 05, DRAIN-TO-SOURCE VOLTAGE-VOLTS
Output Characteristics Transfer Characteristics Saturation Characteristics
w 1.25 4.0 5
~ "'~ 3.6 1-- t-- ~JtS IPUL~E r1esr
0 v 05 = 25V
> us :- p ! 3.2 0
v
iii
~ 2. 8
~ 2.4 ~55'C- r- ./
v ;:
g
TJ= 5
v
v
/ Q
~ 1.
2.0
• //
25°C
125°C 0
.......
v
..
0
~ 1. 2//, / z
""""' VGs=10V
5 ~ 0. 8y ~
Q
o.5c""'""' 'o i 1.5~ - -
~
5
- 40 40 80 120
0.4
0 l 0
- 40
..*
0 0.8 1.6 2.4 3.2 4.0 4.8 5.6 6.4 7.2 8.0 40 80 120
> TJ. JUNCTION TEMPERATURE-°C 10, DRAIN CURRENT- AMPERES TJ• JUNCTION TEMPERATURE-°C
Breakdown Voltage Transconductance Normalized On-Resistance

vs Temperature vs Drain Current vs Temperature
8
SPECIAL TRANSISTORS (FET)
SILICON N-CHANNEL JUNCTION 2N3819

276-2035
FIELD-EFFECT TRANSISTOR
The 2N3819 is designed for general purpose small-signal applications. It
features low capacitance between drain and gate terminals and an excellent high- BOnOMVIEW
em
frequency figure of merit. It achieves a low noise figure and good power gain with
low crossmodulation and intermodulation.
ABSOLUTE MAXIMUM RATING

(TA = 25°C unless otherwise noted) SOURCE GATE DRAIN
Gate-Source Breakdown Voltage BVGSS ... .. . . . . . . . . . . • . . . . . . . . . . . . . . . -40 V

Zero Gate Voltage Drain Current loss ............. · .. ...... ..... ..... 20 rnA T092
Forward Transconductance g15 .........••...•....••....•••..... 7.0- mmhos
Reverse Gate Leakage less .. .. .. .... . ..... ..... .. ... . ..... .. ...... -100 pA
''ON" Resistance r 05 ...... . ..... . . . . . . . . . . . . . . . . . . . . . . . •. ... .• ... 500 ohms
Pinch Off Voltage VGS(OFF)· ... . . .. .... . . .....•.. ....... ..... . .. ..... -6.0 V
Output Conductance g05 . • . . • • . • . . • • . • . • • . . • . . • • • . • • • . . . . . • • . •. . . . 10 14mhos
Feedback Capacitance Crss· . . ... .. ................ . .... .... .. . ....... 0.9 pF
Input Capacitance Ciss· .... . ...................... .. ................. 4.0 pF
Power Gain Gp5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . 12 dB
Power Dissipation ........ . ............................... . ....... 360 mW
COMMON SOURCE
10 10 • 1.0
v08 • 15
Yos • o ~E
+ g,,
I
i,; v ~ ./ J! b 0 . . (x 10~/
/
ct 1.0 ~
;...-~
~
E
I 1.0
....
/ ~b,, ..
~ 0. 1
/"" /.~.
w ;; z
0
z ..!. ~
,.cg
t--1>,,.
~ "cz
...."
c /
.... / Yos= 1SV
Yas"" o
..
8 V 08 • 15V
Yos .. o
~
! 1V0.
100 200 500 1000
o.1
100 200 500 1000
!;
0 0.01
100 200 500 1000
FREQUENCY f - MHz FREQUENCY f - MHz FREQUENCY f - MHz
Input Admittance Forward Transfer Admittance Output Conductance

vs Frequency vs Frequency vs Frequency
COMMON GATE
100 0 i 1.0
IE
v08
Yos • o
• 1SV
- - g,,
~
I
i
I
/
i.!,.1.
b...lx10)./
/
l,;.
: 10 0
+btl v w
~ 0.1 / v ....v
~
0 .i!i
z r--....
g,. .:!;
lI "cz
.. v
0
c
/
~ ... v
./
..
0
0
Vos ""' 15Y
~ ~ Vas = o
!
1
1000
0.1
200 500 1000
" o.o1
0
100 200 500 100 100 200 500 1000
FREQUENCY f - MHz FREQUENCY f - MHz FREQUENCY t-MHz
Input Admittance Forward Transfer Admittance Output Conductance

vs Frequency vs Frequency vs Frequency
9
SPECIAL TRANSISTORS (FEn
BS170 N-CHANNEL TMOS FET

276-2074
GENERAL DESCRIPTION
This TMOS FET is designed for high-voltage, high-speed switching applica·
tions such as line drivers, relay drivers, CMOS logic, microprocessor or TTL- PIN CONNECTION
to-high voltage interface and high voltage display drivers.
FEATURES
• Fast Switching Speed-ton t 0 ff =
6.0 ns Typ =
• Low On-Resistance-5.0 Ohms Max
• Low Drive Requirement, Vcs(thJ = 3.0 V Max
• Inherent Current Sharing Capability Permits Easy Paralleling of Many
PIN 1. DRAIN
Devices 2. GATE
3. SOURCE

Drain-Source Voltage (Voss) ....... . .. . ........ . ..... ...... .... ... .. . . 60 V
Gate-Source Voltage (Vcs) .. . .. . ....... ..... ...... . . . .. . . . . .... ..... ± 20 V
Drain Current-Continuous {1) (I 0 ) . •. . . . . . . . . . . . . • . . . . . . . . . . . . . . .. .. . . 0.5 A
Total Power Dissipation@ Tc = 25°C (P 0 ) . . . .. . . . . . . . . . . . . . . . . . . •.. 0.83 W
Operating and Storage Temperature Range ............... - 55°C to + 150°C
(1) The Power Dissipation of the package may result in a lower continuous drain current.
TYPICAL APPLICATIONS
Switching Test Circuit Switching Waveforms
+ 25 v - t..u-
v,.
90%
Output 10%
Inverted
Input V1n
(V1n Amplitude 10 Volts)
- - - w i dPulse
th_ _ _
Vas(th) Normalized Versus Temperature On-Region Characteristics

2.0 2.0
I Vos = 10V
Vos = Vos /
..--
w 1.6 ~ 1.6 9.0V
10 = 1.0mA
~ ~
~
JL
-r--
8.0V
--
0
6 1.2 112
5
~
I'
!
> 0.4
0.8
0
-50 50
-- "z
~
~
t
0.8
0.4
Ill
II/
U/_.,
,_
/If
Ill 7.0V
6.0V
s.ov-
•.ov -
·100 10 20 30
T), JUNCTION TEMPERATURE V05, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Output Characteristics Capacitance Versus Drain-to· Source Voltage

2.0 100
Vas = 10V
VGs = OV
~ 1.6
...,..--
--
8()
~ ~
a.ov- 0::
r-
i
~
~
/ sw 1\
60
1.2 j;!
~ F- g \.\
7.0V
" ~ ::::--- 8.0V ;,<
-
~ 0.8 40
;.....-
~ ~ <
"u
~
-
.. - 1---
j 0.4 ~ :::::::-- s.ov
20
..........
c~
~~ eM,
.---
1.0 ~0
V05, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

3.0
4.0 V
4.0
' 10 20 30
V05, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
50
c.,
60
10
SPECIAL PURPOSE DEVICES (VARISTOR)
TRANSIENT/SURGE ABSORBER ERZ-C20DK201 U

276-568
ERZ-C14DK201 U
276-570
GENERAL DESCRIPTION
ZNR varistors are zinc oxide resistors whose resistance changes as a func- PIN CONNECTION
tion of the applied voltage. The ZNR has a bilateral and symmetrical V-I char-
acteristic curve and can therefore be used in circuits in place of back-to-hack
zener diodes. This gives your circuit clamping protection in either direction.
The ZNR provides a highly reliable and economical way to protect against
repeated high voltage transients and surges such as those produced by light-
ning, switching surges and noise spikes.
FEATURES
• Excellent clamping voltage characteristic and fast response time ( < 50 nsec.)
when subjected to impulse surges. Eliminates the discharge lag that is indic-
ative of gap-type arrestors.
• Bilateral and symmetrical V-I characteristic curve. The ZNR can, therefore,
be used both in AC and in DC circuits, for protection of either positive or
negative transients.
Varistor Voltage (V-I@ lmA DD) (185V 225V) ..... . . .. .............. . 200V
Applied Voltage ACRMs) . . . ...... . ...... .... .. .. . . .. . . ......... . .. . .. 130V
(DC) ......... ... ... . ........ . . . ............ . ....... 170V
Clamping Voltage@ Test Current (8 X 20 1-1sec) Vc(V) ..... .. . . .. . . . ... . . 340V
IP (A) (276-568) ... . . . ... . lOOA
IP (A) (276-570) ....... . . .. 50A
Peak Pulse Current (8 X 20 1-1s) 1 Time (276-568) ....... . .. . .. ... . . . ... 6500A
(276-570) ... . . .. . . . . ........ . .. 4500A
Energy (Jl (276-568) .... . ..... . .. . ....... . ....... . .. . .................. 70J VOLTAGE~
(276-570) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35J
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Power (276-568) . . . ... .. . . . ... .. . .... . ............. . . .. .. . .. . ..... . .. lW V-1 Characteristic Curve
(276-570) .... . .................. ... . . . . ..... .. . ... . . . ... .... 0.60W
Capacitance (PF@ 1kHz) (276-568) . . .. . . . .. . .. .. . .. . . . . . .. . .. . ..... 2000PF
(276-570) . . . ... . . ....... . .. . . .. _. .... . . . . . lOOOPF
Operating Ambient Temperature . ... . .. .. . . . .. . .. . . . . .. . . . . .. -40° + 85 ° C
Storage Temperature . . .. . ..... .... . . .......... . ............ -40° +125°C
...
TYPICAL APPLICATIONS ~
0
EQUIPMENT
>
PROTECTED
-H- TIME~
A: Original surge wave form

8: Clamping voltage using gap type arrestor
CIRCUIT C: Clamping voltage using ZNR
r: Discharge lag
Clamping Voltage Characteristics

Single Phase Line Surge
Three Phase Line Surge
Transformer Inductive Surge

by Pr,imary Switch Off
Solenoid Inductive Surge Solenoid Inductive Surge

by Thyristor Switching by Transistor Switching
11
SPECIAL PURPOSE DEVICES (SCR) (TRIAC)
276-1000 THYRISTORS
276-1020
276-1067
GENERAL DESCRIPTION
Thyristors and their trigger devices can take numerous forms. but they share these qharacteristics:
• They are "open circuits." capable of withstanding rated voltage until triggered.
• They become low-impedance current paths when triggered. and remain so. even after the trigger source is removed. until current
through that path stops. or is reduced below a minimum "holding" level. ·
SCRs TRIACs
Silicon-Controlled Rectifiers (SCRs) are Thyristors intended Triacs are bidirectional Thyristors. in which a single trigger
to switch load currents in one direction only. making them use- source turns the device on for load current in either direction.
ful for DC and ha lf-wave AC applications as well as full-wave Because they do not require a bridge rectifier in order to handle
app lications. in which bidirectional current is routed in one di- full-wave AC. Triacs are useful in AC power applications that
rection through the SCR via a bridge rectifier. require full source power control capability to be applied to the
load.
IGT VGT IGT VGT

Catalog Imax Vmax (max) (max) Case Catalog lmax Vmax (max) (max) Case
Number A v mA v Style Number A v mA v Style
276-1067 6 200 25 1.5 MU27 276-1000 6 400 50 2.5 MU27
276-1020 6 400 25 1.5 MU27
OPTOELECTRONIC INDEX BY
FUNCTION
FUNCTION CATALOG NO. PAGE NO.

DISPLAY 276-053 ......................... 18
276-064 ............ . ....... . .... 17
276-075 ......................... 17
276-081 . . . ... .... .. .... . ...... .. 15
DRIVER 276-134 ... ... ....... ........... . 16
EMITTER 176-142 ... . . ... . ... . . ......... .. 20
276-143 ... ..... . ............ . . . . 14
LED (BLINKING) 276-030 . ... . .. ..... ....... ...... 15
276-036 .... . . .. ....... . . .. ... ... 15
LED INDICATORS 276-018 ...... .• ................. 13
(CHART) 276-021 . ... . .. .... .... . . . ....... 13
276-022 ... . ..... . .... ..... ..... . 13
\ I
276-025 . . ... .. .... ... . .... . ..... 13
276-026 .. . . . ........ ......... ... 13
276-033 .... . ... ..... . . . ...... . . . 13 tU
276-037 .. . ... ....... ..... .. . .... 13
276-041 ............... . ......... 13
FIGURE 10
276-065 ......................... 13 Super high brightness LED with holder
276-066A ....................... 13
276-068 ... ....... . . .. ... ... . . ... 13
276-069 . .... .... ........ . . .. ... . 13
276-088 . .......... ..... . .. . ..... 13
LED (TRI-COLOR) 276-035 ................. .. . . ... . 19
PHOTOCELL 276-116 . .. . . ... ... .. . ... . ..... . . 18
PHOTOTRANSISTOR 276-145 . ....... ... . .... . .. . ... .. 19
SOLAR CELL 276-124 ..... .... ......... ....... 20
12
OPTOELECTRONIC CLEO)
LED INDICATORS
Max DC
Direct Peak Forward Reverse Forward Max Pwr
Catalog Commercial Wave Length Voltage Voltage Current Diss Fig.
Number Equivalent nM Color VF (V) VR (V) IF (MA) Po (MW) No.
276·018 PR5534S 700 RED 2.5 4 100 75 4
276-021 SLP-2368 565 YELLOW 2.8 3 30 70 5
276-022 SLP-2368 565 GREEN 2.8 3 30 70 5
276·025 R9-56 RED/GREEN 2.0 3.0 10 7
276-026 650 RED 3 50 100 2
276-033 TLR-147 700 RED 2.1 4 35 100 1
276-037 SLP-2358 565 GREEN 2.8 3 30 70 4
276-041 700 RED 1.75 3 70 140 3
276-065 369HHD 697 RED 1.8 5 20 75 8
276-066A SLA-591LT3 660 RED 2.5 (@20 MA) 4 50 100 9
276-068 700 RED 1.9 30 6
276-069 560 GREEN 2.1 30 6
276-088 SLP-888A 660 RED 2.2 (@2 MA) 3 20 70 10
G
CATHODE ANODE
(jJ
ANODE CATHODE
FIGURE 1 FIGURE 2 FIGURE 3

Mini.-ture LED with diffused lens. This LED This LED features a frosted diffused lens in This device is a jumbo LED with a diffused
is compatible with most TTL and transistor a plastic encapsulant. When the device is lens. It can be used in applications such as
circuits. It features a Fresnel lens design. on, it appears as a large, soft light source, pilot and indicator lamps.
making it ideally suited for front panel ap·
plica lions.
FIGURE 4
8
ANODE CATHODE
FIGURE 5
CATHODE ANODE
FIGURE 6
Subminiature LED with diffused lens. Th is This is a frame type solid state LED with a This is a subminiature LED indicator with
device has solid state reliability and is diffused lens. polished chrome reflective holder.
compatible with most TTL and transistor
circuits.
(1)
(3)
(2) ANODE
ANODE
I CATHODE
LONG LEAD IS CATHODE
FIGURE 7
This is a three terminal LED. The light col· FIGURES FIGURE9
or radiates " red " when terminals 2 and 3 This is a jumbo red LED. It consists of two This is a high-brightness red LED. It is
are used. Green light radiates when ter· LED elements connected cathode to cath· many times brighter than ordinary LEOs,
minals 1 and 2 are used. ode in a 10mm diameter housing. yet still runs cool.
13
OPTOELECTRONIC (EMITTER)
TIL906-1 P-N GALLIUM ALUMINUM ARSENIDE

276-143 INFRARED- EMITTING DIODE
This is a P-N Gallium Aluminum Arsenide Infrared-Emitting diode designed
to emit near infrared radiation when forward biased. Its output is spectrally
d)
compatible with silicon sensors and has a high power output with a zoo beam
w
angle.

Forward Voltage (Static) (VF) . .. . . .. . . . ..... . ......... . .. . . ........ . 1.75 V
ANODE
Reverse Voltage (VA) .... . ... . . .. ........ . .... .. .. ..... .. ... .. 3 V
Continuous Forward Current at (Or Below)
Z5°C Free-Air Temperature . . .. ... ... . ...... ..... . .... .. . . . . .... 100 rnA 0
TA = 25"C
Peak Forward Current (See Note 1) .......... . ..... . ..... ... . . . .... ... .. Z A 4
Reverse Current (VR = 3 V) .. . . .. .. .. . . . . .... . . .... . . . . .. .... . . .. .. . 100 J.LA
,I'\.
"'
Radiant Power Output (Po) (IF= ZO rnA) .. . ........ . . ... . ........ ... 1.5 MW
Emission Beam Angle Betw een
Half-Intensity Points ..... . .. . ....... . ....... . . . ..... . ..... . . .. .. . . .. zoo 4
f= 1kHz
Wave Length at Peak Emission (IF = ZO rnA) .. . . . .. . .. . . ... .. .... . .. 880 nM
Operating Temperature Range . . ... . .. .. . ... . . . . . .. . . . . . . .. -40°C To 80°C 1
f=40kHz \I= 10kHZ
Storage Temperature Range ..... . . ... . .............. . .. . .. -40°C to 100°C
NOTE: 1. This value applies for lw :s 10 ~s. f :s 1 kHz. See Figure 1. 4
DC
FEATURES 0.0 1
1~$ 10~-tS 100p.S 1m$
• High power output With a zoo beam angle tw - PULSE WIDTH
• Output spectrally compatible w ith silicon sensors Peak Forward Current

vs
Pulse Width
TYPICAL CHARACTERISTICS Figure 1
16
TA= 25" C
""\
0.9
14
J
./
;t
E / >
t:: 0.8
"'~ I \
TA = - 40"C
v ~
e
12
/ ~
0.7
rT \
/ 25"C /
v ::>
0
10
Po/ z
0.6
/ Vt:-- /
a:
w
~...
8
v ~
~
:
o.5
0 .4
3
2
v .,...-::v 75" C
....c
z
6
4 / ~/
w
>
i= 0.3
:l
I 1\
'/.:; 1:;:/
w 0. 2
1
o/ ~
a: 2
0~
/./ a:
0.1
0
'
0 10 20 30 40 50 60 70 80 90 100 20 40 60 80 100 20" 10" 0" 10" 20"
IF-FORWA RD CURRENT - m A IF- FORWARD CURRENT - mA 8 -ANGULAR DISPLACEMENT
Relative Power Output Radiant Power Output Relative Radiant Intensity

vs VS VS
Forward Current Forward Current Angular Displacement
'•='•·;c; I r;
100
[/ fos•c I
/I/ I/ 40"C
/J I
0
1.0 1.1
/ w
1.2 1.3
VF- FORWARD VOLTAGE-V
1.4 1.5 1.8
Forward Conduction
Characteristics
14
OPTOELECTRONIC (DISPLAY) (LED)
B1001R
276-081 HIGH EFFICIENCY RED BAR GRAPH DISPLAY -
GENERAL DESCRIPTION
The B1001R is a 10 segment bar graph display with separate anodes and
cathodes for each light segment. The packages are end stackable. PIN CONNECTION
TOP VIEW
FEATURES
• Large segments, closely spaced BAR 1 ANODE BAR 1 CATHODE
• End st ackable
• Fast switching, excellent for multiplexing BAR 2 ANODE BAR 2 CATHODE
• Low power consumption BAR 3 ANODE BAR 3 CATHODE

• Directly compatible with ICs
• Wide viewing angle BAR 4 ANODE BAR 4 CATHODE
BAR 5 ANODE BAR 5 CATHODE

(25°C Free Air Temperature Unless Otherwise Specified)
Power dissipation ....... . .. . ..... . .. . . . . . ... . ................... . .lOOmW BAR 7 ANODE BAR 7 CATHODE
Continuous fo rward current

Total ................ . ................. . .... . .... . . . . .... . .. . . . 300 rnA
Per segment ................................... . .... . . ... .. . .. . . 30 rnA BAR 9 ANODE BAR 9 CATHODE
Reverse voltage
BAR 10 ANODE 10 BAR 10 CATHODE
Per segment ........................ . ..... . ........... . .... ... .. . 5.0 V
Storage and operating temperature .......... . ....... . ...... . -30 to + 80°C
ELECTRO-OPTICAL CHARACTERISTICS
Forward Voltage ................... . .... . ...... .. . . .. . .... . . . . .. . . . 1.6 V
Peak emission wavelength ................. .. ...... . ... ... .. .... . . .. 655nm
F336GD
276-030 BLINKING LED
F336HD
276-036

The F336GD is a solid state LED with a green diffused plastic lens. The
F336HD is a solid state LED with a red diffused plastic lens. A built-in IC
flashes the LEDs on/off and can be driven directly by standard TTL and CMOS
circuits, eliminating the need for external switching circuitry.
FEATURES
• Built-in IC chip, flashes LED on and off to attract attention
• Pulse rate l .OHZ
• Tl 3/4 size
• Larger full flood radiating area
• l-inch leads
• 1 .2mcd @ VF = 3.0V
• IC compatible

Operating Voltage ................................. . . .. . .. . .... . ... . . . 5 V
Peak Inverse Voltage . . . .. . . . . . .... ... . . . . . . ... ........ . .. . .... . .... 0.4 V
Operating Temperature ............. . .......... . . . . .. . . ..... . . 0°C to 70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 20°C to + 85°C
Lead Soldering Temperature (1/16 inch from case) . . . . .. . . ... 5 sec. @ 260°C
ELECTRO-OPTICAL CHARACTERISTICS
Luminous Intensity . . .............. .. .. . . . .. . . . . .. . . ....... .. . .. .. 1.2 mcd
Emission Peak Wavelength (F336GD) ..... . ... .......... . .. . .. . . .. . . 565nm
(F336HD) .. .... . ............... . . . .. .. . . 597nm
Spectral Line Halfwidth (F336GD) . . . . . . .... . .......... . . . . .. . .. . .. . . 30nm
(F336HD) .. ... . . . . . . ......... .. . .. . . .. .... .. 90nm
Peak Current (50% Duty Cycle) .... . .. ... . . .. ·... . . . ...... .. . . .... . . 3.5 MA
Pulse Rate .. . . . . .. . . ...... . . . . .. . . ... . .... . . . . . .. . . .. ... . . . ..... . 2.0 HZ
15
OPTOELECTRONIC (DRIVER)
MOC3010 OPTOCOUPLER TRIAC DRIVER

276-134

This device consists of a gallium-arsenide infrared emitting diode. optically
coupled to a silicon bilateral switch and is designed for applications requiring iso-
TOP VIEW
lated triac triggering. low-c urrent isolated ac switching. high electrical isolation
(to 7500 V peak). high detector standoff voltage. small size. and low cost. ANODE
TRIAC
INFRARED EMITTING DIODE MAXIMUM RATINGS CATHODE DRIVER SUBSTRATE
5 (DO NOT CONNECT)
Reverse Voltage ...... .. . . ..... ................... .. ............. 3.0 volts
Forward Current-Continuous ........ . ..... . ..... . ... . . . ... .. .. ... . 50 rnA
Total Power Dissipation@ TA = 25•c .. .............. ... .. . ....... 100 mW
NC
....____ _,
'---+--4.,- ~:::~INAL
OUTPUT DRIVER MAXIMUM RATINGS

Off-State Output Terminal Voltage ............................. . .. 250 Volts
On-State RMS Current TA = 25•c ........................ . ........ 100 rnA
(Full Cycle. 50 to 60 Hz T A = 7o·c) ............ . ................. 50 rnA
Peak Nonrepetive Surge Current ........................ .. ........... 1.2 A
(PW = 10ms. DC= 10'Yt:)
Total Power Dissipation@ TA = 25•c .......... . .... . ...... . ...... 300 mW
Derate above 25•c ........................................... 4.0 mW/"C
TOTAL DEVICE MAXIMUM RATINGS

Isolation Surge Voltage (ls) .... ......... ....... .. ..... ...... ..... . 7500 Vac
(Peak ac Voltage. 60Hz. 5 Second Duration)
Total Power Dissipation ........... ... ............. . ..... .. ....... 330 mW
Junction Temperature Range ....... ..... . ................... -40 to +too•c
Ambient Operating Temperature Range ..... .' ..... . ....... .. .. -40 to +7o•c
Storage Temperature Range . ..... ................ . .......... -40 to + 15o•c
Soldering Temperature (10s) ........................................ 26o•c
APPLICATIONS TYPICAL CHARACTERISTICS
<
E
1800 I
MOC3010
120V
60Hz .ffi
::
1l
~ -400
Resistive Load Z-800~~~~~~-L~~~•
0 -12 -8 -4 12
ON-STATE VOLTAGE VrM - V
• 1800 On-State Current vs

MOC3010 C1 On-State Voltage
Inductive Load with Sensitive Gate Triac

(IGT,;; 15mA)
~ 1.1 r---t-'"'"-1=-+---+-+--+--1
::;
~ 0.9 r---+--l-+---+"""---io---+--1
• 1800 a:
0
z 0.7f--+-l-+---+-+--+~
MOC3010 C1
o.s'---L.-....I_....L.___j__ _J_-L--'
-40 -20 20 40 60 80 100
AMBIENT TEMPERATURE TA- oc
Inductive Load with Non-Sensitive Gate Triac Trigger Current

(15mA < IGT < 50mA) vs Temperature
16
OPTOELECTRONIC (DISPLAY)
COMMON CATHODE DISPLAY MAN74

276-075

This is a red .3 inch common cathode RHDP Display device with a bright-
ness or luminous intensity (Per Seq. MIN) of 125 JLCd @ lOrnA.
TOP VIEW
APPLICATIONS
• Instruments
• Test Equipment
• Office Machines
• Computers
• Automobiles
• Clocks/Radios
• Communication Equipment
• Calculators
• CB Radios

Forward Voltage .. ... .. . . .. . .... .......... ..... ...... . ... ..... . .. .... 2 V
Forward Current .. .. ...... . .... ..... ........ . . ...... ............. . 20 rnA
Power (Pn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700 m W
Wave Length. ..... ............................................... 660 nM
Brightness/Luminous Intensity @ lOrnA............................ 125 JLCd
BIG HI-EFFICIENCY RED LED

EL-811HR
276·064
PIN CONNECTION
GENERAL DESCRIPTION 12 11 10 9 •
The 276-064 is a 0.79" diameter hi-efficiency Red LED. This device is ideal for
a variety of applications where a large bright source is required.

Reverse Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V
Reverse Current (Vr =
5V) . . .. .. . ... . .... ...... ... . ..... .. . ........ lO~tA
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40°C To 85°C
Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40°C To 100°C
Lead Soldering Temperature ................... . ..... 260°C For 5 Seconds
[1.6mm (0.063 inch) From Body]
Spectral Line Half-Width (A>-.) ......................... .. ........... 45mm
Power Dissipation (Pd) .............................. .. ........... lOOmW
Peak Forward Current (duty 1/10. 1KHz) lf (Peak) . . . . . . . . . . . . . . . . . . . 160mA
Recommend Operating Current lf (Rec) ... . .. . ..... . .. ........ .... .. 20mA 2 3 4 5
Average Luminous Intensity 1.2 (lf =

lOrnA) lv . . . . . . . . . . . . . . . . . . . . . 25~tcd
Luminous Intensity Matching Ratio lv-m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2:1
Forward Voltage (lf = 20mA) Vf .................................... 2.8 V
PIN FUNCTION
1 CATHODE
FEATURES 2
3
ANODE
CATHODE
•0.79" (20.0mm) big LED. 4
5
ANODE
CATHODE
• Graphic stacking allowable. 6
7
ANODE
CATHODE
• Suitable for multiplex operation. 8 ANODE
• High luminous intensity. •

,
10
CATHODE
ANODE
CATHODE
• Solid state reliability. 12 ANODE
17
OPTOELECTRONIC (DISPLAY) (PHOTOCELL)
276-053 0.3" SOLID STATE SEVEN SEGMENT DISPLAY ttiJI.

The 276-053 is a common anode LED numeric display. Th.e large 0.3" high
character size generates a bright, continuously uniform 7 segment display. De- TOP VIEW
signed for viewing distances of up to 10 feet, this single digit display has been
human engineered to provide a high contrast ratio and wide viewing angle.
FEATURES
• Fits 14 pin DIP socket
• Excellent character appearance-continuous uniform segments; wide viewing
angle; high contrast
• IC compatible-1.6 V per segment
• Standard 0.3" DIP lead configuration; PC board or standard socket mountable
• Both left and right decimal points
APPLICATIONS
• Electronic calculators • Frequency counters
• TVs • Digital clocks
• Radios
RADIANT CHARACTERISTICS (IF=20mA) TA=25•c
ALTERNATE
Luminous Intensity .... . ..... ..... ..... . ............ . .. . ... ... .... 250 mcd COMMON ANODE CONNECTION
PIN FUNCTION
Wavelength (Peak) . . ..................................... ..... ... 655 nM PIN FUNCTION
1 CATHODE a 1 NO PIN
2 CATHODE t 2 ANODE
3 ANODE 3 CATHODE· f
ABSOLUTE MAXIMUM RATINGS 4
5
NO PIN
NO PIN
4
5
CATHODE· g
CATHODE·e
Power Dissipation T A=25•c . . .. . .. .. . . .. . .. .. . ...... .. .. . .. . . ... . .. 400 mW 6
7
CATHODE dp
CATHODE e '
7
CATHODE· d
NO PIN
Average Forward Current/Segment or Decimal Pt. TA = 25°C . . ........ .. 25 rnA 8
9
CATHODE d
NO CONNECTION '
9
NO PIN
ANODE
CATHODE c CATHODE-dp
Peak Forward Current/Segment or Decimal Pt. T A=12°C 10
11 CATHODE g
10
11 CATHODE-c
(Pulse Duration 500f'S) . .... ............... . ................... . ... 150 rnA 12
13
NO PIN
CATHODE b
12
13
CATHODE-b
CATHODE-a
Reverse Voltage per Segment or Decimal Pt. .... . . .. .... . .... . ....... . . . 6 V 14 ANODE 14 NO PIN
Operating Temperature Range ............... ..... .... . . . . . .. -20 to +85oC

Storage Temperature Range ... . . . . .. . . ........ ...... ...... ... - 20 to +85°C
Max Solder Temperature 1/16" Below Seating Plane (t .;;; 5 sec.) ....... . . 230°C
276-116 CADMIUM SULPHIDE PHOTOCELL

GENERAL DESCRIPTION CONNECTIONS
A cadmium sulphide photo cell is a light variable resistor which is most sensi-
tive in the green to yellow portion of the light spectrum. With it you can use light
BOTTOM VIEW
to control many electronic devices. Max. resistance .5 meg., min. resistance 100
ohms, max. voltage 170 V, max. wattage .2 watts, rugged epoxy case.
APPLICATIONS
•
•
•
•
Night light
Light control
Burglar alarm
Relay
0
SPECIFICATIONS
• Shape ... . . ...... .... ... . . .. .. . ... ..... .. . ... ... .... . ... . . . ..... Round
• Sensitive Area .... .. ..... .. . . ....... . ....... .. . ... ........ . .. .07 sq. in.
• Weight . . . . . .... . . . ...................... . .... . . . .. . ... . ..... 1.56 gms.
• Resistance at 1 Ftc (2870oK) . .... ....... . . .. ...... .... .. . 1.7k Ohms . 40%
• Typical Resistance 100 Ftc (2870°K) .. . . . ... . . .... . .. .... .. .. . . . 100 Ohms
• Resistance Dark Minimum (1 Minute) . ... ....... . .... . . . . .. . 0.5 Megohms

Max. Applied Voltage (ac or de) . ... . . . ....... . ..... ..... .. .... . 170 V peak
Max. Power Dissipation at 25°C . . .... .. ... .. ...... . .... . .. . .... . . . . 2 watts
Power Derating. .. . ... .... . .... . . . .. . . . ..... . . .. ..... . Linearly to o @ 75oC
Operating Temp. Range ..... . ... . ... . .. ..... .. .... ... .. ..... - 40 to +75°C
18
OPTOELECTRONIC . (LED) (PHOTOTRANSISTOR)
TRI-COLOR LIGHT EMITTING DIODE XC-5491

276-035

The XC-5491 tri-state LED provides red. green. and yellow emission in the
same package. This LED is a popular .200 diameter. two-leaded package contain-
BOTTOM VIEW
ing a red and green LED chip in inverse paralleL By reversing the polarity of the
'"'"'moo~"'~
applied current. the LED will emit red or green light while an AC voltage results
in yellow light. The chips used in the XC-5491 are brightness matched so that the
light output is uniform. This eliminates the necessity for the special drive circuits
previously required with tri-state lamps.
These lamps provide the designer with the capability of efficiently displaying
three functions with one indicator. This reduces the number of front panel
indicators and simplifies design.
FEATURES
•
•
•
3 States-red. green. and yellow
Equal brightness in all three colors
Popular T 1'V.. size package
~
GREEN
am,. ill
• Wire wrappable leads
SHORT LONG 'fl
Forward Current ................... ... ............................ 25 rnA
Peak Reverse Voltage .......... . ................. . .... . .. ............. 5V
Power Dissipation .. .............................................. 100 mW
LEAD
Red Cathode
Green Anode
LEAD
Red Anode
Green Cathode J
0~ I
Operating Temperature Range ... ... .................... . .... -55 to +85°C 1.000
MIN
Lead Solder Temperature ............ .. .... . ........................ 260°C
o.o•• I
----..;..
Jo.,oL
--r-
INFRARED PHOTOTRANSISTOR TIL414

276-145
e
The TIL414 is an NPN silicon phototransistor in A T-1 3/4 style case. It pro-
vides high speed and high photosensitivity. suitable for IR switching applications. BOTTOM VIEW
CATHOOE
ABSOLUTE MAXIMUM RATINGS NOICATOR
Collector-Emitter Voltage ............ ... .. ........................... 50 V
Emitter-Collector Voltage .................. . .... .. ............... . .. . . 7 V EMITTER OLLECTOR
Power Dissipation ....... . .. ....... .. ..... . ..... . ...... ... ......... 50 mW

Operating Temperature ..... .. . .... ............. . .... : .. . .. -40° to +100°C
ELECTRICAL CHARACTERISTICS (Typical)
Dark Current (V CE = 30 V) ..... . ................................ . .... 25 nA
Light Current (VeE= 5 V•E. = 20mW/cm2) ............................ 7 rnA
Collector-Emitter Saturation ...................... . ........... ....... 0.4 V
Rise Time ......................................... . ..... . ........... 8 ,.,s
Fall Time ................................... .. ...................... 6 ,.,s
30
IRAADIANCE
50
e_ -
70
mWicm2
.
Collector-Emitter Saturation Voltage
vs lrradlance
19
OPTOELECTRONIC (EMITTER)(SOLAR CELL)
276-142 INFRARED EMITTER AND DETECTOR

GENERAL DESCRIPTION
The 276-142 is a pair consisting of an infrared photodetector and an infrared- PIN CONNECTION
emitting diode. The diode is capable of emitting radiant energy in the infrared re-
gion of the spectrum.
BOTTOM VIEW
FEATURES
• Spectrally and mechanically matched ~ ••m Q'''"~'"

~~~CATHODE
• High power e fficiency ... typically 5 percent at 25' C

Photodetector
Collector-Emitter Voltage ............ . .. . . . .. .. ........ .. .. . .......... 20V
GRAPHIC SYMBOL
Collector Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. ..... 25mA
Continuous Device Dissipation at (or below) 25' C Free-Air Temperature 50mW
Operating Free-Air Temperature Range ... . ................... - 40 to +80' C
Storage Temperature Range ... . . .. .... . .. . ................ . . -40 to +85' C
Lead Temperature 1/16 Inch from Case for 5 Seconds . . . .. .. . .... . ..... 240' C DIODE PHOTODETECTOR
Infrared-Emitting Diode
Reverse Voltage ... . . . ..... .... .... . ... . ... . . . . ... . . . . .. . ..... . ....... 2V
Continuous Forward Current . ... ....... . ............... . ...... . .. . .. 40mA
Radiant Power Output . ... .. . . . . . . .. . . . . . .. . ... .. .. . . . ... .. .. 0.5mW
Wavelength at Peak Emission ...... .. . . ... .... .. ... ... . ........ . ... 915mm
276-124 2.5x Scm SILICON SOLAR CELL
GENERAL DESCRIPTION CONNECTIONS

A solar cell is a silicon semiconductor device which converts light energy di-
rectly to electricity. A typical 2.5 X 5cm cell will produce 0.42 volt and up to .18 FRONT VIEW
amp of usable current. The power generated is affected by the load resistance
(circuit powered by cell) strength of sunlight and temperature.
Be extremely careful when soldering leads. Use only a very fine wire (# 26 or
thinner) and use a small soldering iron (less than 50 watts). Solar cells may be
connected in series to produce more voltage and in parallel for more current.

Voltage (Open Circuit): ............ . .. . ..... . ....... . ................ 0.55V NEGATIVE LEAD- POSITIVE LEAD +
Current (short circuit): . . . , .. . ... . .................. . . . ....... . .... 0.2A (SOLDER TO FROHn (SOLDER TO BACK)
(Test conditions: Full sunlight at noon on a clear day at 25' C (76' F) )
0.25
0.20
0.15
-\
0.10
1\
0.05
\
0
100 200 300 400 500
\ 600
VOLTAGE- mV
Current vs Voltage
20
DIGITAL (CMOS)
QUAD TWO-INPUT NOR GATE 4001

276-2401
GENERAL DESCRIPTION / PIN CONNECTION

The 4001 quad 2-lnput NOR gate is constructed with MOS P-channel and N- TOP VIEW
channel enhancement mode devices in a single monolithic structure. These com-
plementary MOS logic gates find primary use where low power dissipation and/ Y_oo
or high noise immunity is desired.
This device contains circuitry to protect the inputs against damage due to high
static voltages or electric fields; however. it is advised that normal precautions be
taken to avoid application of any voltage higher than maximum rated voltages to
this high impedance circuit. For proper operation it is recommended that Yin and
Vout be constrained to the range Vss ::;(Yin or Voutl ::;;y oo·
Unused inputs must always be tied to an appropriate logic voltage level (e.g..
either Yss or Yool ·
FEATURES
• Quiescent current = 0.5 nA typ/pkg @ 5 Vdc
• Noise immunity= 45% ofV00 typical v..
• Diode protection on all inputs
• Supply voltage range = 3.0 Vdc to 16 Vdc
• Single supply operation-positive or negative
• High fanout > 50
• Input impedance = 1012 ohms typical
• Logic swing independent of fanout

(Voltages referenced to V55)
DC Supply Voltage . .......... . .. . .. . .. . ........... . ..... . - 0.5 to + 16 Vdc
Input Voltage. All Inputs .. . . .. . . . . . . . . . ....... . . . .. . . . - 0.5 to V00 + 0.5 Vdc
DC Current Drain per Pin ... . ... ... ........ . ... . ... . . . .. . ........ 10 mAde
Operating Temperature Range. . . . . . .. . .... . .... . . . . .. . ..... -40 to +Bs· c
Storage Temperature Range ... .. . . .. . .. . . . .. . ... . .... .. . . ... -65 to + 1so· c
SWITCH TIME TEST CIRCUIT SYNC TIMING WAVEFORMS
Voo
14
INPUT
l r J
20ns l- 20ns
J~%~"',"4:;-----,\I.. ______ :: 0
INPUT
t---<>--r---<> OUTPUT IPlHr _ _ __
INVERTING
I/ VoH
4001 OUTPUT
1--'-,;_--f--'
J 't--1!-_ ,-TL-H_ _ _ Vol
tPHL F VoH
Vss
•An unused Inputs of OR, NOR gates must be connected to v 55.
NON·INVERTING
OUTPUT
Jl\_[ ITHL
Vol
+ 9V
Voo
811
SPEAKER
1MII 100K
O.olp.F LEO flashes 1·2 times/second

Tone frequency is about 1kHz
Gated Tone Source LED Flasher
21
DIGITAL (CMOS)
4011 QUAD TWO-INPUT NAND GATE

276-2411

The 4011 is constructed with P and N channel enhancement mode devices in a
single monolithic structure (Complementary MOS). Their primary use is where TOP VIEW
low power dissipation and/or high noise immunity is desired.
Yoo
This device contains circuitry to protect the inputs against damage due to high,
static voltages or electric fields; however, it is advised that normal precautions be
this high impedance circuit. For proper operation it is recommended that Vin and
Vout be constrained to the range Vss .;;; (Vin or Vout) .;;; VDD
Unused inputs must always be tied to an appropriate logic voltage level (e.g..
either Vss or V00).
FEATURES
• Quiescent current= 0.5 nA typ/pkg@ 5 Vdc
• Noise immunity = 45% of VDD typical
• Double diode protection on all inputs

(Voltages referenced to V88 )
DC Supply . . .. . ... . ...... . . . ... ... .. . . . . . .... .. . .. . .... . -0.5 to +16 Vdc
Input voltage. All Inputs ... .... .. . . .. .... .. ....... . ... - 0.5 to V00 + 0.5 Vdc
DC Current Drain per Pin . ..... . . . .. . . .... .... .. . ...... . .. . . .... . 10 mAde
Operating Temperature Range .. .. .. . .... .. . ..... .. .. . .. . . ... -40 to +85•C
Storage Temperature Range . . .. .. .... . . . ..... .. .... . ... . . .. . - 65 to + 15o•c
SWITCH TIME TEST CIRCUIT SYNC TIMING WAVEFORMS
Yoo
INPUT
-,~ ~
r~:•• J
r--
[20ns Yoo
14 ~0~·¥ I\___ ov
INPUT
IPLH~----
.., 1----<>-----<0 OUTPUT
INVERTING
~-ITLH
OUTPUT
VoL
J
NON· INVERTING
OUTPUT
Vss
•An unused Inputs of AND, NAND gates must be connected to v 00.
TO PIN 3
OF 550240
CLOCK
TO PINS 1 & 2
OF 850240
Display flashes once per second when E is high. ClOCK
This produces bagpipe and other unusual sounds.
Adjust R1 to vary interruption rate.
Display Flasher Special Effects
22
DIGITAL (CMOS)
DUAL TYPE D FLIP-FLOP 4013

276-2413

The 4013 dual typeD flip-flop is constructed with MOS P-channel and N-chan- TOP VIEW
nel enhancement mode devices in a single monolithic structure. Each flip-flop has Voo
independent Data, (D). Direct Set, (S), Direct Reset. (R). and Clock (C) inputs and
complementary outputs (Q and Q). These devices may be used as shift register
elements or as type T flip-flops for counter and toggle applications.
this high impedance circuit. For proper operation it is recommended that Vin and
Vout be constrained to the range Vss ,;; (Vin or Vout) ~ Voo·
Unused inputs must always be tied to an appropriate logic voltage level (e.g ..
either Vss or Vool·
FEATURES
• Static operation
• Quiescent current = 2.0 nA/package typical @ 5 Vdc v,
• Noise immunity = 45% of V00 typical
• Diode protection on all inputs
• Single supply operation
• Toggle rate= 4 MHz typical @ 5 Vdc
• Logic edge-clocked flip-flop design-logic state is retained indefinitely with
clock level either high or low; information is transferred to the output only on TRUTH TABLE
the positive-going edge of the clock pulse.
• Capable of driving two-low-power TTL loads, one low-power schottky TTL INPUTS OUTPUTS
load or two HTL loads over the rated temperature range. Clockt Data Reset Set Q Q
- L L L L H
ABSOLUTE MAXIMUM RATINGS - H L L H L
(Voltages referenced to V88) - X L L
DC Supply Voltage ... . ....... .. .. .. ... .. ....... , .. ....... - 0.5to + 16 Vdc
Input Voltage. All Inputs .. .. .. . .... ... ... . .. . .. .. .. . . - 0.5 to V00 + 0.5 Vdc
X
X
X
X
H
L
L
H H L
NoLT:'J'
DC Current Drain per Pin ....... . ..... . . . ... . .... . . .. . .. .. .. ..... 10 mAde X X H H H H
Operating Temperature Range ... . .... .. ..... . .... .. ... .. .... - 40 to + 85°C X = Don't Care H = High Level
Storage Temperature Range ............... . ............... .. - 65 to + 150°C L = Low Level t = Level Change
TYPICAL APPLICATIONS SYNC TIMING WAVEFORMS
1 2 nth .
ll-20ns \[20ns
~"AJ cO
Voo
Q Q DATA(O) __j,f~%
..J ~
10%
Vss
c
-1'
lj
~-lo<>tH) -~ ~- 20ns V
90% DO
CLOCK
CLOCK (C) SO%10%
J··~
Vss
n-Stage Shift Register
•'"
0 at-- - - , Q
OUTPUT(Q)
'"'"It ...: '·"r
So%
VoH
CLOCK o--+-~ C c Vol

Inputs R and S low. .THlJ ~
Data, Clock, and Output
Binary Ripple Up-Counter (Divide-by-2")

20nsl r l 1- 20ns v
~ ~~
SET(S)
_xo~~ fL--- DO
L ,w- 20nsll- r--

••
Vss
r----I o at-~--+l Q al--;---o a
90%
-1 V
DO
RESET (R) 50%
--+---J10% j v55
~- IPlH _ J -·r tPHl VoH
OUTPUT(Q)
___/ov 70
\______ VoL
Modified Ring Counter (Divide-by-(n + 1)) Set, Reset, and Output
23
DIGITAL (CMOS)
4017 DECADE COUNTER/DIVIDER

276-2417

The 4017 is a five-stage Johnson decade counter with built-in code converter.
TOP VIEW
High-speed operation and spike-free outputs are obtained by use of a Johnson
decade counter design. The ten decoded outputs are normally low, and go high
only at their appropriate decimal time period. The output changes occur on the
positive-going edge of the clock pulse. This part can be used in frequency divi-
sion applications as well as decade counter or decimal decode display applica-
tions.
this high impedance circuit. For proper operation it is recommended that Yin and
Vout be constrained to the range V~ (V in or Vout),;;;y DO·
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either Vss or Voo-
FEATURES
• Fully static operation
• DC clock input circuit allows slow rise times
•
•
Carry out output for cascading
12 MHz (typical) operation @ Voo = 10 Vdc ...
• Quiescent current = 5.0 nA/package typical @ 5 Vdc
• Supply voltage range = 3.0 Vdc to 16 Vdc TRUTH TABLE (Positive Logic)
• Capable of driving two low-power TTL loads, one low-power schottky TTL
load or two HTL loads over the rated temperature range Clock Decode
Clock Enable
Reset Output= n
ABSOLUTE MAXIMUM RATINGS L X L n
(Voltages referenced to Vss) X H L n
DC Supply Voltage . . ... .. . ...... .. . .. .. ............. .. .. . -0.5 to + 16 Vdc X X H QL
Input Voltage, All Inputs ........ ......... . ..... . .. .... - 0.5 to V00 + 0.5 Vdc ~ L L n+ 1
DC Current Drain per Pin . . ....... . .. ......... . .... . .... . ... . . . .. 10 mAde "'-- X L n
X _r- L
Operating Temperature Range . . ............ . .. . ... ... .. . . .. . - 40 to + 85•C n
Storage Temperature Range ..... . .... . . . . . . ... .. . .. . . . .... . . - 65 to + 15o·c 1 """\..._ L n + 1
X = Don't Care If n <5 Carry = "H",
Otherwise = "L"
L = Low Level H = High Level
4017 4017
15 14 13 13 14
16 15
CLOCK . TON
Yoo ClOCK TON For N= 9, ground pin 15.
Count to N and Halt Count to N and Recycle
24
DIGITAL (CMOS)
INVERTING HEX BUFFER 4049

276-2449
GENERAL DESCRIPTION PIN CONNECTIONS

The 4049 hex inverter/buffer is constructed with MOS P-channel and N-
channel enhancement mode devices in a single monolithic structure. These
complementary MOS devices find primary use where low power dissipation
and/or high noise immunity is desired. These devices provide logic-level con- TOP VIEW
version using only one supply voltage, Vee- The input-signal high level (VIH) NC NC
can exceed the Vee supply voltage for logic-level conversions. Two TTL/DTL
loads can be driven when the devices are used as CMOS-to-TTL/DTL convert-
ers £Vee= 5.0 V, VoL ::5 0.4 V, IoL~ 3.2 rnA). Note that pin 16 is not connected
internally on this device; consequently connections to this terminal will not
affect circuit operation.
FEATURES
• High source and sink currents
• High-to-low level converter
• Quiescent current = 2.0 nA/package typical @ 5 Vdc

(Voltages referenced to Vss. Pin 8)
DC Supply Voltage ............ . ........... .. ..... . ....... -0.5 to +16 Vdc
Input Voltage, All Inputs ................ . . ... ......... - 0.5 to Voo +0.5 Vdc
DC Current Drain per Input Pin.... .. .. . ... . . ..... . ............... 10 mAde
DC Current Drain per Output Pin . . . ................... . ... .. . ... . 45 mAde
Operating Temperature Range . . . .. .......................... - 40 to +85"C
Storage Temperature Range ................................. -65 to +150"C
TYPICAL CHARACTERISTICS Vee Vee
~...
Vss
~·.. - Yss
- YoH- Voo
Yos- Vos-Y
- OL
~ 18 ~ 0 ~ 180
~ ~ 5~ !..#'
I ..ffi I
.f,L ~
1 Yos=SV Vas=15V-=
g I
1
~ -1 0
r/ I
w I
-- -ssoc
- +125°C
a:
a:
B
1~~--- a:
a:
120
....r
"~ 10
- 20
v "0 80
1..; 10V
I
v
..~ L
w
0
> I
I
§
g
- 30
f-. +- --- /
I/1SV
-I MAXIMUM=
"'z
iii
.. 40
L
/
r-
CAUTION:MAXIMUM
~ACKiGe...oiSSPATiON
I
~
0
~ IV"
"~ : I I v V- - _lc.!!;"!!.iTJ-l!L MU~T Bl OBiER~ED
I - 4 SV
10 15 18 5 -SO -10 -8 -6 -4 -2
"0 ~
0~
0 2 4 6 8 10
~ Y1N,INPUT VOLTAGE -VOLTS ~ 1v
05,DRAIN-TO-SOURCE VOLTAGE-VOLTS
.9 V05, DRAIN-TO-SOURCE VOLTAGE-VOLTS
Output Voltage Output Source Current vs Output Sink Current vs

vs Input Voltage Draln·T~urce Voltage Drain-To-Source Voltage
Voo
R2
Voo
C1 R1
IN <>---j I-->'-M.-_._--J
0.01JlF 1 M!! 7
1,2,3 = 1/2 4049

1.2 :::: 113 4049 Note that the inverters are used in a liNEAR mode.
Pulse Rate = 1/1.4R1C1 Gain = R21A1
Clock Pulse Generator Linear lOX Amplifier
25
DIGITAL (CMOS)
4066 QUAD BILATERAL SWITCH

276-2466

The 4066 consists of four independent switches capable of controlling ~ither TOP VIEW
digital or analog signals. This Quad Bilateral Switch is useful in signal gating,
chopper, modulator, demodulator, and CMOS logic implementation.
static voltages or electrical fields; however, it is advised that normal precautions 1-
IN/OUT -, ........- - - - - '
be taken to avoid applications of any voltage higher than maximum rated

voltages to this high impedance circuit.
For proper operatio.n it is recommended that VIN and VouT be constrained to
the range Vss .;; (V1N or VouT) <;; Voo. OUT/IN -;;
3, - -........- - - - , '---f---:1:=-
2 CONTROL D
Unused inputs must always be tied to the appropriate logic voltage level (e.g.,
either Vss or V00) . IN/OUT -,4,---+---, L---i---...,1:-:-
1 IN/OUT
FEATURES
• Wide supply voltage range-3V to 15V
• High noise immunity-0.45 V00 typ
• Wide range of digital and analog switching-±7.5 VPEAK
• "ON" resistance for 15V operation-BOO typ 8 IN/OUT
~--+--
• Matched "ON" resistance over 15V signal input-L'>RoN =50 typ

• "ON" resistance flat over peak-to-peak signal range
• High "ON"/"OFF" output voltage ratio-65 dB typ
• High degree of linearity-<0.4% distortion typ TRUTH TABLES
• Extremely low "OFF" switch leakage-0.1 nA typ
• Extremely high control input impedance-10120 typ
• Low crosstalk between switches- - 50 dB typ CONTROL SWITCH
• Frequency response. switch "ON" -40 MHz typ 0 OFF
1 ON
APPLICATIONS
• Analog signal switching/multiplexing VcONTROL V1N TO VouT RESISTANCE
Signal gating
Squelch control Vss > 1 Q9 ohms typical
Chopper Yoo 3 x lOZ ohms typical
Modulator/Demodulator
Commutating switch
• Digital signal switching/multiplexing LOGIC DIAGRAM
• CMOS logic implementation 114 OF 4066
• ·Analog-to-digital/digital-to-analog conversion
• Digital control of frequency. impedance. phase. and analog-signal gain
ABSOLUTE MAXIMUM RATINGS OUT/IN
Supply Voltage .. . .... . ...... .... ..... . . .. .. .. . . .. .. . . . . .. . -0.5V to +18V

Input Voltage ... .. ....... .. . ... . . .. . . . . . .... . . . ..... . ... -0.5 to V00 + 0.5V
Package Dissipation . ........... .. .... .. ... . .. .. .................. 500 mW
Operating Temperature Range . ... . . . ..... . . . ...... . . .. . . . .. . -40 to +85°C LOGIC DIAGRAM RESTRICTIONS
Storage Temperature Range ...... . .. . . . ... .. . .. ....... .. .... -65 to + 150°C Yss< YtN <Voo
Lead Temperature (Soldering, 10 seconds) . . ... . ...... . . . ........... . . 300°C Vss<Your<Voo
o YouT
Input Voltage
0 Yc = Yeo for bandwidth test.

Yeo Yss Vc "" Yss for feedthrough test.
Bandwidth and Feedthrough Attenuation
Propagation Delay Time, Control to Output
26
DIGITAL (CMOS)
MELODY GENERATOR UM3482

276-1797
PIN CONNECTION
GENERAL DESCRIPTION
The UM3482A is a mask-ROM-programmed multi-instrument melody gener-
ator, implemented in the CMOS technology. It is designed to play the melody
according to the previously programmed information and· is programmed with
12 songs with 3 instrument sounds, the piano, the organ and the mandolin.
The UM3482A will play the following songs: AMERICAN PATROL, RAB-
BITS, OH, MY DARLING CLEMENTINE, BUTTERFLY, LONDON BRIDGE
IS FALLING DOWN, ROW, ROW, ROW YOUR BOAT, ARE YOU SLEEPING,
HAPPY BIRTHDAY, JOY SYMPHONY , HOME SWEET HOME,
WIEGENLIED, and MELODY ON PURPLE BAMBOO.
The device also includes a pre-amplifier which provides simple interface to
the driver circuit.
FEATURES APPLICATIONS
• Powered by a 1.5V battery • Toys
• Low stand-by current • Doorbells
• 512 notes memory, up to 16 songs • Music Boxes
• Play all the songs repeatedly or auto stop • Melody/Clock Timers
• Play one song only, repeatedly or auto stop • Telephones
• Every song starts from the first note
• Any song can be present
• 3 timbres-piano, organ and mandolin
• 5 tempos available through mask setting
• On chip envelope modulator and pre-amplifier

DC supply voltage ... ..... ..... . .. .. .. .. .. ...... . . . .. ...... - 0.3 V to 5.0 V
Input/output voltage . . . .......... .. .. ..... . ...... Vss -0.3 V to Voo + 0.3 V
Operating ambient temperature . . ..... . .... . . ....... .. . . . .. . - 10°C to 60°C
Storage temperature . . .. .. . .. ..... .. .. . .. . ........ ........ - 55°C to 125°C
BLOCK DIAGRAM TYPICAL APPLICATION

General application
OSC1 OSC2 OSC3 ENV
~~~------~--=-----------------------------,
sw,
MT1
----, I UM3482A
I
I
I
I
I
OP1
OP2
I
I
I
---, I
I
I
I r - - ---...1
I I
CEXS LP SL I I
I I
I I
I I
I I
I I
I I
I I
I I
I I
I
I
I
I
I
L______ _________ _______ _______ ____J
27
DIGITAL (CMOS)
UM3482
276-1797
Chime function application
16 12 11 10 9
v., MT1 OP2 OP1 MTO
UM3482A PIN
TSP CE LP SL liS NC NAMES FUNCTION
1 2 3 4 5 6
1(TSP) Output flag of melody
i SW1
R,
180 K
auto stop
In normal operating
this pin should be
open
Melody door bell 2(CE) Chip enable if
connected to Voo
Chip disable if
connected to Vss
3(LP) The melody plays only
one song if this pin
connected to Voo
16
v., The melody plays all
songs if this pin
TSP CE LP NC ENV v,
1 2 3 6 7 8 connected to Vss
4(SL) A positive going edge
c, R, applied to this pin the
4.7uf 180K
v,. melody will change to
the next song
5(AS) The melody will be
repeated if this pin
Low cost applications connected to Von
The melody will be
v, auto stop if this pin
connected to Vss
6(NC) No connection
C1
47pF 7(ENV) Envelope circuit
12 11 10 terminal
UM3482A
8(Vssl Negative supply
power
9(MTO) Modulated tone signal
output
10(0P1) Pre-amplifier output 1
11(0P2) Pre-amplifier outout 2
12(MT1) Modulated tone signal
input to the pre~
~~~------------_,
SW1
amplifier
13(0SC3)
Pin 13-15 can be
connected as an RC
14 (OSC2) oscillator
External oscillating
signal can be input to
Pin 15
15(0SC1)
16(Vool Positive oower suoolv
28
DIGITAL (MEMORY)
65,536-BIT DYNAMIC RANDOM HYB4164-P2

ACCESS MEMORY (RAM) 276·2506

The HYB4164 is a 65536-word by 1-blt, MOS random access memory circuit
fabricated with new 5-volt only n-channel silicon gate technology, using dou-
ble layer polysilicon. To protect the chip against a-radiation a chip cover is TOP VIEW
used. The HYB4164 uses single transistor dynamic storage cells and dynamic
control circuitry to achieve high speed at very low power dissipation. Multi- NC Vss
plexed address inputs permit the HYB4164 to be packaged in an industry
01 CAS
standard 16-pin dual-in-line package.
System oriented features include single power supply with ±10% tolerance, We DO
on-chip address and data latches which eliminate the need for interface regis-
ters and fully TTL compatible inputs and outputs, including clocks. RAS Ae
In addition to the usual read, write and read-modify-write cycles, the A,

HYB4164 is capable of early and delayed write cycles, RAS-only refresh and
hidden refresh. Common 1/0 capability is given by using "early write" opera-
""
A, A,
tion.
A, As
FEATURES Vee A,
• 65,536 X1 bit organization
• Industry standard 16-pin JEDEC
configuration
• Single +5V ±10% power supply
• Low power dissipation
- 150 mW active (max.) PIN
- 20mW standby (max.)
• 150 ns access time, 280 ns cycle NAMES FUNCTION
• All inputs and outputs TTL com- Ao-A7 Address Inputs
patible
• High over-and undershooting capa- CAS Column Address Strobe
bility on all inputs DI Data In
• Low supply current transients
NC No Connection
• CAS controlled output providing
latched or unlatched data DO Data Out
• Common 1/0 capability using "ear- RAS Row Address Strobe
ly write" operation
• Read-Modify-Write, RAS-only re- WE Write Enable
fresh, hidden refresh Vee Power Supply (+5V)
• 256 refresh cycles with 4 ms long
refresh period Vss Ground (OV)
• Page Mode Read and Write
Voltages on any Pin relative to Vss· .......................... -1.0 to +7.0V
Voltage High Level Input (All Inputs) .................. ...... +2.4 to +6.0V
Voltage Low Level Input .. . ....... . ...... . . . .... . .... .. ..... -1.0 to +0.8V
Voltage Output High (lo = -5mA) .......................... +2.4 to +Vee V
Voltage Output Low (Io = +4.2mA) .............. . ....... . .... . .... . .. 0.4V
Short Circuit Output Current ....................................... 50mA
Power Dissipation ....... ....... .. .................................. 1.0W
Operating Temperature Range .................. . .... . ..... . . . . 0 to +70°C
Storage Temperature Range .. . . .. . ... . .................... -65 to +150°C
FUNCTIONAL DESCRIPTIONS
Addressing (A0 - A1)
For selecting one of the 65536 memory cells, a total of 16 address bits are
required. First 8 row-address bits are setup on pins Ao through A7 and latched
onto the row address latches by the Row Address Strobe (RAS). Then the 8
column-address bits are set-up on pins A0 through A 7 and latched onto the col-
umn address latches by the Column Address Strobe (CAS). All input addresses
must be stable on or shortly after the falling edge ofRAS and CAS respectively.
CAS is internally gated by RAS to permit triggering of column address latches
as soon as the Row Address Hold Time (tRAHl specification has been satisfied
and the address inputs have been changed from row-address to column-
address.
It should be noted that RAS is similar to a chip enable in that it activates the
sense amplifiers as well as the row decoder. CAS is used as a chip-select acti-
vating the column decoder and the input and output buffers.
29
DIGITAL (MEMORY)
HYB4164 21e-2506
BLOCK DIAGRAM TYPICAL CHARACTERISTICS
iiAs-----l
·-
Current Consumption During Po-r
Up <Vee Rlsetlme 10,..s)
Ao
A,
A,
DUMMY CELLS
32K
MEMORY ARRAY
Vee
t :
:1 VI '
~~~~ [J tjJ
Aa
256 DO
SENSE REFRESH AMPS
A,
As
...
32K
MEMORY ARRAY
I
-·
0 100 200 300 400 500j.LS
A, DUMMY CELLS
Current Consumption During Power

Up <Vee Rlsetlme 100,..s)
FUNCTIONAL DESCRIPTIONS (Cont'd) lcc 1 (AVERAGE) vs. CYCLE RATE

Vcc=S.SV
WRITE CYCLE
mA TA=25°C
Write Enable (WE) 25
The read or write mode is selected with the WE input. A logic high (VIH) on
WE dictates read mode; logic low (V 1d dictates write mode. The data input is
t 0
I
/
2
disabled when the read mode is selected. When WE goes low prior to CAS,
data output (DO) will remain in the high-impedance state for the entire cycle
permitting common I/0 operation. 5
Data Input (DI)

Data is written during a write or read-modify-write cycle. The falling edge of
Cf\5 or WE strobes data into the on-chip data latch. In an early write cycle WE
01 /
is brought low prior to CAS and the data is strobed in by CAS with set-up and 5
hold times referenced to this signal. In a delayed write or read-modify write

cycle, CAS will already be low, thus the data will be strobed in by WE with 0
-·
4 MHz
set-up and hold times referenced to this signal.
Power ON
lcc 3 (AVERAGE) vs. CYCLE RATE
An initial pause of 200 f.LS is required after power-up followed by a minimum Vcc=S.SV
of eight (8) initialization cycles (any combination of cycles containing a RAS RiS ONLY REFRESH CYCLE
mATA=25°C
clock such as RAS-only refresh) prior to normal operation. The current 25
requirement of the HYB4164 during power on is, however, dependent upon
the input levels 'RAS, CAS and the rise time of Vee. as shown in the (Current
Consumption During Power Up) diagram. t 2
0
Data Output (DO) 5

I
The output buffer is three-state TTL compatible with a fan-out of two stand-
ard TTL loads. Data-out is the same polarity as data-in. The output is in a high-
impedance state until CAS is brought low. In a read cycle, or read-write cycle, 0
/
the output is valid after tRAc from the transition of RAS when tRco (min) is sat-
isfied, or after tcAc from the transition of CAS when the transition occurs after 5
/
tRco (max.). CAS going high returns the output to a high-impedance state. In an
early write cycle the output is always in the high-impedance state. In a delayed
0
-·
write or read-modify-write cycle, the output will follow the sequence for the 4 MHz
read cycle.
30
DIGITAL (MEMORY)
HYB4164 276-2506
FUNCTIONAL DESCRIPTIONS (Cont'd)

Hidden Refresh TYPICAL CHARACTERISTICS
RAS only refresh cycle may take place while maintaining valid output data.
This feature is referred to as Hidden Refresh. Hidden Refresh is performed by
(Cont'd)
holding CAS at VIL from a previous memory read cycle.
Icc (AVERAGE} vs. TEMPERATURE (TYP.)
Page Mode Vcc=S.SV, tRc= 280 nsec
lcc1 WRITE CYCLE
Page Mode operations allows a faster data transfer rate. This is achieved by rnA lcc3 m ONLY REFRESH CYCLE
25
maintaining the row address while strobing successive column addresses onto
the chip. The time required to set-up and strobe sequential row addresses for ,de 1
the same page is eliminated.
Refresh Cycle IC~3
5
A refresh operation must be performed at least every four milli-seconds to
retain data. Since the output buffer is in the high-impedance state unless CAS
is applied, the RAS only refresh sequence avoids any output signal during 0
refresh. Strobing each of the 256 row addresses (Ao through A 7 ) with RAS
causes all bits in each row to be refreshed. CAS can remain high (inactive) for
this refresh sequence to conserve power. 5
0
-40 -20 0 20 40 60 80 100°C
-r
lcc2 STANDBY CURRENT vs TEMPERATURE (TYP.)

Ycc=S.SV
mA
4
lcc2
ADDRESSES VIH
t '
r--... 1"'--.
vll
-....I'
2 1'-....
1
DO
Read Cycle 0
-40 -20 0 20 40 60 80 100°C
-T
iUS ACCESS TIME CAS ACCESS TIME

vs. SUPPLY VOLTAGE vs. SUPPLY VOLTAGE
T"=25°C TA=25°C
3 1.3
lcAC'
v," lcAC
ADDRESSES
r 2
1. 1
1\
2
1.1
\
1.0
~ 1.0
1\
~ I'.. 1\
.9 0. 9
Dl
1'\
0. 8 o.8
3.5 4.5 5.5 6V 3.5 5.5 6V
DO VoH - - - - - - - - - O P E N - - - - - - - - - - -
-----. vee
Write Cycle (Early Write) Typical Access Time Curves
31
DIGITAL (MEMORY)
HYB4164 276-2so6
TYPICAL CHARACTERISTICS (Cont'd)
v,"
ADDRESSES Read-Write/Read-Modify-Write Cycle
v,"
W.
v"
VoH
DO
VoL
v,H
Dl
v"
RAS
v,"----~
-IRAS
----J~f.--------- ... 3 "RAS-ONLY" REFRESH CYCLE
NOTE CAS= V1H; WE= DON'T CARE
VoH
DO --------OPEN---------
I - - - - - READ CYCLE - -+ - -RAS ONLY CYCLE -1

v,"
RAS
v"
v,H
CAS
v,L.
v,"
ADDRESSES Hidden Refresh
DO
32
DIGITAL (MEMORY)
HYB4164 276-2so6
Page Mode Read Cycle
Page Mode Write Cycle
33
DIGITAL (MEMORY)
HYB4164 2re-2506
[)o-Ro
A3 R1 R255 R255
C255 co
A7
EXTERNAL INTERNAL
ROW [)o-R2 ROW
ADDRESS ADDRESS
AS R3 (PIN 5) AO RAs' (PIN 4)
A4 R4 (PIN 6) A2
DATA STORED=Di
WE (PIN3)
A2 RS (PIN 7)A1 Dl (PIN 2)
A1 R6 (PIN 8) Vee
AD R7 (PIN 9) A7 Vss (PIN 16)
(PIN 10) AS ffi(PIN15)
DATA STORED=DI
2D--::
A6 (PIN 11)A4 00 (PIN 14)
(PIN 12) A3 A6 (PIN 13)
A3------------------------------~~----------
A7------------------------------------------ C2 INTERNAL
EXTERNAL AS----------------------------------------------- C3 , COLUMN
;g~~~S~ A4----------------------------------------------- C4 ADDRESS RO RO
C255 co
A2--------------------------------------------- cs
A1------------------------------------------ C6
AO--------------------------------------------- C7 Internal Topology
INTERNAL DATA POLARITY
DATA STORED= Dl EllAo (ROW)
NOTE: The logic symbol ~exclusive nor~ Is used
solely to Indicate the Jogic function.
Address Decoder Scrambling
Topology Description
The evaluation and incoming testing of RAMs normally requires a description
of the internal topology of the device in order to check for "worst case"
pattern.
34
DIGITAL (MEMORY)
64KUV EPROM MSM 2764RS

276-1251
GENERAL DESCRIPTION PIN CONNECTIONS

The MSM2764RS is a 8192W X 8 bit ultraviolet erasable and electrically
programmable read-only memory. Users can freely prepare the memory con-
tent, which can be easily changed, so the MSM2764RS is ideal for micropro- v.,
cessor programs. ~
The MSM2764RS is manufactured using the N channel double silicon gate A12
MOS technology. NC
A7
A6 A6
FEATURES
• + 5V single power supply Ag
..
As
• 8192 words X 8 bits configuration
A11
• Access time: MAX 250ns
• Powei; consumption: A3 CiE
MAX 525 mW (during operation)
MAX 184 mW (during stand-by) A10
• Perfect static operation

A1 llr
• INPUT/OUTPUT TTL level (three state output)
Ao Og
ABSOLUTE MAXIMUM Rl\TINGS

Program Voltage Vpp .. ....... . . .... _.. .... ... . ........ .. .. -0.6 V to 23 V ""
01 01
All input/output voltages Vin• Vaut ... . .. . .. . ....... . . ........ . . - 0.6 V to 7V
Power Pn . . ......... . ... . .. .. . . . . . ..... . . ..... .......... . . . .. . . .... 1.5 W 04
Operating Temperature T A •• •• • _ •••••••• •• ••• • _ • • ••• •••• •••• • • 0°C to 70°C
03
Storage Temperature Ts&G .. ...... . ............ . . . ....... _- 55°C to 125°C
BLOCK DIAGRAM Time Chart
....,_____ Vee
..,.__ Vpp
. . . _ _ . GND
Ao A1 - - - - - - - - - A 12
35
DIGITAL (MEMORY)
TMS4256 256 K DYNAMIC RAM

276-1252
GENERAL DESCRIPTION
The 4256 is a high-speed, 262,144-bit dynamic random-access memory, PIN CONNECTION
organized as 262,144 words of one bit each. It employs state-of-the-art SMOS
(scaled MOS) N-channel double-level polysilicon/polycide gate technology for
very high performance combined with low cost and improved reliability.
This device features maximum RAS access times of 150ns. Typical power
dissipation is as low as 275 mW operating and 12.5 mW standby.
New SMOS technology permits operation from a single 5-V supply, reducing
system power supply and decoupling requirements, and easing board layout.
Inn peaks are 125 rnA typical, and - 1-V input voltage undershoot can be toler-
ated, minimizing system noise considerations.
All inputs and outputs, including clocks, are compatible with Series 74 TTL.
All address and data-in lines are latched on chip to simplify system design.
Data out is unlatched to allow greater system flexibility.
FEATURES
• 262,144 X 1 organization
• Single 5 V supply
TRUTH TABLE
• Access time row address 150ns (Max.)
PIN
• Access time column address 75ns (Max.)
NAMES FUNCTION
• Read or write cycle 260ns (Min.)
• Long refresh period 4ms (Max.) AO-A8 Address Inputs
• Low refresh overhead time CAS Column-Address
• On-chip substitute bias generator Strobe
• All inputs, outputs, and clocks fully TTL compatible
• . RAS-only refresh mode D Data In
• Hidden refresh mode _Q Data Out
• CAS-before-RAS refresh mode RAS Row-Address Strobe
Von 5-V Supply
ABSOLUTE MAXIMUM RATINGS Vss Ground
Voltage range for any pin including Von supply (see Note 1) .. . . . . - 1 V to 7 V w Write Enable
Short circuit output current ... . .. . . . ..... . . .. . . ..... . .. . .. . . . .... . . 50 rnA
Power dissipation . . . .. .. . ... ... . . ... . ..... . .... . . . . ... . .. . . . . . .. . . . . 1 W
Operating free-air temperature range ... ... . . . . ... . .. . . ... .. . .. . 0°C to 70°C
Storage temperature range ... . ......... . .. . .. . . . ..... . .... - 65°C to 150°C
NOTES: 1. All voltage values are with respect to V55•
BLOCK DIAGRAM
! !
~~l~J~~~-~-~~=T-IM=ING~·=·~·J~NTR-
OL -~~~
J2K A RRAY
R
O
W
DECODE 32K ARRAY
~--~ AO~~~SS ,__ 256 SENSE AMPS 256 SENSE AMP S -

~BUFFE R S_ '
Ao--...W-W-llF~~L~--"-'---jlr?I--'-'K_A_R_RA-v_c. JoL :-~-:-~-:o-LoE_"_•_•_R _.'_--II= •:iit t::RR:::-

:: =_-:::=_-:::j-t+lt+t-tt
_l.-:::=
_-:::=_-+l:: :e~,'.~,r:1 t=J "'""~' "'"" ~'"~' -.._TT-10-,Nr-l~
" --+1-_._--~
A6 --+1----~
AI ---+-----~
256 SEN SE AMP S
32K ARRAY
ROW
DECODE
256 SENSE AMPS
32 K AR RAY
1"1
rl-C_O.!:_~M_N_J
As ------+--~i_~R~o~
w~}-'--------------------~
36
DIGITAL (MEMORY)
OPERATION TMS 4256 21s-12s2

address (AO through A8)
Eighteen address bits are required to decode 1 of 262,144 storage cell loca-
tions. Nine row-address bits are set up on pins AO through AS and latched
onto the chip by the row-address strobe (RAS). Then the nine column-address
bits are set up on pins AO through AS and latched onto the chip by the
column-address strobe (CAS). All addresses must be stable on or before the fall-
ing edges of RAS and CAS. RAS is similar to a chip enable in that it activates
the sense amplifiers as well as the row decoder. CAS is used as a chip select
activating the column decoder and the input and output buffers.
write enable (W)

The read or write mode is selected through the write-enable (W) input. A
logic high on the W input selects the read mode and a logic low selects the
write mode. The write-enable terminal can be driven from standard TTL cir-
cuits without a pull-up resistor. The data input is disabled when the read mode
is selected. When W goes low prior to CAS, data out will remain in the high-
impedance state for the entire cycle permitting common I/0 operation.
data in (D)
Data is written during a write or read-modify-write cycle. Depending on the
mode of operation, the falling edge of CAS or W strobes data into the on-chip
data latch. This latch can be driven from standard TTL circuits without a pull-
up resistor. In an early write cycle, W is brought low prior to CAS and the data
is strobed in by CAS with setup and hold times referenced to this signal. In a
delayed-write or read-modify-write cycle, CAS will already be low, thus the
data will be strobed in by W with setup and hold times referenced to this
signal.
data out (Q)

The three-state output buffer provides direct TTL compatibility (no pull-up
resistor required) with a fan out of two Seri~s 74 TTL loads. Data out is the
same polarity as data in. The output is in the high-impedance (floating) state
until CAS is brought low. In a read cycle the output goes active after the access
time interval talC) that begins with the negative transition of CAS as long as ta!Rl
is satisfied. The output becomes valid after the access time has elapsed and
remains valid while CAS is low; CAS going high returns it to a high-impedance
state. In a read-modify-write cycle, the output will follow the sequence for the
read cycle.
refresh
A refresh operation must be performed at least once every four milliseconds
to retain data. This can be achieved by strobing each of the 256 rows (AO-A7).
A normal read or write cycle will refresh all bits in each row that is selected. A
RAS-only operation can be used by holding CAS at the high (inactive) level,
thus conserving power as the output buffer remains in the high-impedance
state.
CAS-before-RAS refresh
The CAS-before-RAS refresh is utilized by bringing CAS low earlier than
RAS (see parameter tcRL) and holding it low after RAS falls (see parameter
tcLRd· For successive CAS-before-RAS refresh cycles, CAS can remain low
while cycling RAS. The external address is ignored and the refresh address is
generated internally.
hidden refresh
Hidden refresh may be performed while maintaining valid data at the output
pin. This is accomplished by holding CAS at V1L after a read operation and
cycling RAS after a specified precharge period, similar to a "RAS-only"
refresh cycle. The external address is also ignored during the hidden refresh
cycles.
page mode
Page-mode operation allows effectively faster memory access by keeping the
same row address and strobing random column addresses onto the chip. Thus,
the time required to setup and strobe sequential row addresses for the same
page is eliminated. The maximum number of columns that can be addressed is
determined by tw(RL)• the maximum RAS low pulse duration. ·
power-up
To achieve proper device operation, an initial pause of 200 /J-S is required
after power up followed by a minimum of eight initialization cycles.
37
DIGITAL (MEMORY)
TMS -4256 21s-12s2
RAS-only refresh cycle timing
~ r--VIH
\_____/ VIL
\ _ VIH
VIL
AD-A7
0----------------------------------------H•z-------------------------------------------VOH
VOL
hidden refresh cycle timing
VIH
VIL
VIH
VIL
VIH
VIL
'h(RHrd)
VIH
VIL
VOH
DATA
VOL
VOH
Q --------------- Hl-z-------------------..,VOL
38
DIGITAL (TTL)
QUAD TWO-INPUT NAND GATE 7400

276-1801

This device employs TTL logic to achieve high speed at moderate power dis-
TOP VIEW
sipiation. It provides the basic functions used in the implementation of digital 84 A4 Y4 83 A3 Y3
integrated circuit systems.
For best noise immunity and switching speed, unused inputs should not be left
floating, but should be held between 2.4 V and the absolute maximum input
voltage.
Two possible ways at handling unused inputs are:
(1) Connect unused inputs to Vee· For all multi-emitter conventional TTL inputs,
A 1 to 10K ohm current limiting series resistor is recommended, to protect
against Vee transients that exceed 5.5 V.
(2) Connect the unused input to the output of an unused gate that is forced high.

Supply Voltage Vee . . . . .. . . .... .... ............ . . .... ...... . . . 5.25 V
Input High Voltage . . . ..... ..... ... . . . . .. ... . ..... . ....... ...... 2.0 V
Input Low Voltage ..... .. . .. .. . . . . ..... . ... . . .. .. . .... . .. . ..... 0.8 V
InputClampDiodeVoltage (Vee = 5.0V.IrN = -12mA) . . ... ... ... . - 1.5V
InputHighCUrrent(Vee =Max., VrN = 2.4 V) ... . ... ... ........... . 40!-IA TRUTH TABLE
Input Low Current (Vee = Max., VIN = 0.4 V) . ... .. . .. ...... .. . . - 1.6 rnA
Operating Temperature . .... . ......... .. ... .... ... ... . .. . . . 0 to + 70°C I Y=AB I
Vee Vee Vee
A B OUT A B OUT
OUT l l H OUT
l l l
OUT
H H l H l
H l H H l l
H H l H H H
Control Gate Inverter AND Gate
v.. 7400
Vee
1/• 7400
Vee
Vee
A
A
B
OUT OUT OUT
A B OUT 0 OUT
v.. 7400 l l OUT 'I• 7400 l l

l
l H H X X H H H l H
H l H H H X X H H l
H H H H H H H H H H
OR Gate AND-OR Gate NOR Gate
Vee
v. 7400
A
A B c 0 OUT A B OUT A B OUT

l X X X H l l l l l H
X l X X H l H H l H l
X X l X H H l H H l l
X X X l H H H l H H H
H H H H l
4-lnput NAND Gate Exclusive-OR Gate Exclusive-NOR Gate
39
DIGITAL (TTL)
7404
276-1802
HEX INVERTER
sipatiorr. This hex in:verter provides the basic functions used in the implementa-
tion of digita'l integrated circuit systems. TOP VIEW
For b~st noise immunity and switching speed, unused inputs should not be left AI YS AS Y5 A4 Y4
floating, but should be held between 2.4 V and the absolute maximum input
voltage.
Two possible ways of handling unused inputs are:
(1] Connect unused inputs to Vee· For all multi-emitter t:onventional TTL inputs,
A 1 to 10K ohm !':ur.rent limiting series resistor is recommended, to protect
against Vee trai)slents that exceed 5.5 V.
(2] Connect the unused input to the output of an unused gate that is forced high.

/
SupplyVoltageVee ........................................... 5.25V
Input High Voltage ............................................. 2.0 V
lnput Low Voltage ............................................. 0.8 V
InputClampDiodeVoltage[Vee = 5.0V,IIN = -12mA] . ... ........ -1.5V
InputHighCurrent[Vee =Max., VrN = 2.4 V] ...................... 40J,lA.
Input Low Current (Vee = Max., VIN = 0.4 V] ................... - 1.6 rnA
Operating Temperature ................ ........ ...... . . .... o to + 70°C
TRUTH TABLE
I Y= A I
Vee
Vee
270!.1
4.7K
IN 8!1
SPEAKER
4.7K
Output follows switch position. Allows one signal to control two or more Inputs.
Output tone is 4kHz.
Bouncefree Switch Universal Expander Audio Oscillator
This circuit steers the Input bit to the output selected by the address.
DATA ADDRESS OUT A OUT 8

l l l H
H l H H
l H H l
H H H H
1-of-2 Demultiplexer
40
DIGITAL (TTL)
QUAD TWO-INPUT AND GATE 7408

276-1822

sipation. These gates provide the basic functions used in the implementation of
digital integrated circuit systems.
For best noise immunity and switching speed, unused inputs should not be left l TOP VI&!W
floating, but should be held between 2.4 V and the absolute maximum input 84 A4 Y4 83 A3 Y3
voltage.
Two possible ways at handling unused inputs are:
(1) Connect unused inputs to Vee. For all multi-emitter conventional TTL inputs,
a 1 to lOK ohm current limiting series resistor is recommended, to protect
against Vee transients that exoeed 5.5 V.
(2) Connect the unused input to the output of an unused gate that is forced high.

Supply Voltage Vee ..... . .. . ....... . ........ . .. . .... . . .. . ..... 5.25 V
Input High Voltage .. .... . ........ . .... . ..... . ... . .. ............ 2.0 V
Input Low Voltage ... . ....... . .... . .. . .......... .. ... . . . . .. . ... 0.8 V
InputClampDiodeVoltage(Vee = 5.0V,IIN = -12mA) . ........ . .. -1.5V
InputHighCurrent(Vee =Max., VrN = 2.4 V) . .. .. . . . ....... . ...... 40~
InputLowCurrent(Vee =Max., VIN = 0.4 V) . .... . ......... . ... -1.6mA
Operating Temperature ........ ... .................... .. ... 0 to + 70°C
TRUTH TABLE
TYPICAL APPLICATIONS I Y=AB I
Vee
IN:::: OUT Vee

OUT Use for Interfacing without Vee
changing logic states.
A A
AND Gate Buffer OUT
c c
Vee Vee
A 8 OUT
A
OUT L L H A c
L H H A C D OUT
H L H
H H L H H H
X X L
NAND Gate AND-OR-Invert Gate 4-lnput AND Gate
Vee Vee
A
8
Vee
OUT
A c
A 8 OUT 0
L L H
OUT L H L
IN E OUT
H L L
H H L L L L
L H L
H L L A C 0 OUT
H H H
H H H l
X X X H
E - ENABLE
NOR Gate Digital Transmission Gate 4-lnput NAND Gate
41
DIGITAL (TTL)
7447 BCD TO SEVEN-SEGMENT DECODER/DRIVER

276-1805
GENERAL DESCRIPTION
This versatile binary-coded-decimal 7-segment display driver fulfills a wide
variety of requirements for most a ctive high [common cathode) and active low
[common a node) light emitting diodes [LED) or lamp displays. It fully decodes a
PIN CONNECTION
4-bit BCD input into a number from 0 through 9 in the standard 7-segment
TOP VIEW
display format, and BCD numbers above 9 into unique patterns that verify
operation. All circuits operate off of a single 5.0V supply. The output will with- Vee
stand 15 Volts at a maximum leakage current of 250~ . 12 11 10 9
J'"
15 14 13
FEATURES
• Lamp-test input
• Leading trailing zero suppression (RBI and RBO)
• Blanking input that may be used to modulate lamp intensity or inhibit output
• -TTL and DTL compatible
• Input clamping diodes
• Open collector outputs drive indicators directly

8
1 2
C
3
•
LAMP 81/RBO RBI
5
•
~GND
7 I.
Supply Voltage Vee . .. . .. .. . .. . .. ...... .. . ..... .. . ... .. ..... .4.75 .- 5.25 V 'INPUfs' TEST INPUTS
Continuous Voltage at Outputs a-g . ... ... .. . . .. . .. .... .. . .. ...... Max. 15 V
Logic 1 Input Voltage .. . .. .. . .. ... . . .. . . . .. . . . .. . . . . . . . . .. . .. ,. .. . Min. 2 V
Logic 0 Input Voltage .. . .. . .. . . . . .. . ...... . . . ..... .. . . . .. . ..... Max. 0.8 V
Logic 0 Output Voltage BI/RBO . .. ...... . . . . ........ .. . . . .. . . .. . Max. 0.4 V
Logic 1 Output Voltage at BI/RBO . ... .. . . . . ..... . . . .. . . . ....... . Min. 2.4 V
Power . .. . . .. . . .. . . .. . .. .... . . .. . . .... . . . . . . . . ... . ......... . .. . . 320 mW
TRUTH TABLE
DECIMAL INPUTS OUTPUTS
OR BI/ RBOt NOTE
FUNCTION LT RBI D c B A a b c d e f g
0 H H L L L L H L L L L L L H
1 H X L L L H H H L L H H H H
2 H X L L H L H L L H L L H L
3 H X L L H H H L L L L H H L
4 H X L H L L H H L L H H L L
5 H X L H L H H L H L L H L L
6 H X L H H L H H H L L L L L
7 H X L H H H H L L L H H H H
8 H X H L L L H L L L L L L L 1
9 H X H L L H H L L L H H L L
10 H X H L H L H H H H L L H L
11 H X H L H H H H H L L H H L
12 H X H H L L H H L H H H L L
13 H X H H L H H L H H L H L L
14 H X H H H L H H H H L L L L
15 H X H H H H H H H H H H H H
BI X X X X X X L H H H HH H H 2
RBI H L L L L L L H H H HH H H 3
LT L X X X X X LH L L L L L L 4
H = H1gh Level. L = Low Level. X = Irrelevant
Notes: 1. The blanking input (BI) must be open or held at a high logic level when output functions 0 thru 15 are desired.
The ripple-blanking input (RBI) must be open or high , if blanking of a decimal zero is not desired.
2. When a low logic level is applied directly to the blanking input (BI), all segment outputs are H regardless of the
level of any other input.
3. When ripple-blanking input (RBI) and inputs A, B, C, and Dare at a low level with the lamp-test input high, all
segment outputs go H and the ripple-blanking output (RBO) goes to a low level (response condition).
4. When the blanking input/ripple blanking output (BI/RBO) is open or held high and a low is applied to the lamp
test input, all segment outputs are L.
t Bl/RBO is w ire-AND logic serving as blanking input (BI) and/or ripple-blanking output (RBO).
~I -
I I 1_1 I I
I I I I I I_ I_
10 11 12 13 14 15
Numerical Designations and Resultant Displays
42
DIGITAL (TTL)
7447 276-1805
INPUT /OUTPUT EQUIVALENTS

Vee
2.4K BK
NOMINAL NOMINAL
811R81-------'
Each Input Except BIIRBO BIIRBO Input Typical of Outputs a Thru g
Vee
Manually Switched Display
Vee Vee Vee
t5 f,. R3
13
R1~---4--, D D 330!1
1Mil
.f14 11
• 12
R4
330!1
R5
c c
• 2 11 330!1
R2
555
----. 7490 7447
10
R6
330!1
1K
---. 8
9 1
8
9
R7
330!1
RB
6 15 330!1
A A
I
12 7 R9
~
r
14 330!1
C1. O.H OOp F
Close 5 1 to start timing cyc le.

""
I' r
Calibrate 555 for 1 pulse (c ount) per second or 1 count per minute by adj usting R1 .
0-9 Second/Minute Timer
43
DIGITAL (TTL)
7490 DIVIDE BY 2 OR 5, BCD COUNTER

276-1808
GENERAL DESCRIPTION
This monolithic BCD counter contains four master-slave flip-flops and addi-
tional gating to provide a divide-by-two counter and a three-stage binary counter
for which the count cycle length is divide-by-five. PIN CONNECTION
This counter has a gated zero reset and gated set-to-nine inputs for use in BCD INPUT
TOP VIEW
nine's complement applications. A Oo

14 8
To use maximum count length, the B input is conner.ted to the QA output. The
input count pulses are applied to input A and the outputs are as described in the
appropriate truth table. A symmetrical divide-by-ten count can be obtained from
the 90 counter by connecting the Q 0 output to the A input and applying the input
count to the B input which gives a divide-by-ten square wave at output QA.
FEATURES
• Low power consumption 1 2 3 6 7
• High count rates ... typically 50MHz INPUT R0(1) R0(2)
8
R9(1) R9(2)
• Choice of counting modes

• Fully TTL and CMOS compatible
ABSOLUTE MAXIMUM RATINGS TRUTH TABLES

Typical Power Dissipation . .. . ..... . . . . . . . ....... . . . .......... 145 mW RESET/COUNT
Count Frequency . . ..... . ................. . . ... . . . . ..... . .. . . 42 MHz RESET INPUTS OUTPUTS
High Level Input Voltage (Min) ........... . ... . . . .. .... . . ... ... ..... 2 V
~0(1) R0(2) R9(1) R9(2) Qo Qc QB QA
Low Level Input Voltage (Max) . . . . . . . ............... ... ........ . . 0.8 V
High Level Input Current .... . ............. . ..... . . .. ..... . . . . . 800 1-1A H H L X L L L L
Low Level Output Current (Max) .. .. .. . .......... . ..... .. .. ... . .. 16 rnA H H X L L L L L
VcctoGround .. . .. . ......... . .. . ...... . ... . .. . .. . ... . -0.5to +7.0V X X H H H L L H
Voltage Applied to Outputs (Output High) ....... . ..... .. .. . -0.5 to + 5.5 V X L X L COUNT
L X L X COUNT
INPUT /OUTPUT EQUIVALENTS L X X L COUNT
X L L X COUNT
--~----Vee BCD COUNT SEQUENCE (See Note A)
10011
NOMINAL COUNT OUTPUTS
Qo Qc QB QA
0 L L L L
1 L L L H
2 L L H L
3 L L H H
4 L H L L
5 L H L H
6 L H H L
7 L H H H
8 H L L L
Each Input Typical of all Outputs 9 H L L H
BI-QUINARY (5-2) (See Note B)
BLOCK DIAGRAM COUNT OUTPUTS
INPUT A QA Qo Qc QB
14 12 9 8 11
0 L L L L
1 ' L L L H
2 L L H L
3 L L H H
J or- lJ 0 J 0 or- 4 L H L L
1-1---' s 5 H L L L
'---< >cK -,<>ex f---< I> CK ---<: i>CK
6 H L L H
a a a 7 H L H L
rL I"
K K K at-<c-
8 H L H H
nl 9
L =Low Level
H H L L
H = High Level
Notes:
(A) Output QA is connected to input B for
BCD count.
6 7 1 2 3 (B) Output Qo is connected to input A for bi-
A9(1) R9(2) INPUT 8 R0(1) R0(2) quinary count.
44
INTERFACE (DRIVER)
QUAD LINE DRIVER MC1488

276-2520

The 1488 is a monolithic quad line driver designed to interface data terminal
equipment with daH communications equipment in conformance with the TOP VIEW
specifications of EIA Standard No. RS-232C.
FEATURES
• Cur rent Limited Output
±10 MA typ
• Power-Off Source Impedance
300 Ohms min
• Simple Slew Rate Control with External Capacitor
• Flexible Operating Supply Range

Supply Voltage (Vccl . .............. . ..... ......... . . . .... . .. . .. .. . . 15 V
(VEE) . . . . . . . ... .. . .. .......... . . .. . . ... . ... . ...... - 15 V
Output Signal Voltage (VO) . . . . . ..... . ... . ... . . .. . ..... . ... . .. .. ... ±15 V
Power (PD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Input Current-Low Logic State (V1L = 0) (See Fig. 8) . . .. ...... .. .... . 1.6 rnA
Input Current-High Logic State (VIH = 5.0V) (See Fig. 8) ... . .. ... . .. .. 10 J.LA
Output Resistance (Vee = VEE= 0/Vol = ±2.0V
(See Fig. 11) . . .......... .. . . . . .... . . . . . .. ...... . .. . ... . ... .... . ... 3000
Operating Temperature Range (TA) • ... . . . .... . . .. . ... . ... . o•c To+ 75°C
Storage Temperature Range (Tstg) . . ... . . . . .. .... . ... .. . -65°C To +175°C
INTERNAL CIRCUIT
Vee 1 4 0 - - - - - T - - - - - - - - , - - - r - - - - ,
(% of Circuit Shown)
PINS 4, 9, 12 OR 2 8.2K
INPUT o---f4---f
INPUTo---f+-4
PINS 5, 10, 13
70
OUTPUT
t--~+---t-'\M.---oPINS 6, 8, 11 OR 3
300
3.6K
GNO~~
10K
7K 70
v•• ,o----~--+----~--~-~
§' +12 + 12V

0 +9.0
Vee Ve e ± 12V
1-
~ + 9.0 ::--±--t----4. los+
~ +6.0
Vcc=Yee
- ·•v"" "...0 +6.0
I I r-
~ +3.0 5 +3.0
I I
E9.S
!::; .:--Vee -Vee
r~-
0
- =±6V
0
"'
~
>
~ -3.or- Yo JK -3.0 .
"~ -6.
of- I
0
:z:
-6.0
0 - 9.
I I I """
en -9.0 I I
~ -1 ~0 0.2I I I I
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
~ -12
los
- 55 0 +25 + 75 + 125
Yin• I NPUT VOLTAGE (VOLTS) T, TEMPERATURE (° C)
Figure 1 -Slew Rate vs Capacitance Figure 3-Transfer Characteristics Figure 4-Short-Circuit Output Current
for lsc = 10mA vs Power-Supply Voltage vs Temperature
45
L
INTERFACE (DRIVER)
M C 1488 216-2s2o
·~~k+=+=+1
+20
<i" ~ 4~
.§. +1 :~
+1
3KO LOAD LINE c.- Vee I !-....
~ +8.0 r- t-- ~~ 12 r- 914-+--1-+-IP'-...t-r-....-t-1
ffi !E_ 10 1- ..__j.(3;_.v3<:;....._+---t-+,_H
~ +4.0
a:
::0 0 \. 1-"" ~~ S.O r--- 6 3K
~ -~ £l. c(
'":; s.o 1-
8 31(
1 '23\M.·-+---t-+-H
1-!1~
e - 4. 0 1.9V los
._: g: t-
!00~
-8. 4.0 ,AA
-~ ~vo
~ ·~ r- ~ I
::0 -1
0~ -1
.9_20 Vcc =Yee=:!:9V..J$,-
-16 -12 -8.0-4.0 0 +4.0 +8.0 + 12 +16 -55 0 +25 +75 +125
V0 , OUTPUT VOLTAGE {VOLTS) T, TEMPERATURE (0 C)
Figure 5-0utput Slew Rate vs Figure 6-0utput Voltage and Figure 7-Maximum Operating
load Capacitance Current-limiting Characteristic:s Temperature vs Power-Supply
Voltage
··~··
·:fr·
Vo
tTHL--
- SO%
-tTLH
trHL and tnH measured 1O"'o to 90%
Switching Response
TEST CIRCUITS
+9V -9V +9V -9V Vee Vee
1 Figure 9- Output Voltage Figure 10- Output Short- Circuit

Current
Figure 8- ·Input Current
Vee
+1.9V
VJ
+0.8V
VEE
Figure 11 - Output Resistance (Power-Off) Figure 12- Power-Supply Currents
46
INTERFACE (DRIVER)
MC1488 21s-2s2o
APPLICATIONS INFORMATION TYPICAL APPLICATIONS

The Electronic Industries Association (EIA) RS232C specification detail the
requirements for the interface between data processing equipment and data INTERCONNECTING
LINE DRIVER CABLE LINE RECEIVER
communications equipment. This standard specifies not only the number and 1488 1489
type of interface leads, but also the voltage levels to be used. The 1488 quad \ I
driver and its companion circuit, the 1489 quad receiver, provide a complete
interface system between DTL or TTL logic levels and the RS232C defined lev- -, ... __
els. The RS232C requirements as applied to drivers are discussed herein.
INTERCONNECTING
The required driver voltages are defined as between 5 and 15-volts in magni- CABLE
tude and are positive for a logic "0" and negative for a logic "1". These volt-
ages are so defined when the drivers are terminated with a 3000 to 7000-ohm MDTl LOGIC INPUT
I :
- - - ' - - - : - MOTL LOGIC INPUT
I
resistor. The 1488 meets this voltage requirement by converting a DTLITTL
logic level into RS232C levels with one stage of inversion.
The RS232C specification further requires that during transitions, the driver
output slew rate must not exceed 30 volts per microsecond. The inherent slew •cco----.o~---,-------..,..- - ----------r-----
rate of the 1488 is much too fast for this requirement. The current limited out- ,.¢
put of the device can be used to control this slew rate by connecting a capaci- 1
tor to each drive output. The required capacitor can be easily determined by r---,:•.---i
using the relationship C = los X il.T/il. V from which Figure 1 is derived. o-~--!'- ..)>-~-o
Accordingly, a 330-pF capacitor on each output will guarantee a worst case i '-· i
slew rate of 30 volts per microsecond. o- ~--:-- ·p-~ -o
The interface driver is also required to withstand an accidental short to any o-;-~-' :
other conductor in an interconnecting cable. The worst possible signal on any o-L_ __. _, :
conductox would be another driver using a plus or minus 15-volt, 500-mA o--l- - .:. _ ,t>--i -o
source. The 1488 is designed to indefinitely withstand such a short to all four : :
outputs in a package as long as the power-supply voltages are greater than 9.0 o-~-~- 'p.. - ~ 0
volts (i.e., Vcc;:,: 9.0 V; VEE s -9.0 V). In some power-supply designs, a loss of o-r--,. -· :
system power causes a low impedance on the power-supply outputs. When ~--;- ;- ---l
this occurs, a low impedance to ground would exist at the power inputs to the 1'i' ~ '
1488 effectively shorting the 300-ohm output resistors to ground. If all four out- ___________! _L _____ _
puts were then shorted to plus or minus 15 volts, the power dissipation in •••
these resistors would be excessive. Therefore, if the system is designed to per-
Figure 2-Power Supply Protection
mit low impedances to ground at the power-supplies of the drivers, a diode
should be placed in each power-supply lead to prevent overheating in this fault to Meet Power-Off Fault Conditions
condition. These two diodes, as shown in Figure 2, could be used to decouple
all the driver packages in a system. (These same diodes will allow the 1488 to + 12V
withstand momentary shorts to the ±25-volt limits specified in the earlier
Stam!ard RS232B.) The addition of the diodes also permits the 1488 to with-
stand faults with power-supplies of less than the 9.0 volts stated above.
The maximum short-circuit current allowable under fault conditions is more 1K
than guaranteed by the previously mentioned 10 rnA output current limiting. 10K
OTHER APPLICATIONS - 12V
The 1488 is an extremely versatile line driver with a myriad of possible appli-
cations. Several features of the drivers enhance this versatility: Figure 14-MDTL/MTTL-to- MOS
Translator
1. Output Current Limiting-this enables the circuit designer to define the
output voltage levels independing of power-supplies and can be accom-
plished by diode clamping of the output pins. Figure 14 shows the 1488 used
as a DTL to MOS translator where the high-level voltage output is clamped
one diode above ground. The resistor divider shown is used to reduce the
output voltage below the 300 mV above ground MOS input level limit:
2. Power-Supply Range- as can be seen from the schematic drawing of the
drivers, the postive and negative driving elements of the device are essen-
tially independent and do not require matching power-supplies. In fact, the
positive supply can vary from a minimum seven volts (required for driving
the negative pulldown section) to the maximum specified 15 volts. The nega-
tive supply can vary from approximately -2.5 volts to the minimum speci-
fied -15 volts. The 1488 will drive the output to within 2 volts of the postive
or negative supplies as long as the current output limits are not exceeded.
The combination of the current-limiting and supply-voltage features allow a
wide combination of possible outputs within the same quad package. Thus if
- 12V + 12V
only a portion of the four drivers are used for driving RS232C lines, the
remainder could be used for DTL to MOS or even DTL or DTL translation.
Figure 15 shows one such combination. Figure 15-Logic Translator
Applications
47
INTERFACE (RECEIVER)
MC1489 QUAD LINE RECEIVER

276-2521

The 1489 monolithic quad line receiver is designed to interface data terminal
equipment with data communications equipment in conformance with TOP VIEW
specificiations of EIA Standard No. RS-232C .
INPUT A - : - + - - - ,
FEATURES RESPONSE
CONTROL A--+---,
• Input Resistance-3 .0 k to 7.0 K ohms
• Input Signal Range-±30 Volts RESPONSE
• Input Threshold Hysteresis Built In OUTPUT A CONTROL D
• Response Control
a) Logic Threshold Shifting
b) Input Noise Filtering
RESPONSE
ABSOLUTE MAXIMUM RATINGS CONTROL 8 5·
Supply Voltage (Vee) . .. ... ..... . . .... .. .. ...... . ........ .. . . ... . ... . 10 V OUTPUT 8
RESPONSE
CONTROL C
Input Voltage Range (VIR) . . . .. ...... . ... . .... . ... . .. . .. . . . . .. .... . ±30 V
Output Load Current (II.) ...... ... . . . . ...... . . . .... ... .. . . .. ....... 20 rnA
Power Dissipation (Po) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W GROUND OUTPUT C
Operating Temperature Range (TA) . . ... ............ . . . . ... 0°C To +75°C

Storage Temperature Range (T,1g) . . . .. . ..... . .. . . . .... . . -65°C To +175°C
INTERNAL CIRCUIT
(% of Circuit Shown) TEST CIRCUITS
14
.----t---...,----ovcc' +5Vdc
RESPONSE RF OK SK 1.6K
CONTROL 2o-----~"""".rv-or-~
INPUT 1 C>-""""olv-~--+--l
3.55K
10K
7
'---+--~>----...__- ·-+---<GROUND
Input Currenl
Vee
Vee
Output Voltage and Input Output Short-Circuit Current Power-Supply Current

Threshold Voltage
48
INTERFACE (RECEIVER)
MC1489 21s-2s21
+5Ydc
I
:i' + 8.0 f-t--+--+--+--t----1,--t-+-+--1 as.ao.o~~~§~~~l~¥1~~

~
e
~~ 4.0 ~T ---.!:~
S + 6.0f-t-+--f---l---f----1f-t-+_..---::::;l,....,
.. Jj··,, ITLH and tTHL

~ + 4.of-t-++-l--t-ll-b¥"+-l
~ +2.of-t-++-l--t----::!~f-+-+-l
~
~
Of-t--+--f---1-~~f-t--+-+--1
-2.0f-t-+--:::?4--+ 11
~ -•.of-b-1"''+-1--+ v-;-
? s 3·0
Rr ---+Rr
5K - 113K
v,h ~vth
~ 2.o+SV -+SV
foi"
~ ~vth
HRr
f-l1K -
1-- r--sv
=
r--v,h _
~ 1.0~~~~~~~~.!L~-·-.--~~-
Eo measured
ITHL tTLH 10%-90%
1.5V 1.SV ! - 6-0bo--'f--+--+--+-+
0 0 ., '
.: -a.of-t-+--+--+-+ ~ f-- -j--VILH VIHL
C1 = 15pF =total parasitic capacitance, - ~o2.L,5--:L20- -...J.15,..._...,1c,o_...,5-:L.o,--...J.o- +-=5'=-.o-+ -':10_+...J.15,...+-'20':--:'+25 -3.0-2.0-1.0 0+1 .0+2.0+3.0
which Includes probe and wiring
capacitances Yin INPUT VOLTAGE (VOLTS) V1 1NPUT VOLTAGE (Vdc)
Switching Response Figure 1-lnput Current Figure 2-lnput Threshold

Voltage Adjustment .
2.4 ,--,--,---,-,--,--,-,.---,-~ 2.0 .------.----,----,---.---,----, 8
\ \
::~t=l=E=t=t~:=E=t=l~
iii
~ 51\
9~u 1.s
fa~ 1.6
~W 1.4f-_--f-t--f---l--1489 VIHL 1-----
0
2:
g
w 4
~10pF \',rf
1\\\
~ ~~ ~:~~
12
- ~Il;j~~i~=:E::E~
\ 100pf '
1:-
1 ,.<~ 3
1--\ .~y500pF
~> ~::~=t=l~EE~~·~v~=:'":l_3_3
146 2
r-- '-..._~
""'
> 0.2~ w
_06·Lo---'-"---'o'-.L_-'-_+..J.60,---"--...J..._+_j120 oo~--'---74.0~~--...,.~.0~~--~12 1
10 100 1000 10,000
T, TEMPERATURE (°C) Vee• POWER SUPPLY VOLTAGE (Vdc) PW, INPUT PULSE WIDTH (ns}
Figure 3-lnput Threshold Voltage Figure 4-lnput Threshold vs Figure 5-Turn-on Threshold vs
vs Temperature Power-Supply Voltage Capacitance from Response
Control Pin to Gnd
APPLICATIONS INFORMATION TYPICAL APPLICATIONS

The Electronic Industries Association (EIA) has released the RS-232C speci-
fication detailing the requirements for the interface between data processing INTERCONNECTING
equipment and data communications equipment. This standard specifies not LINE DRIVER CABLE LINE RECEIVER
only the number and type of interface leads, but also the voltage levels to be 1488 \ 1469
used. The 1488 quad driver and its companion circuit, the 1489 quad receiver,
provide a complete interface system between DTL or TTL logic levels and the
RS-232C defined levels. The RS-232C requirements as applied to receivers are
~->--6-_l-0~::Jo-
discussed here. The required input impedance is defined as between 3000 INTERCONNECTING
ohms and 7000 ohms for input voltages between 3.0 and 25 volts in magnitude; : CAiLE :
and any voltage on the receiver input in an open circuit condition must be less MOTL LOGIC INPUT : ~ MOTL LOGIC INPUT
than· 2.0 volts in magnitude. The 1489 circuits meet these requirements with a I I
maximum open circuit voltage of one VaE·

The receiver shall detect a voltage between -3.0 and -25 volts as a logic "1" +5Vdc
and input between +3.0 and +25 volts as a logic "0". On some interchange
leads, an open circuit or power "OFF" condition (300 ohms or more to ground)
shall be decoded as an "OFF" condition.or logic "1". For this reason, the input r--'
---1 I
hysteresis thresholds of the 1489 circuits are all above ground. Thus an open
or grounded input will cause the same output as a negative of logic "1 ">input.
I MOS
LOGIC
1469
---1
L - ....-'
DTL OR TTL
,--"I
11 1
-Yoo -Yeo
+5Yde -...
+5VJr
Figure 7-Typical Translator

Application-MOS to DTL or TTL
49
LINCMOS (A TO D CONVERTER)
- GENERAL DESCRIPTION
8-BIT ANALOG TO DIGITAL
CONVERTER
The TLC548 8-bit Analog-to-Digital Converter is a complete data acquisition

system on a single chip. It is designed for serial interface with a microproces-
sor, peripheral, or digital logic circuitry through 3-state Data Output, Chip
PIN CONNECTION
REF+- r-vcc
Select, and 1/0 Clock control signals. ANALOG I N - - INPUT/OUTPUT CLOCK
REF - - - D A T A OUT
FEATURES
• Versatile control logic GND- -cs
• An on-chip sample-and-hold circuit that can operate automatically or under
microprocessor control
• A high-speed converter with differential high-impedance reference voltage
inputs that facilitate ratiometric conversion and scaling, while isolating the
conversion circuitry from logic and supply noises. BLOCK DIAGRAM
• The TLC548 provides low-error conversion of ± 0.5 least-significant bit
(LSB) in less than 17 microseconds. REF + ~I'~l-------------1
REF - -"(3,_)--------------1 ANA8l~1~-TO- -
DIGITAL
ABSOLUTE MAXIMUM RATINGS ANALOG (2)
SAMPLE
AND 1-------1 ~so;,~~~l~
Supply Voltage, Vee (See Note 1) ...... ... . .... . . .... . ........ . . . ... . . 6.5 V INPUT HOLD CAPACITORS)
Input Voltage Range (Any Input) . .. . . . ... . .. . . . .. . . . .. -0.3 V to Vee+ 0.3 V
Output Voltage Range .. .. .. . .... . ... . .. . . . .... . . . ... - 0.3 V to Vee+ 0.3 V I
Operating free-air Temperature Range . .... . .... . . . ......... - 40°C to 85°C
NOTES: 1. All voltage values are with respect to network ground terminal with the REF- and GND ter- I INTERNAL
SYSTEM
CLOCK
r IL I
I
CONTROL
t
I
minal pins connected together, unless otherwise noted. LOGIC
cs -::1'~>---------------1 o~~T
1/0 CLOCK m COUNTER
Overview of Operation
The TLC548 is a complete data acquisition system and it includes such func-
tions as an internal System Clock, Sample-and-hold, 8-bit AID converter, Data
register, Control logic, 1/0 Clock, and a Chip Select (CS).
These control inputs and a 3-state data output facilitate serial communica-
tions with a microprocessor or minicomputer. A conversion can be completed
OUTPUT
in a maximum of 17 microseconds, while total access and conversion time is a DATA
REGISTER
maximum of 25 microseconds. ·
The internal System Clock and I/0 Clock are used independently and require
no special speed or phase relationship. This simplifies the hardware and soft-
ware control tasks for the device. Because of this independence and the inter- --~
nal generation of the System Clock, the microprocessor and software need 4!'
'-----', /.,-j 8-T0-1 DATA
only read the previous conversion result and start the conversion with the 1/0 I SELECTOR
AND
(6) DATA
OUTPUT
Clock. The internal System Clock drives the "conversion-crunching" circuitry. DRIVER
When CS is high, the Data Output pin is in a high-impedance condition and

the 1/0 Clock pin is disabled.
This condition allows each of these pins to share a control logic point with
its counterpart pin when additional TLC548 devices are used.
Typical Control Sequence '

The control sequence has been designed to minimize the time and effort
required to initiate conversion and obtain the conversion result.
A typical control sequence consists of the following steps.
1. CS (Chip Select) is brought low.
After a CS transition (from high to low), the internal circuitry of the
TLC548 waits for two rising edges and then one falling edge of the internal
System Clock before recognizing the transition. This delay minimizes
errors caused by noise at the CS input. The most-significant bit (MSB) of
the result of the previous conversion then appears on the Data Output pin.
2. The negative edges of the first four I/0 Clocks shift out the 2nd, 3rd, 4th,
and 5th most-significant bits of the result of the previous conversion.
3. The on-chip sample-and-hold begins sampling the analog input after the
4th falling edge.
This operation basically involves the charging of internal capacitors to the
voltage level of the analog input.
50
Typical Control Sequence (cont.) TLC 548 276-1796

4. Three more clock cycles are applied to the I/0 pin.
The 6th, 7th, and 8th bits of the result of the previous conversion are
shifted out on the negative edges of these clock cycles.
5. The 8th and final clock cycle is applied to the I/0 Clock pin.
The falling edge of this clock cycle completes the analog sampling process
and initiates the hold function.
6. Conversion is performed during the next 36 System Clock cycles.
After the final I/0 Clock cycle, CS must go high or the I/0 Clock must
remain low for at least 36 System Clock cycles to allow for the conversion
function.
The operating sequence is illustrated below.
Operating Sequence
A7 87
- - PREVIOUS CONVERSION DATA A - - - - - CONVERSION DATA 8 - -- -
MSB LSB MSB LSB
(See Note B)
NOTES: A. The conversion cycle is initiated with the trailing edge of the Bth 110 Clock pulse after CS'
goes low. ·
B. The most-significant bit (MSB) is then placed on the DATA OUT pin after CS' is brought low.
The remaining seven bits (A6-AO) are shifted out on the first seven 110 Clock {ailing edges.
C. To minimize errors caused by noise on the CS signal, the internal circuitry waits for two ris-
ing edges and then one falling edge of the Internal System Clock (1.4 p.s at 2 MHz) after a
Chip Select transition before responding to control input signals. Therefore, no attempt
should be made to shift out conversion data until the minimum Chip Select setup time has
elapsed.
Keeping CS Low During Multiple Conversions

CS can be kept low during periods of multiple conversions.
If CS is taken high, it must remain high until the end of the conversion. Oth-
erwise, a valid falling edge of CS will cause a reset condition, aborting the con-
version in process.
Stopping an Ongoing Conversion

An ongoing conversion can be stopped and a new conversion started by per-
forming steps 1 thru 6 listed under typical control sequence before the 36 Sys-
tem Clock cycles occur. Such an action yields the conversion result of the pre-
vious conversion, not the ongoing conversion.
Starting Conversion at a Specific Time

For certain applications such as strobing, it is necessary to start conversion
at a specific point in time. The TLC548 will accommodate these applications.
To trigger a conversion at a specific point in time, control hardware or soft-
ware must manipulate the 8th I/0 clock cycle. The sequence for a conversion
at a desired instant is:
I. The on-chip sample-and-hold operation waits for the falling edge of the 4th
I/0 clock cycle and begins sampling. The TLC548 follows the analog input
but does not hold it yet.
II. When the 8th I/0 clock cycle is high, control hardware or software must
keep it high until the desired instant.
III. At the desired instant, control hardware or software must lower the clock.
The falling edge of the 8th I/0 clock cycle causes the input to be held and
initiates the conversion.
51
LINCMOS (A 1'0 D CONVERTER)
TLC 548 276-1796
Intel8051/52 Serial Port Interface Operating Sequence

The serial data for the conversion result from the TLC548 enters the micro-
~
30pF 19
XTAl1
processor through the RXD pin. By using the inverted TXD shift clock as an
,---:(~M~'
I/0 Clock for the TLC548, previous conversion data can be transferred to the ::c
rrJn 30pF 18 XTAL2
microprocessor.
The serial port's Mode 0 state is used to permit 8-bit transmission and recep- lntel8051152
tion. The TLC548 sends the most-significant bit of the conversion result first; Family
the serial buffer receives this bit as the least-significant bit. The software then
reverses the conversion bits and places them in the proper order.
The timing consists of the following three major phases:
1. After CS goes low, eight I/0 Clock cycles access and sample the new ana-
log input. At the same time, I/0 Clock falling edges bring out the previous
conversion result.
2. Conversion begins when the eighth I/0 Clock goes low. Conversion
requires 36 internal System Clock cycles after the eighth I/0 Clock goes
low. The maximum conversion time is 17 microseconds.
3. Eight falling edges of the I/0 Clock bring out the previous conversion
result.
Interface Control Software
ACALL SR549D ; Access, sample and hold new analog

; signal.
; Delay must occur here to allow the

; AID chip to complete conversion. The
; delay must allow 36 AID chip internal
; System Clock cycles to occur.
; Conversion requires maximum of 17
; microseconds.
ACALL SR549D ; Access, sample and hold new analog

; signal. Bring out previoous conversion
; result.
; Serial port read reverses data
; conversion bits coming to micro-
; processor so that they are in the following
; order: bO(LSB), bl, b2, b3, b4, b5, b6
; b7(MSB). These bits and Carry bit
; (C) are presented in the following
; instruction comments so the reader
; understands the technique used to
; place bits in proper order.
RLCA ; 6543210C 7; b7 is now in Carry

RLCA ; 543210C7 6; b6 is now in Carry
MOV ACC.t,C ; 54321067 6; put b6 into ACC.1
MOVC,ACC.2 ; 54321067 0; put bO into C
RLCA ; 43210670 5; b5 is now in Carry
MOVACC.3,C ; 43215670 5; put b5 into ACC.3
MOVC,ACC.4 ; 43215670 1; put b1 into C
MOVACC.5,C ; 32456701 4; put b4 into ACC.5
MOVC,ACC.6 ; 32456701 2; put b2 into C
MOV ACC.7,C ; 34567012 3; put b3 into ACC.7
RLA ; 45670123 ; prepare for SWAP A
SWAP A ; 01234567 ; bits ordered correctly
; Conversion result is in Accumulator
; Subroutine ACALL
SR549D CLR Pt.6 ; Lower Chip Select
ORL SCON ,#lOH ; Set REN
ANL SCON,#FEH ; Reset R1
JNB SCON.O,RCV ; R1 flag not set; branch
; until reception is complete.
CPL P1.6 ; Raise Chip Select
RET ; Conversion is in SBUF
END
52
The Operating Sequence (cont.) TLC 548 276-1796

This interface is ideal if the Intel microprocessor's serial port does not have
to be used for another purpose. However, if another purpose is required by the
serial port, the microprocessor's serial port may be multiplexed so that both
the TLC548 and the additional purpose may be accommodated.
Access and sample occurs Retrieval of conversion
during this time interval occurs here
Conversion occurs
during this time interval
1/0
CLOCK
~------------------------ 79 ,s --------------------------~
Circuit Timing for Intel 8051/52

Microprocessor Interface
630ns
--H-
~---- 21 ·· --------~
DATA
OUT
TLC548
Z80A Interface
The Z80A interface is an economical solution, offering efficient control soft-
ware and communications with the TLC548.
Required Software
A simple program segment that reads in a previous conversion result and
starts a conversion is shown below. Placing this program segment in a loop
makes it possible to initiate a conversion and read previous conversion results
in 111 microseconds.
LD C,08H Load bit counter

LD B,OOH Initialize result register
OUT (CSLOW) ,A Bring Chip Select low
LOOP RLC B Rotate result register left
IN A ,(BIT) Read in a bit & shift next
AND OlH Mask off bit 0
ORB Or new bit with result
LDB,A Store in result register
DECC Decrement bit counter
JP NZ,LOOP Get another bit if not zero
OUT (CSHIGH),A Bring Chip Select high
The Operating Sequence

Latching in a low from address bit AO brings Chip Select low. Execution of
an IN instruction causes RD and IORQ to become active, generating one I/0
Clock pulse. A data bit is read in just before the falling edge of the I/0 Clock.
The·falling edge shifts out the next data bit.
Sampling of analog input begins at the falling edge of the 4th I/0 Clock and
continues until the falling edge of the 8th I/0 Clock. At that time, conversion
begins; conversion requires 17 microseconds.
CS is brought high after the 8th I/0 Clock to disable all inputs and outputs so
that conversion may proceed undisturbed.
53
LINCMOS (TIMER)
TLC555 TIMER
276-1718

The TLC555 is a monolithic timing circuit fabricated using the Lin CMOS™
process. Due to its high-impedance inputs (typically 10120), it is capable of pro- TOP VIEW
ducing accurate time delays and oscillations while using less expensive,
GND
smaller timing capacitors. The TLC555 achieves both monostable (using one
resistor and one capacitor) and astable (using two resistors and one capacitor) TRIG
operation. In addition, 50% duty cycle astable operation is possible using only
a single resistor and one capacitor. The Lin CMOS"' process allows the OUT
TLC555 to operate at frequencies up to 2 MHz and be fully compatible with RESET

CMOS, TTL, and MOS logic. It also provides very low power consumption
(typically 1 m W at V00 = 5V) over a wide range of supply voltages ranging
from 2 volts to 18 volts.
Threshold and trigger levels are normally two-thirds and one-third, respec-
tively of VDD· These levels can be altered by use of the control voltage terminal.
When the trigger input falls below trigger level, the flip-flop is set and the out-
put goes high. If the trigger input is above the trigger level and the threshold
input is above the threshold level, the flip-flop is reset and the output is low.
The reset input can override all other inputs and can be used to initiate a new
timing cycle. When the reset input goes low, the flip-flop is reset and the out-
put goes low. Whenever the output is low, a low impedance path is provided
between the discharge terminal and ground. TYPICAL APPLICATION
While the complementary CMOS OUTPUT is capable of sinking over 100
rnA and sourcing over 10 rnA, the TLC555 exhibits greatly reduced supply cur-
rent spikes during output transitions. Yoo
FEATURES 0.1p.F:b
• Very low power consumption (1 mW typical at V00 = 5 V) "• OPEN I

• Capable of very high-speed operation (2 mHz in a stable operation) (5)1 ., (8)
• Complementary CMOS output capable of swinging rail to rail CONT Yoo R,

• High output-current capability (sink 100 rnA typical) (soucre 10 rnA typical) ~ RESET
• Output fully CMOS, TTL, and MOS-compatible (7)
• Low supply current reduces spikes during output transitions DISCH
(3)
OUT OUTPUT
• High impedance input 10120 typical) (8)
"• THRES
• Single supply operation from 2 to 18 volts
~
Supply Voltage (V 00) (See Note 1) .................................... 18 V
Input Voltage Range (Any Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . -03 V To 18 V
c,
l
TRIG
GNO
(1i I''
Power Dissipation (mW) ........ . . ........ . .... . ................. 600mW Circuit for Astable Operation
Operating Temperature Range ................. . .. . ..... .. ... o•c To 70°C
Storage Temperature Range .................. . .......... -65°C To 150°C
NOTES: 1. All voltage values are with respect to network ground terminal.
BLOCK DIAGRAM
Vee RESET
THRESHOLD
OUTPUT
TRIGGER
DISCHARGE
GNO Reset can override Trigger, which

can override Threshold.
54
LINEAR (AUDIO)
8 WATT AUDIO POWER AMPLIFIER 383

276-703

The 383 is a cost effective, high power amplifier suited for automotive ap-
plications. High current capability (3.5A) enables the device to drive low im-
pedance loads with low distortion. The 383 is current limited and thermally pro-
[?I I
tected. The 383 comes in a 5-pin T0-220 package. SSUPPLYVOLTAGE
4 OUTPUT
FEATURES : 3GROUND
21NVERTING INPUT
• High peak current capability (3.5A) • Low distortion 1 NON·INVERTING INPUT
• Large output voltage swing • High input impedance
• Externally programmable gain • No turn-on transients
• Wide supply voltage range (5V -ZOV) • Low noise
• Few external parts required • Short circuit protected
• Pin for pin compatible with TDA2002
ABSOLUTE MAXIMUM RATINGS TYPICAL CHARACTERISTICS

Peak Supply Voltage (50 ms) ...... . .............. . .................... 25V
0
Operating Supply Voltage .... . .... .. ........... .. .... ... ....... ....... ZOV
Output Current
8
Repetitive ................... .. ..... . ............................. 3.5A Av = 100
Non-repetitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..... . .... 4.5A V5 = 14.4V- f-
RL =2Q
Input Voltage ..... : .. .............. . .................. . . . .......... ±o.5V 6
Power Dissipation ................ . ....... .. .... .. ..... .. ............ 15W

Operating Temperature ......... . ......... . .... . . .............. 0 to +7o·c 4
Storage Temperature .... .. . ........ . ........ . .. ...... . . . .. . -60 to +tso·c
Lead Temperature (Soldering. 10 seconds) . . . .. ....................... 3oo•c
oo:~w\ ~
2
INTERNAL CIRCUIT 0
20 50 100 200 500 1K
!=:':'1'
2K SK 10K 20K
FREQUENCY -Hz
Distortion vs
Frequency
0
/
R,l= ~~
~
~
6
_L_ 40 17"
_L
>
I / [/"'
"z 1
2
/ v
...~ L: /
.....
~
~
8
/;:;
~
0
4
0
12 16 20
+INPUT -INPUT VsuPPLv-VOLTS
Output Swing vs
TYPICAL APPLICATIONS Supply Voltage
Vs Vs
14.4V 14.4V
2~~4!1
2.2!.1 2.211 2.211
220H
I 0.2p:F 1
~ -:;:-
16W Bridge Amplifier Basic Audio Amp
55
LINEAR (AUDIO)
386 LOW VOLTAGE AUDIO POWER AMPLIFIER

276-1731

The 386 is a power amplifier designed for use in low voltage consumer ap-
TOP VIEW
plications. The gain is internally set to 20 to keep external part count low, but
the addition of an external resistor and capacitor between pins 1 and 8 will in-
crease the gain to any value up to 200. GAIN
The inputs are ground referenced while the output is automatically biased to
-INPUT
one ha lf the supply voltage. The quiescent power drain is only 18 milli-watts
when operating from a 6 volt supply, making the 386 ideal for battery operation. +INPUT
GND
FEATURES
• Battery operation • Ground referenced input
• Minimum externa l parts • Self-centering output quiescent
• Wide supply voltage range 4-12 volts voltage
• Low quiescent current drain 3 rnA • Low distortion
• Voltage gains from 20 to 200 • Eight pin dual-in-line package
APPLICATIONS
INTERNAL CIRCUIT
• AM-FM radio amplifiers • Line drivers
• Portable tape player amplifiers • Ultrasonic drivers - INPUT BYPASS GAIN GAIN + INPUT
2 7 8 1 3
• Intercoms • Small servo drivers
• TV sound systems • Power converters

Supply Voltage .. . .. .. ... ..... . . . ... . .. . . .. .. ... .. . ... ... .. . . . .. . . ... 15V
Package Dissipation 8 Pin DIP .... . .. . .. .. . .. .. . .. .. .. .... . . ... . .. . 660 mW
Input Voltage .. . ... ... ~ ... . .. . ... ... . . ... .. . . . . .. . .. . . . ... .. .. . . ... ±o.4 V
junction Temperature . .. . . . . .. . ......... ... ... . .. . ..... .. . . . ...... + 15o•c
Operating Temperature . ........ . ... ... . . . ....... . .. ...... .. . . . 0 to +7o·c
Storage Temperature . .. .... . . .. . . . . . .. . . . .. . ... . .. .. . . . .. .. -65 to + 15o•c
Lead Temperature (Soldering. 10 seconds) ... . .. . . . . ......... ........ + 3oo•c
~
~ 2.0r~::-:~:""':b""+T- -+ ' -j·---~;--+T-j
T_- +- -,
l
~ 10 RL
i=
Ya "= SVHI-i+ftttt!H-tltf#tll
80
ii; 1.0
s! JA~t-
5 0.5
~ 1.6 PoUT " 12SmW-t-+--t-H a 1kHzilt-1+ftttt!H-IIH#tll v.~ yl--' ! o.• H--;lo''++-H ,.ct-+-1
co~;~
u: t "' 0.8
~ Av = 26dB(Cu = 0 ) _
~ ;~~T
a 1.2!-H-+-++-t-++-11 c ·~+Hffit-H~~~~ i
z
0.6
~v~
I
- z
2 o.3 1-tl-;;-i:±+::H-,t."f--+-1
:
"~ o.a!-H-+-++-t-++-1 "~ ·~+Hffit-H~~tt~ fg 0.4
I 1oz;:~~r jg 0.2 lh+-h.f-:,1"'++
I c c
~ 0.4 P"-kl-t-+-++:..t--+-1 "
a:
c
:J: ~ 0.2 ~ 0.2
....r
r/ Vs =6V 3~ 01~1+ ~ 0.1 .... <+--+-+
~ r--t---f---j---H---j ~ -(•yc ~
~ 0 20 100 1k
FREQUENCY (Hz)
10k e~ o~~~~titt®;~~
o.oo1 0.01 0.1 1.0
OUTPUT POWER (WATTS)
0 0~0--0~
.•~0~.•~~
0.~
3 --0.~4~
0.5
0 0
0.2 0.4
0.6 0.6 1.0
0
Distortion vs Distortion vs Device Dissipation vs Device Dissipation vs Device Dissipation vs

Frequency Output Power Output Power-40 Load Output Power-80 Load Output Power-160 Load
v,. v,. I >SO~iF4ll v,.

T O.OS~F
~ 100
I
-='"
BYPASS
100fLF ~
+ -;:-
Amplifier with Gain = 20

(Minimum Parts) Amplifier with Gain = 50 Amplifier with Gain = 200
56
LINEAR (AUDIO)
5.8W AUDIO POWER AMPLIFIER TA7205AP

276-705

The TA7205AP is a monolithic audio power amplifier with a built in thermal
shut-down circuit designed for car radio and stereo applications.
FRONT VIEW
FEATURES
• Low distortion 0
THD=0.15o/o (Typ.) (@PouT=1W, Gv=55dB)
THD=0.07o/o (Typ.) (@P0 m=1W, Gv=44dB) •
• Operating supply voltage range: Vcc=9-18V
• 'PCT' process to insure low noise characteristic •
• Current limiting for short-circuit protection
• Built in thermal shut-down circuit
• Built in surge voltage protection circuit
PIN FUNCTION
ABSOLUTE MAXIMUM RATINGS 1 V+
2 BOOTSTRAP
Operating Supply Voltage(Vcd ........................................ 18V 3 DECOUPLING
Quiescent Supply Voltage (VccQ) ...................................... 25V •
5
PHASE COMPENSATION
PHASE COMPENSATION
Output Peak Current (Io) ................ . ......... .. ................. 4.5A I INPUT
7 NEGATIVE FEEDBACK
Quiescent Current (!ceQ) ......... .. ................ ... .............. 80mA I PHASE COMPENSATIOM
Operating Temperature ..................................... -20 to +75"C '

10
GROUND
OUTPUT
Storage Temperature ..................... .. ..... .. ......... -55 to +150"C
INTERNAL CIRCUIT TYPICAL CHARACTERISTICS

0
_! J: : !~Hz
8
Y~c ~ 1~ - - RL ,. 2n
•
,
13.2V
-
4
I .,........
18V
j 18Y
2
~
13i2V1
0
8 10 12 14
OUTPUT POWER Pouy-W
Power Dissipation
vs Output Power
v!,
....
z
~ 20
....
ffi
0 2
1-
lfc~ - t-r-
-
Ill ..
5
0 0
~ 0
8 10 12 14 18 18
TYPICAL APPLICATION SUPPLY VOLTAGE Ycc-V
Quiescent Current and

Output Voltage vs
r-~----------~-o+V
Supply Voltage
I470~F
10
ri1NF/NI E ~JrJIN~
47J.I.F
7 I
64Cm 2 x 2mm
HEAT SINK
OUTPUT
...
;!: 8
~
t- I'..
I.'-
0.047~F 2 r-~Err s.~~i I'::
0
25 50 75 100 125 150 175
AMBIENT TEMPERATURE TA
Allowable Power Dissipation

5 Watt Audio Amplifier vs Ambient Temperature
57
LINEAR (AUDIO)
20W HI-FI AUDIO AMPLIFIER

TDA1520A
276-1305

The TDA1520A is a monolithic integrated hi-fi audio power amplifier designed
for asymmetrical or symmetrical power supplies. The circuit can deliver out-
put power up to 20 watts i11to 4 and 8 ohm speakers and is intended for use in
audio and television.
FEATURES
• Low input offset voltage
• Output stage with low cross-over distortion
•A.C. short-circuit protected
• Very low internal thermal resistance
• Thermal protection
• Very low intermodulation distortion
• Very low transient intermodulation distortion

Supply voltage (VP) ....... .... ....... . . .. .. .......... . .' ...... . ..... . 50 V
Total quiescent current at Vp = 33 V (Itot) . . . . . . . . . . . . . . . . . . . . . . . . . 70 rnA
Output power at d 101 = 0.5% sine-wave power
Vp =33 V; RL =
4 n (PO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 W
Vp =42 V; RL =
8 ll (PO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 W
Closed-loop voltage gain (externally determined) (Gc) .. . .. .. . . .. . . .... 30 dB
Input resistance (externally determined by R8 . 1 ) (Ri) .. . ... . . .. . ....... . 20 kn
Signal-to-noise ratio at P 0 =
50 mW (S/N) . . .. ... ...... . . ..... ........ 76 dB
Supply voltage ripple rejection at f =
100Hz (RR) ........... . . ....... 60 dB
BLOCK DIAGRAM
PIN FUNCTION
1 Non-inverting input
2 Input ground
(substrate)
3 Compensation
4 Negative supply
(ground)
5 Output
6 Positive supply (Vp)
7 Not connected
8 Ripple rejection
9 Investing input
(feedback)
r .
58
LINEAR (AUDIO)
'
TDA1520A 21s-1aos
TYPICAL APPLICATION
Vp Rsupply
, - - ~--- Vsupply(va)
6
~·l
·:4: I
. , 2.2mF
150~F ± 8 TDA1520A
+
i
7 - n.c .
20
KO !"-~OAR & THERMA
PROTECTION
Rsoutce 1ttF 1
r - """"'"--ji• + 5 2.2 f . r D J
~
AM PL.
• RL
~rFt""""~·~
::ho.1~F,
9
I
+680 20
KO 2
PROTECTION
2.1n
10/LF t + ..!,. 3
4
Test Circuit
I 680pF
270!1
TYPICAL CHARACTERISTICS TYPICAL CHARACTERISTICS

0.6
30
Po dtot
(W)
25 / (% )
40 1
I I
20
I I 0.4
80
15
J I
I /
10
I / 0.2
I /
J /
v/
-
5
I
0
v 0
I- /
0 10 20 30 40 Vp(V) 50 0.1 1 10 Po(W) 100
Output power (P0 ) versus supply voltage (Vp) Total harmonic distortion (d101} versus output
at f =
1 kHz, d101 =
0.5%, G, 30 dB. = power (P.) at v. 33 V, RL =
4 !l, f =
1 kHz. =
50 0.3
Ptot
,,
(W)
dtot
40 (%)
30
1'-, '1\ 0.2
\
20
' ~' \
\ J
1/
"'~' ~,
0.1
'..,' .\
/
10
v
0 "\ ,.
150 0
- 25 0 50 100 0.1 1 10 f(kHz) 100
lamb (°C)
Power derating curves. Total harmonic distortion (d1• 1) versus operat·
--- mounted on Infinite heatsink. ing frequency (f) at v. 33 V, RL= 4 0, =
--- mounted on heatsink of 2,3 K/W. P. =
10 W (constant).
59
LINEAR (OP AMP)
353 WIDE BANDWIDTH DUAL JFET INPUT

276-1715
OPERATIONAL AMPLIFIER
These devices are low cost, high speed, dual JFET input operational amplifi-
ers with an internally trimmed input offset voltage (BI-FET II'") technology). TOP VIEW
They require low supply current yet maintain a large gain bandwidth product
and fast slew rate. In addition, well matched high voltage JFET input devices
provide very low input bias and offset currents. OUTPUT A-;1 ;-f---,
These amplifers may be used in applications such as high speed integrators,
fast D/A converters, sample and hold circuits and many other circuits requir- INVERTING
INPUT A 2
..---+--,-
7 OUTPUT B
ing low input offset voltage, low input bias current, high input impedance,
high slew rate and wide bandwidth. The devices also exhibit low noise and off- NON-INVERTING INVERTING
INPUT A 3 I INPUT B
set voltage drift.
FEATURES .
• Internally trimmed offset voltage = 2 mV
• Low input bias current = 50pA
• Low input noise voltage= 16nV/vHz
• Low input noise current= 0.01 pA/vHz
• Wide gain bandwidth = 4 MHz
• High slew rate = 13 V/p.s
• Low supply current = 3.6 rnA
• High input impedance= 1012(!
• Low total harmonic distortion Av = 10,
RL = 10k, Vo = 20 Vp-p, BW =20Hz-20kHz= <0.02% 5.0
• Low 1/f noise corner = 50 Hz

• fast settling time to 0.0% = 2p.s

"'~
~
. 5
r--...
Ys=: 15V
A,•2K
Cl-= 100pF
.- ~
Supply Voltage ...... . ... . .......... . .. . ....... . .... .. ...... . .... . . ±18V
~z •.0
!'---
Power Dissipation . . ...... . ..... . ............... . .... .. ......... . 500 mW ::!
z
I'--
['. ........
Differnetial Input Voltage ........................................... ±30V
Input Voltage Range .. . ...... . .. ... ........... . . ...... . . .. ........ . ±15V ~ 3.5
z
Output Short Circuit Duration .. .. .............. ... .. . . .. ..... . Continuous "
THMAXJ ...... .... .......... . . .. .. ... . ......... .. . . ............. . ... 11s•c 3.0
20 60
Operating Temperature Range .. . . . . ..... . .... . ...... ... . .... .... 0 to 70 o C TEMPERATURE -•C
Storage Temperature Range . ........ ...................... -65 to +1so•c
Lead Temperature (Soldering, 10 seconds) ............................ 3oo•c
Unity Gain Bandwidth
vs Temperature
Cl
Yon_
>-"--<>Yo '8: ~kH• ••
lOOK 0 '·
loUT Av • 2
DC Coupled Low-Pass RC Active Filter
AI
IMO
+ A2
HIGH Z1N
LOWZour YR A
•Htgh It 100 nA
IMO
Yo • v,.
Low Drift Peak Detector Ground Referencing A Differential Input Signal
60
LINEAR (OP AMP)
353 276-1715
TYPICAL APPLICATIONS (Cont'd)

I
R1 R2
1MO
c0 o tv_ J,, "••

R1
390K
c,.
i·- R4
f~
6.2K
l_l Vo
R3 620K
R4
V+
v,. 100K
Ay=1+R21R1
~ C2 I'""F
Av = 11 (As shown)
V+
AC Coupled Non-Inverting Amplifier Bandpass Active Filter
R1
c,. R1 C1
10K
v,. o---1 f--4----H--.-----:c-1
0.001
··f R2
100K
C1 I 100K
10"F Av '"'RtiR1
Ay = 10 (As shown)
AC Coupled Inverting Amplifier Fourth Order High Pass Butterworth Filter
R2
100K
51K
R/2 50K
For R1fR2 '"' R41R3 (CMRR dependa on thla re1lator ratio match)
V0 = 1 + R41R3(V 2 - V1) 100K
As shown Yo =2(V2 - Y,)
•wide control voltage range: OVoc < Yc < 2 N + -1.5Y 0 c)
High Input Z, DC Differential Amplifier Voltage Controlled Oscillator (VCO)
61
LINEAR (OP AMP)
741 ·OPERATIONAL AMPLIFIER

276-007

The 741 series are general purpose operational amplifiers which feature im- TOP VIEW
proved performance over industry standards.
The amplifiers offer many features which make their application nearly
foolproof: overload protection on the input and output. no latch-up when the OFFSET NULL
commpn mode range is exceeded. as well as freedom from oscillations. V+
ABSOLUTE MAXIMUM RATINGS NON-INVERTING

INPUT 3
OUTPUT
Supply Voltage .... ................................................. ±J.6V V- OFFSET NULL

Power Dissipation ............................... ... ... . .... . . .... 500 mW
Differential Input Voltage ..................... .... ..... . .. ... ....... ±:30V
Input Voltage ................. . ... .... .. ...... ...... .. ..... ....... . ±J.5V
Output Short Circuit Duration.... ..... .. . ........... Indefinite
Operating Temperature Range... . . ............... 0 to +70°C
Storage Temperature Range ... . ........... . .. . ...... .. ...... -65 to + 150°C
Lead Temperature (Soldering. 10 seconds) ... .... .. ..... . ..... .. ...... 300°C
R2 +9V
+V
Sto 18V
v,.
Your
GAIN R1 R2 BW
-V
-Sto -18V
10 1K 9K 100kHz 400M!!
100 100~! 9.9K 10kHz 280M!! Your = YtN (1 + R2/R1)
1000 100!! 99.9K 1kHz 80M!! *At sets the voltage detection threshold (up to +9V).
When V1N exceeds the threshold (reference), the LED glows.
Non-Inverting Amplifier Non-Inverting Amplifier Level Detector
R2' R3'
R2
1M!! 1M!!
+V
:~,H
S to18V
Your Your
~~3
v,. R1
0.001Jl F 0.001JtF
- V -v
- Sto - 18V -Sto -18Y
Your = - YtN (R2/R1) Your = YtN
Inverting Amplifier Unity Gain Follower -9V

• Adjust R3 to just below oscillallon point.
Adjust R2 and R3 tor sounds such as bell, drum, tinkling, etc.
.02 ~F
Sl' Electronic Bell
1: 0-10.0p.A CAUTION:
THIS IS
2: 0- 1.0p.A
3: 0- 0.1 p.A AVERY
SENSITIVE PC1
CIRCUIT! 276·116
TOO MUCH CdS PHOTOCELL
LIGHT WILL
SLAM THE
METER R4
NEEDLE.
R1 1K
470!!
8\!
SK SPEAKER
- 9V
R2 100K
PC2
276·11 6
CdS PHOTOCELL
light on PC1 decreases tone frequency

light on PC2 increases tone frequency
Optical Power Meter Audible Light Sensor
62
LINEAR (OP AMP)
DUAL OPERATIONAL AMPLIFIER 1458

276-038

The 1458 is a general purpose dual operational amplifier. The two amplifiers
TOP VIEW
share a common bias network and power supply leads. Otherwise. their operation
is completely independent.
OUTPUT A -:--f---,
FEATURES
• No frequency compensation required. INVERTING
INPUT A 2
• Short-circuit protection
• Wide common-mode and differential voltage ranges NON·INVERTING INVERTING
• Low-power consumption INPUT A 3 IS INPUT 8
• No latch up when input common mode range is exceeded

v- -:--+-----'
Supply Voltage ......... . ... .. . . ... . ...... . ..... . . .... . ..... .. ...... ±:!6V
Power Dissipation . ........................................ . ...... 400 mW
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30V
Input Voltage ...................................... . ............... ±:i5V
Output Short-Circuit Duration .......... 1••••••• • •••• •• ••••• • ••••.• Indefinite
Operating Temperature Range .................................. 0 to +7o·c
Storage Temperature Range ......................... . ....... -65 to +15o·c
Lead Temperature (Soldering. 10 sec) .......... . .... . . ................ 3oo•c
R2
R2 R4
C1'
Your
v,.
R3 R6
10K 1K
-=:=- 100p.F
AS 10K
C1 stores the peak voltage at V1N· •c1 FREQUENCY
0.001 ~t F 5872Hz
0.01011 F 660Hz
0.100JLF 51Hz
1.000p.F r 8Hz Pulses are DC when C1 = 0.1JcF
Amplitude i s 5 volts.
Peak Detector Pulse Generator
R1 RS R8
FREQUENCY = 1kHz
100K 100K 100K
C2 C3 R11
C1
SQUARE : :!:7.5V -t:.:R.:..f=l:. TRIANGLE: :. 2 Y - N W - - SINE::!:2V~ -
Function Generator
63
LINEAR (OP AMP)
324 QUAD OPAMP

276-1711

The 324 series consists of four independent. high gain. internally frequency TOP VIEW
compensated operational amplifiers which were designed specifically to operate
from a single power supply over a wide range of voltages. Operation from split
power supplies is also possible and the low power supply current drain is inde-
pendent of the magnitude of the power supply voltage.
Application areas include transducer amplifiers. de gain blocks and all the con-
ventional op amp circuits which now can be more easily implemented in single
power supply systems. For example. the 324 series can be directly operated off of
the standard + 5 V oc power supply voltage which is used in digital systems and
will easily provide the required interface electronics without requiring the addi-
tional +15 Voc power supplies.
FEATURES
• Internally frequency compensated for unity gain
• Large de voltage gain 100 dB
• Wide bandwidth (unity gain) 1 MHz (temperature compensated)
• Wide power supply range :
Single supply 3 Voc to 30 Voc
or dual supplies ±1 .5 Voc to ±15 Voc
• Very low supply current drain (BOO !LA) -essentially independent of supply
voltage (1 mW/op amp at +5 Vocl
• Low input biasing current 45 nAoc (temperature compensated)
• Low input offset voltage 2m Voc and offset current 5 nAoc INTERNAL CIRCUIT
• Input common-mode voltage range includes ground (Each Amplifier)
• Differential input voltage range equal to the power supply voltage
• Large output voltage swing 0 Voc to V+ -1.5 Voc

Supply Voltage. V+ . . .... . ... . ........ . ... .. . . ...... . .... 32 Voc or ±16 Voc
Differential Input Voltage ...... . ...... . .... . . . ............ . ... . .... . 32 Voc
Input Voltage ... . . . . ... .... . . .. ... . .. .. ...... ... .. ... - 0.3 Voc to +32 Voc
Power Dissipation /
Molded DIP............ . ........ . ... . ...... . . .. ... . ....... 570 mW
Cavity DIP ... . ..... . .... . .... ... .... . ...... . ... . .. . . .. ......... 900 nW
Output Short-Circuit to GND (One Amplifier) ..... . . . . .... . . . . ... Continuous
V+ ~ 15 Vocand TA = 25"C
Input Current (VIN < - 0.3 Vod ...... . . . ..... . .... . . . ....... . ...... . . 50 rnA
Operating Temperature Range ......... . ........ . ..... . ... . . ·.. .. 0 to +70"C
Storage Temperature Range ....... . ............. . ... ... ..... -65 to +150"C
Lead Temperature (Soldering. 10 seconds) . . . . . . . . . . . . . ..... .. ... 300 ~C
+v~
4
Your
TV IN
Rl 2400 Your = V1N
lo 1 amp/ volt VIN RE 10

Driving TTL (Increase RE for 10 small) Voltage Follower
High Compliance Current Sink R1 1N914
1M
R1 R1 1N914 R2 1N914
JOK
100K
R2 R4 RJ R4 RJ
V+~~~4---~~~ AS
100K 100K V+ o--"",o"o"'K---i---,"oo"'K----' V+ ~~~-t------'V'.tv-----'
100K 100K
R3 100K
AS 100K R4 100K
Squarewave Oscillator Pulse Generator Pulse Generator
64
LINEAR (TIMER)
TIMER 555
276-1723

The 555 is a highly stable device for generating accurate time delays or oscilla-
tion. Additional terminals are provided for triggering-or resetting if desired. In the TOP VIEW
time delay mode of operation. the time is precisely controlled by one external re-
sistor and capacitor. For astable operation as an oscillator. the free running fre-
quency and duty cycle are accurately controlled with two external resistors and 7 GND 8 +~c /lf
'-~
one capacitor. The circuit may be triggered and reset on falling waveforms. and 7 DISCHARGE 1,/J
the output circuit can source or sink up to 200 rnA or drive TTL circuits.
~1 B THRESHOLD '2.//l
FEATURES
'fJ I~ ~g~::gi ~ tI
• Timing from microseconds through hours 5
• Operates in both astable and monostable modes

• Adjustable duty cycle
• Output can source or sink 200 rnA
• Output and supply TTL compatible
• Temperature stability better than 0.005% per oc
• Normally on and normally off output
APPLICATIONS
• Precision timing • Time delay generation • Pulse position TRUTH TABLE
• Pulse generation • Pulse width modulation
• Sequential timing modulation • Linear ramp generator PIN 2 PIN 6 PIN 4 PIN 3
TRIGGER THRESHOLD RESET OUTPUT
ABSOLUTE MAXIMUM RATINGS H X H L
Supply Voltage ........................................ . ... . ....... +16V L X H H
Power Dissipation . . .................... . ......................... 600 mW H L H L
Operating Temperature Range ............... . . . ....... . ... . .... 0 to +70°C X X L L
Storage Temperature Range ....... . .................... . .... -65 to +150°C
Lead Temperature (Soldering. 10 seconds) ....... . . . ........ . ......... 300oC X = Don't Care L = Low Level H = High Level
..."-
1
u
w The charge time (output high) is given by: t 1 = 0.693 (RA + R8 ) C
u The discharge lime (output low) Is given by: 12 = 0.693 (Ra) C
z Thus the total period Is: T= 11 + t 2= 0.693 (RA + 2R 8 ) C
~ The frequency of oscillation Is: f = 1fT = 1.44 I (RA + 2R 8 ) C
~
"
u
FREE-RUNNING FREQUENCY t - Hz
Capacitance vs
Free-Running Frequency
_jL
0.1"F LI. 1M
7
4
1M
1
555
01 5 8
TO
+15V NORMALLY 0.01j..!F
1N4001 ON LOAD 3
100K
~
~ ..
C1
R1 4.7K
IGNITION
-_1$ 10~F
10K
~LI·
SWITCH TO
NORMALLY 33K 33K
START a OFF LOAD
ON ~
~
5J
5000
555
]
4
12V
1 8
~
3
2200
R2 n 450
SPEAKER
Automatic Headlight Turn-Off Circuit Relay Timer Warble Alarm Circuit
65
LINEAR (TIMER)
556 DUAL TIMER

276-1728
GENERAL DESCRIPTION · ,. PIN CONNECTION

The 556 dual timing circuit is a highly sti~le c~ntroller capable of producing
accurate time delays or oscillation. The 556 is a dual 555. Timing is provided by TOP VI EW
an external resistor and capacitor for each timing function. The two timers
operate mdependently of each other sharing ohly Vee and ground. The circuits
m~y be triggered and reset on falling waveforms. The output structures may DISCHARGE -:1,.---f------,
sirlk' or source 200 rnA. ·

THRESHOLD 2
FEATURES ~~~~:~~ -:3:---h-Yr

• Timing from microseconds through hours RESET
• Operates in both astable and monostable modes
• Replaces two 555 timers
• Adjustable duty cycle
• Output can source or sink 200 rnA
• Output and supply TTL compatible
• Temperature stability better than 0.005% per ·c
• Normally on and normally off output
APPLICATIONS
• Precision timing • Pulse width modulation
• Pulse generation • Pulse position modulation
• Sequential timing • Linear ramp generator
• Time delay generation

Supply Voltage . . ........... . . . . . .. ... ... .. ... . . .. ... . .. . .. ... .... . +16V
Power Dissipation . ... .. ... . .. . . .. .. . . ... .. .. . ... .. ... .. ..... .. ... 600 mW
Operating Temperature Range .... . ... .. ... .. ...... . .... .. ..... . 0 to +7o•c
Storage Temperature Range .. . ........ .. ..... . ..... .. ... ... . - 65 to +15o•c
Lead Temperature (Soldering, 10 seconds) . .. .. . .. .. .... ... . ..... .. ... 3oo·c
1.2
Vc~ = lsv
• 1.0
... "I T~ = lm·~ V
"I ~ 0.8 f I "- LL
"w
";!z
The charge time (output high) is ginn by:
t1 = 0.693 (RA + Re) C
The discharge time (output low) is given by:
t 2 = 0.693 (R 8 ) c
i
~ 0.6
v_,
2slc ~
N rL'
u Thus the total period Is: ~ -sl•c _
~ T = t 1 + t2 = 0.693 (RA + 2R 8 ) C
"" The frequency of oscillation is: ,.

~ 0.4
f =1fT= 1.44 I(RA + 2R 9 )c
z
i o. 2 /J I
0
V)_V
0 0.1 0.2 0.3 0.4
FREE-RUNNING FREQUENCY I - Hz
LOWEST VOLTAGE LEVEL OF TRIGGER PULSE
Your x Vee- Y
Capacitance vs Minimum Pulse Width vs
Free-Running Frequency Lowest Voltage Level of Trigger Pulse
12
2.0
10
y
>
I
5
f-J. j IJc b.....-
'• ='-s~·c
, ~v
~1. 6
"EI 8 ~ +25°C
0
v ~s•c /
1- 0
ffi ~
-
1. 2
~
/
6
"~ +125°C 1--
V- ~ v ~25"C
::>
" g
~
0.8
4
p ~
ii:
2~ ~
0 0. 4
:z: 5V '" Vcc :!i> 15V
0 ":;: 0 Jj
10 15
SUPPLY VOLTAGE - V 1 10 100
OUTPUT SOURCE CURRENT lsouRCE - mA
Supp,l y Current High Output Voltage vs

vs Supply Voltage Output Source Current
66
LINEAR (VOLT REG)
3-TERMINAL ADJUSTABLE POSITIVE REGULATOR 317T

276-1778
GENERAL DESCRIPTION
The 317T is an adjustable 3-terminal positive voltage regulator capable of
supplying in excess of 1.5 A over a 1.2 V to 37 V output range. This device is PIN CONNECTIONS
exceptionally easy to use and requires only two external resistors to set the
output voltage. FRONT VIEW
• In addition to higher performance than fixed regulators, the 317T offers full
overload protection available only in IC's. Included on the chip are current
limit, thermal overload protection and safe area protection. All overload pro-
tection circuitry remains fully functional even if the adjustment terminal is dis-
connected.
Normally, no capacitors are needed unless the device is situated far from the
input filter capacitors in which case an input bypass is needed. An optional
output capacitor can be added to improve transient response. The adjustment
terminal can be bypassed to achieve very high ripple rejection ratios which are
difficult to achieve with standard 3-terminal regulators.
Besides replacing fixed regulators, the 317T is useful in a wide variety of
other applications. Since the regulator is "floating" and sees only the input-to-
output differential voltage, supplies of several hundred volts can be regulated
as long as the maximum input to output differential is not exceeded. 317T
It will also serve as a simple adjustable switching regulator, programmable
output regulator, or by connecting a fixed resistor between the adjustment and
output, the 317T can be used as a precision current regulator. Supplies with TYPICAL APPLICATIONS
electronic shutdown can be achieved by clamping the adjustment terminal to
ground which programs the output to 1.2 V where most 'oads draw little v,. Your
current.
FEATURES
, • Adjustable output down to 1.2V • 100% electrical burn-in R2 "'
Your=1 .2SY{1+fi;")
• Guaranteed 1.5A outpput current • Eliminates the need to stock many v,N > Your + 1.25
• Line regulation typically 0.01%/V voltages VOLTAGE REGULATOR
• Load regulation typically 0.1% • Standard 3-lead transistor package
• Current limit constant with • 80 dB ripple rejection
temperature
R
YIN lour
ABSOLUTE MAXIMUM RATINGS J
Power Dissipation .. .. . ...... .... . ... . . ..... ..... . .. . .... Internally limited
Input-Output Voltage Differential. ............. . . ... ..... . ..... .. ....... 40V lour= 1:1s
Operating Junction Temperature Range ... . ..... . . . .. . ........ . . 0 to + 125°C
CURRENT LIMITER
Storage Temperature ............ ........ .. .. .. . ......... . .. -65 to +150°C
Lead Temperature (Soldering. 10 seconds) . . ... .. ... . . .. . . . .. ..... .. . . 300°C
INTERNAL CIRCUIT
R1 R2 R3 R4 R5
3100 3100 100!1 82!1 5.6K
R8
200K
01
S.3Y C1
30pf
C2
R10 R12 R13 30pf
4.1K 72!1 5.1K
Rt
11100 R11 R14 R28
5.8K 12K 0.10
Your
ADJ
67
LINEAR (VOLT REG)
317T 276-1778
01
2N37t2
L1 v,.
600JA.H*
R2
18-32Y
0.250 R2 2.4K
R3
C1 • C2
0.011-lF C4 100JA.Ft 12V Battery Charger
50"F
01
1N3810
300pF
tSoaid Tantalum
•core-Arnold A·264111-2 10 tum•
1200
-%12v... ~----4 4800

__r::::::t___ 8Vpop
-----.....::::: 1A
Low Cost 3A Switching Regulator
1200
Your I--.__ _.,__

317
AC Voltage Regulator
0.2!1
Adjustable 4A Regulator SA Constant Voltage/Constant Current Regulator
68
LINEAR (VOLT REG)
~ ADJUSTABLE VOLTAGE REGULATOR 723

276-1740

The 723 is a voltage regulator designed primarily for series regulator applica-
tions. By itself. it will supply output currents up to 150 rnA; but external transis-
tors can be added to provide any desired load current. The circuit features TOP VIEW
FR£QUENCY
extremely low standby current drain. and provision is made for either linear or NC COMPENSATION NC
foldback current limiting.
FEATURES
• 150 rnA output current without external pass transistor
• Output currents in excess of lOA possible by adding external transistors
• Input voltage 40V max
• Output voltage adjustable from 2V to 37V
• Can be used as either a linear or a switching regulator
The 723 is also useful in a wide range of other applications such as a shunt reg-
ulator. a current regulator or a temperature controller.

Pulse Voltage from V+ to V- (50 ms) .......... . ............... . .. .. .... 50V NC CURRENT CURRENT INVERTING NON- YREF
liMIT SENSE INPUT INVERTING
Continuous Voltage from V+ to V- ......... . ... . . .. ........... . ... . .... 40V INPUT
Input-Output Voltage Differential ........... . ....... . .. . .... . ....... . . . 40V

Maximum Amplifier Input Voltage (Either Input) . .. .. . . . .............. . 7.5V
Maximum Amplifier Input Voltage (Differential) ...... . ... . .. . .... . ...... 5V
Current from Vz ... . .. ... .. . . .. .. . ... : . . .. . .... ....... . . ..... .. . .. . 25 rnA
Current from VREF . . .. . . .. . . . . ... . .. .. . . . . .... . . .. .. . .. . . . ....... . . 15 rnA
Internal Power Dissipation Metal Can .... . .. . . . . . . . .. . . . .. . . . . . . . .. 800 mW
Cavity DIP .. .. .. . ... . . .. .. . . . . ... . .. . . . . . ... .. . . .. . . .. . .. .. .. . 900 mW
Molded DIP . . ... . ......... . .. . . . ......... . ....... . .. . ......... 660 mW
Operating Temperature Range .. . ... . . . ...... . ..... . ... . ..... .. . 0 to +7o•c
Storage Temperature Range Metal Can.. .... . ..... . . . . . . .... . -65 to +15o•c
DIP . .. . . . ..... . .. . , . . . ... . . . .. . .. . . ... . ......... ... . ... -55 to +125·c TYPICAL APPLICATIONS
Lead Temperature (Soldering. 10 sec). . .. . . . . . ..... . ............. . ... . 3oo•c
('louT • 2 lo 7Volta)
+0.I
...
1.2
Vout • +5V
v,N .. +12V
1-
LU 1.0 Rsc z 100-1-
~
5 o.8
>
,.J 0
""'!,... ....... r.., .. o•c
I
I
c,.,
1 R2
!; r- 1-- r-rt z 11o·~ I

i""==:::::l.l. TA ::o: 2s•c
~ 0.
• r,. . o•c
z
f-l., r-
"0w
~
•
0.
v1N""
r.., . 25•c
+12V
5
~ - 0.I
r • ro•c
-~=:::~
)'-...
r--.
I' TYPICAL PERFORMANCE
Regulae.d Output YoU11ge SV
~v.,. = 3Y)
5~ 0.2 Your .. +SV
Une R-..lauon (
LNCI Regulation ( AIL " SOmA) 1.5mV
O.SmV
Rsc • 100
Note: R3 "' R~\R:a tor minimum tempen~ture drift.
0 I -0.2
20 80 80 100 0 10 20 30
OUTPUT CURRENT-mA OUTPUT CURRENT-mA
Basic Low Voltage Regulator
Relative Output Voltage
vs Output Current
Load Regulation vs
Output Current
.,.
200
TJMAX • 12S•C~ ~
RrH • 111• CIW
180
h
~.:6·~::;S~Ne:~ -
R3
~ 120
I
:!
1\
"
.=' 80
\
40
f-r\ N- =,25"~ TYPICAL PERFORMANCE
1'+-
rrcN
Regulated Output Voltage 15V
0
T"t •
10
I
20 30
(VIN - Your) - VOLTS
.. 50
LlneRegulatlon(A Y 1N
Note: R3 ::z:
3V)
R 1R~R~2
=
1.5mV
Load Regulation {.lll ::z: 50mA) 4.5mV
tor minimum te mperature dritt.
Maximum Load Current vs Current Limit Sense Voltage

Input-Output Voltage DIHerentlal vs Junction Temperature Basic High Voltage Regulator
69
LINEAR (VOLT REG)
SV VOLTAGE REGULATOR
12V VOLTAGE REGULATOR
15V VOLTAGE REGULATOR

This series of three terminal regulators is available with several fixed output
voltages making them useful in a wide range of applications. One of these is local
on card regulation. eliminating the distribution problems associated with single
point regulation. The voltages available allow these regulators to be used in logic
systems. instrumentation. HiFi. and other solid state electronic equipment. Al-
though designed primarily as fixed voltage regulators these devices can be used
with external components to obtain adjustable voltages and currents.
This series will allow over 1.5A load current if adequate heat sinking is pro-
vided. Current limiting is included to limit the peak output current to a safe
value. Safe area protection for the output transistor is provided to limit internal
power dissipation. If internal power dissipation becomes too high for the heat
sinking provided. the thermal shutdown circuit takes over pr~venting the IC from
overheating.
FEATURES VOLTAGE RANGE

• Internal thermal overload protection 7805 ..... . ... . . . ... . . . . . 5V
• No externa l components required 7812 ... .. . .. ... . ... . ... 12V
• Output transistor safe area protection 781 5 . . ... . .. . . ... . .. . .. 15V
• Internal short circuit current limit

Input Voltage
(Output Voltage Options 5V through 18V) .... .. ... . .. . . . . . ..... . .... . 35V
(Output Voltage Option 24V) . .......... .... . .. . ... .. . .. . . .. .... . .. . . 40V
Internal Power Dissipation . . .. . . ..... . .. . .... ...... . ..... Internally Limited
Maximum Junction Temperature . . .. . . . ... . ..... . ... .. . .. . . ......... . 15o•c
Operating Temperature Range .... ... ..... .. . .... . . ... . . . ... .. . . 0 to + 7o·c
Storage Temperature Range . .... . .. . . . . . . .. . ... .. . . . . . .. .. .. -65 to + 15o·c
Lead Temperature _{Soldering. 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . 3oo•c
+YIN o---.--'-j 78XX ~-=-~---,--r--<>+Your Your

L....--..,.,_....1
l 0.33j..!f
4.7K
YouT
OUTPUT CURRENT : R'f"
4.7K
0.50
Current Regulator
± Tracking Voltage Regulator Switching Regulator
2N4398
1...,.
High Output Current, Short Circuit Protected Positive and Negative Regulator
70
LINEAR (MISCELLANEOUS)
QUAD COMPARATOR 339

276-1712

The 339 series consists of four independent voltage comparators which were TOP VIEW
designed specifically to operate from a single power supply over a wide range of
voltages. Operation from split power supplies is also possible and the low power ,...---+--,1:-:-4 OUTPUT 3
1- ! - - - ,
OUTPUT 2--,.
supply current drain is independent of the magnitude of the power supply
voltage. These comparators also have a unique characteristic in that the input
common-mode voltage range includes ground. even though operated from a
single power supply voltage.
FEATURES
• Wide single supply:
Voltage range 2 Voc to 32 Voc or dual supplies ±:1 Voc to ±:16 Voc
• Very low supply current drain (0.8 rnA) -independent of supply voltage
(1 roW/comparator at +5 Voc)
• Input common-mode voltage range includes ground
• Differential input voltage range equal to the power supply voltage
• Low output 1 mV at 5 ~;saturation voltage 70 mV at 1 rnA
• Output voltage compatible with TTL (fanout of 2). DTL. ECL. MOS and CMOS
logic systems
ABSOLUTE MAXIMUM RATINGS INTERNAL CIRCUIT

Supply Voltage. V+ ........................ . ..... .. ...... 32 Voc or ±:16 Voc
Differential Input Voltage . ... . . .. .... . ... . .... . ... . . . .... . ........ . . 36 Voc
Input Voltage ..................... .. .. . ....... .. .... . . -0.3 Voc to +36 Voc
Power Dissipation
Molded DIP ....... . . . .. . ... . .... . ... . .. .... .. ... . .. . . . . . .. . .. . 570 mW
Cavity DIP ................. . .. .. ... .. ..... . ..... . ..... . .... . .. 900 mW OUTPUT
Output Short-Circuit to GND .............. . ..... . ..... . ........ Continuous
Input Current (YIN <'-0.3 Vocl ... . ..... . ..... .. . . ....... . ........... 50 rnA
Operating Temperature Range .................. . . . . . .. .... ..... 0 to +70' C
Storage Tempera·ture Range ............ . . ...... . . ..... . . . .. -65 to +150'C
Lead Temperature (Soldering. 10 seconds) . . . . .... .. .... . ............. 300' C
5 VOLT GROUP
15V GROUP
Y+
Y+ Y+
+v1,.
39K 200K
YouT 3K 3K
+VREF
Basic Comparator
. Y+
c
vo~ _[ 100K
1K
:·c s 100K
1K I == A+B +C
"0" "1" "0 " " 1"
AND Gate OR Gate
Y+ Y+
1M
:1. 15K
100K
Driving CMOS 10K
Y+ •• ,. o--l rr---+---t
100pF
1NJ14 100K
YouT
R 0-"Nv--+--!
Y+ 100K
0 ___jl_
1M
1N914
Driving TTL One-Shot Multivibrator Bi-Stable Multivibrator
71
567 TONE DECODER

276-1721

The 567 is a general purpose tone decoder designed to provide a saturated
TOP VIEW
transistor switch to ground when an input signal is present within the
passband. The circuit consists of an I and Q detector driven by a voltage con-
trolled oscillator which determines the center frequency of the decoder. Exter-
nal components are used to independently set center frequency, bandwidth
and output delay.
FEATURES
TIMING
• 20 to 1 frequency range with an external resisfor I CAPACITOR
• Logic compatible output with 100 rnA current sinking capability
• Bandwidth adjustable from 0 to 14% V+ 4
TIMING
5 RESISTOR
• High rejection of out of band signals and noise
• Immunity to false signals
• Highly stable center frequency
• Center frequency adjustable from 0.01 Hz to 500 kHz
APPLICATIONS +Y
• Touch tone decoding
• Precision oscillator
• Frequency monitoring and control
• Wide band FSK demodulation
• Ultrasonic controls
• Carrier current remote controls
• Communications paging decoders

Supply Voltage . .. ... . ... . ......... . . . . .. . . ... .. ... . ... .. .... ... .. .. .. 9V
Power Dissipation . . .. .. . ... ... .. . . . ..... . .... . . . ........... . . ... 300 mW
V8 (Output Voltage) ..... . . . ........... . ... . . . . ... .... . . . ....... . .... . 15V
V3 (-Voltage at Input) . . . . . . . . . ... ......... . ..... ... .. ... .... . .. . .. . -10V
V3 (+Voltage at Input) ... . .. . ... .. ........ .. .. . . .. . . .... . . . .. . ... V8 +0.5V
Operating Temperature ... . .. . .. . . .. . . . . ... . ....... . . . . . ...... 0 to +70°C
Storage Temperature Range ........ . .... .. . . . . . . . .. .... . . . -65 to +150°C
The center frequency of the tone decoder 11 equal to the fr...,unnlng

frequency of the VCO.
This Is given by f0 3!l 11A1 C1
The blind width of the filter may be found from the approximation
BW - 1070 ~ ln % offo-
'Jt;C2
Where: V1N """ Input voltage (volta rms), V1N .s 200mV.
C2 """ Caacltance at pin 2 In l'F.
•Note: Adjust for 10 - 100kHz.

f1 = 100kHz +SV
AC Test Circuit
ComPGMnt .,,,.,..
IIJI>)
R1 1.1 to 15K
+Y R2 4.7K
•• 20K
C1 0.10~F
C2 1.0~&F
C3 2.2pF
t_,_ _;::~...,...r--.1-t---' C4 2SOJlF IV
200mVrma
Oscillator with Double

Frequency Output Touch-Tone Decoder
72
LED FLASHER/OSCILLATOR 3909

\_
276-1705

The 3909 is a monolithic oscillator specifically designed to flash light emitting
diodes. By using the timing capacitor for voltage boost, it delivers pulses of 2 or TOP VIEW
more volts to the LED while operating on a supply of 1.5V or less. The circuit is IK SLOWAC V+
inherently self-starting, and requires addition of only a battery and capacitor to • •
function as a LED flasher.
It has been optimized for low power drain and operation from weak batteries so
that continuous operation life exceeds that expected from battery rating.
Application is made simple by inclusion of internal timing resistors and an ••
internal LED current limit resistor.
3K
Timing capacitors will generally be of the electrolytic type. and a small 3V
rated part will be suitable for any LED flasher using a supply up to 6V. However.
when picking flash rates. it should be remembered that some electrolytics have
very broad capacitance tolerances. for example -20% to + 100%.
FEATURES
• Operation over one year from one C size flashlight cell •
• Bright. high current LED pulse
• Minimum external parts
NC Y-
~ Low voltage operation. from just over 1 V to 5V 3K FAST RC OUT
• Low current drain. averages under 0.5 rnA during battery life
• Powerful; as an oscillator directly drives an 80 speaker

Power Dissipation .................. .. .. .. .. . ....... . . 500 mW o •• • •• • • • •• •
V+ Voltage ... . .... .. . o • ••••• • •••• • • •• ••• •• •••• 6.4V

• ••••• o ••••• • •• • •• • • •
Pulse Width . . ... . .. . ...... . o • • ••• • o • • •••• o • • • • 6 ms

•• • • ••• • • ••• • • • ••••••
Peak LED Current .... . o ••••• o •••••• • o ••••• • ••••• 45 rnA • ••••••• • •• • ••••••
Operating Current .... . . . ........... o ••• • • • ••••••• 75 rnA • •••••••• • • • •••••
Flash Frequency . . . .. . . .. . ..... . .. . . ..... . .. ..... .... .. . . .. . .... . . . 1.3 Hz

High Flash Frequency ... . ............ . . . .. . . . ..................... 1.1 kHz
Operating Temperature Range ......... . .. 0 •• •-25 to +7o•c
•• •••••••••• •••
TYPICAL APPLICATIONS TYPICAL CHARACTERISTICS

V+
••
•••
0 ' 1 1!.. 3--,~1.7

1.::-1""'1,..,,2,....1...
....... 4 --"1.5......-;i1.6
1.5V Flasher BATTERY VOLTAGE (V)
Drain Current vs
Battery Voltage
ESTIMATED BATTERY LIFE

(CONTINUOUS 1.5V FLASHER OPERATION)
Warning Flasher High Voltage Powered TYPE

SIZE CELL
STANDARD ALKALINE
AA 3 MONTHS 6 MONTHS
c 7 MONTHS 15 MONTHS
0 1.3 YEARS 2.6 YEARS
1.5V Note: Estimates are made from our testa and manu·
3909 tacturers data. Conditions are fresh baHerles and
room temperature. Clad or " leak-proof" batteries
are recommended for any application of live months
3909 -=..3Y or more. Nickel Cadmium cells are not recommended.
TYP1CAL OPERATING CONDITIONS
V+
NORMAL
FLASH Hz
c, Rs 1W ... V+RAHQE
300pF Note: Normal flash rate: 1Hz. Nominal flash rata: 1.3Hz Avaraga loRAIN • 2mA. 6V 2 400pF 1K 1.5K 5-25V
3V Average I OAAIN = 0. 77mA 15Y 2 180J,.tF 3.9K 1K 13-SOV
1DDY 1.7 180J..LF 43K 1K 85-200Y
3V Flasher Parallel LED's
73
MOS(CMOS)
SSI202 SV LOW-POWER DTMF RECEIVER

276-1303

The SSI 202 is a complete Dual Tone Multiple Frequency (DTMF) receiver
detecting a selectable group of 12 or 16 standard digits. No front-end pre-
filtering is needed. The only externally required components are an inexpen- 01 11 02
sive 3.58-MHz television "colorburst" crystal (for frequency reference) and a 17 04
HEXIB28
bias resistor. Extremely high system density is made possible by using the
clock output of a crystal connected SSI 202 receiver to drive the time bases of EN 18 08
additional receivers. The SSI 202 uses a monolithic integrated circuit fabri- IN1833 15 CLRDY
cated with low-power, complementary symmetry MOS (CMOS) processing. It 14 OV

Yp
requires only a single low tolerance voltage supply.
The SSI 202 employs state-of-the-art circuit technology to combine digital NIC 13 ATB
and analog functions on the same CMOS chip using a standard digital semi- ONO 12 XIN
conductor process. The analog input is pre-processed by 60-Hz reject and
XEN 11 XOUT
band splitting filters and then hard-limited to provide AGC. Eight bandpass fil-
ters detect the individual tones. The digital post-processor times the tone dura- ANALOG IN ONO
tions and provides the correctly coded digital outputs. Outputs interface
directly to standard CMOS circuitry, and are three-state enabled to facilitate
bus-oriented architectures.
FEATURES
• NO front-end band-splitting filters required
• Single, low-tolerance, 5-volt supply
• Detects either 12 or 16 standard DTMF digits
• Uses inexpensive 3.579545-MHz crystal for reference
v, v,
• Excellent speech immunity
• Output in either 4-bit hexadecimal code or binary coded 2 of 8
• Synchronous or handshake interface
• Three-state outputs
VIN<Vp VIN>V,
ABSOLUTE MAXIMUM RATINGS*
.01~F
Supply Voltage (DC) . .. ...... . .. . ..... ... .............. . ............... 7V )----1 9
-l!---o --11--o
Input Voltage (All Inputs Except Analog In) .................. - .5V to + .5V ANALOG 10pF
ANALOG
10pF
Analog In Voltage .... ................ . . . . .. . .......... ... . - 10V to + .5V IN IN
DC Current Into Any Input ...................................... ± 1.0 MA

> 100KO > 100KO
Power Dissipation (Note 1) ......................................... 65 MW
Operating Temperature ...................................... 0°C to 70°C
Storage Temperature ..................................... - 65°C to 150°C
GND GND
• All unused inputs must be connected to VP or GND as appropriate. (ON CHIP) (ON CHIP)
Note 1: Operate above 25°C @ 6.25 mw/°C
ANALOG IN Flg.1
This pin accepts the analog input. It is internally biased so that the input sig-
nal may be AC coupled. The input may be DC coupled as long as it does not
exceed the positive supply. Proper input coupling is illustrated in Fig. 1.
The SSI 202 is designed to accept sinusoidal input wave forms but will oper-
ate satisfactorily with any input that has the correct fundamental frequency
with harmonics greater than 20 dB below the fundamental. r--JDf-
v,
CRYSTAL OSCILLATOR XIN XOUT
The SSI 202 contains an onboard inverter with sufficient gain to provide 12 11
oscillation when connected to a low-cost television "color-burst" crystal. The
8~
ATB
crystal oscillator is enabled by tying XEN high. The crystal is connected 13 $51202
between XIN and XOUT. A 1 MO 10% resistor is also connected between these
pins. In this mode, ATB is a clock frequency output. Other SSI 202's may use
the same frequency reference by tying their ATB pins to the ATB of a crystal-
connected device. XIN and XEN of the auxiliary devices must then be tied
high and low respectively. Ten devices may run off a singltl crystal-connected
1 XIN CONNECTED TO V,
SSI 202. •
12
'11
13 SSI202
UP TO 10 DEVICES
74
MOS(CMOS)
SSI202 21s-13o3
Block Diagram
BANDPASS FILTERS
TIMING
CIRCUITRY ED
CLRDV
15
DV
14
HEX
DATA STROBE ,..-----+-----+'-828
:0
01
02
18
04
17
DB
18
EN
V, 5 GNO 10 GND 7
HEX/B28
This pin selects the format of the digital output code. When HEX/B28 is tied
high, the output is hexadecimal. When tied low, the output is binary coded 2 of
8. The table below describes the two output codes.
Hexadecimal Binary Coded 2 of B

Digit DB D4 D2 Dl DB D4 D2 Dl
1 0 0 0 1 0 0 0 0
2 0 0 1 0 0 0 0 1
3 0 0 1 1 0 0 1 0
4 0 1 0 0 0 1 0 0
5 0 1 0 1 0 1 0 1
6 0 1 1 0 0 1 1 0
7 0 1 1 1 1 0 0 0
8 1 0 0 0 1 0 0 1
9 1 0 0 1 1 0 1 0
0 1 0 1 0 1 1 0 1
* 1 0 1 1 1 1 0 0
# 1 1 0 0 1 1 1 0
A 1 1 0 1 0 0 1 1
B 1 1 1 0 0 1 1 1
c 1 1 1 1 1 0 1 1
D 0 0 0 0 1 1 1 1
75
MOS(CMOS)
SSI202 216-1aoa
IN1633
When tied high, this pin inhibits detection of tone pairs containing the
1633-Hz component. For detection of all 16 standard digits, IN1633 must be
tied low.
OUTPUTS Dl, D2, D4, DB and EN

Outputs Dl, D2, D4, DB are CMOS push-pull when enabled (EN high) and
open circuited (high impedance) when disabled by pulling EN low. These digi-
tal outputs provide the code corresponding to the detected digit in the format
programmed by the HEX/B28 pin. The digital outputs become valid after a
tone pair has been detected and they are then cleared when a valid_pause is
timed.
DVandCLRDV
DV signals a detection by going high after a valid tone pair is sensed and
decoded at the output pins Dl, D2, D4, DB. DV remains high until a valid pause
occurs or the CLRDV is raised high, whichever is earlier.
N/C PINS
These pins have no internal connection and may be left floating.
DETECTION FREQUENCY
Low Groupf0 High Group f0

Row 0 =697Hz Column 0 = 1209 Hz
Row 1 = 770Hz Column 1 = 1336 Hz
SSI 202 TIMING
CLROV
'"
22ms
ED
76
MICROCOMPUTER (8 BIT)
CODE-TO-SPEECH CHIP CTS256AL2

276 1786

The Code-To-Speech chip set consists of two chips: the SP0256A-AL2 (Cat.
TOP VIEW
No. 276-1784), an allophone-base single chip speech synthesizer, and the
CTS256A-AL2, an 8-bit microcomputer programmed with a letter-to-sound
based algorithm. This chip set translates English characters into LPC synthe- ..
sized speech sounds.
The SP0256A-AL2 is a standard allophone chip and is based on the
..
SP0256A speech synthesizer. This synthesizer consists of a 10 or 12 pole 31
second-order cascaded LPC filter, a controller, and a 16-Kbit ROM in which 59
...... .
37
allophones (speech sounds) and five pauses are stored.
The CTS256A-AL2 is a device whose on-board ROM is masked with code-to-
speech algorithm. This algorithm converts English text (in the form of stand- 07
ard ASCII characters) into SP0256A-AL2 compatible allophone addresses,

using letter-to-sound rules. .. ..
This chip set delivers highly recognizable speech output from any peripheral
device or computer in a flexible and cost effective manner. It can be config-
ured as a dedicated code-to-speech system, as well as add speech output to a
REFER TO
TABLE ONE
31
..
..
user's program running in this CTS256A-AL2 from off-chip Rom. Such user D2
programs are written in PIC7001 assembly language which is 100% compatible
with TMS7001 assembly language. 01
Eproms can be added to improve the pronunciation of certain proper names, DO

acronyms and technical words as well as to store user programs. AI
14
FEATURES: AI
• Unlimited vocabulary
"
vee
• Utilizes letter-to-sound rules "
...
17 A10
• Serial or parallel interface
• Microprocessor available for user code 11
..
11 A12
PIN SELECTABLE CODE-TO-SPEECH OPTIONS: A13
Refer to TABLE 1.
INPUT INTERFACE -Serial port & baud rate vs. Parallel port
INPUT BUFFER -Internal RAM vs. External RAM
DELIMITER -Any-delimeter vs Carriage-return-only
UART PARAMETERS -Program defaults vs 74LS373 selectable (or eprom
definable)
FIRMWARE (EXCEPTION-WORD/USER EPROM)
CONTROLLED CODE-TO-SPEECH OPTIONS: (optional)
Refer to TABLE 2.
• Parallel port decode relocatable

• UART parameters 74LS373 decode relocatable
• UART parameters selectable
• Start & end address of External-Ram relocatable
CODE-TO-SPEECH ALGORITHM FEATURES:

-ESCAPE "ESC", (1B Hex) THE ESCAPE-KEY CODE WILL DUMP
THE CONTENTS OF THE INPUT AND
OUTPUT BUFFERS, AND WILL ALSO
SILENCE SPEECH OUTPUT WHICH IS
IN PROGRESS.
-BACKSPACE "<-" , (OB Hex) THE BACKSPACE-KEY CODE ERASES
THE INPUT BUFFER ONE CHARACTER
AT A TIME, BEGINNING WITH THE
LATEST ENTRY.
NOTE: The R/C combination indirectly connected to PIN 14 of the CTS256A-

AL2 and to PIN 2, 25 of the SP0256A-AL2 acts as a power-on reset.
The requirement to reset the chip-set is a negative-going pulse which
remains LO for a minimum of 500 microseconds.
NOTE: A signal (input or output) that is active-LO is designated by its signal

name followed by an asterisk (*).
n
l
MICROCOMPUTER (8-BIT)
CTS256AL2 276-1786
CODE-TO-SPEECH ALGORITHM (Cont'd)
NOTE: The program default address decode of the SP0256A-AL2's ALD*
input is 2000H. It is re-definable via the EXCEPTION-WORD or USER
eprom. Refer to TABLE 2.
NOTE: MSnibble means most significant nibble, where a nibble is half a byte.
MSB means most significant byte; LSB means least significant byte.
'X' stands for the MSnibble of the MSB of the two byte address, and
can be 1,2,3,4,5,6,7,8,9,A,B,C,D, or E because an eprom may reside
from 1000H to EOOOH.
NOTE: The term 'delimiter' refers to any punctuation following a word or

numerical sequence. These include: , . ; : ! ? spaces and carriage-
returns.
CODE-TO-SPEECH ALGORI:rHM
Upon power-up (or hardware reset) the CTS256A-AL2 determines the system
configuration with respect to the following five options:
1- INTERNAL I EXTERNAL RAM SELECTION: (Refer to
TABLE 1.)
INTERNAL-RAM mode has an input buffer which accommodates words
or phrases that are no greater than 19 characters in length followed by a
delimiter; and an output buffer that accommodates an allophone transla-
tion of that word or phrase that is no greater than 26 allophone addresses.
Since the translation more often than not results in the output buffer
contents consisting of two times that of the input buffer, words no longer
than 13 characters in length and numerical sequences of no longer than 4
numbers in length should be used as a rule of thumb. If the output buffer
overflows, what has not been spoken yet from the output buffer might be
lost, and the BUSY* flag will not necessarily show an input buffer empty
status even though the input buffer might be empty. If a translation results
in an output buffer overflow, the system reset may have to be used to clear
·the system.
EXTERNAL-RAM mode can be used to extend the size of the input and
output buffers. If no EXCEPTION-WORD or USER eproms are present,
the start address default is 3000H. Static RAM can be added in 256 byte
contiguous block increments, beginning with a minimum of 512 bytes. The
algorithm will find the end address by searching for the first non-RAM
location at 256 byte intervals. The search for the end address will not prog-
ress beyond 2K bytes.
If an eprom is present, the start and end addresses are re-definable there.
Requirements are: minimum start address is 0200H; the start address must
begin on a boundary where the LSByte of the address == 00; and without
the end address specified in eprom, the maximum valid start address is
EEOOH.
In any case, 256 bytes are taken for the output buffer; the remainder is
the input buffer. (External-Ram used must have an access time of 250 nS or
less.)
2· ROM: A search is made from 1000H to EOOOH is 4K increments for
the · 5 byte sequence (SOH, 48H, 28H, 58H, 85H) which uniquely identifies
the presence of an EXCEPTION-WORD or USER eprom. If neither are pres-
ent, the system options are set to algorithm default values or can be chosen
by the Pin selectable options. If only a USER eprom is present, the system
options may be re-defined from the USER eprom; refer to APPENDIX-0. If
both USER and EXCEPTION-WORD eproms are present or if only an
EXCEPTION-WORD eprom is present, the system option may be re-defined
from the EXCEPTION-WORD eprom; refer to APPENDIX-A.B. (External-
Ram used must have an access time of 300nS or less.)
Exception-Word Eprom(s): (optional)

Exception-word eprom(s) say reside anywhere within the decodeable
addresspace of the CTS256A-AL2 from 1000H to EOOOH, providing its start
address falls on a 4K boundary. The code-to-speech initialization routine will
search for its existence which is denoted by a unique 5-byte sequence of num-
bers (SOH, 48H, 28H, 58H, 85H). A few other locations in the primary
78
Exception-Word Eprom(s): (Cont'd) CTS256AL2 276·1786

exception-word eprom are reserved, and must contain specific sequences of
numbers; the remainder are user-defined. Additional exception-word eprom(s)
contiguous to the primary exception-word eprom contain no reserved loca-
tions. Refer to APPENDIX-A, B for the applicable EXCEPTION-WORD
EPROM MEMORY MAP.
User-Eprom(s): (optional)
If a USER eprom is accompanied by an EXCEPTION-WORO eprom, it may
reside anywhere. If no EXCEPTION-WORD eprom accompanies it then it may
reside anywhere from 1000H to EOOOH providing its start address falls on a 4K
boundary; and it must then begin with the sequence SOH, 48H, 28H, 58H, 85H;
and also contain other reserved locations. If an EXCEPTION-WORD eprom is
present, the USER's program can even reside in an unused portion of the
EXCEPTION-WORD eprom. Refer to APPENDIX-D,E for the applicable USER
EPROM MEMORY MAP.
Interaction between a USER program and the code-to-speech algorithm must
be controlled in an orderly manner, ie; the user must save the processor status
before taking control of the processor for execution of any USER code (except
for character string loading operations, which is described next:)
To prepare the code-to-speech algorithm to process and speak, the USER
program passes the character string it wants spoken into the Accumulator one
character at a time, then calls the routine @SAVE which transfers it into the
input buffer. After the character string loading has been completed, the USER
code can initiate the speech by calling the @SPEAK routine; assuming that a
delimiter followed that character string. After the loaded character string· is
processed and spoken, program control resumes in the hands of the USER pro-
gram by the Branch @ USERCODE instruction.
No registers used by the code-to-speech algorithm may be disturbed by the
USER code during character string loading, (except for the Accumulator).
Prior to the USER code executing anything other than character string load-
ing, all registers used by the code-to-speech algorithm as well as the Stack
Pointer and STATUS register are to be saved. These registers must be recov-
ered prior to future character string loading operations; or prior to initiating
speech.
Because of masked code-to-speech restrictions within the CTS256A-AL2,
Interrupt-1* and Interrupt-3* are not USER accessible. Also, input from the
serial port into the USER code can be obtained, but restrictions apply.
Refer to APPENDIX-F for a discussion of the sequence of events and subrou-
tines necessary for USER/CODE-TO-SPEECH interactions as described above.
3· Serial I Parallel Input Interface Selection: (Refer to

TABLE 1.)
In the parallel mode, ASCII data is latched by an 74LS374, upon receipt
of an Active LO data-valid strobe. This strobe also vectors the algorithm to
accept the data via Interrupt-3*, PIN 12 of the CTS256A-AL2. The latch's
address default is 200H . It is re-definable from EXCEPTION-WORD or
USER eprom. (Refer to TABLE 9 for timing requirements of the parallel
port.)
In the serial mode, ASCII data is accepted via the CTS256A-AL2 PIN 16,
which is a built-in UART that requires a TTL level signal input. The baud
rate is selectable at 50,110,300,1200,2400,4800 and 9600. The other UART
parameters are set to algorithm default values, or are hardware selectable
via an 74LS373 buffer. The buffer address default is 1000H. The UART
parameters as well as the baud rate is re-definable from EXCEPTION-
WORD or USER eprom. The algorithm default UART values are: Asyn-
chronous, 7 bits/character, 2 stop bits, and no parity.
In either serial or parallel mode, the input buffer is protected from over-
flow by a hysteresis subroutine which signals the host when the input
buffer is full , and when the input buffer is ready for additional input. Hard-
ware handshaking (BUSY*) is provided to accomplish this signaling of
input buffer status.
BUSY* is Active-LO. It toggles LO when the input buffer becomes 87.5%
full. In this way the host system may use its discretion to complete that
transmission or a part thereof. If the input buffer becomes 100% full, the
parallel and serial port interrupts are disabled to prevent input buffer over-
write; and the interrupts are not re-enabled until the input buffer full con-
dition has dissipated. BUSY* will toggle hi when the input buffer becomes
50% empty; at which time the interrupts are enabled if they had been disa-
bled by a 100% full condition. (BUSY* is PIN-3 of the CTS256A-AL2 which
is a TTL level output capable of sinking 10 rnA maximum.)
79
CTS256AL2 276-1786
4· Software I Hardware (or Firmware) UART Parameters

Selection: (Refer to TABLE 1.)
This hardware option tells the code-to-speech algorithm to use the
default UART values, or to find the parameters at the 74LS373 buffer. The
buffer address default is 1000H. The UART parameters are re-definable
from eprom, but only if the hardware mode is selected via Pin 9 of the
CTS256A-AL2.
5· Any-Delimiter I Carriage-Return-Only Selection: (Refer to

TABLE 1.}
In the any-delimiter mode, the code-to-speech algorithm will process and
speak words or phrases as soon as they are followed by any delimiter. In
the carriage-return-only mode, the algorithm will process and speak words
or phrases only after a carriage-return is received as a delimiter. The
carriage-return-only mode is meant for use with a slow input device such
as a terminal, where the user wishes to buffer-up a complete phrase so that
it is spoken with fluency. If the carriage-return-only mode is chosen in con-
junction with EXTERNAL-RAM, limit to 160 characters the length of the
phrase which is entered before the carriage-return is entered. This allows
for a two line phrase to be spoken with fluency while insuring that the 256
byte output buffer should not overflow.
After completion of the initialization the phrase "O.K." is spoken to demon-
strate that the system is ready for input, then one of the following two paths is
taken dependent upon the system configuration:
1: In a 'dedicated code-to-speech system' (ie; USER eprom is not present),
the algorithm idles as long as the input buffer remains empty. Input is via
standard ASCII characters. Processing begins with an alphabetical search
of the EXCEPTION-WORD eprom, if it is present. If no exact match for the
character string is found, or if an EXCEPTION-WORD eprom is not pres-
ent, the algorithm employs a letter-to-sound rule table against which main,
right, and left context matches are performed. This results in the transla-
tion of a particular word into the proper string of allophone addresses nec-
essary for its pronunciation. This list of allophone address is sent to the
SP0256A-AL2 after a carriage-return, or after any delimiter- depending on
the mode selected.
2: • In the 'add speech to USER's program' mode (ie; USER eprom is pres-
ent), control of the processor is relinquished to the USER code immedi-
ately after the initialization is complete. The USER code may then execute
its own code, may pass character strings into the input buffer memory, or
may hand-off processor control to the code-to-speech algorithm to speak
any previously loaded character strings. If speech is initiated, control
returns to the USER code after the last delimited character string in the
input buffer has been processed. Refer to APPENDIX-F.
TABLE 1.
Hardware selectable option pin-outs of CTS256A-AL2:
PIN 6 7 8
0 0 0+-PARALLEL INPUT MODE

0 0 1 BAUD 50
J
0 1 0 BAUD 110
0 1 1 BAUD 300
1 0 0 BAUD 1200 SERIAL INPUT MODE
1 0 1 BAUD 2400
1 1 0 BAUD 4800
1 1 1 BAUD 9600
PIN 9
0 +-PROGRAM DEFAULT UART VALUES (Asynchronous, 7 bits/
character, 2 stop bits, no parity).
1 +-HARDWARE (or FIRMWARE) SELECTED UART VALUES.
PIN 10
0 +- INTERNAL-RAM BUFFERS, (20 BYTE INPUT/26 BYTE OUT-
PUT).
1+- EXTERNAL-RAM BUFFERS, (1792 BYTE INPUT/256 BYTE OUT-
PUT WITH A 2-KBYTE RAM).
80
CTS256AL2 276·1786
TABLE 1. Con't.
PIN 11
0 +- CARRIAGE·RETURN-ONL Y DELIMITER.
1 +- ANY DELIMITER.
PIN 03 "BUSY$" (Input buffer flag is a TTL level output); for RS232
compatibility use MC1488 Line Driver or equiv.
0 _, INPUT BUFFER IS > = 87.5% FULL.
1-> INPUT BUFFER IS < = 50.0% EMPTY.
PIN 16 _, UART RECEIVER (Serial input is a TTL level input); for RS232
compatibility use MC1489 Line Receiver or equiv.
NOTE: 0 implies TLL LO level; 1 implies TTL HI level.

+- implies input; -> implies output.
A typical connection to a computer with an RS232 interface:
COMPUTER CODE-TO-SPEECH CHIP-SET

protective GND ++signal GND (Circuit ground).
signal GND ++signal GND (Circuit ground).
Clear To Send (CTS)+-Request To Send (RTS) = CTS256A-ALs's PIN 3
(BUSY$).
Transmitter's Line Driver ->CTS256A-AL2 UART's Line Receiver.
TABLE 2. NEW PARAMETERS.

X009 FF NUMBER OF BYTES OF 50% OF EXTERNAL INPUT
BUFFER (MSB)
XOOA FF NUMBER OF BYTES OF 50% OF EXTERNAL INPUT
BUFFER (LSB)
XOOB FF NUMBER OF BYTES OF 12.5% OF EXTERNAL INPUT
BUFFER (MSB)
xooc FF NUMBER OF BYTES OF 12.5% OF EXTERNAL INPUT
BUFFER (LSB)
XOOD FF EXTERNAL RAM START ADDRESS (MSB) see note 2.3
XOOE FF EXTERNAL RAM START ADDRESS (LSB) see note 2.3
XOOF FF EXTERNAL RAM END ADDRESS-100H (MSB) see note 2.3
X010 FF EXTERNAL RAM END ADDRESS-100H (LSB) see note 2.3
X011 FF EXTERNAL RAM START ADDRESS-1 (MSB) see note 2.3
X012 FF EXTERNAL RAM START ADDRESS-1 (LSB) see note 2.3
X013 FF EXTERNAL RAM END ADDRESS-FFH (MSB) see note 2.3
X014 FF EXTERNAL RAM END ADDRESS·FFH (LSB) see note 2.3
X015 FF EXTERNAL RAM END ADDRESS+ 1 (MSB) see note 2.3
X016 FF EXTERNAL RAM END ADDRESS+ 1 (LSB) see note 2.3
X017 FF ADDRESS DECODE OF SP0256A-AL2's ALD$ (MSB) see
note 2.4
X018 FF ADDRESS DECODE OF SP0256A-AL2's ALD$ (LSB) see note
2.4
X019 FF ADDRESS DECODE OF 74LS374 PARALLEL PORT LATCH
(MSB)
X01A FF ADDRESS DECODE OF 74LS374 PARALLEL PORT LATCH
(LSB)
X01B FF see note 2.1
X01C FF TOTAL NUMBER OF BYTES IN INPUT BUFFER (MSB)
X01D FF TOTAL NUMBER OF BYTES IN INPUT BUFFER (LSB)
X01E FF see note 2.1
X01F FF see note 2.1
X020 FF SERIAL PORT REGISTER (see table 5) see note 2.5
X021 FF SERIAL PORT CONTROL REGISTER (see table 6) see note
2.5
X022 FF SERIAL PORT TIMER DATA REGISTER (see table 6) see
note 2.5
L_ YOUR EXCEPTION-WORD OR USER EPROM CAN RESIDE ANY-

WHERE FROM 1000H TO EOOOH PROVIDING IT BEGINS ON A
4K BOUNDARY WHERE X= 1,2,3,4,5,6,7,8,9,A,B,C,D,or E. (The
least significant 3 nibbles of the address must remain as shown.)
81
CTS256AL2 276·1786
NOTE 2.1 THESE LOCATIONS MUST BE FF, (THEY ARE NOT USER
DEFINABLE).
NOTE 2.2 TO MAINTAIN ANY PARAMETER AT ITS DEFAULT VALUE,
LOAD THAT LOCATION WITH FFH.
NOTE 2.3 IF ANY OF THE EXTERNAL RAM BUFFER PARAMETERS
ARE REDEFINED HERE, ALL OF THEM MUST BE REDE-
FINED HERE.
NOTE 2.4 NO MATTER WHAT ADDRESS IS CHOSEN FOR ALD$, THAT
ADDRESS THRU THAT ADDRESS + 3FH IS RESERVED FOR
SP0256A-AL2 ADDRESSING.
NOTE 2.5 IF ANY OF THE SERIAL PORT PARAMETERS ARE REDE-
FINED HERE, ALL OF THEM MUST BE REDEFINED HERE.
NOTE 2.6 H , AS IN 100H REFERS TO HEXADECIMAL NOTATION.
NOTE 2.7 A NIBBLE IS HALF OF A BYTE, OR 4 BITS.
TABLE 3. SAMPLE OF ASSEMBLED ALPHABETIZED

EXCEPTION-WORD INDEX.
XOA3 Xl MSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "A"
XOA4 93 LSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "A"
BEGINNING WITH "B"
XOA6 A8 LSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "B"
BEGINNING WITH "C"
XOA8 A9 LSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "C"
BEGINNING WITH "D"
XOAA Bl LSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "D"
XOAB Xl MSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "E"
XOAC B2 LSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "E"
XOAD Xl MSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "F"
XOAE B3 LSB OF POfNTER TO START OF EXCEPTION-WORD
BEGINNING WITH "F"
XOAF Xl MSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "G"
XOBO B4 LSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "G"
XOBl Xl MSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "H"
XOB2 El LSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "H"
XOB3 X1 MSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH " I"
XOB4 E2 LSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "I"
XOB5 ' X2 MSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "J"
XOB6 OD LSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH ''J"
BEGINNING WITH "K"
XOB8 OE LSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH " K"
BEGINNING WITH "L"
XOBA OF LSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "L"
XOBB X2 MSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "M"
82
MJCROCOMPUTER (8-BIT)
CTS256AL2 276·1786
TABLE 3. (Cont'd)
XOBC lB LSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "M"
XOBD X2 MSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "N"
XOBE lC LSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "N"
XOBF X2 MSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "0"
xoco 1D LSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "0"
XOCl X2 MSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "P"
xocz lE LSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "P"
XOC3 X2 MSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH " Q"
XOC4 2D LSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "Q"
BEGINNING WITH "R"
XOC6 2E LSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "R"
BEGINNING WITH "S"
XOCB 2F LSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "S"
BEGINNING WITH "T"
XOCA 30 LSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "T"
XOCB X2 MSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "U"
xocc 3D LSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "U"
XOCD X2 MSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "V"
XOCE 5A I:SB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "V"
XOCF X2 MSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "W"
XODO 5B LSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "W"
XODl X2 MSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "X"
XOD2 64 LSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "X"
XOD3 X2 MSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "Y"
XOD4 65 LSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "Y"
XOD5 X2 MSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "Z"
XOD6 6F LSB OF POINTER TO START OF EXCEPTION-WORD
BEGINNING WITH "Z"
XOD7 X2 MSB OF POINTER TO START EXCEPTION-WORD
BEGINNING WITH "NUMBER OF PUNCTUATION"
XODB 70 LSB OF POINTER TO START EXCEPTION-WORD
L
BEGINNING WITH "NUMBER OF PUNCTUATION"
L The least significant nibble of the MSB and the entire LSB
address locations will vary with a different set of exception
words; X= 1,2,3,4,5,6,7,8,9,A,B,C,D,or E.
YOUR EXCEPTION-WORD EPROM CAN RESIDE ANYWHERE

FROM lOOOH TO EOOOH PROVIDING IT BEGINS ON A 4K
BOUNDARY WHERE X= 1,2,3,4,5,6,7,8,9,A,B,C,D,or E. (The least
significant 3 nibbles of the adaress must remain as shown.)
83
CTS256AL2 276·1786
TABLE 4. SAMPLE OF ASSEMBLED ENCODED EXCEPTION-WORDS

Xl93 13 6E Z4 AA:DB 19,110,36,185,19,90,11,1,33,19,0,18,15,0,1,65,34,39,Z0,141
Xl96 B9 13 5A OB 01 Zl 13 00 lZ OF
XlAO 00 01 41 ZZ Z7 14 8D
;<[ANDY]<= [AE NNl PAZ DDZ IY PAl DHl AX PAl PAZ GG3 RR2 EY TT2] ANDY-THE-GREAT
XlA7 FF DB Z55
XlA8 FF BB:DB Z55

.
XlA9 13 61 BO C: DB 19,97,176,33,106,ZO,l37;<[CAP]A= [KKl EY PP] CAPABILITY
XlAC Zl 6A 14 89
XlBO FF DB Z55
;
XlBl FF D: DB Z55
;
XlBZ FF E: DB Z55
;
XlB3 FF F: DB Z55
XlB4 13 E9 13 6: DB 19,Z33,19,74,7,11,51,6Z,O,lZ,ll,55,13,39,31,16,7,11,Z,141
X1B7 4A 07 OB 33 3E 00 OC OB 37 OD
XlClZ71Fl0070BOZBD
;<(GI]< = (JH EH NNl ERl EL PAl IM NNl SS TTZ RRZ UWZ MM EH NNl PA3 TTZ]
;GENERAL INSTRUMENT
X1C8 13 E9 ZD DB 19,Z33,45,33,41,44,19,74,7,11,51,6Z,O,lZ,l1,55,13,39,31,16,7,ll,Z,141
XlCB Zl Z9 ZC 13 4A 07 OB 33 3E 00
XlD5 OC OB 37 OD Z7 lF 10 07 OB OZ
XlDF 8D
;<[GI][MAIL< = [JH EH NNl ERl EL PAl IH NNl SS TTZ RRZ UWZ MM EH NNl PA3 TT2]
XlEO FF DB Z55
XlEl FF H: DB Z55
XlEZ 13 E4 13 I: DB 19,ZZ8,19,70,0,33,7,1l,Z,13,1Z,40,1Z,Z,4Z,Z0,37,15,139; < [ID] < =[AY PAl

X1E5 46 00 Zl 07 OB OZ OD OC ZB OC
XlEF OZ ZA 14 Z5 OF 8B
;DDZ EH NNl PA3 TTZ IH FF IH PA3 KKl EY SH AX NNl) IDENTIFICATION
X1F5 13 73 ZC DB 19,115,44,165,19,70,1,190;<(ISLE]< = [AY PAZ EL] ISLE
XlFB A5 13 46 01 BE
XlFD 13 73 ZC DB 19,115,44,33,46,164,19,70,0,45,Z6,ll,l,Zl,l; <[ISLAND]< = [AYPAZELAENNlDDl]
XZOO Zl ZE A4 13 46 00 ZD 1A OB 01
XZOA 15 01
XZOC FF DB Z55
XZOD FF J: DB Z55
XZOE FF
.
K: DB Z55
.
XZOF 13 69 36 L: DB 19,105,54,37,164,19,109,1Z,35,3,149; <[LIVED]<= [LL IH VV PA4 DDl] LIVED
XZ1Z Z5 A4 13 6D OC Z3 03 95
XZlA FF DB Z55
XZ1B FF M: DB Z55
XZlC FF N: DB Z55
XZlD FF 0: DB Z55
XZ1E 13 75 3Z P: DB 19,117,50,48,47,51,165,19,73,51,9,15,55,183;<[PURPOSE]< =[PPERlPPAXSSSS]

XZZl 30 ZF 33 A5 13 49 33 09 OF 37
XZZB B7
XZZC FF DB Z55
XZZD FF Q: DB Z55
XZZE FF R: DB Z55
XZZF FF
.
S: DB Z55
84
CTS256AL2 276-1786
TABLE 4. (Cont'd)
XZ30 13 6F 34 T: DB 19,111,5Z,33,172,19,77,53,13,0,15,190;<[TOTAL]< = [TTZ OW TTl PAl AXEL]
XZ33 Zl AC 13 40 35 OD 00 OF BE
XZ3C FF DB Z55
'
XZ3D 13 73 Z5 U: DB 19,115,37,50,41,164,19,113,ZZ,43,51,1,6,0,33,7,11,Z,13,1Z,40,1Z,Z,4Z,Z0,37
XZ40 3Z Z9 A4 13 71 16 ZB 33 01 06
XZ4A 00 Zl 07 OB OZ OD OC ZB OC OZ
XZ54 ZA 14 Z5
XZ57 OF BB DB 15,139;<[USERID]< = [YYl UMl ZZ ERl PAl AY PAl DDZ EH NNl PA3 TTZ IH FF IH
;PA3 KKl EY SH AX NNl]
XZ59 FF DB Z55
XZ5A FF
' DB Z55
V:
XZ5B 13 65 07 W: DB 19,101,7,50,165,110,19,180 ; <[WE'RE]= [WW IY ERZ] WE'RE

XZ5E 3Z A5 6E 13 B4
XZ63 FF DB Z55
XZ64 FF X: DB Z55
' DB 19,111,53,7,50,165,19,89,186
XZ65 13 6F 35 Y: ; <[YOU'RE]< = [YYZ OR] YOU'RE
XZ68 07 3Z A5 13 59 BA
XZ6E FF DB Z55
'
Z: DB Z55
XZ6F FF
'
XZ70 13 CF 13 NUMORPUN: DB 19,Z07,19,89,58,1,16,7,55,55,1Z,1,10,0,Z,4Z,Z6
XZ73 59 3A 01 10 07 37 37 OC 01 OA
XZ7D 00 OZ ZA lA
XZ81 OB 01 3F DB 11, 1,63, 19,0,55,55,Z,9,53,Z,4Z,7,11,0,46, 1Z,Z9,0, 18, 15,0,Z,13, 15,Z,50
XZ84 13 00 37 37 OZ 09 35 OZ ZA 07
XZBE OB 00 ZE OC 10 00 lZ OF 00 OZ
XZ9B OD OF OZ 3Z
XZ9C 00 OF Z3 · DB 0,15,35,0,ZO,O,Z,4Z,19,1Z8
XZ9F 00 14 00 OZ ZA 13 80
;<[/]< = [YYl OR PAZ MM EH SS SS IH PAZ JH PAl PA3 KKl AE NNl PAl PAZ BBZ IY
;PAl SS SS PA3 PP OW PA3 KKl EM NNl PAl WW IH TH PAl DHl AX PAl PA3
;TTZ AX PA3 CH PAl AX VV PAlEY PAl PAZ KKl EY PAl]YOU'RE MESSAGE CAN BE SPOKEN
;WITH THE TOUCH OF A KEY
XZA6 C6 5A OB DB 198,90,ll,Zl,lZ8 ;[&] = [AE NNl DOl PAl] AND

XZA915 80
XZAB FF DB Z55 ;MUST END EACH CATEGORY WITH [ ].
L WHERE X= l,Z,3,4,5,6,7,8,9,A,B,C,D, or E. (The least significant 3 nibbles of the address

will vary with a different set of exception words.)
85
MICROCOMPUTER (8·BIT)
CTS256AL2 276·1786
TABLE 5. SERI.t}~lORT MODE REGISTER u
l4t>
r-MSIY-
17 I 1.J JJ q 7 ., 5
LSB -
7 6 5 4 3 2 1 0
l
STOP SIO PEVEN PEN CHAR1 CHARO COMM MULTI
I I L 0 =MOTOROLA PROTOCOL
1 = INTEL PROTOCOL
0 = ISOSYNCHRONOUS COMMUNICATION
1 =ASYNCHRONOUS COMMUNICATION
00 = 5 BITS/CHARACTER
'- 11 = 8 BITS/CHARACTER
1 =PARITY ENABLED
.._ 0 =PARITY DISABLED
1 = EVEN PARITY
'- 0 =ODD PARITY
0 =SERIAL I/0 MODE

- 1 = COMMUNICATION MODE
0 =ONE STOP BIT

'- 1 =TWO STOP BITS
FOR TYPICAL APPLICATIONS USE: MOTOROLA PROTOCOL, ASYNCHRONOUS COMMUNICATION,

7 BITS/CHARACTER, and COMMUNICATION MODE; THE NUMBER OF STOP BITS AND PARITY
MODE REMAIN UP TO THE USER.
TABLE 6. SERIAL PORT CONTROL REGISTER I TIMER REGISTER

Asynchronous Baud Rate = 2.5MH:
64(PL + 1) (TL + 1)
Isosynchronous Baud Rate = 2.5 MH:
-------
4(PL + 1) (TL + 1)
where: PL = prescale latch value

TL = timer latch value
Example: To program the serial port to operate at 300 baud in the asyn·
chronous mode, the prescaler value is set to 0, and the timer
latch value to 81H.
Y . , T PRESCALE LATCH VALUE (PL)
2 I 1 I L~B -
TIMER LATCH VALUE (TL)
86
CTS256AL2 276·1786
TABLE 7. ASCII CHARACTER SET ENCODED VALUES

LETTER ENCODED VALUE (shown in Hexadecimal). LETTER ENCODED VALUE (shown in Hexadecimal).
A 21 N 2E
B 22 0 2F
c 23 p 30
D 24 Q 31
E 25 R 32
F 26 s 33
G 27 T 34
H 28 u 35
I 29 v 36
J 2A w 37
K 2B X 38
L 2C y 39
M 2D z 3A
TABLE 8. ALLOPHpNE ADDRESS ENCODED VALUES (shown in Hexdecimal).

ENCODED SAMPLE ENCODED SAMPLE
VALUE ALLPHONE WORD DURATION (as) VALUE ALLPHONE WORD DURATION (as)
00 PAl PAUSE 10 20 AW OUt ~50
01 PA2 PAUSE 30 21 DD2 Do 80
02 PA3 PAUSE 50 22 GG3 wiG 120
03 PA4 PAUSE 100 23 vv Vest 130
04 PA5 PAUSE 200 24 GG1 Guest 80
05 OY bOY 290 25 SH SHip 120
06 AY skY 170 26 ZH aZUre 130
07 EH End 50 27 RR2 bRain 80
08 KK3 Coab 80 28 FF Food 110
09 pp Pow 150 29 KK2 sKy 140
OA JH dodGe 400 2A KK1 Can't 120
OB NN1 thiN 170 2B zz Zoo 150
oc IH sit 50 2C NG aNchor 200
OD TT2 To 100 2D LL Lake 80
OE RR1 Rural 130 2E ww Wool 140
OF AX sUceed 50 2F XR repaiR 250
10 MM Milk 180 30 WH WHig 150
11 TTl parT 80 31 YY1 Yes 90
12 DH1 THey 140 32 CH CHurch 150
13 IY sEE 170 33 ER1 fiR 110
14 EY bEige 200 34 ER2 fiR 210
15 DD1 coulD 50 35 ow bEAU 170
16 UW1 tO 60 36 DH2 THey 180
17 AO OUght 70 37 ss veST 60
18 AA hOt 60 38 NN2 No 140
19 YY2 Yes 130 39 HH2 Hoe 130
1A AE hAt 80 3A OR stORe 240
1B HH1 He 90 3B AR alARe 200
1C BB1 Business 40 3C YR cleAR 250
1D TH THin 130 3D GG2 Got 80
1E UN bOOk 70 3E EL saddLE 140
1F UW2 fOOd 170 3F BB2 Business 60
TABLE 9. PARALLEL PORT TIMING REQUIREMENTS:

SETUP TIME, BEFORE DATA CLOCK LO TO HI TRANSITION: MIN. 20 nS. HOLD TIME, BEFORE DATA
CLOCK LO TO HI TRANSITION: MIN. 10 nS. WIDTH OF CLOCK LO: MIN. 500 nS.
HOLD OFF TIME, FROM DATA STROBE HI TO LOW TO HI, UNTIL NEXT DATA STROBE HI TO LOW: MIN.
450 uS. ·
NOTE: The addition of an 74LS74 Flip-Flop as shown on the schematic can be used for parallel port latch
handshaking using the Active-LO LATCH-BUSY$ output. LATCH-BUSY$ is LO when the latch is full,
and it is HI when the latch is empty and available for the next character to be strobed in.
87
CTS256AL2 276·1786
APPENDIX-A
Exception-Word Eprom Map (For use without USER eprom present)
NOTE: ENCAPSULATED SEQUENCES ARE USER-DEFINED, REFER TABLES 2,3, AND 4.
XOOO 80 48 28 58 85 EO 35 EO 31,FF FF FF FF FF FF FF +-sample

NEW PARAMETERS.
X010 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF (see table 2).
X020 FF FF FFI1E 1F 20 21 28 29 24 25 22 23 2A 2B 26 +-NEW PARAMETER

INITIALIZATION
X030 27 2C 2D 2E 2F 32 33 34 35 36 EO 65 78 02 31 BE ROUTINE.
X040 F1 43 C5 AA XO 09 2D FF E2 1E B8 AA XO 23 D5 12
X050 DO 13 B9 9B 13 C3 AA XO 09 2D FF E2 OB B8 AA XO The MSnibble of the following locations
X060 23 D5 12 DO 13 B9 9B 13 5D 16 E6 E9 C3 AA XO 09 from the NEW PARAMETER INITIALIZATION
X070 2D FF E2 14 A2 40 11 82 11 A2 15 11 C3 AAXO 09 ROUTINE are user defined also:
X080 82 15 C3 AA XO 09 82 14 98 29 03 98 2B 07 22 20 X044,X04C,X057,X05F,X06E,X07E,and X084;
X090 9B 03 BE F7 2B 9B 03 05 98 07 09 98 03 19 8C F1 where X= 1,2,3,4,5,6,7,8,9,A,B,C,D,or E.
XOAO 00 EO 361 X1 93 X1 AB X1 A9 X1 B1 X1 B2 X1 B3 X1 +-sample

ALPHABETIZED
XOBO B4 X1 E1 X1 E2 X2 OD X2 OE X2 OF X2 1B X2 1C X2 EXCEPTION-W.ORD
XOCO 1D X2 1E X2 2D X2 2E X2 2F X2 30 X2 3D X2 5A X2 INDEX, where X= 1,2,3,4,5,6,7,8,9,A,B,C,D,or E.
(see table 3).
XODO 5B X2 64 X2 65 X2 6F X2 701 DB 02 D8 03 98 03 11 +--EXCEPTION-WORD
ROUTINE.
XOEO BE F7 4B 8E F7 OF 77 01 OA 05 74 80 OB EO 03 73
XOFO 7F OB BE F3 AF 76 20 OA OE 52 34 AA XO A3 DO 14 The MSnibble of the following locations
X100 AAXO A4 DO 15 EO OF C5 2A 41 2C 02 AAXO A3 DO from the EXCEPTION-WORD ROUTINE are user
X110 14 AAXO A4 DO 15 52 01 BE F4 88 8E F4 C2 76 10 defined also: XOFC,X101,X10D,and X112;
X120 OA 4D 2D FF E2 60 98 11 1D 73 BF OA BE F5 64 76 where X= 1,2,3,4,5,6,7,8,9,A,B,C,D,or E.
X130 10 OA 3C BE F4 7E 74 40 OA 8E F5 64 76 10 OA 42
X140 48 37 34 79 00 35 D5 37 73 FD OB 52 02 8E F4 88
X150 8E F4 9E 98 OF 03 98 03 11 8E F7 4B 77 80 OB OA
X160 DB 39 8E F3 47 C9 C9 8C F1 36 C9 C9 8C F3 F4 D3
X170 15 E7 02 D3 14 52 02 BE F4 88 72 01 37 73 FD OB
X180 EO 99 52 03 EO F1 D9 03 D9 02 D5 37 73 FD OB BC
X190 F3 EE FFJ13 6E 24 B9 13 5A OB 01 21 13 00 12 OF +-sample

ENCODED
X1AO 00 01 41 22 27 14 8D FF FF 13 61 BO 21 6A 14 89 EXCEPTION-WORDS.
X1BO FF FF FF FF 13 E9 13 4A 07 OB 33 3E 00 OC OB 37 (see table 4).
X1CO OD 27 1F 10 07 OB 02 BD 13 E9 2D 21 29 2C 13 4A
X1DO 07 OB 33 3E 00 OC OB 37 OD 27 1F 10 07 OB 02 8D
X1EO FF FF 13 E4 13 46 00 21 07 OB 02 OD OC 28 OC 02
X1FO 2A 14 25 OF BB 13 73 2C A5 13 46 01 BE 13 73 2C (see APPENDIX-C
X200 21 2E A4 13 46 00 2D 1A OB 01 15 01 FF FF FF 13 for discussion
X210 69 36 25 A4 13 6D OC 23 03 95 FF FF FF FF 13 75 of encoding scheme.)
X220 32 30 2F 33 A5 13 49 33 09 OF 37 B7 FF FF FF FF
X230 13 6F 34 21 AC 13 4D 35 OD 00 OF BE FF 13 73 25
X240 32 29 A4 13 71 16 2B 33 01 06 00 21 07 OB 02 OD
X250 OC 28 OC 02 2A 14 25 OF BB FF FF 13 65 07 32 A5
X260 6E 13 B4 FF FF 13 6F 35 07 32 A5 13 59 BA FF FF
X270 13 CF 13 59 3A 01 10 07 37 37 OC 01 OA 00 02 2A
X280 1A OB 01 3F 13 00 37 37 02 09 35 02 2A 07 OB 00
X290 2E OC 1D 00 12 OF 00 02 OD OF 02 32 00 OF 23 00
X2AO 14 00 02 2A 13 80 C6 5A OB 15 80 FF
I lo l1 l2 13 14 15 16 17 Is 19 lA IB lc In IE IF
LYOUR EXCEPTION-WORD EPROM CAN RESIDE ANYWHERE FROM
1000H TO EOOOH, PROVIDING IT BEGINS ON A 4K BOUNDARY WHERE X= 1,2,3,4,5,6,7,8,9,A,B,C,D,or E.
88
CTS256AL2 276·1786
APPENDIX·B
Exception-Word Eprom Map (For use without USER eprom present)
NOTE: ENCAPSULATED SEQUENCES ARE USER-DEFINED, REFER TABLES 2,3, AND 4.
xooo 80 48 28 58 85 EO 35 EO 31 IFF FF FF FF FF FF FF +-sample

NEW PARAMETERS.
X020 FF FF FF,1E 1F 20 21 28 29 24 25 22 23 2A 2B 26 +-NEW PARAMETER

INITIALIZATION
X030 27 2C 2D 2E 2F 32 33 34 35 36 EO 65 78 02 31 BE ROUTINE .
X040 F1 43 C5 AA XO 09 2D FF E2 1E BB AA XO 23 D5 12 The MSnibble of the following locataions
X050 DO 13 B9 9B 13 C3 AA XO 09 2D FF E2 OB B8 AA XO from the NEW PARAMETER INITIALIZATION
X060 23 D5 12 DO 13 B9 9B 13 5D 16 E6 E9 C3 AA XO 09 ROUTINE are user defined also:
X070 2D FF E2 14 A2 40 11 82 11 A2 15 11 C3 AAXO 09 X044,X04C,X057,X05F,X06E,X07E,and X084;
XOBO 82 15 C3 AA XO 09 82 14 98 29 03 98 2B 07 22 20 where X= 1,2,3,4,5,6,7,8,9,A,B,C,D,or E.
X090 9B 03 BE F7 2B 9B 03 05 98 07 09 98 03 19 BC MS +-(see note 1 below).
XOAO LS EO 361 X1 93 X1 AB X1 A9 X1 B1 X1 B2 X1 B3 X1 +-sample

ALPHABETIZED
XOBO B4 X1 E1 X1 E2 X2 OD X2 OE X2 OF X2 1B X2 1C X2 EXCEPTION-WORD
XOCO 1D X2 1E X2 2D X2 2E X2 2F X2 30 X2 3D X2 5A X2 INDEX, where X= 1,2,3,4,5,6,7,8,9,A,B,C,D,or E.
(see table 3).
XODO 5B 82 64 82 65 82 6F 82 70 I DB 02 DB 03 98 03 11 +-EXCEPTION-WORD
ROUTINE.
XOEO BE F7 4B BE F7 OF 77 01 OA 05 74 80 OB EO 03 73
XOFO 7F OB BE F3 AF 76 20 OA OE 52 34 AA 80 A3 DO 14 The MSnibble of the following locations
X100 AA80 A4 DO 15 EO OF C5 2A 41 2C 02 AA80 A3 DO from the EXCEPTION-WORD ROUTINE are user
X110 14 AABO A4 DO 15 52 01 BE F4 88 BE F4 C2 76 10 defined also: XOFC,X101,X10D,and X112;
X1~0 OA 4D 2D FF E2 60 98 11 1D 73 BF OA BE F5 64 76 where X= 1,2,3,4,5,6,7,8,9,A,B,C,D,or E.
X130 10 OA 3C BE F4 7E 74 40 OA BE F5 64 76 10 OA 42
X140 48 37 34 79 00 33 D5 37 73 FD OB 52 02 BE F4 88
X150 BE F4 9E 98 OF 03 98 03 11 BE F7 4B 77 80 OB OA
X160 DB 39 BE F3 47 C9 C9 BC F1 36 C9 C9 BC F3 F4 D3
X170 15 E7 02 D3 14 52 02 BE F4 88 72 01 37 73 FD OB
X180 EO 99 52 03 EO F1 D9 03 D9 02 D5 37 73 FD OB BC
X190 F3 EE FF 113 6E 24 B9 15 5A OB 01 21 13 00 12 OF +-sample

ENCODED
X1AO 00 01 41 22 27 14 BD FF FF 13 61 BO 21 6A 14 89 EXCEPTION-WORDS.
X1BO FF FF FF FF 13 E9 13 4A 07 OB 33 3E 00 OC OB 37 (see table 4).
X1CO OD 27 1F 10 07 OB 02 BD 13 E9 2D 21 29 2C 13 4A
X1DO 07 OB 33 3E 00 OC OB 37 OD 27 1F 10 07 OB 02 BD
X1EO FF FF 13 E4 13 46 00 21 07 OB 02 OD OC 2B OC 02
X1FO 2A 14 25 OF BB 13 73 2C A5 13 46 01 BE 13 73 2C
X200 21 2E A4 13 46 00 2D 1A OB 01 15 01 FF FF FF 13 (see APPENDIX-C
X210 69 36 25 A4 13 6D OC 23 03 95 FF FF FF FF 13 75 for discussion
X220 32 30 2F 33 A5 13 49 33 09 OF 37 B7 FF FF FF FF of encoding scheme).
X230 13 6F 34 21 AC 13 4D 35 OD 00 OF BE FF 13 73 25
X240 32 29 A4 13 71 16 2B 33 01 06 00 21 07 OB 02 OD
X250 OC 28 OC 02 2A 14 25 OF BB FF FF 13 65 07 32 A5
X260 6E 13 B4 FF FF 13 6F 35 07 32 A5 13 59 BA FF FF
X270 13 CF 13 59 3A 01 10 07 37 37 OC 01 OA 00 02 2A
X280 1A OB 01 3F 13 00 37 37 02 09 35 02 2A 07 OB 00
X290 2E OC 1D 00 12 OF 00 02 OD OF 02 32 00 OF 23 00
X2AO 14 00 02 2A 13 80 C6 5A OB 15 80 FF
NOTE: 1. APPENDIX·B is the same as APPENDIX-A, except for two address. These are X09F and XOAO (MSB and LSB respec-
tively, labeled MS and LS above). Place the origin of the MAIN-CONTROL-PROGRAM (see APPENDIX-F) in these loca-
tions so that program control will transfer to the user's code at the appropriate time.
89
CTS256AL2 276-1786
APPENDIX-C
Exception-Word Encoding Scheme
To store a unique word or symbol and its corresponding allophone address string in an efficient and flexible manner, the
following encoding format was derived:
<[encoded word or symbol]< = [encoded allophone address(es)]
where: < equals 13H.

[ equals 40H.
] equals 80H.
The first and last byte is 13H. This informs the code-to-speech algorithm that the word or symbol is not a prefix or suffix.
If the word or symbol is an individual letter, then the representation of it between the brackets is an FFH; this includes the value of
the left and right brackets.
Otherwise:
(1) The first letter in the word or symbol is always to be ignored.
(2) The next letter in the word is represented by the value of the letter from TABLE-7, plus the value of the left bracket "[" which is
40H.
(3) The following letter(s), if and only if it is not the last letter in the word or symbol, is represented solely by its value from
TABLE-7.
(4) The last letter in the word or symbol is represented by the value of the letter from TABLE-7, plus the value of the right bracket
"]" which is SOH.
The allophone address string is encoded in a similar manner:
If only one allophone is used for the pronunciation, it is represented by its value from T ABLE-6, plus the value of the right " ["
and left "]" brackets which are 40H and SOH respectively.
Otherwise:
(1) The first allophone is represented by its value from TABLE-8, plus the value of the left bracket "[" which is 40H.
(2) The following allophone(s), if and only if it is not the last allophone in the string, is represented by its value from TABLE-8.
(3) The last allophone is represented by its value from T ABLE-8 plus the·value of the right bracket "]" which is SOH.
Example: To encode "Au" to pronounce as "GOLD"

<[Au]< = [GG2 OW LL DD1]
13,F5,13, 7D, 35,2D,95 +-This line is ready to store in EXCEPTION-WORD epros under the "A" category.
t (The encoded string is shown in Hexadecimal notation.)
-Remember, throw away the first letter (in. this case an "A"), then find the value of the next letter in TABLE-7 and
add 40H plus SOH to it so as to represent the left "[" and right "]" brackets.
APPENDIX-D
User Eprom Map (For use without EXCEPTION-WORD eprom)
NOTE: ENCAPSULATED SEQUENCES ARE USER-DEFII'{ED, REFER TABLES 2,3, AND 4.
XOOO 80 48 28 58 85 Eo 35 EO 311 FF FF FF FF FF FF FF <-sample

NEW PARAMETERS.
X020 FF FF FFI1E 1F 20 21 28 29 24 25 22 23 2A 2B 26 +-NEW PARAMETER

INITIALIZATION
X030 27 2C 2D 2E 2F 32 33 34 35 36 EO 65 78 02 31 BE ROUTINE.
X040 F1 43 C5 AAXO 09 2D FF E2 1E B8 AAXO 23 D5 12 The MSnibble of the following locations
X050 DO 13 B9 9B 13 C3 AAXO 09 2D FF E2 OB B8 AAXO from the NEW PARAMETER INITIALIZATION
X060 23 D5 12 DO 13 B9 9B 13 5D 16 E6 E9 C3 AAXO 09 ROUTINE are user defined also:
X070 2D FF E2 14 A2 40 11 82 11 A2 15 11 C3 AAXO 09 X044,X04C,X057 ,X05F ,X06E,X07E,and X084;
X080 82 15 C3 AAXO 09 82 14 98 29 03 98 2B 07 22 20 where X= 1,2,3,4,5,6,7,8,9,A,B,C,D,or E.
X090 9B 03 BE F7 2B 9B 03 05 98 07 09 98 03 19 8C MS <-(see note A on following page).
90
MICROCOMPUTER ( 8-BIT)
CTS256AL2 276-1786
APPENDIX-D (Cont'd)
XOAO LS 8C F3 F4 , . . . - - - - - - - - - - - - - - - - - ,
....------'1 User code may start at XOA4,
Ibut must contain the MAIN-CONTROL-PROGRAM
somewhere within, refer to APPENDIX·:f.
NOTE A. Place the immediate address of the origin of the MAIN-CONTROL-PROGRAM (see APPENDIX-F) in these locations; so
that program control will transfer to the user's code at the appropriate time.
APPENDIX-E
USER EPROM MAP (For use with EXCEPTION-WORD eprom)
NOTE 1. Contains no reserved locations, except for the MAIN-CONTROL-PROGRAM. (See APPENDIX-F).
NOTE 2. A user's code does not have to reside in a second eprom (USER eprom). It may reside in an unused portion of an
EXCEPTION-WORD eprom which is for use where "USER eprom is present". Refer APPENDIX-B.
APPENDIX-F .
USER's MAIN CONTROL PROGRAM (For residency anywhere within USER eprom).
NOTE: ENCAPSULATED AREAS ARE USER DEFINED UNLESS OTHERWISE NOTED.
FlAC= AUDIBLE EQU OFlACH ;<--

F3E7 = GISPEECH EQU OF3E7H ;< - THESE ARE ADDRESS VECTORS WITHIN
F1E2 = SAVE EQU OF1E2H ; < - - THE MASKED CODE-TO-SPEECH ALGORITHM.
FlFO = ESCAPE EQU OFlFOH ;<--
OOOB = F2 EQU Rll
0002 = FlHI EQU R2
0003 = FlLO EQU R3
0004 = RlHI EQU R4
0005 = RlLO EQU R5
0007 = F2LO EQU R7
0009 = R2LO EQU R9
0038 = WORDCNTH EQU R56
0039 = WORDCNTL EQU R57
0032 = BUFBVALU EQU R50
0000 = IOCNTO EQU PO
9000 ORG > 9000 ;This is the origin of the Main Control Program which is defined by the user.
;Here it is arbitrarily chosen to be 9000H. Remember to place this immediate
;address in the "MS","LS" locations of the EXCEPTION-WORD eprom ("for use
;with USER eprom"), see APPENDIX-B. (MS = MSB = 90 and the LS = LSB = 00 in
;this example.)
9000 BEFlAC MESSAGE: CALL @AUDIBLE
+ - - - - - - - THIS ENCAPSULATED AREA IS NOT USER DEFINED - - - - - - - - - +
I The following two lines are placed here only if the user code wishes to gain I
I access to the serial port. I (The XXXX XXXX here does
xxxxxxxx ANDP % > FE,IOCNTl ;DISABLE INTERRUPT-4 (SERIAL not have the same meaning
PORT). as the X from the previous
appendices and tables.)
xxxxxxxx ANDP %FE,PORTB ;SET BUSY* LO.
+------------------------------------------------+
9003 EOOE JMP ANYSTART
9005 BC9046 CRSTART: BR @USERCODE

L.....-------...1
I ;THE BRANCH ADDRESS BELOW IS USER DEFINED.
;AFTER INITIALIZATION OR AFTER PROCESSING AND
;SPEAKING WHAT HAS BEEN LOADED INTO THE INPUT
;BUFFER CONTROL TRANSFERS TO THE USER CODE VIA THIS
;BRANCH INSTRUCTION.
91
CTS256AL2 276-1786
APPENDIX-F (Cont'd)
900B 76010B07 SPEAK: BTJO %>0l,F2,ANYSTART
900C 73EFOB AND%>EF,F2
900F 77100BFC CRWAIT: BTJZ %10,F2,CRWAIT
9013 4D0305 ANYSTART: CMP FlLO,RlLO
9016 E607 JNE HOLEWORD
9018 4D0204 CMP FlHI,RlHI
901B E602 JNE HOLEWORD
901D EOE6 JMPCRSTART
901F 7D0038 HOLEWORD:CMP o/o > OO,WORDCNTH
9022 E605 JNE BFULTEST
9024 7D0039 CMP %>00,WORDCNTL
9027 E2F6 JEQ HOLEWORD
9029 770BOB09 BFULTEST: BTJZ o/o > 08,F2,PROCESS
902D 7D0132 LOCKUP: CMP %>01,BUFBVALU
9030 E211 JEQ ESC
9032 760BOBFC BFULHOLD: BTJO o/o > 08,F2,BFULHOLD
9036 BEF3D7 PROCESS: CALL @GISPEECH
9039 4D0709 MAINROUT: CMP F2LO,R2LO
903C E205 JEQ ANYSTART
903E A40100 DRP %>01,10CNTO
9041 EODO JMP ANYSTART
9043 BCFlFO ESC: BR @ESCAPE
9046 00 USERCODE: NOP ;FROM THIS POINT IT IS THE USER CODES RESPONSIBILITY
;TO EXECUTE ITS OWN CODE OR TO LOAD A CHARACTER
;STRING INTO THE INPUT BUFFER.
;THE TWO EXAMPLES SHOWN BELOW DEMONSTRATE THE
;RECOMMENDED SEQUENCE OF EVENTS FOR EACH MODE.
;MODE 1 IS USED WHEN THE USER CODE HAS PREVIOUSLY
;PREPARED THE CHARACTER STRING IT WISHES TO HAVE
;SPOKEN; MODE 2 IS USED WHEN THE USER CODE WISHES
;TO EXECUTE ANYTHING ELSE.
IMODEl: I '
;LOADING
'
INPUT BUFFER OF CODE-TO-SPEECH ALGORITHM:
;ACCUMULATOR AND STATUS REGISTER ARE TO BE SAVED.

;NO OTHER REGISTER IS TO BE MODIFIED.
;Loading a character string is accomplished
;by placing each character into the Accumulator and
;then using CALL @SAVE to load it into the input
;buffer. Remember to end each word or phrase with a
;delimeter. Restore the Accumulator and the Status Registers. Call @SPEAK to
;process
;and speak the word(s) or phrase(s) that were loaded.
NOTE: Once "SPEAK" is initiated, control does ' not return to the USERCODE until the last word or phrase that is in the input
buffer has been processed by the code-to-speech algorithm. NOTE: Because of masked code-to-speech restrictions, the USER can
not intercept input from the serial port while speech processing is in progress. During this interval, handshaking (BUSY*) shall
hold off additional serial communication. This is accomplished by the two encapsulated lines shown above.
'
;THE FOLLOWING EXAMPLE WILL LOAD THE LETTER "A" AND
;SPEAK IT:
9047 OE PUSH ST ;SAVE CONTENTS OF STATUS REGISTER.

9048 B8 PUSH A ;SAVE CONTENTS OF ACCUMULATOR.
9049 2241 MOV %>4l,A ;MOVE 41H (which is ASCII "A") into the ACCUMULATOR.
904B 8EF1E2 CALL @SAVE ;LOAD THE ASCII "A" INTO THE INPUT BUFFER.
904E 222D MOV o/o > OD,A ;MOVE ODH (which is a carriage return).
9050 BEF1E2 CALL @SAVE ;LOAD THE DELIMETER INTO THE INPUT BUFFER.
9053 B9 POPA ;RECOVER CONTENTS OF ACCUMULATOR.
9054 08 POPST ;RECOVER CONTENTS OF STATUS REGISTER.
9055 8C900B BR @SPEAK ;TRANSFER CONTROL TO THE MAIN-CONTROL-PROGRAM WHICH
;WILL ACCESS THE CODE-TO-SPEECH ALGORITHM; AFTER WHICH

;THE CONTROL WILL RETURN TO THE "BR @ USERCODE" INSTRUCTION
LOCATION.
92
CTS256AL2 276-1786
APPENDIX-F (Cont'd)
9058 00 IMODE2: NOP I .

;The following is the recommended
;sequence of events necessary for the user's code
;to do anything else (except for loading the input
;buffer as described under MODE 1.)
.
;SAVE STATUS REGISTER
;SAVE REGISTER 0 THRU 39H (EXTERNAL-RAM MODE), along with 3AH thru
;current Stack Pointer.
;OR, SAVE REGISTER 0 THRU 7FH (INTERNAL-RAM MODE).
;(DO NOT USE PUSH INSTRUCTIONS TO SAVE THE REGISTERS BECAUSE
;THE STACK IS NOT LARGE ENOUGH, INSTEAD
;BLOCK MOVE THE RESPECTIVE REGISTER CONTENTS INTO
;EXTERNAL-USER-RAM .
.
;USER DEFINED CODE GOES HERE NEXT .
.
;(TO READ THE SERIAL PORT, SEE THE EXAMPLE SEQUENCE BELOW) .
.
;THEN RECOVER RESPECTIVE REGISTERS.
;RECOVER STATUS REGISTER.
;BRANCH TO MODE 1, OR BRANCH TO OTHER USER CODE such as the
;example shown below
;for reading the serial port.
;The following is the recommended sequence of events necessary
;for the user's code to obtain input from the serial port:
LOOP: DRP % > 01,IOCNT1

.
;ENABLE INTERRUPT-4 (SERIAL PORT) BECAUSE WANT TO RECEIVE SERIAL
;INPUT.
DRP %>01,PORTB ;SET BUSY$ HI.
IDLE ;WAIT HERE FOR SERIAL INTERRUPT TO OCCUR AND TO BE SERVICED.
ANDP % > FE,IOCNTl ;DISABLE INTERRUPT-4 (SERIAL PORT).
.
;THE CHARACTER RECEIVED BY SERIAL PORT IS IN THE ACCUMULATOR,
;SO THE USER MAY EVALUATE IT HERE .
MOV%>08,A
.
;LOAD A "BACKSPACE" INTO ACCUMULATOR IN ORDER TO TELL
CALL @SAVE ;THE CODE-TO-SPEECH INPUT BUFFER TO IGNORE THE CHARACTER
;WHICH ARRIVED VIA THE SERIAL PORT.
;IF USER WANTS ADDITIONAL CHARACTERS FROM THE SERIAL PORT TO
;EVALUATE:
;JUMP TO LOOP TO WAIT FOR NEXT SERIAL PORT INTERRUPT (JMP LOOP) .
.
;OTHERWISE: ENABLE INTERRUPT-4 (DRP %>01,IOCNT1), SET BUSY$ LO
;(ANDP %>FE,PORTB),
;THEN FALL THRU TO REST OF USER CODE.
NOTE: To successfully incorporate a USER program with the code-to-speech algorithm requires a thorough understanding of the
concepts described in this application note, and an in-depth working knowledge of PIC7001 assembly language.
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N-CHANNEL MOS (AUDIO)
SP0256 SPEECH PROCESSOR

276-1784
GENERAL DESCRIPTION
The SP0256 (Speech Processor) is a single chip N-Channel MOS LSI device
that is able, using its stored program to synthesize speech or complex sounds.
PIN CONNECTION
The achievable output is equivalent to a flat frequency response ranging TOP VIEW
from 0 to 5KHz, a dynamic range of 42dB, and a signal to noise ratio of Yss
approximately 35 dB.
The SP0256 incorporates four basic functions:
A. A software programable digital filter that can be made to model a VOCAL
\ ROM DISABLE
TRACT.
B. A 16K ROM which stores both data and instructions (THE PROGRAM). ~ C1
C. A MICROCONTROLLER which controls the data flow from the ROM to
the digital filter, the assembly of the "word settings" necessary for linking \ C2
speech elements together, and the amplitude and pitch information to \ C3

excite the digital filter.
D. A PULSE WIDTH MODULATOR that creates a digital output which is Yoo
converted to an analog signal when filtered by an external low pass filter.
\ SBY
FEATURES
• Natural Speech
• Wide Operating Voltage
• Simple Interface to Most Microcomputers or Microprocessors
• Supports L.P.C. Synthesis: Formant Synthesis: Allophone
Synthesis

Supply Voltage (Vnn) . .. . ... . ... . .. .... . . . .... . . . .. . . . .. . .. . .. . .. . .. . 7 V
(Vm) . ... . . .. . . . .. . . . ... . . .. ... .. . . . . .. .. . .. . ...... .. . 7 V
All Pins With Respect to Vss) . . ... . ..... .... . . . . . .. . . .. . . .. ... -0.3 To 8 V
Supply Current (Inn) !Vnt. Vnn=7V)
(Reset and SBY Reset High) ... . .. .. .. .... . .. . . . ... .. 90 rnA
Supply Current (Im !Vm. Vnn=7V)
(Reset and SBY Reset High) ... . . . ... ......._.. .. . . . . . 21 rnA
Storage Temperature Range . . . . . .. ... .... . . . .... . . ... ... -25°C To l25°C
Operating Temperature Range . . .. . . . . . . ...... . ... ... . . . . . ... o•c To 70°C
STANDARD CONDITIONS
Clock-Crystal Frequency 3.120 MHz
TYPICAL APPLICATION +5V

+SV
MICROCOMPUTER INTERFACE 10,11,13 7 AUDIO AMP

14-18 ,..-,J--,J--:!-;,..,
OUTPUT 1-----''\ 33K
LINES A8-A1
OIGITALI-:.,--'Iv-.-T-'W-~~1---t
OUT 24
OUTPUT!-----! Alii
0.022p.~
SP0256 10K
INPUT I+-----1SBY
INPUTI(;:-----!Dffi
+SV
96
SP0256 276-1784
ALLOPHONE USAGE WITH A MICROPROCESSOR

The SP0256 requires the use of a processor to concatenate the speech
sounds to form words.
The SP0256 is controlled using the address pins [Al-A8), ALD [Address
Load), and SE [Strobe Enable). The object for controlling the chip is to load an
address into it which contains the desired allophone. The speech data for the
allophone set is contained within the internal 16 K ROM of the SP0256.
This particular application [Allophone Set) requires only six address pins
[Al-A6) to address all the 59 allophones plus five pauses, a total of 64locations.
For simplicity, since only six address pins are needed to address the 64 loca-
tions, pins A7 and A8 can be tied low [to ground) and now any further refer-
ences to the address bus will include A1-A6 and A7=A8=0.
There are two modes available for loading an address into the chip. SE
[Strobe Enable) controls the mode that will be used.
Mode 0. [SE=O) will latch in an address when any one or more of the
address pins makes a low to high transition. For example, to load the address
one [1), A2 to A6=0 and Al is pulsed high. To load the address twelve (12
octal), Al=A3=A5=A6=0, A2 and A4 are pulsed high simultaneously. [Note
that an address of zero cannot be loaded using this mode).
Mode 1 [SE=l) will latch in an address using the ALD pin. First, setup the
desired address on the address bus [Al=A6) and then pulse ALD low. Any
address can be loaded using this mode, but certain setup and hold times are
required.
Two microprocessor interface pins are available for quick loading of
addresses. They are LRQ and SBY. LRQ [Load Request) tells the processor
when the input buffer is full. SBY [Stand By) tells the processor that the chip
has stopped talking and np new address has been loaded. Either interface pin
can be used when concatenating allophones. LRQ is an active low signal,
when LRQ goes low it is time to load a new address to the chip. If LRQ is high,
then simply wait for it to go low before loading the address. SBY will stay high
until an address is loaded, then it will go low and stay low until all the internal
instructions (Speech Code) from that orie address are completed. Once this sig-
nal goes high, it is time to load a new address. Since speech does not require
very fast address loading, it would be acceptable to use SBY to interface to the
processor.
To end a word using allophones it is necessary to load a pause to complete
the word. For example, the word "TWO" can be implemented using the fol-
lowing allophones, TT2-VW2-PA1. PAl is actually not an allophone but a
pause which is needed to end the word.
BLOCK DIAGRAM C1
C2
C3
SER
OUT
SERIAL COEFFICIENT TRANSFER
97
SP0256 21s-11s4
ALLOPHONE BASED SPEECH PROCESSOR-SP0256-AL2
PIN FUNCTIONS
PIN NUMBER NAME FUNCTION
1 Vss Ground
2 RESET A logic 0 resets that portion of the SP powered by Vo0 . Must be returned to a logic 1
for normal operation.
3 ROM DISABLE For use with an external serial speech ROM, a logic 1 disables the external ROM.
4,5,6 C1, C2, C3 Output control lines for use,with an external serial speech ROM.
7 Voo Power supply for all portions of the SP except the microprocessor interface logic.
8 SBY STANDBY. A logic 1 output indicates that the SP is inactive and V00 can be pow-
ered down externally to conserve power. When the SP is reactivated by an address
being loaded, SBY will go to a logic 0.
9 LRQ LOAD REQUEST. LRQ is a logic 1 output whenever the input buffer is full. When
LRQ goes to a logic 0, the input port may be loaded by placing the 8 address bits on
A1-A8 and pulsing the ALD output.
10, 11, 13, 14, A8, A7, A6, A5, 8 bit address which defines any one of 256 speech entry points.
15, 16, 17, 18, A4, A3, A2, A1
12 SEROUT SERIAL ADDRESS OUT. This output transfers a 16-bit address serially to an exter-
nal speech ROM.
19 SE STROBE ENABLE. Normally held in a logic 1 state. When tied to ground, ALD is
disabled and the SP will automatically latch in the address on the input bus approxi-
mately 11-'s after detecting a logic 1 on any address line.
20 ALD ADDRESS LOAD. A negative pulse on this input loads the 8 address bits into the
input port. The negative edge of this pulse causes LRQ to go high.
21 SERIN SERIAL IN. This is an 8-bit serial data input from an external speech ROM.
22 TEST This pin should be grounded for normal operation.
23 VD1 Power supply for the microprocessor interface logic and controller.
24 DIGITAL OUT Pulse width modulated digital speech output which, when filtered by a 5KHz low
pass filter and amplified, will drive a loudspeaker.
25 SBYRESET STAND BY RESET. A logic 0 resets the microprocessor interface logic and the
address latches. Must be returned to a logic 1 for normal operation.
26' ROM CLOCK This is a 1.56MHz clock output used to drive an external serial speech ROM.
27 OSC1 XTAL IN. Input connection for a 3.12MHz crystal.
28 OSC2 XTAL OUT. Output connection for a 3.12MHz crystal
ALLOPHONE SPEECH 'SYNTHESIS
INTRODUCTION
The allophone speech synthesis technique provides the user with the ability
to synthesize an unlimited vocabulary at a very low bit rate. Fifty-nine discrete
speech sounds (called allophones) and five pauses are stored at different
addresses in the SP0256 internal ROM. Each speech sound was excised from
a word and analyzed using linear predictive coding (LPC). Any English word
or phrase can be created by addressing the appropriate combination of allo-
phones and pauses. Since there is ·a total of 64 address locations each requires
a 6 bit address. Assuming that speech contains 10 to 12 sounds per second,
allophone synthesis requires addressing less than 100 bits per second.
LINGUISTICS
A few basic linguistic concepts will help you start your own library of "allo-
phone words". (See Table 1 for Allophone Dictionary). First, there is no one-
to-one correspondence between written letters and speech sounds; secondly,
speech sounds are acoustically different depending upon their position within
98
SP0256 276-1784
LINGUISTICS (Continued)
a word; and lastly, the human ear may perceive the same acoustic signal differ-
ently in the context of differe.n t sounds.
The first point compares to the problem that a child encounters when learn-
ing to read. Each sound in a language may be represented by more than one
letter and, conversely each letter may represent more than one sound. (See the
examples in Table 2.) Because of these spelling irregularities, it is necessary to
think in terms of sounds, not letters, when using allophones.
The second, and equally important, point to understand, is that the acoustic
signal of a speech sound may differ depending upon its position within a
word. For example, the initial K sound in coop will be acoustically different
from the K's in keep and speak. The K's in coop and keep differ due to the influ-
ence of the vowels which follow them, and the final K in speak is usually not as
loud as initial K's.
Finally, a listener may identify the same acoustic signal differently depend-
ing on the context in which it is perceived. Don't be surprised, therefore, if an
allophone word sounds slightly different when used in various phrases.
PHONEMES OF ENGLISH
The sounds of a language are called phonemes, and each language has a set
which is slightly different from that of other languages. Table 3 contains a
chart of all the consonant phonemes of English, table 4 all the vowel pho-
nemes.
Consonants are produced by creating an occlusion or constriction in the
vocal tract which produces an aperiodic sound source. If the vocal cords are
vibrating at the same time, as in the case of the voiced fricatives VV, DH, ZZ,
and ZH, (See Table 5) there are two sound sources: one which is aperiodic and
one which is periodic.
Vowels are usually produced with a relatively open vocal tract and a peri-
odic sound source provided by the vibrating vocal cords. They are classified
according to whether the front or back of the tongue is high or low (See Table
4) whether they are long or short, and whether the lips are rounded or
unrounded. In English all rounded vowels are produced in or near the back of
the mouth (UW, UH, OW, AO, OR, AW).
Speech sounds which have features in common behave in similar ways. For
example, the voiceless stop consonants PP, TT and KK (See Table 3) should be
preceded by 50-80 msec of silence, and the voiced stop consonants BB, DD,
and GG by 10-30 msec of silence.
ALLOPHONES
Phoneme is the name given to a group of similar sounds in a language.
Recall that a phoneme is acoustically different depending upon its position
within a word. Each of these positional variants is an allophone of the same
phoneme. An allophone, therefore, is the manifestation of a phoneme in the
speech signal. It is for this reason that our inventory of English speech sounds
is called an allophone set.
HOW TO USE THE ALLOPHONE SET

(See Table 1 for instructions on how to create all the sample words men-
tioned in this section.) The allophone set (Refer to Table 5) contains two or
three versions of some phonemes. It may be necessary to use one allophone of
a particular phoneme for word-or-syllable-final position. A detailed set of
guidelines for using the allophones is given in Table 5. Note that these are sug-
gestions, not rules.
For example, DD2 sounds good in initial position and DD1 sounds good in
final position, as a "daughter" and "collide." One of the differences between
the initial and final versions of a consonant is that an initial version may be
longer than the final version. Therefore, to create an initial SS, you can use
two SSs instead of the usual single SS at the end of a word or syllable, as in
" sister ." Note that this can be done with TH and FF, and the inherently short
vowels (to be discussed below), but with no other consonants. You will want to
experiment with some consonant clusters (strings of consonants such as str, cl)
to discover which version works best in the cluster. For example, KK1 sounds
good before LL as in " clown," and KK2 sounds good before WW as in
"square." One allophone of a particular phoneme may sound better before or
99
SP0256 21s-11s4
HOW TO USE THE ALLOPHONE SET (Continued)

after back vowels and another before or after front vowels. KK3 sounds good
before UH and KKl sounds good before IY, as in "cookie." Some sounds (PP,
BB, TT, DD, KK, GG, CH, and JH) require a brief duration of silence before
them. For most of these, the silence has already been added but you may
decide you want to add more. Therefore, there are several pauses included in
the allophone set varying from 10-200 msec. To create the final sounds in the
words "letter" and "little" use the allophone ER and EL.
Reme.mber that you must always think about how a word sounds, not how it
is spelled. For example, the NG sound is represented by the letter N in
"uncle". And remember that some sounds may not even be represented in
words by any letters, as the YY in "cmp.puter".
As mentioned earlier there are some vowels which can be doubled to make
longer versions for stressed syllables. These are the inherently short vowels
IH, EH, EA, EX, AA, and UH. For example, in the word "extent" use one EH
in the first syllable, which is unstressed and two EHs in the second syllable
which is stressed. Of the inherently long vowels there is one, UW, which has a
long and short version. The short one, UWl, sounds good after YY in com-
puter. The long version, UW2, sounds good in monosyllabic words like "two."
Included in the vowel set is a group called R-colored vowels. These are vowel
+ R combinations. For example, the AR in "alarm" and the OR in "score." Of
the R-colored vowels there is one, ER, which has a long and short version. The
short version is good for polysyllabic words with final ER sounds like "letter,"
and the long version is good for monosyllabic words like "fir." One final sug-
gestion is that you Illay want to add a pause of 30-50 msec. between words,
when creating sentences, and a pause of 100-200 msec. between clauses.
Note: Every utterance must be followed by a pause in order to make the chip stop speaking the last allo-
phone.
TABLE 1: THE ALLOPHONE DICTIONARY

NUMBERS
zero ZZYROW thousand TH AA AW ZZ TH PAl PAl NNl
one, won WWSXZXNNl DDl
two, to, too TT2 UW2 million MM IH IH LL YYl AX NNl
three TH RRl IY DAY OF THE WEEK:
four, for, fore FFFFOR
five FFFF AYVV Sunday SS SS AX AX NNl PA2 DD2 EY
six SS SS IH IH PA3 KK2 SS Monday MM AX AX NNl PA2 DD2 EY
seven SS SS EH EH VV IH NNl Tuesday TT2 UW2 ZZ PA2 DD2 EY
eight, ate EYPA3 TT2 Wednesday WW EH EH NNl ZZ PA2 DD2 EY
nine NNlAAAYNNl Thursday TH ER2 ZZ PA2 DD2 EY
ten TT2 EH EH NNl Friday FF RR2 AY PA2 DD2 EY
eleven IH LL EH EH VV IH NNl Saturday SS SS AE PA3 TT2 PA2 DD2 EY
twelve TT2 WH EH EH LL VV MONTHS:
thirteen TH ERl PA2 PA3 TT2 IY NNl January JH AE AE NNl YY2 XR IY
fourteen FF OR PA2 PA3 TT2 IY NNl February FF EH EH PA2 BR RR2 UW2 XR IY
fifteen FF IH FF PA2 PA3 TT2 IY NNl March MMARPA3CH
sixteen SS SS IH PA3 KK2 SS PA2 PA3 TT2 April EY PA3 PP RR2 IH IH LL
IYNNl May MMEY
seventeen SS SS EH VV TH NNl PA2 PA3 TT2
June JH UW2 NNl
IYNNl
July JH UWl LLAY
eighteen EY PA2 PA3 TT2 IY NNl
August AO AO PA2 GG2 AX SS PA3 TTl
nineteen NNl AY NNl PA2 PA3 TT2 IY NNl
September SS SS EH PA3 PP PA3 TT2 EH EH
twenty TT2 WH EH EH NNl PA2 PA3 TT2
PAl BB,2 ERl
IY October
thirty TH ER2 PA2 PA3 TT2 IY AA PA2 KK2 PA3 TT2 OW PAl BB2
forty FF OR PA3 TT2 IY ERl
fifty FF FF IH FF FF PA2 PA3 TT2 IY November NN2 OW VV EH EH MM PAl BB2
sixty SS SS IH PA3 KK2 SS PA2 PA3 TT2 ERl
IY December DD2 IY SS SS EH EH MM PAl BB2
seventy SS SS EH VV IH NNl PA2 PA3 TT2 ERl
IY
eighty EY PA3 TT2 IY
ninety NNl AY NNl PA3 TT2 IY
hundred HH2 AX AX NNl PA2 DD2 RR2 1H
IH PAl DDl
100
SP0256 21s-11a4
ALLOPHONE DICTIONARY (Continued)

LETTERS:
A EY emotional IY MM OW SH AX NNl AX EL
8 882IY engage EH EH PAl NNl GGl EY PA2 JH
c SS SS IY engagement EH EH PAl NNl GGl EY PA2 JH
D DD2 IY MM EH EH NNl PA2 PA3 TT2
E IY engages EH EH PAl NNl GGl EY PA2 JH IH
F EH EH FF FF zz
G JH IY engaging EH EH PAl NNl GGl EY PA2 JH IH
H EYPA2 PA3 CH NG
I AAAY enrage EH NNl RRl EY PA2 JH
J JH EH EY enraged EHNNl RRl EY PA2 JH PA2 DDl
K KKl EH EY enrages EH NNl RRl EY PA2 JH IH ZZ
L EH EH EL enraging EH NNl RRl EY PA2 JH IH NG
M EHEHEM escape EH SS SS PA3 KKl PA2 PA3 PP
N EHEHNNl escaped EH SS SS PA3 KKl PA2 PA3 PP PA2
0 ow TT2
p PPIY escapes EH SS SS PA3 KKl PA2 PA3 PP SS
Q KKl YYl UW2 escaping EH SS SS PA3 KKl PA2 PA3 PP IH
R AR NG
s EH EH SS SS equal IY PA2 PA3 KK3 WH AXEL
T TT2 IY equals IH PA2 PA3 KK3 WH AXEL ZZ
u YYl UW2 error EHXROR
v VVIY extent EH KKl SS TT2 EH EH NNl TT2
w DD2 AX PA2 882 YYl UW2 fir FFER2
X EH EH PA3 KK2 SS SS freeze FF FF RRl IY ZZ
y WWAY freezer FF FF RRl IY ZZ ERl
z ZZIY freezers FF FF RRl IY ZZ ERl ZZ
freezing FF FF RRl IY ZZ IH NG
DICTIONARY frozen FF FF RRl OW ZZ EH NNl
gauge GGl EYPA2 JH
alarm AXLLARMM gauged GGl EY PA2 JH PA2 DDl
bathe 882 EH DH2 gauges GGl EY PA2 JH IH ZZ
bather 882 EY DH2 ERl gauging GGl EY PA2 JH IH NG
bathing 882 EY DH2 IH NG hello HHEHLLAXOW
beer 882YR hour AWERl
bread 881 RR2 EH EH PAl DDl infinitive IH NNl FF FF IH IH NNl IH PA2
by 882AAAY PA3 TT21HVV
calendar KKl AE AE LL EH NNl PA2 DD2 intrigue IH NNl PA3 TT2 RR2 IY PAl GG3
ERl intrigued IH NNl PA3 TT2 RR2 IY PAl GG3
clock KKl LL AA AA PA3 KK2 PA2 DDl
clown KKl LLAWNNl intrigues IH NNl PA3 TT2 RR2 IY PAl GG3
check CH EH EH PA3 KK2 zz
checked CH EH EH PA3 KK2 PA2 TT2 intriguing IH NNl PA3 TT2 RR2 IY PAl GG3
checker CH EH EH PA3 KKl ERl IHNG
checkers CH EH EH PA3 KKl ERl ZZ investigate IH IH NNl VV EH EH SS PA2 PA3
checking CH EH EH PA3 KKl IH NG TT2 IH PAl GGl EY PA2 TT2
checks CH EH EH PA3 KKl SS investigated IH IH NNl VV EH EH SS PA2 PA3
cognitive KK3 AA AA GG3 NNl IH PA3 TT2 TT2 1H PAl GGl EY PA2 TT2 IH
IHVV PA2 DDl
collide KK3 AX LL AY DDl investigater IH IH NNl VV EH EH SS PA2 PA3
computer KKl AX MM PPl YYl UWl TT2 ER TT2 IH PAl GGl EY PA2 TT2 ERl
cookie KK3 UH KKl IY investigaters 1H 1H NNl VV EH EH SS PA2 PA3
coop KK3 UW2 PA3 PP TT2 1H PAl GGl EY PA2 TT2 ERl
correct KKl ER2 EH EH PA2 KK2 PA2 TTl zz
corrected KKl ER2 EH EH PA2 KK2 PA2 TT2 investigates IH IH NNl VV EH EH SS PA2 PA3
IH PA2 DDl TT2 IH PAl GGl EY PA2 TTl SS
correcting KKl ER2 EH EH PA2 KK2 PA2 TT2 investigating EH EH NNl VV EH EH SS PA2 PA3
IHNG TT2 1H PAl GGl EY PA2 TT2 IH NG
corrects KKl ER2 EH EH PA2 KK2 PA2 TTl key KKl IY
ss legislate LL EH EH PA2 JH JH SS SS LL EY
crown KKl RR2 AW NNl PA2 PA3 TT2
date DD2 EY PA3 TT2 legislated LL EH EH PA2 JH JH SS SS LL EY
daughter DD2 AO TT2 ERl PA2 PA3 TT2 IH DDl
day DD2 EH EY legislates LL EH EH PA2 JH JH SS SS LL EY
divided DD2 IH VV AY PA2 DD2 IH PA2 PA2 PA3 TTl SS
DDl
101
SP0256 27&-1784
ALLOPHONE DICTIONARY
DICTIONARY (Continued)
legislating LL EH EH PAZ JH JH SS SS LL EY sweat SS SS WW EH EH PA3 TTZ
PAZ PA3 TT Z IH NG sweated SS SS WW EH EH PA3 TTZ IH PA3
legislature LL EH EH PAZ JH JH SS SS LL EY DD1
PAZ PA3 CH ER1 sweater SS SS WW EH EH PA3 TTZ ER1
letter LL EH EH PA3 TTZ ER1 sweaters SS SS WW EH EH PA3 TTZ ER1 ZZ
litter LL IH IH PA3 TTZ ER1 sweating SS SS WW EH EH PA3 TTZ IH NG
little LL IH IH PA3 TTZ EL sweats SS SS WW EH EH PA3 TTZ SS
memory MM EH EH MM ERZ IY switch SS SS WH IH IH PA3 CH
memories MM EH EH MM ERZ IY ZZ switched SS SS WH IH IH PA3 CH PA3 TTZ
minute MM 1H NN1 IH PA3 TTZ switches SS SS WH IH IH PA3 CH IH ZZZ
month MMAXNN1 TH switching SS SS WH IH IH PA3 CH IH NGZ
nip NN1 IH IH PAZ PA3 PP system SS SS IH IH SS SS PA3 TTZ EH MM
nipped NNZ IH IH PAZ PA3 PP PA3 TTZ systems SS SS IH IH SS SS PA3 TTZ EH MM
nipping NN1 IH IH PAZ PA3 PP IH NG zz
nips NN1 IH IH PAZ PA3 PP SS talk TTZ AO AO PAZ KKZ
no NNZAXOW talked TTZ AO AO PA3 KKZ PA3 TTZ
physical FF FF IH ZZ IH PA3 KK1 AXEL talker TTZ AO AO PA3 KK1 ER1
pin PP IH IH NN1 talkers TTZ AO AO PA3 KK1 ER1 ZZ
pinned PP IH IH NN1 PAZ DD1 talking TTZ AO AO PA3 KK1 IH NG
pinning PP IH IH NN1 IH NG1 talks TTZ AO AO PAZ KKZ SS
pins PP IH IH NN1 ZZ thread TH RR1 EH EH PAZ DD1
pledge PP LL EH FH PA3 JH threaded TH RR1 EH EH PAZ DDZ IH PAZ
pledged PP LL EH EH PA3 JH PAZ DD1 DD1
pledges PP LL EH EH PA3 JH IH ZZ threader TH RR1 EH EH PAZ DDZ ER1
pledging PP LL EH EH PA3 JH IH NG threaders TH RR1 EH EH PAZ DDZ ER1 ZZ
plus PP LL AX AX SS SS threading TH RR1 EH EH PAZ DDZ IH NG
ray RR1 EH EY threads TH RR1 EH EH PAZ DDZ ZZ
rays RR1 EH EYZZ then DH1 EH EH NN1
ready RR1 EH EH PAl DDZ IY time TTZAAAYMM
red RR1 EH FH PAl DD1 times TTZ AA AY MM ZZ
robot RR1 OW PAZ BBZ AA PA3 TTZ uncle AX NG PA3 KK3 EL
robots RR1 OW PAZ BBZ AA PA3 TTl SS whale WWEYEL
score SS SS PA3 KK3 OR whaler WWEYLLER1
second SS SS EH PA3 KK1 IH NN1 PAZ DD1 whalers WW EY LL ER1 ZZ
sensitive SS SS EH EH NN1 SS SS IH PAZ whales WWEYELZZ
PA3 TTZ IH VV whaling WWEYLLTHNG
sensitivity SS SS EH EH NN1 SS SS IH PAZ year YYZYR
PA3 TTZ IH VV IH PAZ PA3 TTZ IY yes YYS EH EH SS SS
sincere SS SS IH IH NN1 SS SS YR
sincerely SS SS IH IH NN1 SS SS YR LL IY
sincerity SS SS IH IH NN1 SS SS EH EH RR1
IH PAZ PA3 TTZ IY
sister SS SS IH IH SS PA3 TTZ ER1
speak SS SS PA3 IY PA3 KKZ
spell SS SS PA3 PP EH EH EL
spelled SS SS PA3 PP EH EH EL PA3 DD1
speller SS SS PA3 PP EH EH EL ERZ
spellers SS SS PA3 PP EH EH EL ERZ ZZ
spelling SS SS PA3 PP EH EH EL IH NG
spells SS SS PA3 PP EH EH EL ZZ
start SS SS PA3 TTZ AR PA3 TTZ
started SS SS PA3 TTZ AR PA3 TTZ IH PAl
DDZ
starter SS SS PA3 TTZ AR PA3 TTZ ER1
starting SS SS PP3 TTZ AR PA3 TTZ IH NG
starts SS SS PP3 TTZ AR PA3 TTl SS
stop SS SS PA3 TTl AA AA PA3 PP
stopped SS SS PA3 TTl AA AA PA3 PP PA3
TTZ
stopper SS SS PA3 TTl AA AA PA3 PP ER1
stopping SS SS PA3 TTl AA AA PA3 PP IH
NG
stops SS SS PA3 TTl AA AA PA3 PP SS
subject (noun) SS SS AX AX PAZ BB1 PAZ JH EH
PA3 KKZ PA3 TTZ
subject (verb) SS SS AX PAZ BB1 PAZ JH EH EH
PA3 KKZ PA3 TTZ
102
SP0256 21s-11a4
TABLE 2-EXAMPLES OF SPELLING IRREGULARITIES

Same sound Different sounds
represented by represented by the
different letters same letters
Vowels mEAt vEin
fEEt forEign
pEte dEism
pEOple dEicer
penn~ gEisha
Consonants SHip althouGH
tenSion GHastly
preCious couGH
naTion hiccouGH
TABLE3-CONSONANTPHONEMESOFENGLISH
LABIO- INTER- ALVEO-
LABIAL DENTAL DENTAL LAR PALATAL VELAR GLOTTAL
Stops: Voiceless pp TT KK
Voiced BB DD GG
Fricatives: Voiceless WH FF TH ss SH HH
Voiced vv DH zz ZH*
Affricates: Voiceless CH
Voiced JH
Nasals Voiced MM NN NG*
Resonants Voiced ww RR,LL yy
These do not occur in word-initial position in English.

Labial: Upper and Lower Lips Touch or Approximate
Labio-Dental: Upper Teeth and Lower Lip,Touch
Inter-Dental: Tongue Between Teeth
Alveolar: Tip of Tongue Touches or Approximates Alveolar Ridge (just
behind upper teeth)
Palatal: Body of Tongue Approximates Palate (roof of mouth)
Velar: Body of Tongue Touches Velum (posterior portion of roof of
mouth)
Glottal: Glottis (opening between vocal cords)
TABLE4-VOWELPHONEMESOFENGLISH
FRONT CENTRAL BACK
High YR
IY UW#
IH* UH*#
Mid EY ER OW#
EH* AX* OY#
XR
Low AE* AW# AO*#
AY OR#
AR
AA*
*SHORT VOWELS
#ROUNDED VOWELS
103
SP0256 276·1784
TABLE 5-GUIDELINES FOR USING THE ALLOPHONES

Silence Voiced Stops
PAl ( 10 ms) -before BB, DD, GG and JH /BBl/ -final position: rib; between vowels:
PA2 ( 30 ms) -before BB, DD, GG, and JH fibber; -
PA3 (50 ms) -before PP, TT, KK, and CH, and be- -in clusters: bleed, brown
tween words /BB2/ -initial positiOn before a vowel: beast
PA4 (100 ms) -between clauses and sentences IDD11 -final position: played, end -
PA5 (200 ms) -between clauses and sentences 1002/ -initial position: down; clusters: drain
/GG1/ -before high front vowels: YR;- IY, IH,
Short Vowels EY, EH,XR
*/IH/ -sitting, stranded /GG2/ -before high back vowels: UW, UH, OW,
*/EH/ -extimt, gentlemen OY, AX; and
*/AE/ -extract, acting - -clusters; g£een, _g!ue
*/UH/ - cookie, full /GG3/ -before low vowels: AE, AW, AY, AR,
*lAO/ - taiking, song AA, AO, OR, ER; and
*/AX/ -lapel, instruct - medial clusters: an_aer; and final posi-
*/AA/ -p2_ttery, c2_tton tion: pe_a
Long Vowels Voiceless Stops

/IY/ -treat, people, pennl .IPPI -E_leasure, amE_le, triE_
lEY/ -great, st!!tment, tr!!l /TTl/ -final clusters before SS: tests, its
lAY/ -K!te, skl, m!ghty /TT2/ -all other positions: test, street -
lOY/ -nQ!se, t2_l, v2_!ce /KK1/ -before front vowelS: YR, -IY, IH, EY, EH,
/UW1/ - after clusters with YY; com~ter XR, AY, AE, ER, AX;
/UW2/ - in monosyllabic words: two, food - initial clusters: cute, clown, scream
/OW/ -zone, close, snow - - /KK2/ -final position: sp13ak; final clusters: task
lAW/ -sound, mouse, down f /KK3/ -before back vowelS: UW, UH, OW, OY,
/ELl -litt~. ang~. gent~men OR,AR, AQ;
-initial clusters: crane, 5l.!!ick, ~own ,
R-Colored Vowels scream
/ERl/ - letter, furniture, interrupt Affricates
/ER2/ -monosyllables: birdTern, burn /CH/ -church, feature
/OR/ - fortune, adorn, stOre - - /JH/ -iudge, iniure
/AR/ - farm, alarm-:garment Nasal
/YR/ -hear, earring, irresponsible
/XR/ /MM/ -milk, alarm, ample
-hair, declare, stare
INN/ -before front and central vowels: YR, IY,
Resonants IH, EY, EH, XR, AE, ER, AX, AW, AY,
UW; final clusters: earn
/WW/ - we, warrant, linguist /NN2/ -before back vowels:-UH, OW, OY, CR,
/RRl/ - Iiiitial position: read, w rite, x-ray AR,AA
/RR2/ - initial clusters: brown-;-crane, g rease lNG/ - stri!!g, a!!ger
/LLI - like, hello, steel - - -
/YYl/ - clusterS: cute, fieauty,larn, l o-yo *These allophones can be doubled.
IYY21 -initial position: les,larn,lo-yo
Voiced Fricatives
/VV/ -vest, prove, even
/DHl/ -word-initial position: this, then, they
/DH2/ - word-final and between vowelS: bathe,
bathing -
IZZI -zoo, phase
/ZH/ -bei~. pleasure
Voiceless Fricatives
*IFF/ -) These may be doubled for initial posi-
tion and used singly in final position
*/TH/ - )
*ISS/ - )
/SH/ - shirt, leash, nation
/HH1/ - before front vow els, RY, IY, IH EY, EH,
XR,AE
/HH2/ - before back vowels: UW, UH, OW, OY,
AO, OR, AR
/WH/ -white, whim, twenty
104
SP0256 21s-11a4
TABLE 6-ALLOPHONE ADDRESS TABLE

OCTAL ADDRESS DECIMAL ADDRESS ALLOPHONE SAMPLE WORD DURATION
000 000 OOOCOQ PAl PAUSE lOMS
001 001 . oe>OO I PAZ PAUSE 30MS
OOZ OOZ ooof 0 P A3 PAUSE 50MS
003 003 0 0 o I I PA4 PAUSE lOOMS
004 004 ' () 0 I ~ Q PA5 PAUSE ZOOMS
005 005 0 b I 0I lOY/ Boy 4ZOMS
006 006 Q 0 I I 0 /AY/ Sky Z60MS
007 007 0 0 I I I /EH/ End 70Ms
010 008 CJ 1 CJ 0 0 /KK3/ Comb 120MS
011 009 0 I 0 () I /PP/ Pow ZlOMS
OlZ 010 0 10 10 /JH/ Dodge 140MS
013 011 (!; 1 Di I /NNl/ Thin 140MS
014 OlZ 0 0 /IH/ Sit 70MS
015 013 Cl
O tI II 0 I /TTZ/ to 140MS
016 014 ~ I I 0 /RRl/ Rural 170MS
017 015 0 l I I I /AX/ Succeed 70MS
OZO 016 I oO 0 0 /MM/ Milk 180MS
OZl 017 I r 0 0 I /TTl/ Part lOOMS
ozz 018 I P) 0 I () IDH1/ They Z90MS
OZ3 019 I 0 0 I I /IY/ See Z50MS
OZ4 OZO 1 o 1 (J 0 lEY/ Beige Z80MS
OZ5 OZl I O 1 0 f IDD11 Could 70MS
OZ6 ozz I 0 1 1 0 IUW11 To lOOMS
OZ7 OZ3 1 I lAO! Aught lOOMS
030 OZ4 I D I {) 0 fAA/ Hot lOOMS
031 OZ5 I I ~ 0 t IYYZ! Yes 180MS
03Z OZ6 I 1 0 I 0 /AE/ Hat 120MS
033 OZ7 : ~ D 1 I /HHl/ He 130MS
034 OZ8 I I 1 0 C7 IBB1 Business 80MS
035 OZ9 I ' I 0 I /TH/ Thin 180MS
036 030 I 1 1 I 0 /UH/ Book lOOMS
037 031 I I' I I /UWZ/ Food Z60MS
040 03Z . CJ o /AW/ Out 370MS
041 033 I Oelli "' I IDDZ! Do 160MS
I 00 c1 v
04Z 034 f) 0 I 0 /GG3/ Wig 140MS
043 035 1 O !> I 1 IVV/ Vest 190MS
044 036 : ~g 1 o CJ IGG11 Got 80MS
045 037 I 0 0 I 0 I /SH/ Ship 160MS
046 038 I O 0 1 I 0 IZHI Azure 190MS
047 039 1 OO I I I /RRZ/ Brain 120MS
050 040 I tJ J 0 0 iJ IFF/ Food 150MS
051 041 1 o 0 I IKKZI Sky 190MS
05Z 04Z I 0 0 1 1 IKK11 Can't 160MS
053 043 ! 0 1 o I I IZZI Zoo ZlOMS
054 044 I ~: I (. ' lNG/ Anchor ZZOMS
055 045 1 O 1 1 '> I ILL/ Lake llOMS
1
056 046 , O I 1 iJ /WW/ Wool 180MS
o57 o47 ~ 0 , , r txRt Repair 360MS
060 048 !<:lO o OIWHI Whig ZOOMS
061 049 I 1 IYY11 yes 130MS
06Z 050 I IO ~ I o /CH! Church 190MS
063 051 :: ~() I ( IER11 Fir 160MS
064 05Z 1 I Ql 0 /ERZ/ Fir 300MS
065 053 11 0 <lJ /OWI Beau Z40MS
066 054 I I 1 1 0 IDHZ! They Z40MS
067 055 I I I /SS/ Vest 90MS
070 056 I I ~ 0 /NNZ/ No
071 057 II g t l IHHZI Hoe
190MS
180MS
072 058 I 1 v 1 0 lORI Store 330MS
073 059 II I 0 I 1/AR/ Alarm Z90MS
074 060 :; I ot iYRI Clear 350MS
075 061 o I IGGZ/ Guest 40MS
076 06Z II I r- /ELl Saddle 190MS
077 063 II I I IBBZI Business 50MS
II l I
105
N·CHANNEL ION IMPLANT (SOUND GENERATOR)
AY·3·8910A PROGRAMMABLE SOUND GENERATOR

276-1787
GENERAL DESCRIPTION
The AY-3-8910A Programable Sound Generator (PSG) is an LSI circuit which
can produce a wide variety of complex sounds under software controL The PIN CONNECTION
AY-3-8910A is manufactured in the Microelectronics N-Channel Ion Implant TOP VIEW
Process. Operation requires a single + 5V power supply, a TTL compatible

clock, and a microprocessor controller.
The PSG is easily interfaced to any bus-oriented system. Its flexibility makes
it useful in applications such as music synthesis, sound effects generation,
audible alarms, tone signaling, and home computer usage. In order to generate
sound effects while allowing the processor to perform other tasks, the PSG can
continue to produce sound after the initial commands have been given by the
control processor. The fact that realistic sound production often involves more
than one component is satisfied by the three independently controllable analog
sound-output channels available in the PSG. These analog sound-output chan-
nels can each provide 4 bits of logarithmic digital-to-analog conversion, greatly
enhancing the dynamic range of the sounds produced.
All circuit control signals are digital in nature and may be provided directly
by a miroprocessor/microcomputer. Therefore, one PSG can produce the full
range of required sounds with no change in external circuitry. Since the fre-
quency response of the PSG ranges from sub-audible at its lowest frequency to
post-audible at its highest frequency, there are few sounds which are beyond
reproduction.
FEATURES
• Full software control of sound generation
• Interfaces to most 8-bit and 16-bit microprocessors
.. Three independently programmable analog outputs
• One or two 8-bit I/0 ports
• Full 0° to 70°C operation

Vee and all other Input/Output
Voltages with Respect to Vss. . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3V to + 8.0V
Storage Temperature ..... . ....... . ... ....... . .. . .. .. . . - 55°C to + 150°C
Operating Temperature .. . .. .. .. ...... . .. . .............. . . . . 0°C to + 70°C
PIN FUNCTIONS
DA7-DAO (Input/Output/High Impedance)
Data/Address Bits 7-0: Pins 30-37
These 8 lines comprise the 8-bit bidirectional bus used by the microproces-
sor to send both data and addresses to the PSG, and to receive data from the
PSG. In the address mode, DA3- DAO select the internal register address
(0- 17s) and DA7-DA4 in conjunction with address inputs A9 and A8, form the
chip select function. When the high order address bits are "incorrect," the
bidirectional buffers are forced to a high impedance state.
Address 9, Address 8
A8 (input): Pin 25
A9 (input): Pin 24
High order address bits A9 and A8 are fixed to recognize a "01" code. They
may be left unconnected, as each is provided with either an on-chip pull-down
(A9) or pull-up (A8) resistor. In noisy environments, however, it is recom-
mended the A9 and A8 be tied to external ground and + 5V respectively, if
they are not to be used.
RESET (Input): Pin 23
For initialization/power-on purposes, applying a low level input to the
RESET pin will reset all registers to 08 • The RESET pin is provided with an
on-chip pull-up register.
CLOCK (Input): Pin 22
This TTL compatible input supplies the timing reference for the Tone,
Noise, and Envelope Generators.
BDIR, BC2, BC1 (Inputs): Pins 27, 28, 29
BUS Direction, BUS Control 2, Bus Control 1
These bus control signals are generated directly by a microprocessor to
control all bus operations internal and external to the PSG.
106
AV-3-891 OA 276·1787
PSG
BDIR BC2 BCt FUNCTION PSG
-- -- - - --
0 1 0 INACTIVE.
1 1 READ FROM PSG.
>-- BDIR
0
1 1 0 WRITE TO PSG.
1 1 1 LATCH ADDRESS. FROM +5- BC2
PROCESSOR
> - BC1
~
Analog Channel A, B, C (Outputs): Pins 4, 3, 38

Each of these signals is the output of its corresponding digital to analog con·
verter, and provides 1V peak-peak (max) signal representing the complex
sound waveshape generated by the PSG.
Pins 2, 5, 26, 39
These pins are for test purposes only and should be left open. Do not tt'se as
tie-points.
Vee: Pin40
Nominal + 5 Volt power supply to the PSG.
Vss: Pin 1
Ground reference for the PSG.
ARCHITECTURE:
The AY·3·8910A is a register oriented Programable Sound Generator (PSG).
Communication between the processor and the PSG is based on the concept of
memory-mapped I/0. Control ·commands are issued to the PSG by writing to
16 memory-mapped registers. Each of the 16 registers within the PSG is also
readable so that the microprocessor can determine, if necessary, present states
or stored data values. All functions of the PSG are controlled through the 16
registers which, once programmed, generate and sustain the sounds, thus
freeing the system processor for other tasks.
REGISTER ARRAY:
The principal element of the PSG is the array of 16 read/write control regis·
ters. These 16 registers look to the CPU as a block of memory and, as such,
occupy a 16-word block out of 1,024 possible addresses. The 10 address bits (8
bits on the common data/address bus, and 2 separate address bits) are decoded
as follows:
I A9 I A8 I DA7 I DA6 I DA5 I DA4 I DA3 I DA2 I DA1 I DAO I

I o I 1 I o I o I o I o I o I o I o I o I
THROUGH
I\:
0 I 1 I 0 I 0 I 0 I 0 I
'\.
1 I 1 I 1 I 1 I
J
HIGH LOW
ORDER ORDER
(Chip Select) (Register No.)
The four low order address bits select one of the 16 registers (RO-R17 8 ). The
six high order address bits function as chip selects to control the tri-state bidi·
rectional buffers (when the high order address bits are incorrect, the bidirec·
tional buffers are forced to a high impedance state). High order address bits
A9, A8 are fixed in the PSG design to recognize a "01" code; high order
address bits DA7-DA4 are programmed to recognize only a "0000" code. All
addresses are latched internally. This internally latched address is updated and
modified on every latch address signal presented to the PSG via the BDIR,
BC2, and BC1 inputs. A latched address will remain valid until the receipt of a
new address, enabling multiple reads and writes of the same register contents
without the need for redundant re-addressing.
Conditioning of the Register Address Latch/Decoder and the Bidirectional
Buffers to recognize the bus function required (Inactive, Latch Address, Write
Data), is accomplished by the Bus Control Decode block.
107
N-CHANNEL ION IMPLANT (SOUND GENERATOR)
AV-3-8910A 276-1787
SOUND GENERATING BLOCKS:

The basic blocks in the PSG which produce the programmed sounds include:
Tone Generators Produce the basic square wave

tone frequencies for each channel
(A,B,C).
Noise Generator Produces a pulse width mod-
ulated pseudo-random square wave
output.
Mixers Combine the outputs of the Tone
Generators and the Noise Genera-
tor; per channel (A, B, C).
Envelope Generator Produces an envelope pattern
which can be used to amplitude
modulate the output of each Mixer.
Amplitude Control Provides the D/A Converters with
either a fixed or variable amplitude
pattern. Fixed amplitude is under
direct CPU control. Variable ampli-
tude is accomplished via the output
of the Envelope Generator.
DIA Converters The three D/A Converters each
produce a 16 level (max) output sig-
nal as determined by the Amplitude
Control.
OPERATION
Since all PSG functions are processor controlled by writing to the internal
registers, a detailed description of the PSG operation may best be accom-
plished by relating each PSG function to control of the corresponding register.
The function of creating or programming a specific sound effect logically fol-
lows the control sequence listed:
Operation Registers Function

Tone Generator RO-R5 Program tone periods
Control
Noise Generator R6 Program noise period
Control
Mixer Control R7 Enable tone
and/or noise on select-
ed channels
Amplitude R10-R12 Select fixed or variable
Control (envelope) amplitudes
Envelope R13-R15 Program envelope
Generator period and select enve-
Control lope pattern
Tone Generator Control

(Registers RO, R1, R2, R3, R4, R5)
The frequency of each square wave generated by the three Tone Generators
(one each for Channels A, B, and C) is obtained by first dividing the input clock
by 16 then by further dividing the result by the programmed 12-bit Tone Period
value. Each 12-bit tone period value is obtained by combining the contents of
the respective Coarse and Fine Tune registers, as illustrated:
Coarse Tune Fine Tune

Register Channel Register
R1 A RO
R3 B R2
R5 c R4
108
AY-3-8910A 276·1787
COARSE TUNE FINE TUNE
12-bit Tone Period (TP) to Tone Generator
The period of the output of the tone generator is therefore deter-

mined by:
16 X TP X P where P =
the period of the input clock.
NOTE: If the Coarse and Fine Tune registers are both set to 0008 , the
resulting period will be minimum, i.e., the generated tone
period will be as if the Coarse Tune register was set to 0008
and the Fine Tune register set to 001 8 •
Noise Generator Control

(Register R6)
The frequency of the noise source is obtained by dividing the input clock by
16, then by further dividing the result by the programmed 5-bit Noise Period
value. This 5-bit value consists of the lower 5 bits (B4-BO) of register R6, as
illustrated:
Noise Period
Register R6
I B7 I B6 I B5 I B4 I B3 I B2 I B1 I BO I
Not Used 5·bit Noise Period (NP)
to Noise Generator
Mixer Control-I/O Enable

(Register R7)
Register R7 is a multi-function ENABLE register which controls the three
Noise/Tone Mixers.
The Mixers, previously described, combine the noise and tone frequencies
for each of the three channels. The determination of combining neither/either/
both noise and tone frequencies on each channel is made by the state of bits
B5-BO of register R7, as illustrated.
The direction (input or output) of the general purpose I/0 ports (IIOA and
IIOB) is determined by the state of bits B7 and B6 of R7, as illustrated.
MIXER CONTROL REGISTER- R7
I B7 B6 B5 I B4 I B3 B2 I B1 I BO
I
Input
/
Function: · Enable
Port: B IA
Function: Noise Enaole Tone Enaole

Channel: c I B I A c I B I A
109
AY-3-891 OA 276-1787
NOISE ENABLE TRUTH TABLE TONE ENABLE TRUTH TABLE I/0 PORT TRUTH TABLE
R7 Bits Noise Enabled R7 Bits Tone Enabled R7 Bits I/0 Port Status
B5 B4 B2 on Channel B2 B1 BO on Channel B7 B6 IIOB I/OA
0 0 0 c B A 0 0 0 c B A 0 0 Input Input
0 0 1 c B - 0 0 1 c B - 0 1 Input Output
0 1 0 c - A 0 1 0 c - A 1 0 Output Input
c - - 1 1 Output Output
0 1 1 c - - 0 1 1
1 0 0 - B A 1 0 0 - B A
1 0 1 - B - 1 0 1 - B -
1 1 0 - - A 1 1 0 - - A
1 1 1 - - - 1 1 1 - - -
NOTE: Disabling noise and tone does not turn off a channel. Turning a chan-
nel off can only be accomplished by writing all zeros into the corresponding
Amplitude Control Register.
Amplitude Control
(Registers R10, R11, R12)
The amplitude of the signals generated by each of the three D/A Converters
(one each for Channels A, B, and C) is determined by the content of the lower
bits (B4-BO) ofregisters R10, R11, and R12 as illustrated.
These five bits consists of a 1-bit mode select ("M" bit) and a 4-bit "fixed"
amplitude level (L3-LO). When the M bit is low, the output level of the analog
channel is defined by the 4-bit "fixed" amplitude level of the Amplitude Con-
trol Register. This amplitude level is fixed in the sense that the amplitude level
is under direct control of the system processor. When the M bit is high, the
output level of the analog channel is defined by the 4-bits of the Envelope
Generator (bits E3-EO). The amplitude mode bit can also be thought of as an
"envelope enable" bit.
Amplitude Control Register Channel

R10 A
R11 B
R12 c
I B7 I B6 I B5 I B4 I B3 I B2 I B1 I BO l
" Not used /\} '\.'\.
M I L3 I L2 I L1 I LO I
Amplitude 4 bit fixed
Mode Amplitude Level
0 0 0 0 0 Amplitude Defined
' ' ' ByLO-L3
' ' '
' ' '
0 1 1 1 1
1 X X X X Amplitude Defined
By EO-E3
Envelope Generator Control

To accomplish the generation of complex envelope patterns, two independ-
ent methods of control are provided: first, it is possible to vary the frequency
of the envelope using registers R13 and R14; second, the relative shape and
cycle pattern of the envelope can be varied using register R15. The following
paragraphs explain the details of the envelope control functions, describing
first the envelope period control and then the envelope shape/cycle control.
(See Figures 1 and 2).
110
AY-3-8910A 276·1787
Envelope Period Control

(Registers R13, R14) .
The frequency of the envelope is obtained by first dividing the input clock by
256, then by further dividing the result by the programmed 16-bit Envelope
Period value. This 16-bit value is obtained by combining the contents of the
Envelope Coarse and Fine Tune registers, as illustrated:
Envelope Envelope
Coarse Tune Fine Tune
Register R14 Register R13
16-bit Envelope Period (EP) to Envelope Generator

Thus the envelope period is given by:
256 x EP x P Where P = period of input clock
NOTE: If the Coarse and Fine Tune registers are both set to 0008 , the
resulting period will be minimum, i.e., the generated tone period will
be as if the Coarse Tune register was set to 000 8 and the Fine Tune
register set to 001 8 •
Envelope Shape/Cycle Control

(Register R15)
The Envelope Generator further divides the envelope period by 16, produc·
ing a 16-state per cycle envelope pattern as defined by the 4-bit counter output,
E3, E2, E1 and EO. The particular shape and cycle pattern of any desired
envelope is accomplished by controlling the count pattern of the 4-bit counter.
(See Figures 4 and 5). ·
This envelope shape/cycle control is contained in the lower 4 bits (B3-BO) of
register R15. Each of these 4 bits controls a function in the envelope generator,
as illustrated:
Envelope Shape/Cycle
Control Register (R15)
Alternate To
Envelope
Attack Generator
L---------+ Continue
Bit 0: HOLD When this is set high (logic 1) the envelope is limited to
one cycle, the value of the envelope at the end of the
cycle being held.
Bit 1: ALTERNATE When set high (logic 1) the envelope counter reverses
direction at end of each cycle (i.e. performs as an up/
down counter).
Bit 2: ATTACK When set high (logic 1) the envelope counter will count
up (attack). When set low (logic 0) the counter will count
down (decay).
Bit 3: CONTINUE When set high (logic 1) the cycle pattern will be defined
by the HOLD bit. When set low (logic O) the envelope
counter will reset to 0000 after one cycle, and hold that
value.
111
AY-3-8910A 276-1787
D/A CONVERTER OPERATION
Since the primary use of the PSG is to produce sound for the non-linear
amplitude detection mechanism of the human ear, the D/A conversion is per-
formed in logarithmic steps with a normalized voltage range from 0 to 1 volt.
The specific amplitude control of each of the three D/A Converters is accom-
plished by the three sets of 4 bit outputs of the Amplitude Control block, while
the Mixer outputs provide the base signal frequency (Noise and/or Tone).
(See Fig. 3).
NORMALIZED
VOLTAGE
1V 15 15
NOTE: ENVElOPE ONLY-

RTS BITS NOISE AND TONES
83 82 81 80 ARE DISABLED.-
C A
0 L
N A T
T T E
I T R H 14 14
N A ~ 0 GRAPHIC REPRESENTATION
Typical ratio from one step to
U C T L OF ENVELOPE GENERATOR
E K E 0 OUTPUT 83 82 81 80. _.--- the next lowet" step Is: 1.211.7
0 0 X X
13 13
0 1
-- DECIMAL VALUE
12 _..- OFE3E2E1 EO
1 0
1 0
EP ENVELOPE PERIOD
Fig. 3 D/A Converter Output
EP IS THE ENVELOPE PERIOD

(DURATION OF ONE CYCLE)
Fig. 1 Envelope Shape/Cycle Operation
• I I
•
• ~ I I
GRAPHIC REPRESENTATION OF
THE DECIMAL VALUES OF
ENVELOPE GENERATOR
·- ... r
I
OUTPUT E3 E2 E1 EO
' lJ 1. . . . . ~
Fig. 4 Slngletone With Envelope Shape/Cycle Pattern 1010
Fig. 2 Detail of Two Cycles of Fig. 1

(Ref. Waveform "1010" in Fig. 1)
Fig. 5 Mixture of Three Tones With Fixed Amplitudes
112
AY-3-8910A 276·1787
STATE TIMING
While the state flow for many microprocessors can be somewhat involved
for certain operations, the sequence of events necessary to control the PSG is
simple and straightforward. Each of the three major state sequences (Latch
Address, Write to PSG, and Read from PSG) consists of several operations
(indicated below by rectangular blocks), defined by the pattern of bus control
signals (BDIR, BCl).
Analog Channel Output Test Circuit
OUTPUT
ADDRESS
INACTIVE
1 - - - - - - - - - - - Ad~;;~~~n:e~~=~~ata
The functional operation and relative timing of the PSG control sequences
are described in the following paragraphs.
ADDRESS PSG REGISTER SEQUENCE

The Latch Address sequence is normally an integral part of the write or read
sequences, but for simplicity is illustrated here as in individual sequence.
Depending upon the processor used, the program sequence will normally
require four principal microstates: (1) send NACT (inactive); (2) send INTAK
(latch address); (3) put address on bus; (4) send NACT (inactive).
BDIR
I
BC1
I
I
BUS
CONTROL
NACT
~ INTAK
~ NACT
DA7-DAO
DON'T
CARE
X OUTPUT
ADDRESS
X DON'T
CARE
"'I- 1••
Reset Timing
~/,....--- : ::
BUS
CONTROL
DECODE
INACTIVE ~ LATCH
ADDRESS
wa
~
INACTIVE
AliAB ADDRESS•
DA7-DAO
'-------v"
~ BUS CONTROL
~ SIGNALS CHANGING "BDIR BC1
1 1
~ ~ SOns Max., lncludfng Skew.

Latch Address Timing
113
AY-3-891 OA 21s-11s7
WRITE DATA TO PSG SEQUENCE #1

The Write to PSG sequence, which would normally follow immediately after
an address sequence, requires four principal microstates: (1) send NACT
inactive); (2) put data on bus; (3) send DWS (write to PSG); (4) send NACT
(inactive).
READ DATA FROM PSG SEQUENCE #2

As with the Write to PSG sequence, the Read from PSG sequence would also
normally follow immediat\]ly after an address sequence. The four principal
microstates of the read sequence are: (1) send NACT (inactive); (2) send DTB
(read from PSG); (3) read data on bus; (4) send NACT (inactive).
BDIR
BOlA
BC1
I BC1
I
I I
BUS
CONTROL
NACT
~ DWS
~ NACT BUS
CONTROL
NACT
~ DTB
~ NACT
DA7-0AO DON'TCARE X OUTPUT DATA

(TO PSG)
X DON'T CARE OA7-0AO
X INPUT DATA
(FROM PSG)
X
PSG Sequence #1 PSG Sequence #2
~---------- v,
' - - - - - - - - - - - v"
~-iA------- v,
~~·- - - - - - - v"
BOIR/
BC1
Clock and Bus Signal Timing
BUS
CONTROL
INACTIVE ~ READ FROM PSG· ~ INACTIVE
DECODE
-1,,.1 --LI~
DA7-0AO
--~-~-~-~O-U-S-----,xr--R-EA-0V-A-l-ID-D-AT-A---,x;--T-R-IS-TA_T_E - - V,
BUS
CONTROL
Voc DECODE
AWE -----.._
r--·,.~ r---- v,
"'-------~/
1 PREVIOUS
VAllO DATA
STATE
~
BUS CONTROL *BOlA BC1 ~ BUS CONTROL
SIGNALS CHANGING 0 1 ~ SIGNALS CHANGING
---l 1-- SOns MAX, Including Skew ~ ~ SOns MAX, Including Skew
BC1
Read Data Timing Write Data Timing
114
FM RECEIVER
FM RECEIVER
TDA7000
276-1304
PIN CONNECTION
GENERAL DESCRIPTION
TOP VIEW
The TDA7000 is a monolithic integrated circuit for mono FM portable
radios, where a minimum on peripheral components is important (small
dimensions and low costs).
The IC has an FLL (Frequency-Locked-Loop) system with an intermediate
frequency of 70 kHz. The i.f. selectivity is obtained by active RC filters. The
only function which needs alignment is the resonant circuit for the oscillator,
thus selecting the reception frequency. Spurious reception is avoided by
means of a mute circuit, which also eliminates too noisy input signals. Special
precautions are taken to meet the radiation requirements.
The TDA7000 includes the R.F. input stage, mixer, local oscillator, l.F.
amplifier/limiter, phase demodulator, mute detector and mute switch.

Supply voltage range (pin 5) (Vp) . .. ........ . .. . . . . . . .. ....... . . .. .... 12 V
Supply current at VP =
4,5 V (IP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 rnA
Power ..... . .... .. . . ....... . . .. . . . . . . ..... . . . .. (See power derating curve)
R.F. input frequency range (f,r) . ..... . ........ . . . . .. . ... .. . . 1.5 to 110 MHz PIN FUNCTION
Sensitivity for - 3 dB limiting 1 Muting Capacitor
(e.m.f. voltage) 2 Audio frequency output
(source impedance: 75 0; mute disabled) .. . . . ..... . . . ..... . .. ... . . 1.5 11-V 3 Noise source
Signal handling (e.m.f. voltage) 4 Loop filter capacitor
5 Supply voltage
(source impedance: 75 0) .... .. . ... .......... . . .... . . ....... . ... 200 mV 6 vco
A.F. output voltage at RL =
22k0 . . .. .. . ....... .. . . . . ......... . .. . . 75 mV 7 1st integrator capacitor*
8 2nd integrator c,a pacitor
9 1st integrator capacitor*
10 IF filter capacitor (to pin 11)
11 IF filter capacitor
12 IF limiter capacitor
13 RF input
14 Mixer
15 Current source capacitor
16 Ground
17 Demodulator capacitor
18 Correlator capacitor
*Connects between Pins 7 and 9.
AUDIO AMPLIFIER AND DETUNING INDICATOR
CIRCUITS
Audio output stages suitable for use with the TDA7000 are shown in Fig. E
and F. Figure G shows how the muting .s ignal can be used to operate a LED to
give an indication of detuning.
Fig. E A 0.4mW transistor audio output stage without

volume control for driving an earpiece.
470k0
80
Frain pin 1 of the
TDA7000 (Fig. A)
Fig. G A detunlng Indicator driven

1) These components replace C2 and R2 in Fig: A P0 S250mW, d = 10% by the mute signal from the TDA7000.
quiescent current = 8mA
Fig. F An Integrated 250mW audio output stage.
115
FM RECEIVER
TDA7000 276-1304
TYPICAL APPLICATION
C18 C17
330pF
220pF
18 17 12 11 10
r------- r------- 7000 7000

1
I
I 2.7k0
I
I 1.4V
I
I
I
4.7k0
I
I I
I I
I
: CORRELATOR _______________
F.M. DEMODULATOR .JI
L----------
C1
C4
150nF
10nF
a.t. output
Fig. A The TOA7000 as a variable c1pacitor tuned f.m. broadcast monitor.
C 7 to C 12 , C, 7 and C18:
Filter and demodulator capacitors. The values shown are for an i.f. of 70 kHz.
For other intermediate frequencies, the values of these capacitors must be
changed in inverse proportion to the i.f. change.
c,4:
Decouples the reverse r.f. input. It must be connected to the common return
via a good quality short connection to ensure a low-impedance path. Inductive
or capacitive coupling between C14 and the local-oscillator circuit or i.f. output
components must be avoided.
C,s:
Decouples the d.c. feedback for i.f. limiter/amplifier LAl.
C 19 and'C21 :
Local-oscillator tuning capacitors. Their values depend on the required tuning
range and on the value of tuning capacitor C20 •
Czz, CzJ, L, Lz:

The values given are for an r.f. bandpass filter with Q 4 for the European and =
U.S.A. domestic f.m. broadcast band (87.5 MHz to 108 MHz). For reception of
the Japanese f.m. broadcast band (76 MHz to 91 MHz), L1 must be increased to
78 nH and L2 must be increased to 150 nH. If stopband attenuation for high
level a.m. or tv signals is not required, L2 and C 22 can be omitted and C 23
changed to 220 pF.
Rz:
The load for the audio output current source. It determines the audio output
level, but its value must not exceed 22 kO for VP =4.5 V, or 47 kO for VP =9 V.
116
FM RECEIVER
TDA7000 21s-13o4
Circuit with variable-capacitance diode tuning

Since it is only necessary to tune the local-oscillator coil, it is very simple to
modify the circuit of Fig. A for variable-capacitance diode tuning. The modifi-
cations are shown in Fig. B.
100kO 8211
BZX79·
3VO 56nH TOA7000
(Fig. A)
BC558
300k0
1.5kl1
ov---4--------4----------------- pin 16
Fig. B Variable-capacitance diode tuning for the local-ocillator. Additional
measures must be taken to ensure temperature stability.
Narrow-band f.m. receiver

The TDA7000 can also be used for reception of narrow-band f.m. signals. In
this case, the local-oscillator is crystal-controlled as shown in Fig. C and there
is therefore hardly any compression of the i.f. swing by the FLL. The deviation
of the transmitted carrier frequency due to modulation must therefore be lim-
ited to prevent severe distortion of the demodulated audio signal.
The component values in Fig. C result in an i.f. of 4.5 kHz and an i.f. band-
width of 5 kHz (Fig. D). If the i.f. is multiplied by N, the values of capacitors
C17 and C18 in the all-pass filters and the values of filter capacitors C 7 , C8 , C10,
C10, C 11 , and C 12 must be multiplied by 1/N. For improved i.f. selectivity to
achieve greater adjacent channel attenuation, second-order networks can be
used in place of C 10 and C11 .
In this circuit the detuning noise generator is not used. Since the circuit
is mainly for reception of audio signals, the audio output must be passed
through a low-pass Chebyshev filter to suppress i.f. harmonics.
Fig. C A narrow-band t.m. receiver with a crystal-controlled local-oscillator.
117
FM RECEIVER
TDA7000 21s-13o4
+20
2
20(1og)~) +10
Ptot
..
1'\
(W}
(dB) 0
1.5
-10
"- ""'-~ 25dB
"' \ ~
I
-20
\ -30 I
1 I
-40 I
I
I
r\
-50
I
0.5 -60
' t\. 0
Fig. D
5 10 15 f(kHz)
I.F. selectivity lor the narrow-band f.m. receiver.

20
0
-50 0 50 100
\ 150
Power derating curve. lamb (oC)
v,
(dB}
S+N
(75mV)
I"'"
/.
-20
~ r-.. II'
..__ li t'
THO
1 (%}
-40
"' ....... 10
~-;:, ~ THO
Vrl
.,.
pf
1---- 14
TOA 7000
-60
NOI E
v 5
0
10 ' 10 5 10 4 1o-3 1o-2 10 1 1
Vrt(e.m.f.)
Fig. H Audio output as a function of input e.m.f. The curves num·

bered 1 were measured with the muting system active. The curves
numbered 2 were measured with the muting system disabled by inject·
ing about 20 p.A into pin 1 of the TDA7000. The Input frequency was 96
MHz modulated with 1 kHz with a deviation of ± 22.5 kHz for the output
level curves, and ± 75 kHz for the distortion curve.
118
QUICK CASE REFERENCE
r 1.10--j 0.205 t - 1.10 l

MIN 10.160 ! MIN
~=D== 0
o.o34 o.1 o7 I- !
0.028 0.080 ~
May show color bands to denote polarlly.
0.260 -t---1- 0.355- j -0.500- 1

0.240 I I 0.325 I
~~f ioI I ::
Positive: Red or Square Lead
-'--+-------+-- 0 312
0 450
0 250 I I I MIN
0.161
0.151
or~
MAX
-
1
?I
0043
0038
-~:
~
.210
~[J.@jt=I'""
.500
t+
SEATING PLANE -1 SEATI~ANE-j /%~~
.018
.016
0.210
0.170
rr-------t-I
I
0.500
MIN --
1--- 0.625 --j--- 0.562
0.147
o;.~o .5so I o.soo
l 0.230
0.270
~ MAX
Tl
0.650
l- l 0.580
MAX
[J
o.o21
0.016 ~
=3
"""""2
! <=>1
I
' 0.125
SEATING PLANE
j~ 65
0
0
o.2o5
-
0.175
I
0.405
0.395
L
0.210 j___J o.25oL _
I 0.035
0.020
3
2
1
1
~rlpll U
0.139
0.161
0.250
MAX
0.020
0.045
,:
0.230 I I MAX '
119
QUICK CASE REFERENCE
ll•fiN-!:11
0.255 0.365
o.23s,----r-D.36o- r o.soo
0.582l
ils\1 1
0.147
0.142
0.130
0.110
u~; o.o3s
0.025
at:J
i__l_o,oo
' 0.140
1·BASE
2·COLLECTOR :1
13·EMITIER
4-COLLECTOR
SEMICONDUCTOR CROSS REFERENCE NOTES
N1 Two required, connect in series-anode to anode.

N2 Two required, connect in series-cathode to cathode.
N3 Two r~quired, connect in series-anode to cathode.
N5 Four required, connect as in original circuit.
N6 Five required, connect as in original circuit.
N7 Six required, connect as in original circuit.
N8 Seven required, connect as in original circuit.
N9 Eight required, connect as in original circuit.
120
QUICK INDEX
PAGE
CATEGORY NUMBER
A TO D CONVERTER (LINCMOS) .......................................................... 50-53

AUDIO (Linear) ......................................................................... 55-59
AUDIO (N-Channel MOS) ...... .. ...., .......................... ..... ..................... 96-105
COMPARATOR (Quad)(Linear) ............. : . ............................................... 71
DIGITAL (CMOS) ........................................................................ 21-28
(Memory) ...........................................•............................ 29-38
(TTL) ............... . ............. . .............................................. 39-44
DIODE (General Purpose) .. ............ . ................ .... ....................... .. ........ 5
DIODE (Zener) ......................................................................... . ... 5
DRIVER (Interface) ...................................................................... 45-47
FM RECEIVER .................................................................. _,_ .... 115-118
LED FLASHER/OSC (Linear) ................................................................ 73
MICROCOMPUTER (8-Bit) ................................................................ 77-95
OPERATIONAL AMP (Linear) ............................................................. 60-64
OPTOELECTRONIC ..................................................................... 12-20
RECEIVER (Interface) ....................................... . ........................ . .. 48, 49
RECTIFIER (Bridge) ......... ,. ............ . ................................................. 5
SOUND GENERATOR (Programmable) ................................................... 106-114
SCR .................................. . ................................................. 12
THYRISTOR .............................................................................. 12
TIMER (LinCMOS) ........................................ . ................................ 54
TIMER (Linear) .........................................................................65, 66
TONE DECODER (Linear) ................................................................... 72
TRANSISTOR (BiPolar) ............... . ...................................................... 6
TRANSISTOR (FET) ...................................................................... 7-10
TRIAC ................................................................................... 12
VARISTOR ............................................................................... 11
VOLTAGE REG. (Linear) . ...................................................... .. ........ 67-70
121
MASTER INDEX BY CATALOG NUMBER
GENERIC NO. GENERIC NO. GENERIC NO.

CATALOG OR PAGE CATALOG OR PAGE CATALOG OR PAGE
NUMBER DESCRIPTION NUMBER NUMBER DESCRIPTION NUMBER NUMBER DESCRIPTION NUMBER
276-007 741 62 276-1067 SCR 12 276-1771 7812 70
276-018 PR5534S 13 276-1101 1N4001 5 276-1772 7815 70
276-021 SLP-236B(Y) 13 276-1102 1N4003 5 276-1778 317T 67
276-022 SLP-236B(G) 13 276-1103 1N4004 5 276-1784 SP0256 96
276-025 R9-56 13 276-1104 1N4005 5 276-1786 CTC256AL2 77
276-026 MINI RED LED 13 276-1114 PTC205 5 276-1787 AY-3-8910A 106
276-030 F336GD 15 276-1122 1N914/4148 5 276-1796 TLC548 50
276-033 TLR-147 13 276-1123 1N34A 5 276-1797 UM3482 27
276-035 XC-5491 19 276-1141 1N5400 5 276-1801 7400 39
276-036 F336HD 15 276-1143 1N5402 5 276-1802 7404 40
276-037 SLP-235B 13 276-1144 1N5404 5 276-1805 7447 42
276-038 1458 63 276-1146 BRIDGE RECT 5 276-1808 7490 44
276-041 RED LED 13 276-1151 BRIDGE RECT 5 276-1822 7408 41
276-053 DISPLAY 18 276-1152 BRIDGE RECT 5 276-2009 MPS2222A 6
276-064 EL-811HR 17 276-1161 BRIDGE RECT 5 276-2016 MPS3904 6
276-065 369HHD 13 276-1165 DIODE 5 276-2017 TIP31 6
276-066A SLA-591LT3 13 276-1171 BRIDGE RECT 5 276~2020 TIP3055 6
276-068 RED LED 13 276-1173 BRIDGE RECT 5 276-2023 MPS2907 6
276-069 GREEN LED 13 276-1180 BRIDGE RECT 5 276-2027 MJE34 6
276-075 MAN74 17 276-1181 BRIDGE RECT 5 276-2030 2N3053 6
. 276-081 B1001R 15 276-1185 BRIDGE RECT 5 276-2035 2N3819 9
276-088 SLP-888A 13 276-1251 MSM2764RS 35 276-2041 2N3055 6
276-116 PHOTOCELL 18 276-1252 TMS4256 36 276-2043 MJ2955 6
276-124 SOLAR CELL 20 276-1303 SSI202 74 276-2055 2SC1308 6
276-134 MOC3010 16 276-1304 TDA7000 115 276-2058 2.1'14401 6
276-142 IR LED/DET PAIR 20 276-1305 TDA1520A 58 276-2062 MPF102 7
276-143 TIL906-1 14 276-1604 2N3906 6 276-2068 TIP120 6
276-145 TIL414 19 276-1617 2N2222 6 276-2072 IRF511 7
276-561 1N4735 5 276-1705 3909 73 276-2074 BS170 10
276-562 1N4739 5 276-1711 324 64 276-2401 4001 21
276-563 1N4742 5 276-1712 339 71 276-2411 4011 22
276-564 1N4744 5 276-1715 353 60 276-2413 4013 23
276-565 1N4733 5 276-1718 TLC555 54 276-2417 4017 24
276-568 ERZ-C20DK201 U 11 276-1721 567 72 276-2449 4049 25
276-570 ERZ-C14DK201U 11 276-1723 NE555 65 276-2466 4066 26
276-703 383 55 276-1728 NE556 66 276-2506 HYB4164-P2 29
276-705 TA7205AP 57 276-1731 386 56 276-2520 MC1488 45
276-1000 TRIAC 12 276-1740 723 69 276-2521 MC1489 48
276-1020 SCR 12 276-1770 7805 70
122
IMPORTANT SUGGESTIONS ON THE USE
AND REPLACEMENT OF TRANSISTORS
You can use various styles and sizes of transistors in Caution: It may be necessary in some cases to adjust
any given circuit application, as long as the electrical bias values to achieve required operation. With tuned
characteristics of the device are within the required circuits, it is a good practice to check alignment after
range of operation. Thus, a tab-type device can be used replacing any transistor.
to replace a T0-3 or T0-66 case device; or a small When replacing power transistors, always check
epoxy-type device can be used in place of T0-5 or driver devices to be sure they are OK. Also, check
other size transistor. other circuit components to be sure they were not
shorted (or otherwise defective) when the original
Generally speaking, you must observe the following
device failed. If you fail to correct such problems
maximum characteristics of a transistor when con-
before applying power to the circuit once again, there-
templating substitution or selection:
placement transistor could easily be permanently
Power dissipation
damaged. Be sure to use proper heat-sink precautions
Maximum collector current
and use silicon grease to reduce the thermal resistance
Maximum collector-to-emitter voltage
between the case of the transistor and the heat-sink.
Maximum collector-to-base voltage
Always observe temperature limitations as specified
Maximum emitter-to-base voltage
with transistor ratings.
Also, it is useful to consider the following charac- It almost goes without saying, but let us remind you
teristics for actual circuit operation: anyway-
Gain Always observe voltage polarity with all semicon-
Frequency limitations ductor devices.
CROSS-REFERENCE/SUBSTITUTION LISTING
Most users of semiconductors realize that it is al- when making exact replacements (junction capaci-
most impossible to guarantee absolute equivalents (as tances normally vary between devices even from the
in the case of tubes). Thus, the only way to create re- same production run).
placement or cross-reference listings is by carefully
evaluating each characteristic of both devices (original
transistor and the possible alternate). This is how the Information contained in this guide is based on the
Technical Staff of Radio Shack went about preparing latest available data and is believed to be accurate.
the following cross-reference/replacement lists. Every care has been taken to assure technical ac-
curacy. However, Radio Shack does not assume re-
IMPORTANT NOTE sponsibility for any contingencies of the use of this
We caution you that in many cases the listed cross information. Nor does Radio Shack assume any re-
reference ARCHER device may be different in sponsibility for any infringements of patents or other
appearance, size or mounting style. Thus, before rights of third parties which may result from its use.
beginning replacement or installation procedures,
check to be sure you have enough room for proper
mounting. When you are looking for a specific number and it
does not show up in the following listing- refer to the
Also, when making substitutions or replacements in technical data provided for our line of ARCHER
radio or high frequency circuitry, it may be necessary devices. With this information you probably will be
to realign tunable circuit elements. This is true even able to make a suitable substitution.
123
MAJOR SEMICONDUCTOR COMPONENTS
I I
1
COMMONLY USED ROUGHLY
NAME OF CIRCUIT MAX RATINGS MAJOR
DEVICE
I SYMBOL
I JUNCTIO!j
SCHEMATIC I ELECTRICAL CHARACTERISTICS AVAILABLE APPLICATIONS
ANALOGOUS
TO:
Diode ANODE ANODE I 1 Conducts easily in 1500 Amps Rectification Check valve
ANODE
$
3000 Volts
t
or one direction, blocks Blocking Diode tube
VANODE (-) in the other
Rectifier
Detecting Gas diode
CATHODE
CATHODE
f VANODE (+)
Steering
Avalanche ANODE Constant voltage 22 Volts Regulation V-R tube

ANODE I
[Zener) characteristic in 1 Watt Reference
Diode
$
CATHODE
$CATHODE
VANODE (-)
f
VANOOE ( +)
negative quadrant
Clipping
Integrated Programmed to 40 Volts Shunt voltage Avalanche
~
Voltage IR desired V 21 by regulator Diode
R,~::l]j
100 rnA
~
Regulator n two resistors Y2
Reference element
0.4 Watts
(IVR)
3 , .) Error modifier
1 v, L~~ Level sensing

1 Level shifting
Tunnel POSITIVE POSITIVE Displays negative Peak point UHF converter None
rJ
Diode ELECTRODE ELECTRODE resistance when current =
,¢
Logic circuits
$ lp current exceeds 100 rnA

peak point current Microwave
Resistive circuits
VANODE ( • ) lp cutoff freq .
NEGATIVE NEGATIVE = 40 Gc Level sensing
I
ELECTRODE ELECTRODE
Back ANODE ANODE Similar 5 rnA Microwave None
(-)I~
Diode characteristics to mixers and
$ $
400 mV
VANOOE conventional diode low power
except very low oscillators
(
VANODE ( •)
forward voltage
CATHODE drop
CATHODE
~ r+J.
Thyrector Rapidly increasing 70 A peak Transient Thy rite
¢ current above rated

voltage in either
direction
pulse
(2" Sq. cell)
voltage
suppression
and arc
suppression
Two avalanche
diodes in
inverse-series
connection
,~.
n-p-n COLLECTOR COLLECTOR Constant collector 300 Volts Amplification Pent ode
~·' ..~
Transistor Is, current for given Tube
25 Watts Switching
base drive
lo,
BAS
Oscillation
lo2
B
lo,
EMITTER EMITTER 0 VcoLLECTOR t. J
p-n-p COLLECTOR VcoLLECTOR <-J 0

COLLECTOR Complement to 75 Volts Amplification None
~' ..~ '·~

Transistor n-p-n transist or
25 Watts Switching
1., Oscillation
BAS
1.,
I~ lo,
EMITTER EMITTER Iss !coLLECTOR (-J
Photo COLLECTOR COLLECTOR

Incident light acts 45 Volts Tape readers None
"'~ ~~
I COLLECTOR
Transistor as base current of
0.25 Amps Card readers
the photo transistor
r--H4 0.6 Wa tts Position sensor
H3
H2 Tachometers
I I;;-,
H1
EMITTER EMITTER VeE
Unijunction
Transistor
[UJT)
~~
BASE 2
EMITTER
BASE 1
~n
..L_ffi~
3:"'
t-<
.,,.
"'"'
"'a:
v.
Unijunction emitter
blocks until its
voltage reaches
Vp; then
35 Volts
0.450 Watts
Interval timing
Oscillation
Level Detector
None
BASE 1
l.t ""'
..:,...
~!::::
conducts SCR Trigger
BASE 2 ~~ 0 EMITTER I,
.
124
MAJOR SEMICONDUCTOR COMPONENTS
NAME OF
DEVICE
I
CIRCUIT
SYMBOL
I
COMMONLY USED
JUNCTION
SCHEMATIC I ELECTRICAL CHARACTERISTICS I MAX RATINGS
AVAILABLE
I MAJOR
APPLICATIONS
I ROUGHLY
ANALOGOUS
TO:
BASE 1
Comple- v, Functional com- 30 Volts High stability None
BASE 1
~
·~~
mentary plement to UJT timers
~~
Unijunction 0.30 Watts
Transistor
~ POINT 0.15 Amps Oscillators and
f---p-1- level detectors
(CUJT) r-;;- VALLEY
·POINT
BASE 2 EMITTER le
BASE 2
~
Program- ANODE t. Programmed by 40 Volts Low cost timers UJT
ANODE
ctr· ~" l "

mabie two resistors for and oscillators
Unijunction 0.30 Watts
Vp, lp, lv. Long period timers
Transistor VALLEY Function 0.15 Amps
(PUT) POINT SCR trigger
equivalent to
PEAK
normal UJT. Level detector
CATHODE -----_::~POINT
CATHODE v.c
Silicon ANODE
ANODE ANODE With anode voltage 1000 Amps Power switching Gas
,.,,],,,~1!...
[_ __~
Controlled I (+), SCR can be 1800 Volts thyratron or
~~
Rectifier Phase control
triggered by lg, ignitron
(SCR) VANOOE H remaining in con- Inverters
duction until anode I Choppers
CATHODE
t,
( VA,NODE (·)
is reduced to zero
Comple- ANODE GATE Polarity comple- 50 Volts Ring counters None

ANODE ANODE
mentary
00
ment to SCR
cfr ~~
I 0.25 Amps Low speed logic
Silicon
Controlled 0.45 Watts Lamp driver
VAc t-1 ~---
Rectifier
(CSCR)
CATHODE
( VAc t · J
CATHODE
Light ANODE Operates similar 1.6 Amps Relay Replace-

ANODE ANOD~ I None
"'"l' '~"' '

Activated to SCR, except can ment
,:W
scR• 200 Volts
also be triggered
Position controls
(LASCR) VANOOE (·) ---:;? into conduction by
light falling on Photoelectri c
CATHODE
( VANODE ( · J
junctions applications
Slave flashes
'
•••
Silicon w ANODE w ANOD~ Operates similar to 100 Volts Logic applications Complementary
11
~_{Jj~
Controlled SCR except can also transistor pair
be triggered on by a 200 rnA Counters
~
Switch• < p "
(SCS) "w 0w (.!) n ~ VANOOE (·) ---::J negative signal on Nixie drivers
0 0 ~ p ~ anode-gate. Also
0
X
~ CATHODE
z
< ~
....
<
n <C ( VANODE (·)
several other
specialized modes
Lamp drivers
u u CATHODE of operation
Silicon ANODE IANODE (·)

Similar to SCS but 0.350 Watts Switching Circuits
ANODE Shockley or
~ r~ ,
Unilateral GATE zener added to anode 0.200 Amps Counters 4-layer
Switch
(SUS) ~"¢ Ror- ~
~
~
gate to trigger device
into conduction at
- 8 volts. Can also be
10 Volts SCR Trigger
Oscillator
diode
n
triggered by negative
CAT~ ODE
CATHODE
pulse at gate lead.
Silicon GAjE AN 0DE 2 IANODE 2

ANODE 2
1 Symmetrical 0.350 Walls Switching Circuits Two inve rse
Bilateral bilateral version 0.200 Amps Counters Schockley
"'n$ .r-"-11$-"-J'·
Switch
(SBS)
~ ~
VANOOE 2(·) (_= of the SUS . Breaks
down in both
10 Volts TRIAC Phase
Control
diodes
n r.;- ~--) VANOOE 2( · ) directions as SUS

R ~ p ..!!, does in forward.
ANODE 1
ANdoE 1
ANODE 2
Triac Operates similar 25 Amps AC switching Two SCR's
~
ANODE 2
to SCR except can 500 Volts in inverse
Phase control
,.,.$
ANODE 1
n
VANOOE
C---1
2(!) [ ___
VANOOE 2( · )
be triggered into
conduction in either
direction by(+) or
(-)gate signal
Relay replacement
parallel
GATE ANODE 1
«-
Diac When voltage 40 Volts Triac and Neon lamp
Trigger reaches trigger 2 Amps peak SCR trigger
c¢ E$3
level (about 35
volts), abruptly
switches down
about 10 volts.
Oscillator
*Light Activated SCS also available. 125

GLOSSARY OF WORDS, SYMBOLS AND ABBREVIATIONS
The following letter symbols and abbreviations are recommended by the Joint Electron Devi~e Engineering
Council (JEDEC) of the Electronic Industries Association (EIA) and the National Electrical Manufacturers Association
(NEMA) for use in semiconductor device data sheets and specifications.
A, a -Anode Gpc -Common-collector small-signal insertion power

B, b -Base gain
brs -Common-source small-signal forward transfer GPE -Common-emitter large-signal Insertion power
susceptance gain
b;, -Common-source. small-signal input susceptance Gr• -Common-emitter small-signal insertion power
bns -Common-source small-signal output susceptance gain
b,5 -Common-source small-signal reverse transfer Gpg -Common-gate small-signal insertion power gain
susceptance Grs -Common-source small-signal insertion power
C, c -Collector gain
Cc:b -Collector-base interterminal capacitance g,. -Common-source small-signal reverse transfer
Cc• -Collector-emitter interterminal capacitance conductance
Crts -Drain-source capacitance GTs -Common-base large-signal transducer power
Cr1u -Drain-substrate capacitance gain
Ceh -Emitter-base interterminal capacitance G 1b -Common-base small-signal transducer power
C;~"' -Common-base open-circuit input capacitance gain
C;hs -Common-base short-circuit input capacitance Gn: -Common-collector large-signal transducer
C;en -Common-emitter open-circuit input capacitance power gain
C;es -Common-emitter short-circuit input capacitance G," -Common-collector small-signal transducer
C;, 5 -Common-source short-circuit input capacitance power gain
Cnhn -Common-base open-r.ircuit output capacitance Gn: -Common-emitter large-signal transducer power
Cobs -Common-base short-circuit output capacitance gain
Cnen -Common-emitter open-circuit output capaci- G,. -Common-emitter small-signal transducer power
tance gain
-Common-emitter short-circuit output capaci- G 1g -Common-gate small-signal transducer power
tance gain
Cnss -Common-source short-circuit output capacitance G 15 -Common-source small-signal transducer power
Crbs -Common-base short-circuit reverse transfer gain
capacitance hFs -Common-base static forward current transfer
-Common-collector short-circuit reverse transfer ratio
capacita nee hrb -Common-base small-signal short-circuit forward
-Common-emitter short-circuit reverse transfer current transfer ratio
capacitance hFr. -Common-collector static forward current trans-
Crss -Common-source short-circuit reverse transfer fer ratio
capacitance hr.: -Common-collector small-signal short-circuit for-
Ctc -Collector depletion-layer capacitance ward current transfer ratio
c,. -Emitter depletion-layer capacitance hFE -Common-emitter static forward current trans-
D, d -Drain fer ratio
E, e -Emitter hr. -Common-emitter small-signal short-circuit for-
T} -Intrinsic standoff ratio ward current transfer ratio
fhrb -Common-base small-signal short-circuit forward hFEl. -Inherent large-signal forward current transfer
current transfer ratio cutoff frequency ratio
-Common-collector small-signal short-circuit for- h 18 -Common-base static input resistance
ward current transfer ratio cutoff frequency h;h -Common-base small-signal short-circuit input
-Common-emitter small-signal short-circuit for- impedance
ward current transfer ratio cutoff frequency hrr. -Common-collector static input resistance
-Maximum frequency of oscillation h;, -Common-collector small-signal short-circuit in-
-Transition frequency (frequency at which com- put impedance
mon-emitter small-signal forward current trans- hrE -Common-emitter static input resistance
fer ratio extrapolates to unity) h;. -Common-emitter small-signal short-circuit input
G, g . -Gate impedance
-Common-source small-signal forward transfer h;e(ima~I-Imaginary part of common-emitter small-signal
conductance short-circuit input impedance
g;, -Common-source small-signal input conductance h;e(real) -Real part of common-emitter small-signal short-
gMB -Common-base static transconductance circuit input impedance
gMc -Common-collector static transconductance hob -Common-base small-signal open-circuit output
gME -Common-emitter static transconductance admittance
-Common-source small-signal output conduc- hoc -Common-collector small-signal open-circuit out-
tance put admittance
Grs -Common-base large-signal insertion power gain hoe -Common-emitter small-signal open-circuit out-
Gph -Common-base small-signal insertion power gain put admittance
Grc -Common-collector large-signal insertion power hoe(im•Rrimaginary part of common-emitter small-signal
gain ' open-circuit output admittance
126
hoe( real) -Real part of common-emitter small-signal open- lm(hie)-Imaginary part of common-emitter small-signal
circuit output admittance short-circuit input impedance
hrb -Common-base small-signal open-circuit reverse ' lm(hoe)-Imaginary part of common-emitter small-signal
voltage transfer ratio open-circuit output admittance
h,c -Common-collector small-signal open-circuit re- 10 -Average forward current, 180° conduction angle,
verse voltage transfer ratio 60-Hz half sine wave
h,. -Common-emitter small-signal open-circuit re- (p -Peak-point current
verse voltage transfer ratio IR -For voltage-regulator and voltage-reference di-
Ia -Base-terminal de current odes: de reverse current. For signal diodes and
h -Alternating component (rms value) of base-ter- rectifier diodes: de reverse current (no alternat-
minal current ing component)
i8 -Instantaneous total value of base-terminal current I, -Alternating component of reverse current (rms
laEv -Base- cutoff current, de value)
lsz(modJ -Interbase modulated curren~ iR -Instantaneous total reverse current
Ic -Collector-terminal de current hrAVJ -Reverse current, de (with alternating component)
Ic -Alternating component (rms value) of collector- IRM -Maximum (peak) total reverse current
terminal current IRRM -Maximum (peak) reverse current, repetitive
ic -Instantaneous total value of collector-terminal hrRMSJ-Total rms reverse current
current IRsM -Maximum (peak) surge reverse current
Icso -Collector cutoff current (de), emitter open Is -Source current, de
lcEO -Collector cutoff current (de), base open lsos -Zero-gate-voltage source current
leER -Collector cutoff current (de), specified resistance lsroHJ -Source cutoff current
between base and emitter lv -Valley-point current
IcEs -Collector cutoff current (de), base shorted to lz -Regulator current, reference current (de)
emitter lzK -Regulator current, reference current (de near
lcEv -Collector cutoff current (de), specified voltage breakdown knee)
between base and emitter lzM -Regulator current, reference current (de maxi-
lcEx -Collector cutoff current (de), specified circuit mum rated current)
between base and emitter K, k -Cathode
lo -Drain current, de Lc -Conversion loss
lo(olfJ -Drain cutoff current M -Figure of merit
lo(on) -On-state drain current NFo -Overall noise figure
loss -Zero-gate-voltage drain current NRo -Output noise ratio
IE -Emitter-terminal de current PsE -Power input (de) to base, common emitter
1. -Alternating component (rms value) of emitter- PBE -Instantaneous total power input to base, com-
terminal current mon emitter
iE -Instantaneous total Vdlue of emitter-terminal Pes -Power input (de) to collector, common base
current pes -Instantaneous total power input to collector,
hso -Emitter cutoff current (de), collector open common base
hszo -Emitter reverse current PeE -Power input (de) to collector, common emitter
IEqofsJ -Emitter-collector offset current PeE -Instantaneous total power input to collector,
common emitter
lEes -Emitter cutoff current (de), base short-circuited PEs -Power input (de) to emitter, common base
to collector PEB -Instantaneous total power input to emitter, com-
IE1EZ(of[J-Emitter cutoff current mon base
IF -For voltage-regulator and voltage- reference di- PF -Forward power dissipation, de (no alternating
odes: de forward current. For signal diodes and component)
rectifier diodes: de forward current (no alternat- PF -Instantaneous total forward power dissipation
ing component) PFrAv 1-Forward power dissipation, de (with alternating
Ir -Alternating component of forward current (rms component)
value) PFM -Maximum (peak) total forward power dissipation
iF -Instantaneous total forward current P 18 -Common-base large-signal input power
IFrAVJ -Forward current, de (with alternating component) Pib -Common-base small-signal input power
IFM -Maximum (peak) total forward current P,c -Common-collector large-signal input power
IFrovJ -Forward current, overload Pic -Common-collector small-signal input power
IFRM -Maximum (peak) forward current, repetitive P 1E -Common-emitter large-signal input power
hrRMSJ -Total rms forward current Pie -Common-emitter small-signal input power
IFsM -Maximum (peak) forward current, surge Pos -Common-base large-signal output power
lc -Gate current, de Pob -Common-base small-signal output power
lcF -Forward gate current Poe -Common-collector large~signal output power
lcR -Reverse gate current Poe -Common-collector small-signal output power
less -Reverse gate current, drain short-circuited to PoE -Common-emitter large-signal output power
source Poe -Common-emitter small-signal output power
lcssF -Forward gate current, drain short-circuited to PR -Reverse power dissipation, de (no alternating
source comp,onent)
lcssR -Reverse gate current, drain short-circuited to PR -Instantaneous total reverse power dissipation
source PRIAVJ-Reverse power dissipation, de (with alternating
11 -Inflection-point current component)
127
\
\
PRM -Maximum (peak) total reverse power dissipation Vcb -Instantaneous value of alternating component
PT -Total nonreactive power input to all terminals of collector-base voltage
PT -Nonreactive power input, instantaneous total, to Ve 81 n1 -Collector-base de open-circuit voltage (floating
all terminals potential)
Qs -Stored charge Vcso -Collector-base voltage, de, emitter open
rss -Interbase resistance Vee -Collector supply voltage (de)
rbCc ~Collector-base time constant VeE -Average or de voltage, collector to emitter
reE(satJ -Saturation resistance, collector-to-emitter Vee -Instantaneous value of alternating component
ros(on) -Static drain-source on-state resistance of collector-emitter voltage
f ds(on) ~Small-signal drain-source on-state resistance VcE 1n1-Collector-emitter de open-circuit voltage (floating
Re(h;e) -Real part of common-emitter small-signal short- potential)
circuit input impedance Vcw -Collector-emitter voltage (de), base open
Re(hoe)-Real part of common-emitter small-signal open- VcEtofsl -Collector-emitter offset voltage
circuit output admittance VeER -Collector-emitter voltage (de), resistance be-
rele2(oni-Small-signal emitter-emitter on-state resistance tween base and emitter
r; -Dynamic resistance at inflection point VeEs -Collector-emitter voltage (de), base shorted to
Ra -Thermal resistance emitter
RaeA -Thermal res is lance, case to ambient VcEtsatJ -Collector-emitter de saturation voltage
RaJA -Thermal resistance, junction to ambient VcEv -Collector-emitter voltage (de), specified voltage
Ra1e -Thermal resistance, junction to case between base and emitter
S , s -Source VeEx -Collector-emitter voltage (de), specified circuit
TA -Ambient temperature or free-air temperature between base and emitter
Te -Case temperature Voo -Drain supply voltage (de)
td -Delay time Vor. -Drain-gate voltage
l d(offl -Turn-off delay time Vos -Drain-source voltage
ld(on) -Turn-on delay time VostunJ -Drain-source on-state voltage
tr -Fall time Vou -Drain-substrate voltage
t r, -Forward recovery time VEs -Average or de voltage, emitter to base
Ti -Junction temperature Veb -Instantaneous value of alternating component
l urr -Turn-off time of emitter-base voltage
t on -Turn-on time VEBi fiJ-Emitter-base de open-circuit voltage (floating
tp -Pulse time potential)
t, -Rise time VEso -Emitter-base voltage (de), collector open
trr -Reverse recovery time VEBllsatJ-Emitter saturation voltage
t. -Storage time VEe -Average or de voltage, emitter to collector
TSS -Tangential signal sensitivity Vee -Instantaneous value of alternating component
Tstg -Storage temperature of emitter-collector voltage
lw -Pulse average time VEC( ri)-Emitter-collector de open-circuit voltage (float-
U, u -Bulk (substrate) ing potential)
Vss -Base supply voltage (de) VEC(ofsJ -Emitter-collector offset voltage
Vse -Average or de voltage, base to collector VEE -Emitter supply voltage (de)
Vbc -Instantaneous value of alternating component Vr -For voltage-regulator and voltage-reference di-
of ba se-collector voltage odes: de forward voltage. For signal diodes and
VuE -Average or de voltage, base to emitter rectifier diodes: de forward voltage (no alternat-
Vbe -Instantaneous value of alternating component ing component)
of base-emitter voltage Vr -Alternating component of forward voltage (rms
ViBRi -Breakdown voltage (de ) value)
VJBRI -Breakd own voltage (instantaneous total) Vr -Instantaneous total forward voltage
ViBR)eBo -Collector-base breakdown voltage, emitter VFIAVJ-Forward voltage, de (with alternating component)
open VrM -Maximum (peak) total forward voltage
ViBR)eEO -Collector-emitter breakdown voltage, base open VrtRMSJ-Total rms forward voltage
VIBRieER -Collector-emitter breakown voltage, resistance Vee -Gate supply voltage (de)
between base and emitter Vcs -Gate-source voltage
ViBR)eEs -Collector-emitter breakdown voltage, base Vcsr -Forward gate-source voltage
shorted to emitter Vc stoffl -Gate-source cutoff voltage
ViBR)eEv -Collector-emitter breakdown voltage, specified VcsR -Reverse gate-source voltage
voltage between base and emitter Vc sph) -Gate-source threshold voltage
ViBR)eEx -Collector-emitter breakdown voltage, specified Vcu -Gate-substrate voltage
c ircuit between base and emitter v, -Inflection-point voltage
VIBRJEBO -Emitter-base breakdown voltage, collector Vos1 -Base-1 peak voltage
open
Vp -Peak-point voltage
ViBRJEeO -Emitter-collector breakdown voltage, base Vpp -Projected peak-point voltage
VIBRJEJE2 -Emitter-emitter breakdown voltage VR -For voltage-regulator and voltage-reference di-
VIBRJGSs -Gate-source breakdown voltage iodes: de reverse voltage. For signal diodes and
VIBRJGssr-Forward gate-source breakdown voltage rectifier diodes: de reverse voltage (no alternat-
VIBRJGSSR-Reverse gate-source breakdown voltage ing component)
Vs2B1 -Interbase voltage V, -Alternating component of reverse voltage (rms
Vcs -Average or de voltage, collector to base value)
128
VR -Instantaneous total reverse voltage Yob -Common-base small-signal short-circuit out-
VR(AV} -Reverse voltage, de (with alternating component) put admittance
VRM -Maximum (peak) total reverse voltage Yoc -Common- collector small- signal short- circuit
VRRM -Repetitive peak reverse voltage output admittance
VR(RMS}- Total rms reverse voltage Yoe -Common-emitter small-signal short-circuit out-
VRsM -Nonrepetitive peak reverse voltage put admittance
VRT -Reach-through voltage Yoe(imag}-Imaginary part of small-signal short-circuit out-
VRwM -Working peak reverse voltage put admittance (common-emitter)
Vss -Source supply voltage (de) Yoe(real} -Real part of small-signal short-circuit output
Vsu -Source-substrate voltage admittance (common-emitter)
V1To) -Threshold voltage Yos -Common-source small-signal short-circuit out-
Vv -Valley-point voltage put admittance
Vz -Regulator voltage, reference voltage (de) Yos(imag}-Common-source small-signal output suscep-
VzM -Regulator voltage, reference voltage (de at max- tance
imum rated current) Yos(real} -Common-source small-signal output conduc-
Yrb -Common-base small-signal short-circuit forward tance
transfer admittance Yrb -Common-base small-signal short-circuit reverse
Yrc -Common-collector small-signal short-circuit for- transfer admittance
ward transfer admittance Yrc -Common-collector small-signal short-circuit re-
yr. -Common-emitter small-signal short-circuit for- verse transfer admittance
ward transfer admittance Yre -Common-emitter small-signal short-circuit re-
Yrs -Common-source small-signal short-circuit for- verse transfer admittance
ward transfer admittance Yrs -Common-source small-signal short-circuit re-
Yfs(imag)-Common-source small-signal forward transfer verse transfer admittance
susceptance Yrs(imag}-Common-source small-signal reverse transfer
Yfs(real} -Common-source small-signal forward transfer susceptance
conductance Yrs(real} -Common-source small-signal reverse transfer
Yib -Common-base small-signal short-circuit input conductance
admittance Zif -Intermediate-frequency impedance
Yic -Common-collector small-signal short-circuit in- Zm -Modulator-frequency load impedance
put admittance Zrr -Radio-frequency impedance .
Yie -Common-emitter small-signal short-circuit input Za!A(t}- Junction-to-ambient transient thermal impedance
admittance Za!Cit}- Junction-to-case transient thermal impedance
Yie(imag}-Imaginary part of small-signal short-circuit in- Zatt} -Transient thermal impedance
put admittance (common-emitter) Zv -Video impedance
Yie(real} -Real part of small-signal short-circuit input ad- z, -Regulator impedance, reference impedance
mittance (common-emitter) (small-signal at lz)
Yis -Common-source small-signal short-circuit in- Zzk -Regulator impedance , reference impedance
put admittance (small-signal at l zK)
Yis(imag)-Common-source small-signal input susceptance Zzm -Regulator impedance, reference impedance
y is( real} -Common-source small-signal input conduc- (small-signal at lzM)
tance
PREFIX AND MANUFACTURER IDENTIFICATION

PREFIX MANUFACTURER PREFIX MANUFACTURER PREFIX MANUFACTURER
BA Rohm MOC Motorola SLP Sanyo
CEX Control Electronics MPS Motorola SN Texas Instruments
DAC National Semiconductor MRF Motorola TA Toshiba
FND Fairchild MU Motorola TIL Texas Instruments
FRL Litronix MV General Instrument TIP Motorola
ICM lntersil NE Signetics TLO Texas Instruments
LF National Semiconductor NSM National Semiconductor TL Texas Instruments
LM National Semiconductor PCIM PC International TLG Toshiba
MA National Semiconductor s American Micro Systems TLR Toshiba
MC Motorola SAD Ret icon VN Siliconix
Mj Motorola SE Signetics XC Xciton
MM National Semiconductor. SEL Sank en
Motorola or Teledyne scs Spectronics
GENERIC PART NUMBER PREFIX CODE

AD Analog To Digital DA Digital To Analog LM Linear Monolithic
AH Analog Hybrid OM Digital Monolithic MM MOS Monolithic
AM Analog Monolithic LF Linear FET TBA Linear Monolithic
CD CMOS Digital LH Linear Hybrid
129
ARCHER SEMICONDUCTOR REPLACEMENT GUIDE
DEVICE 276· DEVICE 276· DEVICE 276· DEVICE 276· DEVICE 276· DEVICE 276· DEVICE 276·
OOOOOOOFR1 1104 000073230 1617 001.0163-02 565 001-044674-001 2009 1104 1104 01-201.0 2009
OOOOOOOFR2 1104 000073231 1617 001.0163-15 562 001-044676-001 1122 2020 1104 01-9011-5/2221-3 2009
OOOOOOOFRI 1104 000073280 2017 001.01501-0 1123 001-044677.001 2016 1617 1104 01-9013-712221-3 2009
OOOOOOOMV4 1122 000073290 1617 001-02101.0 1617 001-21011 1617 2020 1122 01-9014-212221-3 2009
0000000515 1104 0000733JO 1617 001.0_ll01-1 1617 001-22393!.., 564 2041 2016_ 01-9016.412221~
0000001N60 1123 000073320 2017 001-02102-0 1617 001-226030 1104 180l 2009 01-9018-6/2221-3 2009
0000001001 1104 000073332 1617 001-02103-0 1617 002-006500 1617 2035 2009 01-30828 2058
0000000517 1104 000073333 1617 001-02104-0 1617 002-008300 2016 2023 2023 01-30829 2009
0000000518 1104 000073351 2016 001-02105-0 1617 002-009500 1617 2030 2023 01-57291 2020
00000005-38 1104 000073361 2016 001-02106-0 1617 002-009502 1617 2030 2009 01-117005 2016
0000000538 1104 000073370 2009 001-02107-0 1617 002-0095112-12 1617 2020 104 lll-117006 2016
OOOOOOSD1AB 1104 000073380 2017 001-02108-0 1617 002-009600 2016 2020 1104 01-349418 2009
OOOOOOS01Y 1104 000073390 1617 001-02109.0 1617 002-009601 2016 2035 1123 01-349423 1617
0000005046 1123 000073391 1617 001-02110.0 1617 002-009601-12 2016 2035 1122 01-349426 2058
0000015188 1123 OOOODS410R 1122 001-0211h.9 .2009 002-00980L 2023 2035 11Da 01~9634 2009,
0000015334 562 OOOOFR202 1104 001-02111-1 1617 002-009800A 2023 1801 1122 01-349681 2023
0000015990 1122 OOOOR51542 1104 001-02113-2 1617 002-009900 1617 1802 1104 01-472814 2009
0000010DC1 1104 000050-1AUF 1122 001-02113-3 1617 002-03 1617 1822 1104 01-571591 2023
0000015330A 565 000-04 1617 001-02113-4 1617 002-010300 2023 2041 2016 01-571751 2023
000000518 1101 00015188 1123 001-02113-5 1617 002-010300A 2023 2055 2027 01-571794 2016
0000005-38 1114 00015188AM 1123 001-02119-0 2030 002-010400 1617 2009 2023 01-571804 2009
0000005131 1104 00015188FM 1123 001-02121.0 1617 002.010500 2023 2023 2023 01-571811 2009
0000005410 1122 0002SC373 1617 001-02201.0 2023 002.010500A 2023 0020-0191 2009 2023 01-571821 2009
0000051801 1104 0002SC373W 2009 001-02303-0 565 002.010600 2030 0020-0191(,2SC945) 2023 01-571941 1617
OOOOOWZ090 562 0002SC458B 2009 001-02303-3 561 002-010800 !J1l... 2009 01-5}1588
2QU ~
0000-04 2009 00025C458C 2009 001-02303-4 564 002-010900 2023 0020-0250 2009 2023 01-572631 2055
0000-0141 2023 00025C537F 2009 001-02405-0 1104 002-010900A 2023 0020.0330 2009 2023 01-572774 2027
0000-0150 2023 00025C644Q 2016 001-02405-1 1104 002-011400 2016 0020-0332 2009 2023 01-572784 2020
0000-0300 2023 00025C6445,R,Q 2016 001-02405-2 1104 002-011500 2016 0020-0351 2009 2009 01-572791 2020
000015155_ 1122 00025C710B 2009 001-02406-0 1114 002-012000 1617 0020-0521 2058 2016 01-572811 2023
000015188 1123 0002SC710C 2009 00~1 1114 002-0123cio 2027 -0020-0531 2016 2058 o1-m8t4 2oo7
000015330A 565 0002SC772C 2016 001-02601-0 1104 002-012400 2020 0020-0630 2009 2009 01-572861 2020
0000151555 1122 0002SC828 2009 001-02603-0 1104 002.012500 2030 0030-0091 2020 2009 01-680815 2009
0000151849 1104 0002SC828H 2009 001-02701-1 2035 002.012800 2023 0036-001 2023 2009 01-690733 2023
0000152076 1122 00025C828Q 2009 001-02702,.0 2035 002-012800~ 2!113 OOSQ:O.Qil 1123 2009 01-69094§
0000154460 1123 00025C930D
2C!Il.2
2016 001-02703-0 2035 002-9501 2016 0050-0021 1123 2009 01-691187 2058
000025A550 2023 00025C930E 2016 001-015010 1123 002-9502 2016 0050-0032 1123 2009 01-691674 2016
0000258435 2027 00025C968P 2009 001-015011 1123 002-9502-12 2016 0050-0070 1122 2009 01-700542 2023
0000258460 2016 00025C1023 2016 001-021010 2009 002-9601 2016 0050-0250 1122 2055 01 ST-MPS9700D 2009
0000258968 2009 0002SC1026 2016 001-021011 2009 002-9601-12 2016 0050-0300 1122 2016 01K-4.6E 565
00002SC373
00002SC460
2009
2009
0002SC1026A
00025C1026B
2016-
2016
. 001-021020
001-021030
20o9 002-mo:A
2009 002-12000
2023 0050-0301 1122- 2016 01K-5.0E w·
1617 0050-0302 1122 2009 01K-5.2E 565
00002SC460A 2016 0002SC1026Ci 2016 001-021040 2009 002D235RY 2020 0051.0010 1104 2009 01K5.4E 565
00002SC460B 2016 00025C1032 2016 001-021050 2009 002SB435RY 2027 0051.0070 1104 2023 01K-6.5E 561
00002SC460C 2016 00025C1032A 2016 !!!11-021P60. 2011! 002Sc;~Q 2016 !!!15Y1!!!1 1104 2016 011(6.5(, 561
00002SC461 2009 0002SC1032B 2016 001-021070 2016 002SC735-0Y 2009 0051-0110 1104 2023 01ST-MPS9700D 2009
00002SC535 2016 0002SC1032C 2016 001-021080 2009 002SC7350Y 2009 0051-0130 1104 2009 02-004558 038
00002SC536 2009 00025C1061 2020 001-021090 2009 0025C1061 2017 0051-0160 1104 2009 02-25C458LGC 2009
00002SC537 2009 0002SC1061A 2020 001-021110 2030 002SC1209C 2009 0051-0290 1104 N1 2016 02-1001-112221-3 1123
000025C606 2016 00025C1061B 2020 001-021JIJ 2030 002SC735QY 2QOt_ 0051-0291 1104N2 2058 02-1006-2/2221-3 1122
00002SC644 2016 00025C1061C 2020 001.021130 2009 0025D235RY 2020 0051-0340 1104 20ft- 02-1006-22221-3 1122
00002SC668 2016 0003-009700 563 001.021131 2009 003 1123 0051-0400 1020 2009 02-3002-212221-3 1104
00002SC735 2009 000157GN 1123 001-021132 2009 003-00 2058 0054-0020 565 2009 02-3002-22221-3 1104
00002SC772 2058 000188GN 1123 001-021133 2009 003-00200 1123 0054-0191 565 2016 02-33379-6 2030
00002SC828 2009 000546-1 1617 001,0lll34 2009 003-004toe! 1J23 00.54,0240 563 2016 02-124422 lO,\
00002SC829 2016 000704 2009 001-021135 2009 003-005400 1123 0054-0240(,RD-12EB) 2009 02-257205 705
00002SC838 2009 0001849 1104 001-021136 2016 003-006700 1123 563 2016 02-437205 705
00002SC858 2016 0001849R 1104 001-021172 2023 003-007500 1123 0054-0250 1122 2009 02-455804 038
00002SC870 1617 00023645 2009 001-021180 2041 003-009000 1123 0099-1030 1101 2020 02 RECT-UG-1 004 1173
00002SC870A 1617 00031011049 2009 001-021190 2030 003-009100 564 0099-1040
02iZ4:7-- . tOOt
1122 2009 02 5T-2SC1815Y
00002SC870B 1617 00031013045 2009 001::ci21200 2041 003-009200 1123 001422 2009 2009 565
00002SC870C 1617 00031014021 1123 001-021210 1617 003-009400 1104 003002 1123 2016 02P1B
00002SC929 2016
2023
00031014022 1122 001-021218 1617 003-009600 1123 003007 1104 2009 02RECT-UG-1004 1173
00002SC930 2016 OOOWG1010 1122 001-021270.1 2041 003-009700 563 003008 2009 025T-2SC1815
000025C945 2009 00
2009
2016 001-021290 2030 003-009900 1104 ootQ11 2Q16 Q2ST-2SCD1
00002SC968 1617 001-0000-00 2009
1123 001-022010 2023 003-0 1067 003016 2009 02ST-2SC1875 2055
00002SC1 023 2009 001-00 1617 001-022020 2023 003-01 2058 003017 2016 02Z-6.2A 561
00002SC1026 2016 001-007-00 1104 001-023030 565 003-02000 1123 003023 2009 02Z6.2A 561
00002SC1032 2016 001-0010-00 1123 001-023033 561 003-010000 563 003102 2016 02Z6.2W 561
00002SC1061 2020 001-0020-00 1123 001-023034 564 004-00 1617 003111 2009 0219.1 562
0000250235 2020 001-0020.0 1123 001.023037 565 004-0027.00 1104 003113 2009 02Z-9.1A 562
000071150 2023 001-0022.00 1123 001-024010 1104 004-00900 1122 003114 2058 02Z9.1A 562
000071151 2023 001.0072.00 1104 001-024020 1104 004-002000 1104 003307 2058 02Z12A 563
000072020 1104 001.0077.00 1104 001-024030 1104 004-002700 ~104 003449
000072050 1104
2058 02Z12GR 563
001-0081 1123 001-024050 1104 Q04-002800 1J04 003460 2009
000072090 1123 001-0082-00 561 001-024051 1104 004-003000
02.%1.$ ....56.ot
1104 003461 2058 02Z1.5A 564
000072150 562 001-0095-00 1122 001-024052 1104 004-003300 1104 004567 2016 02Z62A 561
000072160 1123 001-0095-02 1122 001-024060 1143 004-003400 1104 004746 2058 03-0018-0 1104
000072190 562 001-02 2023 001-024061 1143 004-003600 1104 004763 2058 03-160 1123
000073070 2016 001-03 2023 001-024080 2009 004-003700 1101 004792 2009 03-460C 2016
000073080 2016 001-04 2023 001-026010 11~ 004-1103900 1104 '104881 ~20 -o~JI 2016
000073090 1617 001.0101.01 562 001-026030 1122 004-004000 1114 0023645
000073100 2020 03-535A 2016
1617 001.0112.00 1122 001-026060 1122 004-004100 1104 0023828 2020
000073110 03-1585/G 1617
2030 001.0125-00 1122 001-027030 2035 004-009200 1123 0023829 2020
000073120 03-3016 1104
1617 001.0151.00 1122 001-044272-002 2009 004-03300 1104 0044028-014 2020 03-931051
000073130 1123
1617 001.0151.01 1122 001-044273-002 2030 004-03500 1104 0044028-14 2035 03-931601
000073140 1104
2058 001.0153-00 1104 001-044277-002 1104 004-03600 1104 0099201-325 2016 03-931609 1104
130
ALPHABETICAL/NUMERICAL INDEX
DIODES AND RECTIFIERS Linear (Miscellaneous) LED CHART (Indicators)

Bridge Rectifiers-50V , 1OOV , 250V , 400V . ... 5 339 Quad Comparator (276-1712) . . 71 Green SLP-236B (276·022) .. . ....... . . .. . 13
Diode (General Purpose) 56 ?Tone Decoder (276-1721) .... . ... . . ... 72 Green SLP-2358 (276-037) ... . 13
40V , 50V , 60V , 75V , 200V, 400V , 600V 3909 LED Flasher / Osc (276-1705) ......... 73 Green (276-069) . . ........ . .. . ........ . 13
1000V ...... . ... . 5 Red PR5534S (276-018) . ....... . 13
Diode (Zener) Linear (Op Amps) Red(276-026) ............ . . . . . . .13
5.1V, 6.2V , 9.1V , 12V , 15V ......... . 5 324 Op Amp (276-1711) . . . . . . . . . . 64 Red TLR-147 (276 -033) . . . 13
353 Op Amp (276-1715) . . .. 60 Red(276-041) . . . ... . ........... . 13
INTEGRATED CIRCUITS 741 Op Amp (276-007) . . . . . . . . . . . 62 Red 369HHD (276-065) .13
1458 Op Amp (276-038) .......... 63 Red SLA-591 LT3 (276-066A) . . . . 13
Digital (CMOS) Red SLP-888A (276-088) .. . . . ...... . . .... 13
4001 NOR Gate (276-2401) ......... . ..... 21 Linear (Timer) Red (276-068) . . .13
4011 NAND Gate (276-2411) ...... . ....... 22 555 Timer (276 -1723) ........ . .......... 65 Yellow SLP-2368 (276-021) . 13
4013 "D" Flip-Flop (276-2413) .......... . . 23 556 Dual Timer (276-1728) . . . 66 Dual Color Red / Green R9-56 (276-025) .... . . 13
4017 Divider/ Counter (276-2417) ........ . 24
4049 Inverting Hex Buffer (276-2449) ....... 25 Linear (Voltage Regulator) SPECIAL PURPOSE DEVICES
4066 Bilateral Switch (276-2466) . . . 26 317T Positive Regulator (276-1778) . . . 67 SCR·200V , 6A (276-1067) . . ......... . ... . 12
UM3482 Melody Generator (276-1797) ...... 27 723 Adj. Volt Regulator (276-1740) .... 69 SCR-400V , 6A (276-1020) ............... . 12
7805 5 Volt Regulator (276-1770) .......... 70 TRIAC 400V , 6A (276 -1000) .. . .......... . 12
Digital (Memory) 7812 12 Volt Regulator (276 -1771) ...... 70 VARISTOR ERZ-C14DK201U (276-570) ..... . 11
4164 Dynamic RAM (276-2506) ............ 29 7815 15 Volt Regulator (276-1772) ..... 70 VARISTOR ERZ-C20DK201 U (276-568) . . . 11
MSM2764RS 64KUV EPROM (276-1251) . . 35
TMS4256 256K Dynamic RAM (276-1 252) .... 36 MICROCOMPUTER (8-Bit) SPECIAL TRANSISTORS
Digital (TTL) CTS256AL2 Code to Speech Chip Field-Effect MPF102 (276-2062) .. 7
7400NANDGate(276-1801) .. . 39 (276-1786) . . ............. 77 Field-Effect 2N3819 (276-2035) ...... . . . .... 9
7404 Hex Inverter (276-1802) . 40 Power MOSFET 8S170 (276-2074) . . 10
7408 AND Gate (276-1822) . . . . . . . . . . . . . . 41 MOS (CMOS) Power MOSFET IRF511 (276-2072) ..... 7
7447 Decoder/ Driver (276-1805) .......... . 42 SSI202 DTMF Receiver (276-1303) ... 74
7490 BCD Counter (276-1808) ............ . 44 TRANSISTORS (BIPOLAR)
N-Channel ION Implant (Sound Generator) General Purpose NPN-SIL (MPS2222A) ..... . . 6
FM RECEIVER AY -3-891 OA Programmable Sound General Purpose NPN-SIL (2N2222) . . .6
TDA7000 (276-1304) .... . .... .. ....... . 115 Generator (276-1787) ......... . ..... . 106 General Purpose NPN-SIL (2N3904) . . ..... 6
General Purpose PNP-SIL (2N3906) ..... 6
Interface (Driver) N-Channel MOS (Audio) Horiz . Dell. NPN-SIL (2SC1 308) .... 6
MC1488 Quad Line Driver (276-2520) ....... 45 SP0256 Speech Processor (276-1784) ....... 96 Power Amp / Switch PNP-SIL (MJ2955) . . .6
Power Amp / Switch PNP-SIL (MJE34) ... 6
Interface (Receiver) OPTOELECTRONIC DEVICES Power Amp / Switch PNP-SIL (TIP31) . .6
MC1489 Quad Line Receiver (276-2521) . 48 Blinking LED (F336GD)(276-030) . . . 15 Power Amp/ Switch NPN-SIL (TIP120) . ....... 6
Blinking LED (F336HD)(276-036) ......... . 15 Power Amp / Switch NPN-SIL (TIP3055) ....... 6
Detector (Infrared Emitter)(276-142) ....... 20 Power Amp / Switch NPN-SIL (2N3053) . . ..... 6
LinCMOS (A to D Converter) Power Amp / Switch NPN-SIL (2N3055) .. 6
Display (MAN74)(276-075) ........... . 17
TLC548 A to D Converter (276-1796) . ..... 50
Display (B1001 R)(276-081) . . ..... . 15 Switching PNP-SIL (MPS2907) . . . . . . . . . . . 6
Display (276-053) . . . . . . . . . . . . . . . .. . 18 Switching / Amp NPN-SIL (2N4401) ...... 6
LinCMOS (Timer) Display (276·064) . . . . . . . . . . . . . ... 17
TLC555 Timer (276-1718) .. 54 Driver (MOC3010)(276-134) . . .. . 16
Infrared Emitter (TIL906-1 )(276-143) . . . . 14
Linear (Audio) Photocell (276-116) . . 18
TA7205P Power Amp (276-705) . ...... 57 Phototransistor (TIL414)(276-145) . ..... . 19
TDA1520A (276-1305) . . 58 Solar Cell (276-124) . ......... . 20
383 Power Amp (276-703) .55 Tri-Color Red / Green / Yellow (XC-5491)
386 Power Amp (276-1731) . . .... 56 (276-035) . . ...... . 19
\ \
,..
A Division of Tandy Corporation

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PRINTED IN U.S.A.
PRINTED IN U.S.A.

Archer Semiconductor Reference Guide 1988

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INTEGRATED CIRCUITS INDEX BY GENERIC NUMBER

GENERIC CATALOG DESCRIPTION PAGE GENERIC CATALOG DESCRIPTION PAGE

AY-3-8910A 276-1787 PROG SND GEN 106 555 276-1723 TIMER 65

INTEGRATED CIRCUITS INDEX BY CATALOG NUMBER

GENERIC CATALOG DESCRIPTION PAGE CATALOG GENERIC DESCRIPTION PAGE

276-007 741 OP AMP 62 276-1772 7815 15V REG 70

BIPOLAR TRANSISTORS . ....... . ....................... . .............. . .......... . ..... . . . 6

When cutting transistor leads, use scissor-type cut-

~ type resistor in series with the silicon rectifier either

~ tifier, or on the output side between the rectifier and

ZENER DIODES-1 Watt

276-565 5.1 49 7 0041

276-1103 400 1.000 10 1.6 0041 276-1146 50 4 M532a

276-1604# 2N3906 S G.P. PNP 350mW 250 40 40 5 200mA 60 0.1 T092

276-2009 MPS2222A S G.P. NPN 625mW 300 75 40 6 800mA 50 10 10nA T092

(In practice , a is 0 .95 to where , where,

SILICON N-CHANNEL JUNCTION MPF102

GENERAL DESCRIPTION PIN CONNECTION

Drain and source may be interchanged 1

GENERAL DESCRIPTION PIN CONNECTION

ABSOLUTE MAXIMUM RATINGS

8.O 10V 8.0

Output Characteristics Transfer Characteristics Saturation Characteristics

Breakdown Voltage Transconductance Normalized On-Resistance

SILICON N-CHANNEL JUNCTION 2N3819

ABSOLUTE MAXIMUM RATING

Gate-Source Breakdown Voltage BVGSS ... .. . . . . . . . . . . • . . . . . . . . . . . . . . . -40 V

Input Admittance Forward Transfer Admittance Output Conductance

Input Admittance Forward Transfer Admittance Output Conductance

BS170 N-CHANNEL TMOS FET

ABSOLUTE MAXIMUM RATINGS

Switching Test Circuit Switching Waveforms

Vas(th) Normalized Versus Temperature On-Region Characteristics

Output Characteristics Capacitance Versus Drain-to· Source Voltage

" ~ ::::--- 8.0V ;,<

V05, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

TRANSIENT/SURGE ABSORBER ERZ-C20DK201 U

A: Original surge wave form

Clamping Voltage Characteristics

Transformer Inductive Surge

Solenoid Inductive Surge Solenoid Inductive Surge

IGT VGT IGT VGT

FUNCTION CATALOG NO. PAGE NO.

FIGURE 1 FIGURE 2 FIGURE 3

TIL906-1 P-N GALLIUM ALUMINUM ARSENIDE

ABSOLUTE MAXIMUM RATINGS

• Output spectrally compatible w ith silicon sensors Peak Forward Current

Relative Power Output Radiant Power Output Relative Radiant Intensity

• Low power consumption BAR 3 ANODE BAR 3 CATHODE

BAR 5 ANODE BAR 5 CATHODE

ABSOLUTE MAXIMUM RATINGS

Continuous fo rward current

GENERAL DESCRIPTION PIN CONNECTION

ABSOLUTE MAXIMUM RATINGS

MOC3010 OPTOCOUPLER TRIAC DRIVER

GENERAL DESCRIPTION PIN CONNECTION

OUTPUT DRIVER MAXIMUM RATINGS

TOTAL DEVICE MAXIMUM RATINGS

APPLICATIONS TYPICAL CHARACTERISTICS