ph208 Up Slides 6
ph208 Up Slides 6
ph208 Up Slides 6
• INTEL iAPX 8086/8088 – 16-bit μP with 40-pins –1 Mbyte mem. addr – 5 to 10 MHz
• 8088 – 8-bit data bus – same internal architecture & instruction set as 8086 – 16
bit data is transferred as 8 bit words – ‘8 bit P with the power of a 16 bit P’.
Signals (7 categories)
• Address bus, data bus, control and status signals, external requests, response to
external signals, power and clock + multiprocessor environment
A. Srinivasan, Department of Physics, Indian Institute of Technology Guwahati
PH 208 P lecture #6
• Signals (7 categories): Address bus, data
bus, control and status signals, external
requests, response to external signals,
power + clock & multiprocessor environ.
• Data bus and status signals are
multiplexed with addr. bus.
• MN/MX: 2 opn. (Min/Max mode);
MN for single μP environment. MX for
multiprocessor environment, such as a
coprocessor – 8 pins are assigned
different task + bus controller (8288) is
necessary for generating control signals.
Processing with
one processing unit
BIU
EU
Memory segmentation
• In order to access 1 MB, 20-bit addr is required. But IP regr. is 16-bit. So, memory
segmentation by using segment registers (SRs).
• SRs assign memory base addr: CS (instruction), DS (data), SS (Stack), ES (addl. Data)
• SR+MR = 20 bit addr. Default combination can be over ridden by instruction.
If program is < 64K, all SR can be defined at the same base addr.
If program is > 64K, all segments can be separate to avoid overlap
(SP) (SI)
• ARITHMETIC INSTRUCTIONS
ADDITION {ADD, ADC, INC, DAA, AAA}
SUBTRACTION {SUB, SBB, CMP, DEC, NEG, AAS, DAS}
MULTIPLICATION {MUL, IMUL, AAM}
DIVISION {DIV, IDIV, AAD, CBW, CWD}
OTHER 16-bit P’s (80x86 family) Prefetched pipeline, II processing, mem. mgt
l
• 80186
68 pin DIP, 80186 (8 & 10 MHz), integrated to reduce chip count rather than improving
memory addr. Multiplexed addr & data bus with addl lines for clk gen, interrupt controllers,
DMA controller, a chip select unit.
• 80286 (also in 68 pin DIP)
Different architectural philosophy, No multiplexing of buses (uses 24 lines to addr 16Mbytes
Can support memory management unit (MMU) to adddress 1Gb of memory (Virtual Mem.),
in-built protection mechanism (to protect user progr.), Multi-user environ & closer to 80386.
A. Srinivasan, Department of Physics, Indian Institute of Technology Guwahati
PH 208 P lecture #6
High-end high-performance P’s from INTEL (80X86): 32- & 64- bit P’s
Trend of evolution: 1) multiuser, multitasking, time-sharing environ. 2) distributed
processing interconnected with networks.
Single-user – unlimited access to all aspects. But multi-user environment requires
Multi-user operating system & new architectural design needed to handle all these!
Intel 80386 and 80486 (32-bit processors):
• 132-pin grid array packages + non multiplexed 32-bit addr. bus – 20 MHz to 33 MHz
– 4Gbytes of physical memory – 64 (246) Tbytes of virtual memory through MMU.
• Can operate in real mode (PA space is 1 Mbyte with 20-bit addr bus) and protected
mode (PA=4GB with 32-bit addr bus) Main difference in mem. spc & addr. schemes
A. Srinivasan, Department of Physics, Indian Institute of Technology Guwahati
PH 208 P lecture #6
Functional signal groups in
Intel 80386:
• 32 bit registers
• Interrupts and external request
signals are similar to 8085.
• Has new signals for co-processor
interfacing.
• Some signals for spl. functions
– byte enable signals for addr.
bus (for identifying groups of
data lines active in 32-bit
data) and in bus control (BS16# to connect directly to 32-bit or 16-bit buses).
Instruction set and addressing modes:
• Nine categories of instructions and eleven addressing modes.
• Operands can be single bit, string of bits, signed and unsigned 8-, 16-, 64-bit data,
ASCII characters and BCD numbers.
• ENTER, LEAVE, ARPL (Adj Req. Priv. Level), VERR/W (Verify Seg for R/W) - HLL & OS
• MMU and better segmentation / paging (4Kbyte) simplifies swapping with
physical memory & disk; 4-level protection mech. (0-highest, 3-lowest priority)
A. Srinivasan, Department of Physics, Indian Institute of Technology Guwahati
PH 208 P lecture #6
• 32-bit registers can be used as 32-, 16- or 8-bit registers (EAX, AX, AL/AH)
• EIP or IP equivalent to PC
• 14-bit are used as flags in 32-bit flag regr. (8086 has 9 flags, 80286 has 11, 80386 has 13)
6 for data (S, Z, CY, AC, O, P) and 3 for m/c opn. (interrupt, single-step, string) + I/O
privilege (in protected mode to determine usable I/O instr.), nested task (to show link
between two tasks), virtual mode (8086 compatible mode) and resume flag, RF (Resume
Flag to work with break points).
A. Srinivasan, Department of Physics, Indian Institute of Technology Guwahati
PH 208 P lecture #6
INTEL 80486:
• Up-graded and faster version with 168-pin grid array package (DX). Clk speed of 25 to 66
MHz. 1.2 million transistors (as compared to 300,000 in 80386!).
• Important addl. features over 80386 are built in math coprocessor (3x faster than 80386),
8 Kbyte of code and cache memory on chip, highly pipelined execution unit (so execution
time for most instructions is one clock cycle).