BLDC Controller ECM
BLDC Controller ECM
BLDC Controller ECM
Description Features
The TIDA-01353 reference design is a discrete • Onboard Temperature Sensing
MOSFET based three-phase inverter for driving • Optocoupling for Circuit Isolation
brushless DC (BLDC) motors rated up to 375 W in
HVAC blower applications using a sensorless, • Sensorless Motor Control
trapezoidal control method. The cycle-by-cycle • Current Sensing Using Single Shunt Resistor on
overcurrent protection feature protects the power stage DC Bus
from overcurrent, and the board can work up to 85°C • Sensorless Trapezoidal Control Using the TI
ambient. This TI Design is a tested, ready-to-use InstaSPIN-BLDC BEMF Integration Method
hardware and software platform for the speed control
of high-voltage BLDC motors using sensorless • Low BOM Cost, High-Efficiency ECM Motor
trapezoidal control. Controller
• Five Preset Motor Speeds
Resources
Applications
TIDA-01353 Design Folder
• Appliances
MSP430F5132 Product Folder
UCC27714 Product Folder • Building Automation
TLV316 Product Folder • Motor Drives
UCC28881 Product Folder • Brushless DC Drives
LP2985-33 Product Folder
• HVAC Motor Control
LMT84LP Product Folder
TPD1E10B06 Product Folder
InstaSPIN Product Folder
EMI/Circuit EMI/Circuit
120 VAC
Protection Protection
120 V
180 VDC
15
VDC
SMPS
*SMPS ± Switch Mode 3.3
Power Supply VDC
180 VDC
Gate Drivers/
Motor
MOSFETs
15 V
Current
Sensing 24 VAC
Opto- External
Control MCU
Black EMF Couplers Controls
Sensing
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An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and other
important disclaimers and information.
1 System Overview
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EMI/Circuit EMI/Circuit
120 VAC
Protection Protection
120 V
180 VDC
15
VDC
SMPS
*SMPS ± Switch Mode 3.3
Power Supply VDC
180 VDC
Gate Drivers/
Motor
MOSFETs
15 V
Current
Sensing 24 VAC
Opto- External
Control MCU
Black EMF Couplers Controls
Sensing
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1.4.1 MSP430F5132
The TI MSP430™ family of ultra-low-power MCUs consists of several devices featuring different sets of
peripherals targeted for various applications. The architecture is combined with five low-power modes. The
device features a powerful 16-bit reduced instruction set computing (RISC) CPU, 16-bit registers, and
constant generators that contribute to the maximum code efficiency. The digitally controlled oscillator
(DCO) allows the devices to wake up from low-power modes to active mode in less than 5 μs.
The MSP430F51x2 series are microcontroller configurations with two 16-bit high-resolution timers, two
universal serial communication interfaces (USCIs) USCI_A0 and USCI_B0, a 32-bit hardware multiplier, a
high-performance 10-bit 200-ksps analog-to-digital converter (ADC), an on-chip comparator, a three-
channel direct memory access (DMA), 5-V tolerant I/Os, and up to 29 I/O pins. The timer event control
module connects different timer modules to each other and routes the external signals to the timer
modules. The device is capable of working up to a system frequency of 25 MHz. The operating
temperature of the device is –40°C to 85°C. Figure 2 shows the functional block diagram of the
MSP430F5132.
DVCC AVCC DVIO P1.x P2.x P3.x PJ.x
RST/NMI DVSS AVSS DVSS 8 8 8 7
XIN XOUT
CPUXV2 3 DMA
and
Working Channel
Registers
EEM
(S: 3+1)
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1.4.2 UCC27714
The UCC27714 is a 600-V, high-side, low-side gate driver with a 4-A source and 4-A sink current
capability with the purpose of driving power MOSFETs. The device comprises one ground-referenced
channel (LO) and one floating channel (HO). The HO is designed to operate with bootstrap supplies. The
device features an excellent robustness and noise immunity with the capability to maintain operational
logic at negative voltages of up to –8-V DC on the HS pin (at VDD = 12 V). The device features the
industry best-in-class input propagation delays and delay matching between both channels with the
purpose of minimizing pulse distortion in high-frequency switching applications. Each channel is controlled
by its respective input pins (HI and LI), allowing full and independent flexibility to control the on and off
state of the output.
The UCC27714 device output stage features a unique architecture on the pullup structure, which delivers
the highest peak-source current when it is most required during the Miller plateau region of the power-
switch turnon transition (when the power switch drain or collector voltage experiences dv/dt). The
UCC27714 includes protection features at which point the outputs are held LOW when inputs are floating
or when the minimum pulse-width specification of the input is not met. The driver inputs are
complementary metal-oxide semiconductor (CMOS) compatible and transistor-transistor logic (TTL)
compatible for easy interfacing with both digital power controllers and analog controllers.
The UCC27714 driver includes an enable and disable function to enable the output gate signals. The
device accepts a bias supply with a wide input range from 10 to 20 V and offers undervoltage lockout
(UVLO) protection for both the VCC and HB bias supply pins. The UCC27714 is available in an SOIC-14
package and rated to operate from –40°C to 125°C. Figure 3 shows a typical setup using the UCC27714.
Bias
Up to 600 V
RBIAS RBOOT DBOOT
CVDD
UCC27714
7 VDD HB 13
CBOOT
Controller RHI RHO Q1
PWM1 1 HI HO 12
RLI 10 k:
PWM2 2 LI HS 11 Load
CLI CHI
RLO Q2
VSS 3 VSS LO 6
EN 10 k:
4 EN/NC COM 5
1.4.3 TLV316
The TLV316 is a family of low-power, rail-to-rail input and output operational amplifiers. These devices
operate from 1.8 to 5.5 V, are unity-gain stable, and are suitable for a wide range of general-purpose
applications. The class AB output stage is capable of driving ≤10-kΩ loads connected to any point
between V+ and ground. The input common-mode voltage range includes both rails and allows the
TLVx316 to be used in virtually any single-supply application. Rail-to-rail input and output swing
significantly increases dynamic range, especially in low-supply applications, and makes them suitable for
driving sampling ADCs.
The TLV316 features a 10-MHz bandwidth and 6-V/μs slew rate with only a 400-μA supply current per
channel, providing good AC performance at very-low power consumption. DC applications are well served
with a very-low input noise voltage of 12 nV/√Hz at 1 kHz, low input bias current (5 pA), and an input
offset voltage of 0.5 mV (typical).
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1.4.4 UCC28881
The UCC28881 integrates a controller and a 700-V power MOSFET into one monolithic device. The
device also integrates a high-voltage current source, enabling start up and operation directly from the
rectified mains voltage. The UCC28881 is the same family device as the UCC28880 and it provides higher
power handling capability.
The low-quiescent current of the device enables excellent efficiency. The device is suitable for non-
isolated AC-to-DC low-side buck and buck-boost configurations with level-shifted direct feedback, but also
more traditional high-side buck, buck-boost, and low-power flyback converters with low standby power can
be built using a minimum number of external components.
The device generates its own internal low-voltage supply (5 V referenced to the device’s ground, GND)
from the integrated high-voltage current source. The PWM signal generation is based on a maximum
constant on-time, minimum off-time concept, with the triggering of the on-pulse depending on the feedback
voltage level. Each on-pulse is followed by a minimum off-time to ensure that the power MOSFET is not
continuously driven in an on-state. The PWM signal is AND-gated with the signal from a current limit
circuit. No internal clock is required, as the switching of the power MOSFET is load dependent. A special
protection mechanism is included to avoid runaway of the inductor current when the converter operates
with the output shorted or in other abnormal conditions that can lead to an uncontrolled increase of the
inductor current. This special protection feature keeps the MOSFET current at a safe operating level. The
device is also protected from other fault conditions with thermal shutdown, UVLO, and soft-start features.
Features:
• Integrated 14-Ω, 700-V power MOSFET
• Integrated high-voltage current source for internal device bias power
• Integrated current sense
• Internal soft start
• Self-biased switcher (start up and operation directly from rectified mains voltage)
• Supports buck, buck-boost and flyback topologies
• <100-μA device quiescent current
• Robust current protection during load short circuit
• Protection:
– Current limit
– Overload and output short circuit
– Over temperature
Figure 4 shows the functional block diagram of the UCC28881.
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HVIN
5
High Voltage
Current Source 8 DRAIN
Thermal
Shutdown
Gate
VDD 4 LDO
S Q
UVLO R Q
Current
Limit
Control and
Reference
Leading Edge
VREF_TH = 1 V Blanking Time
+ PWM Controller
and Output Short LEB
FB 3 Circuit Protection
1, 2
GND
Copyright © 2016, Texas Instruments Incorporated
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1.4.5 LP2985-33
The LP2985 family of fixed-output, low-dropout regulators offers exceptional, cost-effective performance
for both portable and non-portable applications. Available in voltages of 1.8 V, 2.5 V, 2.8 V, 2.9 V, 3 V, 3.1
V, 3.3 V, 5 V, and 10 V, the family has an output tolerance of 1% for the A version (1.5% for the non-A
version) and is capable of delivering a 150-mA continuous load current. The device includes standard
regulator features such as overcurrent and over-temperature protection.
Features:
• Output tolerance:
– 1% (A Grade)
– 1.5% (Standard Grade)
• Ultra-low dropout, typically:
– 280 mV at full load of 150 mA
– 7 mV at 1 mA
• Wide VIN range: 16 V max
• Low IQ: 850 μA at full load at 150 mA
• Shutdown current: 0.01 μA typ
• Low noise: 30 μVRMS with 10-nF bypass capacitor
• Stable with low-ESR capacitors, including ceramic
• Overcurrent and thermal protection
• High peak-current capability
• ESD protection exceeds JESD 22:
– 2000-V human-body model (A114-A)
– 200-V machine model (A115-A)
1.4.6 LMT84
The LMT84/LMT84-Q1 are precision CMOS integrated-circuit temperature sensors with an analog output
voltage that is linearly and inversely proportional to temperature. Its features make it suitable for many
general temperature sensing applications. It can operate down to a 1.5-V supply with 5.4-µA power
consumption, making it ideal for battery powered devices. Package options including a through-hole TO-
92 package allows the LMT84 to be mounted onboard, off-board, to a heat sink, or on multiple unique
locations in the same application. A class-AB output structure gives the LMT84/LMT84-Q1 strong output
source and sink current capability that can directly drive up to 1.1-nF capacitive loads. This means it is
well suited to drive an ADC sample-and-hold input with its transient load requirements. It has accuracy
specified in the operating range of −50°C to 150°C. The accuracy, 3-lead package options, and other
features also make the LMT84/LMT84-Q1 an alternative to thermistors.
Features:
• Low 1.5-V operation
• Very accurate: ±0.4°C typical
• Wide temperature range: –50°C to 150°C
• Low 5.4-µA quiescent current
• Average sensor gain: –5.5 mV/°C
• Output is short-circuit protected
• Push-pull output with ±50-µA drive capability
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1.4.7 TPD1E10B06
The TPD1E10B06 device is a single-channel electrostatic discharge (ESD) transient voltage suppression
(TVS) diode in a small 0402 package. This TVS protection product offers ±30-kV contact ESD, ±30-kV
IEC air-gap protection, and has an ESD clamp circuit with a back-to-back TVS diode for bipolar or
bidirectional signal support. The 12-pF line capacitance of this ESD protection diode is suitable for a wide
range of applications supporting data rates up to 400 Mbps. The 0402 package is an industry standard
and is convenient for component placement in space-saving applications. The TPD1E10B06 devices are
characterized for operation over a temperature range of –40°C to 125°C.
In addition to its ability to work with just about any BLDC motor, InstaSPIN-BLDC has demonstrated
incredible resilience to speed transient perturbations. With zero-cross timing, the user is always using past
information to predict future commutation events. However, InstaSPIN-BLDC monitors a real-time flux
waveform to determine the appropriate time to commutate. Abrupt speed changes will be reflected in the
flux waveform in real time, so it will still cross the specified threshold value at exactly the right time to
commutate.
Using flux for commutation versus BEMF zero-cross timing also enables more stable operation at lower
speeds. Unlike the flux signal, the BEMF signal amplitude diminishes at lower speeds, resulting in poor
signal-to-noise performance. InstaSPIN-BLDC enables smoother operation at low speeds and provides
more reliable motor starting, even under heavy loads.
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2
R5 2.2 ohm D4 C3
J1
3
1 499k C4 GBJ3502-BP 1000pF
~
2 L2 3300pF
3 RV1 C5 2.5mH C6 4 1
- +
4 0.33µF 0.33µF C7
5 1000µF
C R8
~
1
2
ED120/5DS 499k C9
3
E_GND E_GND 3300pF E_GND C10
1000pF
i
120-VAC
GND
This TI Design also incorporates a 15-A 250-V AC rated fuse to prevent damage to the board in case of
overcurrent. The RV1 metal oxide varistor (MOV), rated for 275-VRMS, is also used for surge protection.
Both 499-kΩ resistors are used as the discharge resistive network for capacitors C5 and C6, and are rated
for 400 V. The rectification bridge is rated for 200 V at 35 A, leaving plenty of room for a sufficient safety
factor. L2 is a common-mode filter. To limit the inrush current of the bulk DC capacitors, an inrush current
limiter RT1 is provided. D4 is the full bridge rectifier. L1 is the DC choke provided for meeting the line
harmonic standard. C7 is the electrolytic capacitor at the DC bus.
The AC-DC subsection of the design has been designed with the DC bus capacitor and necessary filters
for conducted emission, surge, and EFT protection as per the standard EN55014. Figure 7 shows the
simulation output of the design using the listed circuit parameters.
To reduce the voltage ripple of the DC output, calculate the bulk capacitor or DC link capacitor value. This
helps ensure that a sufficient hold up time is provided, during which the regulated supply continues to
provide the regulated voltage output in the event of a short lapse in AC voltage supply. The following
arithmetic is used to properly fit the circuit with an appropriately sized DC bus capacitor.
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The input voltage to this system is rated at 115-V AC at 60 Hz. For a DC ripple of 10%, the peak-to-peak
DC voltage ripple is:
DVDC = 115 ´ 2 ´ 0.10 = 16.3 V
( ) (1)
This gives a maximum DC bus voltage of 178.9 V and a minimum of 146.3 V. The discharge time of the
capacitor can be calculated by setting the instantaneous AC input voltage equal to the minimum value of
the DC bus voltage ripple, as Equation 2 shows.
Vm sin q = 146.3 (2)
where Vm is the amplitude of the input voltage as shown in Figure 8.
9
17 8 .
146.3 Ødischarge
Substituting Vm = 178.9 in Equation 1 results in 178.9 sin θ = 146.3, which leads to θ = 0.9575 radians.
Therefore, the total electrical angle during the capacitor discharging period is:
p
qdischarge = + 0.9575 = 2.5283 rad
2
The electrical angle can be expressed in terms of the angular electrical frequency (ω) and time (t) as
Equation 3 shows:
q = vt (3)
where ω can be expressed in electrical frequency as:
v = 2pf (4)
For a 60-Hz AC supply, ω = 2π × 60 = 376.99 rad/s; therefore, the discharge time of the capacitor is:
qdischarge
t discharge = = 6.71ms
v (5)
The average DC bus voltage is:
DVDC
VDC _ ACVG = 178.9 - = 170.75 V
2
By taking the power consumption of the motor to be:
Watts
HPRated ´
HPRated (6)
where the rated horsepower of the motor is ½ hp and the ratio of watts per horsepower is 745.7 W for
every 1 horsepower. Calculate the power required for the motor as:
1
´ 745.7 = 372.85 Watts
2
The average DC link current at 373 W is:
PDC 373 Watts
IDC = = = 2.19 A
VDC _ AVG 170.75 (7)
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The duty cycle does not force the MOSFET on time to go below tON_TO. If DMIN/TON_TO < fSW(max), the
switching frequency is reduced by current runaway protection and the maximum average switching
frequency is lower than fSW(max), the converter cannot support full load. The minimum inductance value
satisfies both the following conditions:
VOUT + Vd
L> = 0.479 mH
DIL ´ FSW _ VIN(max )
(16)
VIN(max ) + Vd 180.5 V
L> ´ t ON _ TO = ´ 450 ns = 0.258 mH
ILIMIT 315 mA (17)
In this TI Design, 0.479 mH is selected as the minimum standard value that satisfies Equation 16 and
Equation 17. The TIDA-01353 uses a 1.8-mH inductor, roughly four times the minimum required
inductance.
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U7
5 4
VDC_Link HVIN VDD
C17 6 D7
NC R13
10µF FB 3
143k +15V
R14 MURS140-13-F
8 1 C14 10.2k C13
DRAIN GND L3
2 0.1µF 0.1µF 1
GND
2
UCC28881DR 1.8mH
J5
D8 C15 R15
MURS140-13-F 100µF 15.0k
GND
Total Pd Efficiency
0 .2 7 5
8 5 .0
0 .2 5 0
8 2 .5
0 .2 2 5
0 .2 0 0 8 0 .0
Efficiency(%)
Total Pd(W)
0 .1 7 5 7 7 .5
0 .1 5 0
7 5 .0
0 .1 2 5
7 2 .5
0 .1 0 0
7 0 .0
0 .0 7 5
0 .0 5 0 6 7 .5
0 .0 2 5
6 5 .0
0 .0 1 0 .0 2 0 .0 3 0 .0 4 0 .0 5 0 .0 6 0 .0 7 0 .0 8 0 .0 9 0 .1 0 0 .0 1 0 .0 2 0 .0 3 0 .0 4 0 .0 5 0 .0 6 0 .0 7 0 .0 8 0 .0 9 0 .1 0
Output Current (A) Output Current (A)
Vin= 1 4 0 .0 V Vin= 1 6 0 .0 V Vin= 1 8 0 .0 V Vin= 1 4 0 .0 V Vin= 1 6 0 .0 V Vin= 1 8 0 .0 V
Figure 10. Buck Converter Simulation Output (Power Dissipation and Efficiency)
LP2985
VIN 1 5 VOUT
2.2µF
1µF
GND 2
ON/OFF
3 4 BYPASS
10 nF
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0 .6 0
0 .5 5
0 .5 0
0 .4 5
Total Pd(W)
0 .4 0
0 .3 5
0 .3 0
0 .2 5
0 .2 0
0 .1 5
0 .1 0
0 .0 5
0 .0 0
0 .0 0 5 0 .0 1 0 0 .0 1 5 0 .0 2 0 0 .0 2 5 0 .0 3 0 0 .0 3 5 0 .0 4 0 0 .0 4 5 0 .0 5 0
Output Current (A)
Vin= 1 4 .0 V Vin= 1 5 .0 V Vin= 1 6 .0 V
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Table 3 shows the values of some key parameters of the LDO simulation. The total power output is 165
mW with an output voltage ripple of 4.4 mV peak to peak.
R77 C58
5.11 0.1µF
GND C59
0.1µF
U14
C60
TP35 1µF 7 13 R78
VDD HB WT
R79 10.0
D27
PWM_WT R80
51.1 GND 4 NC/EN HO 12
C64 Enable
5.11
220pF SDM20U40-7-F R81
1 11 20.0k
HI HS
TP37
PHW
GND
R82 2 6 D28
PWM_WB LI LO R83
51.1
C65 5.11
220pF 8 SDM20U40-7-F
NC WB
9 NC COM 5
10 R84
NC
GND 14 NC VSS 3 10.0
R85
UCC27714DR 20.0k
GND
C66
1µF
EMT
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2
GND GND
1 Q2 1 Q3 1 Q4 GND
UT IRFU13N20DPBF VT IRFU13N20DPBF WT IRFU13N20DPBF
3
3
PHU PHV PHW
2
2
1 Q5 1 Q6 1 Q7
UB IRFU13N20DPBF VB IRFU13N20DPBF WB IRFU13N20DPBF
3
3
R86
EMT
0.1
R87 R88
100 100
C67
1000pF
For the design’s inverter design, there is a choice between power MOSFETs and insulated-gate bipolar
transistors (IGBT). For this application, the MOSFET is used due to the output switching characteristics,
conduction characteristics, and voltage controllability. These devices have the advantage with respect to
ease of control. These devices are suitable for switching frequencies above 20 kHz, as well as for
applications involving moderate voltage levels, that is 200 V.
For each of the six MOSFETs shown in Figure 14, the gate voltage is provided by the HI and LO gate
driver outputs of the UCC27714. The voltage applied to each gate is 15 V with a current output limited at 4
A. These particular transistors have a source-to-drain voltage rating of 200 V and a maximum ID of 13 A.
The static drain-to-source on-resistance RDS(on) is rated at 0.235 Ω.
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1 VDD OUT 2
Temp_S ense
GND 3
C35 C36
0.1µF 0.1µF
LMT84
GND GND
The LMT84 is used in this TI Design to monitor the heat sinks of the inverter transistors. This data is fed
into an ADC port of the MSP430 for comparison. The capacitors are used to reduce noise coupling. A
series output resistor can be added for capacitive loads greater than 1100 pF. Table 4 shows the
recommended resistance value for three separate capacitance ranges. In this particular case, the input
capacitance of the ADC pin of the MSP430F5132 is 3.5 pF, well below the load limit.
The voltage and ADC digital output readings are converted to a temperature value in Celsius using
Equation 35:
5.506 - (-5.506 )2 + 4 ´ 0.00176 ´ (870.6 - VTEMP (mV ))
Temperature (°C ) = + 30
2 ´ (0.00176 ) (35)
where the VTEMP is the value in millivolts obtained from the ADC. This parabolic equation is an
approximation of the transfer table listed in the LMT84 datasheet and the accuracy of the equation
degrades slightly at the temperature range extremes.
The MSP430F5132 has a 10-bit ADC, therefore the voltage gain per LSB is approximated as:
3.3 V - 0 V mV
= 3.22
1024 LSB
This value can be multiplied by the LSB value from the ADC to find the value of VTEMP in Equation 35. Note
that the LSB values acquired from the LMT84 output are inversely proportional to the sensed
temperatures they represent.
Due to the intrinsic behavior of an NMOS/PMOS rail-to-rail buffer, a slight shift in the output can occur
when the supply voltage is ramped over the operating range of the device. The location of the shift is
determined by the relative levels of VDD and VOUT. The shift typically occurs when VDD – VOUT = 1.0 V. This
slight shift (a few millivolts) takes place over a wide change (approximately 200 mV) in VDD or VOUT.
Because the shift takes place over a wide temperature change of 5°C to 20°C, VOUT is always monotonic.
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GND GND
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3V3 GND
GND
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Timer_D: TDR(max)
Timer_D: TDCL0
Timer_D: TDCL1
Timer_D: TDCL2
0h
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Solving for m gives a gain value of 1.2 V/V and results in a b value of 1.3 V, the offset voltage. To
calculate the resistor values for the differential circuit, the following method and circuit layout is used.
VCC
0.01 µF
+
R1 VOUT
_
R2
VIN
0.01 µF RF
VREF RG RL
The circuit can be written out using a simple voltage divider rule and super positioning. This yields
Equation 41:
æ R + RG ö æ R 2 ö æ RF + RG ö æ R1 ö
VOUT = VIN ç F ÷ç ÷ + VREF ç ÷ç ÷
è R G R
øè 1 + R 2ø è RG ø è R1 + R2 ø (41)
Equating the previously calculated coefficients yields Equation 42 and Equation 43:
æ R + RG ö æ R 2 ö
m=ç F ÷ç ÷
è RG ø è R1 + R2 ø (42)
æ R + RG ö æ R1 ö
b = VREF ç F ÷ç ÷
è RG ø è R1 + R2 ø (43)
Now the values of R1 and R2 can be calculated using the following relationship. A reference voltage source
is left out of the design as a space and cost savings measure, and it sacrifices noise performance,
accuracy, and stability performance. Cost is an important specification, but the VCC supply must be
specified well enough to do the job.
æ RF + RG ö æ R1 + R2 ö b æ R1 + R2 ö
ç ÷=mç ÷= ç ÷
è RG ø è R2 ø VCC è R2 ø (44)
This yields the relationship R1 = 0.3283 R2.
The selected resistance values of R1 and R2 are:
• R1 = 3.3 kΩ
• R2 = 10.0 kΩ
Next, the chosen resistor values for R1 and R2 are substituted into Equation 44 for the ratio of RG and RF.
This yields the ratio RF = 0.594 RG.
For this TI Design, the chosen resistance values are chosen to be:
• RF = 8.87 kΩ
• RG = 14.9 kΩ
Lastly, the shunt resistor value must be calculated based on the given values for the slope and offset
voltage. Using the slope intercept form with the calculated values yields:
2.5 = 1.2 ´ 10 a + 1.3 (45)
where α is the resistance value of the shunt resistor. Solving the shunt resistor value is 0.1 Ω for this TI
Design. The dissipation through this resistor is:
2
PD = IRMS2 RSHUNT = (6.5 A ) ´ 0.1 = 4.225 Watts (46)
For this design, a 20-W, 0.1-Ω resistor is used for current sensing.
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The following simulation output verifies the correct output of the current sense amplifier based on the
current across the shunt resistor.
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The comparator compares the analog voltages at the non-inverting (+) and inverting (–) input terminals. If
the non-inverting terminal is more positive than the inverting terminal, the comparator output CBOUT is
high. The comparator can be switched ON or OFF using the control bit CBON. The output of the
comparator can be used with or without internal filtering. When the control bit CBF is set, the output is
filtered with an on-chip RC filter. The delay of the filter can be adjusted in four different steps. Selecting
the output filter can reduce errors associated with comparator oscillation. The comparator features a high-
precision reference voltage level, low offset voltage, and high speed. The CBRSEL (reference select) bit in
the CBCTL2 register can be configured to obtain different thresholds. The reference voltages available are
1.5 V, 2.0 V, and 2.5 V.
R86
0.1
C37
R87 R88
100 100
10pF
C67
R34
8.87k
1000pF
3V3
C38
CSP CSN GND
5
R45 0.1µF TP17
CSN
15.0k 4 GND
V+ 1 R44
IDC_FB
3 V- 100
R39 TLV316IDBVR C39
CSP 1000pF
3.28k U11
2
R50
3V3 10.0k
GND
GND
R55
IDC_OC
100
C45
1000pF
GND
R1
D1 47k
R2 1 4
SIGNAL_PIN5 High-NoDelay
8.25k
SBRT3U40P1-7 C1 2 3
1µF 3V3
C
U1
GND
R3
D2 47k
R4 1 4
SIGNAL_PIN4 Electric_Heat
8.25k
SBRT3U40P1-7 C2 2 3
1µF 3V3
C
U2
GND
R6
D3 47k
R7 1 4
SIGNAL_PIN3 High
8.25k
SBRT3U40P1-7 C8 2 3
1µF 3V3
C
U3
GND
R9
D5 47k
R10 1 4
SIGNAL_PIN2 Medium
8.25k
SBRT3U40P1-7 C11 2 3
1µF 3V3
C
U4
GND
R11
D6 47k
R12 1 4
SIGNAL_PIN1 Low
8.25k
SBRT3U40P1-7 C12 2 3
1µF
C
U5
GND
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The LTV-817 has a maximum forward diode current of 50 mA and a maximum forward voltage of 1.4 V. In
order to avoid potential damage and provide a more consistent input signal to the MCU, the 24-V signal is
conditioned before entering the isolation interface. The 24-V AC has a maximum DC voltage level ±20%
for transformer voltage fluctuations of:
VDC(MAX ) = 24 2 ´ (1 + 0.20 ) = 40.73 VDC
( ) (47)
Considering the voltage drop across the diode, the voltage is:
40.73 - 0.7 = 40.03 VDC
In order to ensure the current levels stay within the bounds of the optocoupler specifications, a series
resistance is added along with a capacitor to reduce the ripple from the AC source. In order to have a
target current input < 5 mA considering a ±20% tolerance, the resistance value is:
40.029 V
= 8005.8 W
0.005 A (48)
In this application, pick a resistance value close to this target value at 8.25 kΩ, giving a maximum current
input to the optocoupler of 4.44 mA.
Similarly, the input to the MSP430F5132 has a maximum current tolerance of 2 mA at any I/O pin. The
optocoupler current transfer ratio, defined as:
I
CTR = C ´ 100%
IF (49)
where:
• IC is the collector current, rated for a maximum of 50 mA
• IF is the forward current, also rated for a maximum of 50 mA
This rating has a maximum at 600% for the LTV-817, reducing the current output to the MCU down to
0.33 mA. Taking this into consideration, along with the desired pullup resistor network layout, the
maximum current from the 3.3-V power supply into the MCU is 70.2 µA with a 47-kΩ pullup resistor, well
below the limits of the MCU.
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CAUTION
For the control signals, there should only be one 24-V AC signal connected to
the board at a time. See Section 1.5.9 for further details with respect to the
control signal terminal. The 24-V signal should only be tied to J3 terminals to
prevent damage to the board. As with the previous connection, do not apply
power until all wiring has been properly connected to the TIDA-01353 board.
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For this TI Design, the motor chassis is shown in Figure 25. As seen in Figure 25, the three connectors
(U,V,W) are wired to the red, blue, and yellow wire of the socket connector of the motor, respectively. Nte
that the wire gauge should be 18 AWG at a minimum. After completing the connection, ensure there are
no exposed wires, which can create a potential shock hazard.
3-Pin Motor
Connector
J1 (see Note A)
AVCC/DVCC
J2 (see Note A)
R1
47 kW
JTAG
RST/NMI/SBWTDIO
VCC TOOL TDO/TDI TDO/TDI
2 1
VCC TARGET TDI TDI
4 3
TMS
6 5 TMS
TEST TCK
8 7 TCK
GND
10 9
RST
12 11
14 13
TEST/SBWTCK
C1 AVSS/DVSS
2.2 nF
(see Note B)
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3. After turning ON the supply, connect the programming connector from the programmer.
4. Open Code Composer Studio™ (CCS), then build and debug the program to program the code to
MSP430F5132.
WARNING
Failure to allow the DC bus capacitor to fully discharge can result
in serious injury or death. Exercise extreme caution when
operating the board.
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2.2.1 InstaSPIN-BLDC
InstaSPIN-BLDC is one of TI’s key flagship motor control technology targeted for cost sensitive sensorless
BLDC applications. This sensorless technique uses traditional trapezoidal or 120° commutation and
monitors motor flux by integrating BEMF of non-energized phase to determine the commutation instances.
For certain markets such as fans, pumps, blowers, and so on, all which do not require a fast dynamic
torque response, InstaSPIN-BLDC implementation is the right way to meet low-cost requirements.
For any trapezoidal control of a BLDC motor, for each 60 electrical degrees, only two inverter legs are
active and deliver the power to motor while third inverter leg is kept in high impedance state by switching
off both high-side and low-side switches. For a uni-polar two-quadrant drive (see Figure 28), PWM is
applied only to the high-side switch of one active leg while the low-side switch of other active leg is kept
ON continuously for one 60 electrical degree.
Neutral
1 at VDC/2 3 5
on off off
A C
At VDC i=0
B
2 4 6
off on off
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The InstaSPIN-BLDC method requires precise sensing of BEMF of open phase of the motor to determine
the commutation instant. As shown in Figure 29, for the first 60-degree interval, PWM is applied only to
the phase-A top switch. In the phase-C bottom switch is continuously ON, BEMF of open phase B is rising
and can be measured and integrated to determine the commutation instant. During the ON-time of the
PWM pulse, with top switch of phase-A connected to VDC and the bottom switch of phase-C connected to
GND, motor neutral terminal potential rises to VDC/2 with respect to GND, and BEMF of phase-B appears
at VDC/2 level above GND. By capturing the absolute value of voltage across phase-B during PWM on
pulse and subtracting it with VDC/2, actual value of motor BEMF can be derived.
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2.2.3.1 PWM_PERIOD
The PWM_PERIOD is used to set the value in TimerD capture/compare register 0. Because TimeD is
used as the PWM generator, this value specifies at what timer count the timer generates an interrupt and
restarts from zero. TimerD is initialized to operate at 25 MHz; see Equation 50 for calculating the PWM
frequency. The TIMERD PWM is configured in UP Mode.
25 MHz
PWM Frequency (Hz ) =
((PWM _ PERIOD ) - 1) (50)
For example, here PWM_PERIOD = 1251, therefore:
25 MHz
PWM Frequency (Hz ) = = 20 kHz
(1252 - 1)
2.2.3.2 MAX_DUTY_CYCLE
MAX_DUTY_CYCLE sets the maximum threshold the input duty cycle command is allowed to. Every time
the input is read, the duty cycle input command is compared to MAX_DUTY_CYCLE, and if it exceeds it,
the target duty cycle is set to MAX_DUTY_CYCLE. This number is relative to the PWM period.
2.2.3.3 MIN_DUTY_CYCLE
MIN_DUTY_CYCLE sets the minimum duty cycle that can be applied to the motor.
2.2.3.4 BEMF_THRESHOLD
BEMF_THRESHOLD is the only parameter that needs to be measured on the motor. Follow these steps
to calculate this parameter:
1. Verify the motor is not connected to the board.
2. Use an oscilloscope to capture the differential voltage waveform between any two phases.
3. Measure the amplitude and frequency of the BEMF (see Figure 32).
4. Calculate the BEMF constant (Ke) parameter by using Equation 51. Note that the BEMF constant used
is the phase-to-phase value.
æ V ö Amplitude (V )
Ke ç ÷ =
è Hz ø Frequency (Hz ) (51)
where
• T = Time period of the BEMF waveform
• Frequency (Hz) = 1/T
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Figure 33 shows the BEMF integration zones in the motor winding voltage waveform. The center tap
voltage is VDC/2. The BEMF integration starts when the winding voltage of the non-switching phase
crosses the center tap and continues until the integrated value reached the BEMF threshold.
Figure 34 explains how to calculate the BEMF threshold using the BEMF constant of the motor. The
calculations are given in Equation 52 through Equation 55.
In the MCU, the ADC samples in every PWM cycle. The PWM time period = (1 / PWM frequency) ≈ 50 µ.
The full-scale output of a 10-bit ADC = 1024 discrete values with a full-scale input voltage of 3.3 V.
Therefore, the ADC reading for any winding voltage of Vph can be expressed as:
Vph ´ 3.6 1024
BEMF ADC Re ading = ´ = 2.24627 ´ Vph
450 + 3.6 3.3 (52)
From Figure 34, the maximum phase-to-phase BEMF (Vph) is V DC. The Tcommutation is the time period
between two commutation instances:
T
Tcommutation =
6
Using the previously calculated BEMF constant Ke, Tcommutation can be calculated as:
Ke Ke
Tcommutation = =
6 ´ BEMF Amplitude 6 ´ VDC (53)
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2.2.3.5 START_UP_DUTY
The first open loop control duty cycle is fixed to the START_UP_DUTY parameter. This is used to align
the motor to a particular position. This number can be adjusted for a specific motor to control how much
current is used during startup. This number is related to the PWM period.
2.2.3.6 START_UP_DUTY_MAX
During open loop control startup, the START_UP_DUTY parameter is gradually increased to
START_UP_DUTY_MAX to complete the alignment of the motor to the start position. This number is
related to the PWM period.
NOTE: To tune the software parameters for your motor, BEMF_THRESHOLD and
START_UP_DUTY are the key parameters to start with.
To change the direction of rotation of the motor, interchange any two motor winding
connections to the board.
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Figure 36 shows the low-side signal input and the corresponding low-side output of one UCC27714
measured across the gate-to-source voltage (VGS) of the MOSFET. The low-side gate output from the
UCC27714 swings between ground and VCC of the UCC27714.
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Figure 37 shows the high-side signal input and the corresponding high-side output of the UCC27714
measured across the gate-to-source voltage (VGS) of the MOSFET. The gate-to-source voltage is equal to
VCC of the UCC27714 minus the drop across the bootstrap diode of the high-side driver in the UCC27714.
The waveforms reveal that the VGS is approximately 14.6 V.
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The voltage of the signal generator is set to 10 Vp-p and applied to the L1 and N terminals of the circuit
once all other connections have been made. As shown in Figure 39, the DC_Link ripple for this circuit is
approximately 0.219 Vp-p. With an input of 10 V, this makes the ripple of 2.19%.
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Table 7 also shows key testing parameters of the power supply and their respective values.
WARNING
The full-scale DC voltage value at the DC_Link should only be
acquired and tested by a professional, as this creates a serious
shock hazard to the user. Any unintended contact with the high
voltage sections of the board can cause serious harm or death.
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CAUTION
Two separate oscilloscopes are used in the test shown in Figure 40 to keep the
grounds of each power source isolated from the other. Damage may occur if
the oscilloscope is used to read both signals simultaneously.
Figure 41 shows the oscilloscope results for the control board side of the circuit. The voltage level has an
RMS value of 26.373 V with a peak value of 39.9 V. This voltage source is used to drive the internal
optical circuitry to turn on the transistor. The sinusoidal input signal creates a pulsed signal on the input to
the MCU.
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The transistor of the optocoupler is turned "on" once the threshold voltage of the transistor is reached.
Figure 42 shows the output of the optocoupler into the MSP430F5132. This rectified wave has a minimum
value of 581 mV and an RMS voltage of 943 mV, and has a synchronous frequency with that of the 24-V
AC air handler input signal. Once the signal drops below a preset threshold on the input of the MCU, the
speed assigned to that specific input pin can begin execution. In this test, the voltage drops from a DC
value of 3.3 V to an AC signal with an average maximum voltage of 1.15 V over roughly 1.5k samples. In
the event of a no control signal, the pulsed output of the optocoupler stops and the voltage returns to the
3.3 V provided by the pullup resistor network. This simulates the control board relaying to the ECM motor
that the temperature requirement on the thermostat has been reached. If the fan is on "AUTO" it shuts off.
If the fan is on, it remains running regardless of the cooling or heating cycle.
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Figure 43. Motor Winding Current and Current Sense Amplifier Output
As previously mentioned, the threshold voltage of the MCU is set to 2.5 V and the current limit is set at
±10 A. To test and verify simply and safely with respect to functionality, the comparator value is set to 1.5
V with an overcurrent at 1.25 A. Figure 44 shows the current limit operation in action. The PWM is turning
off immediately when the comparator output goes high.
Figure 44. Cycle-By-Cycle Current Limit Showing the PWM Shutdown With Comparator Output of
MSP430F5132
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Figure 45 shows the response time of the current limit action of the design. The response time from the
comparator output going high to PWM shut down event is approximately 100 ns.
Figure 45. Response Time From Comparator Goes High To PWM Shutdown
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The best sampling point is at the mid of the PWM on period, where the oscillations are damping down. At
low duty cycles, the sampling point can be moved towards 75% of the PWM on period. Figure 47 shows
the winding voltage of the non-switching phase in a low inductance motor. When the motor inductance is
very low, the oscillations are small and are getting damped out very soon. Therefore, the ADC sampling
can be done at even 25% of the PWM on period.
Figure 47. Oscillations in Winding Voltage Feedback for Low inductance Motor
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4 Design Files
4.1 Schematics
To download the schematics, see the design files at TIDA-01353.
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5 Related Documentation
1. Texas Instruments, MSP430F51x2 and MSP430F51x1 Mixed Signal Microcontrollers, MSP430F5132
Datasheet (SLAS619)
2. Texas Instruments, UCC27714 High-Speed, 600-V High-Side Low-Side Gate Driver with 4-A Peak
Output, UCC27714 Datasheet (SLUSBY6)
3. Texas Instruments, Sensorless Trapezoidal Control of BLDC Motors, Application Report (SPRABQ7)
4. Texas Instruments, UCC28881 700-V, 225-mA Low Quiescent Current Off-Line Converter, UCC28881
Datasheet (SLUSC36)
5. Texas Instruments, Op Amps for Everyone, Design Reference (SLOD006)
6. Texas Instruments, Analog Temperature Sensors with Class-AB Output, LMT84 Datasheet (SNIS167)
7. Texas Instruments, 230-V/250-W, Hi-η Sensorless Brushless DC Motor Drive With 30% Reduced Bulk
Capacitor Reference Design, TIDA-00472 Design Guide (TIDUAR7)
8. Texas Instruments, WEBENCH Design Center (http://www.ti.com/webench)
5.1 Trademarks
All trademarks are the property of their respective owners.
6 Terminology
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Revision A History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
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