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    Half Adder

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    Sanjay

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    © All Rights Reserved
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    Half Adder

    Uploaded by

    Sanjay
    5 views10 pages

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    half adder

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    Half Adder

    Uploaded by

    Sanjay

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    © All Rights Reserved
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    of 10

    Design of Arithmetic Logic Circuit using IC’s-

    Half Adder
    (Data Processing in Micro-controller Applications)

    Aim:

    To design, simulate, and verify a half adder used in the Arithmetic logic circuit,
    using ICs.

    Software required:

    LTspice software

    Theory:

    Adders form a core component of the Arithmetic Logic Unit (ALU) and play a
    major role in calculating memory addresses, table indices, etc.

    A half adder is the simplest digital adder. It is a combinational circuit that


    performs the addition of two binary digits. It takes in two input bits, A (addend)
    and B (augend), and produces two output bits, the sum, and the carry. The truth
    table for adding two binary digits A and B is shown below:

    Truth Table for Half Adder:

    A B SUM CARRY
    0 0 0 0
    0 1 1 0
    1 0 1 0
    1 1 0 1
    The simplified Boolean functions from the truth table are:

    ̅B + AB
    SUM = A ̅

    CARRY = AB

    Boolean expressions can be implemented in different ways. Below example


    shows the implementation of Half Adder using EX-OR and AND logic gates:

    Implementation of Half Adder using EX-OR and AND logic gates

    XOR
    A 1

    2
    3
    Sum
    B
    7486

    AND
    12

    13
    11
    Carry
    7408

    Note: can try alternative ways to implement a Half Adder by

    a) Using AND-NOR-NOR configuration

    b) Using only AND, OR, and NOT logic

    Procedure

    1) Open LTspice. Go to File – New Schematic.


    2) On the File Menu, click on Edit – Component.

    3) Place XOR gate, AND gate, two resistors, and ground on to schematic.
    4) Place two voltage sources for the two inputs on the schematic.

    5) Make necessary connections as per the circuit diagram. The first


    resistance is connected to the XOR output. The second resistance is
    connected to the AND gate output. Common terminal of both resistances
    are to be grounded. Voltage source 1 – positive terminal acts as 1st input,
    the other terminal is to be grounded; Voltage source 2 – positive terminal
    acts as 2nd input, the other terminal is to be grounded.
    6) Right-click on the resistance and change its value to 440Ω. Repeat the step
    for the other resistance also.

    7) Provide input to the XOR gate. Right click on the first voltage source.

    Select PULSE (V1 V2 Tdelay Trise Tfall Ton Period Ncycles).

    Set the values as (0, 1, 0, 1ns, 1ns, 1ms, 2 ms).


    8) Provide input to the AND gate. Right-click on the first voltage source.

    Select PULSE (V1 V2 Tdelay Trise Tfall Ton Period Ncycles).

    Set the values as (0, 1, 0, 1ns, 1ns, 2ms, 4ms).


    9) Go to Edit – SPICE analysis. Set the stop time to 4 ms

    10) Run the simulation (run symbol on menu bar).


    11) To view the results, right click – Add Plot Pane (add 4 plot panes to
    view the two inputs, sum and carry).

    For each pane, right click – Add Trace – Select V(<<respective


    node>>).

    (nodes correspond to A, B, sum and carry)


    12) Observe the waveforms and verify the truth table.
    0 0
    1 1

    0 0
    1 1

    0 0
    1 1

    0 0 0
    1

    Results and Inferences:


    Thus, a half adder circuit to implement addition operation in the ALU circuit
    using Exclusive-OR and AND gates is designed and implemented.
    Practical Applications:
    Data processing in micro-controller.

    Course Outcome:
    CO4. Design and implement various digital circuits
    Student Learning Outcomes (SLO):
    SLO2. Having a clear understanding of the subject related concepts and of contemporary
    issues

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