Cyborg - TGL REVA00

5 4 3 2 1
Cyborg-N/V/L 14/15_TGL-U &

D D
Watchmen 14N TGL-U Schematic

C C
2021-01-07
REV : A00
B B
DY : None Installed <Core Design>
A
UMA: Unified Memory Architecture Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A
OPS: Optimal Playable Settings Title

Taipei Hsien 221, Taiwan, R.O.C.
Cover Page
Size Document Number Rev
A4 Cyborg TGL SC
Date: Thursday, January 14, 2021 Sheet 1 of 105
5 4 3 2 1
5 4 3 2 1
Cyborg N/V/L & Watchmen 14 TGL Block Diagram
D GPU D
DDR4
GDDR5 NVIDIA PCIE Gen4x4
2GB
N17S-G5 Channel A SODIMM
VRAM(GDDR5) *2 N18S-G5
81,82 76-80
12
eDP x2
DDR4
14"/15" LCD Intel CPU Channel B SODIMM
I2C
55 13
Tiger Lake U
USB2.0 x1 1 PCIE4.0 * 4 Lanes
CCD/DMIC
Re-Timer
(HD Camera) DMIC TCSS DP 1.4/USB3.0
55 BURNSIDE-BRIDGE 8010
USB 4
73 USB 4.0 Type-C
2CH SPEAKER Audio Codec DMIC Rserve (total bandwidth 20Gbps)
(2CH 2W/4ohm) REALTEK 27 TGL PCH-LP PD Controller
I2C CC1/CC2
29
ALC3204 HDA
12 PCIe*3.0 Lanes CYPRESS
CYPD6127
2 SATA Lanes USB2.0
USB2.0
IO Board 4 USB3.1 Gen1/Gen2 Lanes
72
73
Universal Jack 10 USB2.0/1.1 Lanes

C C
HDMI
CNVI 2.0 HDMI 1.4a
Finger Print USB2.0 (Not support 4K2K)
High Definition Audio 57
(Remove SD/EMMC)
PCIE 4.0 x4 M.2 NGFF/NvMe
For CBG-V/L
RJ45 Conn LAN 10/100/1000 PCIE SSD 63
Realtek RTL8111H
PCIEx2 M.2 NGFF/NvMe For CBG 15-N/V
SSD 63
USB2.0
For CBG-L USB2.0
Port3 SATA For CBG L
HDD 60
USB 3.2 Gen1
Re-driver PCIE/USB2.0
USB3.0 PARADE USB3.0
USB3.2 PS8719BT NGFF WLAN
Gen1 CNVi 61
USB2.0
USB3.0
For CBG 15-N/V SD Card CardReader USB3.2
SD 3.0 USB2.0 Gen1
USB2.0
For CBG 14-N/V/L
Micro SD Card Realtek 35
CBG 15-L RTS5144
Sensor BD on Watchmen CBG L using 8 Bits:074.LNG2D.00BZ
CBG N/V using 12 Bits :074.LIS2D.M002
LID SENSOR Panel side
B For CBG-N/V/L S-5712ACDL1 INT E-compass Gyro+G B
Free Fall Gsensor
For Watchmen GMR SENSOR ST
LIS2MDL
ST
LSM6DS3
ST LNG2DMTR 70
HGDEDM013A
KBC
WWAN BD
For CBG-L I2C
KBC NGFF WWAN For CBG-NV: 32M SOIC 8/ NON RPMC

IO expander eSIM SPI BIOS ROM 25 For CBG-L: 32M WSON/ RPMC
I2C WWAN/LTE 32MB
IT8010FN
PCIe x 1
TPM 91 For CBG-V/L
I2C Touch PAD

eSPI debug port eSPI Bus
65
68
INT
Batt Conn KBC

Charger
SMBUS PS2
ISL9538C MICROCHIP
DC Jack MEC1515H-D0-I Fan Control
PWM FAN
Thermal SMBUS 26
A NUVOTON A
NCT7718W 26 24
Keyboard 65
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
Block Diagram
Custom Cyborg TGL SC
5 4 3 2 1
5 4 3 2 1
D D
1D05V_VCCSTG
20191121 Follow upsell
Follow Nakia change R311 from 100k to 51
20191217
R301 1 2 1KR2F-3-GP EAR_N_TEST_NCTF
Follow PDG change to 100
1D05V_VCCSTG_TERM
R311 1 2 100R2J-2-GP XDP_TDO_CPU
R308 1 2 51R2J-2-GP XDP_PREQ#

1D05V_VCCSTG_TERM DY
R312 1 2 51R2J-2-GP XDP_TDI
R302 1 2 1KR2F-3-GP PROCHOT#_CPU
XDP
R313 1 2 51R2J-2-GP XDP_TMS
1D05V_VCCST XDP
R304 1 2 1KR2F-3-GP THERMTRIP#_CPU
R307 1 2 1KR2F-3-GP CPU_CATERR
XDP_TCLK R310 1 2 51R2J-2-GP

CPU_POPI_RCOMP R305 1 2 49D9R2F-GP
XDP
C RN304 C
[24] PECI_CPU PCH_OPI_RCOMP XDP_TRST#
R306 1 2 49D9R2F-GP 1 4
PCH_TCK 2 3
[15] DBG_PMODE DY
SRN51J-GP
[22,24,44,46,72] PROCHOT#_CPU
[24,65] TOUCHPAD_INTR# CPU1U 21 OF 21

[79] GPU_EVENT#
CPU_CATERR M7 K4 XDP_TRST# 1
PECI_CPU CATERR# PROC_TRST# XDP_TMS TP309
BK9 B9 1
PROCHOT#_CPU PROCHOT#_CPU_R PECI PROC_TMS XDP_TDO_CPU TP310
R303 1 2 499R2F-2-GP E2 D12 1
THERMTRIP#_CPU PROCHOT# PROC_TDO XDP_TDI TP311
M5 A12 1
THRMTRIP# PROC_TDI XDP_TCLK TP312
B6 1
CPU_POPI_RCOMP PROC_TCK TP313
CT39
PCH_OPI_RCOMP CB9 PROC_POPIRCOMP D8
CW12 PCH_OPIRCOMP PCH_JTAGX A9
[55] TOUCH_PANEL_DET#
CM39 TP#CW12
TP#CM39
PCH_TMS
PCH_TDO
E12 XDP
DB42: TOUCH_PANEL_DET# B12
DF8: TOUCH_PANEL_PD# DBG_PMODE DF4 PCH_TDI A7 PCH_TCK 1
DBG_PMODE PCH_TCK TP314
H4
TOUCH_PANEL_DET# DB42 PCH_TRST#
TOUCHPAD_INTR# 1 2 TOUCH_PAD_INTR# DB41 GPP_B4/CPU_GP3 C11 XDP_PREQ# 1
TOUCH_PANEL_PD# GPP_B3/CPU_GP2 PROC_PREQ# XDP_PRDY# TP303
[55] TOUCH_PANEL_PD# R315 DF8 D11 1
GPP_E7/CPU_GP1 PROC_PRDY# TP302
0R0402-PAD-7-NP-GP DU5
GPP_E3/CPU_GP0 G1 EAR_N_TEST_NCTF
DF31 EAR_N/EAR_N_TEST_NCTF
B DV32 GPP_H2 DT15 B
DW32 GPP_H1 GPP_F7 DR15 GC6_EVENT# R316 1 2 0R2J-2-GP GPU_EVENT#
GPP_H0 GPP_F9 DT14
3D3V_S0 DJ27 GPP_F10 OPS_N17
20191224 GPP_H19/TIME_SYNC0
1: Non Touch Panel
1
0: Touch Panel
TGL-U-1-GP-U2
R309
100KR2J-1-GP
TOUCH_PANEL_DET#
2
www.teknisi-indonesia.com
A
<Core Design> A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Title
Title
CPU (THML/JTAG)
Size
Size DocumentNumber
Document Number Rev
Rev
A3 Cyborg TGL SC
Date: Thursday, January 14, 2021
Date: Sheet
Sheet 3 of 105
5 4 3 2 1
5 4 3 2 1
eDP
[55] eDP_TX_CPU_N0
[55] eDP_TX_CPU_P0
[55] eDP_TX_CPU_N1
[55] eDP_TX_CPU_P1
D [55] eDP_AUX_CPU_N D
[55] eDP_AUX_CPU_P
[55] EDP_HPD CPU1A 1 OF 21
[24] L_BKLT_EN
[55] eDP_VDD_EN
[55] L_BKLT_CTRL
AC2 AY2 USB1_TCSS_RX_P1 20191211
DDIA_TXP3 TCP0_TXRX_P1 USB1_TCSS_RX_N1 for TBT
AC1 AY1
AD2 DDIA_TXN3 TCP0_TXRX_N1 BB1 USB1_TCSS_RX_P0
HDMI AD1 DDIA_TXP2
DDIA_TXN2
TCP0_TXRX_P0
TCP0_TXRX_N0
BB2 USB1_TCSS_RX_N0
eDP_TX_CPU_P1 AF1 AM5 USB1_TCSS_TX_P1
[57] HDMI_DDI_TX_P3
eDP_TX_CPU_N1 AF2 DDIA_TXP1 TCP0_TX_P1 AM7 USB1_TCSS_TX_N1 TBT
[57]
[57]
HDMI_DDI_TX_N3
HDMI_DDI_TX_P0
eDP eDP_TX_CPU_P0 AG2 DDIA_TXN1
DDIA_TXP0
TCP0_TX_N1
TCP0_TX_P0
AT7 USB1_TCSS_TX_P0
eDP_TX_CPU_N0 AG1 AT5 USB1_TCSS_TX_N0
[57] HDMI_DDI_TX_N0 DDIA_TXN0 TCP0_TX_N0 AP7 USB1_TCSS_AUX_P
[57] HDMI_DDI_TX_P1 TCP0_AUX_P
eDP_AUX_CPU_P AJ2 AP5 USB1_TCSS_AUX_N
[57] HDMI_DDI_TX_N1 DDIA_AUX_P TCP0_AUX_N
eDP_AUX_CPU_N AJ1
[57] HDMI_DDI_TX_P2 DDIA_AUX_N
[57] HDMI_DDI_TX_N2 AT2
W W AN_GPIO_PERST# DN4 TCP1_TXRX_P1 AT1
W W AN_FULL_PW R_EN_R R408 1 2W W AN_FULL_PW R_EN DT6 GPP_E22/DDPA_CTRLCLK/DNX_FORCE_RELOAD TCP1_TXRX_N1 AU1
[57] HDMI_SCL_CPU GPP_E23/DDPA_CTRLDATA TCP1_TXRX_P0
WWAN 0R0402-PAD-7-NP-GP AU2
[57] HDMI_SDA_CPU EDP_HPD TCP1_TXRX_N0
DR5 AD5
[57] CPU_DISP_HPDB
eDP GPP_E14/DDSP_HPDA/DISP_MISCA TCP1_TX_P1
TCP1_TX_N1
AD7
HDMI_DDI_TX_P3 T12 AH7
HDMI_DDI_TX_N3 T11 DDIB_TXP3 TCP1_TX_P0 AH5
DDIB_TXN3 TCP1_TX_N0
TBT HDMI_DDI_TX_P0
HDMI_DDI_TX_N0
Y11
Y9 DDIB_TXP2 TCP1_AUX_P
AF7
AF5
HDMI_DDI_TX_P1 T9 DDIB_TXN2 TCP1_AUX_N
[71] USB1_TCSS_TX_N0
C HDMI_DDI_TX_N1 P9 DDIB_TXP1 BF1 C
[71] USB1_TCSS_TX_P0 DDIB_TXN1 TCP2_TXRX_P1
[71] USB1_TCSS_TX_N1 HDMI_DDI_TX_P2 V11 BF2
HDMI_DDI_TX_N2 V9 DDIB_TXP0 TCP2_TXRX_N1 BE2
[71] USB1_TCSS_TX_P1 DDIB_TXN0 TCP2_TXRX_P0 BE1
[71]
[71]
USB1_TCSS_RX_N0
USB1_TCSS_RX_P0 HDMI AB9
DDIB_AUX_P
TCP2_TXRX_N0
TCP2_TX_P1
BD7
[71] USB1_TCSS_RX_N1 AD9 BD5
DDIB_AUX_N TCP2_TX_N1 AY5
[71] USB1_TCSS_RX_P1 TCP2_TX_P0
HDMI_SCL_CPU DM29 AY7
HDMI_SDA_CPU DK27 GPP_H16/DDPB_CTRLCLK/PCIE_LNK_DOWN TCP2_TX_N0 BB5
GPP_H17/DDPB_CTRLDATA TCP2_AUX_P BB7
[71] USB1_TCSS_TXD TCP2_AUX_N
[15,71] USB1_TCSS_RXD DN4: WWAN_GPO_PEREST# CPU_DISP_HPDB DG43
DT6: WWAN_CARD_PWR_OFF# GPP_A18/DDSP_HPDB/DISP_MISCB/I2S4_RXD BK1
DG47: 3.3V_CAM_EN DG47 TCP3_TXRX_P1 BK2
[71] USB1_TCSS_AUX_P GPP_A21/DDPC_CTRLCLK/I2S5_TXD TCP3_TXRX_N1
[71] USB1_TCSS_AUX_N DF6: TBT_LSX1_TXD KB_DET# DJ47 BJ2
DN23: SENSOR_DB_DET# GPP_A22/DDPC_CTRLDATA/I2S5_RXD TCP3_TXRX_P0 BJ1
DD6: TBT_LSX1_RXD USB1_TCSS_TXD DU8 TCP3_TXRX_N0 BM7
DK23: CPU_DDP4_CTRL_CLK
DN21: CPU_DDP4_CTRL_DATA
TBT USB1_TCSS_RXD DV8 GPP_E18/DDP1_CTRLCLK/TBT_LSX0_TXD
GPP_E19/DDP1_CTRLDATA/TBT_LSX0_RXD
TCP3_TX_P1
TCP3_TX_N1
BM5
[72] USB_OC2# 20191211 BH5
DF47: CPU_DISP_HPD2 for TBT DF6 TCP3_TX_P0 BH7
DH52: USB_OC1# GPP_E21 DD6 GPP_E20/DDP2_CTRLCLK/TBT_LSX1_TXD TCP3_TX_N0 BK5
DK45: CPU_DISP_HPD4 GPP_E21/DDP2_CTRLDATA/TBT_LSX1_RXD TCP3_AUX_P BK7
DN23 TCP3_AUX_N
GPP_D10 DM23 GPP_D9/ISH_SPI_CS#/DDP3_CTRLCLK/TBT_LSX2_TXD/GSPI2_CS0# AN2 TCSS_RCOMP_P
GPP_D10/ISH_SPI_CLK/DDP3_CTRLDATA/TBT_LSX2_RXD/GSPI2_CLK TC_RCOMP_P AN1 TCSS_RCOMP_N R402 1 2 150R2F-1-GP
Other DK23
GPP_D11/ISH_SPI_MISO/DDP4_CTRLCLK/TBT_LSX3_TXD/GSPI2_MISO
TC_RCOMP_N
GPP_D12 DN21 M8
GPP_D12/ISH_SPI_MOSI/DDP4_CTRLDATA/TBT_LSX3_RXD/GSPI2_MOSI DSI_DE_TE_2
[15] GPP_E21 DISP_RCOMP
DF43 AB1 R401 1 2 150R2F-1-GP
CPU_DISP_HPD1 DF45 GPP_A17/DISP_MISCC/I2S4_TXD DDI_RCOMP
B [15] GPP_D12 GPP_A19/DDSP_HPD1/DISP_MISC1/I2S5_SCLK B
DF47 CE4
GPP_A20/DDSP_HPD2/DISP_MISC2/I2S5_SFRM DISP_UTILS/DSI_DE_TE_1
[15] GPP_D10 USB_OC1# DH52
USB_OC2# DK45 GPP_A14/USB_OC1#/DDSP_HPD3/I2S3_RXD/DISP_MISC3/DMIC_CLK_B1
[65] KB_DET# GPP_A15/USB_OC2#/DDSP_HPD4/DISP_MISC4/I2S4_SCLK
eDP_VDD_EN DM8
L_BKLT_EN DN8 EDP_VDDEN
eDP L_BKLT_CTRL DG10 EDP_BKLTEN
EDP_BKLTCTL
CPU_DISP_HPD1 R403 1 2
DY TGL-U-1-GP-U2
USB3.2 Type-A Port2 (IO) 100KR2J-1-GP
[66] USB_OC1#
20191129
3D3V_S0
layout Request Add RTC Gen 9 reset circuit_20170814
RN402 leakage issue 20191224
2 3 HDMI_SCL_CPU Follow Internal review
[62] W W AN_GPIO_PERST#
1 4 HDMI_SDA_CPU 3D3V_S5_VCCPRIM
3D3V_S5_VCCPRIM
[62] W W AN_FULL_PW R_EN_R SRN2K2J-1-GP
R419 1 2 10KR2J-3-GP KB_DET#

1
1
R405
R406 10KR2J-3-GP
10KR2J-3-GP
DY_RTC_RST
A DY_RTC_RST <Core Design> A
2
Q401
2
1 6 CPU_DISP_HPD1
Wistron Corporation
Note:ZZ.27002.F7C01
2 5 75.27002.F7C 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

2nd = 075.27002.0E7C Taipei Hsien 221, Taiwan, R.O.C.
3D3V_S5_VCCPRIM 20191211 CPU_DISP_HPD1_P3 4 3rd = 075.07002.0A7C
Title
Title
R421 1
Remove R422
2 USB_OC1# 2N7002KDW-1-GP
CPU (DDI/EDP/TBT/TPC/)
10KR2J-3-GP DY_RTC_RST Size
Size DocumentNumber
Document Number Rev
Rev
20191224
Follow Internal review
A3 Cyborg TGL SC
Date: Sheet
Sheet 4 of 105
5 4 3 2 1
5 4 3 2 1
Channel A DDR4 ball type: Non-Interleaved Type

CPU1C 3 OF 21
M_A_DQ0 [12] CPU1B 2 OF 21
M_A_DQ1 [12]
M_A_A0 [12] M_A_DQ2 [12] LP4-LP5(NIL)/DDR4 (NIL)/DDR4 (IL) DDR4/LP4/LP5/LP5 CMD
M_A_A1 [12] M_A_DQ3 [12] LP4-LP5(NIL)/DDR4 (NIL)/DDR4 (IL) DDR4/LP4/LP5/LP5 CMD Flip M_B_DQ7 AL53 Flip R41 M_B_CLK1
M_A_A2 [12] M_A_DQ4 [12] M_A_DQ7 CP53 BT42 M_A_CLK1 M_B_DQ6 AL52 DDR4_DQ0_7/DDR1_DQ0_7/DDR0_DQ4_7 DDR1_CLK_P1/DDR7_CLK_P/DDR7_CLK_P/DDR7_CLK_P R42 M_B_CLK#1
M_A_A3 [12] M_A_DQ5 [12] M_A_DQ6 CP52 DDR0_DQ0_7/DDR0_DQ0_7/DDR0_DQ0_7 DDR0_CLK_P1/DDR3_CLK_P/DDR3_CLK_P/DDR3_CLK_P BT41 M_A_CLK#1 M_B_DQ5 AL50 DDR4_DQ0_6/DDR1_DQ0_6/DDR0_DQ4_6 DDR1_CLK_N1/DDR7_CLK_N/DDR7_CLK_N/DDR7_CLK_N M52
M_A_A4 [12] M_A_DQ6 [12] M_A_DQ5 CP50 DDR0_DQ0_6/DDR0_DQ0_6/DDR0_DQ0_6 DDR0_CLK_N1/DDR3_CLK_N/DDR3_CLK_N/DDR3_CLK_N BP52 M_B_DQ4 AL49 DDR4_DQ0_5/DDR1_DQ0_5/DDR0_DQ4_5 NC/DDR6_CLK_P/DDR6_CLK_P/DDR6_CLK_P M53
M_A_A5 [12] M_A_DQ7 [12] M_A_DQ4 CP49 DDR0_DQ0_5/DDR0_DQ0_5/DDR0_DQ0_5 NC/DDR2_CLK_P/DDR2_CLK_P/DDR2_CLK_P BP53 M_B_DQ3 AP53 DDR4_DQ0_4/DDR1_DQ0_4/DDR0_DQ4_4 NC/DDR6_CLK_N/DDR6_CLK_N/DDR6_CLK_N AC42
M_A_A6 [12] M_A_DQ8 [12] M_A_DQ3 CU53 DDR0_DQ0_4/DDR0_DQ0_4/DDR0_DQ0_4 NC/DDR2_CLK_N/DDR2_CLK_N/DDR2_CLK_N CD42 M_B_DQ2 AP52 DDR4_DQ0_3/DDR1_DQ0_3/DDR0_DQ4_3 NC/DDR5_CLK_P/DDR5_CLK_P/DDR5_CLK_P AC41
M_A_A7 [12] M_A_DQ9 [12] M_A_DQ2 CU52 DDR0_DQ0_3/DDR0_DQ0_3/DDR0_DQ0_3 NC/DDR1_CLK_P/DDR1_CLK_P/DDR1_CLK_P CD41 M_B_DQ1 AP50 DDR4_DQ0_2/DDR1_DQ0_2/DDR0_DQ4_2 NC/DDR5_CLK_N/DDR5_CLK_N/DDR5_CLK_N Y52 M_B_CLK0
M_A_A8 [12] M_A_DQ10 [12] M_A_DQ1 CU50 DDR0_DQ0_2/DDR0_DQ0_2/DDR0_DQ0_2 NC/DDR1_CLK_N/DDR1_CLK_N/DDR1_CLK_N CC52 M_A_CLK0 M_B_DQ0 AP49 DDR4_DQ0_1/DDR1_DQ0_1/DDR0_DQ4_1 DDR1_CLK_P0/DDR4_CLK_P/DDR4_CLKP/DDR4_CLK_P Y53 M_B_CLK#0
M_A_A9 [12] M_A_DQ11 [12] M_A_DQ0 CU49 DDR0_DQ0_1/DDR0_DQ0_1/DDR0_DQ0_1 DDR0_CLK_P0/DDR0_CLK_P/DDR0_CLK_P/DDR0_CLK_P CC53 M_A_CLK#0 M_B_DQ15 AF53 DDR4_DQ0_0/DDR1_DQ0_0/DDR0_DQ4_0 DDR1_CLK_N0/DDR4_CLK_N/DDR4_CLK_N/DDR4_CLK_N
D M_A_A10 [12] M_A_DQ12 [12] M_A_DQ15 CH53 DDR0_DQ0_0/DDR0_DQ0_0/DDR0_DQ0_0 DDR0_CLK_N0/DDR0_CLK_N/DDR0_CLK_N/DDR0_CLK_N M_B_DQ14 AF52 DDR4_DQ1_7/DDR1_DQ1_7/DDR0_DQ5_7 R47 D
M_A_A11 [12] M_A_DQ13 [12] M_A_DQ14 CH52 DDR0_DQ1_7/DDR0_DQ1_7/DDR0_DQ1_7 BT45 M_B_DQ13 AF50 DDR4_DQ1_6/DDR1_DQ1_6/DDR0_DQ5_6 NC/DDR7_CKE0/DDR7_WCK_P/DDR7_WCK_P R45
M_A_A12 [12] M_A_DQ14 [12] M_A_DQ13 CH50 DDR0_DQ1_6/DDR0_DQ1_6/DDR0_DQ1_6 NC/DDR3_CKE0/DDR3_WCK_P/DDR3_WCK_P BT47 M_B_DQ12 AF49 DDR4_DQ1_5/DDR1_DQ1_5/DDR0_DQ5_5 NC/DDR7_CKE1/DDR7_WCK_N/DDR7_WCK_N K51
M_A_A13 [12] M_A_DQ15 [12] M_A_DQ12 CH49 DDR0_DQ1_5/DDR0_DQ1_5/DDR0_DQ1_5 NC/DDR3_CKE1/DDR3_WCK_N/DDR3_WCK_N BN51 M_B_DQ11 AH53 DDR4_DQ1_4/DDR1_DQ1_4/DDR0_DQ5_4 NC/DDR6_CKE0/DDR6_WCK_P/DDR6_WCK_P K53
M_A_A14 [12] M_A_DQ16 [12] M_A_DQ11 CL53 DDR0_DQ1_4/DDR0_DQ1_4/DDR0_DQ1_4 NC/DDR2_CKE0/DDR2_WCK_P/DDR2_WCK_P BN53 M_B_DQ10 AH52 DDR4_DQ1_3/DDR1_DQ1_3/DDR0_DQ5_3 NC/DDR6_CKE1/DDR6_WCK_N/DDR6_WCK_N AC47
M_A_A15 [12] M_A_DQ17 [12] M_A_DQ10 CL52 DDR0_DQ1_3/DDR0_DQ1_3/DDR0_DQ1_3 NC/DDR2_CKE1/DDR2_WCK_N/DDR2_WCK_N CD45 M_B_DQ9 AH50 DDR4_DQ1_2/DDR1_DQ1_2/DDR0_DQ5_2 NC/DDR5_CKE0/DDR5_WCK_P/DDR5_WCK_P AC45
M_A_A16 [12] M_A_DQ18 [12] M_A_DQ9 CL50 DDR0_DQ1_2/DDR0_DQ1_2/DDR0_DQ1_2 NC/DDR1_CKE0/DDR1_WCK_P/DDR1_WCK_P CD47 M_B_DQ8 AH49 DDR4_DQ1_1/DDR1_DQ1_1/DDR0_DQ5_1 NC/DDR5_CKE1/DDR5_WCK_N/DDR5_WCK_N W51
M_A_DQ19 [12] M_A_DQ8 CL49 DDR0_DQ1_1/DDR0_DQ1_1/DDR0_DQ1_1 NC/DDR1_CKE1/DDR1_WCK_N/DDR1_WCK_N CA51 M_B_DQ23 AR41 DDR4_DQ1_0/DDR1_DQ1_0/DDR0_DQ5_0 NC/DDR4_CKE0/DDR4_WCK_P/DDR4_WCK_P W53
M_A_DQ20 [12] M_A_DQ23 CT47 DDR0_DQ1_0/DDR0_DQ1_0/DDR0_DQ1_0 NC/DDR0_CKE0/DDR0_WCK_P/DDR0_WCK_P CA53 M_B_DQ22 AV42 DDR5_DQ0_7/DDR1_DQ2_7/DDR1_DQ4_7 NC/DDR4_CKE1/DDR4_WCK_N/DDR4_WCK_N
M_A_DQ21 [12] M_A_DQ22 CV47 DDR1_DQ0_7/DDR0_DQ2_7/DDR1_DQ0_7 NC/DDR0_CKE1/DDR0_WCK_N/DDR0_WCK_N M_B_DQ21 AR42 DDR5_DQ0_6/DDR1_DQ2_6/DDR1_DQ4_6 P52 M_B_CKE1
M_A_DQS_DP0 M_A_DQ22 [12] M_A_DQ21 CT45 DDR1_DQ0_6/DDR0_DQ2_6/DDR1_DQ0_6 BU52 M_A_CKE1 M_B_DQ20 AV41 DDR5_DQ0_5/DDR1_DQ2_5/DDR1_DQ4_5 DDR1_CKE1/DDR6_CA4/DDR6_CA5/DDR6_CA1 J50 M_B_CKE0
M_A_DQS_DP0 [12]
M_A_DQS_DP1 M_A_DQ23 [12] M_A_DQ20 CV45 DDR1_DQ0_5/DDR0_DQ2_5/DDR1_DQ0_5 DDR0_CKE1/DDR2_CA4/DDR2_CA5/DDR2_CA1 BL50 M_A_CKE0 M_B_DQ19 AR45 DDR5_DQ0_4/DDR1_DQ2_4/DDR1_DQ4_4 DDR1_CKE0/DDR6_CA5/DDR6_CA6/DDR6_CA0
M_A_DQS_DP1 [12]
M_A_DQS_DP2 M_A_DQ24 [12] M_A_DQ19 CT42 DDR1_DQ0_4/DDR0_DQ2_4/DDR1_DQ0_4 DDR0_CKE0/DDR2_CA5/DDR2_CA6/DDR2_CA0 M_B_DQ18 AV45 DDR5_DQ0_3/DDR1_DQ2_3/DDR1_DQ4_3 AE42 M_B_CS#1
M_A_DQS_DP2 [12]
M_A_DQS_DP3 M_A_DQ25 [12] M_A_DQ18 CV42 DDR1_DQ0_3/DDR0_DQ2_3/DDR1_DQ0_3 CF42 M_A_CS#1 M_B_DQ17 AR47 DDR5_DQ0_2/DDR1_DQ2_2/DDR1_DQ4_2 DDR1_CS1/DDR5_CA1/DDR5_CA1/DDR5_CA5 AE47 M_B_CS#0
M_A_DQS_DP3 [12]
M_A_DQS_DP4 M_A_DQ26 [12] M_A_DQ17 CT41 DDR1_DQ0_2/DDR0_DQ2_2/DDR1_DQ0_2 DDR0_CS1/DDR1_CA1/DDR1_CA1/DDR1_CA5 CF47 M_A_CS#0 M_B_DQ16 AV47 DDR5_DQ0_1/DDR1_DQ2_1/DDR1_DQ4_1 DDR1_CS0/NC/DDR5_CS1/DDR5_CA4
M_A_DQS_DP4 [12]
M_A_DQS_DP5 M_A_DQ27 [12] M_A_DQ16 CV41 DDR1_DQ0_1/DDR0_DQ2_1/DDR1_DQ0_1 DDR0_CS0/NC/DDR1_CS1/DDR1_CA4 M_B_DQ31 AJ41 DDR5_DQ0_0/DDR1_DQ2_0/DDR1_DQ4_0 N42
M_A_DQS_DP5 [12]
M_A_DQS_DP6 M_A_DQ28 [12] M_A_DQ31 CK47 DDR1_DQ0_0/DDR0_DQ2_0/DDR1_DQ0_0 CE53 M_B_DQ30 AJ42 DDR5_DQ1_7/DDR1_DQ3_7/DDR1_DQ5_7 NC/DDR7_CA5/DDR7_CA6/DDR7_CA0 N45
M_A_DQS_DP6 [12]
M_A_DQS_DP7 M_A_DQ29 [12] M_A_DQ30 CM47 DDR1_DQ1_7/DDR0_DQ3_7/DDR1_DQ1_7 NC/DDR0_CA0/DDR0_CA0/DDR0_CA6 CE50 M_B_DQ29 AL41 DDR5_DQ1_6/DDR1_DQ3_6/DDR1_DQ5_6 NC/DDR7_CA4/DDR7_CA5/DDR7_CA1 N44
M_A_DQS_DP7 [12] M_A_DQ30 [12] M_A_DQ29 CK45 DDR1_DQ1_6/DDR0_DQ3_6/DDR1_DQ1_6 NC/DDR0_CA1/DDR0_CA1/DDR0_CA5 BL53 M_B_DQ28 AL42 DDR5_DQ1_5/DDR1_DQ3_5/DDR1_DQ5_5 NC/DDR7_CA3/DDR7_CA4/DDR7_CS1 N47
M_A_DQ31 [12] M_A_DQ28 CM45 DDR1_DQ1_5/DDR0_DQ3_5/DDR1_DQ1_5 NC/DDR2_CS0/DDR2_CA2/DDR2_CA2 BP47 M_B_DQ27 AJ45 DDR5_DQ1_4/DDR1_DQ3_4/DDR1_DQ5_4 NC/DDR7_CA2/DDR7_CA3/DDR7_CS0 J53
M_A_DQS_DN0 M_A_DQ32 [12] M_A_DQ27 CK42 DDR1_DQ1_4/DDR0_DQ3_4/DDR1_DQ1_4 NC/DDR3_CA5/DDR3_CA6/DDR3_CA0 BP42 M_B_DQ26 AJ47 DDR5_DQ1_3/DDR1_DQ3_3/DDR1_DQ5_3 NC/DDR6_CS0/DDR6_CA2/DDR6_CA2 AC50
M_A_DQS_DN1 M_A_DQS_DN0 [12]
M_A_DQS_DN1 [12]
M_A_DQ33 [12] M_A_DQ26 CM42 DDR1_DQ1_3/DDR0_DQ3_3/DDR1_DQ1_3 NC/DDR3_CA4/DDR3_CA5/DDR3_CA1 BP45 M_B_DQ25 AL45 DDR5_DQ1_2/DDR1_DQ3_2/DDR1_DQ5_2 NC/DDR4_CA1/DDR4_CA1/DDR4_CA5 AC53
M_A_DQS_DN2 M_A_DQ34 [12] M_A_DQ25 CM41 DDR1_DQ1_2/DDR0_DQ3_2/DDR1_DQ1_2 NC/DDR3_CA3/DDR3_CA4/DDR3_CS1 BP44 M_B_DQ24 AL47 DDR5_DQ1_1/DDR1_DQ3_1/DDR1_DQ5_1 NC/DDR4_CA0/DDR4_CA0/DDR4_CA6
M_A_DQS_DN3 [12]
M_A_DQ35 [12] M_A_DQ24 CK41 DDR1_DQ1_1/DDR0_DQ3_1/DDR1_DQ1_1 NC/DDR3_CA2/DDR3_CA3/DDR3_CS0 M_B_DQ39 A43 DDR5_DQ1_0/DDR1_DQ3_0/DDR1_DQ5_0 K36 M_B_DQS_DP7
M_A_DQS_DN4 M_A_DQ36 [12] M_A_DQ39 BF53 DDR1_DQ1_0/DDR0_DQ3_0/DDR1_DQ1_0 BB44 M_A_DQS_DP7 M_B_DQ38 B43 DDR6_DQ0_7/DDR1_DQ4_7/DDR0_DQ6_7 DDR7_DQSP_1/DDR1_DQSP_7/DDR1_DQSP_7 K38 M_B_DQS_DN7
M_A_DQS_DN5 [12]
M_A_DQ37 [12] M_A_DQ38 BF52 DDR2_DQ0_7/DDR0_DQ4_7/DDR0_DQ2_7 DDR3_DQSP_1/DDR0_DQSP_7/DDR1_DQSP_3 BD44 M_A_DQS_DN7 M_B_DQ37 D43 DDR6_DQ0_6/DDR1_DQ4_6/DDR0_DQ6_6 DDR7_DQSN_1/DDR1_DQSN_7/DDR1_DQSN_7 G44 M_B_DQS_DP6
M_A_DQS_DN6 M_A_DQ38 [12] M_A_DQ37 BF50 DDR2_DQ0_6/DDR0_DQ4_6/DDR0_DQ2_6 DDR3_DQSN_1/DDR0_DQSN_7/DDR1_DQSN_3 BK44 M_A_DQS_DP6 M_B_DQ36 E44 DDR6_DQ0_5/DDR1_DQ4_5/DDR0_DQ6_5 DDR7_DQSP_0/DDR1_DQSP_6/DDR1_DQSP_6 J44 M_B_DQS_DN6
M_A_DQS_DN7 [12]
M_A_DQ39 [12] M_A_DQ36 BF49 DDR2_DQ0_5/DDR0_DQ4_5/DDR0_DQ2_5 DDR3_DQSP_0/DDR0_DQSP_6/DDR1_DQSP_2 BH44 M_A_DQS_DN6 M_B_DQ35 A46 DDR6_DQ0_4/DDR1_DQ4_4/DDR0_DQ6_4 DDR7_DQSN_0/DDR1_DQSN_6/DDR1_DQSN_6 D39 M_B_DQS_DP5
M_A_DQ40 [12] M_A_DQ35 BH53 DDR2_DQ0_4/DDR0_DQ4_4/DDR0_DQ2_4 DDR3_DQSN_0/DDR0_DQSN_6/DDR1_DQSN_2 BA51 M_A_DQS_DP5 M_B_DQ34 B46 DDR6_DQ0_3/DDR1_DQ4_3/DDR0_DQ6_3 DDR6_DQSP_1/DDR1_DQSP_5/DDR0_DQSP_7 C39 M_B_DQS_DN5
M_A_DQ41 [12] M_A_DQ34 BH52 DDR2_DQ0_3/DDR0_DQ4_3/DDR0_DQ2_3 DDR2_DQSP_1/DDR0_DQSP_5/DDR0_DQSP_3 BA50 M_A_DQS_DN5 M_B_DQ33 D46 DDR6_DQ0_2/DDR1_DQ4_2/DDR0_DQ6_2 DDR6_DQSN_1/DDR1_DQSN_5/DDR0_DQSN_7 C45 M_B_DQS_DP4
M_A_DQ42 [12] M_A_DQ33 BH50 DDR2_DQ0_2/DDR0_DQ4_2/DDR0_DQ2_2 DDR2_DQSN_1/DDR0_DQSN_5/DDR0_DQSN_3 BG51 M_A_DQS_DP4 M_B_DQ32 E47 DDR6_DQ0_1/DDR1_DQ4_1/DDR0_DQ6_1 DDR6_DQSP_0/DDR1_DQSP_4/DDR0_DQSP_6 D45 M_B_DQS_DN4
M_A_DQ43 [12] M_A_DQ32 BH49 DDR2_DQ0_1/DDR0_DQ4_1/DDR0_DQ2_1 DDR2_DQSP_0/DDR0_DQSP_4/DDR0_DQSP_2 BG50 M_A_DQS_DN4 M_B_DQ47 E38 DDR6_DQ0_0/DDR1_DQ4_0/DDR0_DQ6_0 DDR6_DQSN_0/DDR1_DQSN_4/DDR0_DQSN_6 AJ44 M_B_DQS_DP3
M_A_DQ44 [12] M_A_DQ47 AY53 DDR2_DQ0_0/DDR0_DQ4_0/DDR0_DQ2_0 DDR2_DQSN_0/DDR0_DQSN_4/DDR0_DQSN_2 CK44 M_A_DQS_DP3 M_B_DQ46 D38 DDR6_DQ1_7/DDR1_DQ5_7/DDR0_DQ7_7 DDR5_DQSP_1/DDR1_DQSP_3/DDR1_DQSP_5 AL44 M_B_DQS_DN3
[12] M_A_CLK#0 [12] M_A_ODT0 M_A_DQ45 [12] M_A_DQ46 AY52 DDR2_DQ1_7/DDR0_DQ5_7/DDR0_DQ3_7 DDR1_DQSP_1/DDR0_DQSP_3/DDR1_DQSP_1 CM44 M_A_DQS_DN3 M_B_DQ45 B38 DDR6_DQ1_6/DDR1_DQ5_6/DDR0_DQ7_6 DDR5_DQSN_1/DDR1_DQSN_3/DDR1_DQSN_5 AV44 M_B_DQS_DP2
[12] M_A_ODT1 M_A_DQ46 [12] M_A_DQ45 AY50 DDR2_DQ1_6/DDR0_DQ5_6/DDR0_DQ3_6 DDR1_DQSN_1/DDR0_DQSN_3/DDR1_DQSN_1 CT44 M_A_DQS_DP2 M_B_DQ44 A38 DDR6_DQ1_5/DDR1_DQ5_5/DDR0_DQ7_5 DDR5_DQSP_0/DDR1_DQSP_2/DDR1_DQSP_4 AR44 M_B_DQS_DN2
[12] M_A_CLK0 M_A_DQ47 [12] M_A_DQ44 AY49 DDR2_DQ1_5/DDR0_DQ5_5/DDR0_DQ3_5 DDR1_DQSP_0/DDR0_DQSP_2/DDR1_DQSP_0 CV44 M_A_DQS_DN2 M_B_DQ43 E41 DDR6_DQ1_4/DDR1_DQ5_4/DDR0_DQ7_4 DDR5_DQSN_0/DDR1_DQSN_2/DDR1_DQSN_4 AG51 M_B_DQS_DP1
M_A_DQ48 [12] M_A_DQ43 BC53 DDR2_DQ1_4/DDR0_DQ5_4/DDR0_DQ3_4 DDR1_DQSN_0/DDR0_DQSN_2/DDR1_DQSN_0 CK51 M_A_DQS_DP1 M_B_DQ42 D40 DDR6_DQ1_3/DDR1_DQ5_3/DDR0_DQ7_3 DDR4_DQSP_1/DDR1_DQSP_1/DDR0_DQSP_5 AG50 M_B_DQS_DN1
[12] M_A_CKE0 [12] M_A_ACT_N M_A_DQ49 [12] M_A_DQ42 BC52 DDR2_DQ1_3/DDR0_DQ5_3/DDR0_DQ3_3 DDR0_DQSP_1/DDR0_DQSP_1/DDR0_DQSP_1 CK50 M_A_DQS_DN1 M_B_DQ41 B40 DDR6_DQ1_2/DDR1_DQ5_2/DDR0_DQ7_2 DDR4_DQSN_1/DDR1_DQSN_1/DDR0_DQSN_5 AN51 M_B_DQS_DP0
M_A_DQ50 [12] M_A_DQ41 BC50 DDR2_DQ1_2/DDR0_DQ5_2/DDR0_DQ3_2 DDR0_DQSN_1/DDR0_DQSN_1/DDR0_DQSN_1 CR51 M_A_DQS_DP0 M_B_DQ40 A40 DDR6_DQ1_1/DDR1_DQ5_1/DDR0_DQ7_1 DDR4_DQSP_0/DDR1_DQSP_0/DDR0_DQSP_4 AN50 M_B_DQS_DN0
[12] M_A_CKE1 [12] M_A_PARITY M_A_DQ51 [12] M_A_DQ40 BC49 DDR2_DQ1_1/DDR0_DQ5_1/DDR0_DQ3_1 DDR0_DQSP_0/DDR0_DQSP_0/DDR0_DQSP_0 CR50 M_A_DQS_DN0 M_B_DQ55 G42 DDR6_DQ1_0/DDR1_DQ5_0/DDR0_DQ7_0 DDR4_DQSN_0/DDR1_DQSN_0/DDR0_DQSN_4
M_A_DQ52 [12] M_A_DQ55 BK47 DDR2_DQ1_0/DDR0_DQ5_0/DDR0_DQ3_0 DDR0_DQSN_0/DDR0_DQSN_0/DDR0_DQSN_0 M_B_DQ54 G41 DDR7_DQ0_7/DDR1_DQ6_7/DDR1_DQ6_7 AE44 M_B_ODT1
[12] M_A_ALERT_N
C M_A_DQ53 [12] M_A_DQ54 BK45 DDR3_DQ0_7/DDR0_DQ6_7/DDR1_DQ2_7 CF44 M_A_ODT1 M_B_DQ53 J41 DDR7_DQ0_6/DDR1_DQ6_6/DDR1_DQ6_6 DDR1_ODT1/DDR5_CA0/DDR5_CA0/DDR5_CA6 AE45 M_B_ODT0 C
M_A_DQ54 [12] M_A_DQ53 BH47 DDR3_DQ0_6/DDR0_DQ6_6/DDR1_DQ2_6 DDR0_ODT1/DDR1_CA0/DDR1_CA0/DDR1_CA6 CF45 M_A_ODT0 M_B_DQ52 J42 DDR7_DQ0_5/DDR1_DQ6_5/DDR1_DQ6_5 DDR1_ODT0/DDR5_CS0/DDR5_CA2/DDR5_CA2
M_A_DQ55 [12] M_A_DQ52 BH45 DDR3_DQ0_5/DDR0_DQ6_5/DDR1_DQ2_5 DDR1_ODT0/DDR1_CS0/DDR1_CA2/DDR1_CA2 M_B_DQ51 G45 DDR7_DQ0_4/DDR1_DQ6_4/DDR1_DQ6_4 AA47 M_B_A16
M_A_CLK1 [12] M_A_DQ56 [12] M_A_DQ51 BH42 DDR3_DQ0_4/DDR0_DQ6_4/DDR1_DQ2_4 CB47 M_A_A16 M_B_DQ50 J45 DDR7_DQ0_3/DDR1_DQ6_3/DDR1_DQ6_3 DDR1_MA16/DDR5_CA4/DDR5_CA5/DDR5_CA1 AA44 M_B_A15
[12] M_A_CS#0 M_A_CLK#1 [12] M_A_DQ57 [12] M_A_DQ50 BK42 DDR3_DQ0_3/DDR0_DQ6_3/DDR1_DQ2_3 DDR0_MA16/DDR1_CA4/DDR1_CA5/DDR1_CA1 CB44 M_A_A15 M_B_DQ49 G47 DDR7_DQ0_2/DDR1_DQ6_2/DDR1_DQ6_2 DDR1_MA15/DDR5_CA3/DDR5_CA4/DDR5_CS1 AA45 M_B_A14
M_A_DQ58 [12] M_A_DQ49 BK41 DDR3_DQ0_2/DDR0_DQ6_2/DDR1_DQ2_2 DDR0_MA15/DDR1_CA3/DDR1_CA4/DDR1_CS1 CB45 M_A_A14 M_B_DQ48 J47 DDR7_DQ0_1/DDR1_DQ6_1/DDR1_DQ6_1 DDR1_MA14/DDR5_CA2/DDR5_CA3/DDR5_CS0 AE41 M_B_A13
M_A_DQ59 [12] M_A_DQ48 BH41 DDR3_DQ0_1/DDR0_DQ6_1/DDR1_DQ2_1 DDR0_MA14/DDR1_CA2/DDR1_CA3/DDR1_CS0 CF41 M_A_A13 M_B_DQ63 G38 DDR7_DQ0_0/DDR1_DQ6_0/DDR1_DQ6_0 DDR1_MA13/DDR5_CS1/DDR5_CS0/DDR5_CA3 P53 M_B_A12
M_A_CS#1 [12] M_A_DQ60 [12] M_A_DQ63 BD47 DDR3_DQ0_0/DDR0_DQ6_0/DDR1_DQ2_0 DDR0_MA13/DDR1_CS1/DDR1_CS0/DDR1_CA3 BU53 M_A_A12 M_B_DQ62 G36 DDR7_DQ1_7/DDR1_DQ7_7/DDR1_DQ7_7 DDR1_MA12/DDR6_CA1/DDR6_CA1/DDR6_CA5 N51 M_B_A11
[12] M_A_BA0 M_A_DQ61 [12] M_A_DQ62 BB47 DDR3_DQ1_7/DDR0_DQ7_7/DDR1_DQ3_7 DDR0_MA12/DDR2_CA1/DDR2_CA1/DDR2_CA5 BT51 M_A_A11 M_B_DQ61 H36 DDR7_DQ1_6/DDR1_DQ7_6/DDR1_DQ7_6 DDR1_MA11/NC/DDR6_CS1/DDR6_CA4 U42 M_B_A10
M_A_DQ62 [12] M_A_DQ61 BD45 DDR3_DQ1_6/DDR0_DQ7_6/DDR1_DQ3_6 DDR0_MA11/NC/DDR2_CS1/DDR2_CA4 BV42 M_A_A10 M_B_DQ60 H38 DDR7_DQ1_5/DDR1_DQ7_5/DDR1_DQ7_5 DDR1_MA10/DDR7_CA1/DDR7_CA1/DDR7_CA5 P50 M_B_A9
[12] M_A_BA1 M_A_DQ63 [12] M_A_DQ60 BB45 DDR3_DQ1_5/DDR0_DQ7_5/DDR1_DQ3_5 DDR0_MA10/DDR3_CA1/DDR3_CA1/DDR3_CA5 BU50 M_A_A9 M_B_DQ59 N36 DDR7_DQ1_4/DDR1_DQ7_4/DDR1_DQ7_4 DDR1_MA9/DDR6_CA0/DDR6_CA0/DDR6_CA6 U53 M_B_A8
M_A_DQ59 BB42 DDR3_DQ1_4/DDR0_DQ7_4/DDR1_DQ3_4 DDR0_MA9/DDR2_CA0/DDR2_CA0/DDR2_CA6 BY53 M_A_A8 M_B_DQ58 L36 DDR7_DQ1_3/DDR1_DQ7_3/DDR1_DQ7_3 DDR1_MA8/DDR4_CA2/DDR4_CA3/DDR4_CS0 W50 M_B_A7
[12] M_A_BG0 M_A_DQ58 BB41 DDR3_DQ1_3/DDR0_DQ7_3/DDR1_DQ3_3 DDR0_MA8/DDR0_CA2/DDR0_CA3/DDR0_CS0 CA50 M_A_A7 M_B_DQ57 DDR7_DQ1_2/DDR1_DQ7_2/DDR1_DQ7_2
L38 TGL-U-1-GP-U2 DDR1_MA7/DDR4_CA4/DDR4_CA5/DDR4_CA1 U52 M_B_A6
M_A_DQ57 DDR3_DQ1_2/DDR0_DQ7_2/DDR1_DQ3_2
BD42 TGL-U-1-GP-U2 DDR0_MA7/DDR0_CA4/DDR0_CA5/DDR0_CA1 BY52 M_A_A6 M_B_DQ56 N38 DDR7_DQ1_1/DDR1_DQ7_1/DDR1_DQ7_1 DDR1_MA6/DDR4_CA3/DDR4_CA4/DDR4_CS1 U50 M_B_A5
[12] M_A_BG1 M_A_DQ56 BD41 DDR3_DQ1_1/DDR0_DQ7_1/DDR1_DQ3_1 DDR0_MA6/DDR0_CA3/DDR0_CA4/DDR0_CS1 BY50 M_A_A5 DDR7_DQ1_0/DDR1_DQ7_0/DDR1_DQ7_0 DDR1_MA5/DDR4_CA5/DDR4_CA6/DDR4_CA0 AA51 M_B_A4
DDR3_DQ1_0/DDR0_DQ7_0/DDR1_DQ3_0 DDR0_MA5/DDR0_CA5/DDR0_CA6/DDR0_CA0 CD51 M_A_A4 DDR1_MA4/DDR4_CS0/DDR4_CA2/DDR4_CA2 AA53 M_B_A3
DDR0_MA4/DDR0_CS0/DDR0_CA2/DDR0_CA2 CD53 M_A_A3 DDR1_MA3/DDR4_CS1/DDR4_CS0/DDR4_CA3 U47 M_B_A2
DDR0_MA3/DDR0_CS1/DDR0_CS0/DDR0_CA3 BV47 M_A_A2 DDR1_MA2/DDR7_CS0/DDR7_CA2/DDR7_CA2 AC52 M_B_A1
Channel B DDR0_MA2/DDR3_CS0/DDR3_CA2/DDR3_CA2
DDR0_MA1/NC/DDR0_CS1/DDR0_CA4
CE52
BV41
M_A_A1
M_A_A0
U41 M_B_A0
DDR0_MA0/NC/DDR3_CS1/DDR3_CA4 K50 M_B_BG1
M_B_DQ0 [13] BN50 M_A_BG1 DDR1_BG1/DDR6_CA2/DDR6_CA3/DDR6_CS0 J52 M_B_BG0
M_B_DQ1 [13] DDR0_BG1/DDR2_CA2/DDR2_CA3/DDR2_CS0 BL52 M_A_BG0 DDR1_BG0/DDR6_CA3/DDR6_CA4/DDR6_CS1
M_B_DQ2 [13] DDR0_BG0/DDR2_CA3/DDR2_CA4/DDR2_CS1 AA42 M_B_BA1
M_B_DQ3 [13] CB42 M_A_BA1 DDR1_BA1/DDR5_CA5/DDR5_CA6/DDR5_CA0 U44 M_B_BA0
M_B_DQ4 [13] DDR0_BA1/DDR1_CA5/DDR1_CA6/DDR1_CA0 BV44 M_A_BA0 DDR1_BA0/DDR7_CA0/DDR7_CA0/DDR7_CA6
M_B_A0 [13] M_B_DQ5 [13] DDR0_BA0/DDR3_CA0/DDR3_CA0/DDR3_CA6 N53 M_B_ACT_N
M_B_A1 [13] M_B_DQ6 [13] BT53 M_A_ACT_N DDR1_ACT#/DDR6_CS1/DDR6_CS0/DDR6_CA3
M_B_A2 [13] M_B_DQ7 [13] DDR0_ACT#/DDR2_CS1/DDR2_CS0/DDR2_CA3 U45 M_B_PARITY
M_B_A3 [13] M_B_DQ8 [13] BV45 M_A_PARITY DDR1_PAR/DDR7_CS1/DDR7_CS0/DDR7_CA3
M_B_A4 [13] M_B_DQ9 [13] DDR0_PAR/DDR3_CS1/DDR3_CS0/DDR3_CA3 AU53 M_B_ALERT_N
M_B_A5 [13] M_B_DQ15 [13] AU50 M_A_ALERT_N DDR1_ALERT# AU52 V_SM_VREF_CNTB
M_B_A6 [13] M_B_DQ14 [13] DDR0_ALERT# AU49 V_SM_VREF_CNTA DDR1_VREF_CA
M_B_A7 [13] M_B_DQ12 [13] DDR0_VREF_CA
M_B_A8 [13] M_B_DQ13 [13] E52 VTT_CNTL_CPU
M_B_A9 [13] M_B_DQ10 [13] DDR_VTT_CTL DV47 SM_DRAMRST#_CPU
M_B_A10 [13] M_B_DQ11 [13] DRAM_RESET# C49 SM_RCOMP R502 1 2 100R2F-L1-GP-U
M_B_A11 [13] M_B_DQ22 [13] DDR_RCOMP
M_B_A12 [13] M_B_DQ17 [13]
M_B_A13 [13] M_B_DQ21 [13]
M_B_A14 [13] M_B_DQ19 [13]
B M_B_A15 [13] M_B_DQ18 [13] B
M_B_A16 [13] M_B_DQ16 [13]
M_B_DQ20 [13]
M_B_DQ23 [13]
M_B_DQ30 [13]
M_B_DQ27 [13]
M_B_DQS_DN0 M_B_DQ29 [13]
M_B_DQS_DN0 [13]
M_B_DQS_DN1 [13]
M_B_DQS_DN2 [13]
M_B_DQS_DN3 [13] 1D2V_S3
M_B_DQS_DN4 [13]
M_B_DQS_DN5 [13] 3D3V_S0
M_B_DQS_DN6 [13]
1
M_B_DQS_DN7 [13]
M_B_DQ36 [13]
R510
1
M_B_DQ37 [13]
M_B_DQS_DP0 M_B_DQ34 [13] 1D2V_S3 470R2F-GP
M_B_DQS_DP0 [13] R520
M_B_DQS_DP1 M_B_DQ39 [13]
M_B_DQS_DP1 [13] 220KR2F-GP
2
M_B_DQS_DP2 M_B_DQ32 [13] SM_DRAMRST#_CPU 1 2 SM_DRAMRST_N
M_B_DQS_DP2 [13]
M_B_DQS_DP3 M_B_DQ33 [13] R511
M_B_DQS_DP3 [13]
2
M_B_DQS_DP4 M_B_DQ40 [13] Q501 0R0402-PAD-7-NP-GP

M_B_DQS_DP4 [13] C501
M_B_DQS_DP5 M_B_DQ41 [13] G
M_B_DQS_DP5 [13]
SCD1U16V2KX-3DLGP
M_B_DQS_DP6 M_B_DQ42 [13]
M_B_DQS_DP6 [13] VTT_CNTL
M_B_DQS_DP7 M_B_DQ47 [13] D
M_B_DQS_DP7 [13]
M_B_DQ44 [13]
2
M_B_DQ45 [13] VTT_CNTL_CPU S
M_B_DQ43 [13]
DY
PJA138KA-GP
M_B_DQ46 [13] 084.00138.0A31
[13] M_B_CLK#0 [13] M_B_ODT0 M_B_DQ52 [13] 2nd = 84.05067.031
[13] M_B_ODT1 M_B_DQ51 [13]
[13] M_B_CLK0 M_B_DQ55 [13]
M_B_DQ49 [13]
[13] M_B_ACT_N M_B_DQ54 [13]
M_B_DQ48 [13]
[13] M_B_CKE1 [13] M_B_PARITY M_B_DQ50 [13]
M_B_DQ53 [13]
[13] M_B_CKE0 [13] M_B_ALERT_N
M_B_DQ63 [13]
M_B_DQ62 [13]
M_B_DQ57 [13]
M_B_CLK1 [13] M_B_DQ56 [13]
[13] M_B_CS#0 M_B_CLK#1 [13] M_B_DQ58 [13]
A M_B_DQ59 [13] A
M_B_DQ61 [13]
M_B_DQ60 [13]
[13] M_B_BA0 M_B_CS#1 [13]
[13] M_B_BA1
<Core Design>
[13] M_B_BG0
[13] M_B_BG1 Wistron Corporation

Title
Title
[12] V_SM_VREF_CNTA [51] VTT_CNTL
CPU (DDR)
[13] V_SM_VREF_CNTB [12,13] SM_DRAMRST_N
Size
Size Document
DocumentNumber
Number Rev
Rev
A2
Cyborg TGL SC
Date:
Date: Thursday, January 14, 2021 Sheet
Sheet 5 of 105
5 4 3 2 1
5 4 3 2 1
CPU1T 20 OF 21
1D05V_VCCIO_OUT
T15 A51 TP_RSVD_A51 1 TP607

RN603 CFG14 V17 CFG15 RSVD_TP#A51 B51 TP_RSVD_B51 1
D
CFG14 RSVD_TP#B51 TP608 D
1 4 BPM_N0 U15
2 3 BPM_N1 K11 CFG13 C1 TP_RSVD_C1 1 TP609
CFG11 K12 CFG12 RSVD_TP#C1 D2 TP_RSVD_D2 1 TP610 607872 Ver0.9 page350 recommend
SRN10KJ-5-GP CFG10 K9 CFG11 RSVD_TP#D2
CFG9 T17 CFG10 CP39
RN602 K7 CFG9 RSVD_TP#CP39 CU40
1 4 BPM_N2 CFG7 H7 CFG8 RSVD_TP#CU40 AK9
2 3 BPM_N3 K8 CFG7 RSVD#AK9
XDP H9 CFG6 AH9
SRN10KJ-5-GP CFG4 E6 CFG5 RSVD#AH9
CFG3 H5 CFG4 DW6
CFG2 E9 CFG3 RSVD#DW6 DV6
CFG1 D9 CFG2 RSVD#DV6
E7 CFG1 DV4
CFG0 RSVD_TP#DV4 DW3 TP_RSVD_DW 3 1
RSVD_TP#DW3 TP606
CFG_RCOMP B5
CFG_RCOMP DU1
CFG_RCOMP R605 1 2 49D9R2F-GP U17 RSVD_TP#DU1 DT2
H11 CFG17 RSVD_TP#DT2
CFG16 DW2 TP_RSVD_DW 2 1
RSVD_TP#DW2 TP604
BPM_N3 Y1 DV2 TP_RSVD_DV2 1 TP605
BPM_N2 M4 BPM#_3 RSVD_TP#DV2
BPM_N1 AB4 BPM#_2 E1 TP_RSVD_E1 1
BPM#_1 RSVD_TP#E1 TP611
607872 Ver0.9 page350 Required TP601 1 BPM_N0 Y2 F1 TP_RSVD_F1 1 TP612
BPM#_0 RSVD_TP#F1
A3 AB2
B3 RSVD#A3 RSVD#AB2
RSVD#B3 DR1
C R601 1 2 2K2R2F-GP TCP_MBIAS_RCOMP AR2 RSVD_TP#DR1 DR2 C
AL10 RSVD_TP#AR2 RSVD_TP#DR2
AM12 RSVD_TP#AL10 DR53
AH12 RSVD_TP#AM12 RSVD_TP#DR53 DW5
AJ10 RSVD_TP#AH12 RSVD_TP#DW5
AR1 RSVD_TP#AJ10 DV51
RSVD_TP#AR1 VSS DW52 TP_RSVD_DW 52 1
TP#DW52 TP602
BN10 DV53 TP_RSVD_DV53 1 TP603
BM12 RSVD#BN10 TP#DV53 W34
DD13 RSVD#BM12 RSVD#W34 V35
DF13 RSVD#DD13 RSVD#V35
RSVD#DF13 D52
SKTOCC#
20191112 modify TGL-U-1-GP-U2

Follow Nakia
1D05V_VCCIO_OUT 20200304 607872 Ver0.9 page350 Required
Follow Nakia DY R621
R6171 DY 2 1KR2J-1-GP CFG14
R618 1 2 1KR2J-1-GP CFG11
R619 1 2 1KR2J-1-GP CFG10
R620 1 2 1KR2J-1-GP CFG9
R621 1 2 1KR2J-1-GP CFG7

DY
R625 1 2 1KR2J-1-GP CFG3
B B
R626 1 2 1KR2J-1-GP CFG2
R627 1 2 1KR2J-1-GP CFG1
CFG14 R606 1 DY 2 1KR2J-1-GP
CFG4 R607 1 2 1KR2J-1-GP
CFG7 R608 1 DY 2 1KR2J-1-GP
A A
<Core Design>
Wistron Corporation
Title
CPU (CFG/IST)
A3 Cyborg TGL SC
5 4 3 2 1
5 4 3 2 1
[46] VCCCORE_SENSE
[46] VSSCORE_SENSE CPU1M 13 OF 21

1V_CPU_CORE 1V_CPU_CORE
[46] SVID_ALERT#_CPU
20191112 modify
[46] SVID_CLK_CPU 1D05V_VCCST Follow Nakia
A24 G32
D A26 VCCIN VCCIN H24 20200311(DVT1) D
[46] SVID_DATA_CPU VCCIN VCCIN R701 change to 56R follow INTEL PDG
A29 H26
A30 VCCIN VCCIN H30 R703 1 2 100R2F-L1-GP-U SVID_DATA_CPU
A33 VCCIN VCCIN H32
A35 VCCIN VCCIN J1 R701 1 2 56R2F-1-GP SVID_ALERT#_CPU
AY39 VCCIN VCCIN J2
B24 VCCIN VCCIN K1 Close to CPU
Layout note:
B26 VCCIN VCCIN K2 3.Length matchin 25mil, and close SOC in 2inch "
1
1
B29 VCCIN VCCIN K24 C701
B30 VCCIN VCCIN K26
DY C702 DY
SCD1U25V2KX-1-DL-GP
SCD1U25V2KX-1-DL-GP
B33 VCCIN VCCIN K30
2
2
B35 VCCIN VCCIN K32
BA10 VCCIN VCCIN L24 Layout Note:
BA40 VCCIN VCCIN L26
BB39 VCCIN VCCIN L30
VCCIN VCCIN
BB9
VCCIN VCCIN
L32 1. Place close to CPU within 2"
BC10 N24 2. VCC_SENSE/ VSS_SENSE
BC40 VCCIN VCCIN N26
BD39 VCCIN VCCIN N30 impedance=50 ohm
BD9 VCCIN VCCIN N32 3. Length match<25mil
C BE10 VCCIN VCCIN P24 1V_CPU_CORE C
BE40 VCCIN VCCIN P26
BF9 VCCIN VCCIN P28
BG10 VCCIN VCCIN P30 R704 1 2 100R2F-L1-GP-U VCCCORE_SENSE
BG40 VCCIN VCCIN P32 R705 1 2 100R2F-L1-GP-U VSSCORE_SENSE
BH12 VCCIN VCCIN T21
BH39 VCCIN VCCIN T23
BH9 VCCIN VCCIN T25
BJ10 VCCIN VCCIN T27
BJ40 VCCIN VCCIN T31
BK39 VCCIN VCCIN U23
BL10 VCCIN VCCIN U27
BL40 VCCIN VCCIN U29 1D05V_VCCST
BM39 VCCIN VCCIN U31
BN40 VCCIN VCCIN U33
BP12 VCCIN VCCIN V23
BP39 VCCIN VCCIN V25 R707 2 1 56R2J-4-GP SVID_CLK_CPU
BR10 VCCIN VCCIN V27
DY
BR40 VCCIN VCCIN V29
BT12 VCCIN VCCIN V31
BT39 VCCIN VCCIN V33
B B
BU10 VCCIN VCCIN W22
BU40 VCCIN VCCIN W24
BV12 VCCIN VCCIN W28
BY12 VCCIN VCCIN W32
VCCIN VCCIN
CA10
CB12 VCCIN R38 VCCCORE_SENSE
D24 VCCIN VCCIN_SENSE R37 VSSCORE_SENSE
D26 VCCIN VSSIN_SENSE
D29 VCCIN M12 SVID_DATA_CPU
D30 VCCIN VIDSOUT M11 SVID_CLK_CPU
D33 VCCIN VIDSCK P12 SVID_ALERT#_CPU
D35 VCCIN VIDALERT#
E24 VCCIN
E26 VCCIN
E27 VCCIN
E29 VCCIN
VCCIN <Core Design>
E30
E32 VCCIN
A
E33
G2
VCCIN
VCCIN Wistron Corporation
VCCIN 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A
G24
VCCIN Taipei Hsien 221, Taiwan, R.O.C.
G26
G30 VCCIN
VCCIN Title
CPU (VCCIN/VID)
TGL-U-1-GP-U2
A4 Cyborg TGL SC
5 4 3 2 1
5 4 3 2 1
Main Func = CPU

CPU1O 15 OF 21
D 1D2V_S3
1200mA AA39 AF9
output D
VDD2 VCCSTG_OUT 1D05V_VCCSTG_OUT
AB40 AF12
AC39 VDD2 VCCSTG AD12
VDD2 VCCSTG input
AD40
AD51 VDD2 AN10 1D05V_VCCSTG_OUT_R 1 2 R801
AD52 VDD2 VCCSTG_OUT AM9 0R0603-PAD-7-NP-GP
AE39 VDD2 VCCSTG_OUT AG10
VDD2 VCCSTG_OUT 1D05V_VCCSTG_OUT_R
AF40
AG39 VDD2 V15
VDD2 VCCION_OUT 1D05V_VCCIO_OUT output
AH40
AJ39 VDD2 M9
VDD2 VCCSTG_OUT_LGC 1D05V_VCCSTG_TERM output
AK40
AK51 VDD2 BT2
VDD2 VCCST 1D05V_VCCST
AK52 BT1 (1200mA)
AL39 VDD2 VCCST BT4
AM40 VDD2 VCCST
AN39 VDD2 BP2
VDD2 VCCSTG 1D05V_VCCSTG (300mA)
AP40 BP1
AR39 VDD2 VCCSTG BP4
AT52 VDD2 VCCSTG
C AU40 VDD2 C
AW40 VDD2
AW51 VDD2
AW52 VDD2
BD51 VDD2
BD52 VDD2
BK51 VDD2
BK52 VDD2
BV51 VDD2 1D05V_VCCSTG 1D05V_VCCST 1D05V_VCCSTG_OUT_R
BV52 VDD2
CA40 VDD2
CC40 VDD2
CC49 VDD2
CC50 VDD2
VDD2
1
CE40 C802 C801 C804
VDD2 C803
CG40
VDD2
SC1U10V2KX-1DLGP SC1U10V2KX-1DLGP DY SC1U10V2KX-1DLGP
CH39 SC1U10V2KX-1DLGP
VDD2
2
CJ40
CL40 VDD2
CN40 VDD2
CP47 VDD2
B B
CR40 VDD2
D50 VDD2
E51 VDD2
F49 VDD2
VDD2 C803 close to pin AN10, AM9
T51 C804 close to pin AF12, AD12
T52 VDD2
VDD2
TGL-U-1-GP-U2
<Core Design>
Wistron Corporation
A Lack of VCCPLL_OC / VCC1P8A / VCCPLL 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
A
Title
CPU (VDDQ/VCC/VCCST/VCCSTG)
A4
Cyborg TGL SC
5 4 3 2 1
5 4 3 2 1
D D
CPU1S 19 OF 21
DF53 C53
RSVD#DF53 RSVD#C53 T35
DF52 RSVD#T35 E53
20190430_Byron
RSVD#DF52 RSVD#E53 CF39
PCH_IST_TP1 DT52 RSVD#CF39 CPU1D
1 U35 4 OF 21
TP901 PCH_IST_TP0 DU53 PCH_IST_TP1 RSVD#U35
607872 Ver0.9 page350 Optional 1 F53
TP902 PCH_IST_TP0 RSVD#F53 B53
C DF50 RSVD#B53 AP9 C
DF49 RSVD#DF50 RSVD#AP9 A52 DV24
RSVD#DF49 RSVD#A52 DW47 RSVD#DV24
CY30 BF12 DW49 RSVD#DW47
CY15 RSVD_TP#CY30 RSVD_TP#BF12 V21 A48 RSVD#DW49
RSVD_TP#CY15 RSVD_TP#V21 W20 RSVD#A48
D4 RSVD_TP#W20 U37
20190430_Byron
RSVD_TP#D4 RSVD_TP#U37 CD39
1 IST_TP1 A6 RSVD_TP#CD39 U21
TP903 IST_TP0 IST_TP1 RSVD_TP#U21
607872 Ver0.9 page350 recommend 1 A4 CB39
TP904 IST_TP0 RSVD#CB39 BB12
RSVD_TP#BB12 W37
RSVD_TP#W37 AY12
RSVD_TP#AY12 W38
RSVD_TP#W38 U38
RSVD_TP#U38 CY28
RSVD_TP#CY28
B B
<Core Design>
A
Wistron Corporation A
Title
CPU (RSVD)
A4 Cyborg TGL SC
5 4 3 2 1
5 4 3 2 1
Main Func = CPU
1V_CPU_CORE 22uF *13pcs 1V_CPU_CORE

10uF *6pcs
1
PC1001 PC1002 PC1003 PC1004
1
SC22U6D3V3MX-1-DL-GP SC22U6D3V3MX-1-DL-GP SC22U6D3V3MX-1-DL-GP SC22U6D3V3MX-1-DL-GP PC1031 PC1032 PC1033
2
2
SC10U6D3V3MX-DL-GP SC10U6D3V3MX-DL-GP SC10U6D3V3MX-DL-GP
2
D
DY DY DY D
1
1
PC1005 PC1006 PC1007 PC1008 PC1034 PC1035 PC1036
SC22U6D3V3MX-1-DL-GP SC22U6D3V3MX-1-DL-GP SC22U6D3V3MX-1-DL-GP SC22U6D3V3MX-1-DL-GP
SC10U6D3V3MX-DL-GP SC10U6D3V3MX-DL-GP SC10U6D3V3MX-DL-GP
2
2
DY DY DY
1
1
PC1009 PC1010 PC1011 PC1012 PC1022
SC22U6D3V3MX-1-DL-GP SC22U6D3V3MX-1-DL-GP SC22U6D3V3MX-1-DL-GP SC22U6D3V3MX-1-DL-GP SC22U6D3V3MX-1-DL-GP
2
2
1D8V_CPU_AUX 22uF *12pcs
10uF *4pcs
1
1
PC1013 PC1014 PC1015 PC1023
SC22U6D3V3MX-1-DL-GP SC22U6D3V3MX-1-DL-GP SC22U6D3V3MX-1-DL-GP SC22U6D3V3MX-1-DL-GP 1D8V_CPU_AUX
2
1
PC1026 PC1027
C SC10U6D3V3MX-DL-GP SC10U6D3V3MX-DL-GP C
2
DY DY
1
PC1016 PC1017 PC1018 PC1024

2
1
PC1028 PC1029
SC10U6D3V3MX-DL-GP SC10U6D3V3MX-DL-GP
2
DY DY
1
PC1019 PC1020 PC1021 PC1025

2
B B
A A
<Core Design>
Wistron Corporation
Title
Title
CPU (CORE Power Cap1)
Size
Size Document
DocumentNumber
Number Rev
Rev
A2
Cyborg TGL SC
Date:
Sheet 10 of 105
5 4 3 2 1
5 4 3 2 1
Main Func = CPU

1uF *6pcs
10uF *6pcs
1D05V_VCCST
1D2V_S3
47UF *1pcs
22uF *1pcs
1
1
D C1121 C1122 C1102 C1103 C1104 C1105 C1106 C1107 D
SC1U10V2KX-1DLGP DY SC1U10V2KX-1DLGP PLACE on Primary SIDE SC1U10V2KX-1DLGP SC1U10V2KX-1DLGP SC1U10V2KX-1DLGP SC1U10V2KX-1DLGP SC1U10V2KX-1DLGP SC1U10V2KX-1DLGP
2
2
1
1
1
1
C1109 C1110 C1128 C1129 C1130 C1131
1D05V_VCCSTG SC10U6D3V3MX-DL-GP SC10U6D3V3MX-DL-GP SC10U6D3V3MX-DL-GP SC10U6D3V3MX-DL-GP SC10U6D3V3MX-DL-GP SC10U6D3V3MX-DL-GP
2
2
2
(ADDED) (ADDED) (ADDED) (ADDED)
PLACE on Back SIDE
1
C1126 C1127
SC1U10V2KX-1DLGP DY SC1U10V2KX-1DLGP
1
2
C1111 C1112 C1113

SC10U6D3V2MX-6-GP SC10U6D3V2MX-6-GP SC10U6D3V2MX-6-GP
2
DY DY DY
1D8V_S5
1
C1118 C1116 C1117
C1132 C1133 C1134 PLACE Close to VR SC22U6D3V3MX-1-DL-GP SC22U6D3V3MX-1-DL-GP SC22U6D3V3MX-1-DL-GP
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
2
C
DY C
(ADDED) (NEW DY)
1
DY DY
2
11/5 Tery Don

add 1D8V_S5 decoupling cap. follow Shuri
B B
A <Core Design> A
Wistron Corporation
Title
CPU (Power Cap2)
A3
Cyborg TGL SC
5 4 3 2 1
5 4 3 2 1
Main Func = MEMORY DM1A 1 OF 4

M_A_A0 144 8 M_A_DQ63 10/15 Modify DIM1 DQ/DQS tuning. follow CRB
M_A_A1 133 A0 DQ0 7 M_A_DQ58
M_A_A2 132 A1 DQ1 20 M_A_DQ56 DM1D 4 OF 4
M_A_A3 131 A2 DQ2 21 M_A_DQ59
M_A_A4 128 A3 DQ3 4 M_A_DQ60
M_A_DQ[56:63] DM1B 2 OF 4
1 99
M_A_A5 126 A4 DQ4 3 M_A_DQ62 11 M_A_DQS_DN7 2 VSS VSS 102
M_A_DQS_DN0 M_A_A6 127 A5 DQ5 16 M_A_DQ61 DQS0_C 13 M_A_DQS_DP7 5 VSS VSS 103
M_A_DQS_DN1 M_A_DQS_DN0 [5] M_A_A7 122 A6 DQ6 17 M_A_DQ57 DQS0_T 32 M_A_DQS_DN6 6 VSS VSS 106
M_A_DQS_DN2 M_A_DQS_DN1 [5] M_A_A8 125 A7 DQ7 28 M_A_DQ51 DQS1_C 34 M_A_DQS_DP6 9 VSS VSS 107
M_A_DQS_DN4 M_A_DQS_DN3 [5] M_A_A10 146 A9 DQ9 41 M_A_DQ49 DQS2_C 55 M_A_DQS_DP5 14 VSS VSS 168
M_A_DQS_DN5 M_A_DQS_DN4 [5] M_A_A11 120 A10/AP DQ10 42 M_A_DQ54 DQS2_T 74 M_A_DQS_DN4 15 VSS VSS 171
M_A_DQS_DN6 M_A_DQS_DN5 [5] M_A_A12 119 A11 DQ11 24 M_A_DQ48
M_A_DQ[48:55] DQS3_C 76 M_A_DQS_DP4 18 VSS VSS 172
M_A_DQS_DN7 [5] M_A_A14 151 A13 DQ13 38 M_A_DQ55 DQS4_C 179 M_A_DQS_DP1 22 VSS VSS 176
M_A_DQS_DP0 M_A_A15 156 WE#/A14 DQ14 37 M_A_DQ50 DQS4_T 198 M_A_DQS_DN0 23 VSS VSS 180
D M_A_DQS_DP0 [5] D
M_A_DQS_DP1 M_A_A16 152 CAS#/A15 DQ15 50 M_A_DQ45 DQS5_C 200 M_A_DQS_DP0 26 VSS VSS 181
M_A_DQS_DP2 M_A_DQS_DP1 [5] RAS#/A16 DQ16 49 M_A_DQ47 DQS5_T 219 M_A_DQS_DN3 27 VSS VSS 184
M_A_DQS_DP3 M_A_DQS_DP2 [5] M_A_BA0 150 DQ17 62 M_A_DQ41 DQS6_C 221 M_A_DQS_DP3 30 VSS VSS 185
M_A_DQS_DP4 M_A_DQS_DP3 [5] M_A_BA1 145 BA0 DQ18 63 M_A_DQ40 DQS6_T 240 M_A_DQS_DN2 31 VSS VSS 188
M_A_DQS_DP5 M_A_DQS_DP4 [5] M_A_BG0 115 BA1 DQ19 46 M_A_DQ44
M_A_DQ[40:47] DQS7_C 242 M_A_DQS_DP2 35 VSS VSS 189
M_A_DQS_DP6 M_A_DQS_DP5 [5] M_A_BG1 113 BG0 DQ20 45 M_A_DQ46 DQS7_T 95 1D2V_S3 36 VSS VSS 192
M_A_DQS_DP7 M_A_DQS_DP6 [5] BG1 DQ21 58 M_A_DQ42 DQS8_C 97 39 VSS VSS 193
M_A_DQS_DP7 [5] 92 DQ22 59 M_A_DQ43 DQS8_T 40 VSS VSS 196
91 CB0/NC DQ23 70 M_A_DQ36 12 43 VSS VSS 197
M_A_A0 [5] 101 CB1/NC DQ24 71 M_A_DQ38 DM0#/DBI0# 33 44 VSS VSS 201
M_A_A1 [5] 105 CB2/NC DQ25 83 M_A_DQ33 DM1#/DBI# 54 47 VSS VSS 202
M_A_A3 [5] 87 CB4/NC DQ27 66 M_A_DQ39
M_A_DQ[32:39] DM3#/DBI3# 178 51 VSS VSS 206
M_A_A6 [5] CB7/NC DQ30 80 M_A_DQ32 DM6#/DBI6# 241 57 VSS VSS 213
M_A_A7 [5] M_A_CLK0 137 DQ31 174 M_A_DQ11 DM7#/DBI7# 96 60 VSS VSS 214
M_A_A8 [5] M_A_CLK#0 139 CK0_T DQ32 173 M_A_DQ10 DM8#/DBI#/NC 61 VSS VSS 217
M_A_A9 [5] M_A_CLK1 138 CK0_C DQ33 187 M_A_DQ14 64 VSS VSS 218
M_A_A10 [5] M_A_CLK#1 140 CK1_T/NF DQ34 186 M_A_DQ8 65 VSS VSS 222
M_A_A11 [5] CK1_C/NF DQ35 170 M_A_DQ12
M_A_DQ[8:15] DDR4-260P-78-GP-U
68 VSS VSS 223
M_A_A12 [5] M_A_CKE0 109 DQ36 169 M_A_DQ9 062.10011.M001 3D3V_S0 69 VSS VSS 226
M_A_A13 [5] M_A_CKE1 110 CKE0 DQ37 183 M_A_DQ15 1D2V_S3 72 VSS VSS 227
DM1C 3 OF 4
M_A_A14 [5] CKE1 DQ38 182 M_A_DQ13 73 VSS VSS 230
M_A_A15 [5] M_A_CS#0 149 DQ39 195 M_A_DQ5 111 255 77 VSS VSS 231
M_A_A16 [5] M_A_CS#1 157 CS0# DQ40 194 M_A_DQ7 112 VDD VDDSPD 78 VSS VSS 234
162 CS1# DQ41 207 M_A_DQ0 117 VDD 2D5V_S3 C1228 C1201 81 VSS VSS 235
C0/CS2#/NC DQ42 VDD VSS VSS
1
SCD1U16V2KX-3DLGP
165 208 M_A_DQ2 118 257 82 238
SC2D2U10V3KX-1DLGP-U
M_A_DQ0 [5] C1/CS3#/NC DQ43 191 M_A_DQ6
M_A_DQ[0:7] 123 VDD VPP 259 85 VSS VSS 239
M_A_DQ1 [5] M_A_ODT0 155 DQ44 190 M_A_DQ4 124 VDD VPP 86 VSS VSS 243
M_A_DQ2 [5] ODT0 DQ45 VDD VSS VSS
2
M_A_ODT1 161 203 M_A_DQ3 129 258 89 244
M_A_DQ3 [5] ODT1 DQ46 204 M_A_DQ1 130 VDD VTT 0D6V_VREF_S0 DY DY 90 VSS VSS 247
M_A_DQ4 [5] SA0_CHA_DIM0 256 DQ47 216 M_A_DQ31 135 VDD 93 VSS VSS 248
M_A_DQ5 [5] SA1_CHA_DIM0 260 SA0 DQ48 215 M_A_DQ24 136 VDD 94 VSS VSS 251
M_A_DQ6 [5] SA2_CHA_DIM0 166 SA1 DQ49 228 M_A_DQ26 141 VDD 98 VSS VSS 252
M_A_DQ7 [5] SA2 DQ50 229 M_A_DQ30 142 VDD VSS VSS
M_A_DQ8 [5] CPU_SMB_SDA_DDR 254 DQ51 211 M_A_DQ27
M_A_DQ[24:31] 147 VDD 261
M_A_DQ9 [5] CPU_SMB_SCL_DDR 253 SDA DQ52 212 M_A_DQ29 148 VDD 261 262
M_A_DQ10 [5] DDR4-260P-78-GP-U
SCL DQ53 224 M_A_DQ25 153 VDD 262
M_A_DQ11 [5] DQ54 225 M_A_DQ28 154 VDD 062.10011.M001
M_A_DQ12 [5] SM_DRAMRST_N 108 DQ55 237 M_A_DQ17 159 VDD NP1
C C
M_A_DQ13 [5] 1D2V_S3 M_A_ACT_N 114 RESET# DQ56 236 M_A_DQ23 160 VDD NP1 NP2
M_A_DQ14 [5] M_A_ALERT_N 116 ACT# DQ57 249 M_A_DQ20 163 VDD NP2
M_A_DQ15 [5] 1 2 TS#_DIMM0_1 134 ALERT# DQ58 250 M_A_DQ18 VDD
M_A_DQ16 [5] DY EVENT#/NF DQ59 232 M_A_DQ21
M_A_DQ[16:23]
R1215 240R2F-1-GP
M_A_DQ17 [5] M_A_PARITY 143 DQ60 233 M_A_DQ19 DDR4-260P-78-GP-U
M_A_DQ18 [5] PARITY DQ61 245 M_A_DQ22
M_A_DQ19 [5] M_VREF_CA_DIMMA 164 DQ62 246 M_A_DQ16 062.10011.M001
M_A_DQ20 [5] VREFCA DQ63
M_A_DQ21 [5] 0D6V_VREF_S0 0D6V_VREF_S0 0D6V_VREF_S0
M_A_DQ22 [5]
M_A_DQ23 [5] DDR4-260P-78-GP-U
1
C1229
M_A_DQ24 [5]
062.10011.M001
SCD1U16V2KX-3DLGP
M_A_DQ25 [5] 1D2V_S3

M_A_DQ26 [5] 2nd = 062.10011.M021
2
1
M_A_DQ27 [5] 3rd = 062.10011.M003 C1225 C1226 C1223 C1227
1
SC4D7U6D3V2MX-1-GP
SC4D7U6D3V2MX-1-GP
M_A_DQ28 [5] 4th = 062.10011.M013 DY
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
M_A_DQ29 [5]
2
M_A_DQ30 [5]
2
M_A_DQ31 [5]
M_A_DQ32 [5]
1
C1208 C1202 C1209 C1203 C1204 C1205 C1206 C1210
M_A_DQ33 [5]
M_A_DQ34 [5] 3D3V_S0
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
M_A_DQ35 [5] DY DY DY DY
2
M_A_DQ36 [5]
M_A_DQ37 [5] SA0_CHA_DIM0
R1204 1 DY 2 10KR2J-3-GP
M_A_DQ38 [5]
M_A_DQ39 [5] 2 1
M_A_DQ40 [5]
R1205
M_A_DQ41 [5]
0R0402-PAD-7-NP-GP
M_A_DQ42 [5]
M_A_DQ43 [5]
M_A_DQ44 [5] 2D5V_S3
M_A_DQ45 [5] 3D3V_S0
M_A_DQ46 [5] SM_DRAMRST_N
M_A_DQ47 [5]
1
C1214 C1215 C1216 C1217 C1218 C1219 C1220 C1221
M_A_DQ48 [5]
1
R1208 1 2 10KR2J-3-GP SA1_CHA_DIM0
M_A_DQ49 [5] DY DY DY DY EC1202 DY EC1203 C1231 C1212 C1207
2
1
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC4D7U6D3V2MX-1-GP
SC4D7U6D3V2MX-1-GP
M_A_DQ50 [5]
2
2 1
SC2D2U6D3V2MX-DL-GP
DY
SCD1U25V2KX-1-DL-GP
ED1217
M_A_DQ51 [5]
2
AZ5725-01FDR7G-GP R1210
M_A_DQ52 [5] DY
2
0R0402-PAD-7-NP-GP
B M_A_DQ53 [5] 83.05725.0A0 DY B
M_A_DQ54 [5]
M_A_DQ55 [5]
1
M_A_DQ56 [5] 3D3V_S0

M_A_DQ57 [5]
M_A_DQ58 [5]
M_A_DQ59 [5] SA2_CHA_DIM0
R1211 1 DY 2 10KR2J-3-GP
M_A_DQ60 [5]
M_A_DQ61
M_A_DQ62
[5]
[5]
2 1 10uF *8pcs (DY *3)
M_A_DQ63 [5]
R1212
0R0402-PAD-7-NP-GP 1uF *8pcs (DY *3)
M_A_CLK0 [5]
M_A_CLK#0 [5]
2.2uF *1pcs (DY *1)
M_A_CLK1 [5]
M_A_CLK#1 [5]
0.1uF *1pcs (DY *1)
1D2V_S3
M_A_CKE0 [5]
M_A_CKE1 [5]
M_A_CS#0 [5] RN1201 R1206

1 4
M_A_CS#1 [5] M_VREF_CA_DIMMA1 V_SM_VREF_CNTA
2 3 2
M_A_ODT0 [5] SRN1KJ-7-GP 2R2F-GP
1
M_A_ODT1 [5] C1222

SCD022U16V2KX-3DLGP
2
CPU_SMB_SDA_DDR [13,18] V_SM_VREF_PATH1

CPU_SMB_SCL_DDR [13,18]
1
R1209
SM_DRAMRST_N [5,13] 24D9R2F-L-GP
M_A_ACT_N [5]
M_A_ALERT_N [5]
M_A_PARITY [5]
2
M_A_BA0 [5]
M_A_BA1 [5]
M_A_BG0 [5]
M_A_BG1 [5]
A V_SM_VREF_CNTA [5] A
<Core Design>
Wistron Corporation
Title
Title
DDR3-SODIMM1
Size
Size Document
DocumentNumber
Number Rev
Rev
A2
Cyborg TGL SC
Date: Sheet
Sheet 12 of 105
5 4 3 2 1
5 4 3 2 1
Main Func = MEMORY DM2A 1 OF 4 10/15 Modify DIM2 DQ/DQS tuning. follow CRB 3D3V_S0
M_B_A0 144 8 M_B_DQ42 1D2V_S3

M_B_A1 133 A0 DQ0 7 M_B_DQ47 DM2C 3 OF 4 DM2D 4 OF 4
M_B_A2 132 A1 DQ1 20 M_B_DQ45
M_B_A3 131 A2 DQ2 21 M_B_DQ43 111 255 1 99
M_B_A4 128 A3 DQ3 4 M_B_DQ41
M_B_DQ[40:47] 112 VDD VDDSPD 2 VSS VSS 102
M_B_A0 [5] A4 DQ4 VDD VSS VSS
M_B_A5 126 3 M_B_DQ40 117 2D5V_S3 C1329 C1328 5 103
SCD1U16V2KX-3DLGP
M_B_A6 127 16 M_B_DQ46 118 257 6 106
M_B_A2 [5] A6 DQ6 VDD VPP VSS VSS
M_B_A7 122 17 M_B_DQ44 123 259 9 107
M_B_A3 [5] A7 DQ7 VDD VPP VSS VSS
M_B_A8 125 28 M_B_DQ34 124 0D6V_VREF_S0 10 167
2
M_B_A9 121 29 M_B_DQ36 129 258 14 168
M_B_A5 [5]
M_B_A10 146 A9 DQ9 41 M_B_DQ32 130 VDD VTT DY DY 15 VSS VSS 171
M_B_A6 [5] A10/AP DQ10 VDD VSS VSS
M_B_A11 120 42 M_B_DQ37 135 18 172
M_B_A7 [5]
M_B_A12 119 A11 DQ11 24 M_B_DQ35
M_B_DQ[32:39] 136 VDD 19 VSS VSS 175
M_B_A13 158 25 M_B_DQ33 141 22 176
M_B_A14 151 38 M_B_DQ38 142 23 180
M_B_A10 [5] WE#/A14 DQ14 VDD VSS VSS
M_B_A15 156 37 M_B_DQ39 147 261 26 181
D M_B_A11 [5] CAS#/A15 DQ15 VDD 261 VSS VSS D
M_B_A16 152 50 M_B_DQ58 148 262 27 184
M_B_A12 [5] RAS#/A16 DQ16 VDD 262 VSS VSS
49 M_B_DQ62 153 30 185
M_B_A13 [5] DQ17 VDD VSS VSS
M_B_BA0 150 62 M_B_DQ60 154 31 188
M_B_A14 [5] BA0 DQ18 VDD VSS VSS
M_B_BA1 145 63 M_B_DQ57 159 NP1 35 189
M_B_A15 [5]
M_B_BG0 115 BA1 DQ19 46 M_B_DQ59
M_B_DQ[56:63] 160 VDD NP1 NP2 36 VSS VSS 192
M_B_A16 [5] BG0 DQ20 VDD NP2 VSS VSS
M_B_BG1 113 45 M_B_DQ61 163 39 193
BG1 DQ21 58 M_B_DQ63 VDD 40 VSS VSS 196
M_B_BA0 [5] DQ22 M_B_DQ56 VSS VSS
92 59 43 197
M_B_BA1 [5] CB0/NC DQ23 M_B_DQ54 VSS VSS
91 70 DDR4-260P-82-GP-U 44 201
M_B_BG0 [5] CB1/NC DQ24 M_B_DQ49 VSS VSS
101 71 47 202
M_B_BG1 [5]
105 CB2/NC DQ25 83 M_B_DQ52 062.10011.M004 48 VSS VSS 205
88 CB3/NC DQ26 84 M_B_DQ50 51 VSS VSS 206
M_B_CLK0 [5]
87 CB4/NC DQ27 66 M_B_DQ55
M_B_DQ[48:55] 52 VSS VSS 209
M_B_CLK#0 [5] CB5/NC DQ28 M_B_DQ51 VSS VSS
100 67 56 210
M_B_CLK1 [5] CB6/NC DQ29 M_B_DQ53 VSS VSS
104 79 57 213
M_B_CLK#1 [5] CB7/NC DQ30 M_B_DQ48 VSS VSS
80 DM2B 2 OF 4 60 214
M_B_CLK0 137 DQ31 174 M_B_DQ8 61 VSS VSS 217
M_B_CKE0 [5] M_B_CLK#0 CK0_T DQ32 M_B_DQ14 M_B_DQS_DN5 VSS VSS
139 173 11 64 218
M_B_CKE1 [5] M_B_CLK1 CK0_C DQ33 M_B_DQ10 DQS0_C M_B_DQS_DP5 VSS VSS
138 187 13 65 222
M_B_CLK#1 140 CK1_T/NF DQ34 186 M_B_DQ12 DQS0_T 32 M_B_DQS_DN4 68 VSS VSS 223
M_B_CS#0 [5] CK1_C/NF DQ35 170 M_B_DQ15
M_B_DQ[8:15] DQS1_C 34 M_B_DQS_DP4 69 VSS VSS 226
M_B_CS#1 [5] M_B_CKE0 109 DQ36 169 M_B_DQ13 DQS1_T 53 M_B_DQS_DN7 72 VSS VSS 227
M_B_CKE1 110 CKE0 DQ37 183 M_B_DQ9 DQS2_C 55 M_B_DQS_DP7 73 VSS VSS 230
M_B_ODT0 [5] CKE1 DQ38 M_B_DQ11 DQS2_T M_B_DQS_DN6 VSS VSS
182 74 77 231
M_B_ODT1 [5] M_B_CS#0 DQ39 M_B_DQ7 DQS3_C M_B_DQS_DP6 VSS VSS
149 195 76 78 234
M_B_CS#1 157 CS0# DQ40 194 M_B_DQ6 DQS3_T 177 M_B_DQS_DN1 81 VSS VSS 235
CPU_SMB_SDA_DDR [12,18] 162 CS1# DQ41 207 M_B_DQ2 DQS4_C 179 M_B_DQS_DP1 82 VSS VSS 238
CPU_SMB_SCL_DDR [12,18] 165 C0/CS2#/NC DQ42 208 M_B_DQ3 DQS4_T 198 M_B_DQS_DN0 85 VSS VSS 239
C1/CS3#/NC DQ43 191 M_B_DQ0
M_B_DQ[0:7] DQS5_C 200 M_B_DQS_DP0 86 VSS VSS 243
SM_DRAMRST_N [5,12] M_B_ODT0 155 DQ44 190 M_B_DQ5 DQS5_T 219 M_B_DQS_DN3 89 VSS VSS 244
M_B_ACT_N [5] M_B_ODT1 161 ODT0 DQ45 203 M_B_DQ1 DQS6_C 221 M_B_DQS_DP3 90 VSS VSS 247
M_B_ALERT_N [5] ODT1 DQ46 204 M_B_DQ4 DQS6_T 240 M_B_DQS_DN2 93 VSS VSS 248
SA0_CHB_DIM0 256 DQ47 216 M_B_DQ30 DQS7_C 242 M_B_DQS_DP2 94 VSS VSS 251
M_B_PARITY [5] SA1_CHB_DIM0 260 SA0 DQ48 215 M_B_DQ26 DQS7_T 95 98 VSS VSS 252
SA2_CHB_DIM0 166 SA1 DQ49 228 M_B_DQ29 DQS8_C 97 1D2V_S3 VSS VSS
V_SM_VREF_CNTB [5] SA2 DQ50 229 M_B_DQ25 DQS8_T
CPU_SMB_SDA_DDR 254 DQ51 211 M_B_DQ27
M_B_DQ[24:31] 12 DDR4-260P-82-GP-U
CPU_SMB_SCL_DDR 253 SDA DQ52 212 M_B_DQ31 DM0#/DBI0# 33
SCL DQ53 224 M_B_DQ28 DM1#/DBI# 54 062.10011.M004
DQ54 225 M_B_DQ24 DM2#/DBI2# 75
C SM_DRAMRST_N 108 DQ55 237 M_B_DQ21 DM3#/DBI3# 178 C
M_B_DQ0 [5] RESET# DQ56 DM4#/DBI4#
1D2V_S3 M_B_ACT_N 114 236 M_B_DQ17 199
M_B_DQ1 [5] ACT# DQ57 DM5#/DBI5#
M_B_ALERT_N 116 249 M_B_DQ16 220
M_B_DQ2 [5] ALERT# DQ58 DM6#/DBI6#
1 R1312 2 TS#_DIMM1_1 134 250 M_B_DQ20 241
M_B_DQ3 [5] EVENT#/NF DQ59 232 M_B_DQ19
M_B_DQ[16:23] DM7#/DBI7# 96
M_B_DQ4 [5] DY 240R2F-1-GP M_B_PARITY DQ60 M_B_DQ23 DM8#/DBI#/NC 0D6V_VREF_S0 0D6V_VREF_S0
M_B_DQ5 [5] 143 233
PARITY DQ61 245 M_B_DQ18 0D6V_VREF_S0 2D5V_S3
M_B_DQ6 [5] DQ62
M_VREF_CA_DIMMB 164 246 M_B_DQ22 DDR4-260P-82-GP-U
M_B_DQ7 [5] VREFCA DQ63
M_B_DQ8 [5] 062.10011.M004
M_B_DQ9 [5]
M_B_DQ15 [5] DDR4-260P-82-GP-U C1311 C1313
1
1D2V_S3
SC4D7U6D3V2MX-1-GP
SC1U10V2KX-1DLGP
M_B_DQ14 [5] C1301 C1324 C1325
1
SC4D7U6D3V2MX-1-GP
SC4D7U6D3V2MX-1-GP
062.10011.M004 C1326 C1327
SCD1U16V2KX-3DLGP
M_B_DQ12 [5]
1
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
M_B_DQ13 [5] 2nd = 062.10011.M020
2
M_B_DQ10 [5] 3rd = 062.10011.M007
2
3D3V_S0
M_B_DQ11 [5] 4th = 062.10011.M027 DY
2
M_B_DQ22 [5] SM_DRAMRST_N
M_B_DQ17 [5] C1303 C1304 C1305 C1306 C1307 C1308 C1309 C1310
1
R1302 1 2 10KR2J-3-GP SA0_CHB_DIM0
M_B_DQ21 [5] DY
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
DY DY DY
2
M_B_DQ19 [5]
M_B_DQ18 [5] 2 1
ED1302
2
M_B_DQ16 [5] R1303
DY AZ5725-01FDR7G-GP 0R0402-PAD-7-NP-GP
M_B_DQ20 [5]
M_B_DQ23 [5] 83.05725.0A0
M_B_DQ30 [5]
3D3V_S0
1
M_B_DQ27 [5]
M_B_DQ29 [5]
M_B_DQ31 [5]
R1306 1 2 10KR2J-3-GP SA1_CHB_DIM0
M_B_DQ25 [5]
M_B_DQ28 [5]
teknisi indonesia
M_B_DQ24 [5] 2 DY 1 R1307
M_B_DQ26 [5]
M_B_DQ35 [5] 0R2J-2-GP
M_B_DQ38 [5] EC1303
SC2D2U6D3V2MX-DL-GP
M_B_DQ36 [5] C1315 C1316 C1317 C1318 C1319 C1320 C1321 C1322
3D3V_S0
M_B_DQ37 [5] DY DY DY
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
M_B_DQ34 [5]
2
1D2V_S3
M_B_DQ39 [5]
SA2_CHB_DIM0 DY
M_B_DQ32 [5] R1310 1 DY 2 10KR2J-3-GP
M_B_DQ33 [5]
M_B_DQ40 [5] RN1301 2 1
B 1 4 R1305 B
M_B_DQ41 [5] R1311
2 3 M_VREF_CA_DIMMB1 2 V_SM_VREF_CNTB 0R0402-PAD-7-NP-GP
M_B_DQ42 [5]
M_B_DQ47 [5]
M_B_DQ44 [5] SRN1KJ-7-GP 2R2F-GP
1
M_B_DQ45 [5] C1323

M_B_DQ43
M_B_DQ46
[5]
[5]
SCD022U16V2KX-3DLGP
10uF *8pcs (DY *3)
2
M_B_DQ52
M_B_DQ51
[5]
[5]
V_SM_VREF_PATH2 1uF *8pcs (DY *3)
1
M_B_DQ55
M_B_DQ49
[5]
[5]
R1309
24D9R2F-L-GP
2.2uF *1pcs (DY *1)
M_B_DQ54 [5]
M_B_DQ48 [5]
M_B_DQ50 [5]
2
M_B_DQ53 [5]
M_B_DQ63 [5]
M_B_DQ62 [5]
M_B_DQ57 [5]
M_B_DQ56 [5]
M_B_DQ58 [5]
M_B_DQ59 [5]
M_B_DQ61 [5]
M_B_DQ60 [5]
M_B_DQS_DN0
M_B_DQS_DN0 [5]
M_B_DQS_DN1
M_B_DQS_DN1 [5]
M_B_DQS_DN2
M_B_DQS_DN2 [5]
M_B_DQS_DN3
M_B_DQS_DN3 [5]
M_B_DQS_DN4
M_B_DQS_DN4 [5]
M_B_DQS_DN5
M_B_DQS_DN5 [5]
M_B_DQS_DN6
M_B_DQS_DN6 [5]
M_B_DQS_DN7
M_B_DQS_DN7 [5]
M_B_DQS_DP0
M_B_DQS_DP0 [5]
M_B_DQS_DP1
M_B_DQS_DP1 [5]
M_B_DQS_DP2
M_B_DQS_DP2 [5]
M_B_DQS_DP3
M_B_DQS_DP3 [5]
M_B_DQS_DP4
M_B_DQS_DP4 [5]
M_B_DQS_DP5
M_B_DQS_DP5 [5]
A M_B_DQS_DP6 A
M_B_DQS_DP6 [5]
M_B_DQS_DP7
M_B_DQS_DP7 [5]
<Core Design>
Wistron Corporation
Title
Title
DDR3-SODIMM1
Size
Size Document
DocumentNumber
Number Rev
Rev
A2
Cyborg TGL SC
Date:Thursday, January 14, 2021
Date: Sheet
Sheet 13 of 105
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
<Core Design>
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A
Title
DDR (RSVD) (DDR4-CHA1)
A4 Cyborg TGL SC
5 4 3 2 1
5 4 3 2 1
[18,24,25,91] SPI_SI_ROM
[18,24,25] SPI_WP_ROM
[18,24,25] SPI_HOLD_ROM GPIO GPP_C5 SPI_SI GPP_E6 GPP_B23 SPI_WP ME_UNLOCK (GPP_R2) CNVI debug MODES (GPP_F2)
3D3V_S5 3D3V_S5 3D3V_S5
[21] CNV_RGI_DT =20K PD= =NO INTERNAL= =NO INTERNAL= =20K PD= 3D3V_SPI
=NO INTERNAL= =20K PD= 1D8V_S5
=NO INTERNAL=
[18] CPU_SML0_ALERT# * PH as VCCPGPPR
1
R1501
1
R1503 R1504 1D8V_GPPR_S5
[18] GPP_E6 4K7R2J-2-GP 100KR1J-GP
DY R1507
100KR1J-GP
R1506
[19] HDA_SDOUT_CPU
1
4K7R2J-2-GP 100KR2J-1-GP R1509 20191112 modify
2
Follow Nakia using 1.8V GPPR
[4,71] USB1_TCSS_RXD BOOT_HALT
2
CPU_SML0_ALERT# SPI_SI_ROM GPP_E6 SPI_WP_ROM CNV_RGI_DT
Schematic DY
[4] GPP_D10 Close to U2501
1
D Close to U2501 R1514 4K7R2J-2-GP D
2
1
1
R1502 R1511 ME_UNLOCK1 2HDA_SDOUT_CPU R1516
[3] DBG_PMODE 4K7R1J-GP
20200221(DVT1) R1512 DY R1515 DY
DY DY Change to 4.7k follow CRB DY 4K7R1J-GP 0R0402-PAD-7-NP-GP
[4] GPP_D12
4K7R2J-2-GP
2
20K5R2F-GP 4K7R2J-2-GP
[4] GPP_E21
2
[18] GPP_E10
[18] GPP_E11
ESPI Disable Disable Enable 19.2MHZ CLOCK FROM DIVIDER

High (DERIVED FROM 38.4MHZ CRYSTAL)
Disable OVERRIDEN INTEGRATED CNVI DISABLE
Enable =default= 38.4MHZ CLOCK FROM DIRECT SECURITY MEASURES

Low Enable Disable
CRYSTAL (DEFAULT)
Enable NOT OVERRIDEN
INTEGRATED CNVI ENABLE
GPIO TBT LSX VCCIO conf.#0 TBT LSX VCCIO conf.#1 TBT LSX VCCIO conf.#2 TBT LSX VCCIO conf.#3 A0 GPP_E10 GPP_E11
E19 3D3V_S5
=NO INTERNAL= E21 3D3V_S5
=NO INTERNAL= D10 3D3V_S5
=NO INTERNAL= D12 3D3V_S5
=NO INTERNAL= 3D3V_S5
=NO INTERNAL= 1D05V_S5_OUT
=20K PU=
20191211
1
R1528
1
1
R1518 R1520 R1524 Always stuff 1D8V_S5 1D8V_S5
R1519 R1526 Follow Nakia
DY DY 4K7R1J-GP DY DY 100KR2J-1-GP
1
R1531
4K7R2J-2-GP 4K7R2J-2-GP 4K7R2J-2-GP 1KR2F-3-GP R1530
2
2
2
USB1_TCSS_RXD GPP_E21 GPP_D10 GPP_D12 SPI_HOLD_ROM DBG_PMODE 20KR1J-GP
Schematic Close to U2501
1
1
R1521 sky 0329 R1523 sky 0329 R1525 R1529 20KR2J-L2-GP
2
GPP_E10 GPP_E11
R1522 sky 0329 DY
20KR1J-GP sky 0329 R1527 DY
100KR2J-1-GP
20KR2J-L2-GP 20KR2J-L2-GP 20KR2J-L2-GP 1KR2F-3-GP 20190515_neal
2
2
C C
3.3V 3.3V Disable DFXTESTMODE DISABLED

High 3.3V 3.3V (DEFAULT)
Low 1.8V 1.8V 1.8V 1.8V Enable DFXTESTMODE ENABLED
Original Ref.
GPP_C5 SPI_SI GPP_E6 GPP_B23 SPI_WP ME_UNLOCK M.2 CNVI MODES TBT LSX #0
TBT LSX #1 TBT LSX #2 TBT LSX #3 A0 GPP_E10 GPP_E11
B B
A A
<Core Design>
Wistron Corporation
Title
Title
CPU (STRAP)
Size
Size Document
DocumentNumber
Number Rev
Rev
A2 Cyborg TGL SC
Date: Sheet 15
Sheet of 105
5 4 3 2 1
5 4 3 2 1
HDD GPU
[76] GFX_PCIE_TX_P0
[60] HDD_SATA_RX_N [76] GFX_PCIE_TX_N0
[60] HDD_SATA_RX_P [76] GFX_PCIE_RX_P0
[60] HDD_SATA_TX_N [76] GFX_PCIE_RX_N0
[60] HDD_SATA_TX_P
[60] HDD_DEVSLP [76] GFX_PCIE_TX_P1
[76] GFX_PCIE_TX_N1
[76] GFX_PCIE_RX_P1
[76] GFX_PCIE_RX_N1 CPU1I
[76] GFX_PCIE_TX_P2
SSD2 (for CBG 15 NV) 9 OF 21
[76] GFX_PCIE_TX_N2 HDD1 (for CBG 14/15 L)

M.2 SSD1 [76] GFX_PCIE_RX_P2 HDD_SATA_TX_P R1613 1 2 0R2J-2-GP SSD_PCIE_TX_P3 BT7 CV4 BT_USB20_P
[76] GFX_PCIE_RX_N2 HDD_SATA_TX_N
CBG_L_HDD
CBG_L_HDD R1614 1 2 0R2J-2-GP SSD_PCIE_TX_N3 BT8 PCIE12_TXP/SATA1_TXP
PCIE12_TXN/SATA1_TXN
USB2P_10
USB2N_10
CY3 BT_USB20_N BT
HDD_SATA_RX_P CBG_L_HDD R1615 1 2 0R2J-2-GP SSD_PCIE_RX_P3 CE2
[76] GFX_PCIE_TX_P3 HDD_SATA_RX_N SSD_PCIE_RX_N3 PCIE12_RXP/SATA1_RXP WWAN_USB20_P
R1616 1 2 0R2J-2-GP CE1 DD5
D
[76]
[76]
GFX_PCIE_TX_N3
GFX_PCIE_RX_P3
CBG_L_HDD
PCIE12_RXN/SATA1_RXN USB2P_9
USB2N_9
DD4 WWAN_USB20_N WWAN D
SSD_PCIE_TX_P2 CBG_SSD2 R1611 1 2 0R2J-2-GP SSD_PCIE_TX_P0_C BT9
[76] GFX_PCIE_RX_N3 SSD_PCIE_TX_N2 SSD_PCIE_TX_N0_C PCIE11_TXP/SATA0_TXP 3D3V_VCCDSW
CBG_SSD2 R1612 1 2 0R2J-2-GP BV9 CW9
SSD_PCIE_RX_P2 CBG_SSD2 R1609 1 2 0R2J-2-GP SSD_PCIE_RX_P0_C CF4 PCIE11_TXN/SATA0_TXN USB2P_8 DA9
SSD_PCIE_RX_N2 CBG_SSD2 R1610 1 2 0R2J-2-GP SSD_PCIE_RX_N0_C CF3 PCIE11_RXP/SATA0_RXP USB2N_8
PCIE11_RXN/SATA0_RXN DD1 CARD1_USB20_P
IOBD USB 2.0 PORT WLAN_PCIE_TX_P BV7
PCIE10_TXP
USB2P_7
USB2N_7
DD2 CARD1_USB20_N Card Reader
WLAN_PCIE_TX_N BV8
[63] SSD_PCIE_TX_P2 [66] USB3_USB20_N WLAN WLAN_PCIE_RX_P CG2 PCIE10_TXN DA1 CCD_USB20_P 1 2 R1617 HDD_DET#
[63]
[63]
SSD_PCIE_TX_N2
SSD_PCIE_RX_P2
[66] USB3_USB20_P WLAN_PCIE_RX_N CG1 PCIE10_RXP
PCIE10_RXN
USB2P_6
USB2N_6
DA2 CCD_USB20_N Camera 10KR2J-3-GP
[63] SSD_PCIE_RX_N2 LAN_PCIE_TX_P CBG_L_HDD

C1614 1LAN 2 SCD1U16V2KX-3DLGP LAN_PCIE_TX_C_P BY7 DA12 FP1_USB20_P
LAN_PCIE_TX_N C1613 1LAN 2 SCD1U16V2KX-3DLGP LAN_PCIE_TX_C_N BY8 PCIE9_TXP USB2P_5 DA11 FP1_USB20_N Finger Print
[63]
[63]
SSD_PCIE_TX_P3
SSD_PCIE_TX_N3
LAN (for CBG VL only) LAN_PCIE_RX_P CG5 PCIE9_TXN
PCIE9_RXP
USB2N_5
LAN_PCIE_RX_N CG4 DC8 USB2_USB20_P
[63]
[63]
SSD_PCIE_RX_P3
SSD_PCIE_RX_N3 WWAN PCIE9_RXN USB2P_4
USB2N_4
DC7 USB2_USB20_N IO USB A
SSD_PCIE_TX_P12 CB8
SSD_PCIE_TX_N12 CB7 PCIE8_TXP DB4 USB3_USB20_P
[62] WWAN_PCIE_RX_N
[62] WWAN_PCIE_RX_P
[62] WWAN_PCIE_TX_N
SSD_PCIE_RX_P12
SSD_PCIE_RX_N12
CK5
CK4
PCIE8_TXN
PCIE8_RXP
USB2P_3
USB2N_3
DB3 USB3_USB20_N IO USB B (for L only)
PCIE8_RXN DA5 USB4_USB20_P
[62] WWAN_PCIE_TX_P
SSD_PCIE_TX_P11 CD9
PCIE7_TXP
USB2P_2
USB2N_2
DA4 USB4_USB20_N TBT
SSD_PCIE_TX_N11 CD8
M.2 SSD2 [62] WWAN_USB20_N SSD_PCIE_RX_P11 CK1 PCIE7_TXN DC11 CHAR_USB20_P
[62] WWAN_USB20_P SSD_PCIE_RX_N11 CK2 PCIE7_RXP
PCIE7_RXN
USB2P_1
USB2N_1
DC9 CHAR_USB20_N MB USB A
[63]
[63]
SSD_PCIE_TX_P9
SSD_PCIE_TX_N9 SSD1(Main) SSD_PCIE_TX_P10 CG8
PCIE6_TXP GPP_E0/SATAXPCIE0/SATAGP0
DP4 HDD_DET# 3D3V_S5_VCCPRIM
20191224
SSD_PCIE_TX_N10 CG7 DF41 M2_PEDET1
[63] SSD_PCIE_RX_N9 PCIE6_TXN GPP_A12/SATAXPCIE1/SATAGP1/I2S3_SFRM
SSD_PCIE_RX_P10 CL4
[63] SSD_PCIE_RX_P9 PCIE6_RXP
SSD_PCIE_RX_N10 CL3 DD8 USB_OC0# R1605 1 2 10KR2J-3-GP
PCIE6_RXN GPP_E9/USB_OC0# DJ45 USB_OC3# 1 2 10KR2J-3-GP
USB3.2 Type-A Port1 (MB)
[63] SSD_PCIE_TX_P10 R1607
SSD_PCIE_TX_P9 CJ8 GPP_A16/USB_OC3#/I2S4_SFRM
[63] SSD_PCIE_TX_N10 SSD_PCIE_TX_N9 PCIE5_TXP M2_DEVSLP1 20191211 20191220
CJ7 DN6 Follow Intel check list
[63] SSD_PCIE_RX_P10 SSD_PCIE_RX_P9 PCIE5_TXN GPP_E5/DEVSLP1 HDD_DEVSLP 20191223 Remove R1607 20191224
CN2 DG8
[63] SSD_PCIE_RX_N10 SSD_PCIE_RX_N9 PCIE5_RXP GPP_E4/DEVSLP0 For customer request For Customer and BIOS require
CN1
PCIE5_RXN DN29 DUAL_BOOT_EVENT# 20191211
[63] SSD_PCIE_TX_P11 WWAN_PCIE_TX_P GPP_H15/M2_SKT2_CFG3 WLAN_RF_DIS# For TBT solution 3D3V_S5_VCCPRIM
CR8 DK29
[63] SSD_PCIE_TX_N11 WWAN_PCIE_TX_N PCIE4_TXP/USB31_4_TXP GPP_H14/M2_SKT2_CFG2 PCH_TBT_PERST#
CR7 DT31
[63] SSD_PCIE_RX_P11 WWAN (for L only)
1
WWAN_PCIE_RX_P CN5 PCIE4_TXN/USB31_4_TXN GPP_H13/M2_SKT2_CFG1 DR32 TBT_FORCE_PWR
[63] SSD_PCIE_RX_N11 WWAN_PCIE_RX_N PCIE4_RXP/USB31_4_RXP GPP_H12/M2_SKT2_CFG0
CN4
PCIE4_RXN/USB31_4_RXN DV9 PCIE_RCOMP_P 1 2 100R2F-L1-GP-U R1608
C
[63] SSD_PCIE_TX_P12
CU8 PCIE_RCOMP_P DT9 PCIE_RCOMP_N
R1601 Dual Boot 100KR2J-1-GP C
[63] SSD_PCIE_TX_N12 PCIE3_TXP/USB31_3_TXP PCIE_RCOMP_N
CU7
2
[63] SSD_PCIE_RX_P12 PCIE3_TXN/USB31_3_TXN DUAL_BOOT_EVENT#
[63] SSD_PCIE_RX_N12 HDD CT2
CT1 PCIE3_RXP/USB31_3_RXP USB_VBUSSENSE
DC12
DF1
USB_VBUSSENSE
USB_ID
R1602
R1604
1
1
2 10KR2F-2-GP
2 10KR2F-2-GP
PCIE3_RXN/USB31_3_RXN USB_ID DE1 USB2_COMP R1603 1 2 113R2F-GP
[63] M2_DEVSLP1 USB2_USB30_TX_P USB2_COMP
CW8
[63] M2_PEDET1 [60] HDD_DET# USB2_USB30_TX_N CW7 PCIE2_TXP/USB31_2_TXP E3
IO USB A USB2_USB30_RX_P CU3 PCIE2_TXN/USB31_2_TXN
PCIE2_RXP/USB31_2_RXP
RSVD_BSCAN
USB2_USB30_RX_N CT4
PCIE2_RXN/USB31_2_RXN
USB1 USB1_USB30_TX_P DA8
PCIE1_TXP/USB31_1_TXP
USB1_USB30_TX_N DA7
USB3.2 Type-A Port1 (MB)
[35] USB1_USB30_RX_N
[36] CHAR_USB20_N
[36] CHAR_USB20_P
MB USB A USB1_USB30_RX_P CV2 PCIE1_TXN/USB31_1_TXN
PCIE1_RXP/USB31_1_RXP
USB1_USB30_RX_N CV1
[35] USB1_USB30_RX_P PCIE1_RXN/USB31_1_RXN
[35] USB1_USB30_TX_N
[35] USB1_USB30_TX_P
TGL-U-1-GP-U2
[35,36] USB_OC0#
USB2
USB3.2 Type-A Port2 (IO)
[66] USB2_USB30_RX_P
[66] USB2_USB30_TX_N
[66] USB2_USB20_P
[66] USB2_USB20_N
Card Reader
[66] CARD1_USB20_P
[66] CARD1_USB20_N
B B
Camera
[55] CCD_USB20_P
[55] CCD_USB20_N
Finger Print
[66] FP1_USB20_N
[66] FP1_USB20_P
TpyeC
[72] USB4_USB20_P
[72] USB4_USB20_N
[71,72] TBT_FORCE_PWR
PD
[17,71] PCH_TBT_PERST#
BT
[61] BT_USB20_P
[61] BT_USB20_N CPU1H 8 OF 21
WLAN GFX_PCIE_TX_P3 C1605 1 2 SCD22U10V1KX-1-GP

OPS GFX_PCIE_TX_C_P3 P5
PCIE4_TX_P3
GPU
PCIE4_TX_P1
V5 GFX_PCIE_TX_C_P1 SCD22U10V1KX-1-GP 2
OPS 1 C1601 GFX_PCIE_TX_P1
GFX_PCIE_TX_N3 1 2 SCD22U10V1KX-1-GP GFX_PCIE_TX_C_N3 P7 V7 GFX_PCIE_TX_C_N1 2 1 GFX_PCIE_TX_N1
C1606 OPS GFX_PCIE_RX_P3 N1 PCIE4_TX_N3 PCIE4_TX_N1 T1 GFX_PCIE_RX_P1
SCD22U10V1KX-1-GP OPS C1602
[61] WLAN_RF_DIS# GPU GFX_PCIE_RX_N3 N2 PCIE4_RX_P3
PCIE4_RX_N3
PCIE4_RX_P1
PCIE4_RX_N1
T2 GFX_PCIE_RX_N1 GPU
[61] WLAN_PCIE_RX_N
GFX_PCIE_TX_P2 1 2 SCD22U10V1KX-1-GP GFX_PCIE_TX_C_P2 T5 Y5 GFX_PCIE_TX_C_P0 2 1 GFX_PCIE_TX_P0
A
[61] WLAN_PCIE_RX_P
GFX_PCIE_TX_N2
C1607
1
OPS
2 SCD22U10V1KX-1-GP GFX_PCIE_TX_C_N2 T7 PCIE4_TX_P2 PCIE4_TX_P0 Y7 GFX_PCIE_TX_C_N0
SCD22U10V1KX-1-GP OPS
2 1
C1603
GFX_PCIE_TX_N0 A
[61] WLAN_PCIE_TX_N C1608 OPS GFX_PCIE_RX_P2 R1 PCIE4_TX_N2 PCIE4_TX_N0 V1 GFX_PCIE_RX_P0
SCD22U10V1KX-1-GP OPS C1604
[61] WLAN_PCIE_TX_P PCIE4_RX_P2 PCIE4_RX_P0
GFX_PCIE_RX_N2 R2 V2 GFX_PCIE_RX_N0
PCIE4_RX_N2 PCIE4_RX_N0
Y12 PCIE4_RCOMP_P 1 2 2K2R2F-GP
LAN PCIE4_RCOMP_P
PCIE4_RCOMP_N
V12 PCIE4_RCOMP_N
R1606
<Core Design>
[66] LAN_PCIE_RX_N
[66] LAN_PCIE_RX_P
[66] LAN_PCIE_TX_N Wistron Corporation
[66] LAN_PCIE_TX_P 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
Title
[24,62] DUAL_BOOT_EVENT# CPU (PCIE/SATA/USB)
Size
Size Document
DocumentNumber
Number Rev
Rev
A2 Cyborg TGL SC
Date: Sheet 16
Sheet of 105
5 4 3 2 1
5 4 3 2 1
CPU1L 12 OF 21 20191217
Follow Intel Requirement
[61,62,63,66,71,76,91] PCH_PLTRST# 20191220
Follow vendor suggest
SIO_SLP_SUS# DV49 BM9 TP_VCORE_PWRGD 1 follow 612304 Ver0.9
SLP_SUS# PROCPWRGD DK41 SIO_PWRBTN# TP1702
DM43: SIO_SLP_S5# 1 SIO_SLP_S5# DM43 GPD3/PWRBTN# DN41 PCH_BATLOW# 3D3V_S5
[27,40,55,81] SIO_SLP_S3# TP1705 20191219
DR41: SIO_SLP_A# SIO_SLP_S4# DJ41 GPD10/SLP_S5# GPD0/BATLOW# DK43 AC_PRESENT Follow Nakia
DT44: SIO_SLP_WLAN# SIO_SLP_S3# DJ43 GPD5/SLP_S4# GPD1/ACPRESENT 20200330(DVT2)
[51,66] SIO_SLP_S4# DR41 GPD4/SLP_S3# CW40 TBT_PD_ALERT# Follow CY20 change to 3.3V_S5
1
GPD6/SLP_A# GPP_B11/PMCALERT# TP1703
2
DT44 DN27 CPU_C10_GATE#
GPD9/SPL_WLAN# GPP_H18/CPU_C10_GATE# DG31 TPM_PRSNT# R1742
SIO_SLP_S0# GPP_H3/SX_EXIT_HOLDOFF#
[25,45] 3V_5V_PWRGD TP1709
1 DD42
GPP_B12/SLP_S0# PCH_PCIE_WAKE#
fwTPM 100KR2J-1-GP
DN39 DK39
SLP_LAN# WAKE#
[24] SIO_PWRBTN#
1
PM_RSMRST# DM35 DM41 LAN_WAKE# 20200224(DVT1) TPM_PRSNT#
SYS_RESET# DD10 RSMRST# GPD2/LAN_WAKE# DT41 Reserve 0 ohm to GPD7
D 20191112 modify 20191119 modify D
Follow Nakia Follow EC GPIO review PCH_PLTRST# DD41 SYS_RESET# GPD11/LANPHYPC/DSWLDO_MON
non-G3 GPP_B13/PLTRST#
2
20191203 modify DN43 PCH_TBT_PERST#_GPD7 R1748 1 2 0R2J-2-GP PCH_TBT_PERST#
[24,26] IMVP_VR_ON Follow Nakia PCH_DPWROK R1723 DSW_PWROK_R DK35 GPD7 DY
1 2 0R2J-2-GP R1743
20191206 modify SYS_PWROK DSW_PWROK VCCSTPWRGOOD_TCSS VCCST_OVERRIDE
[24] PCH_RSMRST# For High limit ALL_SYS_PWRGD D1704K DYA RB520S30-GP PCH_PWROK
DF10
SYS_PWROK VCCSTPWRGOOD_TCSS
CE5
VCCST_PWRGD_R
1 R1731 2 TPM 100KR2J-1-GP
DN35 BP8 0R0402-PAD-7-NP-GP
PCH_PWROK VCCST_PWRGD BP9 VCCST_OVERRIDE_R 1 R1728 2 VCCST_OVERRIDE
VCCST_OVERRIDE
1
PWR_IMVP_PWRGD 1 R1745 2 RTC_INTRUDER# DM37 0R0402-PAD-7-NP-GP
0R0402-PAD-7-NP-GP SPI_VCC_SEL DT49 INTRUDER# DR12 EXT_PWR_GATE#
[17,24,40,44,46] ALL_SYS_PWRGD IMVP_VR_ON 1 R1746 2 SPIVCCIOSEL GPP_F20/EXT_PWR_GATE# DW12 EXT_PWR_GATE2#
0R0402-PAD-7-NP-GP GPP_F21/EXT_PWR_GATE2#
[24] SYS_PWROK
TGL-U-1-GP-U2 20191111 follow Nakia
3D3V_S5
[24,40] SIO_SLP_SUS#
1 2 1KR2F-3-GP PCH_PCIE_WAKE#
3rd = 083.52030.0C8F SPI SELECT STRAP SPI SELECT STRAP R1727
[40] VCCST_OVERRIDE
D1701 2nd = 083.52030.008F Cap LOW → 3.3V LOW → 3.3V
A
RB520S30-GP
K
83.R2003.A8M
AC_IN# Cap DY → 1.8V HIGH → 1.8V
3D3V_S5_VCCPRIM PCH_PLTRST#
[64] PM_RSMRST# Q1702 3D3V_RTC_AUX 3D3V_S5_VCCPRIM
AC_PRESENT SYS_RESET# 20191225
1 6 R1701 1 2 10KR2J-3-GP
Note:ZZ.27002.F7C01
Follow Intel check list
3D3V_AUX_S5 20200304
[40] CPU_C10_GATE#
2
1
1
2 5 PM_RSMRST# R1704 R1705 3D3V_S5_VCCPRIM Change SYS_RESET# PU to 3D3V_S5_VCCPRIM
20191224 R1744
R1737 1 2 PM_RSMRST#_M 3 4 1 2 AC_PRESENT
DY Follow Internal review R1713
1 2
100KR2J-1-GP
PCH_BATLOW#
100KR2J-1-GP
100KR2J-1-GP R1715 10KR2J-3-GP
2N7002KDW-1-GP 1MR2F-GP 4K7R2J-2-GP R1740 1 2 100KR2J-1-GP EXT_PWR_GATE#
DY
1
2
2
[24] PCH_DPWROK 1 2 EXT_PWR_GATE2#
75.27002.F7C RTC_INTRUDER# SPI_VCC_SEL
R1741
DY
100KR2J-1-GP
20191112 modify
[44] AC_IN# 2nd = 075.27002.0E7C need confirm
3rd = 075.07002.0A7C 1 2 10KR2J-3-GP LAN_WAKE#
R1724
1
C1701 R1714 R1706
[17,24,40,44,46] ALL_SYS_PWRGD 4K7R2J-2-GP
1MR2F-GP
SCD1U16V2KX-3DLGP
3D3V_S5 DY
2
C C
VCCST_OVERRIDE 1 2
Volatge Level 1V R1730 100KR2J-1-GP
teknisi indonesia
2
C1702 PCH_PWROK R1732 1 2 100KR2J-1-GP
SYS_PWROK 1 2
SCD1U16V2KX-3DLGP
R1733 100KR2J-1-GP
[24] LAN_WAKE# 1D05V_VCCST DSW_PWROK_R R1734 1 2 100KR2J-1-GP
1
20191220
20191217 Follow Intel design
[44,46] PWR_IMVP_PWRGD Follow Nakia N7
1
U1704 R1702
From EC Control
2
1 5
[72] TBT_PD_ALERT# NC#1 VCC
ALL_SYS_PWRGD 2 1KR2F-3-GP 3V_5V_PWRGD R1750 1 2 68KR2F-GP DSW_PWROK_R
A
1
3 4 VCCST_PWRGD_RR R1703 1 2 60D4R2F-GP VCCST_PWRGD_R C1750
GND Y DY
SCD1U10V2KX-4DLGP
[24] EC_RESET#
2
74LVC1G07GW-GP
DY
[16,71] PCH_TBT_PERST# 73.01G07.0HG 11.11 Follow Nakia
20191211 20191112 modify
2nd = 073.7SZ07.000G Remove R1725, R1726
[24,40,50] VCCIN_AUX_PWRGD 3D3V_AUX_S5
R1707 1 2 100KR2J-1-GP
1
R1708
Q1701
4 3 PM_RSMRST# 1 2 1KR2J-1-GP PCH_RSMRST#
10KR2J-3-GP R1709 DY
2
3V_5V_POK# 5 2 3V_5V_POK_C D1705 A K RB520S30-GP 3V_5V_PWRGD

Note:ZZ.27002.F7C01
83.R2003.A8M 2nd = 083.52030.008F 3rd = 083.52030.0C8F

1
6 1 R1711
D1706 A K RB520S30-GP VCCIN_AUX_PWRGD SCD1U16V2KX-3DLGP 3D3V_S5 20191223
20191213
B 2N7002KDW-1-GP 83.R2003.A8M 2nd = 083.52030.008F 3rd = 083.52030.0C8F C1714
2 1
Follow HC ICL for G3 sharing
Change Part number B
75.27002.F7C U1703 0R0201-PAD-GP
2nd = 075.27002.0E7C 100KR2J-1-GP R1772
2
3rd = 075.07002.0A7C 1 8 3V_5V_PWRGD_U 1 2 3V_5V_PWRGD

PCH_RSMRST# 1 2 PCH_RSMRST#_U 2 VDD 3V_5V_PWRGD 7
PCH_DPWROK 1 2 PCH_DPWROK_R 3 PCH_RSMRST# NC#7 6 EC_RESET#_R 1 2 EC_RESET#
3D3V_S5_R 1 2 3D3V_S5_U 4 PCH_DPWPOK EC_PCH_SPI_EN 5 R1774
R1773 0R0201-PAD-GP DSW_PWROK GND 0R0201-PAD-GP
R1775 0R0201-PAD-GP
R1771 0R0201-PAD-GP SLG4E43789VTR-1-GP
074.43789.M001
2nd = 074.03904.0053
SC_191206_add RN1701 R1771 R1772 R1773 R1774 R1775
SC_191209_delete RN1701 and add U1703
SC_191211 add C1714
R1777 D1707
SIO_SLP_SUS# 1 2SIO_SLP_SUS#_R K A
DY 83.R2003.A8M
3D3V_S5 3D3V_S5_VCCPRIM 0R1J-GP DY 2nd = 083.52030.008F
20191121 RB520S30-GP
Follow ICL G3 Rework 3D3V_S5
U1710
3D3V_S5 3rd = 083.52030.0C8F
R1738 1 2 3D3V_S5_PCH_R 1 Q1703 R1735
390KR2F-GP 5 4 3 Q1703_2_3 2 1 100KR2J-1-GP
R1721 1 2 3D3V_S5_R 2 DY
100KR2J-1-GP 4 DSW_PWROK_R 5 2 3D3V_S5
C1713
Note:ZZ.27002.F7C01
DY
1
1
3 U1702
SCD1U16V2KX-3DLGP
C1712 DSW_PWROK 6 1 R1736 PCH_RSMRST# 1

3V_5V_PWRGD K A
DY 10KR2F-2-GP
1
SCD1U16V2KX-3DLGP
TC7SZ08FU-LJ-CT-GP 5
83.R2003.A8M D1708
2
DSW_PWROK
RB520S30-GP 073.7SZ08.000G DY 2N7002KDW-1-GP 2
2nd = 083.52030.008F 2nd = 73.7SZ08.DAH 75.27002.F7C 4 PM_RSMRST#
2
2
3rd = 083.52030.0C8F DSW_PWROK 3
2nd = 075.27002.0E7C
D1702
DY K PCH_DPWROK 3rd = 075.07002.0A7C
1
3D3V_S5_R A TC7SZ08FU-LJ-CT-GP
R1739 073.7SZ08.000G
RB520S30-GP DY 1MR2F-GP 2nd = 73.7SZ08.DAH
A 83.R2003.A8M R1776 0R1J-GP 20191220
Follow Intel design
A
2nd = 083.52030.008F 1 2
2
3rd = 083.52030.0C8F 1 2
DY R1751
0R0402-PAD-7-NP-GP <Core Design>
D1703
DSW_PWROK A PCH_DPWROK
DYK
RB520S30-GP
20191213
Follow HC ICL for G3 sharing
Wistron Corporation
83.R2003.A8M Taipei Hsien 221, Taiwan, R.O.C.
2nd = 083.52030.008F
3rd = 083.52030.0C8F Title
Title
CPU (PMU)
Size
Size Document
DocumentNumber
Number Rev
Rev
Custom Cyborg TGL SC
Date: Sheet
Sheet 17 of 105
5 4 3 2 1
5 4 3 2 1
SPI ROM
3D3V_S0
[24,25,91] SPI_CLK_ROM 3D3V_S5
[15,24,25] SPI_HOLD_ROM
RN1803
[15,24,25] SPI_WP_ROM 1 R1821 2 SPK_ID 1 4 CPU_SMB_SCL
[24,25,91] SPI_SO_ROM 2 3 CPU_SMB_SDA
[15,24,25,91] SPI_SI_ROM
10KR2J-3-GP
[24,25] SPI_CS_ROM_N0
SRN1KJ-7-GP
[91] SPI_CS_ROM_N2 3D3V_S5
RN1807
[17,64] PM_RSMRST# 1 4 CPU_SML_SCL0
3D3V_S0
2
DY 3 CPU_SML_SDA0
RN1804
CPU1E 5 OF 21 R1802 1 4 EC_I2C_SCL_THM
SRN1KJ-7-GP
SATA_LED# 1 2 2 3 EC_I2C_SDA_THM
10KR2J-3-GP RN1801
D 1 4 CPU_SML_SCL1_PD SRN1KJ-7-GP D
SPI_CLK_ROM 1 SPI_CLK_R_CPU
2 0R0402-PAD-7-NP-GP DJ37 DK21 CPU_SMB_SCL 20191217 2 3 CPU_SML_SDA1_PD
R1826 SO-DIMM Follow HC TGL 13
SPI_HOLD_ROM R1827 1 SPI_HOLD_R_CPU
2 0R0402-PAD-7-NP-GP DG35 SPI0_CLK GPP_C0/SMBCLK DM19 CPU_SMB_SDA
SPI_WP_ROM R1828 1 SPI_WP_R_CPU
2 0R0402-PAD-7-NP-GP DJ39 SPI0_IO3 GPP_C1/SMBDATA DN19 CPU_SMB_ALERT# SRN2K2J-1-GP
SPI_SO_ROM R1829 1 SPI_SO_R_CPU
2 0R0402-PAD-7-NP-GP DJ33 SPI0_IO2 GPP_C2/SMBALERT#
SPI_SI_ROM R1830 1 SPI_SI_R_CPU
2 0R0402-PAD-7-NP-GP DJ35 SPI0_MISO DK19 CPU_SML_SCL0
SPI0_MOSI GPP_C3/SML0CLK BB (Reserved) R1823
BIOS ROM_16 SPI_CS_ROM_N1
SPI_CS_ROM_N0
R1831 1 2 0R2J-2-GP SPI_CS_CPU_N1
SPI_CS_CPU_N0
DF35
SPI0_CS1# GPP_C4/SML0DATA
DM17 CPU_SML_SDA0
CPU_SML0_ALERT#
1 DY 2 CPU_SMB_ALERT#
R1832 1 2 0R0402-PAD-7-NP-GP DG37 DN17 1D8V_S5 10KR2J-3-GP
SPI_CS_ROM_N2 DF39 SPI0_CS0# GPP_C5/SML0ALERT#
EC SPI0_CS2#
GPP_C6/SML1CLK
DK17 CPU_SML_SCL1_PD
PD
R1824
1 2 20191225
GPP_E11 DJ6 DJ17 CPU_SML_SDA1_PD 10KR2J-3-GP Reserve for debug
[24,68] ESPI_IO0 DN5 GPP_E11/SPI1_CLK/THC0_SPI1_CLK GPP_C7/SML1DATA CY50 CPU_SML1_ALERT# GPP_B23 Strap pin can't pull High
[24,68] ESPI_IO1 GPP_E2/SPI1_IO3/THC0_SPI1_IO3 GPP_B23/SML1ALERT#/PCHHOT#/GSPI1_CS1# R1825
DR9 Follow Bacchus 1 DY 2 CPU_SML1_ALERT#
[24,68] ESPI_IO2 DM6 GPP_E1/SPI1_IO2/THC0_SPI1_IO2 DN53 ESPI_PCH_CLK 1 2 49D9R2F-GP ESPI_CLK
R1804 10KR2J-3-GP
[24,68] ESPI_IO3 DK6 GPP_E12/SPI1_MISO_IO1/THC0_SPI1_IO1 GPP_A5/ESPI_CLK DJ53 ESPI_PCH_IO3 1 2 15R2F-2-GP ESPI_IO3
R1808
GPP_E10 DK8 GPP_E13/SPI1_MOSI_IO0/THC0_SPI1_IO0 GPP_A3/ESPI_IO3/SUSACK# DH50 ESPI_PCH_IO2 R1807 1 2 15R2F-2-GP ESPI_IO2
[24,68] ESPI_CS# SATA_LED# DV11 GPP_E10/SPI1_CS#/THC0_SPI1_CS# GPP_A2/ESPI_IO2/SUSWARN#_SUSPWRDNACK DP50 ESPI_PCH_IO1 1 2 15R2F-2-GP ESPI_IO1
R1806
[24,68] ESPI_RESET# DGPU_HOLD_RST# DW9 GPP_E8/SPI1_CS1#/SATA_LED# GPP_A1/ESPI_IO1 DP52 ESPI_PCH_IO0 1 2 15R2F-2-GP ESPI_IO0
R1805 to EC,debug14pin
[24,68] ESPI_CLK GPP_E6 DT8 GPP_E17/THC0_SPI1_INT# GPP_A0/ESPI_IO0 DK52 ESPI_PCH_CS# 1 ESPI_CS#
2 0R0402-PAD-7-NP-GP 3D3V_S0
R1809
GPP_E6/THC0_SPI1_RST# GPP_A4/ESPI_CS# DL50 ESPI_PCH_RESET# R1810 1 ESPI_RESET#
2 0R0402-PAD-7-NP-GP RN1808
GC6_FB_EN 1 GC6_FB_EN_MCP GPP_A6/ESPI_RESET#
OPS 2 SPK_ID
DN15
DK13 GPP_F11/THC1_SPI2_CLK
R1814 1 2 75KR2F-GP 1
2
4
3
Audio R1842
0R0402-PAD-7-NP-GP DM13 GPP_F15/GSXSRESET#/THC1_SPI2_IO3
GPP_F14/GSXDIN/THC1_SPI2_IO2
1 HOST_SD_WP# DN13 20191211
TP1801 WWAN_DB_DET# DJ15 GPP_F13/GSXSLOAD/THC1_SPI2_IO1 Follow Intel CRB use 1% SRN1KJ-7-GP
[29] SPK_ID WWAN_BB_RST# DK15 GPP_F12/GSXDOUT/THC1_SPI2_IO0
DN10 GPP_F16/GSXCLK/THC1_SPI2_CS# Q1802
GPP_F18/THC1_SPI2_INT#
1
DV14 CPU_SMB_SDA 6 1 CPU_SMB_SDA_DDR
Note:ZZ.27002.F7C01
R1812 GPP_F17/THC1_SPI2_RST#
M.2 SSD DY 75KR2F-GP DH3

DH4 CL_CLK
5 2
DF2 CL_DATA 4 3
[63] SSD_CLK_CPU_N CL_RST#
2
[63] SSD_CLK_CPU_P
[63] SSD_CLKREQ_CPU_N 2N7002KDW-1-GP CPU_SMB_SCL_DDR
[64] SATA_LED#
CPU1K 11 OF 21 CPU_SMB_SCL 75.27002.F7C
[63] SSD2_CLK_CPU_P
[63] SSD2_CLK_CPU_N 3D3V_S0 2nd = 075.27002.0E7C
[63] SSD2_CLKREQ_CPU_N 3rd = 075.07002.0A7C
RN1805
WWAN_CLK_CPU_P BW1 DU14 WWAN_CLKREQ_CPU_N 1 8 CLK_PCIE_LAN_REQ#
C WWAN_CLK_CPU_N BW2 CLKOUT_PCIE_P6 GPP_F19/SRCCLKREQ6# DF23 SSD2_CLKREQ_CPU_N 2 7 CLK_PCIE_PEG_REQ# C
CLKOUT_PCIE_N6 GPP_H11/SRCCLKREQ5# DG25 SSD_CLKREQ_CPU_N 3 6 CLK_PCIE_WLAN_REQ#
SSD2_CLK_CPU_P CB2 GPP_H10/SRCCLKREQ4# DT24 4 5 SSD2_CLKREQ_CPU_N
GPU SSD2 SSD2_CLK_CPU_N CB1 CLKOUT_PCIE_P5
CLKOUT_PCIE_N5
GPP_D8/SRCCLKREQ3#
GPP_D7/SRCCLKREQ2#
DT30 CLK_PCIE_LAN_REQ#
DV30 CLK_PCIE_WLAN_REQ#
GPP_D6/SRCCLKREQ1# DW30 CLK_PCIE_PEG_REQ# R1844 20200302(DVT1) SRN10KJ-6-GP
[76] GFX_CLK_CPU_N SSD_CLK_CPU_P BW4 GPP_D5/SRCCLKREQ0# Add R1844 R1845 for EMC protect
[76] GFX_CLK_CPU_P
[76] CLK_PCIE_PEG_REQ#
SSD1 SSD_CLK_CPU_N BW5 CLKOUT_PCIE_P4
CLKOUT_PCIE_N4 XTAL_OUT
DM1 XTL_38D4M_X2_CPU 1
33R2J-2-GP
2 XTL_38D4M_X2 R1801 1 2 SSD_CLKREQ_CPU_N
DL1 XTL_38D4M_X1_CPU 1 2 XTL_38D4M_X1 10KR2J-3-GP
CL7 XTAL_IN R1845 R1803 1 2 WWAN_CLKREQ_CPU_N
[76] DGPU_HOLD_RST# CL8 CLKOUT_PCIE_P3 DW41 SUSCLK 33R2J-2-GP 10KR2J-3-GP
[79,86] GC6_FB_EN CLKOUT_PCIE_N3 GPD8/SUSCLK
LAN_CLK_CPU_P CB4 DT47 XTL_32K_X2_CPU
LAN LAN_CLK_CPU_N CB5 CLKOUT_PCIE_P2
CLKOUT_PCIE_N2
RTCX2
RTCX1
DR47 XTL_32K_X1_CPU
3D3V_RTC_AUX
SMBUS WLAN_CLK_CPU_P BY4 DN37 RTC_RST#
WLAN WLAN_CLK_CPU_N BY3 CLKOUT_PCIE_P1
CLKOUT_PCIE_N1
RTCRST#
SRTCRST#
DK37 SRTC_RST#
[12,13] CPU_SMB_SCL_DDR
1
2
GFX_CLK_CPU_P CN7
[12,13] CPU_SMB_SDA_DDR GPU GFX_CLK_CPU_N CN8 CLKOUT_PCIE_P0
CLKOUT_PCIE_N0
RN1802
[72] CPU_SML_SCL1_PD SRN20KJ-1-GP
R1819 2 1 60D4R1F-GP XCLK_BIASREF DJ5
[72] CPU_SML_SDA1_PD TGL-U-1-GP-U2 XCLK_BIASREF
[24,71] CPU_SML_SCL0
TGL-U-1-GP-U2
[24,71] CPU_SML_SDA0
4
3
SRTC_RST#
[24] EC_I2C_SCL_THM XTL_38D4M_X1 RTC_RST#
[24] EC_I2C_SDA_THM
SC1U10V2KX-1DLGP
2
XTL_38D4M_X2
OTHER
1
XTL_32K_X2_CPU
C1803
G1801
1
C1804
XTL_32K_X1_CPU 1 2 200KR2F-L-GP
GAP-OPEN
DJ6: TS_SPI_CLK R1820 SC1U10V2KX-1DLGP
[24,61] SUSCLK
2
DN5: TS_SPI_IO3
2
DR9: TS_SPI_IO2
DM6: TS_SPI_SO 1 2 10MR2J-L-GP X1802
R1811
HW STRAP DK6:
DK8:
TS_SPI_SI
TS_SPI_CS# 2 3
1 2
[15] CPU_SML0_ALERT# DW9: DGPU_HOLD_RST# C1802 X1801 C1801 Layout: Place at the open door area.
SC15P50V2JN-DL-GP
SC15P50V2JN-DL-GP
DK13: SPK_ID XTAL-32D768KHZ-88-GP

[15] GPP_E6 DM13: AUD_PWR_EN 1 4
082.30003.0191
1
B DN13: HOST_SD_WP# B
[15] GPP_E10 2nd = 082.30003.0301 C1806 C1805
SC12P50V2JN-DL-GP
SC12P50V2JN-DL-GP
DJ15: WWAN_DB_DET# 3rd = 082.30003.0A11
DK15: USBC1_AUX_P_BIAS XTAL-38D4MHZ-53-GP
[15] GPP_E11
2
1
082.30040.0381
DV14: USBC1_AUX_N_BIAS 2nd = 082.30040.0251
DT24: CLK_PCIE_SD_REQ# 3rd = 082.30040.0241
2
2
DT30: CLK_PCIE_LAN_REQ#
DK21: MEM_SMBCLK
DM19: MEM_SMBDATA
DN19: SMLB_ALERT#
LAN
[66] LAN_CLK_CPU_N
[66] LAN_CLK_CPU_P
[66] CLK_PCIE_LAN_REQ#
3D3V_S5
WLAN
[61] WLAN_CLK_CPU_P
1
[61] WLAN_CLK_CPU_N WWAN R2002

[61] CLK_PCIE_WLAN_REQ#
10KR2J-3-GP
2
WWAN_DB_DET#
WWAN 0508
[62] WWAN_CLKREQ_CPU_N
[62] WWAN_CLK_CPU_N
[62] WWAN_CLK_CPU_P
[62] WWAN_BB_RST#
SITP
A A
<Core Design>
Wistron Corporation
[62] WWAN_DB_DET# 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
Title
CPU (SPI/LPC/SMBS/XTAL/CLK)
Size
Size Document
DocumentNumber
Number Rev
Rev
A2 Cyborg TGL SC
Date: Sheet 18
Sheet of 105
5 4 3 2 1
5 4 3 2 1
Audio
[27] HDA_SYNC_CODEC
[27] HDA_BITCLK_CODEC
[27] HDA_SDOUT_CODEC
[27] HDA_SDIN0_CPU 20191112 modify
[15] HDA_SDOUT_CPU 1D8V_S5 Follow Nakia
3D3V_S0
[55] DMIC_PCH_CLK_Q
[55] DMIC_PCH_DATA_Q 1 2 1KR1J-GP RTC_DET#
R1949 CBG_L_HDD
1 2 FFS_INT2
GPU SNDW_RCOMP R1903 1 2 200R2F-L-GP R1907 10KR2J-3-GP
[24,85] DGPU_PWROK 1 2 IR_CAM_DET#
D DY D
R1929 10KR2J-3-GP
[86] DGPU_PWR_EN
G SENSOR
[70] FFS_INT2 CPU1G
ID Description Setting Mapping
Colse to R1904 7 OF 21
1D8V_S5_VCCPRIM
1 DY2
RTC EC1901 SC10P50V2JN-4DLGP
TBT_DET# TBT function detected
1 no TBT
HDA_BITCLK_CODEC 1 2 33R2J-2-GP HDA_BITCLK_CPU DR38 DW15
1
R1904
[25] RTC_DET# HDA_SYNC_CODEC R1901 1 2 33R2J-2-GP HDA_SYNC_CPU DU37 GPP_R0/HDA_BCLK/I2S0_SCLK GPP_F8/I2S_MCLK2_INOUT DW24 IR_CAM_DET#
HDA_SDOUT_CODEC HDA_SDOUT_CPU GPP_R1/HDA_SYNC/I2S0_SFRM GPP_D19/I2S_MCLK1 R1906 0 Have TBT
R1905 1 2 33R2J-2-GP DT37 10KR2J-3-GP
HDA_SDIN0_CPU R1918 1 2 0R0402-PAD-7-NP-GP HDA_SDIN0_CPU_R DV37 GPP_R2/HDA_SDO/I2S0_TXD DG41 DGPU_PWROK
ME_FWP_SW 1 2 1KR1J-GP GPP_R3/HDA_SDI0/I2S0_RXD GPP_A23/I2S1_SCLK DT38 BOARD_ID1 NO TBT
BT R1902
CPU_ID2 GPP_R7/I2S1_SFRM DV38 BOARD_ID2
20191211
2
DV41 For TBT solution TBT_DET#
DMIC_PCH_CLK DL53 GPP_R4/HDA_RST# GPP_R6/I2S1_TXD DW38 RTC_DET#
[61] BT_RADIO_DIS# DMIC_PCH_DATA DG51 GPP_A7/I2S2_SCLK/DMIC_CLK_A0 GPP_R5/HDA_SDI1/I2S1_RXD
1
DW15: CAM_MIC_CBL_DET# FFS_INT2 DG50 GPP_A8/I2S2_SFRM/CNV_RF_RESET#/DMIC_DATA_0 DN31 TBT_DET#
GPP_A10/I2S2_RXD/DMIC_DATA1 GPP_S6/SNDW3_CLK/DMIC_CLK_A0 R1919
DN31: TBT_DET# DM31 CPU_ID1 10KR2J-3-GP
DGPU_PWR_EN DL49 GPP_S7/SNDW3_DATA/DMIC_DATA0
3D3V_S5_VCCPRIM
DL52 GPP_A9/I2S2_TXD/MODEM_CLKREQ/CRF_XTAL_CLKREQ/DMIC_CLK_A1 DK33 VRAM_ID1 Have TBT
ME GPP_A11/PMC_I2C_SDA/I2S3_SCLK GPP_S4/SNDW2_CLK/DMIC_CLK_A1 VRAM_ID2
2
DK31
R1928 R1941 BT_RADIO_DIS# DH49 GPP_S5/SNDW2_DATA/DMIC_DATA1
[98] ME_FWP_SW 1 2DGPU_PWR_EN 1 2 GPP_A13/PMC_I2C_SCL/I2S3_TXD/DMIC_CLK_B0 DW35 PROJECT_ID2
DY OPS SNDW_RCOMP DF33 GPP_S2/SNDW1_CLK/DMIC_CLK_B0 DV35 PROJECT_ID3
10KR2J-3-GP 10KR2J-3-GP SNDW_RCOMP GPP_S3/SNDW1_DATA/DMIC_CLK_B1
DT32 PROJECT_ID0
GPP_S0/SNDW0_CLK DR35 PROJECT_ID1
GPP_S1/SNDW0_DATA
TGL-U-1-GP-U2
For SITP 20191129

Follow ICL PROJECT_ID[3:2]
20191126
For High Limit PROJECT_ID[1:0] ID Description Setting Mapping
20200212
1D8V_S5_VCCPRIM 1D8V_S5_VCCPRIM 1D8V_S5_VCCPRIM 1D8V_S5_VCCPRIM
no need level shift
20200331 11 Inspiron
ADD LEVEL SHIFT to Verify
1
C R1920 R1922 R1924 R1926 C
20200416(DVT2) 10 Vostro
Follow MKB AMD solution Inspiron/Vostro Inspiron/Latitude CBG L/CBG NV/WM N PROJECT_ID[3:2] Project Type
20200508(DVT2) CBG L
Follow Nakia add DATA's Solution 10KR1J-GP 10KR1J-GP 10KR1J-GP 10KR1J-GP 01 Latitude
2
[55] IR_CAM_DET# PROJECT_ID3 PROJECT_ID2 PROJECT_ID1 PROJECT_ID0
R1942 00 N/A
1
U1901_2 1 2 U1901_4 R1921 R1923 R1925 R1927
DY 11 3000 Series
0R1J-GP 3D3V_S5 Latitude Vostro DY CBG NV/WM N
10 5000 Series
20200424(DVT1) 10KR1J-GP 10KR1J-GP 10KR1J-GP 10KR1J-GP PROJECT_ID[1:0] Project Series
2
U1901 R1944 change to 0 ohm 01 7000 Series
1 5
DMIC_PCH_CLK 1 R1943 2 2 00 N/A
0R0402-PAD-7-NP-GP 3 4 1 R1944 2 DMIC_PCH_CLK_Q
0R0402-PAD-7-NP-GP
M74VHC1GT50DFT1G-GP
73.1GT50.00H 1D8V_S5_VCCPRIM 1D8V_S5_VCCPRIM
1
1
1
R1945 DY
C1901 C1902
SC27P50V2JN-2-GP
2nd = 073.74134.0A0G DY1KR1F-GP

SCD1U16V2KX-3DLGP
1
R1908 ID Description Setting Mapping R1910 ID Description Setting Mapping
2
2
OPS_N18 Size_14 inch

2
10KR1J-GP 10KR1J-GP
2
BOARD_ID2 BOARD_ID1
R1948
U1902_4 1 2 U1902_2 1 N18S 1 14 inch
1
DY R1911 R1909
0R1J-GP OPS_N17
1D8V_S5 BOARD_ID2 GPU type detected Size_15 inch BOARD_ID1 NVL Size detected
10KR1J-GP 10KR1J-GP
2
2
U1902 0 N17S 0 15 inch
5 1
2 1 R1947 2 DMIC_PCH_DATA_Q
DMIC_PCH_DATA 1 R1946 2 4 3 0R0402-PAD-7-NP-GP
B 0R0402-PAD-7-NP-GP B
M74VHC1GT50DFT1G-GP 1D8V_S5_VCCPRIM 1D8V_S5_VCCPRIM
73.1GT50.00H 20191112 modify CY19 VRAM ID Mapping table
1
Follow Nakia
DY C1903
1
1
R1950 R1912 20191126 R1914
SC27P50V2JN-2-GP
DY1KR1F-GP 2nd = 073.74134.0A0G For High Limit

ID Description Setting Mapping
2
UMA 4GB VRAM/UMA

1
C1904
2
SCD1U16V2KX-3DLGP 10KR1J-GP 10KR1J-GP

2
2
11 UMA Board
2
VRAM_ID2 VRAM_ID1
1
1
R1913 R1915 10 N/A
2GB VRAM/4GB VRAM 2GB VRAM VRAM_ID[2:1] dGPU VRAM size
10KR1J-GP 10KR1J-GP
01 DIS Board with 4GB VRAM
2
00 DIS Board with 2GB VRAM
1D8V_S5_VCCPRIM 1D8V_S5_VCCPRIM
CY19 CPU ID Mapping table
1
R1916 R1930
CPU_H35/CPU_H35_RE CPU_U_RE/CPU_H35_RE ID Description Setting Mapping

10KR1J-GP 10KR1J-GP
2
CPU_ID2 CPU_ID1 11 TGL-H35 Re-flash

1
R1917 R1931 10 TGL-H35

CPU_U/CPU_U_RE CPU_U/CPU_H35 CPU_ID[2:1] CPU type Select
10KR1J-GP 10KR1J-GP
01 TGL-UP3 Re-flash
2
A 00 TGL-UP3 A
<Core Design>
www.teknisi-indonesia.com Wistron Corporation

Title
Title
CPU (HAD/I2S/SD/DMIC)
Size
Size Document
DocumentNumber
Number Rev
Rev
A2 Cyborg TGL SC
Date: Sheet 19
Sheet of 105
5 4 3 2 1
5 4 3 2 1
20200304
KB_LED_BL_DET , GPP_C10 -> GPP_D16 20191129 3D3V_S0
layout design
Internal review , follow Nakia RN2005
Follow GPIO table CPU_I2C_SCL_ISH0 3 2
CPU1F CPU_I2C_SDA_ISH0 4 1
TOUCH PAD/E3 6 OF 21
3D3V_VCCDSW
[65,66] CPU_I2C_SCL_P0 SRN2K2J-1-GP 20191125
[65,66] CPU_I2C_SDA_P0 DC53 DR27 Follow Upsell
DA51 GPP_B16/GSPI0_CLK GPP_D14/ISH_UART0_TXD DW27
DC49 GPP_B18/GSPI0_MOSI GPP_D13/ISH_UART0_RXD DV25 KB_LED_BL_DET
G SENSOR SPKR DC50 GPP_B17/GSPI0_MISO
GPP_B14/SPKR/TIME_SYNC1/GSPI0_CS1#
GPP_D16/ISH_UART0_CTS#
GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/IMGCLKOUT5
DT25 IO_DB_DET#_GPPG5 Accelerometer sensor
10KR2J-3-GP 1 2 R2001 LCD_CBL_DET# DC52
[70] FFS_INT1 GPP_B15/GSPI0_CS0# DB45 CPU_I2C_SCL_ISH0 SENSOR_I2C_SCL
R2052 1 2 0R0402-PAD-7-NP-GP ISH
TPM_SPI_IRQ# CY49 GPP_B6/ISH_I2C0_SCL DB44 CPU_I2C_SDA_ISH0 SENSOR_I2C_SDA
PAID_L R2051 1 2 0R0402-PAD-7-NP-GP
1 GC6_THM_DIS#_PCH CY53 GPP_B20/GSPI1_CLK GPP_B5/ISH_I2C0_SDA
[55,70] SENSOR_I2C_SDA TP2010 CY52 GPP_B22/GSPI1_MOSI CY39 20200113 DVT1
[55,70] SENSOR_I2C_SCL DA50 GPP_B21/GSPI1_MISO GPP_B8/ISH_I2C1_SCL DB47 Follow Customer CY20 change from I2C2 to I2C5
GPP_B19/GSPI1_CS0# GPP_B7/ISH_I2C1_SDA
D [70] GSEN2_INT1_C
[55] GSEN_INT1_C
DV21
GPP_C9/UART0_TXD GPP_B10/I2C5_SCL/ISH_I2C2_SCL
DD47 PCH_I2C_SCL_TBT PCH to BB D
FFS_INT1 DT21 DD44 PCH_I2C_SDA_TBT SDA/SCL Pull UP on BB side(page71)

DR21 GPP_C8/UART0_RXD GPP_B9/I2C5_SDA/ISH_I2C2_SDA
GPP_C11/UART0_CTS# 20191125 20191210
DW21 DJ8 Follow CY20 Follow CY20
GPP_C10/UART0_RTS# GPP_E16/ISH_GP7 DR7 LID_CL_SIO_TAB#
AUDIO DV19
GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_E15/ISH_GP6
GPP_D18/ISH_GP5
DR24 ISH_LID_CL#_NB R20541
0R0402-PAD-7-NP-GP
2 LID_CL_SIO#
DT19 DU25 ISH_NB_MODE R2056 1 2 100KR2J-1-GP
[24,27] SPKR DR18 GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_D17/ISH_GP4 DV31
LCD_CBL_DET# DU19 GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_D3/ISH_GP3/BK3/SBK3 DU31 ISH_TABLE_MODE# R2053 1 TABLE_MODE#
2 0R0402-PAD-7-NP-GP
GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_D2/ISH_GP2/BK2/SBK2 DT27 ISH_ACC2_INT# R2037 1 GSEN2_INT1_C
2 0R0402-PAD-7-NP-GP
CPU_UART2_TXD DJ21 GPP_D1/ISH_GP1/BK1/SBK1 DV27 ISH_ACC1_INT# GSEN_INT1_C
FFS
R2039 1 2
KEYBOARD CPU_UART2_RXD DG23 GPP_C21/UART2_TXD
GPP_C20/UART2_RXD
GPP_D0/ISH_GP0/BK0/SBK0 0R0402-PAD-7-NP-GP
G Sensor
TOUCH_PANEL_INTR# DJ19 DR51 GPP_RCOMP R2021 1 2 200R2F-L-GP
[65] KB_LED_BL_DET DF21 GPP_C23/UART2_CTS# GPP_RCOMP
GPP_C22/UART2_RTS# DN33
PCH to Touch Screen PCH_I2C0_SCL_TS DV18
GPP_C17/I2C0_SCL
GPP_T3/I2C7_SCL
GPP_T2/I2C7_SDA
DT35
PCH_I2C0_SDA_TS DW18
OTHER SDA/SCL/INT Pull UP on PD side(page72)
GPP_C16/I2C0_SDA
GPP_U5/GSPI3_CLK
DG17
CPU_I2C_SCL_P0 DJ23 DG19
[24] TABLE_MODE# PCH to Touch Pad/E3 CPU_I2C_SDA_P0 DT18 GPP_C19/I2C1_SCL
GPP_C18/I2C1_SDA
GPP_U4/GSPI3_CS0#
SDA/SCL/INT Pull UP on TP side(page65)
[24] NB_MODE# DJ29
DJ31 GPP_H5/I2C2_SCL
[91] TPM_SPI_IRQ# GPP_H4/I2C2_SDA
DBC_PANEL_EN DF29
LOM_CABLE_DETECT# DG29 GPP_H7/I2C3_SCL
GPP_H6/I2C3_SDA
DF25
DF27 GPP_H9/I2C4_SCL/CNV_MFUART2_TXD
GPP_H8/I2C4_SDA/CNV_MFUART2_RXD
PD TGL-U-1-GP-U2
[71] PCH_I2C_SCL_TBT
[71] PCH_I2C_SDA_TBT
C 3D3V_S5 C
eDP
3D3V_S0 20200420(DVT2) Q2001
[55] DBC_PANEL_EN
2
1 6 NB_MODE#
Note:ZZ.27002.F7C01
Follow ICL reserved 3.3V PH
R2050
ISH_NB_MODE 2 5 MASK_SATA_LED#
LID 1
R2058
2 FFS_INT1
10KR2J-3-GP
BATT_WHITE_LED# 3 4 SATA_LED#_D
DY
1
[24,66] LID_CL_SIO# 10KR2J-3-GP
[24,66] LID_CL_SIO_TAB# 2N7002KDW-1-GP
NB_MODE#
75.27002.F7C
2nd = 075.27002.0E7C
[68] CPU_UART2_TXD 3rd = 075.07002.0A7C
[68] CPU_UART2_RXD
TOUCH
[55] PCH_I2C0_SDA_TS
[55] PCH_I2C0_SCL_TS
[55] TOUCH_PANEL_INTR#
DA51: NRB_BIT
DC49: VGA_DB_DET#
CY49: TPM_PIRQ#
CY53: GC6_THM_DIS#_PCH
CY52: PCH_3.3V_TS_EN
DA50: HDD_FALL_INT
DV21: SBIOS_TX
B DR21: USBC0_AUX_N_BIAS B
DW21: USBC0_AUX_P_BIAS
DV19: DGPU_MACO_EN
[24,64] MASK_SATA_LED#
DT19: SIO_EXT_WAKE#
DR18: PCH_HDD_EN
[64] SATA_LED#_D
DU19: LCD_CBL_DET#
DG23: cTPM_PRSNT#
[24,64] BATT_WHITE_LED#
DJ19: TOUCH_PANEL_INTR#
DF21: TOUCH_I2C_DET#
DV18: I2C0_SCL_TS
DW18: I2C0_SDA_TS
DF29: DBC_PANEL_EN
DG29: LOM_CABLE_DETECT#
DF25: CNV_COEX1
DF27: CNV_COEX2
DR27: STYLUS_PWR_OCP#
DW27: CAM_SHUTTER#
DT25: IO_DB_DET#
CY39: ISH_I2C1_ALS_SCL
DB47: ISH_I2C1_ALS_SDA
WWAN DD47: ISH_I2C2_SCL
DD44: ISH_I2C2_SDA DG17: ZPODD_PWR_EN#
DJ8: ISH_P_SENSOR_INT# DG19: ZPODD_DA#
DV31: ISH_ALS_INT#
[66] IO_DB_DET#_GPPG5
[66] LOM_CABLE_DETECT#
[55] LCD_CBL_DET#
A A
<Core Design>
Wistron Corporation
Title
Title
CPU (UART/I2C/ISH)
Size
Size Document
DocumentNumber
Number Rev
Rev
A2 Cyborg TGL SC
Date: Sheet 20
Sheet of 105
5 4 3 2 1
5 4 3 2 1
Main Func = PCH

CPU1J 10 OF 21
[61] CNV_W R_DN0
[61] CNV_W R_DP0
[61] CNV_W R_DN1 CNV_W T_DP1
D22 DK47
[61] CNV_W R_DP1 B22 CSI_F_DP1 CNVI_WT_D1P DM47 CNV_W T_DN1
[61] CNV_W R_CLKN E22 CSI_F_DN1 CNVI_WT_D1N DN49 CNV_W T_DP0
[61] CNV_W R_CLKP D20 CSI_F_DP0 CNVI_WT_D0P DR49 CNV_W T_DN0
[61] CNV_W T_DN0 A20 CSI_F_DN0 CNVI_WT_D0N DN45 CNV_W T_CLKP
D D
[61] CNV_W T_DP0 B20 CSI_F_CLK_P CNVI_WT_CLKP DN47 CNV_W T_CLKN
[61] CNV_W T_DN1 CSI_F_CLK_N CNVI_WT_CLKN
[61] CNV_W T_DP1 B18 DU43 CNV_W R_DP1
[61] CNV_W T_CLKN A18 CSI_E_DP1/CSI_F_DP2 CNVI_WR_D1P DV43 CNV_W R_DN1
[61] CNV_W T_CLKP D18 CSI_E_DN1/CSI_F_DN2 CNVI_WR_D1N DR44 CNV_W R_DP0
E18 CSI_E_DP0/CSI_F_DP3 CNVI_WR_D0P DT43 CNV_W R_DN0
[61] CNV_BRI_RSP CSI_E_DN0/CSI_F_DN3 CNVI_WR_D0N CNV_W R_CLKP
C16 DV44
[15] CNV_RGI_DT CSI_E_CLK_P CNVI_WR_CLKP CNV_W R_CLKN
D16 DW44
[61] CNV_RGI_DT_R CSI_E_CLK_N CNVI_WR_CLKN
D15 DN51 CNV_W T_RCOMP R2102 1 2 150R2F-1-GP
[61] CNV_BRI_DT_R CSI_C_DP2 CNVI_WT_RCOMP
E15
[61] CNV_RGI_RSP CSI_C_DN2 CNV_RGI_RSP
A15 DJ13
B15 CSI_C_DP3 GPP_F3/CNV_RGI_RSP/UART0_CTS# DG13 CNV_RGI_DT R2110 1 0R0201-PAD-GP
2 CNV_RGI_DT_R
CSI_C_DN3 GPP_F2/CNV_RGI_DT/UART0_TXD DF15 CNV_BRI_RSP
L18 GPP_F1/CNV_BRI_RSP/UART0_RXD DF17 CNV_BRI_DT CNV_BRI_DT_R
R2109 2 1
0R0402-PAD-7-NP-GP
N18 CSI_C_DP1 GPP_F0/CNV_BRI_DT/UART0_RTS#
L20 CSI_C_DN1 DJ10 CLKREQ_CNV
N20 CSI_C_DP0 GPP_F5/MODEM_CLKREQ/CRF_XTAL_CLKREQ DV15
G20 CSI_C_DN0 GPP_F6/CNV_PA_BLANKING DK10 CNV_RF_RESET#
H20 CSI_C_CLK_P GPP_F4/CNV_RF_RESET#
CSI_C_CLK_N
H16
[61] CNV_RF_RESET# CSI_B_DP1
G16
G18 CSI_B_DN1
H18 CSI_B_DP0
L16 CSI_B_DN0
[61] CLKREQ_CNV CSI_B_CLK_P
N16
CSI_B_CLK_N
C G14 C
H14 CSI_B_DP2
L14 CSI_B_DN2
N14 CSI_B_DP3
CSI_B_DN3
R2103 1 2 150R2F-1-GP CSI_RCOMP K14
CSI_RCOMP
DK25
DM25 GPP_H23/IMGCLKOUT4
DN25 GPP_H22/IMGCLKOUT3
DJ25 GPP_H21/IMGCLKOUT2
DR30 GPP_H20/IMGCLKOUT1
GPP_D4/IMGCLKOUT_0/BK4/SBK4
TGL-U-1-GP-U2
B B
A <Core Design> A
Wistron Corporation
Title
Title
CPU (CSI/EMMC/CNVi)
Size
Size DocumentNumber
Document Number Rev
Rev
A3
Cyborg TGL SC
Date: Sheet
Sheet 21 of 105
5 4 3 2 1
5 4 3 2 1
CPU1N 14 OF 21
[50] VCCAUX_SENSE 1D8V_CPU_AUX
(1.3A) Trace width > 40mil
1D8V_S5_VCCPRIM 1D8V_S5
[50] VSSAUX_SENSE 1D05V_S5_VCCDSW _OUT
AB12 CY18 R2203 1 2
[40,50] CORE_VID0 VCCIN_AUX VCCPRIM_1P8
AC10 CY20 0R0805-PAD-NP-GP
AE10 VCCIN_AUX VCCPRIM_1P8 CY24
[40,50] CORE_VID1 VCCIN_AUX VCCPRIM_1P8
AK2 CY26
VCCIN_AUX VCCPRIM_1P8
1
AR10 DA18 C2204
AT12 VCCIN_AUX VCCPRIM_1P8 DA20 SC1U10V2KX-1DLGP
AU10 VCCIN_AUX VCCPRIM_1P8 DA22
2
AW10 DA24 Place cap within
BV1 VCCIN_AUX VCCPRIM_1P8 DA26
D
BV39 VCCIN_AUX VCCPRIM_1P8 DC18
3mm from SOC edge D
BW40 VCCIN_AUX VCCPRIM_1P8 DC20

BY39 VCCIN_AUX VCCPRIM_1P8 DC22 1D24V_S5_VCCDPHY_OUT
CC1 VCCIN_AUX VCCPRIM_1P8 DC24
[3,24,44,46,72] PROCHOT#_CPU VCCIN_AUX VCCPRIM_1P8
CD12 DC26
CF10 VCCIN_AUX VCCPRIM_1P8 DD20 20191112 modify
CG12 VCCIN_AUX VCCPRIM_1P8 DD22 20191126
VCCIN_AUX VCCPRIM_1P8 (200mA) For High Limit
[40] V1P05_CTRL_R CH10 DV22 3D3V_S5_VCCPRIM
1
CJ1
[40] VNN_CTRL_R CJ12 VCCIN_AUX DA35 For CNVi
VCCIN_AUX VCCPRIM_3P3 Place cap within C2205
CK10 DC28 SC4D7U6D3V2MX-1-GP
VCCIN_AUX VCCPRIM_3P3 3mm from SOC edge
2
CL12 DC30
CM10 VCCIN_AUX VCCPRIM_3P3 DD30
CP1 VCCIN_AUX VCCPRIM_3P3 0D85V_S5_VCCLDOSTD_OUT
CP10 VCCIN_AUX DV34
VCCIN_AUX DCPRTC 3D3V_RTC_EXT
CR12
CT10 VCCIN_AUX DV46
VCCIN_AUX VCCLDOSTD_0P85 0D85V_S5_VCCLDOSTD_OUT 20191126
CU12 For High Limit
VCCIN_AUX
1
CY1 DV16 1D8V_S5_CLKLDO (165mA) C2213
AK1 VCCIN_AUX VCCA_CLKLDO_1P8 DC15
PH/PL 100R at VR side. VCCIN_AUX VCCA_CLKLDO_1P8
SC2D2U6D3V2MX-DL-GP
2
VSSAUX_SENSE AV9 DV28
VCCIN_AUX_VSSSENSE VCCDPHY_1P24 1D24V_S5_VCCDPHY_OUT 20200504(DVT2)
VCCAUX_SENSE AT9
VCCIN_AUX_VCCSENSE C2213 change to common
DD38 1D05V_S5_VCCDSW _OUT
20191224 DD17 VCCDSW_1P05
Follow Internal review(200mA) 1D05V_VNN_BYPASS DD18 VCC_VNNEXT_1P05 BR3
VCC_VNNEXT_1P05 VCC1P05 BR4
1D05V_S5_OUT (1.5A) Supply to
3D3V_S5_VCCPRIM DA15 VCC1P05 BT5
VCCST & VCCSTG
(200mA) 1D05V_S5_BYPASS VCC_V1P05EXT_1P05 VCC1P05
C DA17 C
VCC_V1P05EXT_1P05 DA31
VCCPRIM1P05_OUT_PCH 1D05V_S5_VCCPRIM_OUT (Output)
R2215 1 2 10KR2J-3-GP VRALERT# DB39 DC33 3D3V_VCCDSW
VNN_CTRL_R 1 VNN_CTRL GPP_B2/VRALERT# VCCPRIM1P05_OUT_PCH
V1P05_CTRL_R
R2212
R2213 1 DY 22 0R2J-2-GP V1P05_CTRL DV12
DT12 GPP_F22/VNN_CTRL VCCPRIM1P05_OUT_PCH
DC31
20191112 modify
GPP_F23/V1P05_CTRL 3D3V_RTC_AUX 20191211
0R0402-PAD-7-NP-GP DC35 (3mA)Follow Nakia 1D8V_S5
CORE_VID0 DB37 VCCRTC DD37 3D3V_VCCDSW 1
20191112 modify
Follow Nakia CORE_VID1 DB38 GPP_B0/CORE_VID0 VCCGPPR VCCDSW_3P3 DA28
DY 20R2J-2-GP
R2202 3D3V_S5
GPP_B1/CORE_VID1 VCCPGPPR 1D8V_GPPR_S5
3.3V or 1.8V 1 2
CY31 3D3V_S5_VCCPRIM R2207 Must take care
VCCPRIM_3P3 CY33 0R0402-PAD-7-NP-GP
D2201 VCCPRIM_3P3 CV39
this power layout
RB520S30-GP 1D8V_S5_VCCPRIM
PROCHOT#_CPU A K VRALERT#
VCCPRIM_1P8 and add shield GND.
AP12 TP_VCCANA_EHV 1
RSVD#AP12 TP2201
20191210 83.R2003.A8M 1D8V_S5 1D8V_S5_CLKLDO
Follow Nakia N7 2nd = 083.52030.008F TGL-U-1-GP-U2
Intel CRB and Intel review 3rd = 083.52030.0C8F (165mA)
1 2
Follow Nakia using 1.8V GPPR R2204 C2215 C2216
SC22U6D3V3MX-1-DL-GP
0R0402-PAD-7-NP-GP
PH Same as SPI Programming Guide for details
1
1D8V_S5
2
RN2201
(1.3A)
1 4 CORE_VID0 1D8V_S5_VCCPRIM 3D3V_S5_VCCPRIM 3D3V_RTC_AUX 3D3V_RTC_EXT 1D05V_S5_VCCPRIM_OUT
B 2 3 CORE_VID1 B
SRN10KJ-5-GP
1
1
C2210 C2211 C2201 C2206 C2248 C2203
10/09,RN2201 Pin3 ->CORE_VID1,charon DY DY DY C2202 C2207 SCD1U16V2KX-3DLGP DY
20191112 modify
2
2
Follow Nakia
SC1U10V2KX-1DLGP SC1U10V2KX-1DLGP SC1U10V2KX-1DLGP SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP
(200mA) 20191112 modify

(200mA) Follow Nakia using 1.8V GPPR
1D05V_S5_BYPASS 1D05V_VNN_BYPASS
1D05V_S5_OUT 3D3V_VCCDSW 1D8V_GPPR_S5
DY
1
C2246 C2247 C2208 C2209 1 C2214

DY DY DY SC1U10V2KX-1DLGP SCD1U16V2KX-L-GP
2
SC1U10V2KX-1DLGP SC1U10V2KX-1DLGP SC1U10V2KX-1DLGP
Close to pin DD37
A A
<Core Design>
20191112 modify
(SR#1406479253) Follow Nakia
Wistron Corporation
Title
Title
CPU (PCH-LP PWR&Caps)
Size
Size DocumentNumber
Document Number Rev
Rev
A3 Cyborg TGL SC
Date: Sheet
Sheet 22 of 105
5 4 3 2 1
5 4 3 2 1
CPU1P 16 OF 21 17 OF 21
CPU1Q
18 OF 21 CPU1R
A27 B19 BY44 CY44

VSS VSS BY45 VSS VSS CY45
A32 B2 K34 DP53 VSS VSS
A45 VSS VSS B23 K48 VSS VSS DR11 BY47 CY47
VSS VSS VSS VSS BY49 VSS VSS CY5
A49 B27 K5 DR16 VSS VSS
AA41 VSS VSS B32 L22 VSS VSS DR22 BY9 D27
VSS VSS VSS VSS C13 VSS VSS D32
D AA48 B36 L28 DR28 VSS VSS D
AB5 VSS VSS B39 L34 VSS VSS DR34 C19 D36
VSS VSS VSS VSS C23 VSS VSS D42
AB7 B42 L39 DR40 VSS VSS
AB8 VSS VSS B48 L41 VSS VSS DR46 CA48 D49
VSS VSS VSS VSS CB41 VSS VSS D5
AC44 B52 L42 DT4 VSS VSS
AC49 VSS VSS B8 L44 VSS VSS DT50 CC10 DA30
VSS VSS VSS VSS CC3 VSS VSS DA33
AD4 BA48 L45 DU11 VSS VSS
AD48 VSS VSS BA53 L47 VSS VSS DU16 CC5 DA53
VSS VSS VSS VSS CD44 VSS VSS DC17
AD8 BB4 L49 DU22 VSS VSS
AF4 VSS VSS BB8 M1 VSS VSS DU28 CD48 DD15
VSS VSS VSS VSS CD7 VSS VSS DD24
AF8 BC1 M2 DU34 VSS VSS
AG41 VSS VSS BC2 M50 VSS VSS DU40 CE49 DD26
VSS VSS VSS VSS CG48 VSS VSS DD28
AG42 BD12 N22 DU46 VSS VSS
AG44 VSS VSS BD4 N28 VSS VSS DV1 CG51 DD31
VSS VSS VSS VSS CG52 VSS VSS DD33
AG45 BD48 N34 DV40 VSS VSS
AG47 VSS VSS BD8 N39 VSS VSS DV52 CG9 DD35
VSS VSS VSS VSS CH41 VSS VSS DD39
AG48 BF39 N41 DW51 VSS VSS
AG53 VSS VSS BF4 N48 VSS VSS E13 CH42 DD45
VSS VSS VSS VSS CH44 VSS VSS DD51
AH4 BF41 P11 E19 VSS VSS
AH8 VSS VSS BF42 P14 VSS VSS E35 CH45 DD52
VSS VSS VSS VSS CH47 VSS VSS DE3
C AK12 BF44 P16 E48 VSS VSS C
AK4 VSS VSS BF45 P18 VSS VSS G22 CJ3 DE5
VSS VSS VSS VSS CJ5 VSS VSS DF19
AK48 BF47 P20 G28 VSS VSS
AK5 VSS VSS BF5 P22 VSS VSS G34 CJ9 DF37
VSS VSS VSS VSS CK39 VSS VSS DG15
AK7 BF7 P33 G39 VSS VSS
AK8 VSS VSS BF8 P35 VSS VSS G48 CK48 DG21
VSS VSS VSS VSS CK53 VSS VSS DG27
AM1 BG48 P4 G51 VSS VSS
AM2 VSS VSS BG53 P49 VSS VSS G52 CL9 DG33
VSS VSS VSS VSS CN12 VSS VSS DG39
AM4 BH1 P8 H12 VSS VSS
AM8 VSS VSS BH2 R39 VSS VSS H22 CN48 DG45
AN41 BH4 R44 H28 VSS VSS
AN42 VSS VSS BH8 T19 VSS VSS H34 CN52 DG53
AN44 BK12 T29 H8 VSS VSS
AN45 VSS VSS BK4 T33 VSS VSS J39 CP3 DJ1
VSS VSS VSS VSS CP41 VSS VSS DJ2
AN47 BK48 T4 J49 VSS VSS
AN48 VSS VSS BK8 T48 VSS VSS K16 CP42 DJ4
VSS VSS VSS VSS CP44 VSS VSS DK51
AN53 BL49 T8 K18 VSS VSS
AP4 VSS VSS BM1 U19 VSS VSS K20 CP45 DL3
VSS VSS VSS VSS CP5 VSS VSS DL5
AP8 BM4 U25 K22 VSS VSS
AT4 VSS VSS BM41 U39 VSS VSS K28 CR48 DM10
VSS VSS VSS VSS CR53 VSS VSS DM15
B AT48 BM42 U49 VSS VSS B
AT51 VSS VSS BM44 V19 VSS CR9 DM21
VSS VSS VSS CT5 VSS VSS DM27
AT8 BM45 V4 VSS VSS
AV12 VSS VSS BM47 V8 VSS CU4 DM33
VSS VSS VSS CU9 VSS VSS DM39
AV39 BM8 W1 VSS VSS
AV4 VSS VSS BN48 W16 VSS CV10 DM4
VSS VSS VSS CV48 VSS VSS DM45
AV5 BP41 W26 VSS VSS
AV7 VSS VSS BP49 W30 VSS CV5 DN1
VSS VSS VSS CV51 VSS VSS DN2
AV8 BP5 W39 VSS VSS
AW1 VSS VSS BP50 W41 VSS CV52
VSS VSS VSS CY17 VSS
AW2 BP7 W42 VSS
AW48 VSS VSS BT44 W44 VSS CY22
AY4 BT48 W45 VSS
AY41 VSS VSS BU49 W47 VSS CY41
AY42 BV3 W48 VSS
AY44 VSS VSS BV48 Y4 VSS
AY45 VSS VSS BV5 Y49 VSS
VSS VSS VSS TGL-U-1-GP-U2
<Core Design>
AY47 BW10 Y50
AY8 VSS VSS BY41 Y8 VSS
VSS VSS VSS
A
AY9
B13 VSS VSS
BY42
VSS 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
TGL-U-1-GP-U2 Taipei Hsien 221, Taiwan, R.O.C.
TGL-U-1-GP-U2
Title
CPU (VSS)
A4 Cyborg TGL SC
5 4 3 2 1
5 4 3 2 1
Main Func = KBC

20200331
Follow Vendor requirement change to 1.05V_VCCST
VTR Signal 3D3V_ECVBAT
3D3V_S5
3D3V_S0
PWR_LED
Board ID and Model ID
1
1D05V_VCCST
[66] PCIE_LAN_WAKE#
R2448 3D3V_S5_KBC 3D3V_S5
1
3D3V_S5_KBC 3D3V_S5_KBC 3D3V_S5_KBC 3D3V_S5_KBC 3D3V_S5_KBC 10KR2J-3-GP
1
[65] KSO00 HAVE TBT R2455
2
[65] KSO01 PECI_VREF DY 10KR2J-3-GP R2435
2
2 1 R2496 TBT_DET_EC# 3D3V_S5
[65] KSO02 100KR2J-1-GP
1
[66] PM_LAN_ENABLE R2428 100KR2J-1-GP
[65] KSO03
2
1
0R0402-PAD-7-NP-GP R2443 R2442
[65] KSO04
1 R2427 1 R2425 1 R2424 1 R2423 1 R2422
2
VREF_ADC VTR_REG VTR_PLL VTR1_ADC SSD_SCP# CABLE2_OCP#
1
2 2 2 2 2 2 R2419 1 17K8R2F-GP 64K9R2F-1-GP
C2406
SCD1U16V2KX-3DLGP
VTR2 R2401
[65] KSO05
1
0R0402-PAD-1-GP
[65] KSO06 [55] CABLE2_OCP# 0R0402-PAD-1-GP 0R0402-PAD-1-GP 0R0402-PAD-1-GP 0R0402-PAD-1-GP
LID_POWER_ON#
10KR2J-3-GP BOARD ID MODEL ID
NO TBT 100KR2J-1-GP
1
SCD1U16V2KX-3DLGP
C2432
SCD1U16V2KX-3DLGP
C2427
SCD1U16V2KX-3DLGP
C2425
SCD1U16V2KX-3DLGP
C2422
SCD1U16V2KX-3DLGP
C2424
[65] KSO07
2
[65] KSO08
2
MODEL_ID
[65] KSO09 [18] EC_I2C_SCL_THM BOARD_ID
2
[65] KSO10 [18] EC_I2C_SDA_THM
1
[65] KSO11
1
SCD1U16V2KX-3DLGP
C2407
R2441
[65] KSO12 [26,79] EC_SMB_SCL_THM 3D3V_S5_KBC
SCD1U16V2KX-3DLGP
R2444 100KR2F-L1-GP
[65] KSO13 [26,79] EC_SMB_SDA_THM 3D3V_S5 3D3V_S5_VCCPRIM
1
C2408
100KR2F-L1-GP
[65] KSO14
2
[65] KSO15 [62] EC_I2C_SCL_ITE8010
2
1
[65] KSO16 [62] EC_I2C_SDA_ITE8010 20191125 20191210
2
1
1
R2458 R2457
Follow CY20 Follow CY20 3D3V_S5
DY 10KR2J-3-GP R2436
Follow NAKIA
[18,71] CPU_SML_SCL0 100KR2J-1-GP
For USB Charge Level shift

[18,71] CPU_SML_SDA0 R2494
2
100KR2J-1-GP LID_CL_SIO# 1 2
2
100KR2J-1-GP
FPR_SCAN# LED_MASK# SIO_PWRBTN#
[65] KSI[0..7] [20,27] SPKR
KSI0
KSI1 3D3V_S5
KSI2 1D8V_S5 64.17825.6DL
KSI3
KSI4
3D3V_S5 3D3V_S5 For USB TypeC DY
KSI5 R2491 2 1 10KR2J-3-GP TYPEC_DCIN1_EN#
D D
KSI6 1D8V_S5 3D3V_S5_KBC
[40,54] PWR_VNN1D05V_PG 3D3V_S5_KBC 3D3V_S5
KSI7
2
R2487 R2469
[17,40,50] VCCIN_AUX_PWRGD
2
1
10KR2J-3-GP 10KR2J-3-GP R2470 R2486
1
10KR2J-3-GP 10KR2J-3-GP R2434 RN2413
[18,68] ESPI_IO0
Q2417 R2460 100KR2J-1-GP SRN2K2J-1-GP
[18,68] ESPI_IO1
1
[18,68] ESPI_IO2 USB_POWERSHARE_VBUS_EN USB_POWERSHARE_VBUS_EN_D OPS 10KR2J-3-GP
1
1 S1 D1 6
[18,68] ESPI_IO3
2
2
3
4
2 5 USB_PWR_EN# 2 DY 1 USB_POWERSHARE_VBUS_EN_D
1D8V_S5 G1 PS G2 1D8V_S5 GPU_PWR_LEVEL
R2445 10KR1J-GP
USB_PWR_SHR_EN_L#_D 3 D2 4 USB_PWR_SHR_EN_L# EC_I2C_SDA_PD

S2
EC_I2C_SCL_PD
PJT138KA-GP
[25] VCCDSW_EN
075.00138.0A7C
[65] EC_I2C_SCL_TP 2nd = 075.00139.007C
3rd = 075.00138.0F7C
[65] EC_I2C_SDA_TP
[17] SIO_PWRBTN#
64.10025.6DL
[18,68] ESPI_CS#
[18,68] ESPI_CLK
[18,68] ESPI_RESET#
www.teknisi-indonesia.com D2410
DY
20191126
Follow ICL
64.17825.6DL
64.27025.6DL
A K JIO3_PCIE_WAKE#
64.37425.6DL
3D3V_S5
[17] SYS_PWROK
RB520S30-GP
[43,44] PBAT_PRES# 83.R2003.A8M
1
2ND = 083.52030.008F 64.64925.6DL
[25] RTCRST_ON
R2495 3rd = 083.52030.0C8F
3D3V_S5_KBC 1KR2J-1-GP
3D3V_S5
[17] PCH_RSMRST# 64.82525.6DL
D2401 D2409
2
PANEL_BKEN K A PANEL_BKEN_EC PCIE_WAKE# PCIE_LAN_WAKE#
eDP backlight 2 1 A K 64.10735.6DL
[3,65] TOUCHPAD_INTR# Control from EC R2446
RB520S30-GP RB520S30-GP
0R0402-PAD-7-NP-GP
83.R2003.A8M 83.R2003.A8M 64.15435.6DL
2ND = 083.52030.008F 2ND = 083.52030.008F
[20,66] LID_CL_SIO# 3rd = 083.52030.0C8F 3rd = 083.52030.0C8F
LAN
1
SCD1U16V2KX-3DLGP
C2421
SCD1U16V2KX-3DLGP
C2416
[17,40,44,46] ALL_SYS_PWRGD D2408
D2405
eDP backlight LAN_WAKE#
1
A K
SCD1U16V2KX-3DLGP
C2420
SCD1U16V2KX-3DLGP
C2412
SCD1U16V2KX-3DLGP
C2411
SCD1U16V2KX-3DLGP
C2410
SCD1U16V2KX-3DLGP
C2414
SCD1U16V2KX-3DLGP
C2413
[65] CAP_LED#_R K A L_BKLT_EN
2
Control from PCH 20191125
[64] CHG_AMBER_LED# RB520S30-GP
Follow CY20
2
RB520S30-GP 83.R2003.A8M
83.R2003.A8M D2402 2ND = 083.52030.008F
2ND = 083.52030.008F LID_CL_SIO# K A TOUCH_REPORT_SW 3rd = 083.52030.0C8F
[20,64] BATT_WHITE_LED# 3rd = 083.52030.0C8F LAN
LRB751V-40T1G-GP
83.00751.08F
[26] FAN_TACH1
2nd = 83.R2004.G8F
[43,44] PBAT_CHG_SMBDAT
If don't need RTC alarm wake up,
[17,26] IMVP_VR_ON can change to 3D3V_AUX_S5 For eSPI
U2401
3D3V_RTC
[20] NB_MODE# SSD_SCP#
1D8V_S5 1D8V_S5_KBC A8 B64
B5 VTR1 GPIO101/BGPO1 B43 MS_SMB_SCL
[65] KB_LED_PWM
B48 VTR1 GPIO104/UART0_TX/TFDP_CLK/VTR2_STRAP A41 MS_SMB_SDA
LED
2
B39 VTR1 GPIO105/UART0_RX/TFDP_DATA/TRACECLK B3 RESET_OUT# 2 R2473 1 SYS_PWROK

C R2472 A52 VTR1 GPIO106/PWROK B36 KSO04 0R0402-PAD-7-NP-GP C
[27] BEEP VTR1 GPIO107/SMI#/KSO04/I2C10_SCL
0R0402-PAD-7-NP-GP
VTR1_ADC A15 B37 KSO05
R2462 1 2 0R0402-PAD-7-NP-GP VTR1_ADC GPIO112/KSO05 A35 KSO06 G3
1
VTR2 B26 GPIO113/KSO06/ICT9 B38 PCH_RSMRST#_R 2 R2404 1 PCH_RSMRST#

[43] PS_ID C2423 2 VTR2 GPIO114/PS2_CLK0A/EC_SCI#
1 SCD1U16V2KX-3DLGP B19 A36 LID_CL_SIO# 0R0402-PAD-7-NP-GP
VTR3 GPIO115/PS2_DAT0A B41 PS_ID 2 1 0R2J-2-GP 3D3V_S5
VTR_PLL B4 GPIO116 A39 TABLE_MODE# 20191210 R2453 DY
Follow CY20 R2418
3D3V_ECVBAT A64 VTR_PLL GPIO117 2 1 DUAL_BOOT_EVENT# RN2405
[43,44] PBAT_CHG_SMBCLK VTR_REG B9 VBAT A34 2 3
KSO07 0R2J-2-GP
1
SCD1U16V2KX-3DLGP
C2428
Layout Note: 1 SC1U10V2KX-1DLGP VREF_ADC VTR_REG GPIO120/KSO07

C2418 2
VR_CAP
B11
VREF_ADC GPIO121/PVT_IO0/KSO08
B45 KSO08 Dual Boot 1 4
Place close to Mec1515 B8 A43 KSO09
R2420 1 2 100KR2J-1-GP VR_CAP GPIO122/PVT_IO1/KSO09 B46
DY KSO10 Q2416 SRN100KJ-6-GP
2
[68] HOST_DEBUG_TX 3D3V_RTC GPIO123/PVT_IO2/KSO10 B10 KSO11

R2454 2 1 100KR2J-1-GP SYSPWR_PRES B68 GPIO124/PVT_CS#/KSO11/ICT12 B47 KSO12 BAT2_LED# 1 6 BATT_WHITE_LED#
[65] PTP_DIS# SHD_CS1# GPIO000/SYSPWR_PRES/VCI_IN3#/I2C11_SDA GPIO125/PVT_CLK/KSO12
B28 A44 KSO13
EC_I2C_SDA_THM A59 GPIO002/PWM5/SHD_CS1# GPIO126/PVT_IO3/KSO13 A46 RTCRST_ON 2 5
[3] PECI_CPU EC_I2C_SCL_THM GPIO003/I2C00_SDA/UART2_RI# GPIO127/A20M/UART1_RTS# 3D3V_S5 3D3V_S5
B62
PM_LAN_ENABLE 2 R2483 1 AUX_ON A47 GPIO004/I2C00_SCL/UART2_DCD# A25 PBAT_CHG_SMBDAT 3D3V_S5_KBC CHG_AMBER_LED# 3 4 BAT1_LED#
[27] NB_MUTE# GPIO007/I2C03_SDA/PS2_CLK0B GPIO130/I2C01_SDA PBAT_CHG_SMBCLK
0R0402-PAD-7-NP-GP B27
FPR_SCAN# B50 GPIO131/I2C01_SCL A49 RN2402
[20,66] LID_CL_SIO_TAB# KSO16 2N7002KDW-1-GP
MASK_SATA_LED# B21 GPIO010/I2C03_SCL/PS2_DAT0B GPIO132/I2C06_SDA/KSO16 PBAT_CHG_SMBCLK 3 2
VCCDSW_EN B25 GPIO011/SMI_ALT#/PWM4/ICT7 B53 CAP_LED# PBAT_CHG_SMBDAT 4 1
75.27002.F7C
[44,64] HW_ACAV_IN DGPU_PWROK_EC A24 GPIO012/I2C07_SDA GPIO140/I2C06_SCL/ICT5/KSO17 B60 PTP_DIS# 2nd = 075.27002.0E7C
PWM_FAN1 A27 GPIO013/I2C07_SCL GPIO141/I2C05_SDA/UART2_RTS# A57 TOP_SWAP 2 R2467 1 SPKR SRN4K7J-8-GP
3rd = 075.07002.0A7C
[66] FPR_SCAN# DGPU_PWROK_EC DGPU_PWROK SHD_IO3 GPIO014/PWM6/GPTP_IN2 GPIO142/I2C05_SCL/UART2_CTS# EC_I2C_SDA_PD
2 1 A21 B61 0R0402-PAD-7-NP-GP R2452 2 DY 1 0R2J-2-GP
R2471 KSI0 B32 GPIO016/GPTP_IN1/SHD_IO3/ICT3/DSW_PWROK GPIO143/I2C04_SDA/UART0_CTS# A58 EC_I2C_SCL_PD
[26] PWM_FAN1 GPIO017/KSI0/UART0_DCD# GPIO144/I2C04_SCL/UART0_RTS# JTAG_TDI
0R0402-PAD-7-NP-GP B58
A29 GPIO145/I2C09_SDA/JTAG_TDI/UART2_RX A55 JTAG_TDO
OPS KSI1
GPIO020/KSI1 GPIO146/I2C09_SCL/JTAG_TDO/UART2_TX JTAG_CLK
2
KSI2 B31 B59

R2426 KSI3 B34 GPIO021/KSI2 GPIO147/I2C15_SDA/JTAG_CLK/UART2_DSR#
KSI4 B35 GPIO026/KSI3/UART0_DTR#/I2C12_SDA A56 JTAG_TMS 3D3V_S5_KBC
10KR2J-3-GP
GPIO027/KSI4/UART0_DSR#/I2C12_SCL GPIO150/I2C15_SCL/JTAG_TMS/UART2_DTR# A30 KSO15
[55] LCD_TST GPIO151/ICT4/KSO15 PBAT_PRES#
KSI6 A32 A9 KSO14 R2415 1 2 100KR2J-1-GP
GPIO031/KSI6/GPTP_OUT1 GPIO152/KSO14
1
KSI5 A33 B54 BAT2_LED#

KSI7 B33 GPIO030/KSI5/I2C10_SDA GPIO153/LED2 A48 EC_I2C_SDA_TP
IMVP_VR_ON B1 GPIO032/KSI7/GPTP_OUT0/UART0_RI# GPIO154/I2C02_SDA/PS2_CLK1B B51 EC_I2C_SCL_TP
3D3V_S0 Need very close to EC, BEEP A6 GPIO033/TACH3 GPIO155/I2C02_SCL/PS2_DAT1B B49 PWR_LED R2421
GPIO035/PWM8/CTOUT1/ICT15 GPIO156/LED0 A50 BAT1_LED#
PDG: <0.5 inches. 330R2J-3-GP
Key Matrix
[55] LCD_VCC_TEST_EN GPIO157/LED1
KSO00 A31
PECI_CPU 1 2 PECI_EC A37 GPIO040/GPTP_OUT2/KSO00/UART1_CTS# A54 PCIE_WAKE# I_ADP 2 1 PWR_AD_IA
PANEL_BKEN_EC GPIO042/PECI_DAT/SB-TSI_DAT GPIO165/32KHZ_IN/CTOUT0
2
R2437 B40 20200818

[17] EC_RESET# PECI_VREF GPIO043/SB-TSI_CLK HOST_DEBUG_TX 3D3V_S5_KBC
R2430 43R2J-GP A38 B42 for SUS_SLP#
GPIO044/VREF_VTT GPIO170/UART1_TX/JTAG_STRAP CCG6_I2C_INT# 3D3V_S5_KBC
1
KSO01 B57 B56 R2490
10KR2J-3-GP GPIO045/KSO01/PWM2_ALT/ICT14/CR_STRAP GPIO171/UART1_RX PBAT_PRES# SIO_SLP_SUS#
1
DY C2405 KSO02 B44 A45 1 2 R2481 1 2 C2435
SC100P50V2JN-3GP KSO03 A42 GPIO046/KSO02/ICT11 GPIO175/CMP_VOUT1/PWM8_ALT 0R2J-2-GP 100KR2J-1-GP DY SC2200P50V2KX-2DLGP
GPIO047/KSO03/PWM3_ALT/ICT13
1
2
D2403 R2480 RN2412 RN2403
[43,44] HW_ACAVIN_NB
2
FAN_TACH1 K A TACH_FAN1 B55 A11 PWRGD_R 1 2 VCCIN_AUX_PWRGD 1 8 KSO08 1 8 KSI0
LID_CL_SIO_TAB# R2440 1 2 LID_CL_SIO_TAB#_R A51 GPIO050/ICT0_TACH0 GPIO200/ADC00/TRACEDAT0 B12 I_ADP 0R2J-2-GP 2 7 KSO02 2 7 KSI1
[40] ALWON GPIO051/ICT1_TACH1 GPIO201/ADC01/TRACEDAT1
RB520S30-GP 0R0402-PAD-7-NP-GP LCD_TST A26 A12 MODEL_ID 3 6 KSO10 3 6 KSI2
KB_LED_PWM B29 GPIO052/ICT2_TACH2 GPIO202/ADC02/TRACEDAT2 B13 TOUCHPAD_INTR# 4 5 4 5
[44] PWR_AD_IA 83.R2003.A8M NB_MODE#
0R0402-PAD-7-NP-GP
R2466 1 2 NB_MODE#_R A28 GPIO053/PWM0 GPIO203/ADC03/TRACEDAT3 A13 BOARD_ID DY KSO03 KSI3
2ND = 083.52030.008F SHD_CS0# B24 GPIO054/PWM1 GPIO204/ADC04 B14 TBT_DET_EC#
3rd = 083.52030.0C8F SHD_CLK A23 GPIO055/PWM2/SHD_CS0#/BSS_STRAP GPIO205/ADC05 A14 USB_PWR_EN# SRN100KJ-5-GP SRN10KJ-6-GP
ALL_SYS_PWRGD R2464 1 2 RUNPWROK A2 GPIO056/PWM3/SHD_CLK GPIO206/ADC06 B15 PCH_DPWROK RN2409 RN2404
0R0402-PAD-7-NP-GP GPIO057/VCC_PWRGD GPIO207/ADC07/CMP_STRAP 1 8 KSO15 1 8 KSI4
HW_ACAVIN_NB R2475 1 2 HW_ACAVIN_NB_R B52 A1 NB_MUTE# 2 7 KSO00 2 7 KSI5
[55] PANEL_BKEN ESPI_RESET# GPIO060/KBRST/TST_CLK_OUT GPIO221/32KHZ_OUT/SYS_SHDN#
0R0402-PAD-7-NP-GP B16 B30 PROCHOT 3 6 KSO07 3 6 KSI6
0R0402-PAD-7-NP-GP EC_RESET# B63 GPIO061/ESPI_RESET#/PWM7_ALT/EC_SCI_ALT# GPIO222/PROCHOT_IN# A22 SHD_IO0 4 5 KSO06 4 5 KSI7
[44,79] GPU_PWR_LEVEL USB_PWR_SHR_EN_L# GPIO062(RESETO#)/I2C11_SCL GPIO223/SHD_IO0 SHD_IO1
R2465 1 2 GPIO063 A20 B22
USB_POWERSHARE_VBUS_EN R2439 1 2 GPIO064 A16 GPIO063/ESPI_ALERT#/PWM6_ALT/ICT8 GPIO224/GPTP_IN0/SHD_IO1 A3 LCD_VCC_TEST_EN PROCHOT
[19,85] DGPU_PWROK ESPI_CLK GPIO064/PCI_RESET# GPIO226 SHD_IO2
0R0402-PAD-7-NP-GP B18 B23 SRN100KJ-5-GP SRN10KJ-6-GP
ESPI_CS# B17 GPIO065/ESPI_CLK/I2C13_SCL/ICT5_ALT GPIO227/SHD_IO2/PWRGD_STRAP
[3,22,44,46,72] PROCHOT#_CPU RN2410
TYPEC_DCIN1_EN# GPIO066/ESPI_CS#/I2C13_SDA GPU_PWR_LEVEL 3D3V_S5_KBC
1
A10 A53 1 8 KSO09
GPIO067/VREF2_ADC GPIO241/PWM0_ALT/CMP_VOUT0 B6 PANEL_MONITOR R2417 2 7 KSO12
[4] L_BKLT_EN ESPI_IO0 GPIO242/CMP_VIN0 AC_DIS
A17 A7 DY 100KR2J-1-GP 3 6 KSO13
ESPI_IO1 A18 GPIO070/ESPI_IO0/I2C14_SDA GPIO244/CMP_VIN1 A5 M_BIST 4 5 KSO16
[55] TOUCH_REPORT_SW ESPI_IO2 GPIO071/ESPI_IO1/I2C14_SCL GPIO246/CMP_VREF0
2
B20
GPIO072/ESPI_IO2/I2C01_SDA_ALT
2
3D3V_S5 ESPI_IO3 A19 A60 CABLE2_OCP# R2450
[64] KBC_PWRBTN# GPIO073/ESPI_IO3/I2C01_SCL_ALT GPIO253/BGPO0 SIO_PWRBTN#
B7 SRN100KJ-5-GP 100KR2J-1-GP
GPIO254/PWM1_ALT/CMP_VREF1 A4 ME_FWP
POWER_SW_IN# B67 GPIO255 RN2411
2
VCI_IN0#/GPIO163
1
LID_POWER_ON# A63 1 4
B
[72] EC_I2C_SCL_PD R2498 EC_OSC VCI_IN1#/GPIO162 B66 2 3
KSO11
KSO14 KSO01 GPIO045 (CR_STRAP) B
JTAG
100KR2J-1-GP
[72] EC_I2C_SDA_PD HW_ACAV_IN A61 NC#B66

OSC_SUS_CLK R2479 VCI_OVRD_IN/GPIO172
[18,25,91] SPI_CLK_ROM
1 2 ALWON B65 SRN100KJ-6-GP
0R2J-2-GP VCI_OUT/GPIO250 C1
1
[18,25,91] SPI_SO_ROM GND RN2407

[15,18,25,91] SPI_SI_ROM JTAG_RST# SUS_CLK_PCH
[15,18,25] SPI_WP_ROM SUSCLK 1 2 A62 1 4 KSO05
R2406 nRESET_IN B2 SUSCLK_IN Q2408 2 3 KSO04
[15,18,25] SPI_HOLD_ROM JTAG_RST# A40 RESET_IN#
2
[18,25] SPI_CS_ROM_N0 R2409 C2419 0R2J-2-GP

JTAG_RST# CAP_LED# CAP_LED#_R
2
1 6 SRN100KJ-6-GP
NON_EC_OSC
100R2F-L1-GP-U
SC1U10V2KX-1DLGP
NON_JTAG JTAG MEC1515H-D0-I-NB-GP

3D3V_S0
2 5 PROCHOT
1
071.01515.0A03 PROCHOT#_CPU
1
3 4
[18,61] SUSCLK
3D3V_AUX_S5
2N7002KDW-1-GP
75.27002.F7C
2nd = 075.27002.0E7C
3rd = 075.07002.0A7C
SMBUS Option
[36] USB_PWR_SHR_EN_L#_D pull high on CPU side
3D3V_S0
[36] USB_POWERSHARE_VBUS_EN_D U2403
EC_I2C_SDA_THM R2447 1 2 EC_SMB_SDA_THM
1 4
2
TRI_STATE VDD C2451 0R0402-PAD-7-NP-GP
1
EC_I2C_SCL_THM R2459 1 2 EC_SMB_SCL_THM

SCD01U25V2KX-3DLGP
R2489
2
GND OUTPUT
3 OSC_SUS_CLK
EC_OSC 100KR2J-1-GP 0R0402-PAD-7-NP-GP
[66] PWR_LED
2
OSC-32D768KHZ-17-GP
1
CAP_LED# R2433 2 1 0R0402-PAD EC_I2C_SDA_ITE8010
82.20035.151
1
C2450
SC15P50V2JN-DL-GP
R2499 2 1 0R0402-PAD EC_I2C_SCL_ITE8010

EC_OSC EC_OSC
2
[16,62] DUAL_BOOT_EVENT#
R2429 1 2 0R2J-2-GP CPU_SML_SDA0
20200401
Not used , change to DY
DY
R2431 1 2 0R2J-2-GP CPU_SML_SCL0
[64] LED_MASK# DY
[66] LID_POWER_ON#
[72] CCG6_I2C_INT#
[20,64] MASK_SATA_LED#
Power Switch Logic(PSL) G3 Sharing JTAG DEBUG CONN
[98] ME_FWP
EC G3 Flash Share
SPI_HOLD_ROM R2412 1 SHD_IO3
SPI_WP_ROM R2413 1
G3 2 100R2J-2-GP SHD_IO2
SPI_SO_ROM R2410 1
G3 22 100R2J-2-GP SHD_IO1 3D3V_S5
SPI_SI_ROM G3 2 100R2J-2-GP SHD_IO0
R2411 1 G3 2 100R2J-2-GP
SPI_CLK_ROM R2416 1 SHD_CLK
[43,44] AC_DIS SPI_CS_ROM_N0 R2403 2
G3 1
100R2J-2-GP
0R0402-PAD-7-NP-GP SHD_CS0#
SPI_CS_ROM_N1 R2497 2 1 0R2J-2-GP SHD_CS1#
[35,66] USB_PWR_EN#
BIOS ROM_16 R2485 R2476 R2477 R2478
1
R2468
1
49D9R2F-GP
R2456 R2449
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
R2463
1
10KR2J-3-GP
100KR2J-1-GP
10KR2J-3-GP
10KR2J-3-GP
[17] PCH_DPWROK
JTAG JTAG JTAG JTAG DY
JTAG
2
2
2
[53] PRIM_PWRGD JTAG1
2
11
1 JTAG_PU
[74] TYPEC_DCIN1_EN#
For eSPI 2 JTAG_TDI
3 JTAG_TMS
3D3V_ECVBAT
Power on sequence for G3 sharing 4 JTAG_CLK
GPIO55 (BSS_STRAP) JTAG_TDO
20191217
JTAG 5
MS_SMB_SCL
A 6 A
20191125 Follow HC ICL 7 MS_SMB_SDA
2
Follow Upsell 8 HOST_DEBUG_TX

[63] SSD_SCP# R2451 TP2401 1 PCH_RSMRST# Already pull low 20191126 9 EC_DEBUG_TX
100KR2J-1-GP on CPU side D|ㄆ e to High Limit 10 R24141 2 0R2J-2-GP
[20] TABLE_MODE# TPAD14-OP-GP Change back to D2406 D2407
R2432 PRIM_PWRGD 12
1 2 JTAG
non-G3
1
KBC_PWRBTN# 1 2 POWER_SW_IN# R2407

PCH_RSMRST# SHD_CS0#
R2405 2 1 0R2J-2-GP 3D3V_S5_KBC
0R0402-PAD-7-NP-GP
D2406_A
ACES-CON10-28-GP-U
1KR2J-1-GP non-G3
1
C2426
SC2D2U6D3V2MX-DL-GP
PRIM_PWRGD R2402 2 1 0R2J-2-GP SHD_IO2
D2406 R2408
20.K0460.010
1
K A 1 2 PWR_VNN1D05V_PG HOST_DEBUG_TX 1 R2484 2
[64] M_BIST R2461 G3 DY
2
6K2R2F-GP
DY 10KR2J-3-GP RB520S30-GP 0R2J-2-GP
[55] PANEL_MONITOR 83.R2003.A8M
2nd = 083.52030.008F
2
nRESET_IN 3rd = 083.52030.0C8F
[61] JIO3_PCIE_WAKE#
1
[17] LAN_WAKE#
R2438
100KR2J-1-GP G3 D2407
EC_RESET# <Core Design>
K A
G3
1
RB520S30-GP
Wistron Corporation
2
83.R2003.A8M R2474
2nd = 083.52030.008F DY 100KR2J-1-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
3rd = 083.52030.0C8F Taipei Hsien 221, Taiwan, R.O.C.
2
Title
KBC Nuvoton NPCE285PA0DX
Custom
Cyborg TGL SC
5 4 3 2 1
5 4 3 2 1
3D3V_SPI
Main Func = SPI Flash Socket for 32M (WSON) 20191224
1
R2501 20200225
4K7R2J-2-GP change to 8M 3D3V_SPI
BIOS ROM_8 U2501
20200923
2
SPI_CS_ROM_N0 1 8
BIOS1 ROM_82
SPI_SO_ROM R2507 SPI_SO_ROM_R 2 CS# VCC 7 SPI_HOLD_ROM_R BIOS ROM_8
SPI_HOLD_ROM
[18,24] SPI_CS_ROM_N1 15R2F-2-GP R2570 1 2 15R2F-2-GP
SPI_WP_ROM R2571 2 1 15R2F-2-GP SPI_WP_ROM_R 3 DO/IO1 IO3 6 SPI_CLK_ROM_R R2568 1 2 15R2F-2-GP SPI_CLK_ROM
Remove 4 IO2 CLK 5 SPI_SI_ROM_R R2569 1 2 15R2F-2-GP SPI_SI_ROM

[18,24] SPI_CS_ROM_N0 BIOS ROM_8 GND DI/IO0
9
BIOS ROM_8
BIOS ROM_8
[18,24,91] SPI_SO_ROM
8M GND
[18,24,91] SPI_CLK_ROM W25Q64JVZEIQ-GP

BIOS ROM_8
[15,18,24,91] SPI_SI_ROM 3D3V_S5
D D
3D3V_SPI
[15,18,24] SPI_HOLD_ROM
16M & 32M Colay
1
C2501 C2502
[15,18,24] SPI_WP_ROM
1
SC10U6D3V3MX-DL-GP
SCD1U16V2KX-3DLGP
R2508
2
3D3V_SPI
DY 4K7R2J-2-GP BIOS ROM_16
U2503
2
SPI_CS_ROM_N1 1 8
SPI_SO_ROM R2509 1 2 15R2F-2-GP SPI_SO_ROM_R1 2 CS# VCC 7 SPI_HOLD_ROM_R1 R2574 1 2 15R2F-2-GP SPI_HOLD_ROM
SPI_WP_ROM R2575 2 1 15R2F-2-GP SPI_WP_ROM_R1 3 DO/IO1 HOLD#/RESET#/IO3 6 SPI_CLK_ROM_R1 R2572 1 2 15R1F-GP SPI_CLK_ROM
4 WP#/IO2 CLK 5 SPI_SI_ROM_R1 R2573 1 2 15R1F-GP SPI_SI_ROM
GND DI/IO0
16M
For CBG-NV / WM: 32M WSON/ NON RPMC
W25Q128JVSIQ-GP
3D3V_S5 3D3V_SPI
072.25128.0B51
1 R2506 2
2nd = 072.25128.0D61 For CBG-L: 32M WSON/ RPMC
3rd = 072.25128.0F0D 3D3V_SPI
0R0402-PAD-7-NP-GP
U2504
10/11 add 3D3V_SPI, follow 15 UPSELL 1 8

2 CS# VCC 7
3 SO/IO1 IO3 6
4 IO2 SCLK 5
R2512
VSS SI/IO0 072.25256.0B03
SPI_CS_ROM_N0 1
0R2J-2-GP
2 SPI_CS_ROM_N1 9
2nd = 072.25256.0G03
3rd = 072.25256.0N01
BIOS ROM_32M 32M GND
GD25B256DYIGR-GP
3D3V_RTC 3D3V_RTC_AUX
Main Func = RTC

C C
Q2507
PJA3413-1-GP
3D3V_AUX_S5
S
RTC_RST
D
2
084.03413.0031
2
R2502 2nd = 084.02301.0031 R2505
0R2J-2-GP 4K7R2J-2-GP
3rd = 84.00513.03B RTC_RST
1
3D3V_RTC_SYS
[19] RTC_DET#
RTC_3P3_EN_D 1
3rd = 083.52030.0C8F 3D3V_RTC
[24] VCCDSW_EN 2nd = 083.52030.008F
1
3D3V_RTC_VCC
3D3V_RTC_CELL
83.R2003.A8M
[24] RTCRST_ON R2503 D2501
DY47KR2F-GP RB520S30-GP
A K
2
[17,45] 3V_5V_PWRGD R2510 1 2 0R2J-2-GP 3D3V_RTC_VCC_R A K
1
D2502 C2503
RB520S30-GP SCD47U25V3KX-1-DL-GP
83.R2003.A8M 2
R2511 1 DY 2 0R2J-2-GP 2nd = 083.52030.008F
3rd = 083.52030.0C8F
R2567
RTCRST_ON 1 2 RTC_3P3_EN_G
Q2501
1 6 RTC_DET# RTC_RST
1
1
Note:ZZ.27002.F7C01
C2517
R2504 R2518 1MR2J-1-GP SCD022U16V2KX-3DLGP
2 5 RTC_3P3_EN_G
10MR2J-L-GP 3D3V_RTC_VCC 100KR2J-1-GP
2
RTC_3P3_EN_D 3 4
RTC_RST RTC_RST
2
2
B 2N7002KDW-1-GP B
75.27002.F7C
2nd = 075.27002.0E7C
3rd = 075.07002.0A7C
20191120 follow Nakia
3D3V_S5
3D3V_S5
1
R2514
1
R2520
D2504
3V_5V_PWRGD 1 10KR2J-3-GP
2
100KR2J-1-GP 3
2
VCCDSW_EN 2
3V_5V_DSW_OK
20191120
BAT54A-11-GP Follow ICL
75.BAT54.07D High limit don't change U2502
2nd = 075.00054.0A7D
U2502 3D3V_VCCDSW 3D3V_S5_VCCPRIM
3rd = 75.00054.I7D
20191224 4th = 075.00054.0Z7D 4 3
Follow Internal review EN/EN# FLG# 2
5 GND 1 1 2
3D3V_S5 VIN VOUT R2521
0R0603-PAD-7-NP-GP
RT9742CGJ5-GP
074.09742.0A9F
A
20191111 follow Nakia 2nd = 074.51712.009F A
3rd = 074.03553.007F
4th = 074.03553.0A7F
<Core Design>
20191112 modify
Wistron Corporation
Follow Nakia Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Flash
Size
Size Document
DocumentNumber
Number Rev
Rev
A2
Cyborg TGL SC
Date: Sheet
Sheet 25 of 105
5 4 3 2 1
5 4 3 2 1
Main Func = Thermal Sensor PWM FAN1

Layout Note:
Signal Routing Guideline:
Trace width = 15mil
5V_S0 5V_FAN_VCC
1 R2612 2 5V_FAN_VCC
0R0402-PAD-7-NP-GP
C2605
SCD1U16V2KX-3DLGP
C2604
SC4D7U6D3V2MX-1-GP
RB551V30-GP
D2601
C2603
SC2200P50V2KX-2DLGP
1
1
3D3V_S0 3D3V_S0
DY DY
D D
2
A
83.R5003.H8H
2nd = 83.R5003.T8F
2
1
RN2602
SRN2K2J-1-GP
7718
3
4
Q2601
EC_SMB_SDA_THM 6 1 CPU_SMB_SDA_THM
Note:ZZ.27002.F7C01
5 2 5V_FAN_VCC
[24,79] EC_SMB_SDA_THM 7718
4 3 FAN1
[24,79] EC_SMB_SCL_THM 6
2N7002KDW-1-GP PWM_FAN1 4
FAN_TACH1 3
75.27002.F7C CPU_SMB_SCL_THM 2
2nd = 075.27002.0E7C
3rd = 075.07002.0A7C EC2602 EC2601
1
1
SC10P50V2JN-4DLGP
SC10P50V2JN-4DLGP
[17,24] IMVP_VR_ON EC_SMB_SCL_THM 5
2
DY DY AFTP2604 1 ACES-CON4-29-GP
[40] PURE_HW_SHUTDOWN#
20.F1639.004
2nd = 020.F0097.0004
FAN_TACH1 1
AFTP2601
PWM_FAN1 1
AFTP2602
5V_FAN_VCC 1
[24] PWM_FAN1 3D3V_S0 AFTP2603
C C
[24] FAN_TACH1
C2601
SC10U6D3V3MX-DL-GP
C2602
SCD1U16V2KX-3DLGP
1
1
DY
7718
2
NCT7718_DXP IMVP_VR_ON
7718
THM261
C2607
SC470P50V3JN-2GP
C2606
C
1
1 8 CPU_SMB_SCL_THM
SC2200P50V2KX-2DLGP
Q2603
DY
C2608
SCD1U16V2KX-3DLGP
VDD SCL CPU_SMB_SDA_THM
1
B 7718 2 7
D+ 7718 SDA
LMBT3904LT1G-GP
3 6 ALERT#
84.T3904.H11 D- ALERT# DY
2
2
T_CRIT# 4 5
2nd = 084.03904.0I11 T_CRIT# GND
E
2
NCT7718_DXN 3D3V_S5
3rd = 084.03904.0H11
4th = 84.03904.T112.System Sensor, Put on palm rest NCT7718W-GP
74.07718.0B9
1
2nd = 074.00788.00B9
1
R2602
DY 100KR2J-1-GP
R2601 Q2602
Layout Note: 0R0402-PAD-7-NP-GP 2N7002K-2-GP-U
2
2 IMVP_VR_ON G
C2607 close THM2601
D PURE_HW_SHUTDOWN#
THERM_SYS_SHDN# S
Notice:ZZ.2N702.J3101
Layout Note: 84.2N702.J31

2ND = 084.27002.0N31
B Both DXN and DXP routing 10 mil trace width and 10 mil spacing. 3rd = 084.27002.0L31
B
4th = 084.07002.0C31
3D3V_S0
1
7718 2 7K5R2F-1-GP ALERT#
R2603
3D3V_S5
1
7718 2 10K5R2F-GP T_CRIT#
R2604
A A
<Core Design>
Wistron Corporation
Title
Title
THERMAL NCT7718W/Fan
Size
Size Document
DocumentNumber
Number Rev
Rev
A2
Cyborg TGL SC
Date: Sheet
Sheet 26 of 105
5 4 3 2 1
5 4 3 2 1
Main Func = Audio

[19] HDA_SDIN0_CPU
[19] HDA_SDOUT_CODEC
[19] HDA_SYNC_CODEC AUD_HP1_JACK_L

moat
Audio Codec Chip ALC3204
[19] HDA_BITCLK_CODEC AUD_HP1_JACK_R 5V_AVDD 5V_S0
AUD_AGND 1 2
5V_S0 5V_PVDD Layout Note: R2703
LDO1_CAP
Place close to Pin 20
C2707
SC10U6D3V3MX-DL-GP
C2709
C2708 C2706 0R0603-PAD-7-NP-GP
1
R2701 1 2
SCD1U16V2KX-3DLGP
D SC2D2U6D3V2MX-DL-GP D
1
0R0805-PAD-NP-GP C2702
1
R2707 1 2
R2702
100KR2J-1-GP
1D8V_CPVDD SC2D2U6D3V2MX-DL-GP C2703
2
0R0805-PAD-NP-GP SC2D2U6D3V2MX-DL-GP
SC2D2U6D3V2MX-DL-GP
C2704 C2705
[29] AUD_SPK_R+
2
1
1
SCD1U16V2KX-3DLGP
SC2D2U6D3V2MX-DL-GP
LINE1_VREFO
2
MIC2_VREFO
[29] AUD_SPK_R- 1D8V_S0 1D8V_CPVDD
AUD_VREF
LDO1_CAP
2
2
[29] AUD_SPK_L+ Analog moat
CPVEE
R2709 1 2 AUD_AGND
CBN
CBP
0R0402-PAD-7-NP-GP
[29] AUD_SPK_L- AUD_AGND EC2701 1 2 SCD1U16V2KX-3DLGP
1 2
Digital 1.8V power rail should be supplied by
EC2702
EC2703 1 2
SCD1U16V2KX-3DLGP
SCD1U16V2KX-3DLGP
24
23
26
25
21
29
27
30
28
22
linear regulator, not awitching U2701 EC2704 1 2 SCD1U16V2KX-3DLGP
regulator.if switch regulator is EC2705 1 2 SCD1U16V2KX-3DLGP
LINE1-VREFO-L
MIC2-VREFO
LDO1-CAP
HP-OUT-L
CBP
CPVEE
CPVDD
HP-OUT-R
CBN
VREF
unavilable, please make sure that switch
frequency operates at out-band(over 20KHz)
1D8V_S0 R2719 1 2
0R0402-PAD-7-NP-GP 5V_AVDD AUD_AGND
1
31
AUD_AGND AVSS2
C2710 20
[24] NB_Mute# 1 2 LDO2_CAP 32 AVDD1
SC10U6D3V2MX-2-GP AUD_AGND LDO2-CAP
2
C2711 SC10U6D3V2MX-2-GP 19
[20,24] SPKR 1D8V_AVDD AVSS1 AUD_AGND R2704 1 2 0R0402-PAD-7-NP-GP
33
>2A moat AUD_AGND AVDD2 18 LINE1_L R2705 1 2 0R0402-PAD-7-NP-GP
[24] BEEP 5V_PVDD LINE1-L R2706 1 2 0R0402-PAD-7-NP-GP
34
5V_PVDD PVDD1 LINE1_R
17
ALC3204
SC10U6D3V2MX-2-GP SC10U6D3V3MX-DL-GP
SCD1U16V2KX-3DLGP SCD1U16V2KX-3DLGP
[66] AUD_SENSE LINE1-R
1
C2713 C2714 AUD_SPK_L+ 35
SPK-L+ QFN40 (5X5) 16 3D3V_STB
[29] LINE1_VREFO AUD_SPK_L- 36 VD33STB AUD_AGND Layout Note:
SPK-L-
2
15 MIC_CAP C2715 1 2 Tied at point only under
AUD_SPK_R- 37
071.03204.0003 MIC2-CAP AUD_AGND
SC10U6D3V3MX-DL-GP Codec or near the Codec
[29] MIC2_VREFO SPK-R- 14 AUD_SLEEVE
AUD_SPK_R+ 38 SLEEV/MIC2-R
SPK-R+ 13 AUD_RING
GPIO0/DMIC-DATA12
[29] AUD_HP1_JACK_L 5V_PVDD 39 RING2/MIC2-L
PVDD2 12 AUD_HPJD_N
GPIO1/DMIC-CLK
[29] AUD_HP1_JACK_R Layout Note: HP/LINE1-JD_JD1
1
C2717 C2718 PDB_R 40
PDB 11 AUD_PC_BEEP
Speaker trace
SDATA-OUT
PCBEEP
LDO3-CAP
DVDD must >= DVDD_IO width >40mil @ 41
SDATA-IN
DVDD-IO
[29] LINE1_L GND
DC_DET
BIT-CLK
C C
2W4ohm speaker
DVDD
SYNC
[29] LINE1_R 1D8V_S0 1D8V_DVDD power
1 2 ALC3204-CG-GP-U Analog
10
1D8V_DVDD
R2715
0R0603-PAD-7-NP-GP C2741 C2740
Digital moat
HDA_SDOUT_CODEC_R
HDA_BITCLK_CODEC_R
3D3V_S0
1
SCD1U16V2KX-3DLGP
SC2D2U6D3V2MX-DL-GP
HDA_SDIN0_CODEC
[29,66] AUD_SLEEVE place close to pin8
HDA_SYNC_CODEC
DMIC_SDA_CODEC
DMIC_SCL_CODEC
C2723
SC4D7U6D3V2MX-1-GP
place close to pin1
2
1
[29,66] AUD_RING 3D3V_S0
C2720
SC10U6D3V3MX-DL-GP
C2721
1
SCD1U16V2KX-3DLGP
20191112 modify
LDO3_CAP
[55] DMIC_SCL_CODEC
2
1
Follow Nakia
[55] DMIC_SDA_CODEC
R2717
DVSS
For RTC Gen9 reset circuit change power rail.
2
100KR2J-1-GP Open drain output.
pull up to DVDD or 20170921
max. 5V
2
[17,40,55,81] SIO_SLP_S3# NB_Mute# PDB_R 3D3V_STB
R2712 1 2
3D3V_RTC R2708 1 2
1
0R0402-PAD-7-NP-GP C2722 0R0402-PAD-7-NP-GP
[81] 1D8V_EN# SC10U6D3V3MX-DL-GP R2716 1 DY 2 100KR2J-1-GP DVSS
3D3V_S0
20191204 20191128
2
For Vendor request Follow Nakia
20200302
Stuff R2717
AUD_SENSE R2711 1 2 AUD_HPJD_N

200KR2F-L-GP
R2710 1 2 20191204
3D3V_S0 100KR2J-1-GP For Vendor request
Azalia I/F EMI

HDA_SDOUT_CODEC
HDA_BITCLK_CODEC D2703
HDA_SDIN0_CPU R2724 1 2 33R2J-2-GP HDA_SDIN0_CODEC SPKR R2741 1 2 HDA_SPKR_R 1
B 1KR2J-1-GP C2735 B
1
EC2709 EC2710 3 AUD_PC_BEEP_C 1 2 AUD_PC_BEEP

SC10P50V2JN-4DLGP
DY HDA_SDOUT_CODEC HDA_SDOUT_CODEC_R KBC_BEEP_R 2

SCD1U16V2KX-3DLGP
R2722 1 2 BEEP R2734 1 2
SC15P50V2JN-DL-GP
2
0R0402-PAD-7-NP-GP 1KR2J-1-GP
1
HDA_BITCLK_CODEC R2723 1 2 HDA_BITCLK_CODEC_R
C2739
SC100P50V3JN-2GP
BAT54C-12-GP
1
R2735
1KR2J-1-GP
0R0402-PAD-7-NP-GP 75.00054.A7D DY
2nd = 75.00054.T7D
2
2
20191119
Follow ICL
High limit Q2701
PJA3415AE-GP 150mA
084.03415.0C31
1D8V_S5 2nd = 84.03327.031 1D8V_S0
S D
1
1
C2701 R2713 C2712 C2716

10KR2J-3-GP SC1U10V2KX-1DLGP DY SCD1U16V2KX-3DLGP
G
SCD1U16V2KX-3DLGP
2
2
2
1 2 1D8V_EN_R#
R2714
20KR2J-L2-GP
SIO_SLP_S3#
A A
1D8V_EN#
G
S D
Q2702 <Core Design>
PJE8408-R1-00001-GP
084.08408.0031
2nd = 084.00138.0E31 Wistron Corporation
Title
Title
Audio Codec ALC3204

Size
Size Document
DocumentNumber
Number Rev
Rev
A2
Cyborg TGL SC
Date:
Date:Thursday, January 14, 2021 Sheet
Sheet 27 of 105
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
<Core Design>
A
Title
(Reserved)
A4
Cyborg TGL SC
5 4 3 2 1
5 4 3 2 1
Main Func = Audio Layout Note: Speaker CONN Pin Net name
Speaker trace width >40mil @ 2W4ohm speaker power SPK1
7
Pin1 SPK_L+
AUD_SPK_L+ R2902 1 2 0R0603-PAD-7-NP-GP AUD_SPK_L+_C 1
Pin2 SPK_L-
AUD_SPK_L- R2901 1 2 0R0603-PAD-7-NP-GP AUD_SPK_L-_C 2
Pin3 SPK_R-
AUD_SPK_R- R2903 1 2 0R0603-PAD-7-NP-GP AUD_SPK_R-_C 3
[27] AUD_SPK_R+ AUD_SPK_R+ R2904 1 2 0R0603-PAD-7-NP-GP AUD_SPK_R+_C 4
SPK6P Pin4 SPK_R+
[27] AUD_SPK_R- SPK_ID 5
[27] AUD_SPK_L- 6
Pin5 SPK_DET#
[27] AUD_SPK_L+
D
8
Pin6 GND D
AUD_SPK_R+_C
AUD_SPK_R-_C ACES-CON6-20-GP-U
[18] SPK_ID
AUD_SPK_L-_C 20.F1639.006
SPK_ID 1: VECO
1
EC2902 EC2901 EC2903 EC2904
AUD_SPK_L+_C 2nd = 020.F1263.0006
ED2902
SC1KP50V2KX-1DLGP
SC1KP50V2KX-1DLGP
0: ZY
SC1KP50V2KX-1DLGP
SC1KP50V2KX-1DLGP
AZ5725-01FDR7G-GP
SPK_ID
ED2903
2
AZ5725-01FDR7G-GP
2
ED2904
2
ED2901
DY
ED2905
AZ5725-01FDR7G-GP
2
2
SPK2
AZ5725-01FDR7G-GP
AZ5725-01FDR7G-GP
DY 5
1
DY DY DY
1
2 AUD_SPK_L-_C 1 AFTP2901
For CBG L only
1
3 AUD_SPK_L+_C 1 AFTP2902
1
AUD_SPK_R-_C 1 AFTP2903
1
4
6 AUD_SPK_R+_C 1 AFTP2904
SPK_ID 1 AFTP2911
ACES-CON4-114-GP
83.05725.0A0 83.05725.0A0 83.05725.0A0
020.F1796.M002
83.05725.0A0 83.05725.0A0 2nd = 020.F1794.M001
SPK4P
C
From Codec C
Universal Jack (Moved to I/O Board)

RN2901
MIC2_VREFO 2 3
1 4
[27] MIC2_VREFO
[27,29,66] AUD_RING SRN2K2J-1-GP

AUD_RING
AUD_HP1_JACK_L R2908 1 2 10R2F-L-GP AUD_HP1_JACK_L1
[27] AUD_HP1_JACK_L LINE1_L C2907 1 2 LINE1-L_C R2922 1 2 1KR2J-1-GP
SC10U6D3V3MX-DL-GP
[27] LINE1_L LINE1_R C2908 1 2 LINE1-L_R R2921 1 2 1KR2J-1-GP
[27] LINE1_R AUD_HP1_JACK_R SC10U6D3V3MX-DL-GP R2910 1 2 10R2F-L-GP AUD_HP1_JACK_R1
AUD_SLEEVE
[27] AUD_HP1_JACK_R D2901
LINE1_VREFO A K LINE1_VREFO_D1 R2912 1 2
[27,29,66] AUD_SLEEVE 4K7R2J-2-GP
RB520S30-GP 83.R2003.A8M
[27] LINE1_VREFO 2ND = 083.52030.008F
A
3rdK = 083.52030.0C8F
LINE1_VREFO_D2 R2913 1 2
RB520S30-GP D2902 4K7R2J-2-GP
83.R2003.A8M
2ND = 083.52030.008F
3rd = 083.52030.0C8F
B To IO Board B
[27,29,66] AUD_RING
[66] AUD_HP1_JACK_L1
[66] AUD_HP1_JACK_R1
[27,29,66] AUD_SLEEVE
A <Core Design> A
Wistron Corporation
Title
Title
Size DocumentNumber
Number
Audio IO Rev
Size Document Rev
A3
Cyborg TGL SC
Date:
Sheet 29 of 105
5 4 3 2 1
5 4 3 2 1
D D
(Blanking)
C C
B B
<Core Design>
A
Title
(Reserved)
A4
Cyborg TGL SC
5 4 3 2 1
5 4 3 2 1
Main Func = LAN
D D
C C
B B
A A
<Core Design>
Wistron Corporation
Title
LAN RTL8106
Custom
Cyborg TGL SC
5 4 3 2 1
5 4 3 2 1
Main Func = LAN
D D
C C
B B
A <Core Design> A
Wistron Corporation
Title
XFOM&RJ45
A3
Cyborg TGL SC
5 4 3 2 1
5 4 3 2 1
Main Func = Card Reader
D D
C C
B B
<Core Design>
A
Title
Size
Card Reader-RTS5170
Document Number Rev
A4
Cyborg TGL SC
5 4 3 2 1
5 4 3 2 1
Main Func = USB2.0
D D
C C
B B
A A
<Core Design>
Wistron Corporation
Title
Title
USB2.0 CONN
Size
Size Document
Document Number
Number Rev
Rev
Cyborg TGL SC
Date:
Sheet 34 of 105
5 4 3 2 1
5 4 3 2 1
D D
Main Func = USB3.0 Port1
5V_USB30_VCCA
5V_S5
U3502 2A
[24,66] USB_PWR_EN#
5 1
IN OUT 2 ED3502
C3507S USB_PWR_EN# 4 GND 3
EN# OC#
1
2 USB1_USB20_CON_N
C1U10V2KX-1DLGP
Active Low
G524B2T11U-GP USB_OC0# 3
2
074.00524.0C9F 1 USB1_USB20_CON_P
2nd = 074.03553.007G
3rd = 074.09742.009F AZ5315-02F-GP
[16,36] USB_OC0#
NON_PS 83.05315.0A0
2nd = 075.5V0X2.0070
2020/02/29:swap EL3501
C C
USB1_USB20_N 4 3 USB1_USB20_CON_N
USB1_USB20_P 1 2 USB1_USB20_CON_P
USB3.0 Port1
EL3501
[36] USB1_USB20_N DLM0NSN900HY2D-GP 5V_USB30_VCCA
068.09002.2001 USB3.0 Port 1 Layout Note: Close USB3 USB3
[36] USB1_USB20_P
2nd = 68.02002.061 1 5 USB1_USB30_RX_CON_N
VBUS STDA_SSRX- 6 USB1_USB30_RX_CON_P
STDA_SSRX+
5V_USB30_VCCA USB1_USB20_CON_N 2 8 USB1_USB30_TX_CON_N
USB1_USB20_CON_P 3 D- STDA_SSTX- 9 USB1_USB30_TX_CON_P
2A D+ STDA_SSTX+
10
11 10 4
12 11 GND 7
C3508 13 12 GND
C3509 C3506 13
1
SCD1U16V2KX-3DLGP
C3510
SC1U10V2KX-1DLGP
C3512 SKT-USB13-513-GP
2
USB1_USB30_TX_P 1 2 USB1_USB30_TX_CMC_P USB1_USB30_TX_CON_P USB1_USB30_RX_P USB1_USB30_RX_CON_P Stuff for ESD R2 spec
022.10005.0KF1
SCD1U16V2KX-3DLGP ED3501
FL3503 8
[16] USB1_USB30_TX_N FL3502 FILTER-4P-264-GP 3
FILTER-4P-264-GP USB1_USB30_RX_CON_N 1 10 USB1_USB30_RX_CON_N
3 1
3 1 USB1_USB30_RX_CON_P 2 9 USB1_USB30_RX_CON_P
[16] USB1_USB30_RX_P
4 2 2nd = 68.11800.201
4 2 2nd = 68.11800.201 068.24900.2021 USB1_USB30_TX_CON_N 4 7 USB1_USB30_TX_CON_N
068.24900.2021 USB1_USB30_TX_CON_P USB1_USB30_TX_CON_P
5 6
C3511
USB1_USB30_TX_N 1 2 USB1_USB30_TX_CMC_N USB1_USB30_TX_CON_N USB1_USB30_RX_N USB1_USB30_RX_CON_N AZ1043-04F-R7G-GP
SCD1U16V2KX-3DLGP 075.01043.0073
2nd = 075.08810.0A73
3rd = 075.73044.0003
B B
A A
<Core Design>
Wistron Corporation
TitleTitle
USB3.0 CONN
SizeSize Document
Document Number
Number Rev Rev
A1
Cyborg TGL SC
Date:
Sheet 35 of 105
5 4 3 2 1
5 4 3 2 1
Main Func = USB Charger

For CBG L
USB Charger Port1
5V_USB30_VCCA
D 5V_S5 D
USB_OC0#
C3602
1
SCD1U16V2KX-3DLGP
PS
13
12
1
9
U3601
NC#9
FAULT#
IN
OUT
USB_POW ERSHARE_VBUS_EN_D 5 3 CHAR_USB20_P
EN DP_OUT 2 CHAR_USB20_N
R3605 1 2 100KR2J-1-GP ILIM_SEL 4 DM_OUT
5V_S5 PS R3603 1 ILIM_LO 15 ILIM_SEL USB1_USB20_P
R3604 1
DY 22 20KR2F-L-GP
22K1R2F-L-GP ILIM_HI 16 ILIM_LO PS DP_IN
10
11 USB1_USB20_N
PS ILIM_HI DM_IN
CTL1
CTL2
CTL3
GND
GND
C C
TPS2544RTER-GP
14
17
6
7
8
74.02544.073
[16] CHAR_USB20_P 2nd = 074.03524.0073 NON_PS NON_PS
[16] CHAR_USB20_N USB_PW R_SHR_EN_L#_D R3601 1 2 0R0402-PAD CTL1 NON_PS NON_PS
R3606 1 CHAR_USB20_P 2 0R2J-2-GP USB3_USB20_NONPS_P 2 0R2J-2-GP USB1_USB20_P
5V_S5
R3602 1
PS 22 100KR2J-1-GP
100KR2J-1-GP
CTL2
CTL3 CHAR_USB20_N
R3610
R3611
1
1 2 0R2J-2-GP USB3_USB20_NONPS_N
R3616
R3617
1
1 2 0R2J-2-GP USB1_USB20_N
PS
[35] USB1_USB20_N
[35] USB1_USB20_P
Device Control Pins

CTL1
(EC control) CTL2 CTL3 ILIM_SEL
B B
CDP 1 1 1 1
DCP Auto
[24] USB_POW ERSHARE_VBUS_EN_D
0 1 1 X
[24] USB_PW R_SHR_EN_L#_D
[16,35] USB_OC0#
<Core Design>
A A
Wistron Corporation
Title
Title
Size
USB Charger
DocumentNumber
Number Rev
Size Document Rev
Custom
Cyborg TGL SC
Date: Sheet
Sheet 36 of 106
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
<Core Design>
Wistron Corporation
A 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A
Title
USB3.0 PORT
A4
Cyborg TGL SC
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
<Core Design>
Wistron Corporation
Title
Reserved
A4
Cyborg TGL SC
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
<Core Design>
A
Title
(RSVD)
A4
Cyborg TGL SC
5 4 3 2 1
5 4 3 2 1
[17,51,66] SIO_SLP_S4#
RUN Power HW SHUTDOWN
5V_S5
[17,61,62,63,66,71,76,91] PCH_PLTRST#
U4005
SC470P50V2KX-3DLGP D4006
5V_S5 4 12 U4001_CT1 C4057 1 2
VBIAS CT1 3V_5V_EN A K PURE_HW_SHUTDOWN#
10 U4001_CT2 C4069 1 2 5V_S0
20200815
[51] PWR_VDDQ_PG CT2 SC470P50V2KX-3DLGP
3D3V_S5 RB520S30-GP
[22,50] CORE_VID0 C4071 1 13
2 1 2 IN1#1 OUT1#13 14 83.R2003.A8M 2nd = 083.52030.008F 3rd = 083.52030.0C8F
1
C4070 SC1U10V2KX-1DLGP 6 IN1#2 OUT1#14 8 3D3V_S0 R4003
R4002
20KR2F-L-GP
[22,50] CORE_VID1 2 1 7 IN2#6 OUT2#8 9
IN2#7 OUT2#9 DY 1 2 ALWON
Remove
SC1U10V2KX-1DLGP C4005 C4006
1
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
SIO_SLP_S3# 10KR1J-GP
1 R4014 2 3V5V_S0_ON 3 11
1
[17] VCCST_OVERRIDE 0R0402-PAD-7-NP-GP 5 EN1 GND
EN2 C4001
2
C4007 15
THERMAL_PAD SC2D2U6D3V2MX-DL-GP
SCD22U10V2KX-2-GP
[17,24,44,46] ALL_SYS_PWRGD
2
G2898KD1U-GP
2
[17] CPU_C10_GATE#
DY 074.02898.0093
D D
[26] PURE_HW_SHUTDOWN#
074.05209.0093
3rd = 074.07110.0093
[53] PWR_1D8V_EN
[50,53] PWR_1D8V_PG
[54] PWR_1D05V_EN
[24] ALWON 6A/Rds(on):4.5mOhm/Tr:7~20us

1D05V_S5_OUT
(300mA)
5V_S5 U4002 1D05V_VCCSTG_FIP 1D05V_VCCSTG
[54] PWR_VNN_EN 1 8 1 2
2 IN#1 OUT#8 7 R4018
9 IN#2 OUT#7 6 0R0402-PAD-7-NP-GP
[17,27,55,81] SIO_SLP_S3# IN#9 OUT#6
3
VCCSTG_EN 1 R4033 2 VCCSTG_EN_R 4 VBIAS 5
0R0402-PAD-7-NP-GP ON GND
DY
1
G5027CRD1D-GP-U
1
[45] 3V_5V_EN 20191223 R4008 C4010
1
For Internal Review C4028 C4008 C4024
074.05027.0B93
SCD1U16V2KX-3DLGP
SC1U10V2KX-1DLGP
SCD1U16V2KX-L-GP
100KR2J-1-GP
2
2
SCD1U16V2KX-3DLGP
2nd = 074.05201.0A93
2
[22] V1P05_CTRL_R
[24,54] PWR_VNN1D05V_PG
[18,24,68] ESPI_RESET# 3D3V_S5

6A/Rds(on):4.5mOhm/Tr:7~20us
SIO_SLP_S3# A K 2nd = 83.R2004.G8F
3D3V_S5 D4002 D4004 LRB751V-40T1G-GP
(1200mA)
BAT54C-12-GP 1D05V_S5_OUT 5V_S5 1D05V_VCCST_FIP 1D05V_VCCST
CORE_VID0 VCCST_READY 83.00751.08F VCCST_EN
1
R4005 1 A K U4001
[22] VNN_CTRL_R D4008 LRB751V-40T1G-GP
1
R4006 DY 3 1 8 1 2
83.00751.08F 2nd = 83.R2004.G8F 2 IN#1 OUT#8 7 R4016
[17,24] PCH_RSMRST# CORE_VID1 2 VCCST_READY A K VCCSTG_EN 9 IN#2 OUT#7 6
100KR2J-1-GP Q4001 0R0805-PAD-NP-GP
C4002 IN#9 OUT#6
2
2N7002K-2-GP-U D4009 LRB751V-40T1G-GP
SC1U10V2KX-1DLGP
VCCST_OVERRIDE_Q1 G 3
100KR2J-1-GP 75.00054.A7D 83.00751.08F K 2nd = 83.R2004.G8F VBIAS
2
CPU_C10_GATE# VCCST_EN1 R4036 2 VCCST_EN_R
1
(1.05V) 2nd = 75.00054.T7D A 4 5
20200420(DVT2) D 0R0402-PAD-7-NP-GP ON GND
D4005 LRB751V-40T1G-GP
1
C Change to 084.01900.0033 C4004 R4009 C4027 C
1
83.00751.08F2nd = 83.R2004.G8F
D
2
DY
1
S G5027CRD1D-GP-U C4003
SCD1U16V2KX-3DLGP
SIO_SLP_S3# A K
SCD1U16V2KX-L-GP
100KR2J-1-GP
Q4002 DY
SCD1U16V2KX-3DLGP
074.05027.0B93
20190501_NEAL
2
VCCST_OVERRIDE G PJQ1900-GP-U D4010 LRB751V-40T1G-GP
84.2N702.J31
2
2ND = 084.27002.0N31 83.00751.08F 2nd = 83.R2004.G8F 2nd = 074.05201.0A93
2
3rd = 084.27002.0L31
4th = 084.07002.0C31
S
084.01900.0033
2nd = 084.00290.0033
Power Sequence / Pull High PWRGD
VCCIN_AUX_PWRGD 1 2 0R1J-GP PWR_VNN1D05V_PG

R4001 DY
3D3V_S5
3D3V_S0
SIO_SLP_SUS# R4031 1 2
83.R2003.A8M 1D05V_BYPASS_CTRL PWR_1D8V_PG
1
2nd = 083.52030.008F R4012 0R0402-PAD-7-NP-GP R4022 1 2 20KR2J-L2-GP

PWR_VNN1D05V_VID2 1BYPASS
2 0R1J-GP V1P05_CTRL_R DY
3rd = 083.52030.0C8F [54] PWR_VNN1D05V_VID2 R4010
R4026 1 2 10KR1J-GP PWR_VNN1D05V_PG
BYPASS U4010 3D3V_S5_VCCPRIM
SIO_SLP_S3# K A RB520S30-GP R4025 1 2 4K7R2J-2-GP PWR_1D8V_EN SIO_SLP_SUS# 1 U2502_IN 4 3
D4001 10KR2J-3-GP
3D3V_S5_VCCPRIM DY
R4048
DSW 2 0R2J-2-GP
EN/EN# FLG#
2
1 2 0R2J-2-GP PWR_VNN_EN 2
ALL_SYS_PWRGD
R4013 BYPASS 5 GND 1 3D3V_S5_VCCPRIM_R R4047 1 2
PM_SLP_S3# PWR_VNN1D05V_VID1 SIO_SLP_S3# 3D3V_S5 VIN DSWVOUT DSW
1
1
PWR_VDDQ_PG R4007 1 2
[54] PWR_VNN1D05V_VID1 R4011
BYPASS2 0R2J-2-GP C4030 0R2J-2-GP
DY VCCIN_AUX_PWRGD BYPASS PWR_1D05V_EN
1
0R0402-PAD-7-NP-GP C4032 R4049 1 2 0R2J-2-GP VNN_CTRL_R SCD1U16V2KX-L-GP R4030 1 2 10KR2J-3-GP RT9742CGJ5-GP

DY
2
SCD1U16V2KX-3DLGP
C4031
20191120 074.09742.0A9F
Follow Nakia
2
1
20191223 2nd = 074.51712.009F
B
For Internal Review BYPASS 3rd = 074.03553.007F B
4th = 074.03553.0A7F
2
SC1U10V2KX-1DLGP
V-tree
3D3V_S5
1
20200807
R4051
100KR1J-GP
2
Q4009_D
2D5V_S3
Remove
D
Q4009
G
G PJE8408-R1-00001-GP
1
R4052 ALL_SYS_PWRGD
A S D A
1MR2J-1-GP
S
084.08408.0031
2nd = 084.00138.0E31 Q4010
PJE8408-R1-00001-GP
2
084.08408.0031
2nd = 084.00138.0E31
<Core Design>
Wistron Corporation
TitleTitle
CPU (THML/JTAG)
SizeSize Document
Document Number
Number Rev Rev
A1
Cyborg TGL SC
Date:
Sheet 40 of 105
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
<Core Design>
A
Title
Connected_Standby(1/2)+DS3
A4
Cyborg TGL SC
5 4 3 2 1
5 4 3 2 1
D D
(Blanking)
C C
B B
<Core Design>
A
Title
Connected_Standby(2/2)
A4
Cyborg TGL SC
5 4 3 2 1
5 4 3 2 1
Main Func = ADT Input

[24,44] AC_DIS
84.T3904.H11
2nd = 084.03904.0I11
3rd = 084.03904.0H11 5V_S5
[24] PS_ID 4th = 84.03904.T11
1
R4302 3D3V_S5 3D3V_S5
[24,44] HW_ACAVIN_NB
15KR2F-GP R4303
E
PQ3802_1 10KR2J-3-GP
1
B Q4302
Layout Note:
1
LMBT3904LT1G-GP
1
PSID Layout width > 25mil D4302
C
PSID_DISABLE#_R_C
2
[44,89] 19V_AD_JK_C LBAV99LT1G-1-GP R4304
R4309 2K2R2J-2-GP
100KR2J-1-GP 75.00099.O7D
2nd = 75.00099.E7D
2
D Q4301 G D
3rd = 75.00099.B7D
1
PS_ID_R D
R4305 4th = 075.00099.0E7D Barrel Adapter Piug-in Detect
PS_ID_R1 PS_ID
1
ED4303 S 1 2
AZ5725-01FDR7G-GP PJA138KA-GP 084.00138.0A31 3D3V_S5
83.05725.0A0 33R2J-2-GP
2nd = 083.00051.00AF 2nd = 84.05067.031
1
R4313
2
200KR2F-L-GP
DCIN1 60ohm@100MHz
9
DCR=0.02 ohm
Max current = 6000mA
2
S1
1
C4308 3D3V_S5
20191223
1
2 1
SC100P50V2JN-3DLGP
AFTP4301 For EMC requirement R4320
1
3
100KR2F-L1-GP
4 19V_AD_JK_C 19V_AD+
2
5 PU4301 19V_AD_JK_C DY
6 19V_AD_JK_C 1 S D 8
1
7 2 S D 7
2
1
8 3 S D 6
C4303
SCD01U25V2KX-3DLGP
C4306
SC10U25V5KX-DL-GP
R4316
20KR2J-L2-GP
R4314
240KR3-GP
K
1
1
D 5
SC1U25V3KX-1-DLGP
C4301
EC4302 EC4303 C4302 R4317 U4302 10KR2J-3-GP
10 G
SCD1U25V2KX-1-DL-GP
SCD1U25V2KX-1-DL-GP
DY DY SCD1U25V2KX-1-DL-GP 150KR2F-L-GP
R4307
AONR21321-GP U4302- 1 5
INPUT- VCC
2
ETY-CON8-23-GP-U1 D4301 2
GND
2
3 4 HW_ACAVIN_NB
P6AF24A-R1-00001-GP 084.21321.0037 U4302+
INPUT+ OUTPUT
2
20.F2120.008 2nd = 084.20P03.0033
1
2nd = 20.F1295.008 3rd = 084.03307.0037 C4307
1
Q4305 R4319 AS331KTR-G1-GP
47KR2F-GP
SC100P50V2JN-3DLGP
1
E
R2
Q4304
AD_OFF_L
15KR2F-GP 74.00331.H2F
083.00624.00AM C B
R4308
2
AC_DIS B R1 R1
C 19V_AD_OFF
DY 2nd = 74.00391.02F
2
2nd = 083.FJ24A.00AM E
1
R2 LMUN5112T1G-GP-U
2
R4379
100KR2J-1-GP LMUN5212T1G-GP 084.05112.001K
19V_AD_JK_C PS_ID_R
84.05212.B11 2nd = 84.00124.K1K
2
EC4312 2nd = 84.00124.H1K 3rd = 084.00024.0A1K
SC1KP50V2KX-1DLGP
EC4313 EC4311
3rd = 084.00024.0B1K
1
SCD1U25V2KX-1-DL-GP
SCD1U25V2KX-1-DL-GP
2
2
DY DY
C AFTP4303 1 19V_AD_JK_C C
AFTP4302 1 19V_AD_JK_C
AFTP4305 1 19V_AD_JK_C
AFTP4304 1 PS_ID_R
B B
[24,44] PBAT_CHG_SMBCLK
[24,44] PBAT_CHG_SMBDAT
[24,44] PBAT_PRES#
Main Func = M-BAT Input Placement: Close to Batt Connector
Batt Connecter
PBAT_PRES#
PBAT_CHG_SMBDAT
PBAT_CHG_SMBCLK
BT+
20200324(DVT2)
K
EC4307 change to common DY

1
EC4308 D4307
EC4307
SCD1U50V3KX-GP DY SMF18A-GP
3
3
SCD1U25V2KX-1-DL-GP
2
D4304 D4305 D4306

A
20191218 BATT1 LBAV99LT1G-1-GP LBAV99LT1G-1-GP LBAV99LT1G-1-GP

For EMC required 11 DY 75.00099.O7D DY 75.00099.O7D DY 75.00099.O7D
3D3V_RTC_CELL 1
A RN4302 A
1
2
SRN100J-3-GP 2
PBAT_PRES# 3
PBAT_CHG_SMBCLK 2 3 PWR_SMB_SCL_CHG_R 4
PBAT_CHG_SMBDAT 1 4 PWR_SMB_SDA_CHG_R 5
PBAT_PRES# 3D3V_RTC_CELL 3D3V_S5_KBC
6
1 R4301 2 SYS_PRES1# 7
1 2 0R0402-PAD-7-NP-GP 8 2nd = 75.00099.E7D 2nd = 75.00099.E7D 2nd = 75.00099.E7D
R4310 9
100R2J-2-GP 10 3rd = 75.00099.B7D 3rd = 75.00099.B7D 3rd = 75.00099.B7D
External_RTC 12
D
Q4303 EC4309 EC4310 EC4306 4th = 075.00099.0E7D 4th = 075.00099.0E7D 4th = 075.00099.0E7D
1
1
SC10P50V2JN-4DLGP
SC10P50V2JN-4DLGP
SC10P50V2JN-4DLGP
ETY-CON10-35-GP
020.F1198.0010 <Core Design>
2nd = 020.F1196.0010
2
3D3V_RTC_CELL G 1
DY DY DY 1
AFTP4306
AFTP4307
1 AFTP4308 Wistron Corporation
1

L2N7002SWT1G-GP 3D3V_RTC_CELL 1 AFTP4309 Taipei Hsien 221, Taiwan, R.O.C.
S
PWR_SMB_SDA_CHG_R 1
R4331 Internal_RTC PWR_SMB_SCL_CHG_R 1
AFTP4310
2MR2F-GP 084.27002.0Q31 1
AFTP4311 TitleTitle
2nd = 084.27002.0C31 R4332 BT+ AFTP4312
DCIN
2
3D3V_RTC_VCC 0R2J-2-GP BT+ 1 AFTP4313

1 DY 2 BT+ 1 AFTP4314 SizeSize Document
Document Number
Number RevRev
SYS_PRES1# 1 AFTP4315 A1
Cyborg TGL SC
Date:
Sheet 43 of 105
5 4 3 2 1
5 4 3 2 1
Main Func = Charger
ISL9538C For Charger

+SDC_IN
K
PD4411
AZ4024-01L-R7G-GP
OFFPAGE DY
A
EE needs check it!! +SDC_IN 20V_DCBATOUT
19V_DCBATOUT
19V_AD+
S2
PR4401
PBAT_CHG_SMBDAT 77.C1561.06L D01R6F-26-GP
[24,43] PBAT_CHG_SMBDAT 2nd = 77.21561.01L 1 2
I2C form EC 064.R010I.L002
PC4441 PC4401 PG4401 PG4402
1
2nd = 064.R010K.L002 PC4406 PC4407 PC4408 PC4409 PC4410 PC4411 PC4412 PC4413 PC4414 PC4442
ST15U25VBM-1-GP
SC10U25V5KX-DL-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PBAT_CHG_SMBCLK FC4401 FC4402
1
SC10U25V3MX-5-GP
SC10U25V3MX-5-GP
SC10U25V3MX-5-GP
SC10U25V3MX-5-GP
SC10U25V3MX-5-GP
SC10U25V3MX-5-GP
SC10U25V3MX-5-GP
SC10U25V3MX-5-GP
SC10U25V3MX-5-GP
PU4415 PR4468 PC4469 3rd = 064.R010L.L001 PC4402 PC4403 PC4404 PC4405 DY
1
[24,43] PBAT_CHG_SMBCLK DY
SC33P25V1JN-GP
SC33P25V1JN-GP
PR4466
1
SC10U25V3MX-5-GP
SC10U25V3MX-5-GP
SC10U25V3MX-5-GP
SC10U25V3MX-5-GP
SCD1U25V2KX-1-DL-GP
AONR21321-GP 4th = 064.R010L.L002
1
SC1500P50V2KX-2-DL-GP
100KR2F-L1-GP
100KR2J-1-GP
8 D S 1 5th = 064.R010J.L001
DY DY
2
S
7 D S 2
2
1
2
HW_ACAV_IN PWR_ADP_19V_E
6 D S 3
2
[24,64] HW_ACAV_IN
5 D G
G
PWR_CHG_CSIP_R
PWR_CHG_CSIN_R
To EC PQ4451
2
084.21321.0037 AOSS21319C-GP
4
D D
2
[17] AC_IN# 084.21319.0031
2nd = 084.20P03.0033
D
3rd = 084.03307.0037 2nd = 084.03409.0031
1
20191223 PR4422 PR4423
PWR_ADP_19V_F For high limit
[24,43] AC_DIS 1R2F-GP 1R2F-GP
PWR_ADP_19V_G 1 2
PR4465
2
0R0402-PAD-7-NP-GP
ISL9538 AMON/BMON to EC PC4415
1 PR4494 2 PWR_CHG_IMON 2 1
[24] PWR_AD_IA
0R0402-PAD-1-GP
1
PR4467
SC4D7U25V5KX-DL-GP
PBAT_PRES# PR4447 1 2 PWR_PBAT_PRES# 10KR2F-2-GP
1
[24,43] PBAT_PRES#
1
0R1J-GP
External_RTC PR4464 PC4416 PC4417 PU4403 PU4405
D 8
D 7
D 6
D 5
SC1U25V3KX-1-DLGP SC1U25V3KX-1-DLGP AONR20334C-GP AONR20334C-GP
5
6
7
8
100KR2F-L1-GP
2
084.20334.0037
D
D
D
D
PWR_ADP_19V_A
084.20334.0037
2
2nd = 084.03323.0037 2nd = 084.03323.0037
4ZA_CHARGER DCR=8mm~9m Ohm, 4ZA_CHARGER
4 Idc=13A, Isat=16A 4
G
G
+SDC_IN
10.0mm x 11.5mm x 3.0mm
S
S
S
TP4401
S
S
S
PQ4452
1
2
3
TPAD14-OP-GP PC4436
3
2
1
3 4 SCD22U25V3KX-DL-GP
2 1 PWR_CHG_BT1_R 2 1
AC_DIS 2 5 HW_ACAVIN_NB
U7419_FLTB
Note:ZZ.27002.F7C01
1
[74] U7419_FLTB PR4402
1 6 DC_IN_OFF 2D2R3-1-U-GP PL4401
1 2
2N7002KDW-1-GP IND-2D2UH-447-GP
From NXP ACK +SDC_IN 75.27002.F7C
068.2R210.2351
2nd = 075.27002.0E7C
3rd = 075.07002.0A7C 2nd = 68.2R21F.10V
[24,43] HW_ACAVIN_NB 83.R2003.A8M PU4404 PU4406
PWR_CHG_ASGATE
PWR_CHG_UGATE1
PWR_CHG_PHASE1
PD4407 2ND = 083.52030.008F
5
6
7
8
AONR20334C-GP
PWR_CHG_BOOT1
D 8
D 7
D 6
D 5
RB520S30-GP AONR20334C-GP
3rd = 083.52030.0C8F
1
PWR_CHG_CSIN
D
D
D
D
PWR_CHG_CSIP
19V_DCBATOUT
A K 084.20334.0037 084.20334.0037
2nd = 084.03323.0037 PR4416 2nd = 084.03323.0037
PWR_CHG_DCIN_R
DY DY PR4414
2D2R5J-1-GP
4ZA_CHARGER 4ZA_CHARGER
2D2R5J-1-GP
PWR_CHG_LGATE1 4
G
PD4401 4
1 PWR_CHG_SNB2 2
G
PR4403
S
S
S
RB520S30-GP
S
S
S
[24,79] GPU_PWR_LEVEL
1 PWR_CHG_SNB
A K 2 1
3
2
1
+SDC_IN
1
2
3
1
83.R2003.A8M 10R5J-GP
2ND = 083.52030.008F PC4419
PU4401
16
15
14
13
12
11
10
3rd = 083.52030.0C8FPR4405
9
SC4D7U25V5KX-DL-GP
2
PWR_CHG_VDD
1
CSIN
BOOT1
UGATE1
PHASE1
LGATE1
ADP
CSIP
ASGATE
4D7R2F-GP PC4435 PC4418
PWR_CHG_VDDP 1 2
SC1KP50V2KX-1DLGP
SC1KP50V2KX-1DLGP
PR4404 PC4421 DY DY
402KR2F-GP SC4D7U10V3KX-DL-GP
1
PC4422
2
PWR_CHG_DCIN 17 8 PWR_CHG_VDDP 1 2
SC4D7U10V3KX-DL-GP DCIN VDDP
2
[46] CHGR_PSYS_IMVP
18 7 PWR_CHG_LGATE2
2
VDD LGATE2
PWR_CHG_ACIN 19 6 PWR_CHG_PHASE2
PR4457 ACIN ISL9538CHRTZ-T-2-GP PHASE2 PR4408 PC4423
[17,46] PWR_IMVP_PWRGD
PWR_VCOREOVP_OVP_+ 1 2 0R2J-2-GP PWR_CHG_OTGEN 20
CMIN
1st = 074.09538.M001 UGATE2
5 PWR_CHG_UGATE2 2D2R3-1-U-GP SCD22U25V3KX-DL-GP
1
Gen 12 PWR_CHG_BOOT2 PWR_CHG_BT2_R
2
[17,24,40,46] ALL_SYS_PWRGD PR4489 21 4 2 1 1 2 PC4424
PR4406 1 AC_DISC# 1 SDA BOOT2
2
C 2 0R2J-2-GP PR4417 SC1U25V3KX-1-DLGP C

DY 22 3 1 2
100KR2F-L1-GP
PC4420 TP4402 DY 100KR1F-GP PG4405

SCD1U25V2KX-1-DL-GP SCL VSYS DY PR4424 GAP-CLOSE-PWR-3-GP
TPAD14-OP-GP PC4439
1
23 2 PWR_CHG_CSOP 2 1PWR_CHG_CSOP_R 2 1
1 PROCHOT# CSOP SC1U25V3KX-1-DLGP
[43,89] 19V_AD_JK_C
PWR_CHG_ACOK PWR_CHG_CSON 1R2F-GP PR4407
1
24 1 2 1
AMON/BMON
ACOK CSON PC4425 D005RL3720F-4-GP
1
BATGONE
SC1U25V3KX-1-DLGP 064.R005L.L004
CMOUT
BGATE
33 2nd = 064.R005I.L003
COMP
PROG
PSYS
VBAT
GND
2
PR4425 1PWR_CHG_CSON_R
2
2 2 1 BT+
PU4412
E3 1R2F-GP
25
26
27
28
29
30
31
32
PBAT_CHG_SMBDAT 1 2 PG4406 AONR21307-GP
GAP-CLOSE-PWR-3-GP PWR_CHG_VBATIN 1 S D 8
[66] PWR_CHG_VBATIN PBAT_CHG_SMBCLK PC4426 2 S D 7
FC4403
PWR_CHG_BATGONE
3 D 6
PWR_CHG_CMOUT
PWR_CHG_BGATE
SCD22U25V2KX-4-GP S
PWR_CHG_VBAT1
1
PWR_CHG_AMON
PWR_CHG_COMP
PWR_CHG_PROG
PWR_CHG_PSYS
PWR_CHG_PROCHOT# PC4427 PC4428 D 5 SCD1U16V2KX-3DLGP
DY
1
G
SC10U25V5KX-DL-GP
SC10U25V5KX-DL-GP
2
4
1
PC4429
2
084.21307.0037
SC4700P50V2KX-1DLGP
2nd = 084.01403.0A37
2
PWR_CHG_VDD PWR_CHG_VDD
90815-SA_James add PR4430 PWR_PBAT_PRES# PR4409 2 1 100KR1F-GP PC4440
1
1 PR4430 2 PWR_CHG_PROCHOT#_CPU SC1U25V3KX-1-DLGP

[3,22,24,46,72] PROCHOT#_CPU PR4427 PR4429 2 1
0R0402-PAD-1-GP 100KR2F-L1-GP 100KR2F-L1-GP
1
PR4461
0R1J-GP PR4478
1
PC4430
PR4498 100R1F-GP
Internal_RTC
2
PQ4418_3 PQ4415 SC10P50V2JN-4DLGP 1 2

1 2
20200121 DVT1 External_RTC
ACOK#
2
Follow 15 upsell 4 3 2 1 PR4413
2
0R0402-PAD-1-GP
0R0402-PAD-1-GP
2
2
1 2
HW_ACAV_IN 5 2 PR4410
PG4408 13K3R2F-L1-GP
GAP-CLOSE-PWR-3-GP 316KR1F-GP
PR4412
AC_IN# 1 2 CHGR_PSYS_IMVP
1
6 1
PR4476 PR4442
1 2 PQ4405_3
0R0201-PAD-GP
1
2N7002KDW-1-GP PR4426
196KR2F-GP
0R0402-PAD-1-GP 75.27002.F7C PWR_CHG_IMON
2nd = 075.27002.0E7C
2
3rd = 075.07002.0A7C
1
PC4432
SC1KP50V2KX-1DLGP
2
1
PR4411
499R2F-2-GP
20V_VCCPD_VBUS
19V_AD_JK_C
+3D3V_VDD_DCIN
For CBG L
1
PC4433
0523
2
DY PWR_CHG_COMP_R
SC1KP50V2KX-1DLGP
2
PQ4402
1
1
PC4431 PD44C1
B 2N7002K-2-GP-U B
G PWR_CHG_PROCHOT#_R SCD01U25V2KX-3DLGP BAT54C-12-GP
L 75.00054.A7D
2
GPU_PWR_LEVEL D 2nd = 75.00054.T7D PU44C1 PWR_EXT3D3V_OUT

PU 3V3_AON_S0 on GPU side S 20V>+DC_IN>4.7V
3
PWR_EXT3D3V_VIN 1 5
2 IN OUT
84.2N702.J31 GND L
1
3 4
2ND = 084.27002.0N31 EN ADJ
1
PR44C7 PC44C3
PWR_EXT3D3V_ADJ
3rd = 084.27002.0L31 L L
1
13K3R2F-L1-GP SC10U25V3MX-5-GP PR44C2 PC44C2
4th = 084.07002.0C31 G2920T11U-GP R1 L 16K9R2F-GP L SC2D2U10V3KX-1DLGP-U
2
OPS 074.02920.003F
2
2nd = 074.02205.000F
2
PR44C4
PU44C1_EN 1 PU44C1_EN_R
1
2
L Vout=1.24*(1+(R1/R2)) PR44C3
R2 L 10KR2F-2-GP
1
100KR2F-L1-GP
1
PR44C1 PC44C1
L 10KR2F-2-GP DY SC100P50V2JN-3DLGP
2
PU +VCCSTG = 1.0 V on CPU side
2
3D3V_S5
2
3D3V_S5 PWR_CHG_PROCHOT#_CPU
1
1
PR4435 83.R5003.H8H
PR4472 PQ4416 PD44A2 2nd = 83.R5003.T8F
Vcore_OVP
100KR1F-GP
A
100KR1F-GP 4 3 1V_CPU_CORE Gen 12K
2
RB551V30-GP 83.R5003.H8H PWR_EXT3D3V_OUT +SDC_IN

2
5 2 PWR_CHG_PROCHOT#
PD44A3 2nd = 83.R5003.T8F
Note:ZZ.27002.F7C01
1D8V_CPU_AUX A K PWR_CHG_VDD
PWR_CHG_PROCHOT#_R 6 1 Gen 12
1
RB551V30-GP
2N7002KDW-1-GP PWR_EXT3D3V_OUT PR4459 PR4460
DY 0R2J-2-GPGen 11
Psys detect Function 0R2J-2-GP
75.27002.F7C
CHECK EE
1
2nd = 075.27002.0E7C
2
3rd = 075.07002.0A7C PR4496 PR44A7 DY PR44A8
19V_AD+
follow custormer circuits. CHGR_PSYS_IMVP
0R2J-2-GP
1
DY 2
0R0402-PAD-7-NP-GP 0R2J-2-GP
83.R5003.H8H not verify in
OVP function test, don't
2
stuff on PD44A1 PWR_VCOREOVP_PWR
CPU VR Power Enable PR8635 PR4446
100KR1F-GP
PR4473
1KR2F-3-GP 0R2J-2-GP
1
TypeC Prochot ALL_SYS_PWRGD 2 1 OVP_VR_EN S

Gen 11 D OVP_VR_EN_A 1
Gen 11
2 VCORE_OVP_+_A PD44A1
1
PQ4425 LRB551V-30T1G-GP
1
1
1
K
Follow custormer circuits. Gen 11 AOSS21319C-GP PR44A2 Gen 11A PR44A4
1
PR4437 PC4456 PR4438 084.21319.0031 Gen200KR2F-L-GP
11 100KR2F-L1-GP
Gen 11 Gen4K99R2F-L-GP
11
2
200KR2F-L-GP 2nd = 084.03409.0031 PR44A0 83.R5003.T8F L
G
PQ4418_3 45K3R2F-L-GP PU44A1
Gen 11
2
L
2
2
2
OVP_VR_EN_G PWR_VCOREOVP_OVP_- 1 5 PWR_VCOREOVP_VCC
1
PQ4405_3 INPUT- VCC
2
2
PWR_VCOREOVP_OVP_+ GND Gen 11 PWR_VCOREOVP_OUT
PR4436 DY 3
INPUT+ OUTPUT
4
1
PQ4408_E
1MR1J-GP
PR4439
1
2
Gen 1KR2F-3-GP
11 PC44A9 PR44A3 PC44A1 AS331KTR-G1-GP
SC100P50V2JN-3DLGP
75KR2F-GP
SC100P50V2JN-3DLGP
PR44A1 L Gen 11 Gen 11 74.00331.H2F
A A
46K4R2F-2-GP
PQ4418
2
PD4404
E
L
A PD4403_A
Q2
K B PQ4408
2
3 D2 S2 4 PQ4405
MMBT3906FN3-GP-U Q2
L1SS355T1G-GP 84.03906.010
U7419_FLTB PQ4418_5
C
2 5 3 4
83.00355.G1F 2nd = 084.03906.0A13
D2 S2
G1 G2
OVP_VR_EN_G_A
1 6 2nd = 083.00355.0A1F PQ4405_2 PQ4405_5 CPU VR Power Good PR4441
L
2 5 PQ4423
1
D1
PC4449 0R2J-2-GP
S1 G1 G2
PC4438
1
PWR_IMVP_PWRGD OVP_PCH_PWROK 1
1
TypeC_F 1 2 6 PR4456
Gen 11
Q1
SCD1U16V2KX-3DLGP
1 6
SCD1U16V2KX-3DLGP
PR4499 PX5D8JZ-GP 0R0402-PAD-7-NP-GP

S1 D1
0R1J-GPDY
2
075.PX5D8.007C Charger ACIN PR4493 OVP_PCH_PWROK_G 2 5 OVP_ACIN_G 1 2

1
Q1
2
2nd = 075.08808.007C 19V_DCBATOUT 0R2J-2-GP

PQ4418_6
PR4475 PR4463 PX5D8JZ-GP PWR_CHG_ACIN 1 2 OVP_ACIN 3 4

680KR1F-GP 0R1J-GPDY 075.PX5D8.007C
Gen 12
2
1
PC4458 DY PR4455
PQ4405_6
2nd = 075.08808.007C
2
2N7002KDW-1-GP SC100P50V2JN-3DLGP 0R2J-2-GP <Core Design>

Gen 11
PWR_CHG_ACOK
PWR_CHG_CMOUT
1
1 2
PR4497 75.27002.F7C
PWR_CHG_ACOK
2
2
PR4432 PC4454
240KR1F-GP 2nd = 075.27002.0E7C
1
10KR1F-GP
3D3V_S5 TypeC_F PR4450
PR4474
240KR1F-GP
SCD22U25V3KX-DL-GP 3rd = 075.07002.0A7C Gen 12 Wistron Corporation
1
10KR1F-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

2
3D3V_S5 Taipei Hsien 221, Taiwan, R.O.C.

1
2
Title
Title
Size
Power (Charger_ISL9538)
Document Number Rev
SizeCustomDocument Number Rev
Cyborg TGL SC
5 4 3 2 Date:
1 Sheet
5 4 3 2 1
SSID = PWR.Plane.Regulator_5V
OFFPAGE-Signal OFFPAGE-GAP
19V_DCBATOUT
SY8288C For 5V
K
PD4501
AZ4024-01L-R7G-GP
DY
A
1 2 PWR_5V_EN
[40,45] 3V_5V_EN PR4559
D 0R0402-PAD-7-NP-GP
TDC=8.62A D
PH on EE Side 19V_DCBATOUT PU4551

PG
9 PWR_5V_PG ICCMAX=6.034A
7.2408A<OCP<9.6544A
2
1 2 PWR_5V_PG IN#2 Cyntec. 6.8 x7.3 x 3.0mm
[17,25,45] 3V_5V_PWRGD
PR4561 3 1 PWR_5V_BOOT 1 2PWR_5V_BOOT_A 1 2 DCR: 14~15mOhm
IN#3 BS
Idc : 9A , Isat : 18A
1
0R0402-PAD-7-NP-GP PC4552 PC4554 PC4555 PR4554
4
SCD1U25V2KX-1-DL-GP
SC10U25V5KX-DL-GP
SC10U25V5KX-DL-GP
DY DY 0R0603-PAD-1-GP-U PC4553
teknisi indonesia
IN#4 SCD1U25V2KX-1-DL-GP
2
5 PL4502 5V_S5
IN#5 COIL-1UH-104-GP
6 PWR_5V_PH 1 2
LX#6
PWR_5V_PG 10 19
068.1R010.2141
NC#10 LX#19 2nd = 068.1R010.2621 DY DY
20 PC4556 PC4557 PC4558 PC4559 PC4560 PC4561
LX#20
1
16
NC#16 Trace used 10 mil PC4565
SCD1U16V2KX-3DLGP
PG4562 DY
GAP-CLOSE-PWR-3-GP
2
14 PWR_5V_VOUT 1 2
PWR_5V_VCC 17 OUT
VCC
1
PC4562 13 PWR_5V_FB 1 2PWR_5V_FB_A 2 1
SC2D2U6D3V2MX-DL-GP FF PR4555
PWR_5V_EN 12 PC4563 1KR2F-3-GP
EN1
2
SC1KP50V2KX-1DLGP
PWR_5V_EN2 11 15 PWR_5V_LDO
EN2 LDO
1
For 2cell use
1
PR4556
GND
GND
GND
GND
1MR2J-1-GP PC4551
DY SC4D7U6D3V2MX-1-GP
2
SY8288CRAC-GP
18
21
PR4557 074.08288.0B43
499KR2F-1-GP
1 2
19V_DCBATOUT
2
C PR4558 PC4564 DY PWR_5V_FB C
499KR2F-1-GP
1
SCD1U25V2KX-1-DL-GP
1
2
PR4551
DY348KR2F-GP
2
EN rating 25V
EN Rising Threshold : 0.8V
Ilimt : 8A
SSID = PWR.Plane.Regulator_3D3V
PWR_DCBATOUT_3D3V
TPS51393 For 3D3V

K
19V_DCBATOUT
PG4515
PWR_DCBATOUT_3D3V PD4502
AZ4024-01L-R7G-GP
DY
PR4501
0R0603-PAD-1-GP-U
PC4506
SCD1U25V2KX-1-DL-GP
TDC=7.11713A
GAP-CLOSE-PWR-3-GP PWR_3D3V_BOOT 2 1 PWR_3D3V_BOOT_A 2 1
ICCMAX=10.1009A
A
1 2 PWR_3D3V_EN 1 2
[40,45] 3V_5V_EN
12.12108A<OCP<16.16144A
PWR_3D3V_VCC
PR4560 Vin Operating range : 4.5V~24V
0R0402-PAD-7-NP-GP
Vin_Max : 26V Cyntec. 6.8 x7.3 x 3.0mm
1
PG4516 PC4522
DCR: 14~15mOhm
B
GAP-CLOSE-PWR-3-GP
1 2
Idc : 9A , Isat : 18A Design Current : 8A B
2
PH on EE Side
17
PWR_DCBATOUT_3D3V PU4501 PL4501 3D3V_S5
PG4517 COIL-1UH-104-GP
VCC
1 2 PWR_3D3V_PG GAP-CLOSE-PWR-3-GP 2 6 PWR_3D3V_PH 1 2
[17,25,45] 3V_5V_PWRGD 1 2 3 VIN SW#6 19
PR4562
4 VIN SW#19 20
068.1R010.2141
0R0402-PAD-7-NP-GP PC4502 PC4503
VIN SW#20 2nd = 068.1R010.2621
1
5 PWR_3D3V_LDO
SC10U25V3MX-5-GP
SC10U25V3MX-5-GP
PC4501
VIN
1
10
SCD1U25V2KX-1-DL-GP
PG4518 PC4509 PC4510 PC4511 PC4513 PC4512

PWR_3D3V_EN 12 NC#10 15 PWR_3D3V_LDO
GAP-CLOSE-PWR-3-GP
EN LDO DY
2
1 2 PWR_3D3V_EN2 11 16
ENLDO NC#16
2
1
PR4514 PWR_3D3V_BOOT 1
BOOT
1
PWR_3D3V_PG 9 7
1MR2J-1-GP
PWR_3D3V_FB 13 PGOOD GND 8 PC4507
14 FB GND 18 SC10U6D3V3MX-DL-GP
VOUT GND
2
21
GND
2
TPS51393PRJER-GP
074.51393.0A43
Place another side , make GND plan bigger
Close to PC4511
19V_DCBATOUT Trace used 10 mil PG4530
GAP-CLOSE-PWR-3-GP
1
PWR_3D3V_VOUT 1 2
PR4509
300KR2J-GP PC4526 PR4506
1 2 PWR_3D3V_FB2 1 2
2
EN rating :5.5V SC470P50V2KX-3DLGP 240KR2F-L-GP

EN Rising Threshold :1.5V
EN Falling Threshold : 0.4V
1
PR4508
100KR2J-1-GP
A A
2
DY PR4505
100KR2J-1-GP
3D3V_AUX_S5 1 2 <Core Design>
3D3V_AUX_S5
PG4532
GAP-CLOSE-PWR-3-GP
PWR_3D3V_LDO
Wistron Corporation
2 1 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
Title
POWER (SY8288_5V/3D3V)
Size
Size Document
DocumentNumber
Number Rev
Rev
A2
Cyborg TGL SC
Date:
Sheet 45 of 105
5 4 3 2 1
5 4 3 2 1
Main Func = CPU_CORE 1D05V_VCCST
OFFPAGE Close to VR IC
1
SVID
PR4606
PR4605
PR4604
DY PC4626
SCD1U25V2KX-1-DL-GP
2
1
1
1
[7] SVID_CLK_CPU
DY
2
2
2
[7] SVID_DATA_CPU
43R2F-2-GP
56R2F-1-GP
100R2F-L1-GP-U
D D
1D05V_VCCSTG_TERM
[7] SVID_ALERT#_CPU
SVID_CLK_CPU
SVID_ALERT#_CPU
1
SVID_DATA_CPU
PR4603
DY 1KR2F-3-GP
PR4624
PR4623
PR4622
2
5V_S5 19V_DCBATOUT
PR4607
100R2F-L1-GP-U
1
1
1
1
PWR_VCORE_VRHOT_R 1 2
K
PR4617
0R0402-PAD-7-NP-GP PD4601
AZ4024-01L-R7G-GP
083.04024.0AA1
2
2
2
2
3D3V_S0 2 1 2nd = 83.PJSD2.0AF
19V_DCBATOUT
A
0R0402-PAD-7-NP-GP
0R0402-PAD-1-GP
0R0402-PAD-7-NP-GP
PR4631 PR4601
0R0402-PAD-1-GP 0R0402-PAD-7-NP-GP
1
1 2 PWR_VCORE_VRHOT_R
[3,22,24,44,72] PROCHOT#_CPU
1
PR4609 PC4613 1 2
10KR2J-3-GP SC1U10V2KX-1DLGP
PC4601 SCD22U25V2KX-4-GP
2
2
CHGR_PSYS_IMVP PWR_VCORE_VR_READY
[44] CHGR_PSYS_IMVP
PC4612
20191119
PWR_VCORE_ALERT#
SC4700P50V2KX-1DLGP
PWR_VCORE_VRHOT
check with Nakia need change
PWR_VCORE_SCLK
PR4636
PWR_VCORE_SDIO
PWR_VCORE_VDD
netname to PWR_VCORE_VR_READY or PWR_VCORE_VR_EN
PWR_VCORE_VIN
0R0402-PAD-1-GP 1 2
not 1 2 PWR_VCORE_VR_READY
[17,44] PWR_IMVP_PWRGD
PR4602
PR4635 12K1R2F-L1-GP PROG1
0R0402-PAD-1-GP 1 DY 2
VBOOT:0V
1
C 1 2 PWR_VCORE_VR_EN C
[17,24,40,44] ALL_SYS_PWRGD
PR4619 PR4620 F=750kHz
20200302(DVT1) 78K7R2F-GP 9K31R2F-GP
PC4609
32
31
30
28
33
29
27
26
25
Change PC4609 to 0201
VCORE SENSE SC330P25V1KX-2-GP 20200313(DVT1) PU4601
2
1 2 Change to 25V
VR_READY
VR_ENABLE
VR_HOT#
ALERT#
SCK
SDA
GND
VDD
VIN
20200221(DVT1)
changes to 90.9K
VSSCORE_SENSE CHGR_PSYS_IMVP 1 24 PWR_VCORE_PROG1 PC4610
[7] VSSCORE_SENSE PR4608 PSYS PROG1
1 2 PWR_VCORE_IMON 2 23 PWR_VCORE_PROG2 SCD22U25V2KX-4-GP
90K9R2F-GP PWR_VCORE_NTC 3 IMON PROG2 22 PWR_VCORE_BOOT1 1 2 PWR_VCORE_BOOT1_N 1 2
PWR_VCORE_COMP 4 NTC ISL95869HRTZ-T-GP BOOT1 21 PWR_VCORE_UGATE1 PR4621
VCCCORE_SENSE PWR_VCORE_FB 5 COMP UGATE1 20 PWR_VCORE_PHASE1 0R0603-PAD-7-NP-GP
[7] VCCCORE_SENSE PWR_VCORE_RTN 6 FB PHASE1 19 PWR_VCORE_LGATE1
PWR_VCORE_ISUMN1 7 RTN LGATE1 18
8 ISUMN PWM3 17 PWR_VCORE_VDDP 2 1
ISUMP VDDP 5V_S5
1
PR4616 1st = 074.95869.M001 PR4625

0R0402-PAD-7-NP-GP
10KR2F-2-GP
UGATE2
PHASE2
LGATE2
BOOT2
1
FCCM
ISEN1
ISEN2
ISEN3
PC4625
SC1U10V2KX-1DLGP
2
2
9
10
11
12
13
14
15
16
PWR_VCORE_NTC_N
PWR_VCORE_UGATE2
PWR_VCORE_PHASE2
PWR_VCORE_LGATE2
PWR_VCORE_BOOT2
B=4500
1
PWR_VCORE_UGATE1 PR4618
[47] PWR_VCORE_UGATE1
2
NTC-470K-17-GP
069.60012.0001
2nd = 069.60006.0001
PWR_VCORE_PHASE1 PR4655
[47] PWR_VCORE_PHASE1
27K4R2F-GP
PWR_VCORE_LGATE1
[47] PWR_VCORE_LGATE1
1
PWR_VCORE_UGATE2 20200221(DVT1)
[47] PWR_VCORE_UGATE2 changes to 2K 1 2 PWR_VCORE_BOOT2_N1 2
B PWR_VCORE_PHASE2 20200227(DVT1) PR4611 B
[47] PWR_VCORE_PHASE2 change back to1.3K 0R0603-PAD-7-NP-GP PC4611
PWR_VCORE_LGATE2 SCD22U25V2KX-4-GP
[47] PWR_VCORE_LGATE2 5V_S5
1
1
PR4615 PR4668
1K5R2F-2-GP DY 0R2J-2-GP
PWR_VCORE_ISEN2 PWR_VCORE_ISEN2
[47] PWR_VCORE_ISEN2
PWR_VCORE_COMP_N 2
2
PC4608
1
PWR_VCORE_ISEN1
SC82P50V2JN-3-DL-GP
[47] PWR_VCORE_ISEN1 PWR_VCORE_ISEN1

PWR_VCORE_ISUMP
[47] PWR_VCORE_ISUMP
2
PWR_VCORE_ISUMN PWR_VCORE_ISUMP
[47] PWR_VCORE_ISUMN
1
1
PR4614 PR4613 PR4612
2K87R2F-1-GP
2KR2F-3-GP 392R2F-GP PC4614 PC4618 PR4653
1
1 2PWR_VCORE_ISUMP_N
SCD022U16V2KX-3DLGP
SCD022U16V2KX-3DLGP
PC4602 2K61R2F-1-GP
SCD1U16V2KX-3DLGP
PC4607 PC4623 PR4629 PR4630
1PWR_VCORE_FB1 2
PWR_VCORE_FB4 2
1PWR_VCORE_FB2 2
VCCCORE_SENSE
SCD01U25V2KX-3DLGP
PR4628 0R0402-PAD-7-NP-GP 11KR2F-L-GP
2
1
1
1 2 PWR_VCORE_ISUMN_N 1 2 PC4616 PWR_VCORE_ISUMNP_2
2
2
SCD022U16V2KX-3DLGP
2
PR4667 SC2200P50V2KX-2DLGP 3K48R2F-GP
2
2
0R0402-PAD-1-GP PR4650
PR4640
NTC-10K-29-GP-U
69.60011.201 B=3370
1
100R2F-L1-GP-U 2nd = 69.60013.131

1 2 PR4627
1V_CPU_CORE
PC4606 PC4604 511R2F-2-GP
1
SC820P50V2KX-1-DL-GP 1 2 PWR_VCORE_ISUMN
SC220P50V2KX-3DLGP
PC4615 PR4666
2
1
SCD01U25V2KX-3DLGP 0R0402-PAD-1-GP
1 2 PWR_VCORE_FB3 2 DY 1 1 2 VSSCORE_SENSE PC4603
PR4665 SCD01U25V2KX-3DLGP
2
0R0402-PAD-7-NP-GP 20200212
Change to 0.1u 25V
1
PC4638
1
1
PC4605 PR4626
SC330P50V2KX-3-DL-GP 100R2F-L1-GP-U
2
A A
<Core Design>
Wistron Corporation
Title
Title
POWER (95869_CPUCORE(1/3))
Size
Size Document
DocumentNumber
Number Rev
Rev
A2
Cyborg TGL SC
Date: Sheet 46
Sheet of 105
5 4 3 2 1
5 4 3 2 1
Main Func = VCCIN

20200414 19V_DCBATOUT
19V_DCBATOUT
For acoustic low noice For acoustic noice
OFFPAGE
20200414
1
1
1
PC4702 PC4703 PC4704 PC4705 PC4706
TC4701
For spacing using TC4701 only
SC10U25V3MX-5-GP
SC10U25V3MX-5-GP
SC10U25V5KX-DL-GP
SC10U25V3MX-5-GP
SCD1U25V2KX-1-DL-GP
PWR_VCORE_UGATE1 ST100U25VDM-1-GP
2
[46] PWR_VCORE_UGATE1 077.C1071.0071
2
PWR_VCORE_PHASE1
[46] PWR_VCORE_PHASE1 077.C1071.0101
PWR_VCORE_LGATE1
TGL_U42 28W
D Performance D
[46] PWR_VCORE_UGATE2
PWR_VCORE_UGATE2
PWR_VCORE_PHASE2
TDC=43A
[46] PWR_VCORE_PHASE2
PWR_VCORE_LGATE2 PWR_VCORE_LGATE1 ICCMAX=65A
Cyntec 6.8mmx7.6mmx3.0mm 1V_CPU_CORE
DCR: 0.9m ohm +/-7%
PWR_VCORE_ISEN2 Idc : 38A , Isat : 45A
10
[46] PWR_VCORE_ISEN2 PU4701
PWR_VCORE_ISEN1 S2
PL4701
[46] PWR_VCORE_ISEN1 PWR_VCORE_UGATE1 1 G1 G2 8 IND-D15UH-33-GP
PWR_VCORE_ISUMP
[46] PWR_VCORE_ISUMP PWR_VCORE_PHASE1 2
Q1
S1/D2
Q2
D2/S1 7 PWR_VCORE_PHASE1 1 2
PWR_VCORE_ISUMN
[46] PWR_VCORE_ISUMN 3 6
D1 D2/S1
068.R1510.1171
2nd = 068.R1510.1141
1
4 D1 D2/S1 5
19V_DCBATOUT
1
D1
DY PR4705
2
AOE6932-GP 2D2R6J-3-GP PT4701
9
075.06932.0A73 PG4711 PG4712 ST330U2D5VBM-1-GP
2
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP 80.3371V.A2L
2nd = 075.16038.0073 PWR_VCORE_SNB1 2nd = 77.23371.34L
1
4ZA_CPU CORE
1
19V_DCBATOUT PC4710
DY SC1KP50V2KX-1DLGP
PWR_VCORE_ISUMP_GA
2
K
PWR_VCORE_ISUMN_GA
PD4701
AZ4024-01L-R7G-GP
DY PWR_VCORE_ISEN1 1 2
A
1
PR4721 PR4722
100KR2F-L1-GP PR4709 100KR2F-L1-GP
C
PWR_VCORE_ISUMP 1 2
10R2F-L-GP DY C
2
PR4708
3K65R2F-1-GP
19V_DCBATOUT PWR_VCORE_ISUMN
20200414
For acoustic low noice
K
19V_DCBATOUT PWR_VCORE_ISEN2
PD4702
AZ4024-01L-R7G-GP
DY
A
1
PC4714 PC4715 PC4716 PC4717 PC4718
SC10U25V3MX-5-GP
SC10U25V3MX-5-GP
SC10U25V3MX-5-GP
SC10U25V3MX-5-GP
SCD1U25V2KX-1-DL-GP
2
2
PWR_VCORE_LGATE2
Cyntec 6.8mmx7.6mmx3.0mm
DCR: 0.9m ohm +/-7%
teknisi indonesia
Idc : 38A , Isat : 45A
10
1V_CPU_CORE
PU4702
S2
PL4702
PWR_VCORE_UGATE2 1 G1 G2 8 IND-D15UH-33-GP
Q1 Q2
PWR_VCORE_PHASE2 2 S1/D2 D2/S1 7 PWR_VCORE_PHASE2 1 2
3 D1 D2/S1 6 068.R1510.1171
2nd = 068.R1510.1141
1
4 D1 D2/S1 5
19V_DCBATOUT
D1
DY PR4714
2
AOE6932-GP 2D2R6J-3-GP
9
B B
075.06932.0A73 PG4713 PG4714
2
2nd = 075.16038.0073 GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP
PWR_VCORE_SNB2
1
4ZA_CPU CORE
1
PC4713
DY SC1KP50V2KX-1DLGP
PWR_VCORE_ISUMP_GB
2
PWR_VCORE_ISUMN_GB
PWR_VCORE_ISEN2 1 2
PR4723
100KR2F-L1-GP
1
PWR_VCORE_ISUMP 1 2 PR4724
PR4715 100KR2F-L1-GP
PR4716 10R2F-L-GP DY
3K65R2F-1-GP
2
PWR_VCORE_ISUMN
PWR_VCORE_ISEN1
A A
<Core Design>
Wistron Corporation
Title
Title
POWER (95829_CPUCORE(2/3))
Size
Size Document
DocumentNumber
Number Rev
Rev
A2
Cyborg TGL SC
Date:
Sheet 47 of 105
5 4 3 2 1
5 4 3 2 1
Main Func = CPU_CORE
D D
C C
B B
<Core Design>
A A
Wistron Corporation
Title

A3
SC
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
<Core Design>
Wistron Corporation
A Taipei Hsien 221, Taiwan, R.O.C. A
Title
(RSVD)
A Cyborg TGL SC
5 4 3 2 1
5 4 3 2 1
20200414
Main Func = VCCIN_AUX For acoustic low noice
19V_DCBATOUT 19V_DCBATOUT
19V_DCBATOUT For acoustic noice

OFFPAGE
20200414
1
K
1
1
FC5001 PC5006 PC5007 PC5012 PC5013
TC5001
VID For spacing using TC4701 only
SC33P25V1JN-GP
SC10U25V3MX-5-GP
SC10U25V3MX-5-GP
SC10U25V3MX-5-GP
SC10U25V3MX-5-GP
DY PD5001
ST100U25VDM-1-GP
AZ4024-01L-R7G-GP
2
077.C1071.0071
2
1 2 PWR_VCCIN_AUX_VID0 083.04024.0AA1
[22,40] CORE_VID0 2nd = 83.PJSD2.0AF 2nd = 077.C1071.0101
A
PR5014
0R0402-PAD-7-NP-GP
D 1 2 PWR_VCCIN_AUX_VID1 D
[22,40] CORE_VID1
PR5015
0R0402-PAD-7-NP-GP
TGL_U42 28W
Performance
[40,53] PWR_1D8V_PG
PWR_VCCIN_AUX_BOOT
PC5009
SC1U10V2KX-1DLGP
2 1
TDC=14A
ICCMAX=27A
PR5024 PC5005
32.4A<OCP<37.8A
VCCIN_AUX SENSE 19V_DCBATOUT
2D2R3-1-U-GP
1 2
SCD1U25V2KX-1-DL-GP
1 2
PR5012
10
0R2J-2-GP PR5002 PU5001 1D8V_CPU_AUX
PWR_VCCIN_AUX_FB_O 2 1 1D8V_CPU_AUX
DY 118KR2F-1-GP
BOOT
5V_S5 1 2 PWR_VCCIN_AUX_CS 1 20 PWR_VCCIN_AUX_VSYS 19V_DCBATOUT
3D3V_S5 CS_DIS VSYS
Cyntec. 6.8 x 7.3 x 3mm
PU5002 PU5003
[22] VCCAUX_SENSE
2 1 PWR_VCCIN_AUX_FB_O PR5001 2 2 DCR: 2.5~2.8 mOhm
PR5017 2D2R2J-GP
UG
11 PWR_VCCIN_AUX_UG 3 3 Idc : 23A , Isat : 40A
1
0R0402-PAD-7-NP-GP 2 1 PWR_VCCIN_AUX_VCC 15 1 4 4 1
PVCC 10 10 PL5001
PR5004
1
10KR2J-3-GP PC5008 12 PWR_VCCIN_AUX_LX 9 9 1 2
2 1 PWR_VCCIN_AUX_RGND SC1U10V2KX-1DLGP 16 PH 7 7
[22] VSSAUX_SENSE VCC 8 6 6 8
PR5018 IND-D22UH-37-GP
2
13 PWR_VCCIN_AUX_LG 5 5
0R0402-PAD-7-NP-GP
LG 68.R2210.10V
1
VCCIN_AUX_PWRGD 4
PG 2nd = 068.R2210.1141
PG5005
14 GAP-CLOSE-PWR-3-GP
PWR_1D8V_PG 1 2 PWR_VCCIN_AUX_EN 19 PGND FDMS3600-02-RJK0215-COLAY-GP FDMS3600-02-RJK0215-COLAY-GP
EN
2
PR5005 075.07321.0073 075.07321.0073
1
2 PWR_VCCIN_AUX_ISENP
C 2D2R2J-GP PC5010
ISENSEP 2nd = 075.36304.0073 2nd = 075.36304.0073 C
1
PWR_VCCIN_AUX_ISENP_A
PG5006
GAP-CLOSE-PWR-3-GP
PR5007
100R2F-L1-GP-U
SC1U10V2KX-1DLGP
PWR_VCCIN_AUX_VID1 17 4ZA_AUX 4ZA_AUX
PT5001
VID1
1
3 PWR_VCCIN_AUX_ISENN ST330U2D5VBM-1-GP
ISENSEN
2
PR5021 80.3371V.A2L
2
PWR_VCCIN_AUX_VID0 18 5K36R2F-GP 2nd = 77.23371.34L
VID0 8 PWR_VCCIN_AUX_FB_O PC5011
VOUT SCD1U25V2KX-1-DL-GP
2
2 1
5 PWR_VCCIN_AUX_COMP
PR5003 COMP PR5008 PR5022
2 1 PWR_VCCIN_AUX_FSW 9
DY FSWSEL 6 PWR_VCCIN_AUX_FB 1
267R2F-1-GP
2 PWR_VCCIN_AUX_RC 1
866R1F-GP
2
10KR2J-3-GP FB
PWR_VCCIN_AUX_RGND
AGND
7
RGND
PR5023
RT6543AGQW-GP NTC-10K-29-GP-U
21
074.06543.0073 1 2
PWR_VCCIN_AUX_FB_O
B=3370K
69.60011.201
2nd = 69.60013.131
PC5003 PR5011 PC5002 PR5009

SC2200P50V2KX-2DLGP 10KR2F-2-GP SC470P50V2KX-3DLGP 1K6R2F-GP
1 2 PWR_VCCIN_AUX_COMP_R 1 2 2 1 PWR_VCCIN_AUX_FB_R 2 1
DY
DY
PC5004 PR5010
SC22P50V2JN-4DLGP 5K62R2F-GP
2 1 2 1
1
B
DY PC5020
B
SCD1U25V2KX-1-DL-GP
PR5006
2
100R2F-L1-GP-U
2 1
A A
<Core Design>
Wistron Corporation
Title
Title
RT6543A_VCCIN_AUX
Size
Size Document
DocumentNumber
Number Rev
Rev
A2
SC
Date: Sheet
Sheet 50 of 105
5 4 3 2 1
5 4 3 2 1
19V_DCBATOUT
OFFPAGE OFFPAGE_GAP 19V_DCBATOUT
PC5102 PC5105 PC5101
1
K
SCD1U25V2KX-1-DL-GP
SC10U25V5KX-DL-GP
SC10U25V5KX-DL-GP
S5
D D
PD5101
SIO_SLP_S4# AZ4024-01L-R7G-GP
2D5V
2
[17,66] SIO_SLP_S4#
2
DY
Design Current : 0.105A
A
PWR_VDDQ_V2P5
S3 murata. 2.5 x 2.0 x 1.2 mm

VTT_CNTL
[5] VTT_CNTL 5V_S5 DCR:240mOhm
Idc : 1.3A , Isat : 1.5 A
1
PC5137 PC5126 FC5101
PH on EE Side
SC33P25V1JN-GP
1
PR5107
2
PC5118 put as close as PU5101 pin14
1
PL5102
2
DY DY
2
IND-4D7UH-352-GP
0R0402-PAD-1-GP PC5118
1D2V_VTT_PWRGD
PC5136 068.4R710.1111
1
1 2
SCD1U25V2KX-1-DL-GP
SC10U6D3V3MX-DL-GP
[40] PWR_VDDQ_PG R5101 2nd = 068.4R710.1981
0R0402-PAD-7-NP-GP PR5117
1D2V_S3
2
1 2 PU5101
0R0402-PAD-1-GP
PC5135 7
PVIN
SW_VPP
15 PWR_VDDQVPP_PH
PWR_VDDQVPP_SENSE
PR5118
0R0402-PAD-1-GP TDC=9.6A
1
12 1 2
SC1U10V2KX-1DLGP
3D3V_S5
PWR_VDDQ_VLDOIN
PWR_VDDQ_PVIN 14
PVIN_VPP
VPPSNS
PR5111
5D1R3F-GP
PC5110
SCD1U25V2KX-1-DL-GP Cyntec. 6.6 x 7.3 x 3.0 mm
ICCMAX=6.72A
2
PWR_VDDQ_BOOT PWR_VDDQ_BOOTA
11.52A<OCP<15.36A
18 1 2 2 1
PWR_VDDQ_VCC BST DCR: 4.8m~5.3 mOhm
1
PC5134 13
PR5116 SC10U6D3V3MX-DL-GP VCC_5V 17 PWR_VDDQ_PH Idc : 16 A , Isat : 17 A
100KR2J-1-GP DY PC5135 put as close as PU5101 pin13 SW
2
5 PWR_VDDQ_SENSE PL5101 1D2V_S3
C PWR_VDDQ_VLDOIN 1 VDDQSNS C
VLDOIN
2
2 1 2
1D2V_VTT_PWRGD 8 VTT COIL-D68UH-9-GP
PGOOD 4
SIO_SLP_S4# VTTSNS 68.R6810.20J
1
11 2nd = 068.R6810.1271
SLP_S4 PWR_VDDQ_VTTREF
1
6 20191219 PR5110 PC5106 PC5107 PC5109 PC5113 PC5108
VTTREF For high limit PWR_VDDQVTT
VTT_CNTL 10
DY 2D2R6J-3-GP 3rd = 068.R6810.1651 DY
VTT_CNTL
2
16
PGND_VPP
2
1
PC5127
3 9 PWR_VDDQ_SNB
SC1U10V2KX-1DLGP
AGND PGND
1
PC5130 DY PC5128
2
PR5113
1
TPS51486RJER-GP DY PC5115 0R0402-PAD-1-GP SC22U6D3V3MX-1-DL-GP
2
074.51486.0043 SC1500P50V2KX-2-DL-GP SC22U6D3V3MX-1-DL-GP
2
SC10U6D3V3MX-DL-GP SC22U6D3V3MX-1-DL-GP
SC10U6D3V3MX-DL-GP
put as close as PU5101 pin2
put as close as PU5101 pin6

VTT
Design Current : 0.42A
B B
1D2V_S3 PWR_VDDQ_VLDOIN
PG5115
GAP-CLOSE-PWR-3-GP
1 2
VTT
0D6V_VREF_S0 PWR_VDDQVTT
1 2
PG5111
GAP-CLOSE-PWR-3-GP
A A
2D5V <Core Design>
2D5V_S3 PWR_VDDQ_V2P5
Wistron Corporation
PG5118 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
2 1 Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
GAP-CLOSE-PWR-3-GP
051_POWER (TPS51486R_VDDQ/VTT)
Size Document
Size Document Number
Number Rev
Rev
Custom
Cyborg TGL SC
Date: Sheet 51
Sheet of 105
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Regulator_1D0V
D D
C C
B B
<Core Design>
A A
Wistron Corporation
Title
POWER (AOZ2262Q_1D0V)
A3 Cyborg TGL SC
5 4 3 2 1
5 4 3 2 1
Main Func = 1D8V/1D2V

TDC=1.029A
ICCMAX=1.47A
OFFPAGE OFFPAGE_GAP 3D3V_S5 1.764A<OCP<2.352A
Chilisin. 2.5mm×2.0mmX1.2mm PWR_1D8V
1
3D3V_S5 PWR_1D8V_VIN
PU5301 DCR: 59m Ohm
D
PR5308 PG5301 Idc : 3 A , Isat : 4A D
9
PH on EE Side 10KR1J-GP GAP-CLOSE-PWR-3-GP
1 2
PWR_1D8V_VIN
PGND PL5301 068.1R010.1281
2
4 5 IND-1UH-300-GP
[24] PRIM_PWRGD 1 2 PWR_1D8V_PG PG5302 PWR_1D8V_VIN 3 PGND NC#5 6 PWR_1D8V_PH 1 22nd = 068.1R010.1131
PR5307 GAP-CLOSE-PWR-3-GP PWR_1D8V_PG 2 VIN LX 7 PWR_1D8V_EN
PG EN
1
0R0201-PAD-GP 1 2 1 8
FB SGND PC5302 PC5303
1
PC5301 PR5309
R1 DY
1
SC22U6D3V3MX-1-DL-GP 3D3V_S5 100KR1F-GP
20191112 modify RT5797ALGQW-GP PC5305
2
1
SC22P50V2JN-L-GP
Follow Nakia change to P.40 074.05797.0073
2
20191120 PR5305 2nd = 074.08883.0043
1D8V_S5 PWR_1D8V 100KR1J-GP PWR_1D8V_FB
add offpage net
PG5303
DY
1
GAP-CLOSE-PWR-3-GP
2
2 1
PWR_1D8V_EN
PR5304
49K9R2F-L-GP R2
[40] PWR_1D8V_EN
2
PG5304 PWR_1D8V_EN
GAP-CLOSE-PWR-3-GP
20191125
Follow Upsell 2 1 Vo=0.6x(1+R1/R2)
1
PC5307
PWR_1D8V_PG =0.6x(1+100/49.9)
C [40,50] PWR_1D8V_PG DY SC1U10V2KX-1DLGP C
=1.802V
2
PG5305
GAP-CLOSE-PWR-3-GP
2 1
PWR_1D8V_VIN
K
PD5301
AZ4024-01L-R7G-GP
DY
A
B B
<Core Design>
Wistron Corporation
A A

Title
Title
LCD&CAM&DMC&Touch
Size
Size Document
DocumentNumber
Number Rev
Rev
B
Cyborg TGL SC
Date:
Sheet 53 of 105
5 4 3 2 1
5 4 3 2 1
Main Func = 1D05V
OFFPAGE
PH on EE Side
OFFPAGE-GAP
20191119
Check with UPSELL and Nakia
follow which one
D VCCIN_AUX_PWRGD PW R_VNN_EN 3D3V_S5
D
[40] PW R_VNN_EN
PR5420 1 DY 2 PW R_VNN1D05V_PG
100KR2J-1-GP
1D05V_BP_PWRGD PW R_VNN1D05V_PG
PW R_VNN 1D05V_VNN_BYPASS
[24,40] PW R_VNN1D05V_PG TDC=0.28A

Murata. 2.7mm×2.2mmX1.2mm
R5499 1 2 0R2J-2-GP DCR: 59m Ohm ICCMAX=0.4A
BYPASS Idc : 3A , Isat : 3A 0.48A<OCP<0.64A
PL5401 068.1R010.1281 PW R_VNN
PW R_1D05V_EN IND-1UH-300-GP
[40] PW R_1D05V_EN
PW R_1D05V 1D05V_S5_BYPASS 1 BYPASS22nd = 068.1R010.1131
PH on EE Side
1
R5498 1 2 0R2J-2-GP PC5411 PC5412
BYPASS BYPASS BYPASS
1D05V_BYPASS_CTRL 10/11 change PU5401 to APW8743C
2
2 SC1U10V2KX-1DLGP
PC5401 1BYPASS
PW R_VNN1D05V_VID2
[40] PW R_VNN1D05V_VID2 PR5413 1 2D2R2F-GP
5V_S5 BYPASS2
PU5401 Murata. 2.7mm×2.2mmX1.2mm

PM_SLP_S3# PW R_VNN1D05V_VID1
PC5402 SC4D7U25V3KX-2-GP
PW R_VNN1D05V_VCC PW R_VNN_EN DCR: 460m Ohm
[40] PW R_VNN1D05V_VID1 1 BYPASS
2 8 15
C VCC EN1 6 PW R_1D05V_EN Idc : 0.85A , Isat : 1A PW R_1D05V C
PW R_VNN1D05V_VINA 11 EN2
1 PR5422 2 0R0402-PAD-1-GP
PW R_VNN1D05V_VINB 10 VIN1 PW R_VNN1D05V_PHA PL5402 68.1001S.10K
1 PR5410 2 0R0402-PAD-1-GP 1
19V_DCBATOUT VIN2 LX1 4 PW R_VNN1D05V_PHB 1
2nd = 068.10010.1341
1 BYPASS
2
BYPASS
LX2 BYPASS2
1
PC5403 SC4D7U25V3KX-2-GP PW R_VNN1D05V_VID1 13 5 PW R_VNN1D05V_FB2
VID1 VOUT2 IND-10UH-330-GP
1
PC5414 PR5408
19V_DCBATOUT 16 PW R_VNN1D05V_VOUT1 0R2J-2-GP
DY BYPASS
SC100P50V2JN-3GP
PW R_VNN1D05V_BOOTA_A PC5404 1 2SCD1U25V2KX-1-DL-GPPW R_VNN1D05V_BOOTA 2 VOUT1
BYPASS BOOT1
2
PW R_VNN1D05V_BOOTB_A PC5405 1 2SCD1U25V2KX-1-DL-GPPW R_VNN1D05V_BOOTB 3
BYPASS BOOT2
1
17 PC5410 PC5413
AGND
K
PR5419 BYPASS BYPASS
PD8604 PW R_VNN1D05V_VID2 14 9 1 2
VID2 PGND PW R_VNN
2
PC5406 1 PW R_VNN1D05V_PG
AZ4024-01L-R7G-GP DY 2 SCD1U16V2KX-L-GP 7
POK PGND
12 PR5407
DY 0R0402-PAD-1-GP DY 0R2J-L-GP
2
A
PR54231 2 0R2F-1-GP PW R_VNN1D05V_PHB APW 8743CQBI-TRG-GP

BYPASS PR5430
1
074.08743.0A73 DY 0R2J-L-GP
PR5401 1 BYPASS2 0R0402-PADPW R_VNN1D05V_PHA
1
3D3V_S5 3D3V_S5 TDC=0.28A
ICCMAX=0.4A
PR5426 0.48A<OCP<0.64A
10KR1J-GP
B 1 DY 2 PW R_VNN1D05V_VID1 B
PR5427
10KR1J-GP
1 DY 2 PW R_VNN1D05V_VID2
1
1
PR5433
10KR2F-2-GP
BYPASSBYPASS
PR5428
10KR2F-2-GP
2
2
A A
<Core Design>
Wistron Corporation
Title
Title
POWER(APW8738A_VNN1D05)
Size
Size DocumentNumber
Document Number Rev
Rev
A3 Cyborg TGL SC
Date: Sheet
Sheet 54 of 105
5 4 3 2 1
5 4 3 2 1
Main Func = LCD INVERTER POWER 44
42
40
5V_IRLED
39
3D3V_HINGE_S0 CCD_USB20_CON_N 38
From CPU CCD_USB20_CON_P 37
Camera 36
[4] eDP_TX_CPU_N0
[4] eDP_TX_CPU_P0
19V_DCBATOUT 19V_DCBATOUT_LCD_R 19V_DCBATOUT_LCD
3D3V_S0
Camera & DMIC IR_CAM_DET# 35
DMIC_SDA_EDP 34
DMIC_SCL_EDP 33
[4] eDP_TX_CPU_N1
[4] eDP_TX_CPU_P1
1 2 2
F5503
1 DMIC 32
SENSOR_I2C_SDA SENSOR_I2C_SDA_R
1
R5565 R5574 1 2
2IN1 0R0201-PAD-GP 31
SENSOR_I2C_SCL 1 2 SENSOR_I2C_SCL_R 30
0R1206-DB-GP C5512 C5513 C5514 R5517 R5518
Sensor Board GSEN_INT1_C
R5573 2IN1 0R0201-PAD-GP GSEN_INT1_C_R
1
1 2 29
SCD1U25V2KX-1-DL-GP
SC1KP50V2KX-1DLGP
SC10U25V5KX-DL-GP
POLYSW-1D1A24V-GP-U 4K7R2J-2-GP 4K7R2J-2-GP R5575 2IN1 0R0201-PAD-GP
69.50007.A31 TS_I2C TS_I2C 28
3D3V_HINGE_S0 DBC_PANEL_EN 2 100R2J-2-GP DBC_EN_R
2nd = 69.50007.G71 R5504 1 27
2
LCD_CBL_DET# 26
PCH_I2C0_SCL_TS eDP_TX_CPU_N1 C5523 1 2SCD1U16V2KX-3DLGP eDP_TX_CON_N1 25
PCH_I2C0_SDA_TS eDP_TX_CPU_P1 C5522 1 2SCD1U16V2KX-3DLGP eDP_TX_CON_P1 24
23
eDP_TX_CPU_N0 C5525 1 2SCD1U16V2KX-3DLGP eDP_TX_CON_N0 22
eDP eDP_TX_CPU_P0 C5524 1 2SCD1U16V2KX-3DLGP eDP_TX_CON_P0 21
D eDP_AUX_CPU_P C5526 1 2SCD1U16V2KX-3DLGP eDP_AUX_CON_P 20 D
eDP_AUX_CPU_N C5521 1 2SCD1U16V2KX-3DLGP eDP_AUX_CON_N 19
[4] eDP_AUX_CPU_P
[4] eDP_AUX_CPU_N 18
Trace width = 80mil 17
3D3V_LCDVDD_S0 LCD_TST_C
C5546 16
[4] EDP_HPD
1
C5558 SC1U10V2KX-1DLGP 15
EDP_HPD_CONN 14
SC22U6D3V3MX-1-DL-GP DY C5538
SCD1U16V2KX-3DLGP Display 13
[4] eDP_VDD_EN
2
BLON_OUT_C 12
[4] L_BKLT_CTRL LCD_BRIGHTNESS 11
TOUCH_PANEL_DET# R5570 1 2 0R0201-PAD-GP TOUCH_PANEL_DET#_R 10
From EC 9
5V_3D3V_TOUCH_S0 TOUCH_REPORT_SW R5568 1 2 0R0201-PAD-GP TOUCH_REPORT_SW_R 8
PCH_I2C0_SCL_TS R5567 1 2 0R0201-PAD-GP CPU_I2C_SCL_TS_R 7
[24] PANEL_BKEN PCH_I2C0_SCL_TS 1 Touch PCH_I2C0_SDA_TS R5566 1 2 0R0201-PAD-GP CPU_I2C_SDA_TS_R 6
PCH_I2C0_SDA_TS 1 AFTP5504 AFTE14P-GP TOUCH_PANEL_INTR# 5
AFTP5505 AFTE14P-GP TOUCH_PANEL_PD# R5569 1 2 0R0201-PAD-GP TOUCH_PANEL_PD#_R 4
[17,27,40,81] SIO_SLP_S3# 3
DMIC_SDA_EDP
2
1 2
DMIC_SCL_EDP AFTP5509 AFTE14P-GP 19V_DCBATOUT_LCD
[20] LCD_CBL_DET# 1 R5544
AFTP5510 AFTE14P-GP 1
100KR2J-1-GP DY
3D3V_HINGE_S0 1 41
AFTP5511 AFTE14P-GP
1
43
FOR TESTING LCD1
STAR-CON40-8-GP
[20] DBC_PANEL_EN EDP_HPD_CONN 1
[24] LCD_VCC_TEST_EN
DBC_EN_R 1 AFTP5521 AFTE14P-GP
AFTP5522 AFTE14P-GP
020.F0847.0040
3D3V_LCDVDD_S0 1
19V_DCBATOUT_LCD 1 AFTP5523 AFTE14P-GP 2nd = 020.F1427.0040
[24] LCD_TST AFTP5525 AFTE14P-GP
3rd = 20.F2406.040
[24] CABLE2_OCP#
[24] PANEL_MONITOR
D5502
eDP_VDD_EN A K LCDVDD_EN
RB520S30-GP
83.R2003.A8M
2ND = 083.52030.008F
3rd = 083.52030.0C8F
[20,70] SENSOR_I2C_SDA
[20,70] SENSOR_I2C_SCL D5506
[20] GSEN_INT1_C
Hinge up cable protection LCD_VCC_TEST_EN A K
20191023(EVT1) RB520S30-GP
C Follow Dell_CY20 change net name 83.R2003.A8M C
20200420(DVT2) 2ND = 083.52030.008F
Change C5542 to 0402 for layout limit 3rd = 083.52030.0C8F
20200508(DVT2) CABLE1_OCP# 1 2 CABLE2_OCP# D5503
Change U5501 to 074.02895.0A73 R5527 BAT54C-12-GP RN5501
L_BKLT_CTRL
CABLE2_OCP#
0R0402-PAD-7-NP-GP
1 2
Brightness 1
PANEL_BKEN 1
SRN100J-3-GP
4 BLON_OUT_C
R5528 3 BKLT_CTRL 2 3 LCD_BRIGHTNESS
Main Func = Touch panel 3D3V_S5
U5501
3D3V_LCDVDD_S0
CABLE3_OCP#
0R0402-PAD-7-NP-GP
1 2
EC (BIST MODE) LCD_TST 2
R5505 75.00054.A7D
LCD_TST LCD_TST_C
1
C5505 5V_S5 1 10 0R0402-PAD-7-NP-GP 2nd = 75.00054.T7D 1 4

LCDVDD_EN 2 IN1 OUT1 9 CABLE1_OCP# CABLE4_OCP# 1 2 EDP_HPD 2 3 EDP_HPD_CONN
SC4D7U6D3V2MX-1-GP
3 EN1 FLAG1 8 R5506 LCDVDD_EN

VB GND
2
SIO_SLP_S3# 4 7 CABLE2_OCP# 0R0402-PAD-7-NP-GP RN5503

[20] PCH_I2C0_SDA_TS EN2 FLAG2 3D3V_HINGE_R
1
2
3
4
3D3V_S5 5 6 SRN100J-3-GP
[20] PCH_I2C0_SCL_TS IN2 OUT2
1
C5542
11
SC1U10V2KX-1DLGP
RN5502
THERMAL_PAD SRN100KJ-5-GP
2
C5543 20210114
SC4D7U6D3V2MX-1-GP
G2895BLK21U-GP Remove shortpad
8
7
6
5
[20] TOUCH_PANEL_INTR# 074.02895.0A73
2
[24] TOUCH_REPORT_SW 2nd = 074.05206.0093
3D3V_HINGE_S0
[3] TOUCH_PANEL_DET#
[3] TOUCH_PANEL_PD# 3D3V_HINGE_R 1 2

R5564
0R1206-DB-GP
3D3V_HINGE_R 5V_3D3V_TOUCH_S0
1
1
1
TOUCH_WM
R5501 1 2 0R2J-2-GP
C5557
DY C5544
DY
C5545
DY PANEL_PWRGD CIRCUIT
SC1U25V3KX-1-DLGP
2
2
SCD1U16V2KX-3DLGP
5V_TPAN_VDD
84.T3906.E11
2 1 Q5503_E
TOUCH_CBG 19V_DCBATOUT 2nd = 84.T3906.I11
R5551
R5502 1 2 0R2J-2-GP 0R0402-PAD-7-NP-GP 3rd = 084.03906.0B11 3D3V_S5
E
Q5503_B B Q5502 4th = 084.03906.0C11
LMBT3906LT1G-1-GP
2
R5547
C
100KR2F-L1-GP
19V_DCBATOUT_LCD Q5503_C
1
B R5554 B
5V_S5 5V_S5 10KR2F-2-GP R5546
1
5V_IRLED U5502 4K7R2F-GP PANEL_PWRGD_R 2 R5545 1PANEL_MONITOR
R5503 0R0402-PAD-7-NP-GP
D5504
1
10 1 100KR2J-1-GP R5549 C5529
C
1
2
CABLE3_OCP# 9 OUT1 IN1 2 TP_PWR_EN 2 1 SIO_SLP_S3# A KDCBATOUT_LCD_PWRGD Q5505 1MR2F-GP SCD1U16V2KX-3DLGP
FLAG1 EN1 DCBATOUT_LCD_PG
1
C5504 5V_TPAN_VDD 8 3 TOUCH_CBG B LMBT3904LT1G-GP
2
GND VB
1
CABLE4_OCP# 7 4 RB520S30-GP
SC4D7U6D3V2MX-1-GP
FLAG2 EN2
C5560 C5528 R5555 C5531 84.T3904.H11
6 5
SCD1U25V2KX-1-DL-GP
IR CAP 83.R2003.A8M 200KR2F-L-GP SC2200P50V2KX-2DLGP 2nd = 084.03904.0I11
SCD1U16V2KX-3DLGP
2
1
OUT2 IN2
E
2ND = 083.52030.008F 3rd = 084.03904.0H11
1
2
11 DY 3rd = 083.52030.0C8F 4th = 84.03904.T11
THERMAL_PAD
TOUCH_CBG
SC4D7U6D3V2MX-1-GP
C5501
2
1
G2895BLK21U-GP
074.02895.0A73
2
C5561 C5562
SCD1U16V2KX-3DLGP
2nd = 074.05206.0093
SC1U10V2KX-1DLGP
TOUCH_CBG
TOUCH_CBG
2
TOUCH_CBG 2 1 Q5505_E
3D3V_S0 84.T3906.E11
R5550 2nd = 84.T3906.I11
1
0R0402-PAD-7-NP-GP 3rd = 084.03906.0B11 Gen 10 LCD-BIST
E
Q5504_B B 4th = 084.03906.0C11 Check if 3V and B+ is power on before doing
Q5501
LMBT3906LT1G-1-GP panel self-test. It’s using for judge MB or panel
damaged.
C
Q5504_C
MIC POWER CAMERA POWER SENSOR POWER TOUCH PANEL POWER
1
R5553 R5561
3D3V_LCDVDD_S0 10KR2F-2-GP 4K7R2F-GP
3D3V_HINGE_S0 5V_3D3V_TOUCH_S0 D5505
3D3V_HINGE_S0 3D3V_HINGE_S0
C
1
2
A K LCDVDD_PWRGD
LCDVDD_PG B
1
1
C5530 R5552 C5535 Q5504
C5550 C5555 C5551 RB520S30-GP 200KR2F-L-GP SC2200P50V2KX-2DLGP LMBT3904LT1G-GP
1
C5552
SCD1U16V2KX-3DLGP
C5556
1
C5549 84.T3904.H11
1
SC4D7U6D3V2MX-1-GP
E
1
SC4D7U6D3V2MX-1-GP
1
SC33P50V2JN-3GP
DY DY 83.R2003.A8M
SC10U6D3V3MX-DL-GP
SCD1U16V2KX-3DLGP
DY 2nd = 084.03904.0I11
2
2
C5548 C5559 2ND = 083.52030.008F
SCD1U25V2KX-1-DL-GP
3rd = 084.03904.0H11
SC10U6D3V3MX-DL-GP
DY DY DY 3rd = 083.52030.0C8F
2
2
2
2
2
4th = 84.03904.T11
SCD1U16V2KX-3DLGP
A Main Func = CAMERA 2020/02/29:swap EL5501

EL5501
2020/02/29:swap RN5505 A
EL5502
CCD_USB20_N 1 2 CCD_USB20_CON_N BLM15AG121SN-1GP 1 2 DMIC_PCH_CLK_Q
BLM15AG121SN-1GP 1 2 DMIC_PCH_DATA_Q
CCD_USB20_P 4 3 CCD_USB20_CON_P EL5503
[19] IR_CAM_DET# DLM0NSN900HY2D-GP

068.09002.2001
2nd = 68.02002.061 DMIC_SCL_EDP 2 3 DMIC_SCL_CODEC
[16] CCD_USB20_N
DMIC_SDA_EDP DMIC_SDA_CODEC
1
[16] CCD_USB20_P 1 4
ED5502
AZ5315-02F-GP RN5504 <Core Design>
DY SRN33J-5-GP-U
[27] DMIC_SCL_CODEC C5553 C5554
DY_DMICtoCODEC
[27] DMIC_SDA_CODEC
Wistron Corporation
1
1
SC33P50V2JN-3DLGP
SC33P50V2JN-3DLGP
3

[19] DMIC_PCH_CLK_Q Taipei Hsien 221, Taiwan, R.O.C.
2
[19] DMIC_PCH_DATA_Q Title

Title
Size
LCD&CAM&DMC&Touch
Document Number Rev
Custom
Date:
Cyborg TGL Sheet
SC
5 4 3 2 1
5 4 3 2 1
Main Func = CRT
D D
C C
B B
A <Core Design> A
Wistron Corporation
Title
CRT(Reserved)
A3
Cyborg TGL SC
5 4 3 2 1
5 4 3 2 1
SSID = HDMI Level Shifter/Connector

HDMI_DDI_TX_N3 C5701 1 2 SCD1U16V2KX-3DLGP HDMI_DDI_TX_CON_N3 F5701 5V_HDMI
HDMI_DDI_TX_P3 C5704 1 2 SCD1U16V2KX-3DLGP HDMI_DDI_TX_CON_P3 5V_S0 POLYSW-1D1A6V-9-GP-U
HDMI_DDI_TX_CON_N0
69.48001.081
[4] HDMI_DDI_TX_N0 HDMI_DDI_TX_N0 C5705 1 2 SCD1U16V2KX-3DLGP HDMI_DDI_TX_CON_N0
HDMI_DDI_TX_P0 HDMI_DDI_TX_CON_P0 20200420(DVT2) 1 2
[4] HDMI_DDI_TX_P0 C5703 1 2 SCD1U16V2KX-3DLGP Change to 180R
[4] HDMI_DDI_TX_N1
1
[4] HDMI_DDI_TX_P1
ER5701
2ND = 69.50011.081
[4] HDMI_DDI_TX_N2 180R2J-1-GP
[4] HDMI_DDI_TX_P2
[4] HDMI_DDI_TX_N3 HDMI_DDI_TX_N1 C5707 1 2 SCD1U16V2KX-3DLGP HDMI_DDI_TX_CON_N1
[4] HDMI_DDI_TX_P3 HDMI_DDI_TX_P1 C5706 1 2 SCD1U16V2KX-3DLGP HDMI_DDI_TX_CON_P1
2
HDMI_DDI_TX_N2 C5708 1 2 SCD1U16V2KX-3DLGP HDMI_DDI_TX_CON_N2
D HDMI_DDI_TX_P2 HDMI_DDI_TX_CON_P2 HDMI_DDI_TX_CON_P0 D
C5709 1 2 SCD1U16V2KX-3DLGP 20191122
[4] HDMI_SCL_CPU Follow Nakia
20191127
[4] HDMI_SDA_CPU For High limit
change back to follow ICL
[4] CPU_DISP_HPDB 5V_S0 HDMI_DDI_TX_CON_N1
R5705 1 2 470R2F-GP
R5759 1 2 470R2F-GP
R5773 1 2 470R2F-GP
1
R5774 1 2 470R2F-GP
R5775 1 2 470R2F-GP ER5702
R5776 1 2 470R2F-GP
180R2J-1-GP
5V_HDMI HDMI CONN
G
R5777 1 2 470R2F-GP
R5778 1 2 470R2F-GP HDMI1
20191218
2
For EMC required 18 15 HDMI_SCL_CON
S D HDMI_PLL_GND +5V_POWER SCL
HDMI_DDI_TX_CON_P1 16 HDMI_SDA_CON
SDA
Q5701 5V_S0
HDMI_DDI_TX_CON_P0 7
C5702
SCD1U16V2KX-3DLGP
EC5711
SCD1U16V2KX-3DLGP
TMDS_DATA0+
1
HDMI_DDI_TX_CON_N0
1
9 13
PJE8408-R1-00001-GP HDMI_DDI_TX_CON_P1 TMDS_DATA0- CEC
4 17
HDMI_DDI_TX_CON_N1 6 TMDS_DATA1+ DDC/CEC_GROUNG 19
084.08408.0031 TMDS_DATA1- HOT_PLUG_DETECT
2
2
HDMI_DDI_TX_CON_N2 HDMI_DDI_TX_CON_P2 1
2nd = 084.00138.0E31 HDMI_DDI_TX_CON_N2 3 TMDS_DATA2+ 14
TMDS_DATA2- RESERVED#14
8
A
TMDS_DATA0_SHIELD
1
D5701 D5702 5
RB520S30-GP RB520S30-GP ER5703 2 TMDS_DATA1_SHIELD
180R2J-1-GP TMDS_DATA2_SHIELD 20
83.R2003.A8M 83.R2003.A8M 11 GND 21
3rd = 083.52030.0C8F 2ND = 083.52030.008F HDMI_DDI_TX_CON_P3 10 TMDS_CLOCK_SHIELD GND 22
2ND = 083.52030.008F 3rd = 083.52030.0C8F
K
TMDS_CLOCK+ GND
2
HDMI_DDI_TX_CON_N3 12 HDMI 23
TMDS_CLOCK- (A_Type) GND
HDMI_DDI_TX_CON_P2
SKT-HDMI23-209-GP
022.10025.0411
HDMI_SDA_R
HDMI_SCL_R
C C
3D3V_S0
HDMI_DDI_TX_CON_N3
Q5703
C
4
3
LMBT3904LT1G-GP
1
B HDMI_HPD_B R5710 1 2 150KR2F-L-GP HDMI_DET_CON
3D3V_S0 RN5702 ER5704
SRN2K2J-1-GP 180R2J-1-GP 84.T3904.H11
1
CPU_DISP_HPDB 1 2 HDMI_HPD_E 2nd = 084.03904.0I11 R5711
1
2
2
R5712
Part Reference = Q5702 0R0402-PAD-7-NP-GP 3rd = 084.03904.0H11 200KR2F-L-GP
1
HDMI_SCL_CPU 4 3 HDMI_SCL_CON HDMI_DDI_TX_CON_P3
R5709
4th = 84.03904.T11
2
5 2
Note:ZZ.27002.F7C01
100KR2J-1-GP
6 1
2
2N7002KDW-1-GP
HDMI_SDA_CPU 75.27002.F7C
2nd = 075.27002.0E7C HDMI_SDA_CON
3rd = 075.07002.0A7C
EMI Request:
HDMI_DDI_TX_CON_P0
HDMI_DDI_TX_CON_N0
HDMI_DDI_TX_CON_P1
HDMI_DDI_TX_CON_N1
HDMI_DDI_TX_CON_P2
HDMI_DDI_TX_CON_N2
HDMI_DDI_TX_CON_P3
HDMI_DDI_TX_CON_N3
HDMI_DET_CON
HDMI_SCL_CON
HDMI_SDA_CON
B B
1
1
ED5704 ED5705 ED5706 ED5707 ED5708 ED5709 ED5710 ED5711 ED5712 ED5713 ED5714
PESD5V0H1BSFYL-GP-U1
2
2
083.5V0H1.00AF 083.5V0H1.00AF 083.5V0H1.00AF 083.5V0H1.00AF 083.5V0H1.00AF 083.5V0H1.00AF 083.5V0H1.00AF 083.5V0H1.00AF 083.5V0H1.00AF 083.5V0H1.00AF 083.5V0H1.00AF
2nd = 083.58017.00AF 2nd = 083.58017.00AF 2nd = 083.58017.00AF 2nd = 083.58017.00AF 2nd = 083.58017.00AF
2nd = 083.58017.00AF 2nd = 083.58017.00AF 2nd = 083.58017.00AF 2nd = 083.58017.00AF 2nd = 083.58017.00AF 2nd = 083.58017.00AF
A A
<Core Design>
Wistron Corporation
Title
Title
HDMI
Size
Custom Document Number Rev
Cyborg TGL SC
5 4 3 2 Date: 1 Sheet
5 4 3 2 1
D D
C C
(Blanking)
B B
<Core Design>
Wistron Corporation
Title
(Reserved)
A4
Cyborg TGL SC
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
<Core Design>
Wistron Corporation
Title
(Reserved)
A4
Cyborg TGL SC
5 4 3 2 1
5 4 3 2 1
Main Func = HDD HDD POWER

HDD
[70] FFS_INT2_Q
For CBG L
5V_S0
[16,60] HDD_DEVSLP 5V_HDD_S0
[16] HDD_SATA_TX_P
[16] HDD_SATA_TX_N
E [16] HDD_SATA_RX_P
80 mils 1 2 E
[16] HDD_SATA_RX_N R6001
0R0805-PAD-NP-GP C6007
1
[16,60] HDD_DEVSLP CBG_L_HDD SCD1U16V2KX-3DLGP
C6008 CBG_L_HDD
SC10U6D3V3MX-DL-GP
[16] HDD_DET#
2
CBG_L_HDD
SATA RE-DRIVER
D D
20201013
Remove
C C
HDD_SATA_TX_P CBG_L_HDD C6001 1 2 SCD01U25V1MX-1-GP HDD2_SATA_TX_CON_P
HDD_SATA_TX_N CBG_L_HDD C6002 1 2 SCD01U25V1MX-1-GP HDD2_SATA_TX_CON_N
HDD_SATA_RX_N CBG_L_HDD C6003 1 2 SCD01U25V1MX-1-GP HDD2_SATA_RX_CON_N
HDD_SATA_RX_P CBG_L_HDD C6004 1 2 SCD01U25V1MX-1-GP HDD2_SATA_RX_CON_P
B B
SATA HDD Connector

HDD1
21
1
22 Layout Note:
HDD2_SATA_TX_CON_P 2
HDD2_SATA_TX_CON_N 3 Place near HDD2
4
HDD2_SATA_RX_CON_N 5 ED6001
HDD2_SATA_RX_CON_P 6 8
7 3
Close to HDD1
HDD_DEVSLP 1 R6002 2 HDD_DEVSLP_R 8 HDD2_SATA_TX_CON_P 1 10 HDD2_SATA_TX_CON_P
0R0402-PAD 9
10 CBG_L_HDD HDD2_SATA_TX_CON_N 2 9 HDD2_SATA_TX_CON_N
11
12 HDD2_SATA_RX_CON_N 4 7 HDD2_SATA_RX_CON_N
13
5V_HDD_S0 HDD2_SATA_RX_CON_P HDD2_SATA_RX_CON_P
14 5 6
A 15 A
16 <Core Design>
17
18
FFS_INT2_Q
HDD_DET#
19 23
AZ1043-04F-R7G-GP
075.01043.0073
Wistron Corporation
20 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
24 DY Taipei Hsien 221, Taiwan, R.O.C.
ACES-CON20-37-GP-U Title
Title
0628 change to commond part
020.F0320.0020
2nd = 020.F1230.0020
SATA IF_HDD/ODD
Size
Size Document
DocumentNumber
Number Rev
Rev
A2
Cyborg TGL SC
Date: Sheet
Sheet 60 of 105
5 4 3 2 1
5 4 3 2 1
Main Func = WLAN 3D3V_S5 3D3V_W LAN
AFTE14P-GP AFTP6101 1 3D3V_W LAN

1 CLK_PCIE_WLAN_REQ#
PCIE 1 2
AFTE14P-GP
AFTE14P-GP
AFTP6105
AFTP6106 1 W IFI_RF_EN_R
R6140 AFTE14P-GP AFTP6107 1 BLUETOOTH_EN_R
1 PCH_PLTRST#
[16] W LAN_PCIE_TX_N
3D3V_W LAN 0R0805-PAD-NP-GP
1.1A AFTE14P-GP
AFTE14P-GP
AFTP6108
AFTP6109 1 BT_USB20_CON_N
[16] W LAN_PCIE_TX_P AFTE14P-GP AFTP6110 1 BT_USB20_CON_P
1
C6110 C6106 C6109 AFTE14P-GP AFTP6111 1 JIO3_PCIE_W AKE#
SCD1U16V2KX-3DLGP
SC10U6D3V3MX-DL-GP
SCD1U16V2KX-3DLGP
[16] W LAN_PCIE_RX_N R6145
[16] W LAN_PCIE_RX_P 10KR2J-3-GP
2
D D
2
PCIE_CLK W LAN_RF_DIS# 2 1 W IFI_RF_EN_R
R6144
0R0402-PAD-7-NP-GP
[18] W LAN_CLK_CPU_N
[18] W LAN_CLK_CPU_P 3D3V_W LAN
[18] CLK_PCIE_WLAN_REQ#
1
R6146
10KR2J-3-GP
USB2.0
2
BT_RADIO_DIS# 2 1 BLUETOOTH_EN_R
[16] BT_USB20_P
R6143
[16] BT_USB20_N
0R0402-PAD-7-NP-GP
Single end
[19] BT_RADIO_DIS#
[16] W LAN_RF_DIS#
[17,62,63,66,71,76,91] PCH_PLTRST# 3D3V_W LAN
C
[18,24] SUSCLK W LAN1 C
Debug 76
76 77
77
74 75
72 3_3VAUX GND 73 CNV_W T_CLKP
70 3_3VAUX RESERVED#73 71 CNV_W T_CLKN
68 RESERVED#70 RESERVED#71 69
66 RESERVED#68 GND 67 CNV_W T_DP0
2 R6106 1 CLKIN_XTAL_LCP_R 64 RESERVED#66 RESERVED#67/2ND_LANE_PERN1 65 CNV_W T_DN0
DY
10KR2J-3-GP 62 GPIO0_NFC_RESET#/MGPIO7 RESERVED#65/2ND_LANE_PERP1 63
60 NFC_I2C_IRQ/MGPIO5 GND 61 CNV_W T_DP1
58 NFC_I2C_SM_CLK RESERVED#61/2ND_LANE_PETN1 59 CNV_W T_DN1
Power EN (Madesimo) W IFI_RF_EN_R
BLUETOOTH_EN_R
56
54
NFC_I2C_SM_DATA
W_DISABLE#1
RESERVED#59/2ND_LANE_PETP1
GND
57
55 JIO3_PCIE_W AKE#
PCH_PLTRST# 52 RESERVED#54/W_DISABLE#2 PEWAKE0# 53 CLK_PCIE_WLAN_REQ#
SUSCLK R6135 1 2 33R2J-2-GP SUSCLK_W LAN 50 PERST0# CLKREQ0# 51
48 SUSCLK_32KHZ GND 49 W LAN_CLK_CPU_N
46 COEX1 REFCLKN0 47 W LAN_CLK_CPU_P
44 COEX2 REFCLKP0 45
42 COEX3 GND 43 W LAN_PCIE_RX_N
40 CLINK_CLK PERN0 41 W LAN_PCIE_RX_P
38 CLINK_DATA PERP0 39
[21] CNV_BRI_DT_R CLINK_RESET GND
CNV_BRI_DT_R 36 37 W LAN_PCIE_TX_CON_N C6107 1 2 SCD1U25V1MX-1-GP W LAN_PCIE_TX_N
[21] CNV_RGI_DT_R UART_CTS PETN0
CNV_RGI_RSP R6109 1 2 49D9R1F-GP CNV_RGI_RSP_R 34 35 W LAN_PCIE_TX_CON_P C6108 1 2 SCD1U25V1MX-1-GP W LAN_PCIE_TX_P
CNV_RGI_DT_R 32 UART_RTS PETP0 33
UART_TX GND
[21] CLKREQ_CNV
[21] CNV_RF_RESET#
CNV_BRI_RSP R6118 1 2 49D9R1F-GP CNV_BRI_RSP_R 22 23 CNV_W R_CLKP
20 UART_RX SDIO_RESET 21 CNV_W R_CLKN
B 18 UART_WAKE SDIO_WAKE 19 B
R6141 16 GND SDIO_DAT3 17 CNV_W R_DP0
CLKREQ_CNV 1 233R1F-GP BT_PCMOUT_CLKREQ0_R 14 LED#2 SDIO_DAT2 15 CNV_W R_DN0
R6142 12 PCM_OUT SDIO_DAT1 13
CNV_RF_RESET# 1 233R1F-GP BT_PCMFRM_CRF_RST_N 10 PCM_IN SDIO_DAT0 11 CNV_W R_DP1
[21] CNV_W T_DN0 PCM_SYNC SDIO_CMD
3D3V_W LAN 8 9 CNV_W R_DN1
[21] CNV_W T_DP0 PCM_CLK SDIO_CLK
[21] CNV_W T_DN1 6 7
LED#1 GND
1
4 5 BT_USB20_CON_N
[21] CNV_W T_DP1 3_3VAUX USB_D-
R6134 R6133 2 3 BT_USB20_CON_P
[21] CNV_W T_CLKN
[21] CNV_W T_CLKP 75KR1F-GP DY 71K5R1F-GP
3_3VAUX NGFF_KEY_E_75P USB_D+
GND
1
NP2 NP1
NP2 NP1
2
BT_USB20_CON_P 1 2 BT_USB20_P
[21] CNV_W R_DN0
[21] CNV_W R_DP0 R6111
SKT-NGFF75P-164-GP 0R0402-PAD-7-NP-GP
[21] CNV_W R_DN1
[21] CNV_W R_DP1 062.10003.0B11
[21] CNV_W R_CLKN
[21] CNV_W R_CLKP 2nd = 062.10007.0371
[21] CNV_BRI_RSP
BT_USB20_CON_N 1 2 BT_USB20_N
[21] CNV_RGI_RSP
R6110
0R0402-PAD-7-NP-GP
A [24] JIO3_PCIE_W AKE# <Core Design> A
Wistron Corporation
Title
Title
Size
NGFF_WLAN CONN
DocumentNumber
Number Rev
Size Document Rev
A3
Cyborg TGL SC
Date: Sheet
Sheet 61 of 105
5 4 3 2 1
5 4 3 2 1
Main Func = WWAN

For CBG L
D D
WWAN1
35
close to CONN,<8mils
34
WWAN_PCIE_TX_P C6202 1 2 SCD1U16V2KX-3DLGP WWAN WWAN_PCIE_TX_P_C 33
WWAN_PCIE_TX_N C6201 1 2 SCD1U16V2KX-3DLGP WWAN WWAN_PCIE_TX_N_C 32 KYO-CON34-GP
31
[24] EC_I2C_SCL_ITE8010
[24] EC_I2C_SDA_ITE8010
WWAN_PCIE_RX_P R6210 1 2
0R0402-PAD-7-NP-GP WWAN WWAN_PCIE_RX_P_R 30
WWAN_PCIE_RX_N R6211 1 2
0R0402-PAD-7-NP-GP WWAN WWAN_PCIE_RX_N_R 29
28
WWAN WWAN_CLK_CPU_P 27
teknisi indonesia WWAN_CLK_CPU_N 26
[16] WWAN_PCIE_RX_N 25
[16] WWAN_PCIE_RX_P WWAN_USB20_P R6202 1 2
0R0402-PAD-7-NP-GP WWAN WWAN_USB20_P_R 24
[16] WWAN_PCIE_TX_N WWAN_USB20_N R6203 1 2
0R0402-PAD-7-NP-GP WWAN WWAN_USB20_N_R 23
[16] WWAN_PCIE_TX_P 22
TPAD14-OP-GP 1 WWAN_PCIE_WAKE_N 21
TP6201 WWAN_CLKREQ_CPU_N 20
[18] WWAN_CLK_CPU_P PCH_PLTRST# 19
C [18] WWAN_CLK_CPU_N C
18
[18] WWAN_CLKREQ_CPU_N WWAN_DB_DET# R6201 1 2 WWAN WWAN_DB_DET#_R 17
WWAN_BB_RST# 0R0402-PAD-7-NP-GP 16
R6204
WWAN_GPIO_PERST# 1 2 WWAN_GPIO_PERST#_R 15
[4] WWAN_FULL_PWR_EN_R EC_I2C_SCL_ITE8010 14
0R0201-PAD-GP
EC_I2C_SDA_ITE8010 13
TPAD14-OP-GP 1WWAN_INT#_ITE8010 12
[18] WWAN_BB_RST# DUAL_BOOT_EVENT# R6205 1 DY 2 TP6202 11
[4] WWAN_GPIO_PERST# 0R1J-GP 10
[17,61,63,66,71,76,91] PCH_PLTRST#
9
WWAN_FULL_PWR_EN_R 8
[18] WWAN_DB_DET# 7
6
3D3V_S5 5
[16] WWAN_USB20_N
4
[16] WWAN_USB20_P
3
FC6201 FC6202 2
1
SC33P25V1JN-GP
SC33P25V1JN-GP
DY DY 1
2
B B
36
WWAN
[16,24] DUAL_BOOT_EVENT#
020.K0346.0034
2nd = 020.K0270.0034
<Core Design>
Wistron Corporation
Title
WWAN
A4
Cyborg TGL SC
5 4 3 2 1
5 4 3 2 1
Main Func = M.2 SSD 3D3V_S0 3D3V_SSD1
1 2
R6351
0R0805-PAD-NP-GP
C6319
1
SCD1U16V2KX-3DLGP
C6309
SC33P50V2JN-3DLGP
C6320
SC33P50V2JN-3DLGP
C6310
C6332
1
1
SCD047U25V2KX-4-GP
SCD047U25V2KX-4-GP
DY DY DY DY C6333 C6323
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
2
2
2
2
[18] SSD_CLKREQ_CPU_N
[17,61,62,66,71,76,91] PCH_PLTRST#
D D
[18] SSD_CLK_CPU_P
SSD M.2 CONN

[18] SSD_CLK_CPU_N 3D3V_SSD1
REVERSE TYPE
1
3D3V_SSD1 SSD1
[16] SSD_PCIE_TX_P9 R6349
[16] SSD_PCIE_TX_N9 NP2 NP1 100KR2J-1-GP
76 NP2 NP1 77
[16] SSD_PCIE_RX_N9 76 77
74 75
[16] SSD_PCIE_RX_P9 3_3VAUX GND
For PCIe SSD Only
2
72 73
70 3_3VAUX GND 71
[16] SSD_PCIE_TX_P10 3_3VAUX GND M2_PEDET
68 69
[16] SSD_PCIE_TX_N10 58 SUSCLK_32KHZ PEDET(OC_PCIE/GND_SATA) 67
[16] SSD_PCIE_RX_P10 NC#58 NC#67
56 57
[16] SSD_PCIE_RX_N10 NC#56 GND SSD_CLK_CPU_P
54 55
SSD_CLKREQ_CPU_N 52 PEWAKE#/NC#54 REFCLKP 53 SSD_CLK_CPU_N
[16] SSD_PCIE_TX_P11 PCH_PLTRST# CLKREQ#/NC#52 REFCLKN
50 51
[16] SSD_PCIE_TX_N11 PERST#/NC#50 GND SSD_SATA_TX_CON_P12 SSD_PCIE_TX_P12
48 49 1 2 C6324 SCD22U10V2KX-2-GP
[16] SSD_PCIE_RX_P11 NC#48 D_PERP0/SATA_A+/H_PETP0 SSD_SATA_TX_CON_N12 SSD_PCIE_TX_N12
46 47 1 2 C6325 SCD22U10V2KX-2-GP
[16] SSD_PCIE_RX_N11 NC#46 D_PERN0/SATA_A-/H_PETN0
44 45
42 NC#44 GND 43 SSD_PCIE_RX_P12
[16] SSD_PCIE_TX_P12 NC#42 D_PETP0/SATA_B-/H_PERP0 SSD_PCIE_RX_N12
R6350 40 41
[16] SSD_PCIE_TX_N12 M2_DEVSLP1 MSATA_DEVSLP1_R NC#40 D_PETN0/SATA_B+/H_PERN0
1 2 38 39
[16] SSD_PCIE_RX_P12 36 DEVSLP GND 37 SSD_PCIE_TX_CON_P11 1 2 C6326 SSD_PCIE_TX_P11
[16] SSD_PCIE_RX_N12 0R2J-2-GP SCD22U10V2KX-2-GP
34 NC#36 D_PERP1/H_PETP1 35 SSD_PCIE_TX_CON_N11 1 2 C6327 SCD22U10V2KX-2-GP SSD_PCIE_TX_N11
DY 32 NC#34 D_PERN1/H_PETN1 33
28 NC#30 D_PETP1/H_PERP1 29 SSD_PCIE_RX_N11
26 NC#28 D_PETN1/H_PERN1 27
24 NC#26 GND 25 SSD_PCIE_TX_CON_P10 1 2 C6328 SCD22U10V2KX-2-GP SSD_PCIE_TX_P10
3D3V_SSD1 NC#24 D_PERP2/H_PETP2
22 23 SSD_PCIE_TX_CON_N10 1 2 C6329 SCD22U10V2KX-2-GP SSD_PCIE_TX_N10
[64] M2_PCIE_LED# NC#22 D_PERN2/H_PETN2
20 21
16 3_3VAUX D_PETN2/H_PERP2 17 SSD_PCIE_RX_N10
C 14 3_3VAUX D_PETP2/H_PERN2 15 C
12 3_3VAUX GND 13 SSD_PCIE_TX_CON_P9 1 2 C6330 SCD22U10V2KX-2-GP SSD_PCIE_TX_P9
[24] SSD_SCP# M2_PCIE_LED# 3_3VAUX D_PERP3/H_PETP3 SSD_PCIE_TX_CON_N9 SSD_PCIE_TX_N9
3D3V_SSD1 10 11 1 2 C6331 SCD22U10V2KX-2-GP
SSD_SCP# 1 2 SSD_SCP1# 8 DAS/DSS# D_PERN3/H_PETN3 9
R6357 6 NC#8 GND 7 SSD_PCIE_RX_P9
0R0402-PAD-7-NP-GP 4 NC#6 D_PETN3/H_PERP3 5 SSD_PCIE_RX_N9
2 3_3VAUX D_PETP3/H_PERN3 3
3_3VAUX GND 1
NGFF_KEY_M 75P GND
[16] M2_DEVSLP1
SKT-NGFF75P-294-GP
062.10003.0K11
3D3V_S0
1
R6355
2
0R0805-PAD-NP-GP
3D3V_SSD2
For CBG 15" N/V

CBG_SSD2
C6348
1
SC33P50V2JN-3DLGP
C6336
SC33P50V2JN-3DLGP
C6347
C6338
1
1
SCD047U25V2KX-4-GP
SCD047U25V2KX-4-GP
C6334 C6341 C6340

M.2 SSD2 DY DY DY DY
SCD1U16V2KX-3DLGP
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
CBG_SSD2
CBG_SSD2
CBG_SSD2
2
2
2
B B
[16] SSD_PCIE_TX_P3
[16] SSD_PCIE_TX_N3
[16] SSD_PCIE_RX_P3
[16] SSD_PCIE_RX_N3 SSD M.2 CONN 3D3V_SSD2
[16] SSD_PCIE_TX_P2
10/9 SSD1 PCIE from CPU, not have port to detect SATA, need remove SATA function? such as DEVSLP, PEDET?
REVERSE TYPE
[16] SSD_PCIE_TX_N2
1
3D3V_SSD2 SSD2
[16] SSD_PCIE_RX_P2
[16] SSD_PCIE_RX_N2 R6353
NP2
NP2 NP1
NP1 CBG_SSD2
100KR2J-1-GP
76 77
74 76 77 75
3_3VAUX GND PCIE:1 SATA:0
2
72 73
70 3_3VAUX GND 71
68 3_3VAUX GND 69 M2_PEDET1
[18] SSD2_CLK_CPU_P 58 SUSCLK_32KHZ PEDET(OC_PCIE/GND_SATA) 67
[18] SSD2_CLK_CPU_N 56 NC#58 NC#67 57
[18] SSD2_CLKREQ_CPU_N NC#56 GND SSD2_CLK_CPU_P
54 55
SSD2_CLKREQ_CPU_N 52 PEWAKE#/NC#54 REFCLKP 53 SSD2_CLK_CPU_N
PCH_PLTRST# 50 CLKREQ#/NC#52 REFCLKN 51
PERST#/NC#50 GND SSD_SATA_TX_CON_P3
[16] M2_PEDET1
48
NC#48 D_PERP0/SATA_A+/H_PETP0
49
SSD_SATA_TX_CON_N3
1 2 C6343 CBG_SSD2 SCD22U10V2KX-2-GP SSD_PCIE_TX_P3
46
NC#46 D_PERN0/SATA_A-/H_PETN0
47 1 2 C6345 CBG_SSD2 SCD22U10V2KX-2-GP SSD_PCIE_TX_N3
44 45
42 NC#44 GND 43 SSD_PCIE_RX_N3
40 NC#42 D_PETP0/SATA_B-/H_PERP0 41 SSD_PCIE_RX_P3
M2_DEVSLP1 1 R6301 2 MSATA_DEVSLP2_R 38 NC#40 D_PETN0/SATA_B+/H_PERN0 39
DEVSLP GND SSD_PCIE_TX_CON_P2
0R0402-PAD-7-NP-GP 36
NC#36 D_PERP1/H_PETP1
37
SSD_PCIE_TX_CON_N2
1 2 C6344 CBG_SSD2SCD22U10V2KX-2-GP SSD_PCIE_TX_P2
CBG_SSD2 34
NC#34 D_PERN1/H_PETN1
35 1 2 C6346 CBG_SSD2SCD22U10V2KX-2-GP SSD_PCIE_TX_N2
32 33
28 NC#30 D_PETP1/H_PERP1 29 SSD_PCIE_RX_N2
26 NC#28 D_PETN1/H_PERN1 27
3D3V_SSD2 24 NC#26 GND 25
22 NC#24 D_PERP2/H_PETP2 23
20 NC#22 D_PERN2/H_PETN2 21
18 NC#20 GND 19
16 3_3VAUX D_PETN2/H_PERP2 17
A CBG_SSD2 14 3_3VAUX
3_3VAUX
D_PETP2/H_PERN2
GND
15 A
0R0402-PAD-7-NP-GP 12 13
3D3V_SSD2 M2_PCIE_LED# 1 R6354 2 M2_PCIE_LED#_R 10 3_3VAUX D_PERP3/H_PETP3 11
SSD_SCP# 1 R6356 2 SSD_SCP2# 8 DAS/DSS# D_PERN3/H_PETN3 9
0R0402-PAD-7-NP-GP 6 NC#8 GND 7
NC#6 D_PETN3/H_PERP3
CBG_SSD2 4
3_3VAUX D_PETP3/H_PERN3
5
<Core Design>
2 3
3_3VAUX GND 1
NGFF_KEY_M 75P GND
SKT-NGFF75P-294-GP
Wistron Corporation
062.10003.0K11 Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
mSATA
Size
Size Document
DocumentNumber
Number Rev
Rev
A2
Cyborg TGL SC
Date:
Sheet 63 of 105
5 4 3 2 1
5 4 3 2 1
NONE FINGER PRINT 才會上件

Main Func = Power BTN Power button
KBC_PWRBTN# 2 1 KBC_PWRBTN#_R
R6419
0R0402-PAD-7-NP-GP
G6401
GAP-OPEN
G6402
GAP-OPEN
1
1
KBC_PWRBTN#_R
[24] KBC_PWRBTN# EC6403 DY
D D
2
SC1KP50V2KX-1DLGP
ED6401
AZ5725-01FDR7G-GP
2
[66] KBC_PWRBTN#_R 83.05725.0A0
DY
2
Layout note:
G6401 place to buttom
G6402 place to top
Main Func = Battery LED
Low actived from KBC GPIO 1

0R0201-PAD-GP
R6408
2
5V_S5
Battery LED1 (AMBER_LED)
DY Q6403
E
R2
[24] LED_MASK# Q6406
CHG_AMBER_LED# 1 6 CHG_AMBER_LED#_Q B
Note:ZZ.27002.F7C01
R1
C AMBER_LED_BAT R6407 1 2 BAT_AMBER
LED_MASK# 2 5 LED_MASK# 499R2F-2-GP
LDTA144VLT1G-GP
1
BATT_WHITE_LED#_Q 3 4 BATT_WHITE_LED# EC6402
084.00144.0B11 DY SCD1U25V2KX-1-DL-GP
[24] CHG_AMBER_LED#
2N7002KDW-1-GP 2nd = 84.00144.P11
2
75.27002.F7C
C 2nd = 075.27002.0E7C C
3rd = 075.07002.0A7C
[20,24] BATT_WHITE_LED#
1 2
R6409
0R0201-PAD-GP
LED1
1 + Yellow
5V_S5 - 3
2 + White
Q6404 CBG_NV
E
R2
B
R1
C WHITE_LED_BAT R6406 1 2 BAT_WHITE LED-YW-5-GP
549R2F-GP 083.1212A.0070
LDTA144VLT1G-GP 2nd = 083.00327.0070
1
084.00144.0B11 DY EC6404
2nd = 84.00144.P11
SCD1U25V2KX-1-DL-GP
Battery LED2 (WHITE_LED)
2
SATA HDD LED
Main Func = HDD LED LOW actived from PCH GPIO 1D8V_S0
3D3V_S0
3D3V_S0
1 R6403
[20,24] MASK_SATA_LED# 10KR2J-3-GP
1
R6411 DY R6415
2
[18] SATA_LED# DY 10KR2J-3-GP 10KR2J-3-GP

MASK_SATA_LED#
B B
2
[63] M2_PCIE_LED# D6401

SATA_LED# K A SATA_LED#_D
83.R2003.A8M
[20] SATA_LED#_D RB520S30-GP 2ND = 083.52030.008F
3rd = 083.52030.0C8F
D6402
M2_PCIE_LED# K A 83.R2003.A8M
2ND = 083.52030.008F
RB520S30-GP 3rd = 083.52030.0C8F
Main Func = M-BIST R6405

330R2J-3-GP
1DY 2
3D3V_S5
Q6407
PM_RSMRST# R2
E CHG_AMBER_LED#_Q
Q6407_B B
2
R1
C Q6407_C
R6414 R6404
330KR2F-L-GP 2MR2F-GP LMUN5112T1G-GP-U
2
DY 084.05112.001K R6413
C
1
M_BIST B
2nd = 84.00124.K1K 150R2F-1-GP
Q6408
LMBT3904LT1G-GP 3rd = 084.00024.0A1K
1
D6403
E
[17] PM_RSMRST# RB520S30-GP

HW_ACAV_IN K A
[24] M_BIST KBC_PWRBTN#
1
[24,44] HW_ACAV_IN 83.R2003.A8M C6405

84.T3904.H11
2nd = 083.52030.008F SC1U10V2KX-1DLGP
2nd = 084.03904.0I11
3rd = 083.52030.0C8F
2
A A
3rd = 084.03904.0H11
4th = 84.03904.T11
<Core Design>
M-BIST(Mainboard Built-In Self Test)Check if Wistron Corporation

MB is damage while press power button. 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
There is a LED will light up to indicate the MB Taipei Hsien 221, Taiwan, R.O.C.
is damage by
Title
Title
LED Board&Power Button

Size
Size Document
DocumentNumber
Number Rev
Rev
A2
Cyborg TGL SC
Date: Sheet
Sheet 64 of 105
5 4 3 2 1
5 4 3 2 1
Main Func = KB Internal Keyboard Connector
[24] CAP_LED#_R Keyboard Backlight (Reserved) KB1

31
5V_S0 5V_KB_BL 1
KB_LED_DET_C KB_BL_CTRL# 2
F6502 3
1 2 CAP_LED 4
KBBL
1
EC6501 EC6503 KSO10 5
1
KSO11 6
SCD1U16V2KX-3DLGP
SCD1U16V2KX-3DLGP
POLYSW-1D1A6V-9-GP-U DY DY KSO09 7
[4] KB_DET# 69.48001.081 KBBL
2
C6501 KSO14 8
2
2nd = 69.50011.081 SCD1U16V2KX-3DLGP KSO13 9
KSO15 10
[20] KB_LED_BL_DET KSO16 11
D D
KBBL1 KSO12 12
5 KSO00 13
[24] KB_LED_PWM 1 KSO02 14
R6503 KSO01 15
KB_LED_BL_DET 1 KB_LED_DET_C
KBBL 2 2
3
KBBL KSO03
KSO08
16
17
[24] KSO00 020.K0298.0004
1
KB_BL_CTRL# 4 KSO06 18
CAP LED Control
51KR2J-1-GP
[24] KSO01
[24] KSO02 KBBL 6 2nd = 020.K0311.0004 KSO07 19
KSO04 20
[24] KSO03
R6507
100KR2J-1-GP ACES-CON4-90-GP-U LOW actived from KBC GPIO KSO05 21
[24] KSO04 KSI0 22
[24] KSO05
2
1 Q6502 5V_S0 KSI3 23
[24] KSO06 KSI1 24
[24] KSO07 R2
E KSI5 25
AFTP6565
[24] KSO08 CAP_LED#_R B 26
[24] KSO09
KB Backlight Power Consumption: 285mA max. R6506 KSI2
D
R1
C CAP_LED_Q 1 2 CAP_LED KSI4 27
[24] KSO10 KSI6 28
Q6501
[24] KSO11 PJA3402-R1-00001-GP KSI7 29
LDTA144VLT1G-GP 1KR2J-1-GP
[24] KSO12 KB_LED_PWM G KB_DET# 30
[24] KSO13 084.03402.0031 084.00144.0B11 32
[24] KSO14 2nd = 084.02306.0031 2nd = 84.00144.P11
1
[24] KSO15 KBBL
S
5V_KB_BL 1
[24] KSO16 DY R6505
100KR2J-1-GP
ACES-CON30-29-GP
AFTP6506 020.K0254.0030
2nd = 20.K0750.030
2
KB_LED_DET_C 1
[24] KSI[0..7] KSI0
KSI1 AFTP6566
KSI2
KSI3
KSI4 KB_BL_CTRL# 1
KSI5
KSI6 AFTP6567
KSI7
C
Main Func = TPAD 3D3V_S0 3D3V_TP_S0
C
1 2
R6502
0R0402-PAD-7-NP-GP
Need to check if it is Active High or Active Low

and check if there is PH on TPAD side.
3D3V_TP_S0
TP side has pull high
R6511
TOUCHPAD_INTR# 1 2
10KR2J-3-GP
Support PTP
0R0402-PAD-7-NP-GP
EC_I2C_SCL_TP 1 R6514 2
EC_I2C_SDA_TP 1 2
PS2 R6515 3D3V_TP_S0 Precision Touch Pad Connector
0R0402-PAD-7-NP-GP
B 0R0402-PAD-7-NP-GP B
CPU_I2C_SCL_P0 1 R6513 2 CPU_I2C_SCL_TP_CON
I2C CPU_I2C_SDA_P0 1 2 CPU_I2C_SDA_TP_CON
R6512 TP1 Pin number Pin name
EC6504 EC6502 0R0402-PAD-7-NP-GP 10
1
8 1 VDD
SC33P50V2JN-3GP
SC33P50V2JN-3GP
CPU_I2C_SDA_TP_CON 7
CPU_I2C_SCL_TP_CON 6 DAT(I2C)
2
2
DY DY 5
1
[24] EC_I2C_SDA_TP C6505 TOUCHPAD_INTR# 4 CLK(I2C)
PTP_DIS# 3 3
SCD1U16V2KX-3DLGP
[24] EC_I2C_SCL_TP
2
4 GND
2
1
5 ATTN
1 9
[20,66] CPU_I2C_SCL_P0
[20,66] CPU_I2C_SDA_P0 3D3V_TP_S0 AFTP6531
6 GPIO
PTWO-CON8-16-GP 7 DAT(PS2)
020.K0255.0008
2nd = 020.K0151.0008 8 CLK(PS2)
2
1
RN6503
SRN2K2J-1-GP
3D3V_TP_S0 1 AFTP6529
3
4
CPU_I2C_SCL_TP_CON CPU_I2C_SCL_TP_CON
1 AFTP6528
CPU_I2C_SDA_TP_CON
1 AFTP6527
CPU_I2C_SDA_TP_CON TOUCHPAD_INTR# 1 AFTP6525
PTP_DIS# 1 AFTP6526
[3,24] TOUCHPAD_INTR#
[24] PTP_DIS#
A A
<Core Design>
Wistron Corporation
Title
Key Board&Touch Pad

A2
Cyborg TGL SC
5 4 3 2 1
5 4 3 2 1
Main Func = IO Connector

USB2.0 Power Pin define by follow layout routing
IO DET
C6601
5V_S5
C6602S
5
U6601
IN OUT
1
2
5V_USB30
USB2.0 PORT
For CBG L
[20] IO_DB_DET#_GPPG5 USB_PWR_EN GND USB_OC1#
1
R6635 1 2 0R2J-2-GP 4 3
C8D2P50VCN-2-GP
EN# OC#
SC1U10V2KX-1DLGP
DY Q6602 USB IO 2A
2N7002K-2-GP-U 3D3V_S5 074.00524.0C9F
2
USB_PWR_EN# G G524B2T11U-GP 2nd = 074.03553.007G
USB IO 3A 3rd = 074.09742.009F USB2
AUDIO USB IO 3A D R6634 2

100KR2J-1-GP
1 7
1
S CBG L using 3A :074.03556.009F (1st)
EL6605 LOM_CABLE_DETECT# 2
CBG L using 3A :074.06288.0B9B (2nd) 1 2 USB3_USB20_CON_N 3
[27,29] AUD_RING 84.2N702.J31 CBG N/V using 2A :074.00524.0C9F [16] USB3_USB20_N USB3_USB20_CON_P 4
2ND = 084.27002.0N31 4 3 PWR_LED 5
[27,29] AUD_SLEEVE 3rd = 084.27002.0L31 [16] USB3_USB20_P IO_DB_DET#_GPPG5 6
4th = 084.07002.0C31 DLM0NSN900HY2D-GP 8
[29] AUD_HP1_JACK_L1
D [29] AUD_HP1_JACK_R1
LID sensor C6604
068.09002.2001
2nd = 68.02002.061
USB20
HRS-CON6-21-GP
020.K0448.M001
D
[27] AUD_SENSE R6633 1 2 0R2J-2-GP 1 2

NON_LID_WAKE
SCD1U16V2KX-3DLGP
Q6601 2nd = 020.K0443.M001
20191125 LID_POWER_ON# 3 4
Follow CY20 D6601
LID_CL_SIO# A K LID_CL_NB# R6627 1 2 680KR2F-GP Q6701_G 2 5
Note:ZZ.27002.F7C01
CRD 20191210
Follow CY20
RB520S30-GP 1 6 2
R6628
1 3D3V_AUX_S5
1
83.R2003.A8M 20200305(DVT1)
C6605
680KR2F-GP
[16] CARD1_USB20_N 2ND = 083.52030.008F C6605 change from
SC4D7U6D3V2MX-1-GP 2N7002KDW-1-GP 3D3V_S5
[16] CARD1_USB20_P 3rd = 083.52030.0C8F 78.10523.5FLDL to 75.27002.F7C
2
LID_WAKE 078.47510.05FD 2nd = 075.27002.0E7C
3rd = 075.07002.0A7C
1
R6602
10KR2J-3-GP
USB20
USB3.0
2
IO_DB_DET#_GPPG5
C6603 1 2 SC1U10V2KX-1DLGP
D6602 K A RB520S30-GP Q6701_G_D

PORT1
[16] USB2_USB30_RX_N 83.R2003.A8M
[16] USB2_USB30_RX_P 2ND = 083.52030.008F
[16] USB2_USB30_TX_N 3rd = 083.52030.0C8F
[16] USB2_USB20_N
[16] USB2_USB20_P
USB CONTROL CRD 2nd = 68.02002.061

20191211
Stuff EL6601 for EMC requirement
068.09002.2001
[4] USB_OC1# CARD1_USB20_N 1
DLM0NSN900HY2D-GP
2 CARD1_USB20_CON_N I/O Board Connector (Colay)
[24,35] USB_PWR_EN# CARD1_USB20_P CARD1_USB20_CON_P
4 3
EL6601 IOBD1
20200428 52
5V_S5 For Power Button LED( L only) 54 IOBD2
50 44
AUD_HP1_JACK_L1 AUD_AGND 49
AUD_SENSE 48 42
1 2 5V_S5_LED AUD_HP1_JACK_R1 47
R6601 AUD_SLEEVE 46 40
AUD_SLEEVE 45 AUD_HP1_JACK_L1 AUD_AGND 39
USB3.0 PORT1 0R0603-PAD-7-NP-GP
AUDIO AUD_SLEEVE 44 AUD_SENSE 38
AUD_RING 43 AUD_HP1_JACK_R1 37
DLM0NSN900HY2D-GP AUD_RING 42 AUD_SLEEVE 36
USB2_USB20_N 1 2 USB2_USB20_CON_N AUD_RING 41 AUD_SLEEVE 35
40
AUDIO AUD_SLEEVE 34
USB2_USB20_P USB2_USB20_CON_P FP1_USB20_CON_N AUD_AGND AUD_RING
4 3 39 33
C FP1_USB20_CON_P 38 AUD_RING 32 C
EL6603 FINGER PRINTER LID_CL_NB# 37 AUD_RING 31
LAN 068.09002.2001 FPR_SCAN# 36 AUD_AGND
30
35 FP1_USB20_CON_N 29
[16] LAN_PCIE_RX_N 2nd = 68.02002.061 CARD1_USB20_CON_N 34 FP1_USB20_CON_P 28
[16] LAN_PCIE_RX_P 3D3V_S5 Card Reader CARD1_USB20_CON_P 33 LID_CL_NB# 27
[16] LAN_PCIE_TX_N FPR_SCAN#
[16] LAN_PCIE_TX_P
32 26
USB2_USB20_CON_N 31 25
USB2_USB20_CON_P 30 CARD1_USB20_CON_N 24
[18] LAN_CLK_CPU_N
FP Card Reader CARD1_USB20_CON_P
2
1 2 0R0402-PAD-7-NP-GP 29 23
[18] LAN_CLK_CPU_P R6606
R6615
USB3.1 PORT2 USB2_USB30_TX_P 28 22
100KR2J-1-GP USB2_USB30_TX_N 27 USB2_USB20_CON_N 21
[18] CLK_PCIE_LAN_REQ# USB2_USB30_RX_P USB2_USB20_CON_P
26 20
FP1_USB20_N FP1_USB20_CON_N USB2_USB30_RX_N 25 19
[24] PM_LAN_ENABLE USB3.1 PORT2
1
24 USB2_USB30_TX_P 18
FP1_USB20_P FP1_USB20_CON_P LID_CL_SIO_TAB# SIO_SLP_S4# 23 USB2_USB30_TX_N 17
[24] PCIE_LAN_WAKE# KBC_PWRBTN#_R USB2_USB30_RX_P
22 16
21 USB2_USB30_RX_N 15
RTC 3D3V_RTC_VCC
3D3V_S0
20 14
19 SIO_SLP_S4# 13
LID_CL_SIO_TAB# 3D3V_S5 KBC_PWRBTN#_R
R6611 1 2 0R2J-2-GP 3D3V_AUX_S5
18 12
IOBD_50P_2IN1 17 11
R6607 1 2 0R0402-PAD-7-NP-GP PCIE_LAN_WAKE# R6617 1 2 0R2J-2-GP PCIE_LAN_WAKE#_R 5V_S5_LED
16 RTC 3D3V_RTC_VCC
10
FP IOBD_50P_LAN 5V_USB30
15
LID_CL_SIO_TAB#
3D3V_S0
3D3V_S5
9
14 R6612 1 2 0R2J-2-GP 3D3V_AUX_S5
8
13 IOBD_40P_2IN1 5V_S5_LED
7
[16] FP1_USB20_N 12 PCIE_LAN_WAKE# 1 2 0R2J-2-GP PCIE_LAN_WAKE#_R 6
R6616
[16] FP1_USB20_P PCH_PLTRST# 11 5
10
IOBD_40P_LAN 5V_USB30 4
[24] FPR_SCAN#
9 3
LAN_PCIE_RX_N 8 2
LAN_PCIE_RX_P 7
LAN_PCIE_TX_N 6 PCH_PLTRST# 1
[64] KBC_PWRBTN#_R LAN_PCIE_TX_P 5
LAN_CLK_CPU_N 4 41
[17,51] SIO_SLP_S4# LAN LAN_CLK_CPU_P 3
CLK_PCIE_LAN_REQ# 2 43
PM_LAN_ENABLE 1 STAR-CON40-8-GP
53 IOBD_40P
51 020.F1253.0050 020.F0847.0040
2nd = 020.F0688.0050 2nd = 020.F1427.0040
[20,24] LID_CL_SIO# 3rd = 020.F0574.0050 3rd = 20.F2406.040
STM-CON50-GP
[24] LID_POWER_ON# IOBD_50P
[20,24] LID_CL_SIO_TAB#
[17,61,62,63,71,76,91] PCH_PLTRST#
[20,65] CPU_I2C_SCL_P0
[20,65] CPU_I2C_SDA_P0
[44] PWR_CHG_VBATIN
B B
3D3V_LCDVDD_S0
3D3V_LCDVDD_S0 3D3V_S0 3D3V_SSD1 3D3V_S0 3D3V_SSD2

[20] LOM_CABLE_DETECT# 19V_DCBATOUT 19V_DCBATOUT_LCD_R
[24] PWR_LED
1
1
R6655
1
E3
1
1
1
R6654 0R2J-2-GP
1
1
R6638 R6649 R6652 R6653

E3 E3 R6650 R6651 0R2J-2-GP E3 E3 0R2J-2-GP E3
0R2J-2-GP 0R2J-2-GP
0R2J-2-GP E3 0R2J-2-GP
2
0R2J-2-GP E3
2
2
2
2
2
2
2
19V_DCBATOUT_E3 19V_DCBATOUT_LCD_R_E3 3D3V_SSD2_E3_R

3D3V_LCDVDD_R_E3 3D3V_LCDVDD_S0_E3 3D3V_SSD1_E3_R 3D3V_SSD1_E3 3D3V_SSD2_E3
19V_DCBATOUT 3D3V_S5 19V_DCBATOUT 19V_DCBATOUT

19V_DCBATOUT 19V_DCBATOUT 3D3V_WLAN
PWR_CHG_VBATIN
1
2
2
2
2
2
1
R6640 R6641 R6642 R6647 R6648

E3 0R2J-2-GP R6639 E3 E3 R6643 R6644 R6645 R6646
E3
0R2J-2-GP 0R2J-2-GP
E3 E3 E3 0R2J-2-GP E3 0R2J-2-GP
0R2J-2-GP E3 0R2J-2-GP
E3 0R2J-2-GP 0R2J-2-GP 0R2J-2-GP
2
1
1
1
1
1
2
PWR_CHG_VBATIN_E3
19V_CHARGER_E3 19V_VCOREA_E3 PWR_VCOREA_E3 19V_VCCIN_AUX_E3 3D3V_S5_E3 3D3V_WLAN_E3 19V_VDDQ_E3 PWR_VDDQ_E3

PWR_VCCIN_AUX_E3
A A
E3
WLAN input IN1+ 1 2 19V_DCBATOUT_E3 IN4+
3D3V_S5_E3 LCD BACKLIGHT
IN2+ 3D3V_SSD1_E3_R R6632 1 E3 2 0R2J-2-GP IN1- 3D3V_WLAN_E3 3 4 19V_DCBATOUT_LCD_R_E3 IN4-
SSD 1 2 0R2J-2-GP 3D3V_S0_E3 5 6 3D3V_LCDVDD_R_E3
IN2- 3D3V_SSD2_E3_R R6631 E3
3D3V_SSD
IN3+
R6656 1 E3 2 0R2J-2-GP 7 8 3D3V_LCDVDD_S0_E3 IN3- Panel logic power
3D3V_SSD1_E3 1 2 0R2J-2-GP CPU_I2C_SCL_P0 9 10 CPU_I2C_SDA_P0
3D3V_SSD2_E3 R6657 E3
11 12 3D3V_S0
IN7- 13 14 PWR_VCOREA_E3 IN6-
VDDQ input PWR_VDDQ_E3 15 16 CPU Core input
IN7+ 19V_VDDQ_E3 19V_VCOREA_E3 IN6+
IN8- 17 18 19V_CHARGER_E3 IN5-
PWR_VCCIN_AUX_E3 PWR_CHG_VBATIN_E3 <Core Design>
VCCIN AUX input IN8+ 19V_VCCIN_AUX_E3
19 20 IN5+ System power source
HRS-CONN20A-2-GP
20.F1450.020 Wistron Corporation
TitleTitle
IO Board Connector
Wistron Confidential document, Anyone can not SizeSize Document
Document Number
Number Rev Rev
Duplicate, Modify, Forward or any other purpose A1
application without get Wistron permission Cyborg TGL SC
Date:
Sheet 66 of 105
5 4 3 2 1
5 4 3 2 1
Main Func = HALL SENSOR
D D
C C
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Cyborg TGL SC
5 4 3 2 1
5 4 3 2 1
Main Func = Debug Follow upsell remove 3D3V_DB1

ESPI Debug Connector
DBG1
ESPI 3D3V_S5
20191119
add net name
15
1
3D3V_S0
R6820 1 2 0R2J-2-GP ESPI_CLK 2
D [18,24] ESPI_CLK DY 3 D
R6821 1 2 0R2J-2-GP ESPI_RESET# 4
[18,24] ESPI_RESET# ESPI_CS#
20.F0765.014
5
ESPI_IO3 6
[18,24] ESPI_CS# DEBUG ESPI_IO2 7
ESPI_IO1 8 DEBUG
ESPI_IO0 9
3D3V_DB1 10
HOST_DEBUG_TX R6801 1 2 0R2J-2-GP HOST_DEBUG_TX_CON 11
[18,24] ESPI_IO0 DEBUG 12
[18,24] ESPI_IO1 CPU_UART2_TXD CPU_UART2_TXD_CON
R6802 1DEBUG2 0R2J-2-GP 13
[18,24] ESPI_IO2 CPU_UART2_RXD CPU_UART2_RXD_CON
R6803 1 2 0R2J-2-GP 14
[18,24] ESPI_IO3
DEBUG 16
DM-ACES-CON14-5-GP-01
ZZ.F0765.01401
20191212
3D3V_S0 Follow CY20
C R6804
1
DEBUG2 51KR2J-1-GP CPU_UART2_TXD C
R6805 1 2 51KR2J-1-GP CPU_UART2_RXD
UART DEBUG
[24] HOST_DEBUG_TX
[20] CPU_UART2_TXD
[20] CPU_UART2_RXD
B B
<Core Design>
A
Title
Dubug connector
A4
Cyborg TGL SC
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
<Core Design>
A
Title
Reserved
A4
Cyborg TGL SC
5 4 3 2 1
5 4 3 2 1
SSID = User.interface
Mantis Accelerometer for adaptive thermal and HDD protection
D D
3D3V_GSEN2
3D3V_S0
[20] GSEN2_INT1_C
[20,55] SENSOR_I2C_SCL
1
R7004
2
11uA Free Fall Sensor + G Sensor
0R0402-PAD-7-NP-GP C7003 C7004
[20,55] SENSOR_I2C_SDA
1
SCD1U16V2KX-3DLGP
SC10U6D3V3MX-DL-GP
C7004 near pin9
[20] FFS_INT1
2
[19] FFS_INT2 3D3V_GSEN2
[60] FFS_INT2_Q
U7001
R7006
9 2 GSENSOR_CS 2 1
VDD CS 5
10 RES 10KR2J-3-GP
VDD_IO 12 GSEN2_INT1_C
INT1 11 GSEN2_INT2_C
INT2
SENSOR_I2C_SCL 1
SENSOR_I2C_SDA 4 SCL/SPC 6
R7005 1 2 10KR2J-3-GP 3 SDA/SDI/SDO GND 7
3D3V_GSEN2 DY SDO/SA0 GND 8
2 1 GSENSOR_SDO GND Note:
R7007
0R0402-PAD-7-NP-GP LNG2DMTR-GP
074.LNG2D.00BZ
- no via, trace, under the sensor (keep out area around 2mm)
CBG L/WM using 8 Bits :074.LNG2D.00BZ - stay away from the screw hole or metal shield soldering joints
CBG N/V using 12 Bits :074.LIS2D.M002 - design PCB pad based on our sensor LGA pad size (add 0.1mm)
- solder stencil opening to 90% of the PCB pad size
C - mount the sensor near the center of mass of the NB as possible as you can C
GSEN2_INT1_C
GSEN2_INT2_C
FFS_INT1 R7011 1 2 0R0402-PAD-7-NP-GP 3D3V_S0
FFS_INT2 R7012 1 2 0R0402-PAD-7-NP-GP
1
1
R7018
100KR2J-1-GP
R7001 DY CBG_L_HDD
1MR2J-1-GP
2
FALL_INT2
2
1
Q7001
2N7002KDW-1-GP CBG_L_HDD
Note:ZZ.27002.F7C01
75.27002.F7C
6
2nd = 075.27002.0E7C
3rd = 075.07002.0A7C
FFS_INT2 FFS_INT2_Q CBG_L_HDD
B B
Note:
(1) Keep all signals are the same trace width. (included VDD, GND).
(2) No VIA under IC bottom.
A A
<Core Design>
Wistron Corporation
Title
Title
Free Fall Sensor

Size
Size Document
DocumentNumber
Number Rev
Rev
A2
Cyborg TGL SC
Date:
Sheet 70 of 105
5 4 3 2 1
5 4 3 2 1
Main Func = TBT HP team on applying, only murata have 20191216

sample can meet Intel request Follow SPEC change to 25V
20200324(DVT2)
220nF AC cap must be placed on RX lines close to SOC side U7101D 4 OF 4 HP team on applying ,only murata Change to common part 0.33u
TBT PORTS have sample can meet Intel request 20191212

[4]
[4]
USB1_TCSS_TX_N0
USB1_TCSS_TX_P0
USB1_TCSS_TX_P0
USB1_TCSS_TX_N0
C7101 1
1
BB22 SCD22U10V1KX-1-GP USB1_TCSS_TX_C_P0
USB1_TCSS_TX_C_N0
J1
J2 ASSRXP1 BSSRXP1
J12
J11
USB1_TCSS_RX_RT_P0
USB1_TCSS_RX_RT_N0
R7114 1
1 BB 2 2D2R1J-GP
2 2D2R1J-GP
USB1_SSRX_AR_P0_R
USB1_SSRX_AR_N0_R
C7141 1
C7142 1
BB2 SCD33U6D3V1MX-1-GP USB1_SSRX_AR_P0
USB1_SSRX_AR_N0
R7188 1
Follow Nakia
2 220KR1J-GP Follow Hellcat15 Upsell TGL
[4] USB1_TCSS_TX_N1 C7104 BB SCD22U10V1KX-1-GP
ASSRXN1 BSSRXN1 R7115 BB BB2 SCD33U6D3V1MX-1-GP R7189 1 2 220KR1J-GP
Port B - TypeC Side

[4] USB1_TCSS_TX_P1 USB1_TCSS_RX_P0 1 USB1_TCSS_RX_C_P0 G1 G12 USB1_TCSS_TX_RT_P0 USB1_SSTX_CON_P0_R C7111 1 USB1_SSTX_CON_P0
C7105 BB22 SCD22U10V1KX-1-GP R7120 1
BB 2 2D2R1J-GP
BB 2 SCD22U10V1KX-1-GP R7192 1 2 220KR1J-GP
Port A - Host Side

[4] USB1_TCSS_RX_N0 USB1_TCSS_RX_N0 1 USB1_TCSS_RX_C_N0 G2 ASSTXP1 BSSTXP1 G11 USB1_TCSS_TX_RT_N0 1 2 2D2R1J-GP USB1_SSTX_CON_N0_R C7112 1 2 SCD22U10V1KX-1-GP USB1_SSTX_CON_N0 R7193 1 2 220KR1J-GP
USB1 BB
C7102 SCD22U10V1KX-1-GP
[4] USB1_TCSS_RX_P0 ASSTXN1 BSSTXN1 R7121 BB BB
[4] USB1_TCSS_RX_N1
WPN DPN
USB1_TCSS_TX_P1 1 USB1_TCSS_TX_C_P1 C1 C12 USB1_TCSS_RX_RT_P1 USB1_SSRX_AR_P1_R USB1_SSRX_AR_P1
[4] USB1_TCSS_RX_P1 USB1_TCSS_TX_N1
C7103
1
BB22 SCD22U10V1KX-1-GP
USB1_TCSS_TX_C_N1 C2 ASSRXP2 BSSRXP2 C11 USB1_TCSS_RX_RT_N1
R7116 1
1 BB 2 2D2R1J-GP
2 2D2R1J-GP USB1_SSRX_AR_N1_R
C7143 1 BB2
C7144 1 BB2
SCD33U6D3V1MX-1-GP
USB1_SSRX_AR_N1
R7190 1
R7191 1
2 220KR1J-GP
2 220KR1J-GP
C7107 BB SCD22U10V1KX-1-GP
ASSRXN2 BSSRXN2 R7117 BB SCD33U6D3V1MX-1-GP
USB1_TCSS_RX_P1 1 USB1_TCSS_RX_C_P1 E1 E12 USB1_TCSS_TX_RT_P1 USB1_SSTX_CON_P1_R USB1_SSTX_CON_P1

[4] USB1_TCSS_TXD
C7108 BB22 SCD22U10V1KX-1-GP
ASSTXP2 BSSTXP2 R7129 1
BB 2 2D2R1J-GP C7113 1
BB 22 SCD22U10V1KX-1-GP
SCD22U10V1KX-1-GP R7194 1 2 220KR1J-GP
[4,15] USB1_TCSS_RXD
USB1_TCSS_RX_N1 C7106 1 BB SCD22U10V1KX-1-GP USB1_TCSS_RX_C_N1 E2
ASSTXN2 BB BSSTXN2
E11 USB1_TCSS_TX_RT_N1 R7130 1
BB 2 2D2R1J-GP USB1_SSTX_CON_N1_R C7114 1
BB
USB1_SSTX_CON_N1 R7195 1 2 220KR1J-GP
USB1_TCSS_TXD
USB1_TCSS_RXD
R7101
R7102
1
1
2
0R0201-PAD-GP
2
0R0201-PAD-GP
USB1_TCSS_TXD_R
USB1_TCSS_RXD_R
M7
L7 PA_LSTX_SBU1
PA_LSRX_SBU2
PB_SBU1
PB_SBU2
M10
L10
USB1_BB_SBU1
USB1_BB_SBU2 TBT 071.00TBT.0F0U M11GX
[73] USB1_SSTX_CON_P0 USB1_TCSS_AUX_P BB L8
[73] USB1_SSTX_CON_N0 USB1_TCSS_AUX_N BB M8 PA_AUX_P
[73] USB1_SSTX_CON_P1 PA_AUX_N 20200226(DVT1)
Remove R7107 R7108
D
[73] USB1_SSTX_CON_N1
NON_TBT 071.00TBT.0D0U 7DYVG D
[73] USB1_SSRX_AR_P0
[73] USB1_SSRX_AR_N0
1
R7109 R7110
[73] USB1_SSRX_AR_P1
1MR1F-GP
1MR1F-GP
[73] USB1_SSRX_AR_N1
DY DY
[73] USB1_SSTX_CON_N1_R
[73] USB1_SSRX_AR_P1_R
2
[73] USB1_SSRX_AR_N0_R
[73] USB1_SSTX_CON_N0_R BURNSIDE-BRIDGE-GP-U1
Vincent
ZZ.000IC.002
[73] USB1_SSRX_AR_P0_R 20200225(DVT1)
[73] USB1_SSTX_CON_P0_R Remove TP7104~TP7107 20200113 (DVT1)
3D3V_S0_TCP1
Add for 8010 FW update
20200226(DVT1)
BB TO PCH(TBT)
[73] USB1_SSRX_AR_N1_R Follow Nakia
[73] USB1_SSTX_CON_P1_R
R7196 1 DY 2 CPU_SMBUS_SCL_BB
CPU_SMBUS_SCL_BB R7156 1 2 0R1J-GP CPU_SML_SCL0
1KR2F-3-GP
CPU_SMBUS_SDA_BB R7159 1 DY 2 0R1J-GP CPU_SML_SDA0
[4] USB1_TCSS_AUX_P R7197 1 2 CPU_SMBUS_SDA_BB DY
1KR2F-3-GP
[4] USB1_TCSS_AUX_N U7101A 1 OF 4 1D8V_S5 DY
BB_TCP1_FLASH_DI BB_I2C_SCL Q7101 3D3V_S5
C6 C9 CPU_SMBUS_SCL_BB PCH_I2C_SCL_TBT
BB_TCP1_FLASH_DO EE_DI I2C_SCL BB_I2C_SDA 6 1
Note:ZZ.27002.F7C01
B4 E7
BB_TCP1_FLASH_CS_N B6 EE_DO I2C_SDA A10 BB_I2C_PD_INT# 1 TP7101 R7178 1 DY 2 2K2R2F-GP PCH_I2C_SDA_TBT
5 2
[18,24] CPU_SML_SCL0 BB_TCP1_FLASH_CLK EE_CS# I2C_INT TC_RETIMER_FORCE_PWR 20R0201-PAD-GP TBT_FORCE_PWR DY
FLASH
1
C7 B10 R7168 1BB_Intel 3D3V_S0_TCP1 3D3V_S0_TCP1
[18,24] CPU_SML_SDA0 EE_CLK FORCE_PWR A9 BB_TCP1_FLASH_BUSY_N PCH_I2C_SCL_TBT
R7131 1 2 10KR1F-GP R7179 1 DY 2 2K2R2F-GP R7146
BB_Intel 3D3V_SX_TCP1_D PCH_I2C_SDA_TBT 4 3 CPU_SMBUS_SDA_BB
DY
POC GPIO
3D3V_LC_TCP1 FLASH_BUSY# B9 BB_TCP1_GPIO_5 R7119 1 2 10KR1F-GP
DEBUG
POC_GPIO_5 BB_Intel 10KR1F-GP
MISC &
A8 BB_TCP1_GPIO_6
[72] BB_RST POC_GPIO_6 2N7002KDW-1-GP
R7103 1
BB 2 10KR1F-GP BB_TCP1_TDI A3
TDI PERST#
B8 TCP1_RETIMER_PERST_R_N
BB TO PCH(NON-TBT) 75.27002.F7C
2
R7104 1 2 10KR1F-GP BB_TCP1_TMS C3 A7 CPU_SMBUS_SCL_BB
R7105 1 BB 2 10KR1F-GP BB_TCP1_TCK B5 TMS SMBUS_SCL B7 CPU_SMBUS_SDA_BB TC_RETIMER_FORCE_PWR
BB 2nd = 075.27002.0E7C
JTAG
R7106 1 2 10KR1F-GP BB_TCP1_TDO C5 TCK SMBUS_SDA A4 BB_TCP1_FLASH_SHARE_EN
[72] USB1_BB_SBU1 BB TDO FLASH_SHARE_EN A5 BB_TCP1_FLASH_MSTR_SLV 3rd = 075.07002.0A7C
[72] USB1_BB_SBU2 FLASH_MASTER_SLAVE BB_TCP1_GPIO_12
1
A6
POC_GPIO_12 L3 R7149
R7169 1 DY 2 TP_TCP1_THERMDA M11 NC_L3 BB 10KR1F-GP
0R1J-GP THERMDA
M12
[16,17] PCH_TBT_PERST# TEST_EDM
2
20200221(DVT1)
B2
FUSE_VQPS_64 BB L11 TCP1_RESET_N R7177 1 BB_Intel 2 0R0201-PAD-GP BB_RST
[72] RETIMER_PWREN RESET#
Follow reference circuits NC _A12 A11
A12 MONDC L9 XTL_25M_X1_TBT1 R7111 1BB_Intel 20R0201-PAD-GP XTL_25M_X1_TBT1_R
Main
[16,72] TBT_FORCE_PWR L12 NC#A12 XTAL_25_IN M9 XTL_25M_X2_TBT1 1BB_Intel 20R0201-PAD-GP XTL_25M_X2_TBT1_R
R7113
MONDC_SVR XTAL_25_OUT
DEBUG
R7118 X7101
1 2 BB_TCP1_TEST_PWR_GOOD B3 L5 BB_TCP1_RSENSE R7112 1 2
Type-C PD BB_Intel B11 TEST_PW R_GOOD RSENSE L4 BB_TCP1_RBIAS_1 BB_option Must use Metal shielded crystal for
100R1F-GP
0R1J-GP TEST_EN RBIAS BOM Option
4K75R1D-GP
2
BB_Intel3 better noise immunity.
[72] BB_I2C_SCL TP_TCP1_ATEST_P Intel = 4.75K (064.47516.0GI1) Recommended Crystal List:
R7171 1 DY 2 A1 FW2500025Z by Pericom
[72] BB_I2C_SDA R7173 1 TP_TCP1_ATEST_N A2 ATEST_P Parade = 4.99k (64.49915.GIL)
DY 2
ATEST_N
XRCGB25M00F3L12R0 by Murata
[20] PCH_I2C_SDA_TBT 0R1J-GP 1 4 Suggest adding GND shield across
[20] PCH_I2C_SCL_TBT Crystal and 18pF caps for better
BURNSIDE-BRIDGE-GP-U1 RFI. 3D3V_S0
1
ZZ.000IC.002 C7109
XTAL-25MHZ-302-GP
C7110 R7141 1BB_Intel
2 10KR1F-GP BB_TCP1_GPIO_6 R7143 1 2 10KR1F-GP
SC33P25V1JN-3-GP 082.30005.0501 SC33P25V1JN-3-GP DY
2nd = 082.30005.0C81
2
C C
BB_Intel BB_Intel
20200225(DVT1)
Change to 0201 3D3V_SX_TCP1
20200302
Change to 27p for vendor BB_TCP1_FLASH_SHARE_EN
R7132 1 2 10KR1F-GP R7138 1 2 10KR1F-GP
suggestion
20200313
20191224
R7155 1 DY 2 10KR1F-GP BB_TCP1_GPIO_12 R7158 1 BB 2 10KR1F-GP
Change for resource shortage
R7145 1 DY 2 10KR1F-GP BB_TCP1_FLASH_MSTR_SLV R7147 1 DY 2 10KR1F-GP
20200512 DY DY
Change to 33p for vendor 3D3V_S5_VCCPRIM
suggestion
3D3V_S5 3D3V_SX_TCP1_D
1
20191213 R7162
Change U7103 for High limit 20200226(DVT1) 4K7R1F-GP-U
R7136 1 BB_Intel 2 0R0201-PAD-GP
Follow Nakia
DY
3D3V_SX_TCP1
2
3D3V_SX_TCP1_D PCH_TBT_PERST# R7166 1 2 0R1J-GP TCP1_RETIMER_PERST_R_N
1 R7198 2
20200225(DVT1) DY
1 2 2K2R1J-GP BB_TCP1_FLASH_CS_N DY0R2J-2-GP Change to 0402 size
20200504(DVT2)
R7125 BB_Intel BB_TCP1_FLASH_DO
1
1
1 2 2K2R1J-GP C7115 change to common 1 2 0R0201-PAD-GP
R7126
1
BB_Intel
2 3K32R1F-GP BB_TCP1_FLASH_WP_N
C7115 R7170 [17,61,62,63,66,76,91] PCH_PLTRST# R7167 BB
R7127
1 BB_Intel
2 3K32R1F-GP BB_TCP1_FLASH_HOLD_N BB_Intel
SC2D2U6D3V2MX-DL-GP 20KR1F-GP
R7128
BB_Intel DY
2
U7103
2
BB_TCP1_FLASH_CS_N R7133 1 BB_Intel 2 0R0201-PAD-GP BB_TCP1_FLASH_CS_N_R 1 8
BB_TCP1_FLASH_DO R7134 1 BB_Intel 2 0R0201-PAD-GP BB_TCP1_FLASH_DO_R 2 CS# VCC 7 BB_TCP1_FLASH_HOLD_N
BB_TCP1_FLASH_WP_N 3 DO/IO1 HOLD#/IO3 6 BB_TCP1_FLASH_CLK_R R7135 1 BB_Intel 2 0R0201-PAD-GP BB_TCP1_FLASH_CLK
4 W P#/IO2 CLK 5 BB_TCP1_FLASH_DI_R R7137 1 BB_Intel 2 0R0201-PAD-GP BB_TCP1_FLASH_DI
GND DI/IO0
9
GND
W25Q80DVZPIG-GP
BB_Intel
teknisi indonesia
072.25Q80.0B01
2nd = 072.25803.0A03
B B
3D3V_SX_TCP1
0D9V_SVR_TCP1
U7101B 2 OF 4
3D3V_S0_TCP1
2 1 C7118 3D3V_ANA_TCP1 L2 E6
BB_Intel
SC2D2U6D3V2MX-DL-GP VCC3P3_ANA VCC3P3_SX
E5 M4 3D3V_A_S0_TCP1 U7101C 3 OF 4
3D3V_LC_TCP1
C7117 C7147 VCC3P3_LC
BB VCC3P3_SVR M5
SC2D2U6D3V2MX-DL-GP
SC2D2U6D3V1MX-5-GP
F6 VCC3P3_SVR J5 U7101_J5 1 20200225(DVT1)

DY 2 R7175 B1 F12
BB_Intel
DY
VCC0P9_SVR_ANA NC#J5 Change to 0402 size VSS_ANA VSS_ANA

1
G6 J7 L7102 0D9V_SVR_TCP1 B12 G7

1
0R1J-GP 20200226(DVT1)
VCC0P9_SVR_ANA VCC3P3A IND-1UH-257-GP
20200504(DVT2) Follow Intel D1 VSS_ANA VSS_ANA H1
change to Common VSS_ANA VSS_ANA
Power
E3 L1 0D9V_SVR_TCP1_PHASE 1 D2 H2
VCC0P9_SVR SVR_IND BB 2 VSS_ANA VSS_ANA
2
G3 M1 D11 H11
GND
C7124 C7125 C7126 C7127 C7128 C7129 C7130 C7131 C7146
20200324(DVT2) 68.1R01F.10Y
SC2D2U6D3V2MX-DL-GP
SC2D2U6D3V2MX-DL-GP
SC2D2U6D3V2MX-DL-GP
SC2D2U6D3V2MX-DL-GP
SC2D2U6D3V2MX-DL-GP
SC2D2U6D3V2MX-DL-GP
VCC0P9_SVR SVR_IND D12 VSS_ANA VSS_ANA H12
SC18P25V1JN-2-GP
C7122 change to common
E9 M2 2nd = 068.1R010.1I61 F1 VSS_ANA VSS_ANA J9
VCC0P9_SVR_PB_ANA SVR_VSS VSS_ANA VSS_ANA
1
1
G9 M3 F2 K1
VCC0P9_SVR_PB_ANA SVR_VSS F7 VSS_ANA BB VSS_ANA K2
C7122 1 2 SC2D2U6D3V2MX-DL-GP 0D9V_LC_1 J3 F9 VSS_ANA VSS_ANA K11
BB_Intel VCC0P9_LC BB BB BB BB BB BB BB BB BB VSS_ANA VSS_ANA
2
2
F11 K12
C7123 1 2 SC10U6D3V2MX-2-GP VCC0P9_LVR_1 L6 VSS_ANA VSS_ANA
VCC0P9_LVR
VSS
VSS
VSS
BB_Intel M6 J6
C7138 1 2 SC2D2U6D3V2MX-DL-GP VCC0P9_LVR_SENSE GND
BB 20191213 BURNSIDE-BRIDGE-GP-U1
F3
F5
G5
BURNSIDE-BRIDGE-GP-U1 for High limit
ZZ.000IC.002
C7148 C7149 ZZ.000IC.002
1
C7150
DY
DY
SC2D2U6D3V1MX-5-GP
SC2D2U6D3V1MX-5-GP
DY
SC18P25V1JN-2-GP
2
3D3V_S0
3D3V_S5 20200324(DVT2)
C7135 change to common 1 2 0R2J-2-GP
R7172 DY
3D3V_S0_TCP1 3D3V_S0_TCP1 3D3V_A_S0_TCP1
3D3V_RT_TCP1
20200225(DVT1)
1
3D3V_S5
C7135 BB Change to 0402 size
BB SC1U10V2KX-1DLGP 1 2 R7161 1 2
R7180 0R0402-PAD-7-NP-GP C7132 C7133 C7134 C7151 C7152
SC2D2U6D3V2MX-DL-GP
2
DY
SC10U6D3V2MX-2-GP
SC18P25V1JN-2-GP
SC2D2U6D3V1MX-5-GP
SC18P25V1JN-2-GP
0R0603-PAD-7-NP-GP C7136 C7119 C7120 C7121 C7140
DY
SC10U6D3V2MX-2-GP
SC2D2U6D3V2MX-DL-GP
SC2D2U6D3V2MX-DL-GP
SC2D2U6D3V2MX-DL-GP
A BB
1
1
A
3D3V_RT_TCP1
1
1
R7176
3D3V_RT_TCP1_FIP BB BB
BB 100KR1F-GP U7102 BB BB
2
BB
2
2
1 8 R7123 1 2 BB BB BB
VIN#1 VOUT#8 BB
2
2 7 0R0402-PAD-7-NP-GP
RETIMER_PWREN 3 VIN#2 VOUT#7 6 U7102_CT C7137 1 2
SC220P50V2KX-3DLGP
4 ON CT 5
5V_S5 VBIAS GND
BB GND
9
C7145 3D3V_SX_TCP1 20191213
for High limit
SCD1U10V1KX-DL-GP
TPS22975-GP
1
074.22975.0093 1 2 <Core Design>

2nd = 74.03526.093
2
BB R7181 C7139 20200225(DVT1)

SC10U6D3V2MX-2-GP
0R0603-PAD-7-NP-GP Change to 0402 size

BB 20200504(DVT2)
Wistron Corporation
1
C7116 Change to common

1

BB SC2D2U6D3V2MX-DL-GP Taipei Hsien 221, Taiwan, R.O.C.
BB
2
20200113 (DVT1)
2
Follow Spec. Title

Title
EXT IO (Thunderbolt(1/3)/Type C Re-driver)
Size
Size DocumentNumber
Document Number Rev
Rev
A1
Cyborg TGL SC
Date:
Sheet 71 of 105
5 4 3 2 1
5 4 3 2 1
Follow Hellcat15 Upsell TGL

Main Func = TypeC 3D3V_S5
3D3V_VDDD
Close to Pin32 Close to Pin31
[24] EC_I2C_SCL_PD
[24] EC_I2C_SDA_PD
[24] CCG6_I2C_INT# C7201
SC1U10V2KX-1DLGP
C7207 C7210 C7211
1
SC1U10V2KX-1DLGP
SCD1U16V2KX-3DLGP
SCD1U16V2KX-3DLGP
SCD1U16V2KX-3DLGP
[74] PD_VBUS_C_CTRL1 C7212
2
[73] USB1_CON_CC1
[73] USB1_CON_CC2
D [3,22,24,44,46] PROCHOT#_CPU D
20200213
Change from BGA96P to QFN48P
PD Function
[16] USB4_USB20_P 5V_S5

Normal: High
[16] USB4_USB20_N Avtive : Low
[73] USB1_USB20_CMCT_P
[73] USB1_USB20_CMCT_N 20V_VCCPD_VBUS R7350 1 2 D005R6F-3-GP
[73] USB1_USB20_CMCB_P U7202
[73] USB1_USB20_CMCB_N PG7202
PD_VBUS_C_CTRL1 GAP-CLOSE-PWR-3-GP
47 1
[73] USB1_CON_SBU1 VBUS_C_CTRL VBUS_C 2
[73] USB1_CON_SBU2 USB1_CON_CC1 46 VBUS_C 3 3D3V_S5
5V_VBUS_CSN_R 1 2 5V_VBUS_CSN
USB1_CON_CC2 44 CC1 VBUS_C 48
CC2 VBUS_C
4
USB4_USB20_P 0R0402-PAD-7-NP-GP
2 1 R7260 USB4_USB20_PD_P 23 VBUS_P 5 1 2 5V_VBUS_CSP
1
[71] USB1_BB_SBU1 USB4_USB20_N 0R0402-PAD-7-NP-GP
2 1 R7261USB4_USB20_PD_N 22 DP_SYS VBUS_P 6
[71] USB1_BB_SBU2 DM_SYS VBUS_P 7 R7202
USB1_USB20_CMCT_P 18 VBUS_P C7203 3D3V_VDDD DY 10KR1J-GP
[4] USB_OC2# USB1_USB20_CMCT_N DP_TOP PD_VCCD 1 PG7201
19 9 2
DM_TOP VCCD 3D3V_S5 GAP-CLOSE-PWR-3-GP
SCD1U16V2KX-3DLGP
2
[71] BB_RST USB1_USB20_CMCB_P 20 11 3D3V_S5
USB1_USB20_CMCB_N 21 DP_BOT VDDD BB_RST
[17] TBT_PD_ALERT# DM_BOT 10
USB1_CON_SBU1 2 1 R7203 USB1_CON_SBU1_R 42 VDDIO 5V_VCONN_P1 5V_S5
1
USB1_CON_SBU2 2 1 R7204 USB1_CON_SBU2_R 43 SBU1 8
USB1_BB_SBU1 1 R7205 USB1_BB_SBU1_R 41 SBU2 VSYS R7210
1
2
USB1_BB_SBU2 2 1 R7206 USB1_BB_SBU2_R 40 SBU1_SYS 45 2 R7220 1 0R0603-PAD-7-NP-GP 100KR1J-GP
R7263
SBU2_SYS V5V C7217
0R0402-PAD-7-NP-GP 10KR1J-GP
1
16 CCG6_I2C_SDA R7225 1 2 CPU_SML_SDA1_PD C7216
0R0402-PAD-7-NP-GP
PD to SOC
SCD1U16V2KX-3DLGP
0R0402-PAD-7-NP-GP
2
[71] RETIMER_PWREN I2C_SDA_SCB1/P0.2 CCG6_I2C_SCL R7224 1 CPU_SML_SCL1_PD
SC1U10V2KX-1DLGP
0R0402-PAD-7-NP-GP 13 2
0R0402-PAD-7-NP-GP
0R0402-PAD-7-NP-GP I2C_SCL_SCB1/P0.3
2
[16,71] TBT_FORCE_PWR 5V_VBUS_CSP 39 17 CCG6_I2C_INT R7223 1 2
0R0402-PAD-7-NP-GP TBT_PD_ALERT# USB_OC2#
2
5V_VBUS_CSN 38 CSP I2C_INT_TBT/P0.4 15 CCG6_I2C_ADDR 20191220
0R0402-PAD-7-NP-GP
Type-C PD EC I2C
CSN SWD_CLK/P1.0
SWD_IO/P1.1
14
26
RETIMER_PWREN_R
INT#_Typec_R 1
R7222
1 R7221 2
2
0R0201-PAD-GP
RETIMER_PWRENFollow 13" TGL
CCG6_I2C_INT#
PD_XRES I2C_INT_EC/P1.2 CCG6_UART_RX UPD1_SMBDA_Q
C
[71] BB_I2C_SCL
[71] BB_I2C_SDA
34
XRES UART_RX/P1.3
UART_TX/P1.4
25
24 CCG6_UART_TX
R7259 1
0R0201-PAD-GP2
R7258 1 0R0402-PAD-7-NP-GP
2 UPD1_SMBCLK_Q PD to EC C
27 BB_RST
R7252 1 2 0R0201-PAD-GP HPD/P2.0
I2C_SDA_SCB2/P2.1
28 BB_I2C_SDA PD to BB
[18] CPU_SML_SCL1_PD 29 BB_I2C_SCL
I2C_SCL_SCB2/P2.2 CCG6_ID_2 2 0R2J-2-GP TBT_FORCE_PWR
[18] CPU_SML_SDA1_PD
Q7201
49_THM
THERMAL_PAD P2.3
30
USB_OC2#_R
R7262 1 DY USB_OC2#
EC_I2C_SCL_PD 1 6 UPD1_SMBCLK_Q 31 R7264 1 2
0R0201-PAD-GP USB1_CON_CC2 1 2 SC390P50V2KX-1-GP
P2.4 C7213
Note:ZZ.27002.F7C01
35
P3.0 36 CCG6_PROCHOT#
2 5 USB1_CON_CC1 1 2 SC390P50V2KX-1-GP
3D3V_S5_KBC DY 3D3V_S5_KBC I2C_SDA_SCB3/P3.1 37 CCG6_ID_1 C7208
I2C_SCL_SCB3/P3.2 12
UPD1_SMBDA_Q 3 4 EC_I2C_SDA_PD P3.3 32 UPD1_SMBCLK_Q
2N7002KDW-1-GP
I2C_SCL_SCB0/P4.0
I2C_SDA_SCB0/P4.1
33 UPD1_SMBDA_Q PD to EC
75.27002.F7C
2nd = 075.27002.0E7C CYPD6127-48LQXI-GP
3rd =1 075.07002.0A7C
2
R7253 0R0201-PAD-GP
MODID Setting
3D3V_VDDD 3D3V_VDDD
3D3V_VDDD 3D3V_S5
1
MODID1 MODID2
R7213 R7215
1
DY 1KR2J-1-GP 4K7R1J-GP
0x08 R7256
100KR2J-1-GPDY
R7257
100KR1J-GP
2
3D3V_VDDD 3D3V_VDDD
CCG6_I2C_ADDR PD_XRES
2
20201027(DVT1)
D7201 Follow vendor review value
1
1
C7214 (TBT)
RB520S30-GP
SCD1U25V2KX-1-DL-GP
DY
R7201 DY PROCHOT#_CPU A K CCG6_PROCHOT# R7207 -> 300K R7216
715KR2F-GP
R7207
300KR2F-GP
1KR2J-1-GP R7208 -> 100K
1
TBT_SEL
83.R2003.A8M (NON_TBT)
2
2
2ND = 083.52030.008F R7207 -> 715K CCG6_ID_1 CCG6_ID_2
3rd = 083.52030.0C8F R7208 -> 100K
B B
1
R7226 1 DY 2 0R2J-2-GP
R7218 R7208
100KR2F-L1-GP 100KR2F-L1-GP
2
SWD Programming
20191218
3D3V_S5 Layout requre
3D3V_VDDD
DY 20200212
change RN7204 to RN7101
1
DY 2 2K2R1J-GP UPD1_SMBDA_Q 1
R7209 TP7201
R7211 1 2 2K2R1J-GP UPD1_SMBCLK_Q
1
TP7202
20200221(DVT1)
Remove R7214
PD_XRES 1
1 2 2K2R1J-GP CCG6_I2C_INT# TP7203
R7267
CCG6_I2C_ADDR 1
TP7204
RETIMER_PWREN_R 1
TP7205
A A
R7268 1 2 2K2R2J-2-GP TBT_PD_ALERT#
20191220
Follow 13" TGL
3D3V_VDDD <Core Design>
1 2 2K2R1J-GP BB_I2C_SCL
Wistron Corporation
R7212 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
R7214 1 2 2K2R1J-GP BB_I2C_SDA Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
EXT IO (Thunderbolt(2/3)/Type C CC Logic)
Size
Size Document
DocumentNumber
Number Rev
Rev
A2
Cyborg TGL SC
Date:
Sheet 72 of 105
5 4 3 2 1
5 4 3 2 1
Main Func = TypeC USB1 20200504

A1 B1
USB1
20V_VCCPD_VBUS 20V_VCCPD_VBUS
USB1_SSTX_CON_P0 A2 GND GND B2 USB1_SSTX_CON_P1 Remove C7302 C7304
20V_VCCPD_VBUS
[71] USB1_SSTX_CON_P0
USB1_SSTX_CON_N0 A3 SSTXP1 SSTXP2 B3 USB1_SSTX_CON_N1 Change C7301 C7302 to 0402 size
A4 SSTXN1 SSTXN2 B4
[71] USB1_SSTX_CON_N0 VBUS#A4 VBUS#B4
USB1_CON_CC1 A5 B5 USB1_CON_CC2
[71] USB1_SSTX_CON_P1 CC1 CC2
USB1_USB20_CONT_P A6 B6 USB1_USB20_CONB_P
[71] USB1_SSTX_CON_N1 DP1 DP2
USB1_USB20_CONT_N A7 B7 USB1_USB20_CONB_N
USB1_CON_SBU1 DN1 DN2 USB1_CON_SBU2 C7301 C7303 C7307
A8 B8
1
[71] USB1_SSRX_AR_P0 C7308 C7309
SCD1U25V2KX-1-DL-GP
SCD1U25V2KX-1-DL-GP
RFU1 RFU2
1
SC10U25V3MX-5-GP
A9 B9 DY
SCD1U25V2KX-1-DL-GP
SCD1U25V2KX-1-DL-GP
[71] USB1_SSRX_AR_N0 VBUS#A9 VBUS#B9
USB1_SSRX_AR_N1 A10 B10 USB1_SSRX_AR_N0 FC7301 FC7302
[71] USB1_SSRX_AR_P1 SSRXN2 SSRXN1
USB1_SSRX_AR_P1 A11 B11 USB1_SSRX_AR_P0
SC33P25V1JN-GP
SC33P25V1JN-GP
2
D [71] USB1_SSRX_AR_N1 D
SSRXP2 SSRXP1
2
1
1
A12 B12
GND GND
[72] USB1_USB20_CMCT_P DY DY DY DY
[72] USB1_USB20_CMCT_N 20191216
20191211
2
For layout requirement
[72] USB1_USB20_CMCB_P Follow Connector list 1210
[72] USB1_USB20_CMCB_N
13
CHASSIS#13 14
[72] USB1_CON_CC1 CHASSIS#14
[72] USB1_CON_CC2 15
CHASSIS#15 16
CHASSIS#16
[72] USB1_CON_SBU1
[72] USB1_CON_SBU2
SKT-USB28-46-GP
062.10009.M015
[71] USB1_SSTX_CON_N1_R
[71] USB1_SSRX_AR_P1_R 2nd = 062.10009.M202
[71] USB1_SSTX_CON_N0_R 2020/02/29:swap EL7302/EL7301
[71] USB1_SSRX_AR_P0_R
DLM0NSN900HY2D-GP DLM0NSN900HY2D-GP
USB1_USB20_CMCT_P 2 1 USB1_USB20_CONT_P USB1_USB20_CMCB_P 2 1 USB1_USB20_CONB_P
USB1_USB20_CMCT_N 3 4 USB1_USB20_CONT_N USB1_USB20_CMCB_N 3 4 USB1_USB20_CONB_N
EL7302 EL7301
C
068.09002.2001 068.09002.2001 C
2nd = 68.02002.061 2nd = 68.02002.061
20200213
Follow EMC requestment
USB1_USB20_CONB_N
USB1_USB20_CONB_P
USB1_USB20_CONT_N
USB1_USB20_CONT_P
USB1_CON_SBU2
USB1_CON_SBU1
USB1_CON_CC2
USB1_CON_CC1
USB1_CON_SBU1
USB1_CON_SBU2
083.5V0H1.00AF 083.5V0H1.00AF 083.5V0H1.00AF 083.5V0H1.00AF 083.5V0H1.00AF 083.5V0H1.00AF 083.5V0H1.00AF 083.5V0H1.00AF
B 2nd = 083.58017.00AF 2nd = 083.58017.00AF 2nd = 083.58017.00AF 2nd = 083.58017.00AF 2nd = 083.58017.00AF 2nd = 083.58017.00AF 2nd = 083.58017.00AF 2nd = 083.58017.00AF
2
2
B
2
20191212
ED7301 ED7302 ED7303 ED7304 ED7305 ED7306 ED7307 ED7308 Follow Nakia
DY DY
1
C7305 C7306
SC100P50V2JN-3-LL-GP
SC100P50V2JN-3-LL-GP
1
1
1
2
USB1_SSTX_CON_P0_R
USB1_SSTX_CON_N0_R
USB1_SSRX_AR_P0_R
USB1_SSRX_AR_N0_R
USB1_SSTX_CON_P1_R
USB1_SSTX_CON_N1_R
USB1_SSRX_AR_P1_R
USB1_SSRX_AR_N1_R
083.5V0H1.00AF 083.5V0H1.00AF 083.5V0H1.00AF 083.5V0H1.00AF 083.5V0H1.00AF 083.5V0H1.00AF 083.5V0H1.00AF 083.5V0H1.00AF

A 2nd = 083.58017.00AF 2nd = 083.58017.00AF 2nd = 083.58017.00AF 2nd = 083.58017.00AF 2nd = 083.58017.00AF 2nd = 083.58017.00AF 2nd = 083.58017.00AF 2nd = 083.58017.00AF <Core Design> A
2
ED7309 ED7310 ED7311 ED7312 ED7313 ED7314 ED7315 ED7316
Wistron Corporation

1
Title
Title
EXT IO (Thunderbolt(3/3)/Type C Conn)
Size
Size DocumentNumber
Document Number Rev
Rev
A3
Cyborg TGL SC
Date: Sheet
Sheet 73 of 105
5 4 3 2 1
5 4 3 2 1
[72] PD_VBUS_C_CTRL1
[24] TYPEC_DCIN1_EN#
[44] U7419_FLTB
D D
20V_VCCPD_VBUS 20V_VCCPD_VBUS 20V_VCCPD_SW_VBUS
D7401 PG8622 1 2 GAP-CLOSE-PWR-3-GP

2nd = 083.08515.00AF
083.04520.00AF
AZ4520-01F-R7G-GP
PG8623 1 2 GAP-CLOSE-PWR-3-GP
A
3D3V_VDDD
1
5V_S5 PWR_USB_ADT
20V_VCCPD_SW_VBUS R7414
10KR2J-3-GP
1
R7412
2
10KR2J-3-GP
+SDC_IN
U7419
2
C U7418 C
12 1 8 D S 1
11 OVD/NC12 VOUT1 2 7 D S 2
VCC_O/NC11 VOUT2
1
10 3 NCP: VIH=1.5V ; VIL=0.45V 6 D S 3
VIN10 NC3
1
1
1
9 4 AOZ: VIH=1.4V ; VIL=0.6V 5 D R7406 R7430
R7416 U7419_FLTB 8 VIN9 NC4/CAP 5 U7419_EN R7415 C7405 C7407 R7401 G
PG/FLTB EN 100KR1F-GP 1MR1J-GP
U7419_SS
1
7 6
SC10U25V3MX-5-GP
SC10U25V3MX-5-GP
C7401
0R5J-5-GP 0R5J-5-GP 1MR1F-GP AONR21321-GP
SR/SS GND
S
2
C7406 C7404 20V PATH NCP 20V PATH NCP DY DY 084.21321.0037
2
U7419_THM2 U7419_THM1
1
2
14 13
SC1U25V3KX-1-DLGP
SC1U25V3KX-1-DLGP
R7404
THM_2 THM_1 2nd = 084.20P03.0033
2
2
2
1MR1J-GP G
3rd = 084.03307.0037 Q7408
U7419_CAP
2
1
1
1
C7403 PAD-14P-3033-GP PJA3415AE-GP
1
1
SC5600P50V2KX-1-GP 1st = 074.01394.M001 R7413 084.03415.0C31
D
20V PATH AOZ C7402 100KR1F-GP 2nd = 84.03327.031
D
2
SC1KP50V2KX-1DLGP
20191218
2
1 2 LPS_SW_B
20V PATH AOZ Q7401
2
2N7002K-2-GP-U R7403 For ESD SPEC
84.2N702.J31 0R0402-PAD-7-NP-GP
Close to U7419
LPS_SW
20191223
2ND = 084.27002.0N31 For High limit
3rd = 084.27002.0L31
4th = 084.07002.0C31
S
LPS_SW_C
2
R7402
1
200KR1F-GP
3D3V_S5 R7405
100KR1F-GP
1
1
2
LPS_SW_A
R7427
100KR1F-GP Q7406
3 4
2
D2 S2
TYPEC_DCIN1_EN# 2 5 PD_VBUS_C_CTRL1_R
1 R7422
G1 G2
PD_VBUS_C_EN 2
1 6 LPS_SW_D
1MR1J-GP S1 D1
Q7407 PJT138KA-GP
Form EC (CY18 add) 075.00138.0A7C
3 4
D2 S2 2nd = 075.00139.007C
TYPEC_DCIN1_EN# 2 5 3rd = 075.00138.0F7C
G1 G2
1
1 S1 D1
6
R7428
R7407
100KR1F-GP
PJT138KA-GP 1 2
075.00138.0A7C
2
2nd = 075.00139.007C 200KR1F-GP

3rd = 075.00138.0F7C
20V_VCCPD_VBUS
B B
1
Q7405 R7426
R7425
100KR1F-GP
1 2 PD_VBUS_C_EN_A 3 4
20V_VCCPD_VBUS
100KR1F-GP
2
PD_VBUS_C_CTRL1 1 2 PD_VBUS_C_CTRL1_R 2 5 PD_VBUS_C_CTRL1_R_R
Note:ZZ.27002.F7C01
20191128
Form PD control R7410
10KR2J-3-GP 1 6 Change net name
R7411
1
2N7002KDW-1-GP
750KR1J-GP
R7408
75.27002.F7C
2nd = 075.27002.0E7C 200KR1F-GP
3rd = 075.07002.0A7C
2
A A
<Core Design>
Wistron Corporation
TitleTitle
GPU(2/5)DIGITALOUT
SizeSize Document
Document Number
Number Rev Rev
A1
Cyborg TGL
Thursday, January 14, 2021
SC
Date:
Date: Sheet
Sheet 74 of 105
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Cyborg TGL SC
5 4 3 2 1
5 4 3 2 1
Main Func = dGPU

dGPU Reset
1D8V_AON_S0
U7601
DGPU_HOLD_RST# 1
5
PCH_PLTRST# 2
4 SYS_PEX_RST_MON#
3
OPS
1
R7604 TC7SZ08FU-LJ-CT-GP
10KR2J-3-GP 073.7SZ08.000G
1
OPS 2nd = 73.7SZ08.DAH R7606
2
100KR2J-1-GP
OPS
2
D D
[18] GFX_CLK_CPU_P
[18] GFX_CLK_CPU_N
1V_VGA_S0
[18] DGPU_HOLD_RST# 1.05V +/- 30mV
[17,61,62,63,66,71,91] PCH_PLTRST# 3.3A
1D8V_VGA_S0 1D8V_AON_S0
GPU1A 1 OF 14
1/14 PCI_EXPRESS
Place under GPU Midway Place near GPU
2
GP107S TU117S
R7603 TU117S GP107S

AA22
Q7601 G AA14 PEX_DVDD PEX_CVDD
[18] CLK_PCIE_PEG_REQ# OPS 10KR2J-3-GP
PEX_WAKE#
NC
CLK_PCIE_PEG_REQ# D SYS_PEX_RST_MON# R7613 1 OPS 2 GPU_PEX_RST# AC7 AB23

[16] GFX_PCIE_RX_P0 OPS PEX_RST# PEX_DVDD_2
1
[16] GFX_PCIE_RX_N0 0R0402-PAD-7-NP-GP AC24
PEX_DVDD_3
1
S GPU_CLKREQ# AC6 AD25 C7612 C7610 C7609 C7617 C7618 C7625 C7623 C7626 C7615 C7613 C7611
PEX_CLKREQ# PEX_DVDD_4 AE26
OPS
SC1U10V2KX-1DLGP
OPS
SC4D7U6D3V2MX-1-GP
OPS_N18
SC1U10V2KX-1DLGP
OPS_N18
SC1U10V2KX-1DLGP
OPS_N18
SC1U10V2KX-1DLGP
OPS
SC10U6D3V3MX-DL-GP
OPS
SC10U6D3V3MX-DL-GP
OPS
DY
OPS_N17
SC4D7U6D3V2MX-1-GP
OPS_N17
SC4D7U6D3V2MX-1-GP
[16] GFX_PCIE_TX_P0 GFX_CLK_CPU_P PEX_DVDD_5
[16] GFX_PCIE_TX_N0
AE8 AE27
PJA138KA-GP PEX_REFCLK PEX_DVDD_6
2
GFX_CLK_CPU_N AD8
PEX_REFCLK*
[16] GFX_PCIE_RX_P1 084.00138.0A31
GFX_PCIE_RX_P0 C7601 1 GFX_PCIE_RX_CON_P0
[16] GFX_PCIE_RX_N1 2nd = 84.05067.031 GFX_PCIE_RX_N0 C7602 1
OPS22 SCD22U10V1KX-1-GP
SCD22U10V1KX-1-GP GFX_PCIE_RX_CON_N0
AC9
AB9 PEX_TX0
OPS PEX_TX0*
[16] GFX_PCIE_TX_P1 GFX_PCIE_TX_P0
[16] GFX_PCIE_TX_N1
AG6
GFX_PCIE_TX_N0 PEX_RX0
AG7
PEX_RX0* PEX_HVDD_1
AA10 (NEW ADDED)
[16] GFX_PCIE_RX_P2 AA12
GFX_PCIE_RX_P1 C7603 1 2 SCD22U10V1KX-1-GP GFX_PCIE_RX_CON_P1 AB10 PEX_HVDD_2 AA13
[16] GFX_PCIE_RX_N2 GFX_PCIE_RX_N1 C7604 1 OPS2 SCD22U10V1KX-1-GP GFX_PCIE_RX_CON_N1 AC10 PEX_TX1 PEX_HVDD_3 AA16
OPS PEX_TX1* PEX_HVDD_4 AA18
[16] GFX_PCIE_TX_P2 GFX_PCIE_TX_P1 PEX_HVDD_5
[16] GFX_PCIE_TX_N2 AF7 AA19
GFX_PCIE_TX_N1 AE7 PEX_RX1 PEX_HVDD_6 AA20
PEX_RX1* PEX_HVDD_7 AA21
[16] GFX_PCIE_RX_P3 GFX_PCIE_RX_P2 C7605 1 GFX_PCIE_RX_CON_P2 PEX_HVDD_8 1D8V_VGA_S0
[16] GFX_PCIE_RX_N3 GFX_PCIE_RX_N2 C7606 1
OPS22 SCD22U10V1KX-1-GP
SCD22U10V1KX-1-GP GFX_PCIE_RX_CON_N2
AD11
AC11 PEX_TX2 PEX_HVDD_9
AB22
AC23
OPS PEX_TX2* PEX_HVDD_10 AD24
[16] GFX_PCIE_TX_P3 GFX_PCIE_TX_P2 PEX_HVDD_11
[16] GFX_PCIE_TX_N3 AE9 AE25 Place under GPU Midway Place near GPU
GFX_PCIE_TX_N2 AF9 PEX_RX2 PEX_HVDD_12 AF26
PEX_RX2* PEX_HVDD_13 AF27
C GFX_PCIE_RX_P3 C7607 1 GFX_PCIE_RX_CON_P3 PEX_HVDD_14 C
2 SCD22U10V1KX-1-GP AC12
GFX_PCIE_RX_N3 C7608 1 OPS2 SCD22U10V1KX-1-GP GFX_PCIE_RX_CON_N3 AB12 PEX_TX3
OPS PEX_TX3*
GFX_PCIE_TX_P3 AG9
PEX_RX3
1
GFX_PCIE_TX_N3 AG10 C7614 C7622 C7630 C7631 C7619 C7629 C7627 C7628 C7624 C7621 C7620
PEX_RX3*
DY
SC4D7U6D3V2MX-1-GP
OPS
SC10U6D3V3MX-DL-GP
OPS
SC10U6D3V3MX-DL-GP
OPS
DY
OPS_N17
SC4D7U6D3V2MX-1-GP
OPS_N17
SC4D7U6D3V2MX-1-GP
OPS
OPS
OPS
OPS
AB13
SC1U10V1MX-1-GP
SC1U10V1MX-1-GP
SC1U10V1MX-1-GP
SC1U10V1MX-1-GP
PEX_TX4
2
AC13
PEX_TX4*
AF10
AE10 PEX_RX4
PEX_RX4*
AD14
AC14 PEX_TX5 AA8
PEX_TX5* PEX_PLL_HVDD_1 AA9
AE12 PEX_PLL_HVDD_2
AF12 PEX_RX5
PEX_RX5*
AC15
AB15 PEX_TX6
PEX_TX6*
AG12
AG13 PEX_RX6
PEX_RX6*
AB16
AC16 PEX_TX7
PEX_TX7* 1U 0201*1 X6S
Place under GPU 1D8V_VGA_S0
AF13 (NEW ADDED)
OPS
AE13 PEX_RX7
PEX_RX7*
AD17
AC17 PEX_TX8
PEX_TX8*
1
C7644 C7616
AE15
OPS_N18
OPS_N17
SCD47U6D3V2KX-DL-GP
SCD1U25V2KX-1-DL-GP
AF15 PEX_RX8
PEX_RX8*
2
AC18
AB18 PEX_TX9
PEX_TX9*
AG15
PEX LANES 15 - 4 ARE DEFEATURED

AG16 PEX_RX9
PEX_RX9*
AB19
AC19 PEX_TX10
B B
PEX_TX10*
AF16
AE16 PEX_RX10
PEX_RX10*
AD20
AC20 PEX_TX11
PEX_TX11*
AE18
AF18 PEX_RX11
PEX_RX11*
AC21
AB21 PEX_TX12
PEX_TX12*
AG18
AG19 PEX_RX12
PEX_RX12*
AD23
AE23 PEX_TX13
PEX_TX13*
AF19
AE19 PEX_RX13
PEX_RX13*
AF24
AE24 PEX_TX14
PEX_TX14*
AE21
AF21 PEX_RX14
PEX_RX14*
AG24
AG25 PEX_TX15
PEX_TX15*
AG21
AG22 PEX_RX15
PEX_RX15*
R7601
AF25 PEX_TERMP 1 OPS 2
PEX_TERMP
2K49R2F-GP
N18S-G5-A1-GP
A A
<Core Design>
Wistron Corporation
Title
Title
GPU(1/5)PEG
SizeCustomDocument Number Rev
Cyborg TGL SC
5 4 3 2 Date: 1 Sheet
5 4 3 2 1
Main Func = dGPU
D D
GPU1J 4 OF 14
4/14 IFPAB
1V_VGACORE1_S0 GPU1H 6 OF 14 1V_VGACORE1_S0
DVI HDMI DP 6/14 XVDD
SL/DL
AC4 G1 N4
IFPA_L3* AC3 G2 XVDD_1 XVDD_36 N5 GPU1D 5 OF 14
TXC/TXC
IFPA_L3 G3 XVDD_2 XVDD_37 N7 5/14 NC
AA6 G4 XVDD_3 XVDD_38 P3
IFPAB_RSET Y3 G5 XVDD_4 XVDD_39 P4
TXD0/0
IFPA_L2* Y4 G6 XVDD_5 XVDD_40 P6
IFPA_L2 G7 XVDD_6 XVDD_41 R1
H3 XVDD_7 XVDD_42 R2 AA15
AA2 H4 XVDD_8 XVDD_43 R3 AB8 NC_2
TXD1/1
W7 IFPA_L1* AA3 H6 XVDD_9 XVDD_44 R4 AD10 NC_4
IFPAB_PLLVDD IFPA_L1 J1 XVDD_10 XVDD_45 R5 AD7 NC_5
J2 XVDD_11 XVDD_46 R6 AE22 NC_6
AA1 J3 XVDD_12 XVDD_47 R7 AE3 NC_7
TXD2/2
IFPA_L0* AB1 J4 XVDD_13 XVDD_48 T1 AE4 NC_8
IFPA_L0 XVDD_14 XVDD_49 NC_9
OPS
J5 T2 AF2
IFPA_AUX_SDA*
AA5
J6
J7
XVDD_15
XVDD_16
XVDD_17
XVDD_50
XVDD_51
XVDD_52
T3
T4
AF22
AF3
NC_10
NC_11
NC_12
OPS
AA4 K1 T5 AF4
IFPA_AUX_SCL K2 XVDD_18 XVDD_53 T6 AG3 NC_13
K3 XVDD_19 XVDD_54 T7 D10 NC_14
C AB4 K4 XVDD_20 XVDD_55 U3 E10 NC_15 C
IFPB_L3* AB5 K5 XVDD_21 XVDD_56 U4 F6 NC_16
TXC
IFPB_L3 K6 XVDD_22 XVDD_57 U6 W5 NC_21
K7 XVDD_23 XVDD_58 V1 F5 NC_22
W6 AB2 L3 XVDD_24 XVDD_59 V2 NC_20
TXD0/3
IFP_IOVDD_1 IFPB_L2* AB3 L4 XVDD_25 XVDD_60 V3
Y6 IFPB_L2 M1 XVDD_26 XVDD_61 V4
IFP_IOVDD_2 M2 XVDD_27 XVDD_62 V5
AD2 M3 XVDD_28 XVDD_63 V6
TXD1/4
IFPB_L1* AD3 M4 XVDD_29 XVDD_64 V7
IFPB_L1 M5 XVDD_30 XVDD_65 W1 N18S-G5-A1-GP
M7 XVDD_31 XVDD_66 W2
AD1 N1 XVDD_32 XVDD_67 W3
TXD2/5
IFPB_L0* AE1 N2 XVDD_33 XVDD_68 W4
IFPB_L0 N3 XVDD_34 XVDD_69
XVDD_35
AD5
IFPB_AUX_SDA*
IFPB_AUX_SCL
AD4
OPS
IFPAB N18S-G5-A1-GP
N18S-G5-A1-GP
B B
A <Core Design> A
Wistron Corporation
Title
Title
Size
GPU(2/5)DIGITALOUT
Document Number
Number Rev
Size Document Rev
A3
Cyborg TGL SC
Date: Sheet
Sheet 77 of 105
5 4 3 2 1
5 4 3 2 1
Main Func = dGPU

GPU1B 2 OF 14
2/14 FBA
FBA_D0 E18
FBA_D1 F18 FBA_D0
[81] FBA_DQM0 FBA_D2 E16 FBA_D1
[81] FBA_D[0..31] [81] FBA_DQM1 FBA_D3 F17 FBA_D2
[81] FBA_DQM2 FBA_D4 D20 FBA_D3
[82] FBA_DQM4 FBA_D6 F20 FBA_D5
FBA_D10 F15 FBA_D9
FBA_D11 F13 FBA_D10
[81] FBA_EDC0 FBA_D12 C13 FBA_D11
[81] FBA_EDC1 FBA_D13 B13 FBA_D12
[81] FBA_EDC2 FBA_D14 E13 FBA_D13 C27 FBA_CMD0
[81] FBA_EDC3 FBA_D15 D13 FBA_D14 FBA_CMD0 C26 FBA_CMD1 1D35V_VGA_S0
[82] FBA_EDC4 FBA_D16 B15 FBA_D15 FBA_CMD1 E24 FBA_CMD2
[82] FBA_EDC5 FBA_D17 C16 FBA_D16 FBA_CMD2 F24 FBA_CMD3
[82] FBA_EDC6 FBA_D18 A13 FBA_D17 FBA_CMD3 D27 FBA_CMD4
[82] FBA_EDC7 FBA_D19 A15 FBA_D18 FBA_CMD4 D26 FBA_CMD5
FBA_D20 FBA_D19 FBA_CMD5 FBA_CMD6
2
[81] FBA_CMD0
B18 F25 R7816 R7824
FBA_D21 A18 FBA_D20 FBA_CMD6 F26 FBA_CMD7
10KR2F-2-GP
10KR2F-2-GP
[81] FBA_CMD1 FBA_D21 FBA_CMD7
[81] FBA_CMD2
FBA_D22
FBA_D23
A19
FBA_D22 FBA_CMD8
F23 FBA_CMD8
FBA_CMD9
OPS OPS
[81] FBA_CMD3
C19 G22
FBA_D24 B24 FBA_D23 FBA_CMD9 G23 FBA_CMD10
D [81] FBA_CMD4 D
FBA_D24 FBA_CMD10
1
FBA_D25 C23 G24 FBA_CMD11 FBA_CMD14
[81] FBA_CMD5 FBA_D26 FBA_D25 FBA_CMD11 FBA_CMD12 FBA_CMD30
[81] FBA_CMD6
A25 F27
FBA_D27 A24 FBA_D26 FBA_CMD12 G25 FBA_CMD13
[81] FBA_CMD7 FBA_D28 FBA_D27 FBA_CMD13 FBA_CMD14
[81] FBA_CMD8
A21 G27
FBA_D29 B21 FBA_D28 FBA_CMD14 G26 FBA_CMD15 FBA_CMD29
[81] FBA_CMD9 FBA_D30 FBA_D29 FBA_CMD15 FBA_CMD16 FBA_CMD13
[81] FBA_CMD10
C20 M24
FBA_D31 C21 FBA_D30 FBA_CMD16 M23 FBA_CMD17
[81] FBA_CMD12
R22 K24
FBA_D33 FBA_D32 FBA_CMD18 FBA_CMD19
2
[81] FBA_CMD13
R24 K23 R7820 R7821
FBA_D34 T22 FBA_D33 FBA_CMD19 M27 FBA_CMD20
10KR2F-2-GP
10KR2F-2-GP
[81] FBA_CMD15
FBA_D35
FBA_D36
R23
FBA_D35 FBA_CMD21
M26 FBA_CMD21
FBA_CMD22
OPS OPS
[82] FBA_CMD16
N25 M25
[82] FBA_D[32..63] FBA_D37 N26 FBA_D36 FBA_CMD22 K26 FBA_CMD23
1
FBA_D38 N23 K22 FBA_CMD24
[82] FBA_CMD19
N24 J23
FBA_D40 V23 FBA_D39 FBA_CMD25 J25 FBA_CMD26
[82] FBA_CMD21
V22 J24
FBA_D42 T23 FBA_D41 FBA_CMD27 K27 FBA_CMD28
[82] FBA_CMD23
U22 K25
FBA_D44 Y24 FBA_D43 FBA_CMD29 J27 FBA_CMD30
[82] FBA_CMD25
AA24 J26
FBA_D46 Y22 FBA_D45 FBA_CMD31 B19 FBA_CMD32 1
[82] FBA_CMD26 FBA_D47 FBA_D46 FBA_CMD32 FBA_CMD33 TP9105
[82] FBA_CMD27
AA23 GP107S F22 1
FBA_D48 AD27 FBA_D47 FBA_CMD34 FBA_CMD33 J22 FBA_CMD35 1 TP9106
[82] FBA_CMD28 FBA_D49 FBA_D48 FBA_CMD35 TP9107
[82] FBA_CMD29
AB25
FBA_D50 AD26 FBA_D49
[82] FBA_CMD30 FBA_D51 FBA_D50
[82] FBA_CMD31
AC25
FBA_D52 AA27 FBA_D51
FBA_D53 AA26 FBA_D52
[81] FBA_CLK0P FBA_D54 FBA_D53
[81] FBA_CLK0N
W 26
FBA_D55 Y25 FBA_D54
[82] FBA_CLK1P FBA_D56 FBA_D55
[82] FBA_CLK1N
R26
FBA_D57 T25 FBA_D56
FBA_D58 N27 FBA_D57
FBA_D59 R27 FBA_D58 D24 FBA_CLK0P
FBA_D60 V26 FBA_D59 FBA_CLK0 D25 FBA_CLK0N
FBA_D61 V27 FBA_D60 FBA_CLK0* N22 FBA_CLK1P
[81] FBA_WCK01 FBA_D62 FBA_D61 FBA_CLK1 FBA_CLK1N
[81] FBA_WCK01#
W 27 M22
FBA_D63 W 25 FBA_D62 FBA_CLK1*
[81] FBA_WCK23 FBA_D63
[81] FBA_WCK23#
[82] FBA_WCK45 FBA_DQM0
[82] FBA_WCK45#
D19
FBA_DQM1 D14 FBA_DQM0 D18 FBA_WCK01
[82] FBA_WCK67 FBA_DQM2 FBA_DQM1 FBA_W CK01 FBA_WCK01#
[82] FBA_WCK67#
C17 C18
FBA_DQM3 C22 FBA_DQM2 GP107S FBA_W CK01* A17
FBA_DQM4 P24 FBA_DQM3 N/A FBA_W CKB01 A14
FBA_DQM5 W 24 FBA_DQM4 N/A FBA_W CKB01*
FBA_DQM6 AA25 FBA_DQM5 D17 FBA_WCK23
FBA_DQM7 U25 FBA_DQM6 FBA_W CK23 D16 FBA_WCK23#
FBA_DQM7 FBA_W CK23* A23
N/A FBA_W CKB23 A20
FBA_EDC0 E19 N/A FBA_W CKB23*
FBA_EDC1 C15 FBA_DQS_W P0
FBA_EDC2 B16 FBA_DQS_W P1 T24 FBA_WCK45
FBA_EDC3 B22 FBA_DQS_W P2 FBA_W CK45 U24 FBA_WCK45#
FBA_EDC4 R25 FBA_DQS_W P3 FBA_W CK45* AC27
FBA_EDC5 W 23 FBA_DQS_W P4 N/A FBA_W CKB45 Y27
FBA_EDC6 AB26 FBA_DQS_W P5 N/A FBA_W CKB45*
C FBA_EDC7 T26 FBA_DQS_W P6 C
FBA_DQS_W P7 V24 FBA_WCK67
FBA_W CK67 V25 FBA_WCK67#
TU117S GP107S
F19 FBA_W CK67* U27
C14 FBA_DQS_RN0FBA_DQS_RN0 N/A FBA_W CKB67 P27
A16 FBA_DQS_RN1FBA_DQS_RN1 N/A FBA_W CKB67*
A22 FBA_DQS_RN2FBA_DQS_RN2
P25 FBA_DQS_RN3FBA_DQS_RN3
W 22 FBA_DQS_RN4FBA_DQS_RN4
AB27 FBA_DQS_RN5FBA_DQS_RN5
T27 FBA_DQS_RN6FBA_DQS_RN6
FBA_DQS_RN7FBA_DQS_RN7
1D8V_VGA_S0
62mA 4.7U 0603*2 X6S

F16
FB_PLL_AVDD_1 22U 0603*1 X6S
1U 0201*1 X6S
P22 Place under GPU Place near GPU L7801
FB_PLL_AVDD_2
35mA FB_PLLVDD_16mil OPS
FB_REFPLL_AVDD
H22 1 ( ( 2
BLM18KG300TN1D-GP
CHIP BEAD BLM18KG300TN1D MURATA
C7809 C7807 C7811 Place Under GPU 68.00084.H41
1
C7803 1U 0201*1 X6S 2nd = 68.00334.051
SC4D7U6D3V2MX-1-GP
SC4D7U6D3V2MX-1-GP
OPS
OPS
SC1U10V1MX-1-GP
OPS OPS OPS
1
C7808 C9117 C9118
FB_VREF D23
FB_VREF
OPS
OPS
OPS
SC1U10V1MX-1-GP
SC1U10V1MX-1-GP
SC1U10V1MX-1-GP
2
2
N18S-G5-A1-GP
1
R7802 C7822
49D9R2F-GP SC3D9P50V2CN-1DLGP
2
OPS_N18 OPS_N18
2
1.35V +/- 3%
1D35V_VGA_S0 4.88A
1D35V_VGA_S0
1U 0201*6 X6S Partition A

GPU1E 12 OF 14 10U 0603*2 X6S Place under GPU
B 12/14 FBVDDQ B
B26 C7802 C7805

C25 FBVDDQ_01
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
E23 FBVDDQ_02
FBVDDQ_03 1
1
E26 C7801 C7804 C7806 C7810 C7813 C7816
F14 FBVDDQ_04
F21 FBVDDQ_05
OPS
OPS
OPS
OPS
OPS
OPS
SC1U10V1MX-1-GP
SC1U10V1MX-1-GP
SC1U10V1MX-1-GP
SC1U10V1MX-1-GP
SC1U10V1MX-1-GP
SC1U10V1MX-1-GP
FBVDDQ_06 OPS OPS
2
2
G13
G14 FBVDDQ_07
G15 FBVDDQ_08
G16 FBVDDQ_09
G18 FBVDDQ_10
G19 FBVDDQ_11
G20 FBVDDQ_12
G21 FBVDDQ_13
FBVDDQ_14 22U 0603*1 X6S
L22 1U 0201*2 X6S
L24 FBVDDQ_19
FBVDDQ_20 10U 0603*1 X6S Partition B Place under GPU
L26
M21 FBVDDQ_21
N21 FBVDDQ_22
R21 FBVDDQ_23
T21 FBVDDQ_24
FBVDDQ_25
1
V21 C7818 C7820 C7829 C7833

W 21 FBVDDQ_26
SC22U6D3V3MX-17-GP
SC10U6D3V3MX-DL-GP
H24 FBVDDQ_27
OPS
OPS
SC1U10V1MX-1-GP
SC1U10V1MX-1-GP
FBVDDQ_15 OPS OPS

2
H26
J21 FBVDDQ_16
K21 FBVDDQ_17
FBVDDQ_18
22U 0603*2 X6S 22U 0603*5 X6S

Place near GPU Place near GPU
OPS C7815 C7817 C7819 C7821 C7823 C7824 C7826

1
1
SC22U6D3V3MX-17-GP
SC22U6D3V3MX-17-GP
SC22U6D3V3MX-9-GP-U
SC22U6D3V3MX-9-GP-U
SC22U6D3V3MX-9-GP-U
SC22U6D3V3MX-9-GP-U
SC22U6D3V3MX-9-GP-U
DY DY DY DY DY
Under GPU OPS OPS
2
1D35V_VGA_S0
R7805
D22 FB_CAL_PD_VDDQ 2 1
FB_CAL_PD_VDDQ
OPS
40D2R2F-GP
C24 FB_CAL_PU_GND
FB_CAL_PU_GND
1
A A
B25 FB_CAL_TERM_GND R7807
FB_CAL_TERM_GND 40D2R2F-GP
1
R7806 R7812
OPS
2
40D2R2F-GP 60D4R2F-GP
OPS_N18 OPS_N17
2
N18S-G5-A1-GP
<Core Design>
Wistron Corporation
Title
GPU(3/5)VRAMI/F
Custom
Cyborg TGL SC
5 4 3 2 1
5 4 3 2 1
Main Func = dGPU

1D8V_AON_S0
1
R7933 1D8V_AON_S0
1D8V_VGA_S0 PWR_PLLVDD
1D8V_AON_S0 GC6_20 10KR2J-3-GP
4.7U 0603*1 X6S
RN7910 22u 0805*1 X6S
2
GPIO5_GC6_PWR_EN OVERT_GPU#
1U 0201*6 X6S 1U 0402*1 X6S 1U 0201*2 X6S 0.1U 0402*1 X7R
1
1 4 Place near GPU Place under GPU Place under GPU Place under GPU Place under GPU
R7937 3V3_MAIN_EN is an open-drain GPIO. GPIO9_ALERT 2 3 GPU1L 9 OF 14
0R2J-2-GP L7904 OPS 9/14 XTAL_PLL
OPS_N18 SRN10KJ-5-GP 1 ( ( 2 L6
XS_PLLVDD
2
1D8V_N18S_F10
OPS M6
SP_PLLVDD
BLM18KG300TN1D-GP C7901 C7902 F11
GPCPLL_AVDD
1
N6
SC4D7U6D3V2MX-1-GP
C7951 GPU1M 8 OF 14 68.00084.H41
C7909 C7911 C7915 C7905 VID_PLLVDD
8/14 MISC1 2nd = 68.00334.051 OPS OPS
1
OPS_N18
SC1U10V1MX-1-GP
C7914 C7912
SC1U4V1MX-1-NF-GP
SC1U4V1MX-1-NF-GP
SC1U4V1MX-1-NF-GP
DY DY DY
OPS
SC1U10V1MX-1-GP
OPS
SC1U10V1MX-1-GP
SCD1U16V2KX-3DLGP
OPS
2
TU117S GP107S 1D8V_AON_S0 TU117S GP107S
F10 VIDEO_CLK_XTAL_SS A10 C10 N12P_XTAL_OUTBUFF
TS_AVDD NC D9 GPU_SMB_SCL_THM EXT_REFCLK_FL XTAL_SSIN XTAL_OUTBUFF
D
I2CS_SCL D8 GPU_SMB_SDA_THM PDP-06877-006 D
OVERT_GPU# A6 I2CS_SDA RN7904 C11 B10
AE2 OVERT A9 GPU_I2C_SCL_C 4 1 XTAL_IN XTAL_OUT
TS_VREF I2CC_SCL GPU_I2C_SDA_C
1
B9 3 OPS 2 N18S-G5-A1-GP R7902
I2CC_SDA
1
1D8V_AON_S0 3D3V_S0 20PF 5% 50V +/-0.25PF 0402
100KR2F-L1-GP
E12
SRN2K2J-1-GP
RN7905 OPS R7901
OPS R7903
OPS
THERMDN GPU_I2C_SCL_B
2
C9 4 1 1D8V_AON_S0 10KR2J-3-GP 1MR2J-1-GP
I2CB_SCL
2
GPU_I2C_SDA_B XTL_27M_IN_GPU XTL_27M_OUT_GPU
2
F12 C8 3 OPS 2 R7948 1 DY 2
THERMDP I2CB_SDA
2
1
1
R7949 DY 10KR2J-3-GP C7913
SRN2K2J-1-GP 10KR2J-3-GP G SC1U10V1MX-1-GP C7903
2
SCD1U16V1KX-5-GP
GC6_20 OPS_N17
2
D GPU_EVENT# R7904
GC6_20 OPS_N17 X7901
1
F3
TU117S GP107S
GPU_EVENT_GPU# S
OPS1KR2J-1-GP
[3] GPU_EVENT# F4 ADC_IN NC C6 VGA_CORE_VID Q7906 1 4
ADC_IN* GPIO0
1
NC B2 GC6_FB_EN_GPU PJA138KA-GP
[85,86] GPIO5_GC6_PWR_EN GPIO1 GPU_EVENT_GPU#
D6 084.00138.0A31
GPIO2 C7 1D8V_AON_S0
[24,44] GPU_PWR_LEVEL GPIO3
GPIO4
F9 GPIO5_GC6_PWR_EN_GPU 1 R7936 2 GPIO5_GC6_PWR_EN 2nd = 84.05067.031 2 3 XTL_27M_X2
[81] GPIO10_FBVREF
A3 0R0402-PAD-7-NP-GP OPS
GPIO5 A4 VGA_CORE_PSI
GPIO6 GC6_20
1
[85] VGA_CORE_PSI B6
GPIO7 XTAL-27MHZ-192-GP
2
E9 R7905 OPS
GPIO8 GPIO9_ALERT 100KR2J-1-GP
[85] VGA_CORE_VID GPIO9
F8
GPIO10_FBVREF OPS C7907 082.30008.0421 OPS
C5 SC20P50V2JN-1-DL-GP 2ND = 082.30008.0441 C7908
GPIO10
1
E7 D7902 SC20P50V2JN-1-DL-GP
[18,86] GC6_FB_EN GPIO11
2
D7 PWR_LEVEL A K GPU_PWR_LEVEL
GPIO12 B4
3rd = 082.30008.0401
[24,26] EC_SMB_SDA_THM GPIO13 B3
OPS
L1SS355T1G-GP 3D3V_AUX_S5
GPIO14 C3
[24,26] EC_SMB_SCL_THM GPIO15 D5
83.00355.G1F
GPIO16 D4
2nd = 083.00355.0A1F
GPIO17 FP_FUSE
2
C2 R7916 1 2 10KR1J-GP
[80] FP_FUSE GPIO18 F7 OPS_N18 GC6_20R7952
GPIO19 E6 10KR2J-3-GP
GPIO20 C4 1D8V_AON_S0 Q7907
GPIO21 A7
GPIO22
1
B7 VGA_B7 R7917 2 1 1 6 GC6_FB_EN_GPU_L
S1 D1
GPIO23 10KR1F-GP
GC6_FB_EN_GPU 2 5
OPS_N17 G1 OPS G2
N18S-G5-A1-GP
DA-05691-001_V05 P15 GPIO10_FBVREF 3 D2 4
OPS
S2
1
GPIO20/21 NC : for ALL
R7927 3D3V_S0 R7953 1 2
1
10KR2J-3-GP GC6_20 10KR2J-3-GP PJT138KA-GP
R7910 075.00138.0A7C
100KR2J-1-GP
OPS 2nd = 075.00139.007C
2
OPS 3rd = 075.00138.0F7C
2
GC6_FB_EN
1D8V_AON_S0
C 1D8V_VGA_S0 C
4
3
OPS SRN2K2J-1-GP
RN7901
Q7901
1
2
1D8V_AON_S0 1D8V_AON_S0
EC_SMB_SDA_THM 6 D1 S1 1 GPU_SMB_SDA_THM
5 G2 OPS G1 2
1
4 D2 3 R7918 1D8V_AON_S0 ROM_HOLD# R7971 2 1
OPS_N18
10KR1J-GP
S2
10KR1F-GP ROM_WP# R7972 2 1 10KR1J-GP
PJT138KA-GP
OPS_N18 U7902
OPS_N18
2
075.00138.0A7C ROM_CS#_R
2nd = 075.00139.007C 1 8
GPU_SMB_SCL_THM ROM_SO_R 2 CS# VCC 7 ROM_HOLD#
EC_SMB_SCL_THM 3rd = 075.00138.0F7C ROM_WP# 3 SO/SIO1 HOLD#/SIO3 6 ROM_SLK_R ROM_CS# R7906 1
OPS_N18
2 33D2R1F-GP ROM_CS#_R
WP#/SIO2 SCLK ROM_SI_R
1
4 5 OPS_N18
GND SI/SIO0 C7904 ROM_SI R7913 1 2 33D2R1F-GP ROM_SI_R
9_THM SCD1U16V1KX-5-GP OPS_N18
THERMAL_PAD
2
ROM_SO R7930 1 2 0R1J-GP ROM_SO_R
OPS_N18
MX25U8033EZNI-12G-GP ROM_SLK R7931 1
OPS_N18
2 33D2R1F-GP ROM_SLK_R
OPS_N18
072.25803.0B03
2nd = 072.02580.0A03
GPU1N 3 OF 14
3rd = 072.02580.0H01
3/14 JTAG
AE5
AE6 JTAG_TCK
AF6 JTAG_TDI
AD6 JTAG_TDO
N12P_JTAG_TRST AG4 JTAG_TMS
NVJTAG_SEL AD9 JTAG_TRST#
NVJTAG_SEL
1
R7920 R7912
10KR2F-2-GP
OPS10KR2J-3-GP
2
OPS
N18S-G5-A1-GP
B
OPS B
1D8V_AON_S0
1D8V_AON_S0
H_N17S/S_N17S/M_N18S
M_N17S/H_N17S/S_N17S/H_N18S
S_N18S
GPU1K 10 OF 14
R7938 R7925 R7928 10/14 MISC2
1
1
100KR2F-L1-GP
100KR2F-L1-GP
100KR2F-L1-GP
R7919 R7909 R7914

100KR2F-L1-GP
100KR2F-L1-GP
100KR2F-L1-GP
R7951 R7954 R7950

100KR1F-GP 100KR1F-GP 100KR1F-GP
DY DY DY
D12 ROM_CS# OPS_N17 OPS_N17 OPS_N17
ROM_CS#
2
2
B12 ROM_SI
ROM_SI A12 ROM_SO
STRAP0 D1 ROM_SO C12 ROM_SLK
STRAP1 D2 STRAP0 ROM_SCLK
STRAP2 E4 STRAP1
STRAP2
1
STRAP3 E3
STRAP4 D3 STRAP3 R7932 R7934 R7907
STRAP5 C1 STRAP4 100KR1F-GP 10KR1F-GP 100KR1F-GP
STRAP5
M_N17S/S_N17S/H_N18S/S_N18S
M_N17S/H_N17S/M_N18S/S_N18S
M_N17S/H_N17S/S_N17S/M_N18S/H_N18S
OPS OPS_N18 OPS_N18
2
R7939 R7926 R7929 D11 SNN_GPU_BUFRST 1
BUFRST#
1
1
100KR2F-L1-GP
100KR2F-L1-GP
100KR2F-L1-GP
R7908 R7911 R7915

100KR2F-L1-GP
100KR2F-L1-GP
100KR2F-L1-GP
OPS OPS OPS TP7906

TPAD14-OP-GP
2
N18S-G5-A1-GP
OPS
A A
www.teknisi-indonesia.com <Core Design>
Wistron Corporation
Title Title
GPU(4/5)GPIO/STRAP
SizeSize Document Number
Document Number Rev Rev
Custom
Cyborg TGL SC
Thursday, January 14, 2021
Date:Date: Sheet
Sheet 79 of 105
5 4 3 2 1
5 4 3 2 1
Main Func = dGPU 1V_VGACORE1_S0
GPU1I 13 OF 14
13/14 GND
RF RESERVED GPU1C
11/14 VDD 1 of 2
11 OF 14
A2 K11
K10 AB17 GND_001 GND_057 K13
K12 VDD_001 AB20 GND_005 GND_058 K15
VDD_002 GND_006 GND_059
1
K14 AB24 K17
FC8001
FC8002
K16 VDD_003 AC2 GND_007 GND_060 L10
K18 VDD_004 AC22 GND_008 GND_061 L12
SCD1U16V2KX-L-GP
SCD1U16V2KX-L-GP
VDD_005 GND_009 GND_062
2
L13 AC26 L14
L15 VDD_007 AC5 GND_010 GND_063 L16
DY DY M10 VDD_008 AC8 GND_011 GND_064 L18
M12 VDD_010 AD12 GND_012 GND_065 L5
M16 VDD_011 AD13 GND_013 GND_069 M11
M18 VDD_013 A26 GND_014 GND_070 M13
N11 VDD_014 AD15 GND_002 GND_071 M15
N13 VDD_015 AD16 GND_015 GND_072 M17
22U 0603*10 X6S VDD_016 GND_016 GND_073
Place under GPU N15 AD18 N10
N17 VDD_017 AD19 GND_017 GND_074 N12
P14 VDD_018 AD21 GND_018 GND_075 N14
R11 VDD_021 AD22 GND_019 GND_076 N16
C8011 C8012 C8013 C8014 R13 VDD_024 AE11 GND_020 GND_077 N18
VDD_025 GND_021 GND_078
1
R15 AE14 P11
SC22U6D3V3MX-9-GP-U
SC22U6D3V3MX-9-GP-U
SC22U6D3V3MX-9-GP-U
SC22U6D3V3MX-9-GP-U
C8001 C8002 C8003 C8004 C8005 C8006 C8007 C8008 C8009 C8010
R17 VDD_026 AE17 GND_022 GND_079 P13
SC22U6D3V3MX-17-GP
SC22U6D3V3MX-17-GP
SC22U6D3V3MX-17-GP
SC22U6D3V3MX-17-GP
SC22U6D3V3MX-17-GP
SC22U6D3V3MX-17-GP
SC22U6D3V3MX-17-GP
SC22U6D3V3MX-17-GP
D T10 VDD_027 AE20 GND_023 GND_080 P15 D
OPS OPS OPS OPS OPS OPS OPS OPS OPS OPS VDD_028 GND_024 GND_081
2
DY DY DY DY T12 AB11 P17
T16 VDD_029 AF1 GND_003 GND_082 P23
T18 VDD_031 AF11 GND_025 GND_084 P26
U13 VDD_32 AF14 GND_026 GND_085 R10
U15 VDD_34 AF17 GND_027 GND_087 R12
V10 VDD_35 AF20 GND_028 GND_088 R14
V12 VDD_37 AF23 GND_029 GND_089 R16
V14 VDD_38 AF5 GND_030 GND_090 R18
V16 VDD_39 AF8 GND_031 GND_091 T11
V18 VDD_40 AG2 GND_032 GND_092 T13
VDD_41 AG26 GND_033 GND_093 T15
AB14 GND_034 GND_094 T17
B1 GND_004 GND_095 U10
10U 0603*14 X6S PWR_VGA_NVVDDS_VSEN1_P_R GND_035 GND_096
Place under GPU F2 B11 U12
VDD_SENSE F1 PWR_VGA_NVVDDS_VSEN1_N_R B14 GND_036 GND_097 U14
GND_SENSE B17 GND_037 GND_098 U16
B20 GND_038 GND_099 U18
C8048 C8049 C8050 C8051 C8052 C8053 C8054 C8055 C8015 C8016 C8017 C8018 C8019 C8020 B23 GND_039 GND_100 U23
GND_040 GND_102
1
B27 U26
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
SC10U6D3V2MX-2-GP
SC10U6D3V2MX-2-GP
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
SC10U6D3V2MX-2-GP
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
SC10U6D3V3MX-DL-GP
B5 GND_041 GND_103 V11
B8 GND_042 GND_105 V13
GND_043 GND_106
2
OPS OPS OPS OPS OPS OPS OPS OPS OPS OPS OPS E11 V15
[79] FP_FUSE
OPS OPS OPS N18S-G5-A1-GP E14 GND_044 GND_107 V17
E17 GND_045 GND_108 Y2
OPS E2 GND_046 GND_109 Y23
E20 GND_047 GND_110 Y26
[85] PWR_VGA_NVVDDS_VSEN1_P_R E22 GND_048 GND_111 Y5
E25 GND_049 GND_112 AA7
E5 GND_050 GND_F AB7
[85] PWR_VGA_NVVDDS_VSEN1_N_R E8 GND_051 GND_H
GND_052
GPU1G 7 OF 14
OPTIONAL GND:
1U 0201*5 X6S 7/14 VDD 2 of 2
Place under GPU
XVDD AREA
L11
L17 VDD_6 H2 P2
M14 VDD_9 H5 GND_053 GND_083 P5
C8040 C8041 C8042 P10 VDD_12 L2 GND_056 GND_086 U2
VDD_19 GND_066 GND_101
1
1
P12 U5
SC1U4V1MX-1-NF-GP
SC1U4V1MX-1-NF-GP
SC1U4V1MX-1-NF-GP
C8021 C8022 C8023 C8038 C8039
P16 VDD_20 GND_104
P18 VDD_22
OPS
OPS
OPS
OPS
OPS
SC1U10V1MX-1-GP
SC1U10V1MX-1-GP
SC1U10V1MX-1-GP
SC1U10V1MX-1-GP
SC1U10V1MX-1-GP
VDD_23 PCB ADR/CMD
2
2
DY DY DY T14
U11 VDD_30
U17 VDD_33 PWR REFERENCE
VDD_36 H23 L23
H25 GND_054 GND_067 L25
GND_055 GND_068
N18S-G5-A1-GP
OPS
C C
N18S-G5-A1-GP
OPS
3.3V +/- 5%
85mA
1D8V_VGA_S0
Under GPU Near GPU
1D8V_VGA_S0_R 2 1
R8001
0R3J-0-U-GP
C8034 C8029 C8028 C8024 C8025 OPS_N17
OPS_N17
OPS_N17
OPS_N17
SC1U10V2KX-1DLGP
SCD1U16V2KX-3DLGP
SC1U10V2KX-1DLGP
SC4D7U6D3V2MX-1-GP
OPS_N17
SC4D7U6D3V2MX-1-GP
(NEW ADDED) 1D8V_VGA_S0
1
1
1U 0201*2 X6S
DY Place under GPU
2
2
1D8V_AON_S0
GPU1F 14 OF 14 (NEW ADDED) (NEW ADDED)
1
14/14 VDD18 C8064 C8063
GP107S TU117S
G8
OPS
OPS
SC1U10V1MX-1-GP
SC1U10V1MX-1-GP
VDD18_1
2
VDD18
VDD18 G9 FP_FUSE_SRC
VDD18_2 G10
1V8_AON_1 G12
1V8_AON_2
GP107S TU117S
NC AB6 FP_FUSE_SRC
FP_FUSE_SRC
1
C8068
1
OPS
R8004
OPS_N18
2
2K21R2D-GP
OPS_N18
2
N18S-G5-A1-GP
1
C8065 C8066 C8067
OPS
OPS
OPS
SC1U10V1MX-1-GP
SC1U10V1MX-1-GP
SC1U10V1MX-1-GP
2
2
1D8V_AON_S0 FP_FUSE_SRC
B U8001 B
A1 B1
A2 VOUT GND B2 FP_FUSE
VIN EN
G5017B11U-GP
1
1
OPS_N18 C8069 C8070 C8071
SC4D7U6D3V1MX-1-GP
SC4D7U6D3V1MX-1-GP
SC4D7U6D3V1MX-1-GP
074.05017.009Z
2nd = 074.04622.009Z
2
2
OPS OPS OPS
Place near GPU

1U 0201*3 X6S
4.7U 0603*3 X6S
A A
<Core Design>
Wistron Corporation
TitleTitle
GPU(5/5)PWR/GND
SizeSize Document
Document Number
Number Rev Rev
A1 Cyborg TGL SC
Date:
Sheet 80 of 105
5 4 3 2 1
5 4 3 2 1
SSID = VRAM
Place close VDD ball Place close VDD ball

[78,81] FBA_CMD6 1D35V_VGA_S0 1D35V_VGA_S0
[78,81]
[78,81]
FBA_CMD11
FBA_CMD10 1D35V_VGA_S0 VRAM1A 1 OF 2 Frame Buffer Patition A-Lower Half
[78,81] FBA_CMD7
C5 B5
[78,81] FBA_CMD9
C10 VDD OPS VSS B10 1D35V_VGA_S0 C8104
VDD VSS
1
D11 D10 C8105 C8106 C8107 C8109 C8108 C8115
SC10U6D3V3MX-DL-GP
[78,81] FBA_CMD2 VDD VSS
[78,81] FBA_CMD4 G1 G5 OPS
G4 VDD VSS G10
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
[78,81] FBA_CMD3 VDD VSS OPS OPS OPS OPS OPS OPS
2
1
D [78,81] FBA_CMD1 G11 H1 D
G14 VDD VSS H14 R8106
L1 VDD VSS K1 549R2F-GP
L4 K14
[78,81]
[78,81]
FBA_CMD12
FBA_CMD0 L11 VDD VSS L5 OPS
VDD VSS
2
[78,81] FBA_CMD15 L14 L10 FBA_VREFC0
P11 VDD VSS P10
1
R5 T5
1K33R2F-GP
R8107
931R2F-1-GP
R8104
1D35V_VGA_S0 R10 VDD VSS T10
[78] FBA_CLK0P
[78] FBA_CLK0N
VDD VSS Place close VDD ball 1D35V_VGA_S0
B1 A1 1D35V_VGA_S0
[78,81] FBA_CMD14
B3 VDDQ VSSQ A3 OPS OPS Q8101
VDDQ VSSQ
2
B12 A12
B14 VDDQ VSSQ A14 1 6 FBA_VREF_FET_L
[82] FBA_VREFC0
Note:ZZ.27002.F7C01
D1 VDDQ VSSQ C1 C8102 C8127 C8130
VDDQ VSSQ OPS
1
D3 C3 FBA_VREF_FET_L GPIO10_FBVREF 2 5 SIO_SLP_S3#
SC4D7U6D3V2MX-1-GP
SC4D7U6D3V2MX-1-GP
SC4D7U6D3V2MX-1-GP
[79] GPIO10_FBVREF VDDQ VSSQ
1
D12 C4 C8120 C8121 C8122 C8123 C8124 C8125
D14 VDDQ VSSQ C11 1D8V_EN# 3 4
[78,81] FBA_CMD13 VDDQ VSSQ
2
E5 C12
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
VDDQ VSSQ OPS OPS OPS OPS OPS OPS DY DY DY
2
E10 C14 2N7002KDW-1-GP
F1 VDDQ VSSQ E1
F3 VDDQ VSSQ E3
F12 VDDQ VSSQ E12
75.27002.F7C
F14 VDDQ VSSQ E14
2nd = 075.27002.0E7C
FBA_D[0..31] [78,81]
G2 VDDQ VSSQ F5
3rd = 075.07002.0A7C
G13 VDDQ VSSQ F10 NEW ADDED
H3 VDDQ VSSQ H2
H12 VDDQ VSSQ H13
K3 VDDQ VSSQ K2 Place close VDDQ ball Place close VDDQ ball
K12 VDDQ VSSQ K13 1D35V_VGA_S0 1D35V_VGA_S0
L2 VDDQ VSSQ M5
L13 VDDQ VSSQ M10
M1 VDDQ VSSQ N1
M3 VDDQ VSSQ N3
M12 VDDQ VSSQ N12 C8113
VDDQ VSSQ FBVREF Termination
1
M14 N14 C8114 C8110 C8111 C8112 C8116 C8117 C8118 C8119
SC10U6D3V3MX-DL-GP
N5 VDDQ VSSQ R1
N10 VDDQ VSSQ R3
OPS
Type FBVREF% Voltage GPU_GPIO10
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
VDDQ VSSQ OPS OPS OPS OPS
2
P1 R4 OPS OPS OPS OPS
P3 VDDQ VSSQ R11
FBA_D[0..31] [78,81] VDDQ VSSQ
P12 R12 Un-termination 50% 0.749V High
P14 VDDQ VSSQ R14
C C
T1 VDDQ VSSQ U1
T3 VDDQ VSSQ U3
VDDQ VSSQ Termination 70% 1.0617V Low
T12 U12
T14 VDDQ VSSQ U14
VDDQ VSSQ
FBA_VREFC0 J14 A5
VREFC VPP/NC#A5 U5
A10 VPP/NC#U5
VREFD
1
C8126 U10
VREFD
2
H5GQ2H24AFR-T2C-GP
[78,81] FBA_CMD10 OPS 72.05224.A0U
[78,81] FBA_CMD7
[78,81] FBA_CMD6
[78,81] FBA_CMD11
[78,81] FBA_CMD9
[78,81] FBA_CMD3
[78,81] FBA_CMD1
[78,81] FBA_CMD2
[78,81] FBA_CMD4
[78,81] FBA_CMD8
[78,81] FBA_CMD15
[78,81] FBA_CMD5
[78,81] FBA_CMD12
[78,81] FBA_CMD0
FBA_D[0..31] [78,81]
Normal(MF=0)
VRAM1B 2 OF 2
FBA_CMD6 K4 A4 FBA_D0
FBA_CMD11 H5 A8/A7 OPS DQ0 A2 FBA_D1
FBA_CMD10 H4 A9/A1 DQ1 B4 FBA_D2
FBA_CMD7 K5 A10/A0 DQ2 B2 FBA_D3
B FBA_CMD9 J5 A11/A6
A12/RFU#J5/NC#J5
DQ3
DQ4
E4 FBA_D4 Byte 0 B
FBA_D5
FBA_CMD2 H11 DQ5
E2
F4 FBA_D6 0~7
FBA_CMD4 K10 BA0/A2 DQ6 F2 FBA_D7
FBA_CMD3 K11 BA1/A5 DQ7 A11 FBA_D8
FBA_CMD1 H10 BA2/A4 DQ8 A13 FBA_D9
BA3/A3 DQ9 B11 FBA_D10
FBA_D[0..31] [78,81] FBA_CMD8 DQ10 FBA_D11
J4 B13
FBA_CMD12 G3 ABI#
RAS#
DQ11
DQ12
E11 FBA_D12 Byte 1
FBA_CMD0 FBA_D13
FBA_CMD15
G12
L3 CS# DQ13
E13
F11 FBA_D14 8~15
FBA_CMD5 L12 CAS# DQ14 F13 FBA_D15
WE# DQ15 U11 FBA_D16
FBA_CLK0P J12 DQ16 U13 FBA_D17
FBA_CLK0N J11 CK DQ17 T11 FBA_D18
FBA_CMD14 J3 CK# DQ18 T13 FBA_D19
CKE# DQ19
DQ20
N11 FBA_D20 Byte 2
FBA_DQM0 FBA_D21
FBA_DQM1
D2
D13 DBI0# DQ21
N13
M11 FBA_D22 16~23
FBA_DQM2 P13 DBI1# DQ22 M13 FBA_D23
FBA_DQM3 P2 DBI2# DQ23 U4 FBA_D24
DBI3# DQ24 U2 FBA_D25
[78] FBA_DQM0 FBA_CMD13 DQ25 FBA_D26
[78] FBA_DQM1 J2 T4
RESET# DQ26 T2 FBA_D27
[78] FBA_DQM2
[78] FBA_DQM3
FBA_SEN0 J10
SEN
DQ27
DQ28
N4 FBA_D28 Byte 3
FBA_ZQ0 FBA_D29
[78] FBA_EDC0
FBA_MF1
J13
J1 ZQ DQ29
N2
M4 FBA_D30 24~31
MF DQ30 M2 FBA_D31
121R2F-GP
R8108
[78] FBA_EDC1 DQ31

2
FBA_WCK01 D4
1KR2J-1-GP
R8111
[78] FBA_EDC2 R8110 FBA_WCK01# D5 WCK01 C2 FBA_EDC0

[78] FBA_EDC3 0R0402-PAD-7-NP-GP WCK01# EDC0 C13 FBA_EDC1
BB
OPS OPS FBA_WCK23 P4 EDC1 R13 FBA_EDC2
FBA_WCK23# P5 WCK23 EDC2 R2 FBA_EDC3
WCK23# EDC3
1
[78] FBA_WCK23
[78] FBA_WCK23# H5GQ2H24AFR-T2C-GP
[78] FBA_WCK01
[78] FBA_WCK01#
[78,81] FBA_CMD14 FBA_CLK0P

FBA_CLK0N
A A
[78,81] FBA_CMD13
1
R8102 R8101
[17,27,40,55] SIO_SLP_S3# 40D2R2F-GP 40D2R2F-GP
OPS OPS
2
FBA_CLK0_MIDPT <Core Design>

[27] 1D8V_EN#
1
C8101
OPS SCD01U25V2KX-3DLGP Wistron Corporation
2
Title

GPU-VRAM1,2 (1/4) Rev
Custom
Cyborg TGL SC
5 4 3 2 1
5 4 3 2 1
SSID = VRAM
FBA_D[32..63] [78,82]
1D35V_VGA_S0
Place close VDD ball
1D35V_VGA_S0 VRAM2A
Frame Buffer Patition A-Upper Half
1 OF 2
C5 B5
OPS
C8207
VDD VSS
1
C10 B10 C8224 C8204 C8205 C8206
SC10U6D3V3MX-DL-GP
D11 VDD VSS D10
G1 VDD VSS G5
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
D FBA_D[32..63] [78,82] VDD VSS D
2
G4 G10 OPS OPS OPS OPS OPS
G11 VDD VSS H1
G14 VDD VSS H14
L1 VDD VSS K1
L4 VDD VSS K14
L11 VDD VSS L5
L14 VDD VSS L10
P11 VDD VSS P10
R5 VDD VSS T5
1D35V_VGA_S0 R10 VDD VSS T10 1D35V_VGA_S0
VDD VSS Place close VDD ball
[78,82] FBA_CMD22 B1 A1
B3 VDDQ VSSQ A3
[78,82] FBA_CMD26 B12 A12
VDDQ VSSQ
1
[78,82] FBA_CMD23 B14 A14 C8211 C8212 C8213 C8214 C8220 C8226
D1 VDDQ VSSQ C1
D3 C3
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
VDDQ VSSQ
2
[78,82] FBA_CMD18 D12 C4 OPS OPS OPS OPS OPS OPS
D14 VDDQ VSSQ C11
[78,82] FBA_CMD19 E5 C12
E10 VDDQ VSSQ C14
F1 E1
F3 VDDQ VSSQ E3
[78,82] FBA_CMD28 F12 E12
F14 VDDQ VSSQ E14
[78,82] FBA_CMD31 G2 F5
G13 VDDQ VSSQ F10 1D35V_VGA_S0
[78,82] FBA_CMD21
H3 VDDQ VSSQ H2 Place close VDDQ ball
H12 VDDQ VSSQ H13
[78] FBA_CLK1P VDDQ VSSQ
[78] FBA_CLK1N K3 K2
K12 VDDQ VSSQ K13
C8218
1
L2 M5 C8219 C8215 C8216 C8217
SC10U6D3V3MX-DL-GP
L13 VDDQ VSSQ M10
M1 VDDQ VSSQ N1
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
[81] FBA_VREFC0 VDDQ VSSQ
2
M3 N3 OPS OPS OPS OPS OPS
M12 VDDQ VSSQ N12
FBVREF Termination VDDQ VSSQ
M14 N14
N5 VDDQ VSSQ R1
Type FBVREF% Voltage GPU_GPIO10 N10 R3
P1 VDDQ VSSQ R4
P3 VDDQ VSSQ R11
C C
FBA_D[32..63] [78,82] VDDQ VSSQ
Un-termination 50% 0.749V High P12 R12
P14 VDDQ VSSQ R14
T1 VDDQ VSSQ U1 Place close VDD ball Place close VDDQ ball
T3 VDDQ VSSQ U3 1D35V_VGA_S0 1D35V_VGA_S0
Termination 70% 1.0617V Low VDDQ VSSQ
T12 U12
T14 VDDQ VSSQ U14
VDDQ VSSQ
FBA_VREFC0 J14 A5
VREFC VPP/NC#A5 U5
VPP/NC#U5
1
A10 C8210 C8209 C8221 C8222 C8223 C8225
VREFD
1
C8202 U10
VREFD
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
SC1U10V2KX-1DLGP
2
OPS OPS OPS OPS OPS OPS
2
H5GQ2H24AFR-T2C-GP
OPS 72.05224.A0U
FBA_D[32..63] [78,82]
1D35V_VGA_S0
C8208 C8227 C8228
1
SC4D7U6D3V2MX-1-GP
SC4D7U6D3V2MX-1-GP
SC4D7U6D3V2MX-1-GP
[78,82] FBA_CMD26
[78,82] FBA_CMD23
[78,82] FBA_CMD22
2
[78,82] FBA_CMD27
[78,82] FBA_CMD25 DY DY DY
[78,82] FBA_CMD19
[78,82] FBA_CMD17
[78,82] FBA_CMD18 Mirrored(MF=1)
VRAM2B 2 OF 2
[78,82] FBA_CMD20
NEW ADDED
[78,82] FBA_CMD24 FBA_CMD26 K4 A4 FBA_D56
FBA_CMD23 H5 A8/A7 DQ0 A2 FBA_D57
B
[78,82]
[78,82]
FBA_CMD31
FBA_CMD21 FBA_CMD22 H4 A9/A1 OPS DQ1 B4 FBA_D58 B
FBA_CMD27 K5 A10/A0 DQ2 B2 FBA_D59
[78,82]
[78,82]
FBA_CMD28
FBA_CMD16 FBA_CMD25 J5 A11/A6
A12/RFU#J5/NC#J5
DQ3
DQ4
E4 FBA_D60 Byte 7
FBA_D61
FBA_CMD19 H11 DQ5
E2
F4 FBA_D62 56~63
FBA_CMD17 K10 BA0/A2 DQ6 F2 FBA_D63
FBA_CMD18 K11 BA1/A5 DQ7 A11 FBA_D54
[78,82] FBA_CMD30 BA2/A4 DQ8
FBA_CMD20 H10 A13 FBA_D55
BA3/A3 DQ9 B11 FBA_D52
[78,82] FBA_CMD29 DQ10
FBA_CMD24 J4 B13 FBA_D50
[78] FBA_WCK67 FBA_CMD31 G3 ABI#
RAS#
DQ11
DQ12
E11 FBA_D48 Byte 6
FBA_CMD21 FBA_D49
[78] FBA_WCK67#
[78] FBA_WCK45 FBA_CMD28
G12
L3 CS# DQ13
E13
F11 FBA_D51 48~55
FBA_CMD16 L12 CAS# DQ14 F13 FBA_D53
[78] FBA_WCK45# WE# DQ15 U11 FBA_D40
FBA_CLK1P J12 DQ16 U13 FBA_D41
FBA_CLK1N J11 CK DQ17 T11 FBA_D42
[78] FBA_DQM4 FBA_CMD30 CK# DQ18 FBA_D43
J3 T13
[78] FBA_DQM5 CKE# DQ19 Byte 5
1
N11 FBA_D44
[78] FBA_DQM6 FBA_DQM7 DQ20 FBA_D45
[78] FBA_DQM7 R8206
40D2R2F-GP
R8208
40D2R2F-GP FBA_DQM6
D2
D13 DBI0# DQ21
N13
M11 FBA_D46 40~47
FBA_DQM5 P13 DBI1# DQ22 M13 FBA_D47
[78] FBA_EDC4 OPS OPS FBA_DQM4 P2 DBI2# DQ23 U4 FBA_D35
[78] FBA_EDC5 DBI3# DQ24
2
FBA_CLK1_MIDPT U2 FBA_D33
[78] FBA_EDC6 FBA_CMD29 J2 DQ25 T4 FBA_D34
[78] FBA_EDC7 RESET# DQ26 Byte 4
1
C8201 T2 FBA_D32
OPS FBA_SEN2 DQ27 FBA_D36
SCD01U25V2KX-3DLGP
FBA_ZQ3
J10
J13 SEN DQ28
N4
N2 FBA_D37 32~39
ZQ DQ29
2
2 1 FBA_MF4 J1 M4 FBA_D38
1D35V_VGA_S0 OPS
R8210 1KR2J-1-GP MF DQ30 M2 FBA_D39
DQ31
1
FBA_WCK67 D4
121R2F-GP
R8213
R8209 FBA_WCK67# D5 WCK01 C2 FBA_EDC7
0R0402-PAD-7-NP-GP WCK01# EDC0 C13 FBA_EDC6
OPS
OPS FBA_WCK45 P4 EDC1 R13 FBA_EDC5
FBA_WCK45# P5 WCK23 EDC2 R2 FBA_EDC4
WCK23# EDC3
2
H5GQ2H24AFR-T2C-GP
A A
<Core Design>
Wistron Corporation
Title

GPU-VRAM3,4 (2/4) Rev
Custom
Cyborg TGL SC
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A <Core Design> A
Wistron Corporation
Title
GPU-VRAM5,6 (3/4)
A3
Cyborg TGL SC
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
<Core Design>
Wistron Corporation
Title
GPU-VRAM7,8 (4/4)
A4
Cyborg TGL SC
5 4 3 2 1
5 4 3 2 1
[79] VGA_CORE_PSI
PH on EE side
2 R8544 1 PWR_VGA_NVVDDS_PSI
0R0402-PAD-7-NP-GP
OPS
PWR_VGA_NVVDDS_VID VGA : N17S-G3/G5

RT8816B For NVVDDS
2 R8545 1
EDP-Peak : 69.9A
[79] VGA_CORE_VID
0R0402-PAD-7-NP-GP
OPS
1. Check EE side
2. Modify DAT
R8542
2 1 PWR_VGA_NVVDDS_VSEN1_P
[80] PWR_VGA_NVVDDS_VSEN1_P_R OPS
20200221(DVT1)
0R2J-2-GP 3D3V_S0
changes to 3D3V_S0
D R8543 D
2 1 PWR_VGA_NVVDDS_VSEN1_N
[80] PWR_VGA_NVVDDS_VSEN1_N_R OPS
1
0R2J-2-GP
PR8557 1D8V_AON_S0
OPS 100KR2J-1-GP
PH on EE side
2
PWR_VGA_NVVDDS_PG
1
[85,86] PWR_VGA_NVVDDS_PG PWR_VGA_NVVDDS_PG PR8559
PWR_VGA_NVVDDS_PG [85,86]
OPS 6K04R2F-GP
2
PWR_VGA_NVVDDS_PSI
K
1
PD8501
1
PC8557 PR8563 AZ4024-01L-R7G-GP
EE need check SCD01U25V2KX-3DLGP DY OPS 12K1R2F-L1-GP PC8552 PC8553 OPS
1
SC10U25V5KX-DL-GP
SC10U25V5KX-DL-GP
TC8501 083.04024.0AA1
A
ST22U25VBM-GP
5V_S0 DY OPS OPS 2nd = 83.PJSD2.0AF
2
1
PR8556
2 PU8552 PU8554
VGA : N17S-G5/N18S-G5
OPS 2D2R3-1-U-GP PU8552
3 For G5: 075.07362.0073
1 4
EDP:32.6A
2
10
PC8554 PWR_VGA_NVVDDS_PVCC 9
SCD1U25V2KX-1-DL-GP 7
EDP-Peak : 78A
1 2 PWR_VGA_NVVDDS_TON_1 8 6
Rdson: 8.5~11.1m/2~2.6m (Q1/Q2)
1
PC8555 5
93.6A<OCP<109.2A
OPS
SC1U10V2KX-1DLGP
2
19V_DCBATOUT PR8561
PR8562
499KR2F-1-GP
OPS FDMS3600-02-RJK0215-COLAY-GP
2D2R3-1-U-GP 1st = 075.07362.0073
1 2 1 2 Cyntec 6.8mmx7.6mmx3.0mm
2nd = 075.36302.M002
OPS OPS DCR: 0.9m ohm +/-7%
1V_VGACORE1_S0
PR8551 PC8556 OPS_4ZA_GPU CORE
PU8551 2D2R3-1-U-GP SCD1U25V2KX-1-DL-GP Idc : 37A , Isat : 41A
18 1 PWR_VGA_NVVDDS_BOOT1 1 2 PWR_VGA_NVVDDS_BOOT1_A 1 2
PVCC BOOT1
OPS OPS PL8552
2 PWR_VGA_NVVDDS_HG1 1 2
PWR_VGA_NVVDDS_TON 9 UGATE1 OPS
3D3V_S0 TON 20 PWR_VGA_NVVDDS_PHASE1 IND-D15UH-96-GP
OPS PHASE1
1
0R0402-PAD-7-NP-GP
1 R8531 2 DGPU_PWROK_L 1
U8502
19 PWR_VGA_NVVDDS_LGATE1 068.R1510.2421 PC8558 PC8559
[86] 1V_VGA_S0_PG 5 PWR_VGA_NVVDDS_PG 13 LGATE1 2nd = 068.R1510.1511 DY DY
PGOOD
2
1 R8530 1D35V_PGOOD_L 2
2 12 PWR_VGA_NVVDDS_OCSET 1V_VGACORE1_S0
[86] 1D35V_PGOOD 4 PWR_VGA_NVVDDS_PSI 4 OCSET/SS
0R0402-PAD-7-NP-GP OPS DGPU_PWROK [19,24] PC8560
PSI
1
C 3 C
OPS SC1KP50V2KX-1DLGP
PWR_VGA_NVVDDS_VID
1
1 2 5 OPS PR8564 PC8561 SC22U6D3V3MX-1-DL-GP
TC7SZ08FU-LJ-CT-GP VID 127KR2F-GP SC22U6D3V3MX-1-DL-GP
SC33P50V2JN-3DLGP
PWR_VGA_NVVDDS_EN_R 3 15 PWR_VGA_NVVDDS_BOOT2
073.7SZ08.000G PC8562 DY EN BOOT2 OPS
2
2nd = 73.7SZ08.DAH SCD1U25V2KX-1-DL-GP DY
2
PWR_VGA_NVVDDS_VREF PWR_VGA_NVVDDS_HG2
1
1 2 8 14
VREF UGATE2 PT8551 PT8553 PT8554
PWR_VGA_NVVDDS_PHASE2
1
16
ST330U2D5VBM-1-GP
80.3371V.A2L
2nd = 77.23371.34L
ST330U2D5VBM-1-GP
80.3371V.A2L
2nd = 77.23371.34L
ST330U2D5VBM-1-GP
80.3371V.A2L
2nd = 77.23371.34L
OPS PHASE2
2
PR8566
17 PWR_VGA_NVVDDS_LGATE2
OPS 20K5R2F-GP PWR_VGA_NVVDDS_REFADJ 6 LGATE2 OPS OPS OPS
teknisi indonesia
PR8567 REFADJ
2
6K19R2F-GP 10 PWR_VGA_NVVDDS_VSEN1_N
PWR_VGA_NVVDDS_REFADJ_R 1 2 RGND
GND
PWR_VGA_NVVDDS_REFIN 7 11 PWR_VGA_NVVDDS_VSEN1_P
For VGA_CORE sequence OPS REFIN VSNS
2
PR8569
EE need check PR8568 RT8816BGQW-GP 100R2F-L1-GP-U
21
OPS 4K32R2F-GP 074.08816.0A73 1 2
3D3V_S0
OPS Place Near GPU (NVVDDS)
1
PC8564
1X330uF (Poscap) - PT8511 (Page85)
1
PWR_VGA_NVVDDS_REFIN
1
PC8563 SC33P50V2JN-3DLGP
1
SC33P50V2JN-3DLGP DY
2
R8541 DY
2
2
OPS 10KR2J-3-GP
PR8570
PR8577
100R2F-L1-GP-U
Q8509 OPS 16K5R2F-2-GP 1 2
2
PWR_VGA_NVVDD_OR# 6 1
OPS
D1 S1 OPS 19V_DCBATOUT
1
PC8566
1
5 G2 G1 2 PC8565 SC33P50V2JN-3DLGP 1V_VGACORE1_S0
[79,86] GPIO5_GC6_PWR_EN PWR_VGA_NVVDDS_REFIN_R
1
1V_VGA_EN_R [86]
OPS D2 PC8567
SC4700P50V2KX-1DLGP DY
2
4 S2 3 PWR_VGA_NVVDD_OR#
PWR_VGA_NVVDD_OR# [86] SC4700P50V2KX-1DLGP
2
19V_DCBATOUT
OPS
2
2
PJT138KA-GP PC8568 PC8551
1
SC10U25V5KX-DL-GP
SC10U25V5KX-DL-GP
075.00138.0A7C PR8572
K
2nd = 075.00139.007C OPS 309R2F-GP OPS OPS
3rd = 075.00138.0F7C PD8502
2
AZ4024-01L-R7G-GP
1
1D8V_VGA_S0
DY
A
PWR_VGA_NVVDDS_VSEN1_N
PU8554 2 PU8552 PU8554

3
For G5: 075.07362.0073
2
1 4
R8529 10
OPS10KR2J-3-GP 9
Q8504 7
8 6
2N7002K-2-GP-U Rdson: 8.5~11.1m/2~2.6m (Q1/Q2)
1
PWR_VGA_NVVDD_OR# G 5
R8501
D PWR_VGA_NVVDDS_EN 2 470R2F-GP1 PWR_VGA_NVVDDS_EN_R
OPS
S OPS FDMS3600-02-RJK0215-COLAY-GP
1st = 075.07362.0073
84.2N702.J31 2nd = 075.36302.M002

1
B
2ND = 084.27002.0N31 C8501
B
3rd = 084.27002.0L31 SCD1U16V2KX-3DLGP PR8573 PC8569 OPS_4ZA_GPU CORE Cyntec 6.8mmx7.6mmx3.0mm
4th = 084.07002.0C31 OPS 2D2R3-1-U-GP SCD1U25V2KX-1-DL-GP
DCR: 0.9m ohm +/-7%
1V_VGACORE1_S0
2
PWR_VGA_NVVDDS_BOOT2 1 2 PWR_VGA_NVVDDS_BOOT2_A 1 2
OPS OPS Idc : 37A , Isat : 41A
PWR_VGA_NVVDDS_HG2 PL8551
PWR_VGA_NVVDDS_PHASE2 1 2
OPS
PWR_VGA_NVVDDS_LGATE2 IND-D15UH-96-GP
1
068.R1510.2421 PC8570 PC8571
2nd = 068.R1510.1511 DY DY
2
A A
<Core Design>
Wistron Corporation
TitleTitle
GPU (RT8816A_VGA)
SizeSize Document
Document Number
Number Rev Rev
A1
Cyborg TGL SC
Date:
Sheet 85 of 105
5 4 3 2 1
5 4 3 2 1
Main Func = dGPU
Main Func = dGPU dGPU Power Discharge Circuit

3D3V_AUX_S5
[DG-07158-001 Rev03]Power up sequence: OPS
3.3V ==> NVVDD (VGA_CORE) ==> PEX_VDD (1.05V) ==> FBVDD/Q (1.35V) 1 2 PWR_VGA_NVVDD_PG#
1V_VGA_S0
1V_VGA_S0
R8612 D G S
100KR2J-1-GP
3D3V_S0 to 3V3_AON_S0 and 3D3V_VGA_S0
4 S2
D1
G2
D Q8615 D
3D3V_1D8V_S0
3D3V_VGA_S0: 3A @ 3.3V
1 2 PJT138KA-GP
U8601
1
1D8V_S5
R8602 C8611S 075.00138.0A7C OPS R8618
2nd = 075.00139.007C 10R2J-2-GP-U
1
0R0603-PAD-7-NP-GP 4 12 1D8V_VGA_CT_1 1
C8610 OPS 22 SC470P50V2KX-3DLGP
OPS

Cyborg - TGL REVA00

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5 4 3 2 1

Cyborg-N/V/L 14/15_TGL-U &

Watchmen 14N TGL-U Schematic

DY : None Installed <Core Design>

OPS: Optimal Playable Settings Title

Cyborg N/V/L & Watchmen 14 TGL Block Diagram

Universal Jack 10 USB2.0/1.1 Lanes

KBC NGFF WWAN For CBG-NV: 32M SOIC 8/ NON RPMC

I2C Touch PAD

Batt Conn KBC

R311 1 2 100R2J-2-GP XDP_TDO_CPU

R308 1 2 51R2J-2-GP XDP_PREQ#

R304 1 2 1KR2F-3-GP THERMTRIP#_CPU

R307 1 2 1KR2F-3-GP CPU_CATERR

XDP_TCLK R310 1 2 51R2J-2-GP

[24,65] TOUCHPAD_INTR# CPU1U 21 OF 21

R419 1 2 10KR2J-3-GP KB_DET#

2 5 75.27002.F7C 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Channel A DDR4 ball type: Non-Interleaved Type

M_B_DQS_DP4 M_B_DQ40 [13] Q501 0R0402-PAD-7-NP-GP

[13] M_B_BG1 Wistron Corporation

T15 A51 TP_RSVD_A51 1 TP607

20191112 modify TGL-U-1-GP-U2

R618 1 2 1KR2J-1-GP CFG11

R619 1 2 1KR2J-1-GP CFG10

R620 1 2 1KR2J-1-GP CFG9

R621 1 2 1KR2J-1-GP CFG7

R627 1 2 1KR2J-1-GP CFG1

CFG14 R606 1 DY 2 1KR2J-1-GP

CFG4 R607 1 2 1KR2J-1-GP

CFG7 R608 1 DY 2 1KR2J-1-GP

[46] VSSCORE_SENSE CPU1M 13 OF 21

Main Func = CPU

Main Func = CPU

1V_CPU_CORE 22uF *13pcs 1V_CPU_CORE

PC1016 PC1017 PC1018 PC1024

PC1019 PC1020 PC1021 PC1025

Main Func = CPU

C1111 C1112 C1113

11/5 Tery Don

Main Func = MEMORY DM1A 1 OF 4

M_A_DQ25 [5] 1D2V_S3

M_A_DQ56 [5] 3D3V_S0

M_A_CS#0 [5] RN1201 R1206

M_A_ODT0 [5] SRN1KJ-7-GP 2R2F-GP

M_A_ODT1 [5] C1222

CPU_SMB_SDA_DDR [13,18] V_SM_VREF_PATH1

M_B_A0 144 8 M_B_DQ42 1D2V_S3

M_B_DQ45 [5] C1323

ESPI Disable Disable Enable 19.2MHZ CLOCK FROM DIVIDER

Enable =default= 38.4MHZ CLOCK FROM DIRECT SECURITY MEASURES

3.3V 3.3V Disable DFXTESTMODE DISABLED

Low 1.8V 1.8V 1.8V 1.8V Enable DFXTESTMODE ENABLED

TBT LSX #1 TBT LSX #2 TBT LSX #3 A0 GPP_E10 GPP_E11

[76] GFX_PCIE_TX_N2 HDD1 (for CBG 14/15 L)

[63] SSD_PCIE_RX_N2 LAN_PCIE_TX_P CBG_L_HDD

WLAN GFX_PCIE_TX_P3 C1605 1 2 SCD22U10V1KX-1-GP

3V_5V_POK# 5 2 3V_5V_POK_C D1705 A K RB520S30-GP 3V_5V_PWRGD