LT1016

UltraFast Precision
10ns Comparator

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FEATURES DESCRIPTIO
■ UltraFastTM (10ns typ) The LT®1016 is an UltraFast 10ns comparator that inter-
■ Operates Off Single 5V Supply or ±5V faces directly to TTL/CMOS logic while operating off either
■ Complementary Output to TTL ±5V or single 5V supplies. Tight offset voltage specifica-
■ Low Offset Voltage tions and high gain allow the LT1016 to be used in
■ No Minimum Input Slew Rate Requirement precision applications. Matched complementary outputs
■ No Power Supply Current Spiking further extend the versatility of this comparator.
■ Output Latch Capability A unique output stage provides active drive in both direc-
tions for maximum speed into TTL/CMOS logic or passive
U loads, yet does not exhibit the large current spikes found
APPLICATIO S in conventional output stages. This allows the LT1016 to
■ High Speed A/D Converters remain stable with the outputs in the active region which,
■ High Speed Sampling Circuits greatly reduces the problem of output “glitching” when the
■ Line Receivers input signal is slow moving or is␣ low level.
■ Extended Range V-to-F Converters The LT1016 has a LATCH pin which will retain input data
■ Fast Pulse Height/Width Discriminators at the outputs, when held high. Quiescent negative power
■ Zero-Crossing Detectors supply current is only 3mA. This allows the negative
■ Current Sense for Switching Regulators supply pin to be driven from virtually any supply voltage
■ High Speed Triggers with a simple resistive␣ divider. Device performance is not
■ Crystal Oscillators affected by variations in negative supply voltage.
Linear Technology offers a wide range of comparators in
addition to the LT1016 that address different applications.
See the Related Parts section on the back page of the data
, LTC and LT are registered trademarks of Linear Technology Corporation.
UltraFast is a trademark of Linear Technology Corporation. sheet.

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TYPICAL APPLICATION Response Time
10MHz to 25MHz Crystal Oscillator
5V
VIN THRESHOLD
10MHz TO 25MHz 100mV STEP
2k (AT CUT)
22Ω 5mV OVERDRIVE THRESHOLD

5V
820pF V+
+ Q
LT1016
2k OUTPUT VOUT
– Q 1V/DIV
GND
LATCH
V–

2k 0 20 0 20
200pF
TIME (ns)
1016 TA1a 1016 TA2b

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LT1016
W W W U
ABSOLUTE AXI U RATI GS (Note 1)

Positive Supply Voltage (Note 5) ............................... 7V Operating Temperature Range

Negative Supply Voltage ............................................ 7V LT1016I ...............................................–40°C to 85°C
Differential Input Voltage (Note 7) ........................... ±5V LT1016C .................................................. 0°C to 70°C
+IN, –IN and LATCH ENABLE Current (Note 7) .. ±10mA Storage Temperature Range ................. – 65°C to 150°C
Output Current (Continuous) (Note 7) ................ ±20mA Lead Temperature (Soldering, 10 sec).................. 300°C

U W U
PACKAGE/ORDER I FOR ATIO
ORDER PART ORDER PART
TOP VIEW NUMBER TOP VIEW NUMBER
V+ 1 8 Q OUT V+ 1
LT1016CN8 8 Q OUT
LT1016CS8
+IN 2 + 7 Q OUT +
LT1016IN8 +IN 2 7 Q OUT
LT1016IS8
–IN 3 – 6 GND – IN 3 – 6 GND
V– 4 5 LATCH V– 4 5 LATCH
ENABLE ENABLE S8 PART
N8 PACKAGE S8 PACKAGE
8-LEAD PDIP 8-LEAD PLASTIC SO
MARKING
TJMAX = 100°C, θJA = 130°C/W (N8) TJMAX = 110°C, θJA = 120°C/W
1016
1016I

Consult LTC marketing for parts specified with wider operating temperature ranges.

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 LT1016
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+ = 5V, V– = 5V, VOUT (Q) = 1.4V, VLATCH = 0V, unless otherwise noted.
LT1016C/I
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOS Input Offset Voltage RS ≤ 100Ω (Note 2) 1.0 ±3 mV
● 3.5 mV
∆VOS Input Offset Voltage Drift ● 4 µV/°C
∆T
IOS Input Offset Current (Note 2) 0.3 1.0 µA
● 0.3 1.3 µA
IB Input Bias Current (Note 3) 5 10 µA
● 13 µA
Input Voltage Range (Note 6) ● –3.75 3.5 V
Single 5V Supply ● 1.25 3.5 V
CMRR Common Mode Rejection –3.75V ≤ VCM ≤ 3.5V ● 80 96 dB
PSRR Supply Voltage Rejection Positive Supply 4.6V ≤ V + ≤ 5.4V ● 60 75 dB
LT1016C
Positive Supply 4.6V ≤ V + ≤ 5.4V ● 54 75 dB
LT1016I
Negative Supply 2V ≤ V – ≤ 7V ● 80 100 dB
AV Small-Signal Voltage Gain 1V ≤ VOUT ≤ 2V 1400 3000 V/V
VOH Output High Voltage V+ ≥ 4.6V IOUT =1mA ● 2.7 3.4 V
IOUT = 10mA ● 2.4 3.0 V
VOL Output Low Voltage ISINK = 4mA ● 0.3 0.5 V
ISINK = 10mA 0.4 V
I+ Positive Supply Current ● 25 35 mA
I– Negative Supply Current ● 3 5 mA
VIH LATCH Pin Hi Input Voltage ● 2.0 V
VIL LATCH Pin Lo Input Voltage ● 0.8 V
IIL LATCH Pin Current VLATCH = 0V ● 500 µA
tPD Propagation Delay (Note 4) ∆VIN = 100mV, OD = 5mV 10 14 ns
● 16 ns
∆VIN = 100mV, OD = 20mV 9 12 ns
● 15 ns
∆tPD Differential Propagation (Note 4) ∆VIN = 100mV, 3 ns
Delay OD = 5mV
Latch Setup Time 2 ns

Note 1: Absolute Maximum Ratings are those values beyond which the life ∆tPD limits shown can be guaranteed with this test if additional DC tests
of a device may be impaired. are performed to guarantee that all internal bias conditions are correct. For
Note 2: Input offset voltage is defined as the average of the two voltages low overdrive conditions VOS is added to overdrive. Differential
measured by forcing first one output, then the other to 1.4V. Input offset propogation delay is defined as: ∆tPD = tPDLH – tPDHL
current is defined in the same way. Note 5: Electrical specifications apply only up to 5.4V.
Note 3: Input bias current (IB) is defined as the average of the two input Note 6: Input voltage range is guaranteed in part by CMRR testing and in
currents. part by design and characterization. See text for discussion of input
Note 4: tPD and ∆tPD cannot be measured in automatic handling voltage range for supplies other than ±5V or 5V.
equipment with low values of overdrive. The LT1016 is sample tested with Note 7: This parameter is guaranteed to meet specified performance
a 1V step and 500mV overdrive. Correlation tests have shown that tPD and through design and characterization. It has not been tested.

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LT1016
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TYPICAL PERFOR A CE CHARACTERISTICS
Propagation Delay vs Input Propagation Delay vs Load
Gain Characteristics Overdrive Capacitance
5.0 25 25
VS = ± 5V VS = ±5V VS = ± 5V
4.5 IOUT = 0 TJ = 25°C TJ = 25°C
TJ = 125°C VSTEP = 100mV I =0
4.0 20 CLOAD = 10pF 20 VOUT = 100mV
STEP
OUTPUT VOLTAGE (V)

3.5 OVERDRIVE = 5mV

3.0 15 15

TIME (ns)

TIME (ns)
TJ = 25°C
2.5 tPDHL

2.0 10 10 tPDLH
1.5
1.0 TJ = – 55°C 5 5
0.5
0 0 0
– 2.5 –1.5 – 0.5 0.5 1.5 2.5 0 10 20 30 40 50 0 10 20 30 40 50
DIFFERENTIAL INPUT VOLTAGE (mV) OVERDRIVE (mV) OUTPUT LOAD CAPACITANCE (pF)
1016 G01 1016 G02 1016 G03

Propagation Delay vs Source Propagation Delay vs Supply Propagation Delay vs

Resistance Voltage Temperature
80 25 30
VS = ± 5V V – = – 5V VS = ± 5V
T = 25°C TJ = 25°C
70 J OVERDRIVE = 5mV
OVERDRIVE = 20mV VSTEP = 100mV 25 STEP SIZE = 100mV
EQUIVALENT INPUT 20 OVERDRIVE = 5mV
60 CLOAD = 10pF
CAPACITANCE IS ≈ 3.5pF CLOAD = 10pF
CLOAD = 10pF 20
50 15 TIME (ns)
TIME (ns)
TIME (ns)

STEP SIZE = 800mV

40 400mV 15
200mV FALLING EDGE tPDHL
100mV 10 FALLING OUTPUT tPDHL
30 RISING EDGE tPDLH 10
20 RISING OUTPUT tPDLH
5
5
10

0 0 0
0 500 1k 1.5k 2k 2.5k 3k 4.4 4.6 4.8 5.0 5.2 5.4 5.6 –50 –25 0 25 50 75 100 125
SOURCE RESISTANCE (Ω) POSITIVE SUPPLY VOLTAGE (V) JUNCTION TEMPERATURE (°C)
1016 G04 1016 G05 1016 G06

Latch Set-Up Time vs Output Low Voltage (VOL) vs Output High Voltage (VOH) vs
Temperature Output Sink Current Output Source Current
6 0.8 5.0
VS = ± 5V VS = ± 5V VS = ± 5V
IOUT = 0V 0.7 VIN = 30mV 4.5 VIN = – 30mV
4
0.6 4.0
OUTPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

TJ = 125°C
2 TJ = – 55°C
0.5 3.5
TIME (ns)

TJ = 25°C
0 0.4 TJ = 25°C 3.0
TJ = – 55°C
0.3 2.5
–2
0.2 TJ = 125°C 2.0
–4
0.1 1.5

–6 0 1.0
–50 –25 0 25 50 75 100 125 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20
JUNCTION TEMPERATURE (°C) OUTPUT SINK CURRENT (mA) OUTPUT SOURCE CURRENT (mA)
1016 G07 1016 G08 1016 G09

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 LT1016
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TYPICAL PERFOR A CE CHARACTERISTICS
Negative Supply Current vs Positive Supply Current vs Positive Supply Current vs
Temperature Positive Supply Voltage Switching Frequency
6 50 40
VS = ± 5V V – = 0V TJ = 125°C
IOUT = 0 45 VIN = 60mV 35 TJ = 25°C
5 IOUT = 0 TJ = – 55°C
40
30
35
4

CURRENT (mA)
CURRENT (mA)

CURRENT (mA)
30 25

3 25 20
20 15
2 15 TJ = 25°C
TJ = 125°C 10
10 VS = ± 5V
1
5 5 VIN = ± 50mV
TJ = – 55°C
IOUT = 0
0 0 0
–50 –25 0 25 50 75 100 125 0 1 2 3 4 5 6 7 8 1 10 100
JUNCTION TEMPERATURE (°C) SUPPLY VOLTAGE (V) SWITCHING FREQUENCY (MHz)
1016 G12
1016 G10 1016 G11

Common Mode Rejection vs Positive Common Mode Limit vs Negative Common Mode Limit vs
Frequency Temperature Temperature
120 6 2
VS = ± 5V VS = ± 5V*
110 VIN = 2VP-P VS = SINGLE 5V SUPPLY
TJ = 25°C 5 1
100
REJECTION RATIO (dB)

INPUT VOLTAGE (V)

INPUT VOLTAGE (V)

4 0
90
*SEE APPLICATION INFORMATION
80 3 –1 FOR COMMON MODE LIMIT WITH
VARYING SUPPLY VOLTAGE.
70
2 –2
60
1 *SEE APPLICATION INFORMATION
–3
50 FOR COMMON MODE LIMIT WITH
VARYING SUPPLY VOLTAGE. VS = ± 5V*
40 0 –4
10k 100k 1M 10M –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
FREQUENCY (Hz) JUNCTION TEMPERATURE (°C) JUNCTION TEMPERATURE (°C)
1016 G13 1016 G14 1016 G15

LATCH Pin Threshold vs LATCH Pin Current* vs

Temperature Temperature
2.6 300
VS = ± 5V VS = ± 5V
VLATCH = 0V
2.2 250

1.8 200
CURRENT (µA)
VOLTAGE (V)

OUTPUT LATCHED
1.4 150
OUTPUT UNAFFECTED
1.0 100

0.6 50
*CURRENT COMES OUT OF
LATCH PIN BELOW THRESHOLD
0.2 0
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
JUNCTION TEMPERATURE (°C) JUNCTION TEMPERATURE (°C)
1016 G16 1016 G17

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LT1016
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APPLICATIO S I FOR ATIO
Common Mode Considerations Input capacitance is typically 3.5pF. This is measured by
inserting a 1k resistor in series with the input and measur-
The LT1016 is specified for a common mode range of
ing the resultant change in propagation delay.
–3.75V to 3.5V with supply voltages of ±5V. A more
general consideration is that the common mode range is LATCH Pin Dynamics
1.25V above the negative supply and 1.5V below the
positive supply, independent of the actual supply voltage. The LATCH pin is intended to retain input data (output
The criteria for common mode limit is that the output still latched) when the LATCH pin goes high. This pin will float
responds correctly to a small differential input signal. to a high state when disconnected, so a flowthrough
Either input may be outside the common mode limit (up to condition requires that the LATCH pin be grounded. To
the supply voltage) as long as the remaining input is within guarantee data retention, the input signal must be valid at
the specified limit, and the output will still respond cor- least 5ns before the latch goes high (setup time) and must
rectly. There is one consideration, however, for inputs that remain valid at least 3ns after the latch goes high (hold
exceed the positive common mode limit. Propagation time). When the latch goes low, new data will appear at the
delay will be increased by up to 10ns if the signal input is output in approximately 8ns to 10ns. The LATCH pin is
more positive than the upper common mode limit and then designed to be driven with TTL or CMOS gates. It has no
switches back to within the common mode range. This built-in hysteresis.
effect is not seen for signals more negative than the lower
common mode limit. Measuring Response Time
The LT1016 is able to respond quickly to fast low level
Input Impedance and Bias Current signals because it has a very high gain-bandwidth product
Input bias current is measured with the output held at (≈50GHz), even at very high frequencies. To properly
1.4V. As with any simple NPN differential input stage, the measure the response of the LT1016 requires an input
LT1016 bias current will go to zero on an input that is low signal source with very fast rise times and exceptionally
and double on an input that is high. If both inputs are less clean settling characteristics. This last requirement comes
than 0.8V above V –, both input bias currents will go to about because the standard comparator test calls for an
zero. If either input exceeds the positive common mode input step size that is large compared to the overdrive
limit, input bias current will increase rapidly, approaching amplitude. Typical test conditions are 100mV step size
several milliamperes at VIN = V +. with only 5mV overdrive. This requires an input signal that
settles to within 1% (1mV) of final value in only a few
Differential input resistance at zero differential input nanoseconds with no ringing or “long tailing.” Ordinary
voltage is about 10kΩ, rapidly increasing as larger DC high speed pulse generators are not capable of generating
differential input signals are applied. Common mode input such a signal, and in any case, no ordinary oscilloscope is
resistance is about 4MΩ with zero differential input capable of displaying the waveform to check its fidelity.
voltage. With large differential input signals, the high input Some means must be used to inherently generate a fast,
will have an input resistance of about 2MΩ and the low clean edge with known final value.
input greater than 20MΩ.

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 LT1016
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APPLICATIO S I FOR ATIO
The circuit shown in Figure 1 is the best electronic means in its linear region, a feature no other high speed compara-
of generating a known fast, clean step to test comparators. tor has. Additionally, output stage switching does not
It uses a very fast transistor in a common base configura- appreciably change power supply current, further enhanc-
tion. The transistor is switched “off” with a fast edge from ing stability. These features make the application of the
the generator and the collector voltage settles to exactly 50GHz gain-bandwidth LT1016 considerably easier than
0V in just a few nanoseconds. The most important feature other fast comparators. Unfortunately, laws of physics
of this circuit is the lack of feedthrough from the generator dictate that the circuit environment the LT1016 works in
to the comparator input. This prevents overshoot on the must be properly prepared. The performance limits of high
comparator input that would give a false fast reading on speed circuitry are often determined by parasitics such as
comparator response time. stray capacitance, ground impedance and layout. Some of
these considerations are present in digital systems where
To adjust this circuit for exactly 5mV overdrive, V1 is
designers are comfortable describing bit patterns and
adjusted so that the LT1016 output under test settles to
memory access times in terms of nanoseconds. The
1.4V (in the linear region). Then V1 is changed –5V to set
LT1016 can be used in such fast digital systems and
overdrive at 5mV.
Figure␣ 2 shows just how fast the device is. The simple test
The test circuit shown measures low to high transition on circuit allows us to see that the LT1016’s (Trace B)
the “+” input. For opposite polarity transitions on the response to the pulse generator (Trace A) is as fast as a
output, simply reverse the inputs of the LT1016. TTL inverter (Trace C) even when the LT1016 has only
millivolts of input signal! Linear circuits operating with
High Speed Design Techniques this kind of speed make many engineers justifiably wary.
A substantial amount of design effort has made the LT1016 Nanosecond domain linear circuits are widely associated
relatively easy to use. It is much less prone to oscillation with oscillations, mysterious shifts in circuit characteris-
and other vagaries than some slower comparators, even tics, unintended modes of operation and outright failure to
with slow input signals. In particular, the LT1016 is stable function.

5V 0.01µF**

0V
–100mV 25Ω
+ Q 10× SCOPE PROBE
(CIN ≈ 10pF)
0.1µF 130Ω 25Ω LT1016
10k 10× SCOPE PROBE
2N3866 – L
Q (CIN ≈ 10pF)
PULSE
IN V1†
10Ω
0V
– 3V
– 5V 0.01µF
50Ω 400Ω 750Ω

– 5V * SEE TEXT FOR CIRCUIT EXPLANATION

** TOTAL LEAD LENGTH INCLUDING DEVICE PIN.
SOCKET AND CAPACITOR LEADS SHOULD BE 1016 F01

LESS THAN 0.5 IN. USE GROUND PLANE

† (VOS + OVERDRIVE) • 1000

Figure 1. Response Time Test Circuit

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LT1016
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APPLICATIO S I FOR ATIO
Other common problems include different measurement devices connected to an unbypassed supply can “commu-
results using various pieces of test equipment, inability to nicate” through the finite supply impedances, causing
make measurement connections to the circuit without erratic modes. Bypass capacitors furnish a simple way to
inducing spurious responses and dissimilar operation eliminate this problem by providing a local reservoir of
between two “identical” circuits. If the components used energy at the device. The bypass capacitor acts like an
in the circuit are good and the design is sound, all of the electrical flywheel to keep supply impedance low at high
above problems can usually be traced to failure to provide frequencies. The choice of what type of capacitors to use
a proper circuit “environment.” To learn how to do this for bypassing is a critical issue and should be approached
requires studying the causes of the aforementioned carefully. An unbypassed LT1016 is shown responding to
difficulties. a pulse input in Figure 3. The power supply the LT1016
sees at its terminals has high impedance at high fre-
By far the most common error involves power supply
quency. This impedance forms a voltage divider with the
bypassing. Bypassing is necessary to maintain low supply
LT1016, allowing the supply to move as internal condi-
impedance. DC resistance and inductance in supply wires
tions in the comparator change. This causes local feed-
and PC traces can quickly build up to unacceptable levels.
back and oscillation occurs. Although the LT1016
This allows the supply line to move as internal current
responds to the input pulse, its output is a blur of 100MHz
levels of the devices connected to it change. This will
oscillation. Always use bypass capacitors.
almost always cause unruly operation. In addition, several

TEST CIRCUIT
7404

PULSE TRACE A
GENERATOR 5V/DIV
1k
OUTPUTS
10Ω
+ TRACE B
5V/DIV
LT1016
–
TRACE C
5V/DIV
VREF
10ns/DIV 1016 F02

Figure 2. LT1016 vs a TTL Gate

2V/DIV

100ns/DIV 1016 F03

Figure 3. Unbypassed LT1016 Response

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 LT1016
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APPLICATIO S I FOR ATIO
In Figure 4 the LT1016’s supplies are bypassed, but it still problem in high speed circuits and can be quite confusing.
oscillates. In this case, the bypass units are either too far It is not due to suspension of natural law, but is traceable
from the device or are lossy capacitors. Use capacitors to a grossly miscompensated or improperly selected
with good high frequency characteristics and mount them oscilloscope probe. Use probes that match your
as close as possible to the LT1016. An inch of wire oscilloscope’s input characteristics and compensate them
between the capacitor and the LT1016 can cause prob- properly. Figure 6 shows another probe-induced problem.
lems. If operation in the linear region is desired, the Here, the amplitude seems correct but the 10ns response
LT1016 must be over a ground plate with good RF bypass time LT1016 appears to have 50ns edges! In this case, the
capacitors (≥0.01µF) having lead lengths less than 0.2 probe used is too heavily compensated or slow for the
inches. Do not use sockets. oscilloscope. Never use 1× or “straight” probes. Their
bandwidth is 20MHz or less and capacitive loading is high.
In Figure 5 the device is properly bypassed but a new
Check probe bandwidth to ensure it is adequate for
problem pops up. This photo shows both outputs of the
the measurement. Similarly, use an oscilloscope with
comparator. Trace A appears normal, but Trace B shows
adequate bandwidth.
an excursion of almost 8V—quite a trick for a device
running from a 5V supply. This is a commonly reported

2V/DIV

100ns/DIV 1016 F04

Figure 4. LT1016 Response with Poor Bypassing

TRACE A
2V/DIV

1V/DIV

TRACE B
2V/DIV

10ns/DIV 1016 F05 50ns/DIV 1016 F06

Figure 5. Improper Probe Compensation Causes Figure 6. Overcompensated or Slow Probes

Seemingly Unexplainable Amplitude Error Make Edges Look Too Slow

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LT1016
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APPLICATIO S I FOR ATIO
In Figure 7 the probes are properly selected and applied power supplies. The inductance created by a long device
but the LT1016’s output rings and distorts badly. In this ground lead permits mixing of ground currents, causing
case, the probe ground lead is too long. For general undesired effects in the device. The solution here is
purpose work most probes come with ground leads about simple. Keep the LT1016’s ground pin connection as short
six inches long. At low frequencies this is fine. At high (typically 1/4 inch) as possible and run it directly to a low
speed, the long ground lead looks inductive, causing the impedance ground. Do not use sockets.
ringing shown. High quality probes are always supplied Figure 9 addresses the issue of the “low impedance
with some short ground straps to deal with this problem. ground,” referred to previously. In this example, the
Some come with very short spring clips which fix directly output is clean except for chattering around the edges.
to the probe tip to facilitate a low impedance ground This photograph was generated by running the LT1016
connection. For fast work, the ground connection to the without a “ground plane.” A ground plane is formed by
probe should not exceed one inch in length. Keep the using a continuous conductive plane over the surface of
probe ground connection as short as possible. the circuit board. The only breaks in this plane are for the
Figure 8 shows the LT1016’s output (Trace B) oscillating circuit’s necessary current paths. The ground plane serves
near 40MHz as it responds to an input (Trace A). Note that two functions. Because it is flat (AC currents travel along
the input signal shows artifacts of the oscillation. This the surface of a conductor) and covers the entire area of
example is caused by improper grounding of the compara- the board, it provides a way to access a low inductance
tor. In this case, the LT1016’s GND pin connection is ground from anywhere on the board. Also, it minimizes the
one inch long. The ground lead of the LT1016 must be as effects of stray capacitance in the circuit by referring them
short as possible and connected directly to a low imped- to ground. This breaks up potential unintended and harm-
ance ground point. Any substantial impedance in the ful feedback paths. Always use a ground plane with the
LT1016’s ground path will generate effects like this. The LT1016 when input signal levels are low or slow moving.
reason for this is related to the necessity of bypassing the

1V/DIV

20ns/DIV 1016 F07

Figure 7. Typical Results Due to Poor Probe Grounding

TRACE A
1V/DIV

TRACE B
2V/DIV 2V/DIV

100ns/DIV 1016 F08

100ns/DIV 1016 F09

Figure 8. Excessive LT1016 Ground Path Figure 9. Transition Instabilities Due to No Ground Plane
Resistance Causes Oscillation

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 LT1016
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APPLICATIO S I FOR ATIO
“Fuzz” on the edges is the difficulty in Figure 10. This source resistance and 10pF to ground gives a 20ns time
condition appears similar to Figure 10, but the oscillation constant—significantly longer than the LT1016’s
is more stubborn and persists well after the output has response time. Keep source impedances low and mini-
gone low. This condition is due to stray capacitive feed- mize stray input capacitance to ground.
back from the outputs to the inputs. A 3kΩ input source Figure 12 shows another capacitance related problem.
impedance and 3pF of stray feedback allowed this oscilla- Here the output does not oscillate, but the transitions are
tion. The solution for this condition is not too difficult. discontinuous and relatively slow. The villain of this
Keep source impedances as low as possible, preferably 1k situation is a large output load capacitance. This could be
or less. Route output and input pins and components away caused by cable driving, excessive output lead length or
from each other. the input characteristics of the circuit being driven. In
The opposite of stray-caused oscillations appears in most situations this is undesirable and may be eliminated
Figure 11. Here, the output response (Trace B) badly lags by buffering heavy capacitive loads. In a few circum-
the input (Trace A). This is due to some combination of stances it may not affect overall circuit operation and is
high source impedance and stray capacitance to ground at tolerable. Consider the comparator’s output load
the input. The resulting RC forces a lagged response at the characteristics and their potential effect on the circuit. If
input and output delay occurs. An RC combination of 2k necessary, buffer the load.

2V/DIV

50ns/DIV 1016 F10

Figure 10. 3pF Stray Capacitive Feedback

with 3kΩ Source Can Cause Oscillation

TRACE A
2V/DIV
2V/DIV
TRACE B
2V/DIV

10ns/DIV 1016 F11 100ns/DIV 1016 F12

Figure 11. Stray 5pF Capacitance from Figure 12. Excessive Load Capacitance Forces Edge Distortion
Input to Ground Causes Delay

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LT1016
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APPLICATIO S I FOR ATIO
Another output-caused fault is shown in Figure 13. The 200ns-0.01% Sample-and-Hold Circuit
output transitions are initially correct but end in a ringing
Figure 14’s circuit uses the LT1016’s high speed to
condition. The key to the solution here is the ringing. What
improve upon a standard circuit function. The 200ns
is happening is caused by an output lead that is too long.
acquisition time is well beyond monolithic sample-and-
The output lead looks like an unterminated transmission
hold capabilities. Other specifications exceed the best
line at high frequencies and reflections occur. This ac-
commercial unit’s performance. This circuit also gets
counts for the abrupt reversal of direction on the leading
around many of the problems associated with standard
edge and the ringing. If the comparator is driving TTL this
sample-and-hold approaches, including FET switch errors
may be acceptable, but other loads may not tolerate it. In
and amplifier settling time. To achieve this, the LT1016’s
this instance, the direction reversal on the leading edge
high speed is used in a circuit which completely abandons
might cause trouble in a fast TTL load. Keep output lead
traditional sample-and-hold methods.
lengths short. If they get much longer than a few inches,
terminate with a resistor (typically 250Ω to 400Ω). Important specifications for this circuit include:
Acquisition Time <200ns
Common Mode Input Range ±3V
Droop 1µV/µs
Hold Step 2mV
1V/DIV Hold Settling Time 15ns
Feedthrough Rejection >>100dB

When the sample-and-hold line goes low, a linear ramp

starts just below the input level and ramps upward. When
50ns/DIV 1016 F13 the ramp voltage reaches the input voltage, A1 shuts off
Figure 13. Lengthy, Unterminated Output Lines the ramp, latches itself off and sends out a signal indicat-
Ring from Reflections ing sampling is complete.

5V

5.1k 1N4148 390Ω 470Ω 100Ω 1k

100Ω

1N4148 1k
DELAY
Q2 Q1 COMP
8pF
2N2907A 2N5160
Q7 –
0.1µF 5.1k 1.5k A1
2N5486
LT1016 NOW
1000pF
Q3 (POLYSTYRENE)
+
SN7402 SN7402
2N2369 Q6 LATCH
220Ω 2N2222
INPUT Q5 820Ω 390Ω
±3V 2N2222 1N4148
1.5k
LT1009 SN7402
2.5V 100Ω 300Ω
Q4
2N2907A
1.5k

SAMPLE-HOLD
–15V – 5V OUTPUT COMMAND (TTL) 1016 F14

Figure 14. 200ns Sample-and-Hold

12
 LT1016
U U W U
APPLICATIO S I FOR ATIO
1.8µs, 12-Bit A/D Converter
The LT1016’s high speed is used to implement a very fast To get faster conversion time, the clock is controlled by the
12-bit A/D converter in Figure 15. The circuit is a modified window comparator monitoring the DAC input summing
form of the standard successive approximation approach junction. Additionally, the DMOS FET clamps the DAC
and is faster than most commercial SAR 12-bit units. In output to ground at the beginning of each clock cycle,
this arrangement the 2504 successive approximation reg- shortening DAC settling time. After the fifth bit is con-
ister (SAR), A1 and C1 test each bit, beginning with the verted, the clock runs at maximum speed.
MSB, and produce a digital word representing VIN’s value.
5V

2.5k
0.01µF
5V
– 5V – 5V
150Ω 620Ω* 620Ω* 1
VIN 4 5
0V TO 10V – 8
1k
1000pF C1
5V LT1021 10V LT1016
10V 2.5k** 3
Q3 + 9
NC
10k** 10k 15V –15V 6
1k 7
14 15 13 19 20 17
1k
VR+ VR– GND IO V+ V–
0.01µF
16 18
–15V COMP AM6012 IO Q1 Q2
SD210 5V
150k
PARALLEL 15k
5V DIGITAL MSB LSB 27k
9 DATA
OUTPUT 24 Q6
6 5V V+ 11
–15V
74121 Q AM2504 D
13 Q4
CLK GND E S CC
IN B
3 4 5 7 12 1 14 3 150k

Q5 1/4 74S00

STATUS

5V
5V
1k 1
4 6 8
– NC
C3
0.1µF 10Ω LT1016
3
+ 7 9 1/4 74S00
5 1/4 74S08 1/4 74S08
– 5V D Q
5V 1/2 74S74
– 5V 1 CLK
3 6 8 PRS
+ PRS
Q1 TO Q5 RCA CA3127 ARRAY C2
1k
1N4148 LT1016 1/2 74S74
4
HP5082-2810 – 7 9
NC
RST
5 1/6 74S04 1/6 74S04
*1% FILM RESISTOR 0.1µF 10Ω
– 5V CLOCK CONVERT
**PRECISION 0.01%; VISHAY S-102
7.4MHz COMMAND
1016 F15

Figure 15. 12-Bit 1.8µs SAR A-to-D

13
LT1016
U
TYPICAL APPLICATIO S

Voltage Controlled Pulse Width Generator Single Supply Precision RC 1MHz Oscillator

5V FULL-SCALE
LM385 CALIBRATION ≈ 6.2k*
1.23V 500Ω

2N3906 1k

25Ω 5V
2N3906
1000pF 100pF 100pF
2.7k 5V
– Q
+ LT1016
2k Q
LT1016 START +
GND
VIN = 0V TO 2.5V – 5V LATCH
CEXT B
V–
–5V 74121
1k
Q A1 Q 10k
1N914
1%
2N3906 5V 5pF 74HC04
0µs TO 2.5µs
(MINIMUM
470pF 10k
WIDTH ≈ 0.05µs) 10k
1%
1% OUTPUTS

8.2k
* SELECT OR TRIM FOR f = 1.00MHz 1016 AI02

1016 AI01
–5V

50MHz Fiber Optic Receiver with Adaptive Trigger

5V

3k

10k

– –
0.005µF
LT1220 + 22M LT1097
500pF
+ LT1223 +
330Ω
– 1k
0.005µF 22M
0.1µF
+
50Ω OUTPUT
= HP 5082-4204 LT1016

NPN = 2N3904
–
PNP = 2N3906
3k
–5V
1016 AI03

14
 LT1016
U
TYPICAL APPLICATIO S

1MHz to 10MHz Crystal 18ns Fuse with Voltage Programmable Trip Point
Oscillator
Q1
2N3866
5V 28V

1MHz TO 10MHz
2k CRYSTAL 330Ω 1k*
9k*
Q2 2.4k +
– 5V
5V 2N2369 A1 10Ω
+ LT1193 9k* CARBON
V
+ Q 900Ω –
LT1016 FB 1k*
2k
OUTPUT
– Q 33pF 300Ω 200Ω
CALIBRATE
GND +
LATCH A2
V– LT1016
1k
TRIP SET
2k
L
– 0mA TO 250mA = 0V TO 2.5V

0.068µF * = 1% FILM RESISTOR RESET (NORMALLY OPEN) LOAD

A1 AND A2 USE ±5V SUPPLIES
1016 AI04

1016 AI05

U
APPE DIX A
About Level Shifts
The TTL output of the LT1016 will interface with many transistor’s supplies. This 3ns delay stage is ideal for
circuits directly. Many applications, however, require some driving FET switch gates. Q1, a gated current source,
form of level shifting of the output swing. With LT1016 switches the Baker-clamped output transistor, Q2. The
based circuits this is not trivial because it is desirable to heavy feedforward capacitor from the LT1016 is the key to
maintain very low delay in the level shifting stage. When low delay, providing Q2’s base with nearly ideal drive. This
designing level shifters, keep in mind that the TTL output capacitor loads the LT1016’s output transition (Trace A,
of the LT1016 is a sink-source pair (Figure A1) with good Figure A4), but Q2’s switching is clean (Trace B, Figure A4)
ability to drive capacitance (such as feedforward capaci- with 3ns delay on the rise and fall of the pulse.
tors).
Figure A5 is similar to Figure A2 except that a sink
Figure A2 shows a noninverting voltage gain stage with a transistor has replaced the Schottky diode. The two emit-
15V output. When the LT1016 switches, the base-emitter ter-followers drive a power MOSFET which switches 1A at
voltages at the 2N2369 reverse, causing it to switch very 15V. Most of the 7ns to 9ns delay in this stage occurs in
quickly. The 2N3866 emitter-follower gives a low imped- the MOSFET and the 2N2369.
ance output and the Schottky diode aids current sink
When designing level shifters, remember to use transis-
capability.
tors with fast switching times and high fTs. To get the kind
Figure A3 is a very versatile stage. It features a bipolar of results shown, switching times in the ns range and fTs
swing that may be programmed by varying the output approaching 1GHz are required.

15
LT1016
U
APPE DIX A

15V
+V 1k

2N2369
2N3866

OUTPUT = 0V TO
+ HP5082-2810
TYPICALLY 3V TO 4V LT1016
OUTPUT
– 1k
1k

NONINVERTING
VOLTAGE GAIN 12pF
LT1016 OUTPUT 1016 FA01
tRISE = 4ns
tFALL = 5ns 1016 fFA02

Figure A1 Figure A2

5V

+
INPUT LT1016 4.7k 430Ω
1N4148
– 5V
(TYP)
Q1
1000pF
2N2907
HP5082-2810 330Ω
OUTPUT TRANSISTOR SUPPLIES
5V
0.1µF 820Ω (SHOWN IN HEAVY LINES)
OUTPUT
CAN BE REFERENCED ANYWHERE
–10V
Q2 BETWEEN 15V AND –15V
2N2369
820Ω

INVERTING VOLTAGE GAIN—BIPOLAR SWING

–10V
tRISE = 3ns
(TYP) 1016 FA03
tFALL = 3ns
Figure A3

15V

TRACE A 1k RL
2V/DIV 2N2369
2N3866
+ POWER FET
TRACE B
10V/DIV LT1016
(INVERTED) 2N5160 1k
– 1k 12pF

NONINVERTING
VOLTAGE GAIN
tRISE = 7ns
5ns/DIV 1016 FA04
tFALL = 9ns 1016 FA05

Figure A4. Figure A3’s Waveforms Figure A5

16
 W

800Ω 800Ω 15pF 375Ω 2k 700Ω

Q32

+
50Ω 50Ω
Q15 Q30
+ Q31 D8
+ 170Ω
75Ω 75Ω 100pF Q29
W

15pF 150Ω 150Ω

D7
Q3 Q11 150Ω 150Ω Q33
Q22
SI PLIFIED SCHE ATIC

Q4 Q12 670Ω Q

+ INPUT Q1 Q5 Q6 Q13 Q28 Q35

90Ω Q34

D1 Q7 Q8 Q14
D6
Q36
1.3k 1.3k 3k 1.3k 1.3k 1.8k 1.8k
D2 1.2k 490Ω
Q51
1k
– INPUT Q2 Q9 Q10 955Ω
350Ω V+
1k
Q40 700Ω
830Ω 1.5k Q41 D9
Q49 Q23 Q24 + 170Ω Q43
+ 15pF
Q18 15pF Q44
Q17
LATCH Q50 565Ω 300Ω 100Ω 100Ω 300Ω D10
1.5k 1.5k Q42

670Ω Q
D5
Q25 Q26
Q16 D3 D4 Q19 90Ω Q46
Q20
Q21 210Ω 3.5k 3.5k 210Ω D10
Q45
Q47

65Ω 1.1k 165Ω 165Ω Q27 1.2k 480Ω

V– GND

17
LT1016
LT1016
U
PACKAGE DESCRIPTIO

N8 Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)

0.400*
(10.160)
MAX

8 7 6 5

0.255 ± 0.015*
(6.477 ± 0.381)

1 2 3 4

0.300 – 0.325 0.045 – 0.065 0.130 ± 0.005

(7.620 – 8.255) (1.143 – 1.651) (3.302 ± 0.127)

0.065
(1.651)
0.009 – 0.015 TYP
(0.229 – 0.381) 0.125
(3.175) 0.020
+0.035 MIN (0.508)
0.325 –0.015

( )
0.100 0.018 ± 0.003 MIN
+0.889
8.255 (2.54) (0.457 ± 0.076)
–0.381 BSC
N8 1098

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

18
 LT1016
U
PACKAGE DESCRIPTIO

S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)

0.189 – 0.197*
(4.801 – 5.004)
8 7 6 5

0.228 – 0.244 0.150 – 0.157**

(5.791 – 6.197) (3.810 – 3.988)

SO8 1298

1 2 3 4

0.010 – 0.020
× 45° 0.053 – 0.069
(0.254 – 0.508)
(1.346 – 1.752)
0.004 – 0.010
0.008 – 0.010
0°– 8° TYP (0.101 – 0.254)
(0.203 – 0.254)

0.016 – 0.050
0.014 – 0.019 0.050
(0.406 – 1.270)
(0.355 – 0.483) (1.270)
TYP BSC
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

19
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LT1016
U U W U
APPLICATIO S I FOR ATIO
1Hz to 10MHz V-to-F Converter A1’s 68pF feedback capacitor. The amplifier controls the
circuit’s output pulse generator, closing feedback loop
The LT1016 and the LT1122 FET input amplifier combine
around the integrating amplifier. To maintain the sum-
to form a high speed V-to-F converter in Figure 16. A
ming node at zero, the pulse generator runs at a frequency
variety of techniques is used to achieve a 1Hz to 10MHz
that permits enough charge pumping to offset the input
output. Overrange to 12MHz (VIN = 12V) is provided. This
signal. Thus, the output frequency is linearly related to the
circuit’s dynamic range is 140dB, or seven decades, which
input voltage.
is wider than any commercially available unit. The 10MHz
full-scale frequency is 10 times faster than monolithic To trim this circuit, apply 6.000V at the input and adjust the
V-to-F’s now available. The theory of operation is based on 2kΩ pot for 6.000MHz output. Next, excite the circuit with
the identity Q = CV. a 10.000V input and trim the 20k resistor for 10.000MHz
output. Repeat these adjustments until both points are
Each time the circuit produces an output pulse, it feeds
fixed. Linearity of the circuit is 0.03%, with full-scale drift
back a fixed quantity of charge, Q, to a summing node, Σ.
of 50ppm/°C. The LTC1050 chopper op amp servos the
The circuit’s input furnishes a comparison current at the
integrator’s noninverting input and eliminates the need for
summing node. This difference current is integrated in
a zero trim. Residual zero point error is 0.05Hz/°C.
INPUT OUTPUT
0V TO 10V 15pF 1Hz TO 10MHz 5V REF 15V 15V
Q1 –15V
(POLYSTYRENE)
+
4.7µF A4 A3
LT1010 LT1006 470Ω
+
Q2
–
15V 0.1µF
2k
6MHz 5V 6.8Ω
TRIM 68pF 1.2k
10k* Σ LM134
100k*
– 8 5V – 5V
100k*
A1
LT1122 +
A2
+ 100Ω LT1016 LT1034-1.2V

10k – 5V
– LT1034-2.5V
150pF
2.2M*
Q3

1k 5pF

5V
Q4
0.02µF
–
= 2N2369 36k 1k 10M
LTC1050
= 74HC14 +
+ 10µF 20k
10MHz
* = 1% METAL FILM/10ppm/°C TRIM
BYPASS ALL ICs WITH 2.2µF ON – 5V
EACH SUPPLY DIRECTLY AT PINS 1016 F16

Figure 16. 1Hz to 10MHz V-to-F Converter. Linearity is Better Than 0.03% with 50ppm/°C Drift

RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LT1116 12ns Single Supply Ground-Sensing Comparator Single Supply Version of LT1016, LT1016 Pinout and Functionality
LT1394 7ns, UltraFast, Single Supply Comparator 6mA, 100MHz Data Rate, LT1016 Pinout and Functionality
LT1671 60ns, Low Power, Single Supply Comparator 450µA, Single Supply Comparator, LT1016 Pinout and Functionality
LT1711/LT1712 Single/Dual 4.5ns 3V/5V/±5V Rail-to-Rail Comparators Rail-to-Rail Inputs and Outputs
LT1713/LT1714 Single/Dual 7ns 3V/5V/±5V Rail-to-Rail Comparators 5mA per Comparator, Rail-to-Rail Inputs and Outputs
LT1715 Dual 150MHz 4ns 3V/5V Comparator 150MHz Toggle Rate, Independent Input/Output Supplies
LT1719/LT1720/LT1721 Single/Dual/Quad 4.5ns 3V/5V Comparators 4mA per Comparator, Ground-Sensing Rail-to-Rail Inputs and Outputs

1016fc LT/TP 0601 1.5K REV C • PRINTED IN USA

Linear Technology Corporation
20 1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com  LINEAR TECHNOLOGY CORPORATION 1991