Infineon-CY8C21334 CY8C21534 Automotive PSoC Programmable System-on-Chip-DataSheet-v12 00-EN
Infineon-CY8C21334 CY8C21534 Automotive PSoC Programmable System-on-Chip-DataSheet-v12 00-EN
Infineon-CY8C21334 CY8C21534 Automotive PSoC Programmable System-on-Chip-DataSheet-v12 00-EN
Automotive
®
PSoC Programmable System-on-Chip™
Features ■ Programmable pin configurations
❐ 25 mA sink, 10 mA drive on all GPIOs
■ Automotive Electronics Council (AEC) Q100 qualified
❐ Pull-up, pull-down, high Z, strong, or open drain drive modes
■ Powerful Harvard-architecture processor on all GPIOs
❐ M8C processor speeds up to 24 MHz ❐ Analog input on all GPIOs
❐ Low power at high speed ❐ Configurable interrupt on all GPIOs
❐ Operating voltage: 3.0 V to 5.25 V ■ Versatile analog mux
❐ Automotive temperature range: –40 C to +85 C ❐ Common internal analog bus
®
■ Advanced peripherals (PSoC blocks) ❐ Simultaneous connection of I/O combinations
❐ Four analog Type E PSoC blocks provide: ■ Additional system resources
• Two comparators with digital-to-analog converter (DAC) 2
❐ Inter-Integrated Circuit (I C™) master, slave, or multi-master
references operation up to 400 kHz
• Up to 10-bit single or dual, 24 channel analog-to-digital ❐ Watchdog and sleep timers
converters (ADC) ❐ User-configurable low-voltage detection (LVD)
❐ Four digital PSoC blocks provide: ❐ Integrated supervisory circuit
• 8- to 32-bit timers, counters, and pulse width modulators ❐ On-chip precision voltage reference
(PWMs)
• Cyclical redundancy check (CRC) and pseudo-random Logic Block Diagram
sequence (PRS) modules
• Full- or half-duplex UART
• SPI master or slave
• Connectable to all general purpose I/O (GPIO) pins
❐ Complex peripherals by combining blocks
• Capacitive sensing application capability
■ Flexible on-chip memory
❐ 8 KB flash program storage
❐ 512 bytes SRAM data storage
❐ In-system serial programming (ISSP)
❐ Partial flash updates
❐ Flexible protection modes
❐ EEPROM emulation in flash
■ Complete development tools
❐ Free development software (PSoC Designer™)
❐ Full-featured in-circuit emulator (ICE) and programmer
❐ Full-speed emulation
❐ Complex breakpoint structure
❐ 128 KB trace memory
■ Precision, programmable clocking
❐ Internal ±5% 24 MHz oscillator
❐ Internal low-speed, low-power oscillator for Watchdog and
Sleep functionality
❐ Optional external oscillator, up to 24 MHz
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-12550 Rev. *K Revised March 9, 2017
CY8C21334/CY8C21534
Contents
PSoC Functional Overview .............................................. 3 DC Electrical Characteristics ..................................... 15
The PSoC Core ........................................................... 3 AC Electrical Characteristics ..................................... 18
The Digital System ...................................................... 3 Packaging Information ................................................... 24
The Analog System ..................................................... 4 Packaging Dimensions .............................................. 24
Additional System Resources ..................................... 4 Thermal Impedances ................................................. 25
PSoC Device Characteristics ...................................... 5 Solder Reflow Specifications ..................................... 25
Getting Started .................................................................. 5 Tape and Reel Information ........................................ 26
Application Notes ........................................................ 5 Development Tool Selection ......................................... 28
Development Kits ........................................................ 5 Software .................................................................... 28
Training ....................................................................... 5 Development Kits ...................................................... 28
CYPros Consultants .................................................... 5 Evaluation Tools ........................................................ 28
Solutions Library .......................................................... 5 Device Programmers ................................................. 29
Technical Support ....................................................... 5 Accessories (Emulation and Programming) .............. 29
Development Tools .......................................................... 6 Ordering Information ...................................................... 30
PSoC Designer Software Subsystems ........................ 6 Ordering Code Definitions ......................................... 30
Designing with PSoC Designer ....................................... 7 Acronyms ........................................................................ 31
Select Components ..................................................... 7 Reference Documents .................................................... 31
Configure Components ............................................... 7 Document Conventions ................................................. 32
Organize and Connect ................................................ 7 Units of Measure ....................................................... 32
Generate, Verify, and Debug ....................................... 7 Numeric Conventions .................................................... 32
Pinouts .............................................................................. 8 Glossary .......................................................................... 32
20-Pin Part Pinout ....................................................... 8 Document History Page ................................................. 37
28-Pin Part Pinout ....................................................... 9 Sales, Solutions, and Legal Information ...................... 39
Registers ......................................................................... 10 Worldwide Sales and Design Support ....................... 39
Register Conventions ................................................ 10 Products .................................................................... 39
Register Mapping Tables .......................................... 10 PSoC® Solutions ...................................................... 39
Electrical Specifications ................................................ 13 Cypress Developer Community ................................. 39
Absolute Maximum Ratings ....................................... 14 Technical Support ..................................................... 39
Operating Temperature ............................................. 14
PSoC Functional Overview which are called user modules. Digital peripheral configurations
include those listed.
The PSoC family consists of many devices with on-chip
controllers. These devices are designed to replace multiple ■ PWMs (8- to 32-bit)
traditional microcontroller unit (MCU)-based system ■ PWMs with dead band (8- to 24-bit)
components with one, low-cost single-chip programmable
component. A PSoC device includes configurable blocks of ■ Counters (8- to 32-bit)
analog and digital logic, and programmable interconnect. This
■ Timers (8- to 32-bit)
architecture makes it possible for you to create customized
peripheral configurations, to match the requirements of each ■ Full or half-duplex 8-bit UART with selectable parity
individual application. Additionally, a fast CPU, flash program
memory, SRAM data memory, and configurable I/O are included ■ SPI master and slave
in a range of convenient pinouts. ■ I2C master, slave, or multi-master (implemented in a dedicated
The PSoC architecture, as illustrated in the Logic Block Diagram I2C block)
on page 1, comprises of four main areas: the core, the system
■ Cyclical redundancy checker/generator (16-bit)
resources, the digital system, and the analog system. Configu-
rable global bus resources allow all the device resources to be ■ Infrared Data Association (IrDA)
combined into a complete custom system. Each CY8C21x34
PSoC device includes four digital blocks and four analog blocks. ■ PRS generators (8- to 32-bit)
Depending on the PSoC package, up to 24 GPIOs are also The digital blocks can be connected to any GPIO through a
included. The GPIOs provide access to the global digital and series of global buses that can route any signal to any pin. The
analog interconnects. buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
The PSoC Core constraints of a fixed peripheral controller.
The PSoC core is a powerful engine that supports a rich Figure 1. Digital System Block Diagram
instruction set. It encompasses SRAM for data storage, an
Port 3 Port 1
interrupt controller, sleep, and watchdog timers, and an internal
Port 2 Port 0
main oscillator (IMO) and internal low-speed oscillator (ILO). The
CPU core, called the M8C, is a powerful processor with speeds
up to 24 MHz. The M8C is a four-million instructions per second Digital Clocks To System Bus To Analog
(MIPS) 8-bit Harvard-architecture microprocessor. From Core System
Configuration
Row Output
Row Input
through a series of global buses that can route any signal to any 8 8
pin. This frees designs from the constraints of a fixed peripheral 8 8
controller.
The Analog System is composed of four analog PSoC blocks, GIE[7:0] Global Digital GOE[7:0]
supporting comparators and analog-to-digital conversion with up GIO[7:0] Interconnect
GOO[7:0]
to 10 bits of precision.
The Digital System Digital blocks are provided in rows of four, where the number of
The digital system is composed of four digital PSoC blocks. Each blocks varies by PSoC device family. This allows you the
block is an 8-bit resource that can be used alone or combined optimum choice of system resources for your application. Family
with other blocks to form 8-, 16-, 24-, and 32-bit peripherals, resources are shown in Table 1 on page 5.
ASE10 ASE11
Getting Started
For in-depth information, along with detailed programming CYPros Consultants
details, see the PSoC® Technical Reference Manual.
Certified PSoC consultants offer everything from technical
For up-to-date ordering, packaging, and electrical specification assistance to completed PSoC designs. To contact or become a
information, see the latest PSoC device datasheets on the web. PSoC consultant go to the CYPros Consultants web site.
Application Notes Solutions Library
Cypress application notes are an excellent introduction to the Visit our growing library of solution focused designs. Here you
wide variety of possible PSoC designs. can find various application designs that include firmware and
hardware design files that enable you to complete your designs
Development Kits quickly.
PSoC Development Kits are available online from and through a
growing number of regional and global distributors, which Technical Support
include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Technical support – including a searchable Knowledge Base
Newark. articles and technical forums – is also available online. If you
cannot find an answer to your question, call our Technical
Training Support hotline at 1-800-541-4736.
Free PSoC technical training (on demand, webinars, and
workshops), which is available online via www.cypress.com,
covers a wide variety of topics and skill levels to assist you in
your designs.
Notes
1. Automotive qualified devices available in this group.
2. Limited analog functionality.
3. Two analog blocks and one CapSense® block.
Development Tools
PSoC Designer™ is the revolutionary integrated design Code Generation Tools
environment (IDE) that you can use to customize PSoC to meet The code generation tools work seamlessly within the
your specific application requirements. PSoC Designer software PSoC Designer interface and have been tested with a full range
accelerates system design and time to market. Develop your of debugging tools. You can develop your design in C, assembly,
applications using a library of precharacterized analog and digital or a combination of the two.
peripherals (called user modules) in a drag-and-drop design
environment. Then, customize your design by leveraging the Assemblers. The assemblers allow you to merge assembly
dynamically generated application programming interface (API) code seamlessly with C code. Link libraries automatically use
libraries of code. Finally, debug and test your designs with the absolute addressing or are compiled in relative mode, and are
integrated debug environment, including in-circuit emulation and linked with other software modules to get absolute addressing.
standard software debug features. PSoC Designer includes: C Language Compilers. C language compilers are available
■ Application editor graphical user interface (GUI) for device and that support the PSoC family of devices. The products allow you
user module configuration and dynamic reconfiguration to create complete C programs for the PSoC family devices. The
optimizing C compilers provide all of the features of C, tailored
■ Extensive user module catalog to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
■ Integrated source-code editor (C and assembly) display support, and extended math functionality.
■ Free C compiler with no size restrictions or time limits
Debugger
■ Built-in debugger PSoC Designer has a debug environment that provides
■ In-circuit emulation hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
■ Built-in support for communication interfaces: device. Debugger commands allow you to read and program and
2
❐ Hardware and software I C slaves and masters read and write data memory, and read and write I/O registers.
❐ Full-speed USB 2.0 You can read and write CPU registers, set and clear breakpoints,
❐ Up to four full-duplex universal asynchronous and provide program run, halt, and step control. The debugger
receiver/transmitters (UARTs), SPI master and slave, and also allows you to create a trace buffer of registers and memory
wireless locations of interest.
PSoC Designer supports the entire library of PSoC 1 devices and
Online Help System
runs on Windows XP, Windows Vista, and Windows 7.
The online help system displays online, context-sensitive help.
PSoC Designer Software Subsystems Designed for procedural and quick reference, each functional
subsystem has its own context-sensitive help. This system also
Design Entry provides tutorials and links to FAQs and an online support Forum
In the chip-level view, choose a base device to work with. Then to aid the designer.
select different onboard analog and digital components that use
the PSoC blocks, which are called user modules. Examples of In-Circuit Emulator
user modules are ADCs, DACs, amplifiers, and filters. Configure A low-cost, high-functionality in-circuit emulator (ICE) is
the user modules for your chosen application and connect them available for development support. This hardware can program
to each other and to the proper pins. Then generate your project. single devices.
This prepopulates your project with APIs and libraries that you The emulator consists of a base unit that connects to the PC
can use to program your application. using a USB port. The base unit is universal and operates with
The tool also supports easy development of multiple all PSoC devices. Emulation pods for each device family are
configurations and dynamic reconfiguration. Dynamic available separately. The emulation pod takes the place of the
reconfiguration makes it possible to change configurations at run PSoC device in the target board and performs full-speed
time. In essence, this allows you to use more than 100 percent (24 MHz) operation.
of PSoC's resources for an application.
Pinouts
The CY8C21x34 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port
pin (labeled with a “P”) is capable of digital I/O and connection to the common analog bus. However, VSS, VDD, and XRES are not
capable of digital I/O.
Note
4. These are the ISSP pins, which are not high Z when coming out of POR. See the PSoC Technical Reference Manual for details.
Note
5. These are the ISSP pins, which are not high Z when coming out of POR. See the PSoC Technical Reference Manual for details.
Registers
Register Conventions Register Mapping Tables
This section lists the registers of the CY8C21x34 PSoC device. The PSoC device has a total register address space of
For detailed register information, refer to the PSoC Technical 512 bytes. The register space is referred to as I/O space and is
Reference Manual. divided into two banks, bank 0 and bank 1. The XIO bit in the
The register conventions specific to this section are listed in the Flag register (CPU_F) determines which bank the user is
following table. currently in. When the XIO bit is set to ‘1’, the user is in bank 1.
Note In the following register mapping tables, blank fields are
Convention Description Reserved and must not be accessed.
R Read register or bit(s)
W Write register or bit(s)
L Logical register or bit(s)
C Clearable register or bit(s)
# Access is bit specific
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C21x34 PSoC device. For the most up-to-date electrical
specifications, visit the Cypress website at http://www.cypress.com.
Specifications are valid for –40 C TA 85 C and TJ 100 C as specified, except where noted. Refer to Table 12 on page 18 for
the electrical specifications for the IMO using slow IMO (SLIMO) mode.
Figure 5. Voltage versus CPU Frequency Figure 6. IMO Frequency Trim Options
5.25
lid ing 5.25
Va rat ion SLIMO SLIMO
pe g
4.75
O Re Mode = 1 Mode = 0
4.75
3.6 3.6
lid ing SLIMO SLIMO
Va rat ion
pe g Mode = 1 Mode = 0
3.0
O Re 3.0
0 0
93 kHz 12 MHz 24 MHz 6 MHz 12 MHz 24 MHz
CPU Frequency
IMO Frequency
(nominal setting)
Operating Temperature
DC Electrical Characteristics
DC Chip Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 C TA 85 C or 3.0 V to 3.6 V and –40 C TA 85 C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 C
and are for design guidance only.
Table 6. DC Chip Level Specifications
Symbol Description Min Typ Max Units Notes
VDD Supply voltage 3.0 – 5.25 V See table titled DC POR and LVD Specifi-
cations on page 16
IDD Supply current, IMO = 24 MHz – 4 6 mA Conditions are VDD = 5.25 V, CPU =
3 MHz, 48 MHz disabled. VC1 = 1.5 MHz,
VC2 = 93.75 kHz, VC3 = 0.366 kHz
IDD3 Supply current, IMO = 6 MHz using – 2 4 mA Conditions are VDD = 3.3 V, CPU =
SLIMO mode 3 MHz, 48 MHz disabled. VC1 = 375 kHz,
VC2 = 23.4 kHz, VC3 = 0.091 kHz
ISB1 Sleep (mode) current with POR, LVD, – 2.8 7 A VDD = 3.3 V, –40 C TA 85 C
sleep timer, WDT, and ILO active
ISB2 Sleep (mode) current with POR, LVD, – 5 15 A VDD = 5.25 V, –40 C TA 85 C
sleep timer, WDT, and ILO active
VREF Reference voltage (Bandgap) 1.28 1.30 1.32 V Trimmed for appropriate VDD range
DC GPIO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 C TA 85 C or 3.0 V to 3.6 V and –40 C TA 85 C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 C
and are for design guidance only.
Notes
6. Atypical behavior: IEBOA of Port 0 Pin 0 is below 1 nA at 25 C; 50 nA over temperature. Use Port 0 Pins 1-7 for the lowest leakage of 200 pA.
7. Always greater than 50 mV above VPPOR1 (PORLEV[1:0] = 01b) for falling supply.
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 C TA 85 C or 3.0 V to 3.6 V and –40 C TA 85 C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 C
and are for design guidance only.
Notes
8. The erase/write cycle limit per block (FlashENPB) is only guaranteed if the device operates within one voltage range. Voltage ranges are 3.0 V to 3.6 V and 4.75 V to
5.25 V.
9. For the full temperature range, the user must employ a temperature sensor user module (FlashTemp) or other temperature sensor, and feed the result to the temperature
argument before writing. Refer to the Flash APIs Application Note AN2015 for more information.
10. The maximum total number of allowed erase/write cycles is the minimum FlashENPB value multiplied by the number of flash blocks in the device.
AC Electrical Characteristics
AC Chip Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 C TA 85 C or 3.0 V to 3.6 V and –40 C TA 85 C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 C
and are for design guidance only.
Notes
11. Accuracy derived from IMO with appropriate trim for VDD range.
12. See the individual user module datasheets for information on maximum frequencies for user modules.
13. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information.
AC GPIO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 C TA 85 C or 3.0 V to 3.6 V and –40 C TA 85 C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 C
and are for design guidance only.
90%
GPIO
Pin
Output
Voltage
10%
TRiseF TFallF
TRiseS TFallS
Notes
14. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
15. Accuracy derived from IMO with appropriate trim for VDD range.
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 C TA 85 C or 3.0 V to 3.6 V and –40 C TA 85 C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 C
and are for design guidance only.
Note
16. For the full temperature range, the user must employ a temperature sensor user module (FlashTemp) or other temperature sensor, and feed the result to the
temperature argument before writing. Refer to the Flash APIs Application Note AN2015 for more information.
AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 C TA 85 C or 3.0 V to 3.6 V and –40 C TA 85 C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 C
and are for design guidance only.
Figure 8. Definition for Timing for Fast/Standard Mode on the I2C Bus
I2C_SDA
TSUDATI2C TSPI2C
THDSTAI2C THDDATI2CTSUSTAI2C TBUFI2C
I2C_SCL
Notes
17. FSCLI2C is derived from SysClk of the PSoC. This specification assumes that SysClk is operating at 24 MHz, nominal. If SysClk is at a lower frequency, then the
FSCLI2C specification adjusts accordingly
18. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSUDATI2C 250 ns must then be met. This is automatically the
case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line trmax +tSUDATI2C = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Packaging Information
This section illustrates the packaging specifications for the CY8C21x34 PSoC device, along with the thermal impedances for each
package.
Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of
the emulation tools' dimensions, refer to the emulator pod drawings at http://www.cypress.com.
Packaging Dimensions
Figure 9. 20-pin SSOP (210 Mils) O20.21 Package Outline, 51-85077
51-85077 *F
Figure 10. 28-pin SSOP (210 Mils) O28.21 Package Outline, 51-85079
51-85079 *F
Note
19. TJ = TA + Power x JA
51-51101 *C
Figure 12. 28-pin SSOP (209 Mils) C-PAK Carrier Tape Drawing, 51-51100
51-51100 *D
Software pre-defined control circuitry and plug-in hardware. The kit comes
with a control boards for CY8C20x34 and CY8C21x34 devices
PSoC Designer as well as a breadboard module and a button(5)/slider module.
At the core of the PSoC development software suite is
PSoC Designer. Utilized by thousands of PSoC developers, this Evaluation Tools
robust software has been facilitating PSoC designs for years. All evaluation tools can be purchased from the Cypress Online
PSoC Designer is available free of charge at Store.
http://www.cypress.com. PSoC Designer comes with a free C
compiler. CY3210-PSoCEval1
The CY3210-PSoCEval1 kit features an evaluation board and
PSoC Programmer the MiniProg1 programming unit. The evaluation board includes
Flexible enough to be used on the bench in development, yet an LCD module, potentiometer, LEDs, an RS-232 port, and
suitable for factory programming, PSoC Programmer works plenty of breadboarding space to meet all of your evaluation
either as a standalone programming application or it can operate needs. The kit includes:
directly from PSoC Designer. PSoC Programmer software is
■ Evaluation board with LCD module
compatible with both PSoC ICE-Cube in-circuit emulator and
PSoC MiniProg. PSoC programmer is available free of charge at ■ MiniProg programming unit
http://www.cypress.com.
■ Two 28-Pin CY8C29466-24PXI PDIP PSoC device samples
Development Kits
■ PSoC Designer software CD
All development kits can be purchased from the Cypress Online
Store. The online store also has the most up-to-date information ■ Getting Started guide
on kit contents, descriptions, and availability. ■ USB 2.0 cable
CY3215-DK Basic Development Kit CY3235-ProxDet
The CY3215-DK is for prototyping and development with PSoC The CY3235 CapSense Proximity Detection Demonstration Kit
Designer. This kit supports in-circuit emulation, and the software allows quick and easy demonstration of a PSoC
interface allows you to run, halt, and single step the processor, CapSense-enabled device (CY8C21x34) to accurately sense
and view the contents of specific memory locations. Advanced the proximity of a hand or finger along the length of a wire
emulation features are also supported through PSoC Designer. antenna. The kit includes:
The kit includes:
■ Proximity detection demo board w/antenna
■ ICE-Cube unit
■ I2C to USB debugging/communication bridge
■ 28-Pin PDIP emulation pod for CY8C29466-24PXI
■ USB cable (6 feet)
■ Two 28-Pin CY8C29466-24PXI PDIP PSoC device samples
■ Supporting software CD
■ PSoC designer software CD
■ CY3235-ProxDet Quick Start guide
■ ISSP cable
■ One CY8C24894 PSoC device on I2C-USB bridge
■ MiniEval socket programming and evaluation board
■ One CY8C21434 PSoC device on proximity detection demo
■ Backward compatibility cable (for connecting to legacy pods) board
■ Universal 110/220 power supply (12 V)
CY3210-21X34 Evaluation Pod (EvalPod)
■ European plug adapter The CY3210-21X34 PSoC EvalPods are pods that connect to
■ USB 2.0 cable the ICE in-circuit emulator (CY3215-DK kit) to allow debugging
capability. They can also function as a standalone device without
■ Getting Started guide debugging capability. The EvalPod has a 28-pin DIP footprint on
the bottom for easy connection to development kits or other
■ Development kit registration form
hardware. The top of the EvalPod has prototyping headers for
CY3280-BK1 easy connection to the device's pins. CY3210-21X34 provides
evaluation of the CY8C21x34 PSoC device family.
The CY3280-BK1 Universal CapSense Control Kit is designed
for easy prototyping and debug of CapSense designs with
Notes
20. Pod kit contains an emulation pod, a flex-cable (connects the pod to the ICE), two feet, and device samples.
21. Foot kit includes surface mount feet that can be soldered to the target PCB.
22. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters are available at
http://www.emulation.com.
Ordering Information
The following table lists the CY8C21x34 PSoC device’s key package features and ordering codes.
Table 24. PSoC Device Key Features and Ordering Information
Temperature
Digital I/O
XRES Pin
Ordering
Package
Outputs
Analog
(Bytes)
(Bytes)
Analog
Analog
Blocks
Blocks
Range
Digital
Inputs
SRAM
Flash
Code
Pins
20-Pin (210-Mil) SSOP CY8C21334-24PVXA 8K 512 –40 C to +85 C 4 4 16 16 0 Yes
20-Pin (210-Mil) SSOP CY8C21334-24PVXAT 8K 512 –40 C to +85 C 4 4 16 16 0 Yes
(Tape and Reel)
28-Pin (210-Mil) SSOP CY8C21534-24PVXA 8K 512 –40 C to +85 C 4 4 24 24 0 Yes
28-Pin (210-Mil) SSOP CY8C21534-24PVXAT 8K 512 –40 C to +85 C 4 4 24 24 0 Yes
(Tape and Reel)
CY 8 C 21 xxx-24xx
Package Type: Thermal Rating:
PX = PDIP Pb-free A = Automotive –40 C to +85 C
SX = SOIC Pb-free C = Commercial
PVX = SSOP Pb-free I = Industrial
LFX = QFN Pb-free E = Automotive Extended –40 C to +125 C
AX = TQFP Pb-free
CPU Speed: 24 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = PSoC
Company ID: CY = Cypress
Acronyms
Table 25 lists the acronyms that are used in this document.
Table 25. Acronyms Used in this Datasheet
Reference Documents
CY8CPLC20, CY8CLED16P01, CY8C29x66, CY8C27x43, CY8C24x94, CY8C24x23, CY8C24x23A, CY8C22x13, CY8C21x34,
CY8C21x23, CY7C64215, CY7C603xx, CY8CNP1xx, and CYWUSB6953 PSoC® Programmable System-on-Chip Technical
Reference Manual (TRM) (001-14463)
Design Aids – Reading and Writing PSoC® Flash – AN2015 (001-40459)
Document Conventions
Units of Measure
The following table lists the units of measure that are used in this document.
Numeric Conventions
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’).
Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended
lowercase ‘b’ (for example, ‘01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or ‘0x’ are in decimal format.
Glossary
active high 1. A logic signal having its asserted state as the logic 1 state.
2. A logic signal having the logic 1 state as the higher voltage of the two states.
analog blocks The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks.
These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more.
analog-to-digital A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts
converter (ADC) a voltage to a digital number. The digital-to-analog converter (DAC) performs the reverse operation.
Application A series of software routines that comprise an interface between a computer application and lower level services
programming and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that create
interface (API) software applications.
asynchronous A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal.
bandgap A stable voltage reference design that matches the positive temperature coefficient of VT with the negative
reference temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference.
bandwidth 1. The frequency range of a message or information processing system measured in hertz.
2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is
sometimes represented more specifically as, for example, full width at half maximum.
Glossary (continued)
buffer 1. A storage area for data that is used to compensate for a speed difference, when transferring data from one
device to another. Usually refers to an area reserved for I/O operations, into which data is read, or from which
data is written.
2. A portion of memory set aside to store data, often before it is sent to an external device or as it is received
from an external device.
3. An amplifier used to lower the output impedance of a system.
bus 1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing
patterns.
2. A set of signals performing a common function and carrying similar data. Typically represented using vector
notation; for example, address[7:0].
3. One or more conductors that serve as a common connection for a group of related devices.
clock The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to
synchronize different logic blocks.
comparator An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy
predetermined amplitude requirements.
compiler A program that translates a high level language, such as C, into machine language.
configuration In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to ‘1’.
space
crystal oscillator An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less
sensitive to ambient temperature than other circuit components.
cyclic redundancy A calculation used to detect errors in data communications, typically performed using a linear feedback shift
check (CRC) register. Similar calculations may be used for a variety of other purposes such as data compression.
data bus A bi-directional set of signals used by a computer to convey information from a memory location to the central
processing unit and vice versa. More generally, a set of signals used to convey data between digital functions.
debugger A hardware and software system that allows you to analyze the operation of the system under development. A
debugger usually allows the developer to step through the firmware one step at a time, set break points, and
analyze memory.
dead band A period of time when neither of two or more signals are in their active state or in transition.
digital blocks The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator,
pseudo-random number generator, or SPI.
digital-to-analog A device that changes a digital signal to an analog signal of corresponding magnitude. The analog-to-digital
converter (DAC) converter (ADC) performs the reverse operation.
Glossary (continued)
duty cycle The relationship of a clock period high time to its low time, expressed as a percent.
emulator Duplicates (provides an emulation of) the functions of one system with a different system, so that the second
system appears to behave like the first system.
external reset An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop
(XRES) and return to a pre-defined state.
flash An electrically programmable and erasable, non-volatile technology that provides you the programmability and
data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power is
off.
flash block The smallest amount of flash ROM space that may be programmed at one time and the smallest amount of flash
space that may be protected.
frequency The number of cycles or events per unit of time, for a periodic function.
gain The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually
expressed in dB.
I2C A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). It is used to connect
low-speed peripherals in an embedded system. The original system was created in the early 1980s as a battery
control interface, but it was later used as a simple internal bus system for building control electronics. I2C uses
only two bi-directional pins, clock and data, both running at the VDD suppy voltage and pulled high with resistors.
The bus operates up to100 kbits/second in standard mode and 400 kbits/second in fast mode.
ICE The in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging
device activity in a software environment (PSoC Designer).
input/output (I/O) A device that introduces data into or extracts data from a system.
interrupt A suspension of a process, such as the execution of a computer program, caused by an event external to that
process, and performed in such a way that the process can be resumed.
interrupt service A block of code that normal code execution is diverted to when the CPU receives a hardware interrupt. Many
routine (ISR) interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends
with the RETI instruction, returning the device to the point in the program where it left normal program execution.
jitter 1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on
serial data streams.
2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between
successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles.
low voltage detect A circuit that senses VDD and provides an interrupt to the system when VDD falls below a selected threshold.
(LVD)
M8C An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by
interfacing to the flash, SRAM, and register space.
master device A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in
width, the master device is the one that controls the timing for data exchanges between the cascaded devices
and an external interface. The controlled device is called the slave device.
Glossary (continued)
microcontroller An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a
microcontroller typically includes memory, timing circuits, and I/O circuitry. The reason for this is to permit the
realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This
in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for
general-purpose computation as is a microprocessor.
mixed-signal The reference to a circuit containing both analog and digital techniques and components.
noise 1. A disturbance that affects a signal and that may distort the information carried by the signal.
2. The random variations of one or more characteristics of any entity such as voltage, current, or data.
oscillator A circuit that may be crystal controlled and is used to generate a clock frequency.
parity A technique for testing transmitted data. Typically, a binary digit is added to the data to make the sum of all the
digits of the binary data either always even (even parity) or always odd (odd parity).
phase-locked An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference
loop (PLL) signal.
pinouts The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their
physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between
schematic and PCB design (both being computer generated files) and may also involve pin names.
power-on reset A circuit that forces the PSoC device to reset when the voltage is below a pre-set level. This is one type of hardware
(POR) reset.
PSoC® Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-on-Chip™ is a trademark
of Cypress.
pulse width An output in the form of duty cycle which varies as a function of the applied value.
modulator (PWM)
RAM An acronym for random access memory. A data-storage device from which data can be read out and new data
can be written in.
reset A means of bringing a system back to a known state. See hardware reset and software reset.
ROM An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot
be written in.
serial 1. Pertaining to a process in which all events occur one after the other.
2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or
channel.
settling time The time it takes for an output signal or value to stabilize after the input has changed from one value to another.
Glossary (continued)
shift register A memory storage device that sequentially shifts a word either left or right to output a stream of serial data.
slave device A device that allows another device to control the timing for data exchanges between two devices. Or when
devices are cascaded in width, the slave device is the one that allows another device to control the timing of data
exchanges between the cascaded devices and an external interface. The controlling device is called the master
device.
SRAM An acronym for static random access memory. A memory device where you can store and retrieve data at a high
rate of speed. The term static is used because, after a value is loaded into an SRAM cell, it remains unchanged
until it is explicitly altered or until power is removed from the device.
SROM An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate
circuitry, and perform flash operations. The functions of the SROM may be accessed in normal user code,
operating from flash.
stop bit A signal following a character or block that prepares the receiving device to receive the next character or block.
synchronous 1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal.
2. A system whose operation is synchronized by a clock signal.
tri-state A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any
value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit,
allowing another output to drive the same net.
UART A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits.
user modules Pre-built, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower
level analog and digital PSoC blocks. User modules also provide high level API (Application Programming
Interface) for the peripheral function.
user space The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal
program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during
the initialization phase of the program.
VDD A name for a power net meaning “voltage drain.” The most positive power supply signal. Usually 5 V or 3.3 V.
VSS A name for a power net meaning “voltage source.” The most negative power supply signal.
watchdog timer A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time.
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