Features: - Äìéqìåéë Olj NCK

Features _äìÉqìåÉë∆=olj=nck
■ Cost-effective single-chip solution for stereo _äìÉqìåÉë=olj=píÉêÉç=eÉ~ÇëÉí=pçäìíáçå

headset and wireless speaker applications
■ A2DP1.2 and AVRCP1.0 profiles enabled with
Single-chip Bluetooth® v2.1 + EDR
SBC encoder for streaming audio over Bluetooth System
and for remote control functionality
■ MP31 decoder for improved audio quality and Advance Information
reduced power consumption
■ Configurable A2DP 5-band EQ BC57F687A05
■ High-quality audio 95dB SNR on DAC playback
■ 64MIPS Kalimba DSP co-processor Issue 1
■ FastStream, CSR’s low-latency codec for video
and gaming applications
■ HFP 1.5 (includes 3-way calling) and HSP 1.0
support
■ cVc support for echo and noise reduction
_äìÉqìåÉë=olj=nck Data Sheet

■ Low-power consumption: over 10 hours of audio
playback from a 180mAh battery
■ Fully qualified Bluetooth v2.1 + EDR specification
system with support for secure simple pairing
■ Best-in-class Bluetooth radio with 7dBm transmit
power and -90dBm receive sensitivity
■ Integrated linear regulator with 1.5V output from
1.8V to 2.7V input
■ Integrated switch-mode regulator
■ Integrated 150mA lithium battery charger
■ 68-lead 8 x 8 x 0.9mm, 0.4mm pitch QFN package
■ Green (RoHS and no antimony or halogenated
flame retardants)
■ BlueTunes ROM Stereo Headset Solution
Development Kit (includes example design)
available. Order code BTN-003-1A
General Description Applications

■ Stereo headset solution with support for echo and
Based on _äìÉ`çêÉ∆RJjìäíáãÉÇá~=olj=nck, the
noise reduction
_äìÉqìåÉë=olj=nck integrates a Bluetooth radio,
■ Wireless stereo speakers
baseband, DSP, high-quality audio codec, SMPS,
LDOs and a battery charger for minimal BOM, BlueTunes ROM QFN includes, as standard, the cVc
component count and PCB area. single-microphone algorithm for echo and noise
suppression. cVc 1-mic is for headset applications
BlueTunes ROM QFN uses advanced DSP features
only, it provides full-duplex echo-cancellation and a
for the latest stereo enhancements and to improve
10dB stationary noise suppressor.
audio quality; including SBC and MP3 decoder,
support for FastStream (low-latency codec) and 5- The cVc dual-microphone algorithm provides >30dB of
band EQ. noise suppression in both dynamic and stationary
noise conditions such as babble, road, music and
XTAL RAM I2 C EEPROM competing voices. In addition the cVc dual-
microphone solution integrates an acoustic echo-
UART
canceller, further enhancing the far-end user-
ROM experience. A software license enables this dual-
microphone algorithm.
I/O PIO
RF IN
RF OUT
2.4
GHz
BlueTunes ROM QFN includes secure simple pairing,
Radio MCU
Audio In/Out
which greatly simplifies the pairing process, making it
even easier to use a Bluetooth headset.
Kalimba
DSP
SPI BlueTunes ROM QFN is available in a 8 x 8 x 0.9mm
QFN package.
1 MP3 decode functionality requires an appropriate license from Thomson, see Section 17.1
Advance Information
CS-122312-DSP1 This material is subject to CSR's non-disclosure agreement Page 1 of 77
© Cambridge Silicon Radio Limited 2008
Document History
Document History
Revision Date Change Reason
1 23 OCT 08 Original publication of this document
If you have any comments about this document, email [email protected] giving the
number, title and section with your feedback.
Advance Information
Status Information
Status Information
The status of this Data Sheet is Advance Information.
CSR Product Data Sheets progress according to the following format:
Advance Information
Information for designers concerning CSR product in development. All values specified are the target values of the
design. Minimum and maximum values specified are only given as guidance to the final specification limits and must
not be considered as the final values.
All detailed specifications including pinouts and electrical specifications may be changed by CSR without notice.
Pre-production Information
Pinout and mechanical dimension specifications finalised. All values specified are the target values of the design.
Minimum and maximum values specified are only given as guidance to the final specification limits and must not be
considered as the final values.

All electrical specifications may be changed by CSR without notice.
Production Information
Final Data Sheet including the guaranteed minimum and maximum limits for the electrical specifications.
Production Data Sheets supersede all previous document versions.
ESD Precautions
BlueTunes ROM QFN is classified as a JESD22-A114 class 2 product. Apply ESD static handling precautions during
manufacturing.
Life Support Policy and Use in Safety-critical Applications
CSR's products are not authorised for use in life-support or safety-critical applications. Use in such applications is
done at the sole discretion of the customer. CSR will not warrant the use of its devices in such applications.
CSR Green Semiconductor Products and RoHS Compliance
BlueTunes ROM QFN devices meet the requirements of Directive 2002/95/EC of the European Parliament and of
the Council on the Restriction of Hazardous Substance (RoHS).
BlueTunes ROM QFN devices are also free from halogenated or antimony trioxide-based flame retardants and other
hazardous chemicals. For more information, see CSR's Environmental Compliance Statement for CSR Green
Semiconductor Products.
Trademarks, Patents and Licences
Unless otherwise stated, words and logos marked with ™ or ® are trademarks registered or owned by CSR plc or its
affiliates. Bluetooth® and the Bluetooth logos are trademarks owned by Bluetooth SIG, Inc. and licensed to CSR.
Other products, services and names used in this document may have been trademarked by their respective owners.
The publication of this information does not imply that any license is granted under any patent or other rights owned
by CSR plc.
CSR reserves the right to make technical changes to its products as part of its development programme.
While every care has been taken to ensure the accuracy of the contents of this document, CSR cannot accept
responsibility for any errors.
CSR’s products are not authorised for use in life-support or safety-critical applications.
Refer to www.csrsupport.com for compliance and conformance to standards information.
Advance Information
Contents
Contents
1 Device Details ................................................................................................................................................. 8
2 Functional Block Diagram ............................................................................................................................... 9
3 Package Information ..................................................................................................................................... 10
3.1 Pinout Diagram .................................................................................................................................... 10
3.2 Device Terminal Functions .................................................................................................................. 11
3.3 Package Dimensions ........................................................................................................................... 15
3.4 PCB Design and Assembly Considerations ......................................................................................... 16
3.5 Typical Solder Reflow Profile ............................................................................................................... 16
4 Bluetooth Modem .......................................................................................................................................... 17
4.1 RF Ports ............................................................................................................................................... 17
4.1.1 RF_N and RF_P ..................................................................................................................... 17
4.2 RF Receiver ......................................................................................................................................... 17

4.2.1 Low Noise Amplifier ............................................................................................................... 17
4.2.2 RSSI Analogue to Digital Converter ....................................................................................... 17
4.3 RF Transmitter ..................................................................................................................................... 18
4.3.1 IQ Modulator .......................................................................................................................... 18
4.3.2 Power Amplifier ...................................................................................................................... 18
4.4 Bluetooth Radio Synthesiser ............................................................................................................... 18
4.5 Baseband ............................................................................................................................................. 18
4.5.1 Burst Mode Controller ............................................................................................................ 18
4.5.2 Physical Layer Hardware Engine ........................................................................................... 18
4.6 Basic Rate Modem .............................................................................................................................. 18
4.7 Enhanced Data Rate Modem .............................................................................................................. 18
4.7.1 Enhanced Data Rate π/4 DQPSK .......................................................................................... 19
4.7.2 Enhanced Data Rate 8DPSK ................................................................................................. 20
5 Clock Generation .......................................................................................................................................... 22
5.1 Clock Architecture ................................................................................................................................ 22
5.2 Input Frequencies and PS Key Settings .............................................................................................. 22
5.3 Crystal Oscillator (XTAL_IN, XTAL_OUT) ........................................................................................... 22
5.3.1 Load Capacitance .................................................................................................................. 23
5.3.2 Frequency Trim ...................................................................................................................... 23
5.3.3 Transconductance Driver Model ............................................................................................ 24
5.3.4 Negative Resistance Model ................................................................................................... 24
5.3.5 Crystal PS Key Settings ......................................................................................................... 25
5.4 External Reference Clock .................................................................................................................... 25
5.4.1 Input (XTAL_IN) ..................................................................................................................... 25
5.4.2 XTAL_IN Impedance in External Mode .................................................................................. 25
5.4.3 Clock Start-up Delay .............................................................................................................. 25
5.4.4 Clock Timing Accuracy ........................................................................................................... 26
6 Bluetooth Stack Microcontroller .................................................................................................................... 27
6.1 Programmable I/O Parallel Ports, PIO and AIO ................................................................................... 27
7 Kalimba DSP ................................................................................................................................................ 28
8 Memory Interface and Management ............................................................................................................. 29
8.1 Memory Management Unit .................................................................................................................. 29
8.2 System RAM ........................................................................................................................................ 29
8.3 Kalimba DSP RAM .............................................................................................................................. 29
8.4 Internal ROM ....................................................................................................................................... 29
9 Serial Interfaces ............................................................................................................................................ 30
9.1 UART Interface .................................................................................................................................... 30
9.1.1 UART Configuration While Reset is Active ............................................................................ 31
Advance Information
Contents
9.2 Serial Peripheral Interface ................................................................................................................... 31

9.2.1 Instruction Cycle ..................................................................................................................... 32
9.2.2 Writing to the Device .............................................................................................................. 32
9.2.3 Reading from the Device ........................................................................................................ 32
9.2.4 Multi-slave Operation ............................................................................................................. 33
9.3 I2C Interface ......................................................................................................................................... 33
10 Audio Interface .............................................................................................................................................. 34
10.1 Audio Input and Output ........................................................................................................................ 34
10.2 Audio Codec Interface ......................................................................................................................... 35
10.2.1 Audio Codec Block Diagram .................................................................................................. 35
10.2.2 ADC ........................................................................................................................................ 35
10.2.3 ADC Sample Rate .................................................................................................................. 35
10.2.4 ADC Digital Gain .................................................................................................................... 35
10.2.5 ADC Analogue Gain ............................................................................................................... 36
10.2.6 DAC ........................................................................................................................................ 37

10.2.7 DAC Sample Rate Selection .................................................................................................. 37
10.2.8 DAC Digital Gain .................................................................................................................... 37
10.2.9 DAC Analogue Gain ............................................................................................................... 39
10.2.10 Microphone Input ................................................................................................................... 40
10.2.11 Line Input ............................................................................................................................... 42
10.2.12 Output Stage .......................................................................................................................... 43
10.2.13 Mono Operation ..................................................................................................................... 43
10.2.14 Side Tone ............................................................................................................................... 43
10.2.15 Integrated Digital Filter ........................................................................................................... 44
10.3 AuriStream Codec ............................................................................................................................... 45
11 Power Control and Regulation ...................................................................................................................... 46
11.1 Power Sequencing ............................................................................................................................... 46
11.2 External Voltage Source ...................................................................................................................... 46
11.3 Switch-mode Regulator ....................................................................................................................... 47
11.4 Low-voltage Linear Regulator .............................................................................................................. 47
11.5 Low-voltage Audio Linear Regulator .................................................................................................... 47
11.6 Voltage Regulator Enable Pins ............................................................................................................ 48
11.7 Battery Charger ................................................................................................................................... 48
11.8 LED Drivers ......................................................................................................................................... 49
11.9 Reset, RST# ........................................................................................................................................ 50
11.9.1 Digital Pin States on Reset .................................................................................................... 50
11.9.2 Status after Reset .................................................................................................................. 50
12 Example Application Schematic ................................................................................................................... 51
13 Electrical Characteristics .............................................................................................................................. 52
13.1 Absolute Maximum Ratings ................................................................................................................. 52
13.2 Recommended Operating Conditions .................................................................................................. 52
13.3 Input/Output Terminal Characteristics ................................................................................................. 53
13.3.1 Low-voltage Linear Regulator ................................................................................................ 53
13.3.2 Low-voltage Linear Audio Regulator ...................................................................................... 54
13.3.3 Switch-mode Regulator .......................................................................................................... 55
13.3.4 Battery Charger ...................................................................................................................... 56
13.3.5 Reset ...................................................................................................................................... 57
13.3.6 Regulator Enable ................................................................................................................... 57
13.3.7 Digital Terminals .................................................................................................................... 58
13.3.8 Mono Codec: Analogue to Digital Converter .......................................................................... 59
13.3.9 Stereo Codec: Digital to Analogue Converter ........................................................................ 60
13.3.10 Clocks .................................................................................................................................... 60
13.3.11 LED Driver Pads .................................................................................................................... 61
Advance Information
Contents
13.3.12 Auxiliary ADC ......................................................................................................................... 62

14 HCI Power Consumption .............................................................................................................................. 63
15 CSR Green Semiconductor Products and RoHS Compliance ..................................................................... 66
15.1 RoHS Statement .................................................................................................................................. 66
15.1.1 List of Restricted Materials ..................................................................................................... 66
16 BlueTunes ROM QFN Software Stack ......................................................................................................... 67
16.1 Stand-alone BlueTunes ROM QFN and Kalimba DSP Applications ................................................... 67
16.2 HCI Stack ............................................................................................................................................. 68
16.2.1 Key Features of the HCI Stack: Standard Bluetooth Functionality ......................................... 68
16.2.2 Key Features of the HCI Stack: Extra Functionality ............................................................... 70
16.3 BlueTunes ROM Stereo Headset Solution Development Kit, BTN-003-1A ......................................... 70
16.4 BlueTunes ROM QFN Stereo Headset ROM Software, BC57F687A05 ............................................. 70
17 Ordering Information ..................................................................................................................................... 72
17.1 MP3 Licence Statement ....................................................................................................................... 72
17.2 BlueTunes ROM Stereo Headset Solution Development Kit Ordering Information ............................. 72

18 Tape and Reel Information ........................................................................................................................... 73
18.1 Tape Orientation .................................................................................................................................. 73
18.2 Tape Dimensions ................................................................................................................................. 73
18.3 Reel Information .................................................................................................................................. 74
18.4 Moisture Sensitivity Level .................................................................................................................... 74
19 Document References .................................................................................................................................. 75
Terms and Definitions ............................................................................................................................................ 76
List of Figures
Figure 2.1 BlueTunes ROM QFN Functional Block Diagram ............................................................................. 9
Figure 3.1 BlueTunes ROM QFN Device Pinout .............................................................................................. 10
Figure 3.2 BlueTunes ROM QFN 68 Lead QFN Package Dimensions ............................................................ 15
Figure 4.1 Simplified Circuit RF_N and RF_P .................................................................................................. 17
Figure 4.2 Basic Rate and Enhanced Data Rate Packet Structure .................................................................. 19
Figure 4.3 π/4 DQPSK Constellation Pattern ................................................................................................... 20
Figure 4.4 8DPSK Constellation Pattern .......................................................................................................... 21
Figure 5.1 Clock Architecture ........................................................................................................................... 22
Figure 5.2 Crystal Driver Circuit ....................................................................................................................... 22
Figure 5.3 Crystal Equivalent Circuit ................................................................................................................ 22
Figure 5.4 TCXO Clock Accuracy .................................................................................................................... 26
Figure 7.1 Kalimba DSP Interface to Internal Functions .................................................................................. 28
Figure 9.1 Universal Asynchronous Receiver .................................................................................................. 30
Figure 9.2 Break Signal .................................................................................................................................... 30
Figure 9.3 SPI Write Operation ........................................................................................................................ 32
Figure 9.4 SPI Read Operation ........................................................................................................................ 33
Figure 9.5 Example EEPROM Connection ...................................................................................................... 33
Figure 10.1 BlueTunes ROM QFN Audio Interface ............................................................................................ 34
Figure 10.2 Codec Audio Input and Output Stages ............................................................................................ 35
Figure 10.3 ADC Analogue Amplifier Block Diagram ......................................................................................... 37
Figure 10.4 Microphone Biasing (Single Channel Shown) ................................................................................. 40
Figure 10.5 Differential Input (Single Channel Shown) ...................................................................................... 42
Figure 10.6 Single-Ended Input (Single Channel Shown) .................................................................................. 43
Figure 10.7 Speaker Output (Single Channel Shown) ....................................................................................... 43
Figure 11.1 Voltage Regulator Configuration ..................................................................................................... 46
Figure 11.2 LED Equivalent Circuit .................................................................................................................... 49
Figure 12.1 BlueTunes ROM QFN Example Application Schematic .................................................................. 51
Figure 16.1 Stand-alone Application: BlueTunes ROM Stereo Headset Solution .............................................. 67
Advance Information
Contents
Figure 16.2 BlueCore HCI Stack ........................................................................................................................ 68

Figure 18.1 BlueTunes ROM QFN Tape Orientation ......................................................................................... 73
Figure 18.2 Reel Dimensions ............................................................................................................................. 74
List of Tables
Table 4.1 Data Rate Schemes ......................................................................................................................... 19
Table 4.2 2-Bits Determine Phase Shift Between Consecutive Symbols ......................................................... 20
Table 4.3 3-Bits Determine Phase Shift Between Consecutive Symbols ......................................................... 21
Table 5.1 Crystal Specification ......................................................................................................................... 23
Table 5.2 External Clock Specifications ........................................................................................................... 25
Table 9.1 Possible UART Settings ................................................................................................................... 30
Table 9.2 Standard Baud Rates ....................................................................................................................... 31
Table 9.3 Instruction Cycle for an SPI Transaction .......................................................................................... 32
Table 10.1 ADC Digital Gain Rate Selection ...................................................................................................... 36

Table 10.2 DAC Digital Gain Rate Selection ...................................................................................................... 37
Table 10.3 DAC Analogue Gain Rate Selection ................................................................................................. 39
Table 10.4 Voltage Output Steps ....................................................................................................................... 41
Table 10.5 Current Output Steps ....................................................................................................................... 42
Table 11.1 BlueTunes ROM QFN Voltage Regulator Enable Pins .................................................................... 48
Table 11.2 BlueTunes ROM QFN Digital Pin States on Reset .......................................................................... 50
List of Equations
Equation 5.1 Load Capacitance ........................................................................................................................... 23
Equation 5.2 Trim Capacitance ............................................................................................................................ 23
Equation 5.3 Frequency Trim ............................................................................................................................... 23
Equation 5.4 Pullability ......................................................................................................................................... 24
Equation 5.5 Transconductance Required for Oscillation .................................................................................... 24
Equation 5.6 Equivalent Negative Resistance ..................................................................................................... 24
Equation 9.1 Baud Rate ....................................................................................................................................... 31
Equation 10.1 IIR Filter Transfer Function, H(z) ..................................................................................................... 45
Equation 10.2 IIR Filter plus DC Blocking Transfer Function, HDC(z) .................................................................... 45
Equation 11.1 LED Current .................................................................................................................................... 49
Equation 11.2 LED PAD Voltage ............................................................................................................................ 49
Advance Information
Device Details
1 Device Details
Radio Kalimba DSP

■ Common TX/RX terminal simplifies external ■ Very low-power Kalimba DSP co-processor,
matching; eliminates external antenna switch 64MIPS, 24-bit fixed point core
■ BIST minimises production test time ■ Support for SBC and MP3(1) codec for improved
■ Bluetooth v2.1 + EDR specification compliant audio quality
■ Single-cycle MAC; 24 x 24-bit multiply and 56-bit
Transmitter accumulator
■ 7dBm RF transmit power with level control from on- ■ 32-bit instruction word, dual 24-bit data memory
chip 6-bit DAC over a dynamic range >30dB ■ 6K x 32-bit program RAM, 8K x 24-bit + 8K x 24-bit
■ Class 2 and Class 3 support without the need for an data RAM
external power amplifier or TX/RX switch ■ 64 x 32-bit program memory cache when executing
from ROM

Receiver
Audio Codec
■ Receiver sensitivity of -90dBm
■ Integrated channel filters ■ 16-bit internal codec
■ Digital demodulator for improved sensitivity and co- ■ DAC for stereo audio
channel rejection ■ ADC dual channel mono voice band audio
■ Real-time digitised RSSI available on HCI interface ■ Integrated amplifiers for driving 16Ω speakers; no
■ Fast AGC for enhanced dynamic range need for external components
■ Support for single-ended speaker termination and
Synthesiser line output
■ Integrated low-noise microphone bias
■ Fully integrated synthesiser requires no external
VCO, varactor diode, resonator or loop filter Baseband and Software
■ Compatible with crystals 16MHz to 26MHz or an
external clock 12MHz to 52MHz ■ Internal ROM
■ 48KB of internal RAM, allows full-speed data
Physical Interfaces transfer, mixed voice/data and full piconet support
■ Synchronous serial interface for system debugging
■ Logic for FEC, HEC, access code correlation, CRC,
■ demodulation, encryption bit stream generation,
I2C compatible interface to external EEPROM
whitening and transmit pulse shaping
containing device configuration data (PS Keys)
■ Transcoders for A-law, μ-law and linear voice from
■ UART interface
host and A-law, μ-law and CVSD voice over air
■ 2 LED drivers with faders ■ FastStream, CSR low latency codec significantly
Auxiliary Features reduces the latency of the audio link, from source to
sink, avoiding lip-sync issues when simultaneously
■ Crystal oscillator with built-in digital trimming listening to audio and watching video images
■ Power management includes digital shutdown and ■ Configurable stereo headset ROM software to set-
wake-up commands with an integrated low-power up headset features and user interface
oscillator for ultra-low power Park/Sniff/Hold mode ■ HFP 1.5 (including 3-way calling) and HSP 1.0
■ Clock request output to control external clock support
■ On-chip regulators: 1.5V output from 1.8V to 2.7V ■ Bluetooth v2.1 + EDR specification Secure Simple
input Pairing support
■ On-chip high-efficiency switched-mode regulator: ■ DSP based single-microphone cVc echo and noise
1.8V output from 2.7V to 4.4V input reduction is included in the BlueTunes ROM QFN
■ Power-on-reset cell detects low-supply voltage ■ A new high-performance dual-microphone noise
■ 10-bit ADC available to applications reduction is available in BlueTunes ROM QFN as a
■ On-chip 150mA charger for lithium ion/polymer licensed option for an extra 20dB of noise
batteries suppression, order code BCSW‑CVC‑HS‑2M‑R3
Package Option
■ QFN 68-lead, 8 x 8 x 0.9mm, 0.4mm pitch
(1) MP3 decode functionality requires an appropriate license from Thomson, see Section 17.1
Advance Information
Functional Block Diagram
2 Functional Block Diagram

I2 C bus interface can only connect
to a serial EEPROM
I2C Interface
PIO[8]
SDA
PIO[7]
SCL PIO[6]
Bluetooth Modem Memory Management Unit
VDD_UART
Baseband
Serial Interfaces
UART_RTS
UART_CTS
UART
Basic Rate System RAM
RF_N Bluetooth v2.1 Modem UART_RX
RF_P Radio UART_TX

Enhanced
Rate Modem Microcontroller DSP
SPI_MOSI
VDD_CORE
Interface
Interrupt Interrupt SPI_MISO
VDD_RADIO
SPI
Radio Control Controller Controller
SPI_CS#
VDD_LO
SPI_CLK
LO_REF Timers MCU Timers Kalimba DSP
XTAL_OUT Clock
Generation SPKR_A_N
XTAL_IN
SPKR_A_P
SPKR_B_N
Data Memory Data Memory Program SPKR_B_P
Audio Codec
Interface
DM1 DM2 Memory PM MIC_BIAS
Audio
MIC_A_N
MIC_A_P
MIC_B_N
Power Control and Regulation MIC_B_P
VDD_CHG IN AU_REF_DCPL
Battery Charger
OUT
BAT_P
VDD_SMP_CORE SENSE
Programmable I/O Internal Memory Interface
Switch Mode
LX Regulator
VSS EN
LED Driver AIO GPIO ROM
VREGENABLE_H
VREGENABLE_L VDD_PADS
VREGIN_L IN EN
Low Voltage
Linear Regulator
VDD_ANA OUT SENSE
VREGIN_AUDIO IN EN
Audio Low
Voltage Regulator
VDD_AUDIO OUT SENSE RST#
TEST_EN
LED[0]
LED[1]
AIO[0]
AIO[1]
VSS_PIO
VDD_PIO
PIO[5:0]
PIO[14:11, 9]
VDD_MEM
Figure 2.1: BlueTunes ROM QFN Functional Block Diagram
Advance Information
Package Information
3 Package Information
3.1 Pinout Diagram
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
1 51
2 50
3 49
4 48
47

5
6 46
7 45
8 44
9 43
10 42
11 41
12 40
13 39
14 38
15 37
16 36
17 35
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Figure 3.1: BlueTunes ROM QFN Device Pinout
Advance Information
Package Information
3.2 Device Terminal Functions

Bluetooth Radio Lead Pad Type Supply Domain Description
Transmitter output/switched
RF_N 65 RF
receiver
VDD_RADIO
RF_P 64 RF Complement of RF_N
Synthesiser and
Lead Pad Type Supply Domain Description
Oscillator
XTAL_IN 3 For crystal or external clock input
XTAL_OUT 4 Drive for crystal

Analogue VDD_ANA

Reference voltage to decouple
LO_REF 5
the synthesiser
SPI Interface Lead Pad Type Supply Domain Description
Input, with weak internal pull-

SPI_MOSI 28 SPI data input
down
Bidirectional with weak

SPI_CS# 30 Chip select for SPI, active low
internal pull-down
VDD_PADS
SPI_CLK 29 SPI clock
internal pull-down

SPI_MISO 31 SPI data output
internal pull-down
UART Interface Lead Pad Type Supply Domain Description
Output, tri-state, with weak

UART_TX 9 UART data output, active high
internal pull-down

UART_RX 10 UART data input, active high
internal pull-down
VDD_UART
Bidirectional CMOS output,
UART_RTS 12 tri-state, with weak internal UART request to send active low
pull-up
CMOS input with weak

UART_CTS 11 UART clear to send active low
internal pull-down
Advance Information
Package Information
PIO Port Lead Pad Type Supply Domain Description
PIO[14] 20
PIO[13] 19
PIO[12] 18
PIO[11] 15
PIO[9] 14 Bidirectional with

programmable strength VDD_PADS Programmable input/output line
PIO[8] 21 internal pull-up/down
PIO[7] 22
PIO[6] 23

PIO[5] 24
PIO[4] 25
PIO[3] 58
PIO[2] 59 Bidirectional with

programmable strength VDD_PIO Programmable input/output line
PIO[1] 60 internal pull-up/down
PIO[0] 61
AIO[1] 6
Bidirectional VDD_ANA Programmable input/output line
AIO[0] 7
Advance Information
Package Information
Audio Lead Pad Type Supply Domain Description
Speaker output, negative,

SPKR_A_N 56 Analogue VDD_AUDIO
channel A
Speaker output, positive,

SPKR_A_P 57 Analogue VDD_AUDIO
channel A
Speaker output, negative,

SPKR_B_N 53 Analogue VDD_AUDIO
channel B
Speaker output, positive,

SPKR_B_P 54 Analogue VDD_AUDIO
channel B
Microphone input, negative,

MIC_A_N 52 Analogue VDD_AUDIO
channel A

Microphone input, positive,
MIC_A_P 51 Analogue VDD_AUDIO
channel A
Microphone input, negative,

MIC_B_N 50 Analogue VDD_AUDIO
channel B
Microphone input, positive,

MIC_B_P 48 Analogue VDD_AUDIO
channel B
VDD_AUDIO,
MIC_BIAS 45 Analogue Microphone bias
BAT_P
Decoupling of audio reference,

AU_REF_DCPL 55 Analogue VDD_AUDIO
for high-quality audio
LED Drivers Lead Pad Type Supply Domain Description
LED[1] 33 LED driver

Open drain output Open drain
LED[0] 32 LED driver
Test and Debug Lead Pad Type Supply Domain Description
Reset if low. Input debounced so

Input with weak internal pull-
RST# 26 must be low for >5ms to cause a
up
reset
VDD_PADS
Input with strong internal pull- For test purposes only. Leave
TEST_EN 27
down unconnected
Advance Information
Package Information
Power Supplies
Lead Description
Control
Low-voltage linear regulator and low-voltage audio

VREGENABLE_L 68
linear regulator enable, active high
VREGIN_L 1 Input to internal low-voltage regulator
VREGENABLE_H 35 Switch-mode regulator enable, active high
VREGIN_AUDIO 46 Input to internal audio low-voltage linear regulator
VDD_AUDIO 47 Positive supply for audio
LX 37 Switch-mode regulator output
Positive supply output for analogue circuitry and

VDD_ANA 2 1.5V regulated output, from internal low-voltage
regulator
VDD_PIO 62 Positive supply for digital input/output ports PIO[3:0]
Positive supply for all other digital input/output ports

VDD_PADS 16
including PIO[14:11,9:4]
VDD_CORE 17, 34 Positive supply for internal digital circuitry
VDD_RADIO 63, 66 Positive supply for RF circuitry
VDD_UART 13 Positive supply for UART ports
VDD_LO 67 Positive supply for local oscillator circuitry
Lithium ion/polymer battery positive terminal. Battery

BAT_P 38
charger output and input to switch-mode regulator
VDD_CHG 39 Lithium ion/polymer battery charger input
VDD_SMP_CORE 36 Positive supply for switch-mode control circuitry
VSS Exposed Pad Ground connections
Unconnected Leads (N/Cs) Description
8, 40, 41, 42, 43, 44, 49 Leave unconnected
Advance Information
Package Information
3.3 Package Dimensions

Top View Bottom View
D D1 PIN 1 I.D.
X 68
Y
51 1
E E1
e

35 17
34 18
Exposed Die
F Attach Pad
Z
(A3)
Seating Plane
Description 68-lead Quad Flat No-lead Package
Size 8 x 8 x 0.9mm
Pitch 0.4mm
Dimension Minimum Typical Maximum Notes
A 0.80 0.85 0.90 1 Top-side polarity mark. The dimensions of

A1 0.00 0.035 0.05 the square polarity mark are 0.75 x
0.75mm.
A2 - 0.65 0.67
A3 - 0.203 -
Coplanarity applies to leads, corner leads
b 0.15 0.20 0.25 and die attach pad.
D 7.90 8.00 8.05
E 7.90 8.00 8.05
e - 0.40 -
D1 6.10 6.20 6.30
E1 6.10 6.20 6.30
F 0.35 0.40 0.45
X - 1.00 -
Y - 0.85 -
JEDEC MO-220
Unit mm
Figure 3.2: BlueTunes ROM QFN 68 Lead QFN Package Dimensions
Advance Information
Package Information
3.4 PCB Design and Assembly Considerations

This section lists recommendations to achieve maximum board-level reliability of the 8 x 8 x 0.9mm QFN 68-lead
package:
■ NSMD lands (lands smaller than the solder mask aperture) are preferred, because of the greater accuracy
of the metal definition process compared to the solder mask process. With solder mask defined pads, the
overlap of the solder mask on the land creates a step in the solder at the land interface, which can cause
stress concentration and act as a point for crack initiation.
■ PCB land width should be 0.2mm and PCB land length should be 0.55mm to achieve maximum reliability.
■ Solder paste must be used during the assembly process.
3.5 Typical Solder Reflow Profile

See Typical Solder Reflow Profile for Lead-free Devices for information.
Advance Information
Bluetooth Modem
4 Bluetooth Modem
4.1 RF Ports
4.1.1 RF_N and RF_P
RF_N and RF_P form a complementary balanced pair and are available for both transmit and receive. On transmit
their outputs are combined using an external balun into the single-ended output required for the antenna. Similarly,
on receive their input signals are combined internally.
Both terminals present similar complex impedances that may require matching networks between them and the
balun. Viewed from the chip, the outputs can each be modelled as an ideal current source in parallel with a lossy
capacitor. An equivalent series inductance can represent the package parasitics.
BlueCore

PA RF_N
+ RF
Switch
RF_P
RF
Switch
+
LNA
_
Figure 4.1: Simplified Circuit RF_N and RF_P

The DC level must be set at VDD_RADIO.
4.2 RF Receiver
The receiver features a near-zero IF architecture that allows the channel filters to be integrated onto the die. Sufficient
out-of-band blocking specification at the LNA input allows the receiver to be used in close proximity to GSM and W-
CDMA cellular phone transmitters without being desensitised. The use of a digital FSK discriminator means that no
discriminator tank is needed and its excellent performance in the presence of noise allows BlueTunes ROM QFN to
exceed the Bluetooth requirements for co-channel and adjacent channel rejection.
For EDR, the demodulator contains an ADC which digitises the IF received signal. This information is then passed
to the EDR modem.
4.2.1 Low Noise Amplifier

The LNA operates in differential mode and takes its input from the shared RF port.
4.2.2 RSSI Analogue to Digital Converter

The ADC implements fast AGC. The ADC samples the RSSI voltage on a slot-by-slot basis. The front-end LNA gain
is changed according to the measured RSSI value, keeping the first mixer input signal within a limited range. This
improves the dynamic range of the receiver, improving performance in interference limited environments.
Advance Information
Bluetooth Modem
4.3 RF Transmitter
4.3.1 IQ Modulator
The transmitter features a direct IQ modulator to minimise the frequency drift during a transmit timeslot, which results
in a controlled modulation index. Digital baseband transmit circuitry provides the required spectral shaping.
4.3.2 Power Amplifier

The internal PA has a maximum output power that allows BlueTunes ROM QFN to be used in Class 2 and Class 3
radios without an external RF PA.
4.4 Bluetooth Radio Synthesiser

The Bluetooth radio synthesiser is fully integrated onto the die with no requirement for an external VCO screening
can, varactor tuning diodes, LC resonators or loop filter. The synthesiser is guaranteed to lock in sufficient time
across the guaranteed temperature range to meet the Bluetooth v2.1 + EDR specification.
4.5 Baseband

4.5.1 Burst Mode Controller
During transmission the BMC constructs a packet from header information previously loaded into memory-mapped
registers by the software and payload data/voice taken from the appropriate ring buffer in the RAM. During reception,
the BMC stores the packet header in memory-mapped registers and the payload data in the appropriate ring buffer
in RAM. This architecture minimises the intervention required by the processor during transmission and reception.
4.5.2 Physical Layer Hardware Engine

Dedicated logic performs the following:
■ Forward error correction
■ Header error control
■ Cyclic redundancy check
■ Encryption
■ Data whitening
■ Access code correlation
■ Audio transcoding
Firmware performs the following voice data translations and operations:
■ A-law/µ-law/linear voice data (from host)
■ A-law/µ-law/CVSD (over the air)
■ Voice interpolation for lost packets
■ Rate mismatches
The hardware supports all optional and mandatory features of Bluetooth v2.1 + EDR specification including AFH
and eSCO.
4.6 Basic Rate Modem

The basic rate modem satisfies the basic data rate requirements of the Bluetooth v2.1 + EDR specification. The
basic rate was the standard data rate available on the Bluetooth v1.2 specification and below, it is based on GFSK
modulation scheme.
The inclusion of the basic rate modem allows BlueTunes ROM QFN compatibility with earlier Bluetooth products.
The basic rate modem uses the RF ports, receiver, transmitter and synthesiser, alongside the baseband components
described in Section 4.5.
4.7 Enhanced Data Rate Modem

The EDR modem satisfies the requirements of the Bluetooth v2.1 + EDR specification. EDR has been introduced
to provide 2x and 3x data rates with minimal disruption to higher layers of the Bluetooth stack. BlueTunes ROM QFN
supports both the basic and enhanced data rates and is compliant with the Bluetooth v2.1 + EDR specification.
Advance Information
Bluetooth Modem
At the baseband level, EDR utilises both the same 1.6kHz slot rate and the 1MHz symbol rate as defined for the
basic data rate. EDR differs in that each symbol in the payload portion of a packet represents 2 or 3-bits. This is
achieved using two new distinct modulation schemes. Table 4.1 and Figure 4.2 summarise these. Link Establishment
and management are unchanged and still use GFSK for both the header and payload portions of these packets.
The enhanced data rate modems uses the RF Ports, Receiver, Transmitter and Synthesiser, with the baseband
components described in Section 4.5.
Data Rate Scheme Bits Per Symbol Modulation
Basic Data Rate 1 GFSK
EDR 2 π/4 DQPSK
EDR 3 8DPSK (optional)
Table 4.1: Data Rate Schemes

Basic Rate
Access Code Header Payload
Enhanced Data Rate

Access Code Header Guard Sync Payload Trailer
/4 DQPSK or 8DPSK
Figure 4.2: Basic Rate and Enhanced Data Rate Packet Structure
4.7.1 Enhanced Data Rate π/4 DQPSK

The 2x data rate for EDR uses a π/4-DQPSK. Each symbol represents 2-bits of information. Figure 4.3 shows the
constellation. It has two planes, each having four points. Although it seems there are eight possible phase states,
the encoding ensures that the trajectory of the modulation between symbols is restricted to the four states in the
other plane.
For a given starting point, each phase change between symbols is restricted to 3π/4, π/4, -π/4 or -3π/4 radians
(135°, 45°, -45° or -135°). For example, the arrows shown in Figure 4.3 represent trajectory to the four possible
states in the other plane. Table 4.2 shows the phase shift encoding of symbols.
There are two main advantages in using π/4 DQPSK modulation:
■ The scheme avoids the crossing of the origin (a π or -π phase shift) and therefore minimises amplitude
variations in the envelope of the transmitted signal. This in turn allows the RF power amplifiers of the
transmitter to be operated closer to their compression point without introducing spectral distortions.
Consequently, the DC to RF efficiency is maximised.
■ The differential encoding also allows for the demodulation without the knowledge of an absolute value for
the phase of the RF carrier.
Advance Information
Bluetooth Modem
01 00
11 10

Figure 4.3: π/4 DQPSK Constellation Pattern
Bit Pattern Phase Shift
00 π/4
01 3π/4
11 -3π/4
10 -π/4
Table 4.2: 2-Bits Determine Phase Shift Between Consecutive Symbols
4.7.2 Enhanced Data Rate 8DPSK

The 3x data rate modulation uses 8DPSK. Each symbol in the payload portion of the packet represents 3 baseband
bits. Although it seems the 8DPSK is similar to π/4 DQPSK, the differential phase shifts between symbols are now
permissible between any of the eight possible phase states. This reduces the separation between adjacent symbols
on the constellation to π/4 (45°) and thereby reduces the noise and interference immunity of the modulation scheme.
Nevertheless, because each symbol now represents 3 baseband bits, the actual throughput of the data is 3x when
compared with the basic rate packet.
Figure 4.4 shows the 8DPSK constellation and Table 4.3 shows the phase encoding.
Advance Information
Bluetooth Modem
011
010 001
110 000
111 100

101
Figure 4.4: 8DPSK Constellation Pattern
Bit Pattern Phase Shift
000 0
001 π/4
011 π/2
010 3π/4
110 π
111 -3π/4
101 -π/2
100 -π/4
Table 4.3: 3-Bits Determine Phase Shift Between Consecutive Symbols
Advance Information
Clock Generation
5 Clock Generation
BlueTunes ROM QFN requires a Bluetooth reference clock frequency of 12MHz to 52MHz from either an externally
connected crystal or from an external TCXO source.
All BlueTunes ROM QFN internal digital clocks are generated using a phase locked loop, which is locked to the
frequency of either the external 12MHz to 52MHz reference clock source or an internally generated watchdog clock
frequency of 1kHz.
The Bluetooth operation determines the use of the watchdog clock in low-power modes.
5.1 Clock Architecture

Bluetooth
Reference Clock
Radio

Auxiliary Digital
PLL Circuitry
Figure 5.1: Clock Architecture
5.2 Input Frequencies and PS Key Settings

BlueTunes ROM QFN is configured to operate with a chosen reference frequency. Configuration is by setting the
PS Key PSKEY_ANA_FREQ (0x01FE) for all frequencies with an integer multiple of 250kHz. The input frequency
default setting for BlueTunes ROM QFN is 26MHz depending on the software build. Full details are in the software
release note for the specific build from www.csrsupport.com.
5.3 Crystal Oscillator (XTAL_IN, XTAL_OUT)

BlueTunes ROM QFN contains a crystal driver circuit. This operates with an external crystal and capacitors to form
a Pierce oscillator. The external crystal is connected to pins XTAL_IN, XTAL_OUT.
gm
C trim C int
XTAL_OUT
XTAL_IN
Ct2 Ct1
Figure 5.2: Crystal Driver Circuit

Figure 5.3 shows an electrical equivalent circuit for a crystal. The crystal appears inductive near its resonant
frequency. It forms a resonant circuit with its load capacitors.
Cm Lm Rm
Co
Figure 5.3: Crystal Equivalent Circuit
Advance Information
Clock Generation
The resonant frequency may be trimmed with the crystal load capacitance. BlueTunes ROM QFN contains variable
internal capacitors to provide a fine trim.
Parameter Min Typ Max Unit
Frequency 16 26 26 MHz
Initial Tolerance - ±25 - ppm
Pullability - ±20 - ppm/pF
Transconductance 2.0 - - mS
Table 5.1: Crystal Specification

The BlueTunes ROM QFN driver circuit is a transconductance amplifier. A voltage at XTAL_IN generates a current
at XTAL_OUT. The value of transconductance is variable and may be set for optimum performance.

5.3.1 Load Capacitance
For resonance at the correct frequency the crystal should be loaded with its specified load capacitance, which is
defined for the crystal. This is the total capacitance across the crystal viewed from its terminals. BlueTunes ROM QFN
provides some of this load with the capacitors Ctrim and Cint. The remainder should be from the external capacitors
labelled Ct1 and Ct2. Ct1 should be three times the value of Ct2 for best noise performance. This maximises the signal
swing, hence slew rate at XTAL_IN (to which all on-chip clocks are referred).
Crystal load capacitance, Cl is calculated with Equation 5.1:
(C +C )C
t2 trim t1
Cl = Cint +
C +C +C
t2 trim t1
Equation 5.1: Load Capacitance

Note:
Ctrim = 3.4pF nominal (mid-range setting)
Cint = 1.5pF
Cint does not include the crystal internal self capacitance; it is the driver self capacitance.
5.3.2 Frequency Trim

BlueTunes ROM QFN enables frequency adjustments to be made. This feature is typically used to remove initial
tolerance frequency errors associated with the crystal. Frequency trim is achieved by adjusting the crystal load
capacitance with an on-chip trim capacitor, Ctrim. The value of Ctrim is set by a 6-bit word in the PS Key
PSKEY_ANA_FTRIM (0x1f6). Its value is calculated as follows:
Ctrim = 125fF × PSKEY_ANA_FTRIM
Equation 5.2: Trim Capacitance

The Ctrim capacitor is connected between XTAL_IN and ground. When viewed from the crystal terminals, the
combination of the tank capacitors and the trim capacitor presents a load across the terminals of the crystal which
varies in steps of typically 125fF for each least significant bit increment of PSKEY_ANA_FTRIM.
Equation 5.3 describes the frequency trim.
( )
Δ (F ) C
x t1
= pullability × 0.110 × (ppm / LSB)
F C +C +C
x t1 t2 trim
Equation 5.3: Frequency Trim
Advance Information
Clock Generation
Note:
Fx = crystal frequency
Pullability is a crystal parameter with units of ppm/pF.

Total trim range is 0 to 63.
If not specified, the pullability of a crystal may be calculated from its motional capacitance with Equation 5.4.
∂ (FX ) FX Cm
= •
∂ (CI ) 2(CI + C0 )2
Equation 5.4: Pullability

Note:
C0 = Crystal self capacitance (shunt capacitance)
Cm = Crystal motional capacitance (series branch capacitance in crystal model). See Figure 5.3.

It is a Bluetooth requirement that the frequency is always within ±20ppm. The trim range should be sufficient to
pull the crystal within ±5ppm of the exact frequency. This leaves a margin of ±15ppm for frequency drift with
ageing and temperature. A crystal with an ageing and temperature drift specification of better than ±15ppm is
required.
5.3.3 Transconductance Driver Model

The crystal and its load capacitors should be viewed as a transimpedance element, whereby a current applied to
one terminal generates a voltage at the other. The transconductance amplifier in BlueTunes ROM QFN uses the
voltage at its input, XTAL_IN, to generate a current at its output, XTAL_OUT. Therefore, the circuit will oscillate if
the transconductance, transimpedance product is greater than unity. For sufficient oscillation amplitude, the product
should be greater than three. The transconductance required for oscillation is defined by the relationship shown in
Equation 5.5.
gm > 3
(2 πF
x
)2R
m ((C0 +C
int )(Ct1 +C
t2
+C
trim ) + Ct1 (Ct2 +C
trim ))
C (C +C )
t1 t2 trim
Equation 5.5: Transconductance Required for Oscillation

BlueTunes ROM QFN guarantees a transconductance value of at least 2mA/V at maximum drive level.
Note:
More drive strength is required for higher frequency crystals, higher loss crystals (larger Rm) or higher
capacitance loading.
Optimum drive level is attained when the level at XTAL_IN is approximately 1V pk-pk. The drive level is
determined by the crystal driver transconductance.
5.3.4 Negative Resistance Model

An alternative representation of the crystal and its load capacitors is a frequency dependent resistive element. The
driver amplifier may be considered as a circuit that provides negative resistance. For oscillation, the value of the
negative resistance must be greater than that of the crystal circuit equivalent resistance. Although the
BlueTunes ROM QFN crystal driver circuit is based on a transimpedance amplifier, an equivalent negative resistance
can be calculated for it using Equation 5.6.
C (C +C )
t1 t2 trim
Rneg >
gm ( 2 π Fx )2 C0 + Cint( )((Ct1 + Ct2 + Ctrim ) + Ct1 (Ct2 + Ctrim ))2
Equation 5.6: Equivalent Negative Resistance
This formula shows the negative resistance of the BlueTunes ROM QFN driver as a function of its drive strength.
The value of the driver negative resistance may be easily measured by placing an additional resistance in series
with the crystal. The maximum value of this resistor (oscillation occurs) is the equivalent negative resistance of the
oscillator.
Advance Information
Clock Generation
5.3.5 Crystal PS Key Settings

The BlueTunes ROM QFN firmware automatically controls the drive level on the crystal circuit to achieve optimum
input swing. The PS Key PSKEY_XTAL_TARGET_AMPLITUDE (0x24b) is used by the firmware to servo the
required amplitude of crystal oscillation. Refer to the software build release note for a detailed description.
BlueTunes ROM QFN should be configured to operate with the chosen reference frequency.
5.4 External Reference Clock

5.4.1 Input (XTAL_IN)
The external reference clock is applied to the BlueTunes ROM QFN XTAL_IN input.
BlueTunes ROM QFN is configured to accept the external reference clock at XTAL_IN by connecting XTAL_OUT
to ground. The external clock can be either a digital level square wave or sinusoidal, and this may be directly coupled
to XTAL_IN without the need for additional components. A digital level reference clock gives superior noise immunity,
as the high slew rate clock edges have lower voltage to phase conversion. If peaks of the reference clock are either
below VSS or above VDD_ANA, it must be driven through a DC blocking capacitor (approximately 33pF) connected
to XTAL_IN.

The external reference clock signal should meet the specifications outlined in Table 5.2.
Min Typ Max Unit
Frequency(a) 12 26 52 MHz
Duty cycle 20:80 50:50 80:20
Edge Jitter (At Zero Crossing) - - 15 ps rms
AC coupled sinusoid 0.4 - VDD_ANA(b) V pk-pk
VIL - VSS(c) - V
Signal Level
DC coupled
digital VDD_ANA(b)
VIH - (c) - V
Table 5.2: External Clock Specifications

(a) The frequency should be an integer multiple of 250kHz except for the CDMA/3G frequencies
(b) VDD_ANA is 1.50V nominal
(c) If driven via a DC blocking capacitor max amplitude is reduced to 750mV pk-pk for non 50:50 duty cycle
5.4.2 XTAL_IN Impedance in External Mode

The impedance of XTAL_IN does not change significantly between operating modes, typically 10fF. When
transitioning from Deep Sleep to an active state a spike of up to 1pC may be measured. For this reason CSR
recommends that a buffered clock input is used.
5.4.3 Clock Start-up Delay

BlueTunes ROM QFN hardware incorporates an automatic 5ms delay after the assertion of the system clock request
signal before running firmware. This is suitable for most applications using an external clock source. However, there
may be scenarios where the clock cannot be guaranteed to either exist or be stable after this period. Under these
conditions, BlueTunes ROM QFN firmware provides a software function that extends the system clock request signal
by a period stored in PSKEY_CLOCK_STARTUP_DELAY. This value is set in milliseconds from 1-31ms. Zero is
the default entry for 5ms delay.
This PS Key allows the designer to optimise a system where clock latencies may be longer than 5ms while still
keeping the current consumption of BlueTunes ROM QFN as low as possible. BlueTunes ROM QFN consumes
about 2mA of current for the duration of PSKEY_CLOCK_STARTUP_DELAY before activating the firmware.
Advance Information
Clock Generation
5.4.4 Clock Timing Accuracy

As Figure 5.4 shows, the 250ppm timing accuracy on the external clock is required 2ms after the firmware begins
to run. This is to guarantee that the firmware can maintain timing accuracy in accordance with the Bluetooth
v2.1 + EDR specification. Radio activity may occur after 6ms after the firmware starts. Therefore, at this point the
timing accuracy of the external clock source must be within ±20ppm.
CLK_REQ
Firmware Activity PSKEY_CLOCK_STARTUP_DELAY

Firmware Activity
Clock Accuracy 1000 ppm 250 ppm 20 ppm
ms After Firmware 0 2 6
Radio Activity

Figure 5.4: TCXO Clock Accuracy
Advance Information
Bluetooth Stack Microcontroller
6 Bluetooth Stack Microcontroller

A 16-bit RISC MCU is used for low power consumption and efficient use of memory.
The MCU, interrupt controller and event timer run the Bluetooth software stack and control the Bluetooth radio and
host interfaces.
6.1 Programmable I/O Parallel Ports, PIO and AIO

BlueTunes ROM QFN contains 14 lines of programmable bidirectional I/O.
BlueTunes ROM QFN has two general-purpose analogue interface pins, AIO[1:0], used to access internal circuitry
and control signals. Auxiliary functions available on the analogue interface include a 10-bit ADC.
Note:
The PIO and AIO configuration is dependent on the BlueTunes ROM Stereo Headset Solution.
PIO[14:11,9:4] are powered from VDD_PADS and PIO[3:0] are powered from VDD_PIO. AIO[1:0] are powered
from VDD_ANA.
Advance Information
Kalimba DSP
7 Kalimba DSP
The Kalimba DSP is an open platform Kalimba DSP allowing signal processing functions to be performed on over
air data or codec data in order to enhance audio applications. The Kalimba DSP interfaces to other functional blocks
within BlueTunes ROM QFN as shown in Figure 7.1.
Kalimba DSP Core
MCU Register Interface (including Debug)
Memory
Management Unit
DSP MMU Port
Data Memory Address
Interface Generators
Registers
Instruction Decode ALU

DSP, MCU and Flash Window Control
Program Flow DEBUG
Clock Select PIO

PIO In/Out
DSP Program Control
Programmable Clock = 64MHz Internal Control Registers

IRQ to Subsystem
MMU Interface
Interrupt Controller
IRQ from Subsystem
Timer 1µs Timer Clock
DSP RAMs MCU Window
Flash Window
DM2
( 8K x 24-bit ) DSP Data Memory 2 Interface (DM2)
DM1
( 8K x 24-bit ) DSP Data Memory 1 Interface (DM1)
PM
(6K x 32-bit) DSP Program Memory Interface (PM)
Figure 7.1: Kalimba DSP Interface to Internal Functions

The key features of the DSP include:
■ 64MIPS performance, 24-bit fixed point DSP Core
■ Single cycle MAC of 24 x 24-bit multiply and 56-bit accumulate
■ 32-bit instruction word
■ Separate program memory and dual data memory, allowing an ALU operation and up to two memory
accesses in a single cycle
■ Zero overhead looping
■ Zero overhead circular buffer indexing
■ Single cycle barrel shifter with up to 56-bit input and 24-bit output
■ Multiple cycle divide (performed in the background)
■ Bit reversed addressing
■ Orthogonal instruction set
■ Low overhead interrupt
Advance Information
Memory Interface and Management
8 Memory Interface and Management

8.1 Memory Management Unit
The MMU provides a number of dynamically allocated ring buffers that hold the data that is in transit between the
host, the air or the Kalimba DSP. The dynamic allocation of memory ensures efficient use of the available RAM and
is performed by a hardware MMU to minimise the overheads on the processor during data/voice transfers.
8.2 System RAM

48KB of on-chip RAM supports the RISC MCU and is shared between the ring buffers used to hold voice/data for
each active connection and the general-purpose memory required by the Bluetooth stack.
8.3 Kalimba DSP RAM

Additional on-chip RAM is provided to support the Kalimba DSP:
■ 8K x 24-bit for data memory 1 (DM1)

■ 8K x 24-bit for data memory 2 (DM2)
■ 6K x 32-bit for program memory (PM)
Note:
The DSP can also execute directly from internal ROM, using a 64-instruction on-chip cache.
8.4 Internal ROM

Internal ROM is provided for system firmware implementation.
Advance Information
Serial Interfaces
9 Serial Interfaces
9.1 UART Interface
BlueTunes ROM QFN has a standard UART serial interface that provides a simple mechanism for communicating
using RS232 protocol.
UART_TX
UART_RX
UART_RTS
UART_CTS

Figure 9.1: Universal Asynchronous Receiver
Figure 9.1 shows the 4 signals that implement the UART function. When BlueTunes ROM QFN is connected to
another digital device, UART_RX and UART_TX transfer data between the 2 devices. The remaining 2 signals,
UART_CTS and UART_RTS, can implement RS232 hardware flow control where both are active low indicators.
UART configuration parameters, such as baud rate and packet format, are set using BlueTunes ROM QFN firmware.
Note:
To communicate with the UART at its maximum data rate using a standard PC, an accelerated serial port adapter
card is required for the PC.
Parameter Possible Values
1200 baud (≤2%Error)

Baud rate Minimum
9600 baud (≤1%Error)
Maximum 4Mbaud (≤1%Error)
Flow control RTS/CTS or None
Parity None, Odd or Even
Number of stop bits 1 or 2
Bits per byte 8
Table 9.1: Possible UART Settings

The UART interface can reset BlueTunes ROM QFN on reception of a break signal. A break is identified by a
continuous logic low (0V) on the UART_RX terminal, as shown in Figure 9.2. If tBRK is longer than the value, defined
by the PS Key PSKEY_HOSTIO_UART_RESET_TIMEOUT, (0x1a4), a reset occurs. This feature allows a host to
initialise the system to a known state. Also, BlueTunes ROM QFN can emit a break character that may be used to
wake the host.
tBRK
UART RX
Figure 9.2: Break Signal
Advance Information
Serial Interfaces
Table 9.2 shows a list of commonly used baud rates and their associated values for the PS Key
PSKEY_UART_BAUDRATE (0x1be). There is no requirement to use these standard values. Any baud rate within
the supported range can be set in the PS Key according to the formula in Equation 9.1.
PSKEY_UART_BAUDRATE
Baud Rate =
0.004096
Equation 9.1: Baud Rate
Persistent Store Value

Baud Rate Error
Hex Dec
1200 0x0005 5 1.73%
2400 0x000a 10 1.73%
4800 0x0014 20 1.73%

9600 0x0027 39 -0.82%
19200 0x004f 79 0.45%
38400 0x009d 157 -0.18%
57600 0x00ec 236 0.03%
76800 0x013b 315 0.14%
115200 0x01d8 472 0.03%
230400 0x03b0 944 0.03%
460800 0x075f 1887 -0.02%
921600 0x0ebf 3775 0.00%
1382400 0x161e 5662 -0.01%
1843200 0x1d7e 7550 0.00%
2764800 0x2c3d 11325 0.00%
3686400 0x3afb 15099 0.00%
Table 9.2: Standard Baud Rates
9.1.1 UART Configuration While Reset is Active

The UART interface for BlueTunes ROM QFN is tri-state while the chip is being held in reset. This allows the user
to daisy chain devices onto the physical UART bus. The constraint on this method is that any devices connected to
this bus must tri-state when BlueTunes ROM QFN reset is de-asserted and the firmware begins to run.
9.2 Serial Peripheral Interface

The primary function of the SPI is for debug. BlueTunes ROM QFN uses a 16-bit data and 16-bit address SPI, where
transactions may occur when the internal processor is running or is stopped. This section details the interface
considerations for connection to BlueTunes ROM QFN .
Data may be written or read one word at a time, or the auto-increment feature is available for block access.
Advance Information
Serial Interfaces
9.2.1 Instruction Cycle

The BlueTunes ROM QFN is the slave and receives commands on SPI_MOSI and outputs data on SPI_MISO. Table
9.3 shows the instruction cycle for an SPI transaction.
1 Reset the SPI interface Hold SPI_CS# high for two SPI_CLK cycles
2 Write the command word Take SPI_CS# low and clock in the 8-bit command
3 Write the address Clock in the 16-bit address word
4 Write or read data words Clock in or out 16-bit data word(s)
5 Termination Take SPI_CS# high
Table 9.3: Instruction Cycle for an SPI Transaction

With the exception of reset, SPI_CS# must be held low during the transaction. Data on SPI_MOSI is clocked into
the BlueTunes ROM QFN on the rising edge of the clock line SPI_CLK. When reading, BlueTunes ROM QFN replies
to the master on SPI_MISO with the data changing on the falling edge of the SPI_CLK. The master provides the
clock on SPI_CLK. The transaction is terminated by taking SPI_CS# high.
Sending a command word and the address of a register for every time it is to be read or written is a significant
overhead, especially when large amounts of data are to be transferred. To overcome this BlueTunes ROM QFN
offers increased data transfer efficiency via an auto increment operation. To invoke auto increment, SPI_CS# is kept
low, which auto increments the address, while providing an extra 16 clock cycles for each extra word to be written
or read.
9.2.2 Writing to the Device

To write to BlueTunes ROM QFN, the 8-bit write command (00000010) is sent first (C[7:0]) followed by a 16-bit
address (A[15:0]). The next 16-bits (D[15:0]) clocked in on SPI_MOSI are written to the location set by the address
(A). Thereafter for each subsequent 16-bits clocked in, the address (A) is incremented and the data written to
consecutive locations until the transaction terminates when SPI_CS# is taken high.
Reset End of Cycle
Write_Command Address(A) Data(A) Data(A+1) etc
SPI_CS#
SPI_CLK
SPI_MOSI C7 C6 C1 C0 A15 A14 A1 A0 D15 D14 D1 D0 D15 D14 D1 D0 D15 D14 D1 D0 Don't Care
Processor Processor
SPI_MISO MISO Not Defined During Write
State State
Figure 9.3: SPI Write Operation
9.2.3 Reading from the Device

Reading from BlueTunes ROM QFN is similar to writing to it. An 8-bit read command (00000011) is sent first (C[7:0]),
followed by the address of the location to be read (A[15:0]). BlueTunes ROM QFN then outputs on SPI_MISO a
check word during T[15:0] followed by the 16-bit contents of the addressed location during bits D[15:0].
The check word is composed of {command, address [15:8]}. The check word may be used to confirm a read operation
to a memory location. This overcomes the problems encountered with typical serial peripheral interface slaves,
whereby it is impossible to determine whether the data returned by a read operation is valid data or the result of the
slave device not responding.
If SPI_CS# is kept low, data from consecutive locations is read out on SPI_MISO for each subsequent 16 clocks,
until the transaction terminates when SPI_CS# is taken high.
Advance Information
Serial Interfaces
Reset End of Cycle
Read_Command Address(A) Check_Word Data(A) Data(A+1) etc
SPI_CS#
SPI_CLK
SPI_MOSI C7 C6 C1 C0 A15 A14 A1 A0 Don't Care
Processor Processor
SPI_MISO MISO Not Defined During Address T15 T14 T1 T0 D15 D14 D1 D0 D15 D14 D1 D0 D15 D14 D1 D0
State State
Figure 9.4: SPI Read Operation
9.2.4 Multi-slave Operation

BlueTunes ROM QFN should not be connected in a multi-slave arrangement by simple parallel connection of slave
MISO lines. When BlueTunes ROM QFN is deselected (SPI_CS# = 1), the SPI_MISO line does not float. Instead,

BlueTunes ROM QFN outputs 0 if the processor is running or 1 if it is stopped.
9.3 I2C Interface

PIO[8:6] is available to form a master I2C interface. The interface is formed using software to drive these lines.
Note:
The program memory for the BlueTunes ROM QFN is internal ROM so the I2C interface can only connect to a
serial EEPROM, an example is shown in Figure 9.5. The EEPROM stores PS Keys and configuration
information.
+1.8V
Decoupling
Capacitor
8 1
VCC A0
PIO[8] 7 WP A1 2
6 3
PIO[6] SCL A2
5 4
PIO[7] SDA GND
Serial EEPROM
(24AA32)
Figure 9.5: Example EEPROM Connection
Advance Information
Audio Interface
10 Audio Interface
The BlueTunes ROM QFN audio interface circuit consists of:
■ Stereo audio DAC and outputs
■ Dual channel mono voice band ADC with dual microphone inputs
The audio interface supports all requirements of the BlueTunes ROM Stereo Headset Solution and Figure 10.1
shows the functional blocks of the BlueTunes ROM QFN audio interface. The audio interface supports stereo
playback of audio signals at multiple sample rates with 16-bit resolution.
Audio Codec
Stereo
Audio DAC A
DAC DAC B
Driver
MMU Voice Port Voice Port
Memory Dual
Management

Channel
Unit Voice ADC A
ADC B
ADC
Input
MCU Register Interface Registers
Figure 10.1: BlueTunes ROM QFN Audio Interface
10.1 Audio Input and Output

The audio input circuitry consists of a dual audio input that can be configured to be either single-ended or fully
differential and programmed for either microphone or line input. It has an analogue and digital programmable gain
stage for optimisation of different microphones.
The audio output circuitry consists of a dual differential class A-B output stage.
Advance Information
Audio Interface
10.2 Audio Codec Interface

The main features of the interface are:
■ Stereo and mono analogue output for voice band and audio band
■ Dual mono analogue microphone input for voice band
Important Note:
To avoid any confusion regarding stereo operation this data sheet explicitly states which is the left and right
channel for audio output. With respect to software and any registers, channel 0 or channel A represents the left
channel and channel 1 or channel B represents the right channel for output.
10.2.1 Audio Codec Block Diagram

Stereo Audio and Voice
Band Audio Output LP Filter
SPKR_B_P
Output
Amplifier ΣΔ - DAC

SPKR_B_N
LP Filter
SPKR_A_P
Output
Amplifier ΣΔ - DAC
SPKR_A_N
Digital
Dual Channel Mono Voice Circuitry
Band Audio Input

MIC_B_P
Input
Amplifier ΣΔ -ADC
MIC_B_N
MIC_A_P
Input
Amplifier ΣΔ -ADC
MIC_A_N
Figure 10.2: Codec Audio Input and Output Stages

The audio codec uses a fully differential architecture in the analogue signal path, which results in low noise sensitivity
and good power supply rejection while effectively doubling the signal amplitude. It operates from a single power-
supply of 1.5V and uses a minimum of external components.
10.2.2 ADC
The ADC consists of:
■ Two second-order Sigma Delta converters allowing two separate channels that are identical in functionality,
as shown in Figure 10.2.
■ Two gain stages for each channel, one of which is an analogue gain stage and the other is a digital gain
stage.
10.2.3 ADC Sample Rate

Each ADC supports 8kHz sample rate only.
10.2.4 ADC Digital Gain

The digital gain stage has a programmable selection value in the range of 0 to 15 with the associated ADC gain
settings summarised in Table 10.1. There is also a high resolution digital gain mode that allows the gain to be
changed in 1/32dB steps. Contact CSR for more information.
Advance Information
Audio Interface
Gain Selection Value ADC Digital Gain Setting (dB)
0 0
1 3.5
2 6
3 9.5
4 12
5 15.5
6 18
7 21.5

8 -24
9 -20.5
10 -18
11 -14.5
12 -12
13 -8.5
14 -6
15 -2.5
Table 10.1: ADC Digital Gain Rate Selection
10.2.5 ADC Analogue Gain

Figure 10.3 shows the equivalent block diagram for the ADC analogue amplifier. It is a two-stage amplifier:
■ The first stage amplifier has a selectable gain of either bypass for line input mode or gain of 24dB gain for
the microphone mode.
■ The second stage has a programmable gain with seven individual 3dB steps. By combining the 24dB gain
selection of the microphone input with the seven individual 3dB gain steps, the overall range of the analogue
amplifier is approximately -3dB to 42dB in 3dB steps. All gain control of the ADC is controlled by the
BlueTunes.
Advance Information
Audio Interface
Switches shown for Line Mode
Bypass or 24dB gain -3dB to 18dB gain
P P
N N
Line Mode / Mic Mode Gain 0:7
Microphone Mode input impedance = 6kΩ

Line mode input impedance = 6kΩ to 30kΩ

Figure 10.3: ADC Analogue Amplifier Block Diagram
10.2.6 DAC
The DAC consists of:
■ Two second-order Sigma Delta converters allowing two separate channels that are identical in functionality,
as shown in Figure 10.2.
■ Two gain stages for each channel, one of which is an analogue gain stage and the other is a digital gain
stage.
10.2.7 DAC Sample Rate Selection

Each DAC supports the following samples rates:
■ 8kHz
■ 11.025kHz
■ 12kHz
■ 16kHz
■ 22.050kHz
■ 24kHz
■ 32kHz
■ 44.1kHz
■ 48kHz
10.2.8 DAC Digital Gain

The digital gain stage has a programmable selection value in the range of 0 to 15 with associated DAC gain settings,
summarised in Table 10.2. There is also a high resolution digital gain mode that allows the gain to be changed in
1/32dB steps. Contact CSR for more information.
The overall gain control of the DAC is controlled by the BlueTunes. Its setting is a combined function of the digital
and analogue amplifier settings.
Digital Gain Selection Value DAC Digital Gain Setting (dB)
0 0
1 3.5
2 6
3 9.5
4 12
Advance Information
Audio Interface
Digital Gain Selection Value DAC Digital Gain Setting (dB)
5 15.5
6 18
7 21.5
8 -24
9 -20.5
10 -18
11 -14.5
12 -12

13 -8.5
14 -6
15 -2.5
Table 10.2: DAC Digital Gain Rate Selection
Advance Information
Audio Interface
10.2.9 DAC Analogue Gain

The DAC analogue gain stage consists of eight gain selection values that represent seven 3dB steps, as shown in
Table 10.3.
The overall gain control of the DAC is controlled by the BlueTunes. Its setting is a combined function of the digital
and analogue amplifier settings.
Analogue Gain Selection Value DAC Analogue Gain Setting (dB)
7 3
6 0
5 -3
4 -6

3 -9
2 -12
1 -15
0 -18
Table 10.3: DAC Analogue Gain Rate Selection
Advance Information
Audio Interface
10.2.10 Microphone Input

The microphone for each channel should be biased as shown in Figure 10.4. The microphone bias, MIC_BIAS,
derives its power from the BAT_P and requires a 1µF capacitor on its output.
Microphone Bias
R2
C1 MIC_A_P
C3
Input
R1
C2 Amplifier
MIC_A_N
C4
+ MIC1
Figure 10.4: Microphone Biasing (Single Channel Shown)

The MIC_BIAS is like any voltage regulator and requires a minimum load to maintain regulation. The MIC_BIAS

maintains regulation within the limits 0.200 - 1.230mA. If the microphone sits below these limits, then the microphone
output must be pre-loaded with a large value resistor to ground.
The audio input is intended for use in the range from 1μA @ 94dB SPL to about 10μA @ 94dB SPL. With biasing
resistors R1 and R2 equal to 1kΩ, this requires microphones with sensitivity between about –40dBV and –60dBV.
The input impedance at MIC_A_N, MIC_A_P, MIC_B_N and MIC_B_P is typically 6.0kΩ.
C1 and C2 should be 150nF if bass roll-off is required to limit wind noise on the microphone.
R1 sets the microphone load impedance and is normally in a range of 1 - 2kΩ.
R2, C3 and C4 improve the supply rejection by decoupling supply noise from the microphone. Values should be
selected as required. R2 may be connected to a convenient supply, in which case the bias network is permanently
enabled, or to the MIC_BIAS output (which is ground referenced and provides good rejection of the supply), which
may be configured to provide bias only when the microphone is required.
The microphone bias provides a 4-bit programmable output voltage, shown in Table 10.4, with a 4-bit programmable
output current, shown in Table 10.5.
The characteristics of the microphone bias include:
■ Power supply:
■ BlueTunes ROM QFN microphone supply is BAT_P
■ Minimum input voltage = Output voltage + drop-out voltage
■ Maximum input voltage is 4.4V
■ Typically the microphone bias is at the same level as VDD_AUDIO (1.5V)
■ Drop-out voltage:
■ 300mV minimum
■ Guaranteed for configuration of voltage or current output shown in Table 10.4 and Table 10.5
■ Output voltage:
■ 4-bit programmable between 1.7 - 3.6V
■ Tolerance 90 - 110%
■ Output current:
■ 4-bit programmable between 200µA – 1.230mA
■ Maximum current guaranteed to be >1mA
■ Load capacitance:
■ Unconditionally stable for 1µF ±20% and 2.2µF ±20% pure C
Advance Information
Audio Interface
Output Step VOL_SET[3:0] Min Typ Max Units
0 0000 - 1.71 - V
1 0001 - 1.76 - V
2 0010 - 1.82 - V
3 0011 - 1.87 - V
4 0100 - 1.95 - V
5 0101 - 2.02 - V
6 0110 - 2.10 - V

7 0111 - 2.18 - V
8 1000 - 2.32 - V
9 1001 - 2.43 - V
10 1010 - 2.56 - V
11 1011 - 2.69 - V
12 1100 - 2.90 - V
13 1101 - 3.08 - V
14 1110 - 3.33 - V
15 1111 - 3.57 - V
Table 10.4: Voltage Output Steps
Advance Information
Audio Interface
Output Step CUR_SET[3:0] Typ Units
0 0000 0.200 mA
1 0001 0.280 mA
2 0010 0.340 mA
3 0011 0.420 mA
4 0100 0.480 mA
5 0101 0.530 mA
6 0110 0.610 mA

7 0111 0.670 mA
8 1000 0.750 mA
9 1001 0.810 mA
10 1010 0.860 mA
11 1011 0.950 mA
12 1100 1.000 mA
13 1101 1.090 mA
14 1110 1.140 mA
15 1111 1.230 mA
Table 10.5: Current Output Steps

Note:
For BAT_P, the PSRR at 100Hz - 22kHz, with >300mV supply headroom, decoupling capacitor of 1.1μF, is
typically 58.9dB and worst case 53.4dB.
For VDD_AUDIO, the PSRR at 100Hz - 22kHz, decoupling capacitor of 1.1μF, is typically 88dB and worst case
60dB.
10.2.11 Line Input

If the input analogue gain is set to less than 24dB, BlueTunes ROM QFN automatically selects line input mode. In
line input mode the first stage of the amplifier is automatically disabled, providing additional power saving. In line
input mode the input impedance varies from 6kΩ - 30kΩ, depending on the volume setting. Figure 10.5 and Figure
10.6 show two circuits for line input operation and show connections for either differential or single-ended inputs.
C1
MIC_A_P
C2
MIC_A_N
Figure 10.5: Differential Input (Single Channel Shown)
Advance Information
Audio Interface
C1
MIC_A_P
C2
MIC_A_N
Figure 10.6: Single-Ended Input (Single Channel Shown)
10.2.12 Output Stage

The output stage digital circuitry converts the signal from 16-bit per sample, linear PCM of variable sampling
frequency to bit stream, which is fed into the analogue output circuitry.
The output stage circuit comprises a DAC with gain setting and class AB output stage amplifier. The output is
available as a differential signal between SPKR_A_N and SPKR_A_P for the left channel, as shown in Figure
10.7, and between SPKR_B_N and SPKR_B_P for the right channel.

The output stage is capable of driving a speaker directly when its impedance is at least 8Ω and an external regulator
is used, but this will be at a reduced output swing.
SPKR_A_P
SPKR_A_N
Figure 10.7: Speaker Output (Single Channel Shown)

The analogue gain of the output stage is controlled by a 3-bit programmable resistive divider, which sets the gain in
steps of approximately 3dB.
10.2.13 Mono Operation

Mono operation is a single-channel operation of the stereo codec. The left channel represents the single mono
channel for audio in and audio out. In mono operation the right channel is auxiliary mono channel that may be used
in dual mono channel operation.
In single channel mono operation, the power consumption can be reduced by disabling the other channel.
Important Note:
For mono operation this data sheet uses the left channel for standard mono operation for audio input and output
and with respect to software and any registers, channel 0 or channel A represents the standard mono channel
for audio input and output. In mono operation the second channel which is the right channel, channel 1 or channel
B could be used as a second mono channel if required and this channel is referred to as the auxiliary mono
channel for audio input and output.
10.2.14 Side Tone

In some applications it is necessary to implement side tone. This involves feeding an attenuated version of the
microphone signal to the earpiece. The BlueTunes ROM QFN codec contains side tone circuitry to do this. The side
tone hardware is configured through the following PS Keys:
■ PSKEY_SIDE_TONE_ENABLE
■ PSKEY_SIDE_TONE_GAIN
■ PSKEY_SIDE_TONE_AFTER_ADC
■ PSKEY_SIDE_TONE_AFTER_DAC
Advance Information
Audio Interface
10.2.15 Integrated Digital Filter

BlueTunes ROM QFN has a programmable digital filter integrated into the ADC channel of the codec. The filter is a
two stage, second order IIR and can be used for functions such as custom wind noise rejection. The filter also has
optional DC blocking.
The filter has 10 configuration words used as follows:
■ 1 for gain value
■ 8 for coefficient values
■ 1 for enabling and disabling the DC blocking
The gain and coefficients are all 12-bit 2's complement signed integer with the format XX.XXXXXXXXXX
Note:
The position of the binary point is between bit 10 and bit 9, where bit 11 is the most significant bit.
For example:

01.1111111111 = most positive number, close to 2
01.0000000000 = 1
00.0000000000 = 0
11.0000000000 = -1
10.0000000000 = -2, most negative number
The equation for the IIR filter is shown in Equation 10.1. When the DC blocking is enabled the equation is shown in
Equation 10.2.
The filter can be configured, enabled and disabled from the VM via the CodecSetIIRFilterA and
CodecSetIIRFilterB traps2. The configuration function takes 10 variables in the order shown below:
0 : Gain
1 : b01
2 : b02
3 : a01
4 : a02
5 : b11
6 : b12
7 : a11
8 : a12
9 : DC Block (1 = enable, 0 = disable)
2 Requires firmware support
Advance Information
Audio Interface
(1 +b −1 −2 ) (1 +b −1 −2 )
z +b z z +b z
01 02 11 12
Filter, H(z) = Gain × ×
(1 +a −1 −2 ) (1 +a −1 −2 )
01 z + a02 z 11 z + a12 z
Equation 10.1: IIR Filter Transfer Function, H(z)
Filter with DC Blocking, HDC (z) = H(z) × ( 1 − z−1 )
Equation 10.2: IIR Filter plus DC Blocking Transfer Function, H DC(z)
10.3 AuriStream Codec

The AuriStream codec is an ADPCM codec and works on the principle of transmitting the difference between the
actual value of the signal and a prediction rather than the signal itself. Therefore, the information transmitted is
reduced along with the power requirement. The quality of the output depends on the number of bits used to represent
the sample.
Note:
The use of the AuriStream codec is as follows:

■ The AuriStream codec is an alternative to standard CVSD
■ It requires CSR devices supporting AuriStream at both ends of the link
■ AuriStream is negotiated when the link is brought up. If AuriStream is not supported on either end, the
system will switch to standard CVSD ensuring full interoperability with any non-AuriStream Bluetooth
devices
The inclusion of the AuriStream codec can greatly enhance audio quality in the wideband mode and results in
reduced power consumption compared to a CVSD implementation when used at both ends of the system.
AuriStream codec on BlueTunes ROM QFN supports only one G726 mode of operation which is configured by PS
Key PSKEY_USR28:
■ 4-bit, 8kHz sample rate, 32kbps
■ Mode 1 gives 30% reduced power in both handset and headset Bluetooth ICs
Advance Information
Power Control and Regulation
11 Power Control and Regulation

BlueTunes ROM QFN contains 3 regulators:
■ One switch-mode regulator used to generate a 1.8V rail for the chip I/Os
■ Two low-voltage regulators which run in parallel to supply the 1.5V core supplies from the 1.8V rail.
Various configurations for power control and regulation with BlueTunes ROM QFN are as follows:
■ Powered from the switch-mode regulator and the low-voltage regulators in series, as shown in Figure 11.1
■ Powered directly from an external 1.8V rail, omittiing the switch-mode regulator
■ Powered from an external 1.5V rail omitting all regulators
1.8V Rail
VDD_CHG IN
Battery Charger
OUT

L1
BAT_P LX
LX
VSS Switch Mode
VREGENABLE_H Regulator VDD_SMP_CORE C1
EN SENSE
VREGENABLE_L VDD_ANA
EN OUT
Low Voltage
Linear Regulator
IN SENSE
VREGIN_L
VREGIN_AUDIO
IN OUT
VDD_AUDIO
Audio Low
Voltage Regulator
EN SENSE
Figure 11.1: Voltage Regulator Configuration
11.1 Power Sequencing

The 1.50V supply rails are VDD_ANA, VDD_LO, VDD_RADIO, VDD_AUDIO and VDD_CORE. CSR recommends
that these supply rails are all powered at the same time.
The digital I/O supply rails are VDD_PIO, VDD_PADS and VDD_UART.
The sequence of powering the 1.50V supply rails relative to the digital I/O supply rails is not important. If the digital
I/O supply rails are powered before the 1.50V supply rails, all digital I/Os will have a weak pull-down irrespective of
the reset state.
VDD_ANA, VDD_LO, VDD_RADIO and VDD_AUDIO can connect directly to a 1.50V supply.
A simple RC filter is recommended for VDD_CORE to reduce transients fed back onto the power supply rails.
The digital I/O supply rails are connected together or independently to an appropriate voltage rail. Decoupling of the
digital I/O supply rails is recommended.
11.2 External Voltage Source

If any of the supply rails for BlueTunes ROM QFN are supplied from an external voltage source, rather than one of
the internal voltage regulators, then it is recommended that VDD_LO, VDD_RADIO and VDD_AUDIO should have
less than 10mV rms noise levels between 0 to 10MHz. Also avoid single tone frequencies.
Advance Information
The transient response of any external regulator used should match or be better than the internal regulator available
on BlueTunes ROM QFN, refer to regulator characteristics in Section 13. It is essential that the power rail recovers
quickly at the start of a packet, where the power consumption jumps to high levels.
11.3 Switch-mode Regulator

The on-chip switch-mode regulator is available to power a 1.8V supply rail.
An external LC filter circuit of a low-resistance series inductor, L1 (22µH), followed by a low ESR shunt capacitor,
C1 (4.7µF), is required between the LX terminal and the 1.8V supply rail. A connection between the 1.8V supply rail
and the VDD_SMP_CORE pin is required.
A decoupling capacitor (2.2µF) is required between BAT_P and VSS.
To maintain high-efficiency power conversion and low supply ripple, it is essential that the series resistance of tracks
between the BAT_P and VSS terminals, the filter and decoupling components, and the external voltage source are
minimised.
The switch-mode regulator is enabled by either:
■ VREGENABLE_H pin

■ BlueTunes ROM QFN device firmware
■ BlueTunes ROM QFN battery charger
The switch-mode regulator is switched into a low-power pulse skipping mode when the device is sent into deep-
sleep mode, or in reset.
When the switch-mode regulator is not required the terminals BAT_P and LX must be grounded or left unconnected.
11.4 Low-voltage Linear Regulator

The low-voltage linear regulator is available to power a 1.5V supply rail. Its output is connected internally to
VDD_ANA, and can be connected externally to the other 1.5V power inputs.
If the low-voltage linear regulator is used a smoothing circuit using a low ESR 2.2µF capacitor and a 2.2Ω resistor
to ground, should be connected to the output of the low-voltage linear regulator, VDD_ANA. Alternatively use a 2.2µF
capacitor with an ESR of at least 2Ω.
The low-voltage linear regulator is enabled by either:
■ VREGENABLE_L pin
The low-voltage linear regulator is switched into a low power mode when the device is in deep-sleep mode, or in
reset.
When the low-voltage linear regulator is not used the terminal VREGIN_L must be left unconnected, or tied to
VDD_ANA.
11.5 Low-voltage Audio Linear Regulator

The low-voltage audio linear regulator is available to power a 1.5V audio supply rail. Its output is connected internally
to VDD_AUDIO, and can be connected externally to the other 1.5V audio power inputs.
If the low-voltage audio linear regulator is used a smoothing circuit using a low ESR 2.2µF capacitor and a 2.2Ω
resistor to ground, should be connected to the output of the low-voltage linear regulator, VDD_AUDIO. Alternatively
use a 2.2µF capacitor with an ESR of at least 2Ω.
The low-voltage audio linear regulator is enabled by either:
■ VREGENABLE_L pin
The low-voltage audio linear regulator is switched into a low-power mode when no audio cells are enabled, or when
the chip is in reset.
When this regulator is not used the terminal VREGIN_AUDIO must be left unconnected or tied to VDD_AUDIO.
Advance Information
11.6 Voltage Regulator Enable Pins

The voltage regulator enable pins, VREGENABLE_H and VREGENABLE_L, are used to enable the
BlueTunes ROM QFN device if the on-chip regulators are being used. Table 11.1 shows the enable pin responsible
for each voltage regulator.
Enable Pin Regulator
VREGENABLE_H Switch-mode Regulator
VREGENABLE_L Low-voltage Linear Regulator and Low-voltage Audio Linear Regulator
Table 11.1: BlueTunes ROM QFN Voltage Regulator Enable Pins

The voltage regulator enable pins are active high, with weak pull-downs.
BlueTunes ROM QFN boots-up when the voltage regulator enable pins are pulled high, enabling the appropriate
regulators. The firmware then latches the regulators on and the voltage regulator enable pins may then be released.

The status of the VREGENABLE_H pin is available to firmware through an internal connection. VREGENABLE_H
also works as an input line.
11.7 Battery Charger

The battery charger is a constant current / constant voltage charger circuit, and is suitable for lithium ion/polymer
batteries only. It shares a connection to the battery terminal, BAT_P, with the switch-mode regulator. However it may
be used in conjunction with either of the high-voltage regulators on the device.
The constant current level can be varied to allow charging of different capacity batteries.
The charger enters various states of operation as it charges a battery, as listed below. A full operational description
is in BlueCore5 Charger Description and Calibration Application Note:
■ Off : entered when charger disconnected.
■ Trickle charge: entered when battery is below 2.9V. The battery is charged at a nominal 4.5mA. This mode
is for the safe charge of deeply discharged cells.
■ Fast charge constant current: entered when battery is above 2.9V. The charger enters the main fast charge
mode. This mode charges the battery at the selected constant current, Ichgset.
■ Fast charge constant voltage: entered when battery has reached a selected voltage, Vfloat. The charger
switches mode to maintain the cell voltage at the Vfloat voltage by adjusting the charge current.
■ Standby: this is the state when the battery is fully charged and no charging takes place. The battery voltage
is continuously monitored and if it drops by more than 150mV below the Vfloat voltage the charger will re-
enter the fast charge constant current mode to keep the battery fully charged.
When a voltage is applied to the charger input terminal VDD_CHG, and the battery is not fully charged, the charger
operates and an LED connected to the terminal LED[0] illuminates. By default, until the firmware is running, the LED
pulses at a low-duty cycle to minimise current consumption.
The battery charger circuitry auto-detects the presence of a power source, allowing the firmware to detect, using an
internal status bit, when the charger is powered. Therefore when the charger supply is not connected to VDD_CHG,
the terminal must be left open-circuit. The VDD_CHG pin when not connected must be allowed to float and not pulled
to a power rail. When the battery charger is not enabled this pin may float to a low undefined voltage. Any DC
connection increases current consumption of the device. Capacitive components may be connected such as diodes,
FETs and ESD protection.
The battery charger is designed to operate with a permanently connected battery. If the application enables the
charger input to be connected while the battery is disconnected, then the BAT_P pin voltage may become unstable.
This in turn may cause damage to the internal switch-mode regulator. Connecting a 470µF capacitor to BAT_P limits
these oscillations so preventing damage.
Advance Information
11.8 LED Drivers

BlueTunes ROM QFN includes two pads dedicated to driving LED indicators. Both terminals may be controlled by
firmware, while LED[0] can also be set by the battery charger.
The terminals are open-drain outputs, so the LED must be connected from a positive supply rail to the pad in series
with a current limiting resistor.
It is recommended that the LED pad (LED[0] or LED[1] pins) are operated with a pad voltage below 0.5V. In this
case the pad can be thought of as a resistor, RON. The resistance together with the external series resistor sets the
current, ILED, in the LED. The current is also dependent on the external voltage, VDD, shown in Figure 11.2.
VDD
LED Forward Voltage, VF

ILED

RLED Resistor Voltage Drop, VR
LED0 or LED1
Pad Voltage, VPAD; RON = 20Ω
Figure 11.2: LED Equivalent Circuit

From Figure 11.2 it is possible to derive Equation 11.1 to calculate ILED or if a known value of current is required
through the LED, to give a specific luminous intensity, then the value of RLED could be calculated.
VDD − V
F
ILED =
R +R
LED ON
Equation 11.1: LED Current

For LED[0] or LED[1] pad to act as resistance, the external series resistor, RLED, needs to be such that the voltage
drop across it, VR, keeps VPAD below 0.5V. Therefore Equation 11.2 also applies.
VDD = VF + VR + VPAD
Equation 11.2: LED PAD Voltage

Note:
The LED current will add to the overall current, so conservative selection of the LEDs will extend talk‑time.
Advance Information
11.9 Reset, RST#

BlueTunes ROM QFN can be reset from several sources:
■ RST# pin
■ Power-on reset
■ UART break character
■ Software configured watchdog timer
The RST# pin is an active low reset and is internally filtered using the internal low frequency clock oscillator. A reset
is performed between 1.5 and 4.0ms following RST# being active. CSR recommends that RST# be applied for a
period greater than 5ms.
The power-on reset typically occurs when the VDD_CORE supply falls below 1.26V and is released when
VDD_CORE rises above typically 1.31V. At reset the digital I/O pins are set to inputs for bi-directional pins and
outputs are tri-state. Following a reset, BlueTunes ROM QFN assumes the maximum XTAL_IN frequency, which
ensures that the internal clocks run at a safe (low) frequency until BlueTunes ROM QFN is configured for the actual
XTAL_IN frequency. If no clock is present at XTAL_IN, the oscillator in BlueTunes ROM QFN free runs, again at a
safe frequency.

11.9.1 Digital Pin States on Reset
Table 11.2 shows the pin states of BlueTunes ROM QFN on reset.
No Core Voltage
Pin Name / Group I/O Type Full Chip Reset
Reset
UART_RX Digital input with PD PD PD
UART_CTS Digital input with PD PD PD
UART_TX Digital bidirectional with PU PU PU
UART_RTS Digital bidirectional with PU PU PU
SPI_MOSI Digital input with PD PD PD
SPI_CLK Digital input with PD PD PD
SPI_CS# Digital input with PU PU PU
SPI_MISO Digital tri-state output with PD PD PD
RST# Digital input with PU PU PU
TEST_EN Digital input with PD PD PD
PIO[15:11,9:0] Digital bidirectional with PU/ PD PD PD
Table 11.2: BlueTunes ROM QFN Digital Pin States on Reset

Note:
PU = pull-up
PD = pull-down
Pull-up and pull-down default to weak values unless specified otherwise
11.9.2 Status after Reset

The chip status after a reset is as follows:
■ Warm reset: data rate and RAM data remain available
■ Cold reset: data rate and RAM data not available
Advance Information
Example Application Schematic
12 Example Application Schematic

VBAT
SW1
PWR
1V5 1V5 1V5 1V5 1V8 VBUS VBAT 1V8 1V5_AUDIO 1V8 1V8
1V5 R15
1V8 10k 1V5_AUDIO
VBUS
R1
2R2 R2
2R2 1V8
L1
22u SW2
PWR
R16
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10
1V5 15p 15p 2u2 22n 4u7 2u2 2u2 2u2 22n 22n 10k
VBAT
1V8
X1
TSX3225 26 MHz
67
66
63
17
34
37
36
39
38
35
68
46
47
62
13
16
2
1
L2 U1 LED1
SW3
15n R17
VDD_CORE
VDD_CORE
VDD_BUCK_CORE
VREGENABLE_H
VDD_PADS
VDD_UART
VDD_CHG
VDD_PIO
BAT_P
VREGENABLE_L
VREGIN_L
VDD_LO
VDD_RADIO
VDD_RADIO
VREGIN_L_AUDIO
LX
VDD_AUDIO
VDD_ANA
3 C12 10k
XTAL_IN C13
6p8

18p
C11
3
15p FLT1
Blue Red
DBF81F107-CSR SW4
R11
2 6 64 4 R5 R4 10k 1V8
DC BAL RF_P XTAL_OUT
C14 47R 390R
1
UNBAL REG REG REG 33 LED1
0R0 LED[1]
ANT1 3 4 65 32LED0 C24
GND
GND
GND
NC BAL RF_N LED[0] SW5 R12 R14

R18 2k2 100n
L3 L4 2k2
8n2 NF 20 PIO14 10k
PIO[14]
5
8
7
19 PIO13 R13
PIO[13] 2k2
18 PIO12
PIO[12]
15 PIO11
PIO[11] U4
14 8 1
PIO[9] VCC E0
21 WP 7 2
PIO[8] WC E1
22 SDA 5 3
PIO[7] SDA E2
23 SCL 6 4
PIO[6] SCL VSS
24
BlueTunes ROM QFN
PIO[5]
25 M24C32-FMB5TG
PIO[4]
58
PIO[3] 1V8
59 SW6
PIO[2] R19
60 PIO1
PIO[1]
61 10k
PIO[0]
29 SPI_CLK
SPI_CLK SPI_CLK
31 SPI_MISO
SPI_MISO SPI_MISO
28 SPI_MOSI
SPI_MOSI SPI_MOSI
30 SPI_CS#
SPI_CS# SPI_CS#
9 UART_RX
UART_TX UART_RX
10 UART_TX
UART_RX UART_TX
11
UART_CTS
12
UART_RTS
7
AIO[0]
6
VSS_CNTR_PAD
AIO[1]
AU_REF_DCPL
5
LO_REF
MIC_BIAS
SPK_A_N
SPK_B_N
SPK_A_P
SPK_B_P
MIC_B_N
MIC_A_N
MIC_B_P
MIC_A_P
27 C16
TEST_EN
22n
26
NC
NC
NC
NC
NC
NC
NC
RST#
40
41
42
49
69
43
44
55
53
54
57
56
MIC_A_P 51
MIC_A_N 52
MIC_B_P 48
MIC_B_N 50
45
8
R23
1k RST#
MIC_BIAS
0402 C22
47n C21 C33
2u2 2u2 RST# VBUS
C17 C18 C19 C20
100n 100n 100n 100n
D
R9 R10 C15
Q1 220n
2k2 MIC_BIAS 2k2 MIC_BIAS
NTA4153N
G
S
R8
220k
Connect at star point
L5
MIC_BP
L6
MIC_AP
MIC_N
SPK_AN
SPK_AP
SPK_BP
SPK_BN
Figure 12.1: BlueTunes ROM QFN Example Application Schematic
Advance Information
Electrical Characteristics
13 Electrical Characteristics
13.1 Absolute Maximum Ratings
Rating Min Max Unit
Storage Temperature -40 105 °C
Core supply VDD_ANA, VDD_LO, VDD_RADIO,

-0.4 1.65 V
voltage VDD_AUDIO and VDD_CORE
I/O voltage VDD_PIO, VDD_PADS and VDD_UART -0.4 3.6 V
VREGIN_L -0.4 2.7 V
VREGIN_AUDIO -0.4 2.7 V

VREGENABLE_H and VREGENABLE_L -0.4 4.9 V
Supply voltage
BAT_P -0.4 4.4 V
LED[1:0] -0.4 4.4 V
VDD_CHG -0.4 6.5 V
Other terminal voltages VSS - 0.4 VDD + 0.4 V
13.2 Recommended Operating Conditions

Operating Condition Min Typ Max Unit
Operating temperature range -20 20 70 °C
VDD_ANA, VDD_LO,
Core supply VDD_RADIO,
1.42 1.50 1.57 V
voltage VDD_AUDIO and
VDD_CORE
I/O supply VDD_PIO, VDD_PADS

1.7 3.3 3.6 V
voltage and VDD_UART
Note:
For radio performance over temperature refer to BlueTunes ROM QFN Performance Specification.
BlueTunes ROM QFN operates up to the maximum supply voltage given in the Absolute Maximum Ratings, but
RF performance is not guaranteed above 4.2V.
Advance Information
13.3 Input/Output Terminal Characteristics

Note:
For all I/O Terminal Characteristics:
■ VDD_ANA, VDD_LO, VDD_RADIO, VDD_AUDIO and VDD_CORE at 1.50V unless shown otherwise.
■ VDD_PIO, VDD_PADS and VDD_UART at 3.3V unless shown otherwise.
■ Current drawn into a pin is defined as positive; current supplied out of a pin is defined as negative.
13.3.1 Low-voltage Linear Regulator
Normal Operation Min Typ Max Unit
Input voltage 1.70 1.80 1.95 V
Output voltage (Iload = 70mA / VREGIN_L = 1.7V) 1.42 1.50 1.57 V
Temperature coefficient -300 0 300 ppm/°C

Output noise(a) (b) - - 1 mV rms
Load regulation (100µA < Iload < 90mA ), ΔVout - - 5 mV
Settling time(a) (c) - - 50 μs
Maximum output current 115 - - mA
Minimum load current 5 - 100 µA
Drop-out voltage ( Iload = 115mA) - - 300 mV
Quiescent current (excluding load, Iload < 1mA) 50 90 150 μA
Low-power Mode (d)
Quiescent current (excluding load, Iload < 100μA) 5 8 15 μA
(a) Regulator output connected to 47nF pure and 4.7μF 2.2Ω ESR capacitors.
(b) Frequency range 100Hz to 100kHz.
(c) 1mA to 115mA pulsed load.
(d) The regulator is in low power mode when the chip is in deep sleep mode, or in reset.
Advance Information
13.3.2 Low-voltage Linear Audio Regulator
Normal Operation Min Typ Max Unit
Input voltage 1.70 1.80 1.95 V
Output voltage (Iload = 70mA / VREGIN_AUDIO = 1.7V) 1.42 1.50 1.57 V
Temperature coefficient -300 0 300 ppm/°C
Output noise(a) (b) - - 1 mV rms
Settling time(a) (c) - - 50 μs

Maximum output current 70 - - mA
Minimum load current 5 - 100 µA
Dropout voltage ( Iload = 70mA) - - 300 mV
Quiescent current (excluding load, Iload < 1mA) 25 30 50 μA
Low-power Mode (d)
Quiescent current (excluding load, Iload < 100μA) 5 8 15 μA
(a) Regulator output connected to 47nF pure and 4.7μF 2.2Ω ESR capacitors.
(b) Frequency range 100Hz to 100kHz.
(c) 1mA to 70mA pulsed load.
Advance Information
13.3.3 Switch-mode Regulator
Switch-mode Regulator Min Typ Max Unit
Input voltage 2.5 - 4.4 V
Output voltage (Iload = 70mA) 1.70 1.80 1.90 V
Temperature coefficient -250 - 250 ppm/°C
Normal Operation
Output ripple - - 10 mV rms
Transient settling time(a) - - 50 μs
Maximum load current 200 - - mA

Conversion efficiency (Iload = 70mA) - 90 - %
Switching frequency(b) - 1.333 - MHz
Start-up current limit(c) 30 50 80 mA
Low-power Mode (d)
Output ripple - - 1 mV rms
Transient settling time(e) - - 700 μs
Maximum load current 5 - - mA
Minimum load current 1 - - µA
Conversion efficiency (Iload = 1mA ) - 80 - %
Switching frequency(f) 50 - 150 kHz
(a) For step changes in load of 30 to 80mA and 80 to 30mA.

(b) Locked to crystal frequency.
(c) Current is limited on start-up to prevent excessive stored energy in the filter inductor.
(e) 100μA to 1mA pulsed load.
(f) Defines minimum period between pulses. Pulses are skipped at low current loads.
Note:
The external inductor used with the switch-mode regulator must have an ESR in the range 0.3 - 0.7Ω:
■ Low ESR < 0.3Ω causes instability.
■ High ESR > 0.7Ω derates the maximum current.
Advance Information
13.3.4 Battery Charger
Battery Charger Min Typ Max Unit
Input voltage 4.5 - 6.5 V
Charging Mode (BAT_P rising to 4.2V) Min Typ Max Unit
Supply current(a) - 4.5 6 mA
Battery trickle charge current(b) - 4 - mA
Headroom(e) > 0.7V - 140 - mA

Maximum battery fast charge
current (I-CTRL = 15)(c) (d)
Headroom = 0.3V - 120 - mA

Headroom > 0.7V - 40 - mA
Minimum battery fast charge
current (I-CTRL = 0)(c) (d)
Headroom = 0.3V - 35 - mA
Fast charge step size

Spread ±17% - 6.3 - mA
(I-CTRL = 0 to 15)
Trickle charge voltage threshold - 2.9 - V
Float voltage (with correct trim value set), VFLOAT (f) 4.17 4.2 4.23 V
Float voltage trim step size(f) - 50 - mV
Battery charge termination current, % of fast charge

5 10 20 %
current
(a) Current into VDD_CHG does not include current delivered to battery (IVDD_CHG - IBAT_P)
(b) BAT_P < Float voltage
(c) Charge current can be set in 16 equally spaced steps.
(d) Trickle charge threshold < BAT_P < Float voltage
(e) Where headroom = VDD_CHG - BAT_P
(f) Float voltage can be adjusted in 15 steps. Trim setting is determined in production test and must be loaded into the battery charger by
firmware during boot-up sequence
Standby Mode (BAT_P falling from 4.2V) Min Typ Max Unit
Supply current(a) - 1.5 2 mA
Battery current - -5 - µA
Battery recharge hysteresis(b) 100 - 200 mV
(a) Current into VDD_CHG - does not include current delivered to battery (IVDD_CHG - IBAT_P)
(b) Hysteresis of (VFLOAT - BAT_P) for charging to restart
Advance Information
Shutdown Mode (VDD_CHG too low or disabled by

Min Typ Max Unit
firmware)
Supply current - 1.5 2 mA
Battery current -1 - 0 µA
VDD_CHG rising - 3.90 - V

VDD_CHG under-voltage
threshold
VDD_CHG falling - 3.70 - V
VDD_CHG rising - 0.22 - V

VDD_CHG - BAT_P lockout
threshold
VDD_CHG falling - 0.17 - V
13.3.5 Reset

Power-on Reset Min Typ Max Unit
VDD_CORE falling threshold 1.13 1.25 1.30 V
VDD_CORE rising threshold 1.20 1.30 1.35 V
Hysteresis 0.05 0.10 0.15 V
13.3.6 Regulator Enable
Switching Threshold Min Typ Max Unit
VREGENABLE_H
Rising threshold 0.50 - 0.95 V
Falling threshold 0.35 - 0.80 V
Hysteresis 0.14 - 0.28 V
VREGENABLE_L
Rising threshold 0.50 - 0.95 V
Falling threshold 0.35 - 0.80 V
Hysteresis 0.14 - 0.28 V
Advance Information
13.3.7 Digital Terminals
Supply Voltage Levels Min Typ Max Unit
VDDPRE Pre-driver supply voltage 1.4 1.5 1.6 V
Full spec. 3.0 3.3 3.6 V

VDD I/O supply
voltage (post-driver)
Reduced spec. 1.7 - 3.0 V
Input Voltage Levels Min Typ Max Unit
VIL input logic level low -0.3 - 0.25 x VDD V
VIH input logic level high 0.625 x VDD - VDD + 0.3 V

VSCHMITT Schmitt voltage 0.25 x VDD - 0.625 x VDD V
Output Voltage Levels Min Typ Max Unit
VOL output logic level low, lOL = 4.0mA 0 - 0.125 V
VOH output logic level high, lOH = -4.0mA 0.75 x VDD - VDD V
Input and Tri-state Currents Min Typ Max Unit
Ii input leakage current at Vin = VDD or 0V -100 0 100 nA
Ioz tri-state output leakage current at Vo = VDD or 0V -100 0 100 nA
With strong pull-up -100 -40 -10 μA
With strong pull-down 10 40 100 μA
With weak pull-up -5 -1.0 -0.2 μA
With weak pull-down -0.2 1.0 5.0 μA
CI Input Capacitance 1.0 - 5.0 pF
Resistive Strength Min Typ Max Unit
Rpuw weak pull-up strength at VDD - 0.2V 0.5 - 2 MΩ
Rpdw weak pull-down strength at 0.2V 0.5 - 2 MΩ
Rpus strong pull-up strength at VDD - 0.2V 10 - 50 kΩ
Rpds strong pull-down strength at 0.2V 10 - 50 kΩ
Advance Information
13.3.8 Mono Codec: Analogue to Digital Converter
Analogue to Digital Converter
Parameter Conditions Min Typ Max Unit
Resolution - - - 16 Bits
Input Sample
- - 8 - kHz
Rate, Fsample
fin = 1kHz Fsample

B/W = 20Hz→20kHz
Signal to Noise
A-Weighted
Ratio, SNR
THD+N < 1% 8kHz - 79 - dB
150mVpk-pk input

Digital Gain Digital Gain Resolution = 1/32dB -24 - 21.5 dB
Analogue Gain Analogue Gain Resolution = 3dB - - 42 dB
Input full scale at maximum gain (differential) - 4 - mV rms
Input full scale at minimum gain (differential) - 800 - mV rms
3dB Bandwidth - 20 - kHz
Microphone mode input impedance - 6.0 - Ω
THD+N (microphone input) @ 30mV rms input - 0.04 - %
Advance Information
13.3.9 Stereo Codec: Digital to Analogue Converter
Digital to Analogue Converter
Parameter Conditions Min Typ Max Unit
Resolution - - - 16 Bits
Output Sample
- 8 - 48 kHz
Rate, Fsample
Fsample
8kHz - 95 - dB
fin = 1kHz 11.025kHz - 95 - dB

B/W = 20Hz→20kHz

16kHz - 95 - dB
Signal to Noise A-Weighted
Ratio, SNR THD+N < 0.01%
22.050kHz - 95 - dB
0dBFS signal
Load = 100kΩ 32kHz - 95 - dB
44.1kHz - 95 - dB
48kHz - 95 - dB
Digital Gain Digital Gain Resolution = 1/32dB -24 - 21.5 dB
Analogue Gain Analogue Gain Resolution = 3dB 0 - -21 dB
Output voltage full-scale swing (differential)(a) - 750 - mV rms
Resistive 16(8) - O.C. Ω

Allowed Load
Capacitive - - 500 pF
THD+N 100kΩ load - - 0.01 %
THD+N 16Ω load - - 0.1 %
SNR (Load = 16Ω, 0dBFS input relative to digital silence) - 95 - dB
(a) Any combination of gain (digital and / or analogue) and input signal which results in the output signal level exceeding the minimum or maximum
signal level (analogue or digital) could result in distortion.
13.3.10 Clocks
Clock Source Min Typ Max Unit
Crystal Oscillator
Crystal frequency(a) 16 26 26 MHz
Digital trim range(b) 5.0 6.2 8.0 pF
Trim step size(b) - 0.1 - pF
Transconductance 2.0 - - mS
Advance Information
Clock Source Min Typ Max Unit
Negative resistance(c) 870 1500 2400 Ω
External Clock
Input frequency(d) 12 26 52 MHz
Clock input level(e) 0.4 - VDD_ANA V pk-pk
Edge jitter (allowable jitter), at zero crossing - - 15 ps rms
XTAL_IN input impedance - ≥10 - kΩ
XTAL_IN input capacitance - ≤4 - pF

(a) Integer multiple of 250kHz
(b) The difference between the internal capacitance at minimum and maximum settings of the internal digital trim.
(c) XTAL frequency = 16MHz; XTAL C0 = 0.75pF; XTAL load capacitance = 8.5pF.
(d) Clock input can be any frequency between 12MHz to 52MHz in steps of 250kHz plus CDMA/3G TCXO frequencies of 14.40, 15.36, 16.2,
16.8, 19.2, 19.44, 19.68, 19.8 and 38.4MHz.
(e) Clock input can be either sinusoidal or square wave. If the peaks of the signal are below VSS or above VDD_ANA. A DC blocking capacitor
is required between the signal and XTAL_IN.
13.3.11 LED Driver Pads
LED Driver Pads Min Typ Max Unit
Off current - 1 2 µA
On resistance VPAD < 0.5V - 20 33 Ω
On resistance, pad enabled

VPAD < 0.5V - 20 50 Ω
by battery charger
Advance Information
13.3.12 Auxiliary ADC
Auxiliary ADC Min Typ Max Unit
Resolution - - 10 Bits
Input voltage range(a) 0 - VDD_ANA V
INL -1 - 1 LSB
Accuracy
(Guaranteed monotonic)
DNL 0 - 1 LSB
Offset -1 - 1 LSB
Gain Error -0.8 - 0.8 %
Input Bandwidth - 100 - kHz

Conversion time - 2.5 - µs
Samples/
Sample rate(b) - - 700
s
(a) LSB size = VDD_ANA/1023

(b) The auxiliary ADC is accessed through a VM function. The sample rate given is achieved as part of this function.
Advance Information
HCI Power Consumption
14 HCI Power Consumption

Average Current
DUT Role Connection Packet Type Description Low-voltage Switch-mode Unit

Linear Regulator Regulator
N/A Deep Sleep - Host connection TBD TBD mA
N/A Page Scan - 1280ms Interval TBD TBD mA
Inquiry (1280ms interval)

N/A Inquiry and Page Scan - TBD TBD mA
Page (1280ms interval)
Master ACL DH1 No traffic TBD TBD mA
Master ACL DH1 File transfer, TX TBD TBD mA
Master ACL DH1 Sniff mode (40ms interval, 1 attempt) TBD TBD mA
Sniff mode (1280ms interval, 8

Master ACL DH1 TBD TBD mA
attempts)
Master SCO HV1 - TBD TBD mA
Master SCO HV3 - TBD TBD mA

Master SCO HV3 TBD TBD mA
attempts)
Master eSCO EV3 - TBD TBD mA
Master eSCO EV5 - TBD TBD mA
Master eSCO EV3 Setting S1 TBD TBD mA
Advance Information
Average Current
Master eSCO 2EV3 Setting S2 TBD TBD mA

Master eSCO 2EV3 Setting S3 TBD TBD mA
Setting S3 with Sniff mode (100ms

Master eSCO 2EV3 TBD TBD mA
interval, 1 attempt)
Slave ACL DH1 No Traffic TBD TBD mA
Slave ACL DH1 File transfer, RX TBD TBD mA
Slave ACL DH1 Sniff mode (40ms interval, 1 attempt) TBD TBD mA

Slave ACL DH1 TBD TBD mA
attempts)
Slave SCO HV1 - TBD TBD mA
Slave SCO HV3 - TBD TBD mA

Slave SCO HV3 TBD TBD mA
attempts)
Advance Information
Average Current
Slave eSCO EV3 - TBD TBD mA

Slave eSCO EV5 - TBD TBD mA
Slave eSCO EV3 Setting S1 TBD TBD mA
Slave eSCO 2EV3 Setting S2 TBD TBD mA
Slave eSCO 2EV3 Setting S3 TBD TBD mA
Setting S3 with Sniff mode (100ms

Slave eSCO 2EV3 TBD TBD mA
interval, 1 attempt)
Note:
Current consumption values are taken with:
■ VREGIN_L for low-voltage linear regulator = 1.8V
■ BAT_P for switch-mode regulator = 3.7V
■ Clock frequency = 16MHz
■ UART baud rate is 115200
■ QFN device.
Advance Information
CSR Green Semiconductor Products and RoHS Compliance
15 CSR Green Semiconductor Products and RoHS Compliance

15.1 RoHS Statement
BlueTunes ROM QFN where explicitly stated in this Data Sheet meets the requirements of Directive 2002/95/EC of
the European Parliament and of the Council on the Restriction of Hazardous Substance (RoHS).
15.1.1 List of Restricted Materials

BlueTunes ROM QFN is compliant with RoHS in relation to the following substances:
■ Cadmium
■ Lead
■ Mercury
■ Hexavalent chromium
■ Polybrominated Biphenyl
■ Polybrominated Diphenyl Ether

In addition, the following substances are not intentionally added to BlueTunes ROM QFN devices:
■ Halogenated flame retardant
■ Antinomy (Sb) and Compounds, including Antimony Trioxide flame retardant
■ Polybrominated Diphenyl and Biphenyl Oxides
■ Tetrabromobisphenol-A bis (2,3-dibromopropylether)
■ Asbestos or Asbestos compounds
■ Azo compounds
■ Organic tin compounds
■ Mirex
■ Polychlorinated napthelenes
■ Polychlorinated terphenyls
■ Polychlorinated biphenyls
■ Polychlorinated/Short chain chlorinated paraffins
■ Polyvinyl Chloride (PVC) and PVC blends
■ Formaldehyde
■ Arsenic and compounds (except as a semiconductor dopant)
■ Beryllium and its compounds
■ Ethylene Glycol Monomethyl Ether or its acetate
■ Ethylene Glycol Monoethyl Ether or its acetate
■ Halogenated dioxins and furans
■ Persistent Organic Pollutants (POP), including Perfluorooctane sulphonates
■ Red phosphorous
■ Ozone Depleting Chemicals (Class I and II): Chlorofluorocarbons (CFC) and Halons
■ Radioactive substances
For further information, see CSR's Environmental Compliance Statement for CSR Green Semiconductor Products.
Advance Information
BlueTunes ROM QFN Software Stack
16 BlueTunes ROM QFN Software Stack

BlueTunes ROM QFN is supplied with Bluetooth v2.1 + EDR specification compliant stack firmware, which runs on
the internal RISC MCU.
The BlueTunes ROM QFN software architecture allows Bluetooth processing and the application program to be
shared in different ways between the internal RISC MCU and an external host processor, if any. The upper layers
of the Bluetooth stack, above the HCI, can be run either on-chip or on the host processor.
16.1 Stand-alone BlueTunes ROM QFN and Kalimba DSP Applications

Internal MCU Kalimba DSP
Stereo Headset Application Stereo Headset Application

Program Memory
RFCOMM SDP

HCI
LM
LC DSP Control
Bluetooth Stack
48KB RAM DM1 DM2 PM
MCU
Host I/O
Radio
Digital Audio
2
Microphones
2 Analogue Audio
Speaker
Figure 16.1: Stand-alone Application: BlueTunes ROM Stereo Headset Solution

Note:
Program memory in Figure 16.1 is internal ROM.

Figure 16.1 shows how the BlueTunes ROM Stereo Headset Solution is built on to the BlueTunes ROM QFN stack.
The application requires no host processor, although it can use a host processor for debugging. All software layers,
including the BlueTunes ROM Stereo Headset Solution software, RFCOMM, HCI stack etc. run internally.
Section 16.4 describes the features of the BlueTunes ROM Stereo Headset Solution software, some of these
features are run as DSP application code in the DSP program memory RAM, e.g. cVc algorithm. This code executes
alongside the main BlueTunes ROM QFN firmware.
Section 16.3 describes the development tools for the BlueTunes ROM Stereo Headset Solution.
Section 16.2 describes the core functionality of the HCI stack available on the BlueTunes ROM QFN.
Advance Information
16.2 HCI Stack
Program Memory
HCI
LM
LC
Bluetooth Stack
48KB RAM
MCU
Host UART Host I/O

Radio
Digital Audio
2
Microphone
2 Analogue Audio
Speaker
Figure 16.2: BlueCore HCI Stack

Note:
Program Memory in Figure 16.2 is internal ROM.

In the implementation shown in Section 16.2 the internal processor runs the Bluetooth stack up to the HCI. The HCI
stack is part of the overall application stack shown in Figure 16.1.
16.2.1 Key Features of the HCI Stack: Standard Bluetooth Functionality

CSR supports the following Bluetooth v2.1 + EDR specification functionality:
■ Secure simple pairing
■ Sniff subrating
■ Encryption pause resume
■ Packet boundary flags
■ Encryption
■ Extended inquiry response
As well as the following mandatory functions of Bluetooth v2.0 + EDR specification:

■ AFH, including classifier
■ Faster connection: enhanced inquiry scan (immediate FHS response)
■ LMP improvements
■ Parameter ranges
And optional Bluetooth v2.0 + EDR specification functionality:
■ AFH as master and automatic channel classification
■ Fast connect: interlaced inquiry and page scan plus RSSI during inquiry
■ eSCO, eV3 +CRC, eV4, eV5
■ SCO handle
■ Synchronisation
The firmware was written against the Bluetooth v2.1 + EDR specification:
■ Bluetooth components:
Advance Information
■ Baseband including LC
■ LM
■ HCI
■ Standard UART HCI Transport Layers
■ All standard Bluetooth radio packet types
■ Full Bluetooth data rate, enhanced data rates of 2 and 3Mbps
■ Operation with up to seven active slaves3
■ Scatternet v2.5 operation
■ Maximum number of simultaneous active ACL connections: 7
■ Maximum number of simultaneous active SCO connections: 34
■ Operation with up to three SCO links, routed to one or more slaves
■ All standard SCO voice coding, plus transparent SCO
■ Standard operating modes: Page, Inquiry, Page-Scan and Inquiry-Scan
■ All standard pairing, authentication, link key and encryption operations
■ Standard Bluetooth power saving mechanisms: Hold, Sniff and Park modes, including Forced Hold
■ Dynamic control of peers' transmit power via LMP
■ Master/slave switch

■ Broadcast
■ Channel quality driven data rate
■ All standard Bluetooth test modes
3 This is the maximum allowed by Bluetooth v2.1 + EDR specification.

4 BlueTunes ROM QFN supports all combinations of active ACL and SCO channels for both master and
slave operation, as specified by the Bluetooth v2.1 + EDR specification.
Advance Information
16.2.2 Key Features of the HCI Stack: Extra Functionality

The firmware extends the standard Bluetooth functionality with the following features:
■ Supports BCSP, a proprietary, reliable alternative to the standard Bluetooth UART Host Transport
■ Supports H4DS, a proprietary alternative to the standard Bluetooth UART Host Transport, supporting Deep
Sleep for low-power applications
■ Provides a set of approximately 50 manufacturer-specific HCI extension commands. This command set,
called BCCMD, provides:
■ Access to BlueTunes ROM QFN general-purpose PIO port
■ The negotiated effective encryption key length on established Bluetooth links
■ Access to the firmware random number generator
■ Controls to set the default and maximum transmit powers; these can help minimise interference
between overlapping, fixed-location piconets
■ Dynamic UART configuration
■ Bluetooth radio transmitter enable/disable. A simple command connects to a dedicated hardware
switch that determines whether the radio can transmit.
■ The firmware can read the voltage on a pair of BlueTunes ROM QFN external pins. This is normally used

to build a battery monitor
■ A block of BCCMD commands provides access to the BlueTunes ROM QFN persistent store configuration
database . The database sets the BlueTunes ROM QFN Bluetooth address, Class of Device, Bluetooth
radio (transmit class) configuration, SCO routing, LM, etc.
■ A UART break condition can be used in three ways:
■ Presenting a UART break condition to the chip can force the chip to perform a hardware reboot
■ Presenting a break condition at boot time can hold the chip in a low power state, preventing normal
initialisation while the condition exists
■ With BCSP, the firmware can be configured to send a break to the host before sending data. (This is
normally used to wake the host from a Deep Sleep state.)
■ A block of Bluetooth radio test or BIST commands allows direct control of the BlueTunes ROM QFN radio.
This aids the development of modules' radio designs, and can be used to support Bluetooth qualification.
■ Hardware low power modes: Shallow Sleep and Deep Sleep. The chip drops into modes that significantly
reduce power consumption when the software goes idle.
■ SCO channels are normally routed via HCI (over BCSP).
Note:
Always refer to the Firmware Release Note for the specific functionality of a particular build.
16.3 BlueTunes ROM Stereo Headset Solution Development Kit, BTN-003-1A

CSR’s BlueTunes ROM Stereo Headset Solution development kit for BlueTunes ROM QFN, order code
BTN-003-1A, includes a headset demonstrator board, form-factor representative example design, audio adapter,
music and voice dongle and necessary interface adapters and cables. In conjunction with the BlueTunes
Configurator tool and other supporting utilities the development kit provides the best environment for designing a
stereo headset solution with BlueTunes ROM QFN.
16.4 BlueTunes ROM QFN Stereo Headset ROM Software, BC57F687A05

■ BlueTunes ROM QFN integrates a stereo audio codec and powerful DSP that enables SBC and MP3
decode, and a configurable 5-band EQ
■ The headset supports A2DP1.2 and AVRCP1.0 profiles enabled with SBC encoder for streaming audio
over Bluetooth and for remote control functionality
■ The headset supports MP3 decoder for improved audio quality and 5-band EQ audio for better user
experience
■ The headset supports HFP1.5 and HSP1.0. Advanced features in these specifications are supported,
including 3-way calling.
■ Bluetooth v2.1 + EDR specification is supported in the ROM software including Secure Simple Pairing,
greatly simplifying the pairing process.
■ BlueTunes ROM QFN includes cVc 1-microphone algorithm for echo and noise reduction and is for headset
applications only. This algorithm is particularly effective for the removal of static noise. It is enabled in the
ROM part and no license key is required. The algorithm is configured for different headset plastics using
the Parameter Manager tool.
Advance Information
■ For superior noise suppression the cVc 2-microphone algorithm can be enabled. This provides 30dB noise
suppression and is effective at cancelling both dynamic and static noise. This software is also configured
using the Parameter Manager tool. A license key is required to enable this algorithm. For more information
see www.csrsupport.com/cvc
■ Most headset features can be configured on the BlueTunes ROM QFN using the BlueTunes Configurator
tool available from www.csrsupport.com/StereoHeadsetSolutions. The tool can be used to read and write
headset configurations directly to the EEPROM or alternatively to a PSR file. Configurable headset features
include:
■ Bluetooth v2.1 + EDR specification features
■ Reconnection policies, e.g. reconnect on power on
■ Audio features, including default volumes
■ 5-band EQ audio enhancements
■ Button events: configuring button presses and durations for certain events, e.g. double press on PIO[1]
for Last Number redial
■ LED indications for states, e.g. headset connected, and events, e.g. power on
■ Indication tones for events and ringtones
■ Battery divider ratios and thresholds, e.g. thresholds for battery low indication, full battery etc.

■ The headset includes the FastStream, CSR’s low latency codec which reduces the latency of the audio
link (from source to sink) significantly to avoid lip-sync issues when listening to audio and watching
video images at the same time.
■ The ROM software has undergone extensive interoperability testing to ensure that it will work with the
majority of phones on the market
Note:
Access to www.csrsupport.com/cvc and www.csrsupport.com/StereoHeadsetSolutions require appropriate

access privileges. For more information contact a CSR representative, email [email protected] or go to
www.csr.com/contacts.
Advance Information
Ordering Information
17 Ordering Information
Package
Device Shipment Order Number
Type Size
Method
QFN 68-lead 8 x 8 x 0.9mm,

BlueTunes ROM QFN Tape and Reel BC57F687A05-IQF-E4
(Pb free) 0.4mm pitch
Note:
MP3 decode functionality requires an appropriate license from Thomson, see Section 17.1.
Until BC57F687A05 reaches Production status, engineering samples order number applies. This is
BC57F687A05-ES-IQF-E, with no minimum order quantity.

BlueTunes ROM QFN is a ROM-based device where the product code has the form BC57F687Axx. xx is the
specific ROM-variant, 05 is the ROM-variant for BlueTunes ROM Stereo Headset Solution.
At Production status Minimum Order Quantity is 2kpcs taped and reeled.
To contact a CSR representative, email [email protected] or go to www.csr.com/contacts
17.1 MP3 Licence Statement

Supply of the BlueTunes ROM QFN does not convey a licence under the relevant intellectual property of Thomson
and/or Frauhofer Gesellschaft nor imply any right to use this product in any finished end user or ready-to-use final
product. An independent licence for such use is required. For details, please visit http://www.mp3licensing.com.
17.2 BlueTunes ROM Stereo Headset Solution Development Kit Ordering

Information
Description Order Number
BlueTunes ROM Stereo Headset Solution Development Kit,

BTN-003-1A
including headset example design
Advance Information
Tape and Reel Information
18 Tape and Reel Information

For tape and reel packing and labelling see IC Packing and Labelling Specification.
18.1 Tape Orientation

Figure 18.1 shows the BlueTunes ROM QFN packing tape orientation.
Pin 1

User Direction of Feed
Figure 18.1: BlueTunes ROM QFN Tape Orientation
18.2 Tape Dimensions

4.0 0.25
•See Note 1
2.0
•See Note 6
R.25
Ø1.5 MIN Ø1.5 +0.1/-0.0 1.75
0.30 ± 0.05
A
R0.3 MAX
7.5
•See Note 6
Bo
16.0 ± 0.3
Ao
Ko A
12.0
Section A-A
Advance Information
Tape and Reel Information
A0 B0 K0 Unit Notes
1. 10 sprocket hole pitch cumulative tolerance ±0.2

2. Camber not to exceed 1mm in 100mm
3. Material: PS + C
4. A0 and B0 measured as indicated
8.30 8.30 1.10 mm
5. K0 measured from a plane on the inside bottom of
the pocket to the top surface of the carrier
6. Pocket position relative to sprocket hole measured
as true position of pocket, not pocket hole
18.3 Reel Information

102.0 Detail "A"
ATTENTION
Electrostatic Sensitive Devices
a(rim height) 2.0
Safe Handling Required
20.2
330.0 88 REF
2.0 MIN
"A" 13.0 +0.5

-0.2
"b" REF 2.0 0.5
6 6
PS
Detail "B"
PS
(MEASURED AT HUB) W1
(MEASURED AT HUB) W2
Figure 18.2: Reel Dimensions
Nominal Hub
Package Type Width a b W1 W2 Max Units
(Tape Width)
8 x 8 x 0.9mm 16.4
16 4.5 98.0 19.1 mm
QFN (3.0/-0.2)
18.4 Moisture Sensitivity Level

BlueTunes ROM QFN is qualified to moisture sensitivity level MSL3 in accordance with JEDEC J-STD-020.
Advance Information
Document References
19 Document References
Document Reference, Date
BlueCore5 Charger Description and Calibration

CS-113282-ANP, 2007
Procedure Application Note
BlueCore5-Multimedia External Recommendations for

CS-114058-ANP, 2007
ESD Protection
Bluetooth and IEEE 802.11 b/g Co-existence Solutions

bcore-an-066P, 2005
Overview
BlueTunes ROM QFN Performance Specification CS-122327-SPP, 2008
Core Specification of the Bluetooth System v2.1 + EDR, 2007

IC Packing and Labelling Specification CS-112584-SPP, 2007
Moisture / Reflow Sensitivity Classification for

IPC / JEDEC J-STD-020
Nonhermitic Solid State Surface Mount Devices
Optimising BlueCore5-Multimedia ADC Performance

CS-120059-AN, 2008
Application Note
Selection of I2C EEPROMS for Use with BlueCore bcore-an-008P, 2003
Test Suite Structure (TSS) and Test Purposes (TP)

RF.TS/2.1.E.0, 2006
System Specification 1.2/2.0/2.0 + EDR/ 2.1/2.1 + EDR
Typical Solder Reflow Profile for Lead-free Devices CS-116434-ANP, 2007
Advance Information
Terms and Definitions

Term Definition
8DPSK 8 phase Differential Phase Shift Keying
π/4 DQPSK π/4 rotated Differential Quaternary Phase Shift Keying
ACL Asynchronous ConnectionLess
ADC Analogue to Digital Converter
ADPCM Adaptive Differential Pulse Code Modulation (e.g G.726)
AFH Adaptive Frequency Hopping
AGC Automatic Gain Control
AuriStream CSR proprietary ADPCM codec
BCCMD BlueCore Command
BCSP BlueCore Serial Protocol

BlueCore® Group term for CSR’s range of Bluetooth wireless technology ICs
Bluetooth® Set of technologies providing audio and data transfer over short-range radio connections
BMC Burst Mode Controller
codec Coder decoder
CRC Cyclic Redundancy Check
CVSD Continuous Variable Slope Delta Modulation
DAC Digital to Analogue Converter
DC Direct Current
DSP Digital Signal Processor
EDR Enhanced Data Rate
eSCO Extended SCO
ESR Equivalent Series Resistance
etc et cetera, and the rest, and so forth
FEC Forward Error Correction
FHS Frequency Hop Synchronisation
FSK Frequency Shift Keying
GFSK Gaussian Frequency Shift Keying
GSM Global System for Mobile communications
H4DS H4 Deep Sleep
HCI Host Controller Interface
HEC Header Error Check Correction
IIR Infinite Impulse Response (filter)
IQ In-Phase and Quadrature
I/O Input/Output
I2C Inter-Integrated Circuit
IF Intermediate Frequency
LC Link Controller
LC An inductor (L) and capacitor (C) network
LED Light-Emitting Diode
LM Link Manager
LMP Link Manager Protocol
Advance Information
Term Definition
LNA Low Noise Amplifier
MAC Medium Access Control
MCU Micro Controller Unit
MIPS Million Instructions Per Second
MMU Memory Management Unit
NSMD Non Solder Mask Defined
PA Power Amplifier
PIO Programmable Input Output
RAM Random Access Memory
RF Radio Frequency
RISC Reduced Instruction Set Computer
RoHS Restriction of Hazardous Substances in Electrical and Electronic Equipment Directive

(2002/95/EC)
RSSI Received Signal Strength Indication
SBC Sub-band Coding
SCO Synchronous Connection-Oriented
SNR Signal-to-Noise Ratio
TBD To Be Defined
UART Universal Asynchronous Receiver Transmitter
VCO Voltage Controlled Oscillator
VM Virtual Machine
W-CDMA Wideband Code Division Multiple Access
Advance Information

Features: - Äìéqìåéë Olj NCK

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Features _äìÉqìåÉë∆=olj=nck

■ Cost-effective single-chip solution for stereo _äìÉqìåÉë=olj=píÉêÉç=eÉ~ÇëÉí=pçäìíáçå

_äìÉqìåÉë=olj=nck Data Sheet

General Description Applications

_äìÉqìåÉë=olj=nck Data Sheet

_äìÉqìåÉë=olj=nck Data Sheet

_äìÉqìåÉë=olj=nck Data Sheet

9.2 Serial Peripheral Interface ................................................................................................................... 31

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13.3.12 Auxiliary ADC ......................................................................................................................... 62

_äìÉqìåÉë=olj=nck Data Sheet

Figure 16.2 BlueCore HCI Stack ........................................................................................................................ 68

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Radio Kalimba DSP

_äìÉqìåÉë=olj=nck Data Sheet

2 Functional Block Diagram

_äìÉqìåÉë=olj=nck Data Sheet

_äìÉqìåÉë=olj=nck Data Sheet

3.2 Device Terminal Functions

XTAL_IN 3 For crystal or external clock input

XTAL_OUT 4 Drive for crystal

_äìÉqìåÉë=olj=nck Data Sheet

SPI Interface Lead Pad Type Supply Domain Description

Input, with weak internal pull-

Bidirectional with weak

Bidirectional with weak

UART Interface Lead Pad Type Supply Domain Description

Output, tri-state, with weak

Bidirectional with weak

CMOS input with weak

PIO Port Lead Pad Type Supply Domain Description

PIO[9] 14 Bidirectional with

_äìÉqìåÉë=olj=nck Data Sheet

PIO[2] 59 Bidirectional with

Audio Lead Pad Type Supply Domain Description

Speaker output, negative,

Speaker output, positive,

Speaker output, negative,

Speaker output, positive,

Microphone input, negative,

_äìÉqìåÉë=olj=nck Data Sheet

Microphone input, negative,

Microphone input, positive,

Decoupling of audio reference,

LED Drivers Lead Pad Type Supply Domain Description

LED[1] 33 LED driver

Test and Debug Lead Pad Type Supply Domain Description

Reset if low. Input debounced so

Low-voltage linear regulator and low-voltage audio

VREGIN_L 1 Input to internal low-voltage regulator

VREGENABLE_H 35 Switch-mode regulator enable, active high

VREGIN_AUDIO 46 Input to internal audio low-voltage linear regulator

VDD_AUDIO 47 Positive supply for audio

LX 37 Switch-mode regulator output

Positive supply output for analogue circuitry and

_äìÉqìåÉë=olj=nck Data Sheet

VDD_PIO 62 Positive supply for digital input/output ports PIO[3:0]

Positive supply for all other digital input/output ports

VDD_CORE 17, 34 Positive supply for internal digital circuitry