Dilip K, et. al.

International Journal of Engineering Research and Applications

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ISSN: 2248-9622, Vol. 11, Issue 7, (Series-V) July 2021, pp. 32-41

RESEARCH ARTICLE OPEN ACCESS

Design and Verification of AHB Protocol Using System Verilog

and Universal Verification Methodology (UVM)
Dilip K*, Vijaya Prakash A M*
* M.Tech, Department of ECE, Bangalore Institute of Technology, Karnataka, India
* Professor Department of ECE, Bangalore Institute of Technology, Karnataka, India

ABSTRACT :
Recently, VLSI technology has improved significantly and more transistors can be incorporated in a chip. A
System on-Chip (SOC) Configuration have number of blocks are integrated on a single chip. Numerous blocks
are integrated in single IC, but to access their function, they requires a powerful communication architecture.
This can only be achieved by using on-chip bus architecture to meet their requirements. Different Companies
has various on-Chip Bus architectures but one of the most suitable architecture is AMBA by ARM. AMBA
consist of three buses, namely, Advanced System Bus (ASB), Advanced Peripheral Bus (APB) and Advanced
High Performance Bus (AHB).when compared to other two buses AHB is high performance, high bandwidth
and for high clock frequency system modules the System designers select AHB as their primary choice. The
AHB (Advanced High-performance Bus) is a superior bus in AMBA (Advanced Microcontroller Bus
Architecture) family. It is a norm for intercommunication of modules in a framework. The AHB (Advance High
performance) bus Standards are characterized by ARM which supports for the communication of on-chip
memories, processors and interfaces of external off-chip memory. Here the basic blocks such as master, slave,
decoder, and arbiter are used to design and verify an AHB that supports multiples master and multiples slave.
The conventional way of verification is simulation based. As the Technology improves the complexity of IC’s
has been increased. Thus, time spent on verification has also been increased. The main focus is to design of
AHB protocol in Verilog and verify using Hardware verification language such as System Verilog and standard
Methodology such as Universal Verification Methodology (UVM). QuestaSim (Advanced verification tool from
Mentor Graphics) is an EDA tool used to simulate and verify the design and obtain Coverage report.
Keywords – AMBA, AHB, APB, ASB, OCB, SOC, UVM
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Date of Submission: 10-07-2021 Date of Acceptance: 26-07-2021
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used for optimizing power consumption. AMBA is
I. INTRODUCTION the Standard bus-based microcontroller typical
1.1 About AMBA bus feature a high-performance system hub bus (AHB or
The AMBA is an Advanced ASB) that supports for external memory bandwidth,
Microcontroller Bus Architecture defined by ARM, including CPUs, on-chip memories, and other direct
it is an open standard widely used for an on-chip bus data access (DMA) devices. For most of the
system. The standard is intends to simplify the transmission between various units, such as CPUs,
component design by allowing the use of on-chip memories, and DMA, the bus serves as a
interchangeable parts the within the SoC style. It high bandwidth interface.
promotes the use of holding parts, so that a
minimum of a neighborhood of the SoC can be
reconstructed, instead of having to rewrite it entirely
each time. AHB (Advanced High-performance Bus),
ASB (Advanced System Bus), and APB (Advanced
Peripheral Bus) are the bus groups defined in the
AMBA AHB. The AHB is employed for high-
performance, high frequency architecture. These
applications includes are ARM cores and high-speed
RAM inside the system, Nand Flash, DMA and
Bridge links. [1] The APB is used for connecting
external devices such as UART, keypad and timer,
and has low performance requirements, while it is

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design, all bus masters transmit address and control

signals indicating the data transfer they want to
perform and the arbiter determines which master has
its address and control signal based on that
information it is provided to all of the slaves. The
decoder is used to control the read data and response
signal from multiplexer, which chooses the proper
signals from the slave that is engaged in the transfer.

II. LITERATURE REVIEW

Design and verification of AMBA AHB
bus which consist of one master and multiple slave
designed in Verilog Hardware descriptive language
Fig.1: AMBA bus Block Diagram and shown the output for read and write operation.
[1] The Design under test is verified using the
1.2 Advance System Bus (ASB) system Verilog environment and obtained the
The ASBs (Advanced system buses) are coverage report around 65%.This paper tells us the
used for defining high performance buses that can be coverage report obtained is less. The Questa sim is
used in embedded microcontrollers with 16-bit and the EDA tool used to obtain the simulation output.
32-bit architecture. An ASB provides a high The paper presents a Method for Designing
performance pipelined bus that can provide access to an efficient[2] master interface and slave interface
multiple masters. The Flow of essential operations of based on the finite state machines in Verilog
ASB is: hardware description language and used the Mentor
• Master communicates with the bus. graphics tool Model sim 10.03a to simulate and the
• Arbiter observes master’s status. synthesis of the design is performed in Xilinx ISE
• Then, master begins communicating with the bus. design tool. The completed AMBA AHB system is
• The decoder uses the accurate address lines to then inspected for proper lossless communication
choose a bus slave. between master and slave interface. This article tells
• Then, a signal is given back to the bus master by us does not used the verification language such as
the slave. system Verilog.
In this the efficient design of an AMBA
1.3 Advance Peripheral Bus (APB) controller is designed and tested [3] for read and
The Advanced Peripheral Bus (APB) is
write operations using a Xilinx simulator. The read
utilized for connecting low bandwidth peripherals.
and write operations using AMBA are illustrated
APB is a simple non-pipelined protocol that can be
with simple examples.
utilized to communicate from a master to a multiple
As reported in paper [4], The AHB master
slaves for read and write through the shared bus. [5]
interface and arbiter interface are designed using the
The read and write bus shares the same set of signals
finite state machines in Verilog hardware description
and no burst data transfers are supported.
language and the design is simulated with the help of
Questa Sim. AMBA AHB system is then tested to
1.4 Advance High Performance Bus (AHB)
ensure that the master and the slave interfaces
An AHB bus is a latest generation of
communicate in the lossless manner
AMBA bus that is intended to handle the necessities
addresses the prerequisites of high performance The above review tell about the most of the
synthesizable design styles. It is a Standard system related work is on the Verilog hardware descriptive
bus that supports multiple bus masters and provides language and the more work to be done in the
high-bandwidth operation. AMBA AHB implements verification. The present work use the verification
the features needed for standard, high clock language such as system Verilog and standard
frequency systems including: methodology such as UVM (universal verification
• Burst transfers. methodology).
• Single-cycle bus master relinquishing.
• Single-clock edge operation. III. DESIGN METHODOLOGY
• Non-tristate implementation. The Design under Test (DUT) Block
• Wider information bus configurations (32/128 diagram consist of multiple masters and slaves. The
bits). masters are namely m1, m2, and m3 and slaves are
The AMBA AHB bus protocol is designed using a namely s1, s2, and s3. The master as address and
central multiplexer interconnection design. By control signals such as HADDR, HTRANS,

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HBURST and HSIZE. Slave as address and control

signal such as HADDR, HREADY and HRESP. The
block diagram of DUT as the blocks such as master,
slave, decoder and arbiter. The Arbiter consist of
both decoder and multiplexer.
Initially the master as the data_1, data_2,
and data_3 each masters as the data and it is driven
by address and control signals. At the output of
master block the HWDATA_tb1, HWDATA_tb2
and HWDATA_tb3 are the write data transactions
obtained when wr=1; then the write data is send to
multiplexer based on the address on the decoder.
The arbiter perform the operation such that it does
not allows the masters to send the data to same slave
at a particular time for the particular address it
allows master m1 as the write data HWDATA_tb1 is
send to slave i.e. HSEL1, then the slave1 read the
data, rddata1 and send the response signal HRESP1
to the m1 through slave multiplexer based on the
address on the decoder that it complete the
transaction of data when m1 receive the response. Fig.2: AHB multi master and slave DUT
For the next particular transaction the
initial three master m1, m2 and m3 as the data_1, 3.1 Components of AHB
data_2 and data_3 are send and obtained the The AHB bus as four components namely
HWDATA_tb1, HWDATA_tb2 and HWDATA_tb3
as the write data transactions, now the arbiter is 3.1.1 AHB Master
allows the m1 and m2 write data to transfer and the 3.1.2 AHB Slave
write data is read by the slaves i.eHSEL1 and 3.1.3 AHB Arbiter
HSEL2 when the wr=0 and obtained the output 3.1.4 AHB decoder
rddata1, rddata2, and the slave as HRESP signal 3.1.1 AHB Master
which goes high and additional HREADY signal The AHB bus master initiate the
indicates that the transaction of rddata1 and rddata2 read/write operations by providing address and
are completed and ready to receive the other data. control information. The maximum of 16 masters are
For the next transaction the initial three allowed in our design we are using 3 masters.
master m1, m2 and m3 as the data1, data2 and data3
are send and obtained the HWDATA_tb1
,HWDATA_tb2 and HWDATA_tb3 as the write
data transactions, now the arbiter allows the m1 , m2
and m3 write data to transfer and the transaction
write data is read by the slaves i.eHSEL1 , HSEL2
and HSEL3 when the wr=0; and obtained the output
rddata1 , rddata2 and rddata3, and the slave as
HREADY signal indicates that the transaction of
rddata1 , rddata2 and rddata3 are completed and
ready to receive the other data from the masters.

Fig.3: AHB Master

 HRESETn: The bus reset signal it is used to

reset the system and the bus.
 HCLK: The clk is used for all bus transfers.
 HADDR [31:0]: The 32-bit address bus.

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 HTRANS [1:0]: Indicates the type of HSIZE HSIZE HSIZE Size Description
transfer such as idle, busy, sequential and non- [3] [2] [0] (bytes)
Sequential. 0 0 0 1 Byte
0 0 1 2 Half word
0 1 0 4 word
Type Description Table.2: HSIZE type
HTRANS
Master uses the idle  HBRUST [3:0]: Indicates Type of burst
transfer when it does operation such as fixed type, increment type and 4-
not wish to perform beat wrap and 4-beat increment type [6]
Idle the data transfer the .
00 slave must ignore HBURST[2:0] Type Description
the data by sending b000 Fixed/Single Fixed burst
the OKAY response b001 Single INCR Increment
to the master type
The busy transfer b010 WRAP4 4-beat
type used to insert wrapping
the idle cycle in burst
between the burst b011 INCR 4-beat
01 Busy and the master Increment
address and control burst
reflect in the next Table.3: BURST type
burst transfer the
slave must provide  HWDATA [31:0]: The write data bus
the zero OKAY which is used to transfer the data from master to the
state response to the slave during write operation.
master
The address and 3.1.2 AHB Slave
11 Non control signal is not The AHB slave response to the transfer
sequential related to previous given by the master and the decoder is used to select
transfer and it of the slave based on the HSELx signal it is the slave
single burst type or signal used to select the slaves and the response is
fixed type burst send to the master based on HRESP. There are two
The remaining types of response given to the master if the data is
transfer of burst is successfully read by the slave it give OKAY
related to sequential response for the slave if it unsuccessful it provide
10 sequential the address and ERROR response.
control signal is
related to previous
and based on the
HSIZE[2:0] and
burst operation such
as wrap and
increment
Table.1: HTRANS Types

 HWRITE: when this signal is low indicate

the read Transfer and when it is high indicates the
write transfer.
 HSIZE [2:0]: indicate the size of transfer
such as
Byte (8-bit), half-word (16-bit), word (32-bit) Fig.4: AHB Slave
etc.
 HRDATA [31:0]: The read data bus which
is used to read the data from the master when
HWRITE is low.

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 HREADY: when the HREADY signal is IV. VERIFICATION

high indicates theat the transfer is finished by the METHODOLOGY
slave Verification is the significant part in the
 HRESP : it is response given to the if the VLSI technology. Since it is used to find out the
response is zero then the slave as completed the bugs in the RTL design at the initial stage so the
transfer of data and indictes okay signal and if it is overall Design should not prove any error. Here we
one indicates error in the transfer. creating a System Verilog Environment and
 HREADYOUT: output of slave indicate the Universal verification methodology (UVM)
status of transfer. Environment for an AHB design. The main intention
of creating verification environment is to generate
3.1.3 AHB Arbiter the stimulus to the Design under test (DUT), and
check the results to verify that the DUT function is
correct.
4.1 System Verilog Environment
System Verilog is a Hardware Description
language (HDL) and Hardware Verification
Language (HVL) based on Verilog. While it has few
features to help with design, the purpose of language
is to verify of electronic designs. [7] Open Vera, a
language denoted by Synopsys, provides the
majority of verification functionality. System
Verilog as the IEEE standard P1800-2005.
System Verilog is a special hardware
Fig.5: AHB Arbiter verification language and Hardware verification
language intended to be used in function
The arbiter controls the three master write verification. It is used to provide the high level data
data such as HWDATA_tb1, HWDATA_tb2 and Structures accessible in object-oriented languages,
HWDATA_tb.It operation is to control the master such as C++. The data structures empower a higher
data such way that different master data should not level of abstraction and modeling of complex data
Send to thesingle slave. types. The System Verilog also as constructs
necessary for modeling hardware concepts such as
3.1.4 AHB Decoder cycles, tri-state values, wires, same like Verilog
The below Figure 6 shows the AHB hardware languages. System Verilog can be used to
decoder The AHB slave has its own slave select simulate and verify the Verilog HDL design by
signals i.e HSEL1, HSEL2, HSEL3 and this signal applying the high level of test input as it is known to
indicates that the transfer is particularly for the be Hardware verification language (HVL). The
selected slave. This slave select signal is selected system Verilog as the test bench architecture which
based on the address of the decoder .Then the consist of component such as basepkt, generator,
transfer data is read by the slave and send the driver, monitor and scoreboard.
response to the particular master and ready signal
goes high for that transfer of data. If the response is
low indicates okay transfer. If the responsre is high
indicates errror transfer.

Fig.6: AHB Decoder Fig.7: System Verilog Environment

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The above Figure7 shown is a System

Verilog environment. The Environment includes
Design under test (DUT) written in Verilog
Hardware descriptive language (HDL) and System
Verilog test bench that includes System Verilog
interface, simulation module and test program. In
system Verilog test bench, the basepkt contains the
all input and output are send as a packet through
mailbox to generator. The generator is utilized to
create constrained random test vectors. These
vectors are sent to the driver, and then through
interface can simulate the DUT. A monitor generates
verification reports for each state, transaction, and
model message. Using the Scoreboard to checks the
results of the driven and the monitor driving them
through mailboxes any changes in the modifications Fig.8: UVM Environment
that need to be done. The development of coverage
class based on the coverage plane and we will apply Sequence item: Using the uvm_sequence_item
the test cases and analyze the code coverage report. class, the transactions are extended to send the
System Verilog advantage is to use of object randomized data to a driver to be driven onto the
oriented programming, which enables the reusability bus. The field automation macros are applied to
of test bench components. The interface is used to these members of the class as well.
combine the DUT and the System Verilog test bench Sequences: A sequence is a bulk of transaction. In
which includes the test program. the sequence class, the users can make complex
4.2 Universal Verification Methodology (UVM) stimulus. This sequences can be randomized,
System verilog is a Hardware descriptive extended to make another sequence and can be
and Hardware verification language just like verilog combined.
and has its particular constructs, syntax and features. Sequencer: The data flow between Sequences and
But universal verification methodology is a structure driver is signaled by the sequencer verification
of system verilog classes from which we can built component. The sequencer has a collection of
fully functional test benches. The RTL (Register sequences combined with it called a sequence
transfer level) design is verified using the Standard library. The collection of sequences utilized by a
Methodology such as Universal Verification sequencer is called sequence library. This type of
Methodology. It comprises of base class library component is also known to as a driver sequencer.
coded in System Verilog. [7] The verification Driver: Driver collect the object from the sequencer
engineer can make different verification components and drives it to the next lower level such as DUT
by extending these classes. Additionally, UVM (Design under Test) through the interface. It is
provides several useful verification features such as generated by extending the uvm_driver.
utilizing of macros for implementing complex Monitor: monitor samples the DUT signals through
functions and factories for creating the objects. The the Virtual interface signals are converts into packet
below Figure 8 is a UVM environment. The level which is then sent to other components, such as
environment includes interface and DUT with test scoreboards for the analysis. It was generated by
bench. The test bench environment consist of agent, extending the uvm_monitor.
sequencer, and driver and monitor as sub Agent: The agent consist the verification
components. components such as driver, monitor, collector and
sequencer. It used to connect these components
using TLM connections. The agent as one of the
operating modes active or passive. In the active
mode of operation, the agent initiate driver,
sequencer and monitor where as in the passive mode
of operation initiate only monitor and configured
Environment: The Environment class consist all the
sub components such as agents, driver and monitor
etc. and configures them.
Testbench: The uvm_test class defines the test cases
for the test bench specified in the test. The Different
test cases is applied to enable the configuration of

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the test bench and verification components. The

uvm_test is written by extended from the
uvm_component.

V. RESULTS AND DISCUSSION

5.1 Master1 to Slave1 data transfer
The Figure 9 show below shows the
simulation output for master1 to slave1 data transfer.
When reset is high the master data is send to the
input of the arbiter. The arbiter comprises of both
decoder and multiplexer based on that arbiter filters
the other master write data and allows for the
master1 to send the data to the slave1 (HSEL1). The
slave1 read the data and obtain the output rddata1.
When slave1 complete the transfer of data. The
response signal goes low indicating to master that
the slave as completed the transfer of data and it is Fig.10: Simulation Result for Activation of Multiple
ready to accept the other data by indication the Slaves
HREADY signal high.
Figure 11 shown below shows the
simulation result for data transfer from multiple
master to multiple slave the arbiter allows the
multiple master to transfer the data to multiple slave
it control the master write data to send for the
particular slave without any mismatching of data.
The control and address related to slave will sends
the signal to the master after transferring of data.

Fig.9: Master1 to Slave1 data transfer

5.2 Multi master to Multi slave data transfer

When reset is high the master data is send
to the input of the arbiter. The arbiter consist of both
decoder and multiplexer based on that the arbiter
filter it allows the masters to transfer the data to the
particular slaves the Figure 10 shows simulation
result for activation of multi slaves. Fig.11: simulation result for multi master and multi
slave

5.3 Simulation result for burst Operation

Figure 12 shows the wrap 4 burst operation
(HBRUST=b010). The address bus get wrapped
when it reach it boundary size. The wrap4 burst
operation depends on the HSIZE (010=2). i.e. the
wrap4 as 4-beat each beat depend on the size of
transfer below figure we taken the size type word i.e.
the word as 4 bytes now 1-beat takes 4 bytes for 4-
beat it takes 16-bytes of data and address is wrapped

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when it reached maximum. Initial transfer of burst as 5.4 System Verilog top module waveform
transfer type non sequential (11) is given for stating
single burst later for next transfer sequential (10) is
related to the previous address and next burst
operation continuous sequentially when it each
address boundary again the address get wrapped to
initial boundary.

Fig.14: System Verilog Test bench Environment

Figure 14 shows the system Verilog top module

waveform for multiple master and multiple slave.

5.5 Code coverage Report

Fig.12: WRAP4 Burst operation

Figure 13 shown below shows the

increment type of burst operation (HBRUST=b011)
the incr4 is type of burst operation with the HSIZE
(010) word size of 4 bytes and the address is
increment gradually based on the size of the bytes
and each address as the data is stored in the
particular address the data are stored in the each
address. The figure shows multi master and multi
slave increment 4 type of burst operation.
Fig.15: Coverage report

Fig.13: INCR4 burst operation

Fig.16: cover point analysis report

Figure 15 and 16 shows the coverage report

and Cover point analysis Report. The coverage
report gives information about statement, Toggle
and coverage group it includes both code coverage
and Function coverage. The cover point analysis

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report it is basically a functional coverage report. The AHB bus is designed which supports for
The bins are created based on the constraints. And multiple masters and slaves. Which consist of basic
applied the test cases if they met then that blocks such as master, slave, decoder and arbiter.
functionality is said to be hit or covered. Here the The AHB design Block is designed using Verilog
overall coverage report obtained is 100%. HDL and verified using the system Verilog and
Universal verification methodology. The Tool used
5.6 UVM top module waveform is Questa sim is an EDA tool used to simulate and
verify the design and obtained the coverage report.
Which says that the functionality is correct. The
UVM report summary also ensure that functional
Correctness of the design. In the present work we
have designed AHB which support for 3 master and
3 slaves. Developing the design which can support
for 16 master and 16 slaves could be the future work
of this project design.

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Dilip K, et. al. “Design and Verification of AHB Protocol Using System Verilog and Universal
Verification Methodology (UVM).” International Journal of Engineering Research and
Applications (IJERA), vol.11 (7), 2021, pp 32-41.

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