LOMBOK/CAICOS/CEDAR TMDP A&B DP/HDMI OVERLAP OPTIONAL ESD protection diodes

U1I GPU(215-0804070-00)

+1.8V
PART 9 OF 15
B2503
+DPAB_VDD18
D1603
1 2 AG8 DPA_PVDD
120R
D1600 DPB_AUXN 8
DPB_3N 1 A DNI Y1 10 DPB_3N
8

1
AK3 DPB_3P 2 9 DPB_3P
TX2P_DPA0P 8 B Y2 8
C2509 C2510 C2511 D1601 DPB_AUXP 3 8
GND GND1
4.7uF 1uF 0.1uF AK1 DPB_2N 4 7 DPB_2N
TX2M_DPA0N 8 C Y3 8
6.3V 6.3V 10V
DNI AG7 DPA_PVSS D1602 DPB_DONGLE_DET 8
DPB_2P 5 D Y4 6 DPB_2P
8

2
TX1P_DPA1P AH3
D1605 HPD_DPB RCLAMP0524P
TX1M_DPA1N AH1

D1604
Please pay attention to the grounding TX0P_DPA2P AG3 DPB_1N
strategies for these filter capacitors to AG10 1 10 DPB_1N
DPB_PVDD 8 A DNI Y1 8
maintain a close loop for current. DPB_1P DPB_1P
TX0M_DPA2N AG5 8 2 B Y2 9 8
3 GND GND1 8
AF2 DPB_0N 4 7 DPB_0N
TXCAP_DPA3P 8 C Y3 8
DPB_0P 5 6 DPB_0P
8 D Y4 8
AG11 DPB_PVSS TXCAM_DPA3N AF4

RCLAMP0524P

+1V B2505
1 2 +DPAB_VDD10 AF6 DPA_VDD10
120R AF7 DPA_VDD10

1
C2515 C2516 C2517

4.7uF 1uF 0.1uF

6.3V 6.3V 6.3V

2
T
AF8 DPB_VDD10 M
AF9 D
DPB_VDD10
P
A
/
B

AE11 DPA_VDD18
AF11 DPA_VDD18 J1601

DP
DPB_A0P C1630 1 20.1uF 6.3V 8 DPB_0P 1
8 ML_Lane_0p GASKET DP
AK8 DPB_A0P DP 2
TX5P_DPB0P 8 GND_0 1st source:NTK 6140073700G
DPB_A0N C1631 1 20.1uF 6.3V 8 DPB_0N 3
8 ML_Lane_0n
AL7 DPB_A0N DP
TX5M_DPB0N 8
AE13 DPB_A1P C1632 1 20.1uF 6.3V 8 DPB_1P 4
DPB_VDD18 8 ML_Lane_1p
DPB_A1P DP
AF13 DPB_VDD18 TX4P_DPB1P AJ7 8 5 GND_1
DPB_A1N C1633 1 20.1uF 6.3V 8 DPB_1N 6
8 ML_Lane_1n
AH6 DPB_A1N DP
TX4M_DPB1N 8
DPB_A2P C1634 1 20.1uF 6.3V 8 DPB_2P 7
8 ML_Lane_2p
AK6 DPB_A2P DP 8
TX3P_DPB2P 8 GND_2
DPB_A2N C1636 1 20.1uF 6.3V 8 DPB_2N 9
8 ML_Lane_2n
R2500 1 2 150R 1% DPAB_CALR AE10 AM5 DPB_A2N DP
DPAB_CALR TX3M_DPB2N 8
DPB_A3P C1637 1 20.1uF 6.3V 8 DPB_3P 10
8 ML_Lane_3p
AK5 DPB_A3P DP 11
TXCBP_DPB3P 8 GND_3
DPB_A3N C1638 1 20.1uF 6.3V 8 DPB_3N 12
8 ML_Lane_3n
AE1 AM3 DPB_A3N DP
DPA_VSSR TXCBM_DPB3N 8
AE3 DPA_VSSR 13 CONFIG 1
AG1 R1624 1 DP 2 1M DPB_1M 14
DPA_VSSR CONFIG 2
AG6 DPA_VSSR
AH5 DPA_VSSR 8 DPB_AUXP 15 AUX_CHp
AF10 DPB_VSSR R1622 1 DP 2 100K 16 GND_6
AG9 8 DPB_AUXN 17
DPB_VSSR AUX_CHn
AH8 DPB_VSSR R1623 1 DP 2 100K
+3.3V_BUS
AM6 DPB_VSSR 6 DDCCLK_AUX5P C1635 1 20.1uF 6.3V 18HPD_DPB Hot_Det G4 G4
IN DP +3.3V_BUS
AM8 DPB_VSSR F1601 G3 G3
DP
DDCDATA_AUX5N C1641 1 20.1uF 6.3V 1 2 +3.3V_DPB 20 G2
6 BI
DPB_AUXN DP_PWR G2
DP 19 G1
1.5A PWR_RTN G1

1
CEDAR PRO A11P HF MVE SLT BIN1 TSMC FB12
C1640 R1626
Q1601B 5.1M
22uF DP DP_W/GASKET
2N7002DW 6.3V
DP 8 DP

2
HPD_DPB
MR1628 1
DP 2 0R 1 UNNAMED_7_MOSN_I122_S 6 UNNAMED_7_MOSN_I122_D PR1628 1
DP 2 0R DPB_AUXP

+12V_BUS +12V_BUS
Q1601A
2N7002DW
DP +3.3V_BUS

1
MR1629 1DP 2 0R 4 UNNAMED_7_MOSN_I123_S 3 PR1629
UNNAMED_7_MOSN_I123_D
1
DP 2 0R 8 DPB_DONGLE_DET
R1805
R1604 10K

3
10K DP
DP Q1613 1 R1627
UNNAMED_7_NPN_I155_B
1DP 2 10K

2
DPB_AUX_BYPSS_EN MMBT3904
DP

UNNAMED_7_MOSN_I114_D
Q1603

2
3

3
MMBT3904 GPIO_14_HPD2
DP Q1604 6 OUT
1 2N7002E
DP

1
1 DPB_DONGLE_DET
R1630

2
10K
DP

2
OVERLAP HDMI WITH DP D
 LOMBOK/CAICOS/CEDAR LVTMDP E&F dDVI-I
U1K GPU(215-0804070-00)

PART 11 OF 15

+1.8V B1500
1 2 UNNAMED_10_BEAD_I15_B
AG18 AH18 DPF_A0P C2530 1 20.1uF 6.3V DPF_0P
DPE_PVDD T2X2P_DPE0P 10 10
HDMI
120R

1
AJ17 DPF_A0N C2531 1 20.1uF 6.3V DPF_0N
DNI T2X2M_DPE0N 10 10
C1500 C1501 C1502 HDMI

4.7uF 1uF 0.1uF AL17 DPF_A1P C2532 1 20.1uF 6.3V DPF_1P

T2X1P_DPE1P 10 10
6.3V 6.3V 10V HDMI
AF19 DPE_PVSS

2
AK16 DPF_A1N C2533 1 20.1uF 6.3V DPF_1N
T2X1M_DPE1N 10 10
HDMI

AH16 DPF_A2P C2534 1 20.1uF 6.3V DPF_2P

T2X0P_DPE2P 10 10
HDMI

AJ15 DPF_A2N C2536 1 20.1uF 6.3V DPF_2N

T2X0M_DPE2N 10 10
AG19 HDMI
DPF_PVDD
AL15 DPF_A3P C2537 1 20.1uF 6.3V DPF_3P
Please pay attention to the grounding T2XCEP_DPE3P 10 10
strategies for these filter capacitors to
HDMI
maintain a close loop for current. AK14 DPF_A3N C2538 1 20.1uF 6.3V DPF_3N
T2XCEM_DPE3N 10 10
HDMI

AF20 DPF_PVSS +5V_VESA R2701 1 HDMI 2 2.2K

R2703 1 HDMI 2 2.2K

DPF_AUXP
10
+1V
B1502 +DPEF_VDD10
1 2 AG20 DPF_AUXN
DPE_VDD10 10
120R AG21 DPE_VDD10
1

1
C1506 C1507 C1508 DDCCLK_AUX3P R2528 1HDMI 2 0R
6 IN
DPF_AUXP

4.7uF 1uF 0.1uF

6.3V 6.3V 10V
DNI L
2

2
V DDCDATA_AUX3N R2529 1HDMI 2 0R
T 6 BI
DPF_AUXN

AF22 DPF_VDD10 M
D Q1801B
AG22 DPF_VDD10 P 2N7002DW
HDMIMOS
E MR2528 1
HDMIMOS 2 0R 1 UNNAMED_10_MOSN_I55_S 6 UNNAMED_10_MOSN_I55_D
PR2528 1
HDMIMOS 2 0R
/
F +12V_BUS
Q1801A
2N7002DW
HDMIMOS +3.3V_BUS

1
AG15 DPE_VDD18 MR2529 1HDMIMOS 2 0R 4 UNNAMED_10_MOSN_I56_S 3 PR2529
UNNAMED_10_MOSN_I56_D
1
HDMIMOS 2 0R
AG16 DPE_VDD18 R1804

3
10K

HDMIMOS Q2513 1 R2527

UNNAMED_10_NPN_I88_B
1HDMI 2 10K HPD_DPF

2
DPF_AUX1_BYPSS_EN MMBT3904
HDMI

2
AL23 DPF_A0P HPD1
T2X5P_DPF0P 10 6 OUT
AF16 DPF_VDD18

1
AG17 AK22 DPF_A0N
DPF_VDD18 T2X5M_DPF0N 10
R2530
10K
AH22 DPF_A1P HDMI
T2X4P_DPF1P 10

2
+5V_VESA
AJ21 DPF_A1N
T2X4M_DPF1N 10
SHORT HDMI
R1500 1 2 150R 1% DPEF_CALR AF17 AL21 DPF_A2P
DPEF_CALR T2X3P_DPF2P 10
J2501
AK20 DPF_A2N DPF_0P 1 20
T2X3M_DPF2N 10 10 P1 CASE
2 P2 CASE 21
AG14 AH20 DPF_A3P DPF_0N 3 22
DPE_VSSR T2XCFP_DPF3P 10 10 P3 CASE
AH14 DPF_1P 4 23
DPE_VSSR 10 P4 CASE
AM14 AJ19 DPF_A3N 5
DPE_VSSR T2XCFM_DPF3N 10 P5
AM16 DPF_1N 6
DPE_VSSR 10 P6 HDMI
AM18 DPF_2P 7
DPE_VSSR 10 P7
AF23 DPF_VSSR 8 P8
AG23 DPF_2N 9
DPF_VSSR 10 P9
AM20 DPF_3P 10
DPF_VSSR 10 P10
AM22 DPF_VSSR 11 P11
AM24 DPF_3N 12
DPF_VSSR 10 P12
13 P13
14 P14
CEDAR PRO A11P HF MVE SLT BIN1 TSMC FB12

1 DPF_0N

1 DPF_1N

1 DPF_2N

1 DPF_3N
1 DPF_0P

1 DPF_1P

1 DPF_2P

1 DPF_3P
DPF_AUXP 15
10 P15
DPF_AUXN 16
10 P16
R2713 R2714 R2715 R2716 R2717 R2718 R2719 R2720 17
499R 499R 499R 499R 499R 499R 499R 499R P17
1% 1% 1% 1% 1% 1% 1% 1% 18 P18
HDMI HDMI HDMI HDMI HDMI HDMI HDMI HDMI HPD_DPF
10 19 P19

2
+12V_BUS

1
DPF_GND HDMI_W/TAB
C2722

1
1uF

3
R844 6.3V
HDMI

2
10K
HDMI

Q2701

2
TMDP_EN 1 2N7002E
HDMI

2
C843

0.1uF
16V
HDMI

2
OPTIONAL ESD protection diodes

D2503
D2500 DPF_AUXN
DPF_3N 1 10 DPF_3N
10 A DNI Y1 10
DPF_3P 2 9 DPF_3P
10 B Y2 10
D2510 DPF_AUXP 3 GND GND1 8
DPF_2N 4 7 DPF_2N
10 C Y3 10
DPF_2P 5 6 DPF_2P
10 D Y4 10
D2505 HPD_DPF
RCLAMP0524P

D2504
DPF_1N
1 10 DPF_1N
10 A DNI Y1 10
DPF_1P 2 9 DPF_1P
10 B Y2 10
3 GND GND1 8
DPF_0N 4 7 DPF_0N
10 C Y3 10
DPF_0P 5 6 DPF_0P
10 D Y4 10

RCLAMP0524P
 For 2-WIRE FAN ONLY

FANOUT_P
12

1
C4103
1uF
Fan Control
+12V_BUS
Mechanical and Thermal Management

2
FANOUT_N
12

1
B4001
U1N GPU(215-0804070-00) DVI/DVI SCREWS with top tab
26R

+1.8V PART 14 OF 15
This circuit provides a minimum voltage for the fan, +12V_BUS

2
T4 independent of PWM input -> check if needed for RV710

2 FANOUT_P
DPLUS

1
AD17 TSVDD

1
D1721 C4008
BAT54S
T2 R4105 C4403 1uF
C4020 DMINUS 1K DNI
1uF 16V
3 22uF 0805

2
16V
DNI

2
AC17 TSVSS +3.3V_BUS +12V_BUS
T Q4102

UNNAMED_115_PNP_I182_E
Q4101 JU4001
S

1
MMBT3906

2
S PWM_B MMBT3906 12 FANOUT_P 1

1
PFB 1 1 NFB R4107 1 2 820R 12 FANOUT_N 2
F

1
D R4100
2.61K

1
O 1% R4112 C4104 HEADER_1X2_SHROUDED

3
DNI 5.1K
DNI R4108 1uF R4110
Q4100

2
1M 0R

2
TS_FDO0 R4410 TS_FDO 2N7002E 16V
TS_FDO R5 1 2 1 DNI DNI

2
D4100
20K BAT54KFILM BU ONLY

2
1
DNI

2
1
R4409
CEDAR PRO A11P HF MVE SLT BIN1 TSMC FB12

1
20K
MR4104 DNI
10K

UNNAMED_115_RES_I177_A
DNI

2
4
2

1
Warning: TS_FDO is not 5V tolerant. MAX sink current 1.65mA R4113
6.8K
DNI VDIFF 1 Add Copper under pad 4
Q4103
PERST#_BUF 3 PBSS4350Z (at least 1cm^2)
2,3,12 IN D1720

3
1
BAT54S C4102
If Critical Temperature is reached this will force the fan to run at full

speed while power is removed from GPU & rest of the board. 1uF R4106

2
6.3V 1K
This is an open collector signal. Active level is hard pull down to ground.

2
footprints for
D4101 and

MD4101

Critial Temperature Fault

6
R4057 1 2 20K PWM_ENB 2 Q4010A
MMDT3904-7

1
+12V_BUS

1
C4402 R4063
100K
0.1uF DNI

1
16V
DNI

2
R4102
3K

2
R4103 1 2 10K

1
Place close to its CTLR
R4111 C4100 R4109
1K 1M
1% 1uF
DNI 16V

2
CTF2: R4051=20K, R4053 DNI, C4401=0.1UF; VDDC_EN
OUT 14,18

3
R4051 1 2 20K VDDC_ENB 5 Q4010B
MMDT3904-7

4
12 CTF_BYPASS C4401 R4053
R4062 1 DNI 2 0R
100K
0.1uF DNI
10V

2
+3.3V_BUS
1

Critial Temperature Fault R4407 J8 J9

20K
DNI
2

MMBT3906
Q4400 1 CTF2_GAT FM1 FM5
X_PIN1*2 X_PIN1*2 1 SW_FB 1 SW_FB
GND GND
3

CTF2_VCNTL R4406 1 2 0R 12 F_PAD_X F_PAD_X

MEM_Address MEM_DATA
BOTTOM TOP FM2 FM6
1

0.13MM / 45ohm +/- 5ohm 0.13MM / 50ohm +/- 5ohm 1 SW_FB 1 SW_FB
1

R4405
20K Reference L2,L3 Reference L2
1

R4408
1K
R4404
F_PAD_X F_PAD_X
2

20K
FM3
UNNAMED_115_NPN_I150_C

J11 J12 1 SW_FB

2

CTF2_RESET CTF2_TRIP 3 1 3 1
6
GPIO_19_CTF R4400 1 2 47K R4402 1 2 47K 1 Q4401
IN 4 2 4 2
MMBT3904 F_PAD_X
impedence impedence
2
1

GND GND GND GND FM4

R4403 C4400 1 SW_FB
100K
3 D4400 0.01uF
10V
MEM_CLOCK PEX_PCIE
2

BAT54S
BOTTOM TOP F_PAD_X
0.13MM / 0.18MM / 80ohm +/- 10% 0.11MM / 0.14MM / 85ohm +/- 10%
2

Reference L2,L3 Reference L2,L3

PERST#_BUF
2,3,12 IN

For HDMI Connector SCREW203

HDMI SCREW
Single-slot fansink 14W Single-slot fansink 17W
HS1DNI HS3 17WHS(71232811H0G) HDMITABSCREW;DPTABSCREW

SCREW
For VGA Connector

7120036200G 7123281100G

ASSY-SCREW202 ASSY-SCREW203

FANSINK
HS4A
25WHS(7122107700G) 25WHS(7122107700G) 25WHS(7122107700G)

HS4B HS4C HS4D 7020000800G 7020000800G

Rectangular Heatsink 8W

PCB
25WHS(7122107700G)
AMD
PCB
ASSY-SCREW200
Bracket Components

PCB(109-C98251-00A) MT200 MT201

SCREW

8020055300G
BK
9 16
17 25
24 32
BKTSCREW(7020005200G)
1
2
3
4
5
6
7
8

10
11
12
13
14
15

18
19
20
21
22
23

26
27
28
29
30
31

BRACKET
ASSY-SCREW201

1 8 1 8
2
3
4
5
6
7

2
3
4
5
6
7

SCREW

620NOPN029 620NOPN029

BKTSCREW(7020005200G)

BRACKET VGA+DP+HDMI
 8 7 6 5 4 3 2 1

TABLE OF CONTENTS

SHEET NO. SHEET NAME

D D
1 TOC

2 PCI-E Edge Connector

3 CAICOS PCIE

4 CAICOS MEM

5 GDDR5

6 CAICOS GPIO STRAP PLL

7 CAICOS DAC

8 CAICOS TMDP AB DP

9 CAICOS TMDP C (UNUSED)

10 CAICOS LVTMDP E&F HDMI

11 CAICOS Power&GND

12 Mech/Thermal Management

13 Debug Circuit

14 PWR SEQ

15 1V

16 1.8V

17 5V

C 18 VDDC C
19 MVDD

20 Diagram

21 REVISION HISTORY

GROUP NAME DESCRIPTION

COMMON INSTALLED IN MAIN BOM

NOPN NO PN,WON'T BE IN BOM
DNI DON'T INSTALL
INT INTERNAL BOM, WON'T BE IN PRODUCTION BOM
B GPU GPU PN
B
BK BRACKET
HS HEATSINK OR FANSINK
BACO BACO circuit
SUBBOM SUBBOM PN

SUB BOM
MEM MEMORY SUB BOM
DEBUG DEBUG SUB BOM

POWER SUB BOM

VDDC VDDC SUB BOM
VDDCI VDDCI SUB BOM
MVDD MVDD SUB BOM

CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.

AMD - PLATFORM HARDWARE ENG C 2014 Advanced Micro Devices

#48, No.1387, ZHANGDONG ROAD This AMD Board schematic and design is the exclusive property of AMD, and

A SHANGHAI, CHINA 201203 is provided only to entities under a non-disclosure agreement with AMD A
for evaluation purposes. Further distribution or disclosure is strictly

prohibited. Use of this schematic and design for any purpose other than

evaluation requires a Board Technology License Agreement with AMD.

AMD makes no representations or warranties of any kind regarding this

SHEET: TOC
schematic and design, including, not limited to, any implied warranty

of merchantability or fitness for a particular purpose, and disclaims

responsibility for any consequences resulting from use of the

DATE: Thu Jun 04 06:11:34 2015 REV: 1.0
information included herein.

SHEET NUMBER: 1 OF 21 TITLE:

Caicos G5 VGA+DP+HDMI 25W ASIC, 5.7"

DOCUMENT NUMBER: 105-C982xx-00A

NOTES: NOTE

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

PCI-EXPRESS EDGE CONNECTOR

D D

+3.3V_BUS +12V_BUS +12V_BUS

+3.3V_BUS

MPCIE1

B1 +12V#B1 PRSNT1#A1 A1 PRESENCE

2
B2 +12V#B2 +12V#A2 A2
B3 +12V#B3 +12V#A3 A3 +3.3V_BUS

B4 GND#B4 GND#A4 A4 System JTAG TDI and TDO are hard wired. +3.3V_BUS
B5 SMCLK see p. 20 for GPU JTAG connection

2
B6 SMDAT JTAG3 A6 JTDIO_LOOP

B7 GND#B7 JTAG4 A7
10K U4
B8 +3.3V#B8 R25
+3.3V#A9 A9 3 5 C1012 1 20.1uF 6.3V

1
A VCC
+3.3V#A10 A10 15 +1V_PG 1 4 PERST#_BUF 3,12
IN PERST#
B Y OUT
PERST# A11 6 GND 2
C
Mechanical Key

74AUP1G57GM
REFCLK+ A13 PCIE_REFCLKP
3 R1007 1 DNI 2 0R
OUT
PETP0_GFXRP0 B14 PETp0 REFCLK- A14 PCIE_REFCLKN Place R1007 in U4
3 OUT OUT 3
PETN0_GFXRN0 B15 PETn0 GND#A15 A15
3 OUT
PERp0 A16 PERP0
3
IN
PERn0 A17 PERN0
3
IN
B18 GND#B18 GND#A18 A18
PETP1_GFXRP1 B19 PETp1
3 OUT
PETN1_GFXRN1 B20 PETn1
3 OUT
PERp1 A21 PERP1
3
IN
B22 GND#B22 PERn1 A22 PERN1
3
IN
3
PETP2_GFXRP2 B23 PETp2 GND#A23 A23
C 3
OUT
PETN2_GFXRN2 B24 PETn2
C
OUT
PERp2 A25 PERP2
IN 3
Place these caps as close to the PCIE B26 GND#B26 PERn2 A26 PERN2
3
IN
CAP CER 10UF 20% 16V X5R 3
PETP3_GFXRP3 B27 PETp3 GND#A27 A27
OUT
connector as possible PETN3_GFXRN3 B28 PETn3
3 OUT
(1206)1.8MM H MAX PERp3 A29 PERP3
IN 3
PERn3 A30 PERN3
IN 3

B32 GND#B32

3
PETP4_GFXRP4 B33 PETp4
OUT
PETN4_GFXRN4 B34 PETn4 GND#A34 A34
3 OUT
+12V_BUS B35 GND#B35 PERp4 A35 PERP4
IN 3
PERn4 A36 PERN4
3
IN
1

3
PETP5_GFXRP5 B37 PETp5 GND#A37 A37
C14
OUT
3
PETN5_GFXRN5 B38 PETn5
OUT
10uF B39 GND#B39 PERp5 A39 PERP5
IN 3
16V PERN5
DNI PERn5 A40 3
IN
2

3
PETP6_GFXRP6 B41 PETp6
OUT
3
PETN6_GFXRN6 B42 PETn6 GND#A42 A42
OUT
B43 GND#B43 PERp6 A43 PERP6
3
IN
PERn6 A44 PERN6
IN 3
+12V_BUS PETP7_GFXRP7 B45 PETp7 GND#A45 A45
3 OUT
3
PETN7_GFXRN7 B46 PETn7
OUT
1

B47 GND#B47 PERp7 A47 PERP7

3
C20 C21
IN
PERn7 A48 PERN7
3
IN
0.15uF 0.15uF GND#A49 A49
16V 16V PETP8_GFXRP8
3 B50 PETp8
OUT
2

3
PETN8_GFXRN8 B51 PETn8
OUT
B52 GND#B52 PERp8 A52 PERP8
3
IN
PERn8 A53 PERN8
3
IN
PETP9_GFXRP9 B54 PETp9 GND#A54 A54
3 OUT
+3.3V_BUS CAP CER 10UF 10% 6.3V X5R PETN9_GFXRN9 B55 PETn9
3 OUT
(0805)1.4MM MAX THICK B56 GND#B56 PERp9 A56 PERP9
3
IN
1

PERn9 A57 PERN9

3
C27
IN
3
PETP10_GFXRP10 B58 PETp10 GND#A58 A58
OUT
10uF PETN10_GFXRN10 B59 PETn10
3
B 6.3V
DNI
OUT
B60 GND#B60 PERp10 A60 PERP10
3 SYMBOL LEGEND
B
IN
2

PERn10 A61 PERN10

3
IN
3
PETP11_GFXRP11 B62 PETp11 GND#A62 A62
OUT
3
PETN11_GFXRN11 B63 PETn11 DNI DO NOT
OUT
B64 GND#B64 PERp11 A64 PERP11 INSTALL
IN 3
+3.3V_BUS PERn11 A65 PERN11
IN 3
3
PETP12_GFXRP12 B66 PETp12 GND#A66 A66 # ACTIVE
OUT
1

3
PETN12_GFXRN12 B67 PETn12 LOW
C33 C34 C35
OUT
B68 GND#B68 PERp12 A68 PERP12
3
IN
0.1uF 1uF 0.01uF PERn12 A69 PERN12 DIGITAL
IN 3
6.3V 6.3V 10V PETP13_GFXRP13
3 B70 PETp13 GND#A70 A70 GROUND
OUT
2

3
PETN13_GFXRN13 B71 PETn13
OUT
B72 GND#B72 PERp13 A72 PERP13
3 ANALOG
IN
PERn13 A73 PERN13
3 GROUND
IN
PETP14_GFXRP14 B74 PETp14 GND#A74 A74
3 OUT
PETN14_GFXRN14 B75 PETn14 BUO BRING UP
3 OUT
B76 GND#B76 PERp14 A76 PERP14
3
ONLY
IN
PERn14 A77 PERN14
3
+12V_BUS
IN
3
PETP15_GFXRP15 B78 PETp15
OUT
PETN15_GFXRN15 B79 PETn15 GND#A79 A79
3 OUT
PERp15 A80 PERP15
IN 3
1

PRESENCE B81 PRSNT2#B81 PERn15 A81 PERN15

2 IN 3
C43 C44 C47

0.1uF 0.1uF 0.1uF

16V 16V 16V
DNI
2

x16 PCIe

CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.

AMD - PLATFORM HARDWARE ENG C 2014 Advanced Micro Devices

#48, No.1387, ZHANGDONG ROAD This AMD Board schematic and design is the exclusive property of AMD, and

A SHANGHAI, CHINA 201203 is provided only to entities under a non-disclosure agreement with AMD A
for evaluation purposes. Further distribution or disclosure is strictly

prohibited. Use of this schematic and design for any purpose other than

evaluation requires a Board Technology License Agreement with AMD.

AMD makes no representations or warranties of any kind regarding this

SHEET: PCI-E Edge Connector
schematic and design, including, not limited to, any implied warranty

of merchantability or fitness for a particular purpose, and disclaims

responsibility for any consequences resulting from use of the

DATE: Thu Jun 04 06:11:34 2015 REV: 1.0
information included herein.

SHEET NUMBER: 2 OF 21 TITLE:

Caicos G5 VGA+DP+HDMI 25W ASIC, 5.7"

DOCUMENT NUMBER: 105-C982xx-00A

NOTES: NOTE

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

LOMBOK/CAICOS/CEDAR PCIe Interface

NOTE: Some of the PCIE testpoints will

be available through vias on traces.

U1B GPU(215-0804070-00)
D D
PART 2 OF 15

PETP0_GFXRP0 AF30 AH30 PCIE_TX0P C3 1 20.1uF 6.3V PERP0

2 IN PCIE_RX0P PCIE_TX0P OUT 2
PETN0_GFXRN0 AE31 AG31 PCIE_TX0N C4 1 20.1uF 6.3V PERN0
2 IN PCIE_RX0N PCIE_TX0N OUT 2

PETP1_GFXRP1 AE29 AG29 PCIE_TX1P C5 1 20.1uF 6.3V PERP1

2 IN PCIE_RX1P PCIE_TX1P OUT 2
PETN1_GFXRN1 AD28 AF28 PCIE_TX1N C6 1 20.1uF 6.3V PERN1
2 IN PCIE_RX1N PCIE_TX1N OUT 2

PETP2_GFXRP2 AD30 AF27 PCIE_TX2P C7 1 20.1uF 6.3V PERP2

2 IN PCIE_RX2P PCIE_TX2P OUT 2
PETN2_GFXRN2 AC31 AF26 PCIE_TX2N C9 1 20.1uF 6.3V PERN2
2 IN PCIE_RX2N PCIE_TX2N OUT 2

PETP3_GFXRP3 AC29 AD27 PCIE_TX3P C10 1 20.1uF 6.3V PERP3

2 IN PCIE_RX3P PCIE_TX3P OUT 2
PETN3_GFXRN3 AB28 AD26 PCIE_TX3N C11 1 20.1uF 6.3V PERN3
2 IN PCIE_RX3N PCIE_TX3N OUT 2

PETP4_GFXRP4 AB30 AC25 PCIE_TX4P C12 1 20.1uF 6.3V PERP4

2 IN PCIE_RX4P PCIE_TX4P OUT 2
PETN4_GFXRN4 AA31 AB25 PCIE_TX4N C13 1 20.1uF 6.3V PERN4
2 IN PCIE_RX4N PCIE_TX4N OUT 2

PETP5_GFXRP5 AA29 Y23 PCIE_TX5P C15 1 20.1uF 6.3V PERP5

2 IN PCIE_RX5P PCIE_TX5P OUT 2
PETN5_GFXRN5 Y28 Y24 PCIE_TX5N C16 1 20.1uF 6.3V PERN5
2 IN PCIE_RX5N PCIE_TX5N OUT 2
TP109 1
PETP6_GFXRP6 Y30 AB27 PCIE_TX6P C17 1 20.1uF 6.3V PERP6
2 IN PCIE_RX6P PCIE_TX6P OUT 2
PETN6_GFXRN6 W31 AB26 PCIE_TX6N C18 1 20.1uF 6.3V PERN6
2 IN PCIE_RX6N PCIE_TX6N OUT 2
TP110 1
PETP7_GFXRP7 W29 Y27 PCIE_TX7P C19 1 20.1uF 6.3V PERP7
2 IN PCIE_RX7P PCIE_TX7P OUT 2
PETN7_GFXRN7 V28 Y26 PCIE_TX7N C22 1 20.1uF 6.3V PERN7
2 IN PCIE_RX7N PCIE_TX7N OUT 2

PETP8_GFXRP8 V30 W24 PCIE_TX8P C23 1 20.1uF 6.3V PERP8

2 IN PCIE_RX8P PCIE_TX8P OUT 2
PETN8_GFXRN8 U31 W23 PCIE_TX8N C24 1 20.1uF 6.3V PERN8
2 IN PCIE_RX8N PCIE_TX8N OUT 2

PETP9_GFXRP9 U29 V27 PCIE_TX9P C25 1 20.1uF 6.3V PERP9

2 IN PCIE_RX9P PCIE_TX9P OUT 2
PETN9_GFXRN9 T28 U26 PCIE_TX9N C26 1 20.1uF 6.3V PERN9
2 IN PCIE_RX9N PCIE_TX9N OUT 2
P
PETP10_GFXRP10 T30 C U24 PCIE_TX10P C28 1 20.1uF 6.3V PERP10
2 IN PCIE_RX10P I PCIE_TX10P OUT 2
PETN10_GFXRN10 R31 U23 PCIE_TX10N C29 1 20.1uF 6.3V PERN10
2 PCIE_RX10N E PCIE_TX10N 2
IN X OUT
C 2
PETP11_GFXRP11 R29 PCIE_RX11P
P
R PCIE_TX11P T26 PCIE_TX11P C30 1 20.1uF 6.3V PERP11
2
C
IN E PCIE_TX11N
OUT
PETN11_GFXRN11 P28 T27 C31 1 20.1uF 6.3V PERN11
2 IN PCIE_RX11N PCIE_TX11N OUT 2
S
S
PETP12_GFXRP12 P30 T24 PCIE_TX12P C32 1 20.1uF 6.3V PERP12
2 IN PCIE_RX12P PCIE_TX12P OUT 2
PETN12_GFXRN12 N31 T23 PCIE_TX12N C36 1 20.1uF 6.3V PERN12
2 IN PCIE_RX12N PCIE_TX12N OUT 2

PETP13_GFXRP13 N29 P27 PCIE_TX13P C37 1 20.1uF 6.3V PERP13

2 IN PCIE_RX13P PCIE_TX13P OUT 2
PETN13_GFXRN13 M28 P26 PCIE_TX13N C38 1 20.1uF 6.3V PERN13
2 IN PCIE_RX13N PCIE_TX13N OUT 2

PETP14_GFXRP14 M30 P24 PCIE_TX14P C39 1 20.1uF 6.3V PERP14

2 IN PCIE_RX14P PCIE_TX14P OUT 2
PETN14_GFXRN14 L31 P23 PCIE_TX14N C40 1 20.1uF 6.3V PERN14
2 IN PCIE_RX14N PCIE_TX14N OUT 2
TP121 1
PETP15_GFXRP15 L29 M27 PCIE_TX15P C41 1 20.1uF 6.3V PERP15
2 IN PCIE_RX15P PCIE_TX15P OUT 2
PETN15_GFXRN15 K30 N26 PCIE_TX15N C42 1 20.1uF 6.3V PERN15
2 IN PCIE_RX15N PCIE_TX15N OUT 2
TP122 1

2
PCIE_REFCLKP AK30 PCIE_REFCLKP
IN
2
PCIE_REFCLKN AK32 PCIE_REFCLKN
IN

Cedar: Install R7
+1V
RV710: Do not install R7 1K 2 1 R7 PX_EN AB16 Y22 PCIE_CALRP R9 1 2 1.27K 1%
PX_EN PCIE_CALRP
AA22 PCIE_CALRN R8 1 2 2K 1%
PCIE_CALRN

2,12
PERST#_BUF AL27 PERSTB
IN
+1.8V

B11
1 2 +PCIE_PVDD AM30 PCIE_PVDD

1
120R
C89 C73 C75 C74
COMMON(3150000000G)
10uF 1uF 0.1uF 0.01uF PCIE_VSS#1 AA27
6.3V 6.3V 6.3V 10V
DNI DNI DNI PCIE_VSS#2 AB24

2
PCIE_VSS#3 AB32
PCIE_VSS#4 AC24
PCIE_VSS#5 AC26
B +1.8V PCIE_VSS#6 AC27 B
PCIE_VSS#7 AD25
AB23 PCIE_VDDR#1 PCIE_VSS#8 AD32
1

1
AC23 PCIE_VDDR#2 PCIE_VSS#9 AE27
C147 C143 C144 C145 C146 C148 C149 C156 AD24 AF32
PCIE_VDDR#3 PCIE_VSS#10
4.7uF 1uF 1uF 1uF 1uF 1uF 0.1uF 0.1uF AE24 PCIE_VDDR#4 PCIE_VSS#11 AG27
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
DNI DNI DNI AE25 PCIE_VDDR#5 PCIE_VSS#12 AH32
2

2
AE26 PCIE_VDDR#6 PCIE_VSS#13 K28
AF25 PCIE_VDDR#7 PCIE_VSS#14 K32
AG26 PCIE_VDDR#8 PCIE_VSS#15 L27
PCIE_VSS#16 M32
PCIE_VSS#17 N25
PCIE_VSS#18 N27
+1V P25
PCIE_VSS#19
PCIE_VSS#20 P32
L23 PCIE_VDDC#1 PCIE_VSS#21 R27
1

1
L24 PCIE_VDDC#2 PCIE_VSS#22 T25
C158 C150 C151 C152 C153 C154 C155 L25 T32
PCIE_VDDC#3 PCIE_VSS#23
10uF 1uF 1uF 1uF 1uF 1uF 1uF L26 PCIE_VDDC#4 PCIE_VSS#24 U25
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
DNI DNI DNI M22 PCIE_VDDC#5 PCIE_VSS#25 U27
2

N22 PCIE_VDDC#6 PCIE_VSS#26 V32

N23 PCIE_VDDC#7 PCIE_VSS#27 W25
N24 PCIE_VDDC#8 PCIE_VSS#28 W26
R22 PCIE_VDDC#9 PCIE_VSS#29 W27
T22 PCIE_VDDC#10 PCIE_VSS#30 Y25
U22 PCIE_VDDC#11 PCIE_VSS#31 Y32
V22 PCIE_VDDC#12

CEDAR PRO A11P HF MVE SLT BIN1 TSMC FB12

CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.

AMD - PLATFORM HARDWARE ENG C 2014 Advanced Micro Devices

#48, No.1387, ZHANGDONG ROAD This AMD Board schematic and design is the exclusive property of AMD, and

A SHANGHAI, CHINA 201203 is provided only to entities under a non-disclosure agreement with AMD A
for evaluation purposes. Further distribution or disclosure is strictly

prohibited. Use of this schematic and design for any purpose other than

evaluation requires a Board Technology License Agreement with AMD.

AMD makes no representations or warranties of any kind regarding this

SHEET: CAICOS PCIE
schematic and design, including, not limited to, any implied warranty

of merchantability or fitness for a particular purpose, and disclaims

responsibility for any consequences resulting from use of the

DATE: Thu Jun 04 06:11:35 2015 REV: 1.0
information included herein.

SHEET NUMBER: 3 OF 21 TITLE:

Caicos G5 VGA+DP+HDMI 25W ASIC, 5.7"

DOCUMENT NUMBER: 105-C982xx-00A

NOTES: NOTE

8 7 6 5 4 3 2 1
LOMBOK/CAICOS/CEDAR MEM Interface Ch A&B

U1C GPU(215-0804070-00)

PART 3 OF 15

DQA0<0> 0 DQA0<0> K27 5 4E17 DQA1<0> 0 DQA1<0>

5,4 BI DQA0_0 DQA1_0 BI 5,4
DQA0<1> 1 DQA0<1> J29 5 4D16 DQA1<1> 1 DQA1<1>
5,4 BI DQA0_1 DQA1_1 BI 5,4
DQA0<2> 2 DQA0<2> H30 5 4F15 DQA1<2> 2 DQA1<2>
5,4 BI DQA0_2 DQA1_2 BI 5,4
DQA0<3> 3 DQA0<3> H32 5 4A15 DQA1<3> 3 DQA1<3>
5,4 BI DQA0_3 DQA1_3 BI 5,4
DQA0<4> 4 DQA0<4> G29 5 4D14 DQA1<4> 4 DQA1<4>
5,4 BI DQA0_4 DQA1_4 BI 5,4
DQA0<5> 5 DQA0<5> F28 5 4F13 DQA1<5> 5 DQA1<5>
5,4 BI DQA0_5 DQA1_5 BI 5,4
DQA0<6> 6 DQA0<6> F32 5 4A13 DQA1<6> 6 DQA1<6>
5,4 BI DQA0_6 DQA1_6 BI 5,4
DQA0<7> 7 DQA0<7> F30 5 4C13 DQA1<7> 7 DQA1<7>
5,4 BI DQA0_7 DQA1_7 BI 5,4
DQA0<8> 8 DQA0<8> C30 5 4E11 DQA1<8> 8 DQA1<8>
5,4 BI DQA0_8 DQA1_8 BI 5,4
DQA0<9> 9 DQA0<9> F27 5 4A11 DQA1<9> 9 DQA1<9>
5,4 BI DQA0_9 DQA1_9 BI 5,4
DQA0<10> 10 DQA0<10> A28 5 4C11 DQA1<10> 10 DQA1<10>
5,4 BI DQA0_10 DQA1_10 BI 5,4
DQA0<11> 11 DQA0<11> C28 5 4F11 DQA1<11> 11 DQA1<11>
5,4 BI DQA0_11 DQA1_11 BI 5,4
DQA0<12> 12 DQA0<12> E27 5 4A9 DQA1<12> 12 DQA1<12>
5,4 BI DQA0_12 DQA1_12 BI 5,4
DQA0<13> 13 DQA0<13> G26 5 4C9 DQA1<13> 13 DQA1<13>
5,4 BI DQA0_13 DQA1_13 BI 5,4
DQA0<14> 14 DQA0<14> D26 5 4F9 DQA1<14> 14 DQA1<14>
5,4 BI DQA0_14 DQA1_14 BI 5,4
DQA0<15> 15 DQA0<15> F25 5 4D8 DQA1<15> 15 DQA1<15>
5,4 BI DQA0_15 DQA1_15 BI 5,4
DQA0<16> 16 DQA0<16> A25 5 4E7 DQA1<16> 16 DQA1<16>
5,4 BI DQA0_16 DQA1_16 BI 5,4
DQA0<17> 17 DQA0<17> C25 5 4A7 DQA1<17> 17 DQA1<17>
5,4 BI DQA0_17 DQA1_17 BI 5,4
DQA0<18> 18 DQA0<18> E25 5 4C7 DQA1<18> 18 DQA1<18>
5,4 BI DQA0_18 DQA1_18 BI 5,4
DQA0<19> 19 DQA0<19> D24 5 4F7 DQA1<19> 19 DQA1<19>
5,4 BI DQA0_19 DQA1_19 BI 5,4
DQA0<20> 20 DQA0<20> E23 5 4A5 DQA1<20> 20 DQA1<20>
5,4 BI DQA0_20 DQA1_20 BI 5,4
DQA0<21> 21 DQA0<21> F23 5 4E5 DQA1<21> 21 DQA1<21>
5,4 BI DQA0_21 DQA1_21 BI 5,4
DQA0<22> 22 DQA0<22> D22 5 4C3 DQA1<22> 22 DQA1<22>
5,4 BI DQA0_22 DQA1_22 BI 5,4
DQA0<23> 23 DQA0<23> F21 5 4E1 DQA1<23> 23 DQA1<23>
5,4 BI DQA0_23 DQA1_23 BI 5,4
DQA0<24> 24 DQA0<24> E21 5 4G7 DQA1<24> 24 DQA1<24>
5,4 BI DQA0_24 DQA1_24 BI 5,4
DQA0<25> 25 DQA0<25> D20 5 4G6 DQA1<25> 25 DQA1<25>
5,4 BI DQA0_25 DQA1_25 BI 5,4
DQA0<26> 26 DQA0<26> F19 5 4G1 DQA1<26> 26 DQA1<26>
5,4 BI DQA0_26 DQA1_26 BI 5,4
DQA0<27> 27 DQA0<27> A19 5 4G3 DQA1<27> 27 DQA1<27>
5,4 BI DQA0_27 DQA1_27 BI 5,4
DQA0<28> 28 DQA0<28> D18 5 4J6 DQA1<28> 28 DQA1<28>
5,4 BI DQA0_28 DQA1_28 BI 5,4
DQA0<29> 29 DQA0<29> F17 5 4J1 DQA1<29> 29 DQA1<29>
5,4 BI DQA0_29 DQA1_29 BI 5,4
DQA0<30> 30 DQA0<30> A17 5 4J3 DQA1<30> 30 DQA1<30>
5,4 BI DQA0_30 DQA1_30 BI 5,4
DQA0<31> 31 DQA0<31> C17 5 4J5 DQA1<31> 31 DQA1<31>
5,4 BI DQA0_31 DQA1_31 BI 5,4

5
5,4
MAA0<0> 0 4 MAA0<0> K17 MAA0_0 5 4
MAA1_0 J14 MAA1<0> 0 MAA1<0>
4,5
OUT MAA0<1> MAA1<1>
BI
MAA0<1> 1 J20 5 4 K14 1 MAA1<1>
5,4 OUT MAA0_1 M MAA1_1 BI 4,5
MAA0<2> 2 MAA0<2> H23 E 5 4 J11 MAA1<2> 2 MAA1<2>
5,4 OUT MAA0_2 MAA1_2 BI 4,5
MAA0<3> 3 MAA0<3> G23 M 5 4 J13 MAA1<3> 3 MAA1<3>
5,4 OUT MAA0_3 MAA1_3 BI 4,5
MAA0<4>
O MAA1<4>
5,4
MAA0<4> 4 G24 MAA0_4 R 5 4
MAA1_4 H11 4 MAA1<4>
4,5
OUT MAA0<5> Y MAA1<5>
BI
MAA0<5> 5 H24 5 4 G11 5 MAA1<5>
5,4 OUT MAA0_5 MAA1_5 BI 4,5
MAA0<6> 6 MAA0<6> J19 5 4 J16 MAA1<6> 6 MAA1<6>
5,4 OUT MAA0_6 I MAA1_6 BI 4,5
5,4
MAA0<7> 7 MAA0<7> K19 MAA0_7 N 5 4
MAA1_7 L15 MAA1<7> 7 MAA1<7>
4,5
OUT MAA0<8>
T MAA1<8>
BI
5,4
MAA0<8> 8 G20 MAA0_8 E 5 4
MAA1_8 G14 8 MAA1<8>
4,5
OUT BI
R
F
A
C
E
5
WCKA0_0 E32 WCKA0_0 WCKA1_0 E13 WCKA1_0
5
OUT OUT
5
WCKA0#_0 E30 WCKA0B_0 WCKA1B_0 D12 WCKA1#_0
5
OUT OUT
WCKA0_1 A21 E3 WCKA1_1
5 OUT WCKA0_1 WCKA1_1 OUT 5
WCKA0#_1 C21 F4 WCKA1#_1
5 OUT WCKA0B_1 WCKA1B_1 OUT 5

5 EDCA0_0 H28 EDCA0_0 EDCA1_0 E15 EDCA1_0 5

OUT B OUT
5 EDCA0_1 C27 EDCA0_1 EDCA1_1 D10 EDCA1_1 5
OUT A OUT
5 EDCA0_2 A23 EDCA0_2 N EDCA1_2 D6 EDCA1_2 5
OUT K
OUT
5 EDCA0_3 E19 EDCA0_3 EDCA1_3 G5 EDCA1_3 5
OUT OUT
A

DDBIA0_0 H27 C15 DDBIA1_0

5 OUT DDBIA0_0 DDBIA1_0 OUT 5
5 DDBIA0_1 A27 DDBIA0_1 DDBIA1_1 E9 DDBIA1_1
5
OUT OUT
5 DDBIA0_2 C23 DDBIA0_2 DDBIA1_2 C5 DDBIA1_2
5
OUT OUT
5 DDBIA0_3 C19 DDBIA0_3 DDBIA1_3 H4 DDBIA1_3
5
OUT OUT
ADBIA0 L18 K16 ADBIA1
5 OUT ADBIA0 ADBIA1 OUT 5

5
CSA0#_0 H22 CSA0B_0 CSA1B_0 G13 CSA1#_0
5
OUT OUT
J22 CSA0B_1 CSA1B_1 K13

5
CASA#0 G19 CASA0B CASA1B G16 CASA#1
5
OUT OUT
5
RASA#0 G22 RASA0B RASA1B G17 RASA#1
5
OUT OUT
WEA#0 G25 H10 WEA#1
5 OUT WEA0B WEA1B OUT 5

5
CKEA0 K20 CKEA0 CKEA1 J17 CKEA1
5
OUT OUT

CLKA0 H26 G9 CLKA1 +MVDD

5 OUT CLKA0 CLKA1 OUT 5
5
CLKA#0 H25 CLKA0B CLKA1B H9 CLKA#1
5
OUT OUT
R301 1 DNI 2 243R 1% MEM_CALRP0
R291/R293: C396 is using 40.2

1
1

R291
46.4R
R303 1%
243R
+MVDD 1% +MVDD

2
DNI MVREFD_A
K25 MEM_CALRP0 MVREFDA K26
2

R302 1 DNI 2 243R 1% MEM_CALRN0 J25 MEM_CALRN0 1

1
C295

1
1uF R292
6.3V 100R
1% 1% R293
2

46.4R
2 1%
MVREFD/S =0.7* VDDR1 (GDDR3/4/5)

2
DRAM_RST R3616 1 2 49.9R 1% DRST_R R3615 1 2 0R 5% DRST L10 J26 MVREFS_A
5 OUT DRAM_RST MVREFSA
1

1
1

1
C3608 C3600 C297

120pF R3600 68pF 1uF R294

5.1K CEDAR PRO A11P HF MVE SLT BIN1 TSMC FB12 100R
50V 50V 6.3V
DNI 1%
2

2
2

CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.

AMD - PLATFORM HARDWARE ENG C 2014 Advanced Micro Devices

#48, No.1387, ZHANGDONG ROAD This AMD Board schematic and design is the exclusive property of AMD, and

SHANGHAI, CHINA 201203 is provided only to entities under a non-disclosure agreement with AMD

for evaluation purposes. Further distribution or disclosure is strictly

prohibited. Use of this schematic and design for any purpose other than

evaluation requires a Board Technology License Agreement with AMD.

AMD makes no representations or warranties of any kind regarding this

SHEET: CAICOS MEM
schematic and design, including, not limited to, any implied warranty

of merchantability or fitness for a particular purpose, and disclaims

responsibility for any consequences resulting from use of the

DATE: Thu Jun 04 06:11:35 2015 REV: 1.0
information included herein.

SHEET NUMBER: 4 OF 21 TITLE:

Caicos G5 VGA+DP+HDMI 25W ASIC, 5.7"

DOCUMENT NUMBER: 105-C982xx-00A

NOTES: NOTE
2pcs GDDR5 x32
MEM(23F24GB7MP60)
DQA0<0> 0 DQA0<0> +MVDD DQA1<0> 0 DQA1<0>
4,5 BI 4 5 PART_NUMBER = 23CNOPN001 4,5 BI 4 5 MEM(23F24GB7MP60)
DQA0<1> 1 DQA0<1> U202 DQA1<1> 1 DQA1<1> +MVDD
4,5 BI 4 5 4,5 BI 4 5 PART_NUMBER = 23CNOPN001
DQA0<2> 2 DQA0<2> DQA0<14> M2 B1 DQA1<2> 2 DQA1<2> U402
4,5 BI 4 5 5 4 DQ31__DQ7 VDDQ_B1 4,5 BI 4 5
DQA0<3> 3 DQA0<3> DQA0<15> M4 B3 DQA1<3> 3 DQA1<3> DQA1<22> M2 B1
4,5 BI 4 5 5 4 DQ30__DQ6 VDDQ_B3 4,5 BI 4 5 5 4 DQ31__DQ7 VDDQ_B1
DQA0<4> 4 DQA0<4> DQA0<13> N2 B12 DQA1<4> 4 DQA1<4> DQA1<23> M4 B3
4,5 BI 4 5 5 4 DQ29__DQ5 VDDQ_B12 4,5 BI 4 5 5 4 DQ30__DQ6 VDDQ_B3
DQA0<5> 5 DQA0<5> DQA0<12> N4 B14 DQA1<5> 5 DQA1<5> DQA1<21> N2 B12
4,5 BI 4 5 5 4 DQ28__DQ4 VDDQ_B14 4,5 BI 4 5 5 4 DQ29__DQ5 VDDQ_B12
DQA0<6> 6 DQA0<6> DQA0<10> T2 D1 DQA1<6> 6 DQA1<6> DQA1<20> N4 B14
4,5 BI 4 5 5 4 DQ27__DQ3 VDDQ_D1 4,5 BI 4 5 5 4 DQ28__DQ4 VDDQ_B14
DQA0<7> 7 DQA0<7> DQA0<8> T4 D3 DQA1<7> 7 DQA1<7> DQA1<16> T2 D1
4,5 BI 4 5 5 4 DQ26__DQ2 VDDQ_D3 4,5 BI 4 5 5 4 DQ27__DQ3 VDDQ_D1
DQA0<8> 8 DQA0<8> DQA0<11> V2 D12 DQA1<8> 8 DQA1<8> DQA1<17> T4 D3
4,5 BI 4 5 5 4 DQ25__DQ1 VDDQ_D12 4,5 BI 4 5 5 4 DQ26__DQ2 VDDQ_D3
DQA0<9> 9 DQA0<9> DQA0<9> V4 D14 DQA1<9> 9 DQA1<9> DQA1<18> V2 D12
4,5 BI 4 5 5 4 DQ24__DQ0 VDDQ_D14 4,5 BI 4 5 5 4 DQ25__DQ1 VDDQ_D12
DQA0<10> 10 DQA0<10> DQA0<1> M13 E5 DQA1<10> 10 DQA1<10> DQA1<19> V4 D14
4,5 BI 4 5 5 4 DQ23__DQ15 VDDQ_E5 4,5 BI 4 5 5 4 DQ24__DQ0 VDDQ_D14
DQA0<11> 11 DQA0<11> DQA0<0> M11 E10 DQA1<11> 11 DQA1<11> DQA1<25> M13 E5
4,5 BI 4 5 5 4 DQ22__DQ14 VDDQ_E10 4,5 BI 4 5 5 4 DQ23__DQ15 VDDQ_E5
DQA0<12> 12 DQA0<12> DQA0<2> N13 F1 DQA1<12> 12 DQA1<12> DQA1<24> M11 E10
4,5 BI 4 5 5 4 DQ21__DQ13 VDDQ_F1 4,5 BI 4 5 5 4 DQ22__DQ14 VDDQ_E10
DQA0<13> 13 DQA0<13> DQA0<3> N11 F3 DQA1<13> 13 DQA1<13> DQA1<27> N13 F1
4,5 BI 4 5 5 4 DQ20__DQ12 VDDQ_F3 4,5 BI 4 5 5 4 DQ21__DQ13 VDDQ_F1
DQA0<14> 14 DQA0<14> DQA0<5> T13 F12 DQA1<14> 14 DQA1<14> DQA1<26> N11 F3
4,5 BI 4 5 5 4 DQ19__DQ11 VDDQ_F12 4,5 BI 4 5 5 4 DQ20__DQ12 VDDQ_F3
DQA0<15> 15 DQA0<15> DQA0<6> T11 F14 DQA1<15> 15 DQA1<15> DQA1<31> T13 F12
4,5 BI 4 5 5 4 DQ18__DQ10 VDDQ_F14 4,5 BI 4 5 5 4 DQ19__DQ11 VDDQ_F12
DQA0<16> 16 DQA0<16> DQA0<4> V13 G2 DQA1<16> 16 DQA1<16> DQA1<29> T11 F14
4,5 BI 4 5 5 4 DQ17__DQ9 VDDQ_G2 4,5 BI 4 5 5 4 DQ18__DQ10 VDDQ_F14
DQA0<17> 17 DQA0<17> DQA0<7> V11 G13 DQA1<17> 17 DQA1<17> DQA1<28> V13 G2
4,5 BI 4 5 5 4 DQ16__DQ8 VDDQ_G13 4,5 BI 4 5 5 4 DQ17__DQ9 VDDQ_G2
DQA0<18> 18 DQA0<18> DQA0<22> F13 H3 DQA1<18> 18 DQA1<18> DQA1<30> V11 G13
4,5 BI 4 5 5 4 DQ15__DQ23 VDDQ_H3 4,5 BI 4 5 5 4 DQ16__DQ8 VDDQ_G13
DQA0<19> 19 DQA0<19> DQA0<23> F11 H12 DQA1<19> 19 DQA1<19> DQA1<15> F13 H3
4,5 BI 4 5 5 4 DQ14__DQ22 VDDQ_H12 4,5 BI 4 5 5 4 DQ15__DQ23 VDDQ_H3
DQA0<20> 20 DQA0<20> DQA0<21> E13 K3 DQA1<20> 20 DQA1<20> DQA1<14> F11 H12
4,5 BI 4 5 5 4 DQ13__DQ21 VDDQ_K3 4,5 BI 4 5 5 4 DQ14__DQ22 VDDQ_H12
DQA0<21> 21 DQA0<21> DQA0<20> E11 K12 DQA1<21> 21 DQA1<21> DQA1<13> E13 K3
4,5 BI 4 5 5 4 DQ12__DQ20 VDDQ_K12 4,5 BI 4 5 5 4 DQ13__DQ21 VDDQ_K3
DQA0<22> 22 DQA0<22> DQA0<19> B13 L2 DQA1<22> 22 DQA1<22> DQA1<12> E11 K12
4,5 BI 4 5 5 4 DQ11__DQ19 VDDQ_L2 4,5 BI 4 5 5 4 DQ12__DQ20 VDDQ_K12
DQA0<23> 23 DQA0<23> DQA0<17> B11 L13 DQA1<23> 23 DQA1<23> DQA1<11> B13 L2
4,5 BI 4 5 5 4 DQ10__DQ18 VDDQ_L13 4,5 BI 4 5 5 4 DQ11__DQ19 VDDQ_L2
DQA0<24> 24 DQA0<24> DQA0<18> A13 M1 DQA1<24> 24 DQA1<24> DQA1<9> B11 L13
4,5 BI 4 5 5 4 DQ9__DQ17 VDDQ_M1 4,5 BI 4 5 5 4 DQ10__DQ18 VDDQ_L13
DQA0<25> 25 DQA0<25> DQA0<16> A11 M3 DQA1<25> 25 DQA1<25> DQA1<8> A13 M1
4,5 BI 4 5 5 4 DQ8__DQ16 VDDQ_M3 4,5 BI 4 5 5 4 DQ9__DQ17 VDDQ_M1
DQA0<26> 26 DQA0<26> DQA0<25> F2 M12 DQA1<26> 26 DQA1<26> DQA1<10> A11 M3
4,5 BI 4 5 5 4 DQ7__DQ31 VDDQ_M12 4,5 BI 4 5 5 4 DQ8__DQ16 VDDQ_M3
DQA0<27> 27 DQA0<27> DQA0<24> F4 M14 DQA1<27> 27 DQA1<27> DQA<11> F2 M12
4,5 BI 4 5 5 4 DQ6__DQ30 VDDQ_M14 4,5 BI 4 5 5 4 DQ7__DQ31 VDDQ_M12
DQA0<28> 28 DQA0<28> DQA0<26> E2 N5 DQA1<28> 28 DQA1<28> DQA<10> F4 M14
4,5 BI 4 5 5 4 DQ5__DQ29 VDDQ_N5 4,5 BI 4 5 5 4 DQ6__DQ30 VDDQ_M14
DQA0<29> 29 DQA0<29> DQA0<27> E4 N10 DQA1<29> 29 DQA1<29> DQA1<2> E2 N5
4,5 BI 4 5 5 4 DQ4__DQ28 VDDQ_N10 4,5 BI 4 5 5 4 DQ5__DQ29 VDDQ_N5
DQA0<30> 30 DQA0<30> DQA0<29> B2 P1 DQA1<30> 30 DQA1<30> DQA1<3> E4 N10
4,5 BI 4 5 5 4 DQ3__DQ27 VDDQ_P1 4,5 BI 4 5 5 4 DQ4__DQ28 VDDQ_N10
DQA0<31> 31 DQA0<31> DQA0<30> B4 P3 DQA1<31> 31 DQA1<31> DQA1<5> B2 P1
4,5 BI 4 5 5 4 DQ2__DQ26 VDDQ_P3 4,5 BI 4 5 5 4 DQ3__DQ27 VDDQ_P1
DQA0<28> A2 P12 DQA1<7> B4 P3
5 4 DQ1__DQ25 VDDQ_P12 5 4 DQ2__DQ26 VDDQ_P3
DQA0<31> A4 P14 DQA1<4> A2 P12
5 4 DQ0__DQ24 VDDQ_P14 5 4 DQ1__DQ25 VDDQ_P12
T1 DQA1<6> A4 P14
VDDQ_T1 5 4 DQ0__DQ24 VDDQ_P14
VDDQ_T3 T3 VDDQ_T1 T1
VDDQ_T12 T12 VDDQ_T3 T3
VDDQ_T14 T14 VDDQ_T12 T12
MAA0<0> 0 MAA0<0> T14
4,5 IN 4 5 VDDQ_T14
MAA0<1> 1 MAA0<1> MAA0<8> J5 +MVDD
4,5 IN 4 5 5 4 RFU_A12_NC
MAA0<2> 2 MAA0<2> MAA0<0> K4 C5 MAA1<8> 8 MAA1<8> J5 +MVDD
4,5 IN 4 5 5 4 A7_A8__A0_A10 VDD_C5 4,5 IN RFU_A12_NC
MAA0<3> 3 MAA0<3> MAA0<1> K5 C10 MAA1<7> 7 MAA1<7> K4 C5
4,5 IN 4 5 5 4 A6_A11__A1_A9 VDD_C10 4,5 IN A7_A8__A0_A10 VDD_C5
MAA0<4> 4 MAA0<4> MAA0<3> K10 D11 MAA1<6> 6 MAA1<6> K5 C10
4,5 IN 4 5 5 4 A5_BA1__A3_BA3 VDD_D11 4,5 IN A6_A11__A1_A9 VDD_C10
MAA0<5> 5 MAA0<5> MAA0<2> K11 G1 MAA1<5> 5 MAA1<5> K10 D11
4,5 IN 4 5 5 4 A4_BA2__A2_BA0 VDD_G1 4,5 IN A5_BA1__A3_BA3 VDD_D11
MAA0<6> 6 MAA0<6> MAA0<5> H10 G4 MAA1<4> 4 MAA1<4> K11 G1
4,5 IN 4 5 5 4 A3_BA3__A5_BA1 VDD_G4 4,5 IN A4_BA2__A2_BA0 VDD_G1
MAA0<7> 7 MAA0<7> MAA0<4> H11 G11 MAA1<3> 3 MAA1<3> H10 G4
4,5 IN 4 5 5 4 A2_BA0__A4_BA2 VDD_G11 4,5 IN A3_BA3__A5_BA1 VDD_G4
MAA0<8> 8 MAA0<8> MAA0<6> H5 G14 MAA1<2> 2 MAA1<2> H11 G11
4,5 IN 4 5 5 4 A1_A9__A6_A11 VDD_G14 4,5 IN A2_BA0__A4_BA2 VDD_G11
MAA0<7> H4 L1 MAA1<1> 1 MAA1<1> H5 G14
5 4 A0_A10__A7_A8 VDD_L1 4,5 IN A1_A9__A6_A11 VDD_G14
L4 MAA1<0> 0 MAA1<0> H4 L1
VDD_L4 4,5 IN A0_A10__A7_A8 VDD_L1
VDD_L11 L11 VDD_L4 L4
VDD_L14 L14 VDD_L11 L11
4
WCKA0_1 D4 WCK01__WCK23 VDD_P11 P11 VDD_L14 L14
IN
4
WCKA0#_1 D5 WCK01#__WCK23# VDD_R5 R5 4
WCKA1_0 D4 WCK01__WCK23 VDD_P11 P11
IN IN
R10 WCKA1#_0 D5 R5
VDD_R10 4 IN WCK01#__WCK23# VDD_R5
WCKA0_0 P4 R10
4 IN WCK23__WCK01 VDD_R10
4
WCKA0#_0 P5 WCK23#__WCK01# 4
WCKA1_1 P4 WCK23__WCK01
IN IN
VSSQ_A1 A1 4
WCKA1#_1 P5 WCK23#__WCK01#
IN
4
EDCA0_1 R2 EDC3__EDC0 VSSQ_A3 A3 VSSQ_A1 A1 +MVDD
IN
EDCA0_0 R13 A12 EDCA1_2 R2 A3
4 IN EDC2__EDC1 VSSQ_A12 4 IN EDC3__EDC0 VSSQ_A3
EDCA0_2 C13 A14 EDCA1_3 R13 A12
4 IN EDC1__EDC2 VSSQ_A14 4 IN EDC2__EDC1 VSSQ_A12
4
EDCA0_3 C2 EDC0__EDC3 VSSQ_C1 C1 4
EDCA1_1 C13 EDC1__EDC2 VSSQ_A14 A14
IN IN
VSSQ_C3 C3 4
EDCA1_0 C2 EDC0__EDC3 VSSQ_C1 C1
IN
4 DDBIA0_1 P2 DBI3#__DBI0# VSSQ_C4 C4 VSSQ_C3 C3 MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM DNI MEM MEM
BI

1
4 DDBIA0_0 P13 DBI2#__DBI1# VSSQ_C11 C11 4 DDBIA1_2 P2 DBI3#__DBI0# VSSQ_C4 C4 C413

C322

C317

C319

C362

C363

C364

C365

C367

C369

C462

C464

C476

C477
BI BI
4 DDBIA0_2 D13 DBI1#__DBI2# VSSQ_C12 C12 4 DDBIA1_3 P13 DBI2#__DBI1# VSSQ_C11 C11
BI BI
4 DDBIA0_3 D2 DBI0#__DBI3# VSSQ_C14 C14 4 DDBIA1_1 D13 DBI1#__DBI2# VSSQ_C12 C12
+MVDD
BI BI
VSSQ_E1 E1 +MVDD 4 DDBIA1_0 D2 DBI0#__DBI3# VSSQ_C14 C14
BI

2
0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF
VSSQ_E3 E3 VSSQ_E1 E1
R380 1 MEM 2 60.4R 1% CLKA#0 4 5 VSSQ_E12 E12 R400 1 MEM 2 60.4R 1% CLKA#1
4 5 VSSQ_E3 E3
R381 1 MEM 2 60.4R 1% CLKA0 4 5 4
CASA#0 G3 RAS#__CAS# VSSQ_E14 E14 R401 1 MEM 2 60.4R 1% CLKA1
4 5 VSSQ_E12 E12
IN
4
RASA#0 L3 CAS#__RAS# VSSQ_F5 F5 4 RASA#1 G3 RAS#__CAS# VSSQ_E14 E14
IN IN
VSSQ_F10 F10 4
CASA#1 L3 CAS#__RAS# VSSQ_F5 F5
IN
VSSQ_H2 H2 VSSQ_F10 F10
+MVDD CKEA0 J3 H13 H2
4 IN CKE# VSSQ_H13 VSSQ_H2
CLKA#0 J11 K2 +MVDD CKEA1 J3 H13
4,5 IN CK# VSSQ_K2 4 IN CKE# VSSQ_H13
C389 1 DNI 21uF 6.3V 4,5
CLKA0 J12 CK VSSQ_K13 K13 4,5
CLKA#1 J11 CK# VSSQ_K2 K2
IN IN
VSSQ_M5 M5 C489 1 DNI 21uF 6.3V 4,5
CLKA1 J12 CK VSSQ_K13 K13
IN
R352 1 MEM 2 2.37K 1% VSSQ_M10 M10 VSSQ_M5 M5
R353 1 MEM 2 5.49K 1% VREFD1_A0 WEA#0 G12 N1 R452 1 MEM 2 2.37K 1% M10
5 4 IN CS#__WE# VSSQ_N1 VSSQ_M10
CSA0#_0 L12 N3 R453 1 MEM 2 5.49K 1% VREFD1_A1 CSA1#_0 G12 N1
4 IN WE#__CS# VSSQ_N3 5 4 IN CS#__WE# VSSQ_N1
C390 1 MEM 21uF 6.3V VSSQ_N12 N12 4
WEA#1 L12 WE#__CS# VSSQ_N3 N3
IN
VSSQ_N14 N14 C490 1 MEM 21uF 6.3V VSSQ_N12 N12
R358 1 MEM 2 120R 1% J13 UNNAMED_4_170BALLGDDR5_I49_ZQ
ZQ VSSQ_R1 R1 VSSQ_N14 N14
J10 SEN VSSQ_R3 R3 R458 1 MEM 2 120R 1% J13 UNNAMED_4_170BALLGDDR5_I159_ZQ
ZQ VSSQ_R1 R1
VSSQ_R4 R4 J10 SEN VSSQ_R3 R3
+MVDD R11 R4
VSSQ_R11 VSSQ_R4
DRAM_RST J2 R12 +MVDD R11
4,5 IN RESET# VSSQ_R12 VSSQ_R11
C391 1 DNI 21uF 6.3V J1 MF VSSQ_R14 R14 4,5
DRAM_RST J2 RESET# VSSQ_R12 R12
+MVDD IN
VSSQ_V1 V1 C491 1 DNI 21uF 6.3V J1 MF VSSQ_R14 R14
R354 1 MEM 2 2.37K 1% VSSQ_V3 V3 VSSQ_V1 V1
R355 1 MEM 2 5.49K 1% VREFD2_A0 V12 R454 1 MEM 2 2.37K 1% V3
5 VSSQ_V12 VSSQ_V3
V14 R455 1 MEM 2 5.49K 1% VREFD2_A1 V12
VSSQ_V14 5 VSSQ_V12
C392 1 MEM 21uF 6.3V A5 Vpp_NC C492 1 MEM 21uF 6.3V VSSQ_V14 V14
V5 Vpp_NC1 A5 Vpp_NC
VSS_B5 B5 V5 Vpp_NC1
VREFD1_A0 A10 B10 B5
5 VREFD1 VSS_B10 VSS_B5
VREFD2_A0 V10 D10 VREFD1_A1 A10 B10
5 VREFD2 VSS_D10 5 VREFD1 VSS_B10
+MVDD G5 VREFD2_A1 V10 D10
VSS_G5 5 VREFD2 VSS_D10
VSS_G10 G10 +MVDD VSS_G5 G5 +MVDD
C393 1 DNI 21uF 6.3V VSS_H1 H1 VSS_G10 G10
VSS_H14 H14 C493 1 DNI 21uF 6.3V VSS_H1 H1
R356 1 MEM 2 2.37K 1% VSS_K1 K1 VSS_H14 H14
R357 1 MEM 2 5.49K 1% VREFC_A0 5 VREFC_A0 J14 K14 R456 1 MEM 2 2.37K 1% K1
5 VREFC VSS_K14 VSS_K1 MEM DNI DNI DNI MEM DNI DNI DNI DNI DNI DNI DNI

1
L5 R457 1 MEM 2 5.49K 1% VREFC_A1 5 VREFC_A1 J14 K14
VSS_L5 5 VREFC VSS_K14

C334

C335

C336

C337

C338

C386

C388

C484

C485

C486

C487

C488
C394 1 MEM 21uF 6.3V VSS_L10 L10 VSS_L5 L5
VSS_P10 P10 C494 1 MEM 21uF 6.3V VSS_L10 L10
4
ADBIA0 J4 ABI# VSS_T5 T5 VSS_P10 P10
IN

2
10uF

10uF

10uF

10uF

10uF

10uF

10uF

10uF

10uF

10uF

10uF

10uF
VSS_T10 T10 4
ADBIA1 J4 ABI# VSS_T5 T5
IN
VSS_T10 T10

Value = GDDR5
Value = GDDR5

+MVDD +MVDD +MVDD

CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.

AMD - PLATFORM HARDWARE ENG C 2014 Advanced Micro Devices

#48, No.1387, ZHANGDONG ROAD

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF

1uF
0.1uF

0.1uF

This AMD Board schematic and design is the exclusive property of AMD, and

SHANGHAI, CHINA 201203 is provided only to entities under a non-disclosure agreement with AMD
C300

MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM DNI MEM MEM MEM DNI MEM MEM MEM MEM MEM MEM DNI MEM MEM MEM MEM DNI MEM MEM DNI DNI DNI MEM MEM DNI DNI MEM MEM DNI DNI DNI MEM DNI DNI DNI MEM DNI DNI DNI MEM DNI
C301

C302

C303

C304

C307

C308

C309

C310

C352

C353

C400

C410

C455

C456

C457

C401
1

for evaluation purposes. Further distribution or disclosure is strictly

C354

C355

C402

C403

C414

C458

C459

C460

C461

C463

C465

prohibited. Use of this schematic and design for any purpose other than
C323

C311

C312

C313

C314

C315

C316

C318

C320

C366

C368

C411

C412

C420

C415

C468

evaluation requires a Board Technology License Agreement with AMD.

C450

C451

C471

C452

C453

C454

C470
C321

AMD makes no representations or warranties of any kind regarding this

SHEET: GDDR5
2

schematic and design, including, not limited to, any implied warranty
0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

of merchantability or fitness for a particular purpose, and disclaims

responsibility for any consequences resulting from use of the

DATE: Thu Jun 04 06:11:36 2015 REV: 1.0
information included herein.

SHEET NUMBER: 5 OF 21 TITLE:

Caicos G5 VGA+DP+HDMI 25W ASIC, 5.7"

DOCUMENT NUMBER: 105-C982xx-00A

NOTES: NOTE
 8 7 6 5 4 3 2 1
U1D GPU(215-0804070-00)

+3.3V_BUS PART 4 OF 15 +3.3V_BUS VIDEO BIOS

GPIO_0 U6 GPIO_0
6
FIRMWARE LOMBOKCAICOS/CEDAR GPIOs Strap CF XTAL OSC
OUT
AA17 U10 GPIO_1
VDDR3 GPIO_1 OUT 6

1
BIOS1
DNI DNI DNI AA18 VDDR3 GPIO_2 T10 GPIO_2
6
OUT

2
C164 C165 C166 C167 AB17 U8 GPIO_3_SMBDATA
VDDR3 GPIO_3_SMBDATA BI 6
0.1uF 0.1uF 0.1uF 0.1uF AB18 VDDR3 GPIO_4_SMBCLK U7 GPIO_4_SMBCLK
6 R24 COMMON(2280012200G)
6.3V 6.3V 6.3V 6.3V GPIO_5
OUT 1K +3.3V_BUS
BIOS
DNI GPIO_5_AC_BATT T9 6

2
U2
GPIO_6_TACH T8

1
T7 1 8 +3.3V_BUS +3.3V_BUS
GPIO_7 CE VDD

1
P10 GPIO_8_SO R13 1 2 33R 6 GPIO_8_R 2 7
GPIO_8_ROMSO SO HOLD BIOS(113-C398XX-XXX)
P4 GPIO_9_SI R14 1 2 33R 6 GPIO_9_R 3 6
GPIO_9_ROMSI WP SCK C57

1
P2 GPIO_10_SCK R15 1 2 33R GPIO_10_R 4 5 0.1uF
GPIO_10_ROMSCK GND SI DNI DNI
N6 GPIO_11
GPIO_11 6 R1 R2

2
N5 GPIO_12 45.3K 45.3K
GPIO_12 6 PM25LV010A-100SCE
N3 GPIO_13 DNI DNI
GPIO_13 6
D D

2
G GPIO_14_HPD2 Y9 GPIO_14_HPD2
8
OUT
P GPIO_15_PWRCNTL_0 N1 GPIO_15_PWRCNTL_0
14 1Mbit ROM
I GPIO_16
OUT GPIO_3_SMBDATA
O GPIO_16_SSIN M4 6 6
GPIO_17_THERMAL_INT R6
GPIO_18_HPD3 W10
AA11 M2 GPIO_19_CTF GPIO_4_SMBCLK
NC GPIO_19_CTF OUT 12 6
V11 P8 GPIO_20_PWRCNTL_1
NC GPIO_20_PWRCNTL_1 OUT 14
U11 NC GPIO_21_BB_EN P7
AA12 N8 GPIO_22_CS R16 1 2 33R GPIO_22_ROMCSB_R PIN BASED STRAPS
NC GPIO_22_ROMCSB
GPIO_23_CLKREQB N7 CLKREQ# requires open drain connection,
and cannot be used as pinstrap

AB11 RSVD
AB12 RSVD +3.3V_BUS
AJ23 RSVD GENERICA AB13 GPIO(0) - TX_PWRS_ENB (Transmitter Power Savings Enable)
AK18 W8 R45 1 2 10K GPIO_0 0: 50% Tx output swing for mobile mode
RSVD GENERICB GPIO_0
6
AK24 RSVD GENERICC W9 10K 2 DNI 1 MR45 1: full Tx output swing (Default setting for Desktop)
AL19 RSVD GENERICD W7
GENERICE_HPD4 AD10 GPIO(1) - TX_DEEMPH_EN (Transmitter De-emphasis Enable)
R46 1 2 10K GPIO_1 0: Tx de-emphasis disabled for mobile mode
GPIO_1 6
MR46 1 DNI 2 10K 1: Tx de-emphasis enabled (Default setting for Desktop)
PWRGOOD_GPU N10 AC14 HPD1
PWRGOOD HPD1 OUT 10
GPIO(2) - BIF_GEN2_EN (5.0 GT/s Enable)
R47 1 DNI 2 10K GPIO_2 0 : Default. (Driver Controlled Gen2)
GPIO_2 6
1

CEDAR PRO A11P HF MVE SLT BIN1 TSMC FB12 +3.3V_BUS MR47 1 DNI 2 10K 1 : Strap Controlled Gen2
R60
1K
GPU(215-0804070-00) VGA DISABLE : 1 for disable (set to 0 for normal operation)
U1O GPIO_9_R
R44 1 DNI 2 10K GPIO_9_R 6
2

2
MR44 1 DNI 2 10K
PART 15 OF 15
R33 R34
4.7K 4.7K GPIO(13,12,11) - CONFIG[2..0]
DDC
I2C AE6 DDC1CLK R49 1 2 1K GPIO_13
DDC1CLK 7 GPIO_13
6 100 - 512Kbit M25P05A (ST)
OUT

1
SCL R1 AE5 DDC1DATA MR49 1 DNI 2 1K CONFIG[2] 101 - 1Mbit M25P10A (ST)
SCL DDC1DATA BI 7
SDA GPIO_12 101 - 2Mbit M25P20 (ST)
R3 SDA R50 1 DNI 2 10K GPIO_12 6 101 - 4Mbit M25P40 (ST)
AUX1P AD2 MR50 1 DNI 2 10K CONFIG[1] 101 - 8Mbit M25P80 (ST)
AD4 R48 1 2 1K GPIO_11
SCL must be tied high if not used AUX1N GPIO_11
6 100 - 512Kbit Pm25LV512 (Chingis)
MR48 1 DNI 2 1K CONFIG[0] 101 - 1Mbit Pm25LV010 (Chingis)
C C
DDC2CLK AC11
I
2 DDC2DATA AC13
AC1 DDC6CLK C CEDAR VIP_DEVICE_STRAP_DIS
AC3 / AD13 R43 1 2 10K A_VSYNC_DAC2
DDC6DATA D AUX2P 7 0:VIP host port devices present (use if Theater is populated)
OUT
D AUX2N AD11 MR43 1 DNI 2 10K 1: No slave VIP host port devices reporting presence during reset
C (use for configurations without video-in)

GPU(215-0804070-00) CAICOS REMOVED

U1E
DDCCLK_AUX3P AD20 DDCCLK_AUX3P
10
OUT
DDCDATA_AUX3N AC20 DDCDATA_AUX3N
10
+1.8V PART 5 OF 15 BI
RESERVED:
R51 1 2 10K A_VSYNC_DAC1
OUT 7
U12 VDDR4 DVDATA_0 Y7 DDCCLK_AUX5P AE16 DDCCLK_AUX5P
8 MR51 1 DNI 2 10K Internal use only. Other logic must not affect these signals
OUT
1

DNI DNI DNI V12 VDDR4 DVDATA_1 Y8 DDCDATA_AUX5N AD16 DDCDATA_AUX5N

8 R52 1 2 10K A_HSYNC_DAC1
7
during RESET.
C179 C180 C181
BI OUT
Y12 VDDR4 DVDATA_2 AB2 MR52 1 DNI 2 10K
1uF 1uF 1uF AB4 R56 1 DNI 2 10K A_HSYNC_DAC2
DVDATA_3 OUT 7
6.3V 6.3V 6.3V
DVDATA_4 AB7 MR56 1 DNI 2 10K BIF_CLK_PM_EN
2

CEDAR PRO A11P HF MVE SLT BIN1 TSMC FB12 GPIO_8_R

DVDATA_5 AB8 R53 1 DNI 2 10K GPIO_8_R 6 0 - Disable CLKREQ# power management capability
AB9 MR53 1 DNI 2 10K 1 - Enable CLKREQ# power management capability
DVDATA_6
DVDATA_7 AC7
DVDATA_8 AC8 DDC1 VGA Don't set GENERICC high at reset

DVDATA_9 AD7
DVDATA_10 AC10 AUX1 NC MEMORY VENDOR SELECTION
Y11 DVCLK DVDATA_11 AD9
DVDATA_12 AE8 DDC2 NC [GPIO_5 : GPIO_16]
D
R54 1 DNI 2 10K GPIO_5 Hynix [0:1]
V GPIO_5
6
AE9 P AUX2 NC MR54 1 DNI 2 10K
Samsung [1:0]
DVCNTL_0
L9 R55 1 DNI 2 10K GPIO_16
DVCNTL_1 GPIO_16
6
N9 DVCNTL_2 DDC/AU HDMI MR55 1 DNI 2 10K

DDC/AUX5 TOP DP

DDC6 NC

+1.8V
I2C Debug Access Port
R21 1 2 221R 1% VREFG AC16 VREFG
B R22 1 2 110R 1% B
C53 1 20.1uF 6.3V

CEDAR PRO A11P HF MVE SLT BIN1 TSMC FB12

+3.3V_BUS

B71 2 1 120R

GPU(215-0804070-00)
U1F
B72 2 1 120R

1
Y3
PART 6 OF 15 XOUT_OSC XIN_OSC C91 C90
+1.8V B7 +DPLL_PVDD
1 3
1 2 AF14 DPLL_PVDD 2 4 +3.3V_BUS 0.1uF 0.1uF
1

120R 6.3V 6.3V

27.000MHz

2
C63 C64 C59 U12

4.7uF 1uF 0.1uF AE14 DPLL_PVSS C93 1 212pF 50V 10 XTALOUT XTALIN 1 C92 1 212pF 50V

1
6.3V 6.3V 6.3V
2

4 VDD33_100M R70 R71

VDD_100M 5.1K 5.1K
+1V AB22 XO_IN2 R74 1 2 0R 100MHZ_OUT 5 8 VDD33_27M DNI DNI
B8 XO_IN2 100M_OUT VDD_27M
1 2 +DPLL_VDDC AD14 DPLL_VDDC COMMON(2750013004G)

2
1

120R 7 SS_SEL0
SS_SEL0
C67 C66 3 SS_SEL1
SS_SEL1
1uF 0.1uF AC22 XO_IN1 R75 1 2 0R 27MHZ_OUT 9
XO_IN 27M_OUT

1
6.3V 6.3V
GND_100M 6
2

+1.8V 2 MR70 MR71

B5 P GND_27M 5.1K 5.1K
1 2 +SPV18 H7 SPV18
L GND_PAD 11
L
1

120R
S

2
C58 C61 C62 SL16020DC
X XTALIN
4.7uF 1uF 0.1uF J7 SPVSS T XTALIN AM28 C82 1 DNI 212pF 50V
6.3V 6.3V 6.3V
A
2

L
27.000MHz

+1V
Y2

B9 R31 DNI
1 2 +SPV10 H8 AK28 XTALOUT 1M
SPV10 XTALOUT
2

DNI
1

120R CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.

2

C70 C71 C83 1 DNI 212pF 50V AMD - PLATFORM HARDWARE ENG C 2014 Advanced Micro Devices
1uF
6.3V
0.1uF
6.3V #48, No.1387, ZHANGDONG ROAD This AMD Board schematic and design is the exclusive property of AMD, and

A A
2

+1.8V
B12 CLKTESTA K8 SHANGHAI, CHINA 201203 is provided only to entities under a non-disclosure agreement with AMD

+MPV18 for evaluation purposes. Further distribution or disclosure is strictly

1 2 L8 MPV18
1

120R prohibited. Use of this schematic and design for any purpose other than
CLKTESTB L7
C77 C78 C79 C80 evaluation requires a Board Technology License Agreement with AMD.

AMD makes no representations or warranties of any kind regarding this

4.7uF 10uF 1uF 0.1uF SHEET: CAICOS GPIO STRAP PLL
6.3V 6.3V 6.3V 6.3V schematic and design, including, not limited to, any implied warranty
DNI
2

CEDAR PRO A11P HF MVE SLT BIN1 TSMC FB12 of merchantability or fitness for a particular purpose, and disclaims

responsibility for any consequences resulting from use of the

DATE: Thu Jun 04 06:11:37 2015 REV: 1.0
information included herein.

SHEET NUMBER: 6 OF 21 TITLE:

Caicos G5 VGA+DP+HDMI 25W ASIC, 5.7"

DOCUMENT NUMBER: 105-C982xx-00A

NOTES: NOTE

8 7 6 5 4 3 2 1
LOMBOK/CAICOS/CEDAR DAC1 OPTIONAL ESD PROTECTION DIODES

D2000 A_R_DAC1_F

D2001 A_G_DAC1_F 7

D2002 A_B_DAC1_F 7

See BOM for qualified filters D2003 DDCDATA_DAC1_R 7

+1.8V D2004 DDCCLK_DAC1_R

GPU(215-0804070-00) Pseudo differential RGB should be routed from the ASIC to the display 7
U1G
connector without switching reference plane or running over split plane.

VGA(5260050400G) D2005 A_HSYNC_DAC1_R 7

+VDD1DI PART 7 OF 15
B6 L2001
1 2 AE23 VDD1DI R AM26 A_R_DAC1 1 2 D2006 A_VSYNC_DAC1_R 7

1
120R DNI RB AK26 A_RB_DAC1
VGA 0.047uH
C1052 C1051 C1050 R2003 C2001 C2004 GND
75R 7
1uF 0.1uF 0.01uF 1% 8pF 12pF
6.3V 6.3V 10V 50V 50V
402 DNI DNI

2
AD23 AL25 A_G_DAC1 R2027 1 VGA 2 37.4R 1% +5V_VESA
VSS1DI G
AJ25 A_GB_DAC1
GB VGA(5260050400G)
+1.8V
B2 L2002
1 2 +AVDD AG24 1 2
AVDD D
1

1
120R A VGA
0.047uH
DNI
C1055 C1054 C A_B_DAC1 R2002 C2002 C2005
1 B AH24 R2008 R2005
75R
1uF 0.1uF AG25 A_BB_DAC1 1% 8pF 12pF 2.2K 2.2K
BB VGA
6.3V 6.3V 50V 50V VGA
402 DNI 402
2

2
AE22 AVSSQ R2028 1 VGA 2 37.4R 1%
A_R_DAC1_F
VGA(5260050400G) 7
AH26 A_G_DAC1_F
HSYNC L2003 7
R12 1 2 499R 1% RSET AD22 AJ27 1 2 A_B_DAC1_F
RSET VSYNC 7

1
0.047uH
VGA
R2001 C2003 C2006 DDC1DATA R1006 1 VGA 2 33R DDCDATA_DAC1_R
75R 6 BI 7
CEDAR PRO A11P HF MVE SLT BIN1 TSMC FB12 1% 8pF 12pF
50V 50V DDC1CLK DDCCLK_DAC1_R
402 DNI DNI 6 R1009 1 VGA 2 33R 7
IN

2
R2029 1 VGA 2 37.4R 1%
A_HSYNC_DAC1_R
7
A_VSYNC_DAC1_R
7

+5V_VESA

1
C2011 C2010

1uF 68pF
10V 50V
DNI VGA

2
A_HSYNC_DAC1 VGA(6012000300G)
2 4 A_HSYNC_DAC1_B R2010 1 VGA 2 24R J2000
6 OUT
U1700A A_R_DAC1_F 1 2 A_G_DAC1_F
7 7

1
+5V_VESA 74AHCT1G126GW A_B_DAC1_F 3 4
7
VGA C2007 5 6

1
12pF 7 8
50V
DNI 9 10

2
1
11 12 DDCDATA_DAC1_R
7
A_HSYNC_DAC1_R 13 14 A_VSYNC_DAC1_R
7 7
A_VSYNC_DAC1 2 4 A_VSYNC_DAC1_B R2011 1 VGA 2 24R DDCCLK_DAC1_R 15 16
6 OUT 7
U1701A

1
74AHCT1G126GW HEADER_2X8
VGA
C2008
+5V_VESA 12pF VGA Header
50V
DNI

2
VGA cable: 6110026200G

5
U1700B U1701B

1
74AHCT1G126GW 74AHCT1G126GW
VGA C1750 VGA C1751

0.1uF 0.1uF
6.3V 6.3V
VGA

2
VGA

U1H GPU(215-0804070-00)

PART 8 OF 15

AD19 VDD2DI R2 AM12

R2B AK12

AC19 VSS2DI G2 AL11

Ground AC19 for Cedar G2B AJ11

AE17 A2VDDQ
B2 AK10
B2B AL9
D
A
C
AE19 2
A2VSSQ /
T H2SYNC AL13 A_HSYNC_DAC2
6
V OUT
V2SYNC AJ13 A_VSYNC_DAC2
6
OUT CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.

AE20 A2VDD
AMD - PLATFORM HARDWARE ENG C 2014 Advanced Micro Devices

#48, No.1387, ZHANGDONG ROAD This AMD Board schematic and design is the exclusive property of AMD, and
Y AM10
C AH12 SHANGHAI, CHINA 201203 is provided only to entities under a non-disclosure agreement with AMD

for evaluation purposes. Further distribution or disclosure is strictly

AG13 R2SET COMP AJ9
R2SET prohibited. Use of this schematic and design for any purpose other than

evaluation requires a Board Technology License Agreement with AMD.

AMD makes no representations or warranties of any kind regarding this

CEDAR PRO A11P HF MVE SLT BIN1 TSMC FB12 SHEET: CAICOS DAC
schematic and design, including, not limited to, any implied warranty

of merchantability or fitness for a particular purpose, and disclaims

Install R23 for Cedar
1

responsibility for any consequences resulting from use of the

NC R23 for Caicos DATE: Thu Jun 04 06:11:37 2015 REV: 1.0
information included herein.
R23
715R
DNI
SHEET NUMBER: 7 OF 21 TITLE:16ci203
TITLE:
2

Caicos G5 VGA+DP+HDMI 25W ASIC, 5.7"

DOCUMENT NUMBER: 105-C982xx-00A

NOTES: NOTE
 8 7 6 5 4 3 2 1

LOMBOK/CAICOS/CEDAR Display Port C (Unused)

D D

+1.8V

U1J GPU(215-0804070-00)

DNI
+DPC_VDD18 PART 10 OF 15
B2507
1 2 W6 DPC_PVDD TX2P_DPC0P AA3
120R
TX2M_DPC0N Y2

TX1P_DPC1P Y4
V6 DPC_PVSS
TX1M_DPC1N W5
+1V

TX0P_DPC2P W3
C C
DNI TX0M_DPC2N V2
B2508
1 2 +DPC_VDD10 AA5 DPC_VDD10 TXCCP_DPC3P V4
T
120R AA6 DPC_VDD10 M
D TXCCM_DPC3N U5
P
C

AC5 DPC_VDD18
AC6 DPC_VDD18

Cedar: DPCD_CALR (150-ohm)

RV710: MEM_CALRP1 (243-ohm)

R298 1 DNI 2 150R 1% DPCD_CALR J8 DPC_CALR

AA1 DPC_VSSR
U1 DPC_VSSR
U3 DPC_VSSR
W1 DPC_VSSR
Y6 DPC_VSSR

CEDAR PRO A11P HF MVE SLT BIN1 TSMC FB12

B B

CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.

A AMD - PLATFORM HARDWARE ENG C 2014 Advanced Micro Devices

A
#48, No.1387, ZHANGDONG ROAD This AMD Board schematic and design is the exclusive property of AMD, and

SHANGHAI, CHINA 201203 is provided only to entities under a non-disclosure agreement with AMD

for evaluation purposes. Further distribution or disclosure is strictly

prohibited. Use of this schematic and design for any purpose other than

evaluation requires a Board Technology License Agreement with AMD.

AMD makes no representations or warranties of any kind regarding this

SHEET: CAICOS TMDP C (UNUSED)
schematic and design, including, not limited to, any implied warranty

of merchantability or fitness for a particular purpose, and disclaims

responsibility for any consequences resulting from use of the

DATE: Thu May 28 03:09:00 2015 REV: 1.0
information included herein.

SHEET NUMBER: 9 OF 21 TITLE:

Caicos G5 VGA+DP+HDMI 25W ASIC, 5.7"

DOCUMENT NUMBER: 105-C982xx-00A

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

LOMBOK/CAICOS/CEDAR Power & GND

D D

U1L GPU(215-0804070-00) U1M GPU(215-0804070-00)

+VDDC

PART 12 OF 15 PART 13 OF 15

+MVDD A3 GND GND H14

H13 VDDR1 VDDC N15 A30 GND GND H17

1
H16 VDDR1 VDDC N17 AA13 GND GND H2
1

1
H19 R13 C182 C168 C169 C170 C171 C172 C173 C85 AB10 H20
VDDR1 VDDC GND GND
C120 C121 C122 C123 C124 C125 J10 R16 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF AB15 H6
VDDR1 VDDC GND GND
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
0.01uF 0.1uF 0.01uF 0.1uF 0.01uF 0.1uF J23 VDDR1 VDDC R18 DNI DNI DNI AB6 GND GND J27

2
10V 10V 10V 6.3V 10V 6.3V
DNI DNI J24 VDDR1 VDDC V21 AC9 GND GND J31
2

2
J9 VDDR1 VDDC T12 AD6 GND GND K11

1
K10 VDDR1 VDDC T15 AD8 GND GND K2
K23 T17 C183 C184 C185 C186 C187 C188 C189 C190 AE7 K22
VDDR1 VDDC GND GND
K24 VDDR1 VDDC T20 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF AG12 GND GND K6
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
K9 VDDR1 VDDC U13 AH10 GND GND M6

2
L11 VDDR1 VDDC U16 AH28 GND GND N13
L12 VDDR1 VDDC U18 B10 GND GND N16
L13 VDDR1 VDDC Y21 B12 GND GND N18
G
L20 VDDR1 VDDC V15 B14 GND N GND N21
L21 V17 B16 D P6
VDDR1 VDDC GND GND
1

1
L22 VDDR1 VDDC V20 B18 GND GND P9
C134 C135 C136 C137 C138 C139 C140 Y13 C174 C175 C176 C177 C178 C191 C192 B20 R12
VDDC GND GND
1uF 1uF 0.1uF 1uF 1uF 1uF 0.1uF VDDC Y16 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF 4.7uF B22 GND GND R15
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
VDDC Y18 DNI DNI DNI DNI DNI DNI DNI B24 GND GND R17
2

2
VDDC AA15 B26 GND GND R20

1
VDDC M11 B6 GND GND T13
M12 MC174 MC175 MC176 MC177 MC178 MC191 MC192 B8 T16
VDDC GND GND
1

10uF 10uF 10uF 10uF 10uF 10uF 10uF C1 GND GND T18
MC130 MC131 MC132 MC133 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
DNI DNI DNI DNI C32 GND GND T21

2
4.7uF 4.7uF 4.7uF 4.7uF Overlap cap pair foorprints (0805 with 0603) E28 GND GND T6
6.3V 6.3V 6.3V 6.3V
DNI DNI F10 GND GND U15
2

F12 GND GND U17

C F14 GND GND U20 C
+1.8V F16 U9
GND GND
1

P F18 GND GND V13

C130 C131 C132 C133 AA20 O F2 V16
VDD_CT W M11,M12 of NC pins powered for Cedar GND GND
10uF 10uF 10uF 10uF 1 AA21 VDD_CT E F20 GND GND V18

1
6.3V 6.3V 6.3V 6.3V R
DNI DNI DNI DNI DNI DNI AB20 VDD_CT F22 GND GND Y10
2

C161 C162 C163 AB21 R21 F24 Y15

VDD_CT BIF_VDDC GND GND
Overlap cap pair foorprints (0805 with 0603)
1uF 1uF 0.1uF BIF_VDDC U21 F26 GND GND Y17
6.3V 6.3V 6.3V
F6 GND GND Y20
2

2
F8 GND GND N11
G10 GND GND N12
G27 GND GND AA16
G31 GND GND T11
G8 GND GND R11
L17 NC_VDDRHA

A32 VSS_MECH
L16 NC_VSSRHA AM1 VSS_MECH
Overlap cap pair foorprints AM32 VSS_MECH
+VDDC (0805 with 0603)

M13 VDDCI CEDAR PRO A11P HF MVE SLT BIN1 TSMC FB12
1

M15 VDDCI
C196 MC196 C195 C194 C193 C87 C86 M16 VDDCI
10uF 4.7uF 1uF 1uF 0.1uF 0.1uF 0.1uF M17 VDDCI
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
M18 VDDCI
2

DNI
M20 VDDCI
M21 VDDCI
N20 VDDCI

CEDAR PRO A11P HF MVE SLT BIN1 TSMC FB12

B B

CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.

A AMD - PLATFORM HARDWARE ENG C 2014 Advanced Micro Devices

A
#48, No.1387, ZHANGDONG ROAD This AMD Board schematic and design is the exclusive property of AMD, and

SHANGHAI, CHINA 201203 is provided only to entities under a non-disclosure agreement with AMD

for evaluation purposes. Further distribution or disclosure is strictly

prohibited. Use of this schematic and design for any purpose other than

evaluation requires a Board Technology License Agreement with AMD.

AMD makes no representations or warranties of any kind regarding this

SHEET: CAICOS Power&GND
schematic and design, including, not limited to, any implied warranty

of merchantability or fitness for a particular purpose, and disclaims

responsibility for any consequences resulting from use of the

DATE: Thu May 28 03:09:00 2015 REV: 1.0
information included herein.

SHEET NUMBER: 11 OF 21 TITLE:

Caicos G5 VGA+DP+HDMI 25W ASIC, 5.7"

DOCUMENT NUMBER: 105-C982xx-00A

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

(19) Debug Circuits

D D

JTAG
+3.3V_BUS

1
U1A
GPU(215-0804070-00)

R436
PART 1 OF 15 1K
DNI
TESTEN_LEGACY AF24

2
K7 13 TESTEN
TESTEN
L6 JTAG_TRSTB R38 1 2 1K
JTAG_TRSTB +3.3V_BUS

1
L3 JTAG_TCK
J JTAG_TCK 13

1
T L5 JTAG_TDI R37
JTAG_TDI 13 1K
A JTAG_TDO R39
G JTAG_TDO K4 13 1K
L1 JTAG_TMS
JTAG_TMS 13

2
DNI

2
CEDAR PRO A11P HF MVE SLT BIN1 TSMC FB12

J4004
+3.3V_BUS
HEADER_RECEPT_2X4

JTAG_TDO 7 8
13
JTAG_TDI 5 6
13 JTAG
JTAG_TMS 3 4
13
JTAG_TCK 1 2 TESTEN
13 13

C C

B B

CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.

A AMD - PLATFORM HARDWARE ENG C 2014 Advanced Micro Devices

A
#48, No.1387, ZHANGDONG ROAD This AMD Board schematic and design is the exclusive property of AMD, and

SHANGHAI, CHINA 201203 is provided only to entities under a non-disclosure agreement with AMD

for evaluation purposes. Further distribution or disclosure is strictly

prohibited. Use of this schematic and design for any purpose other than

evaluation requires a Board Technology License Agreement with AMD.

AMD makes no representations or warranties of any kind regarding this

SHEET: Debug Circuit
schematic and design, including, not limited to, any implied warranty

of merchantability or fitness for a particular purpose, and disclaims

responsibility for any consequences resulting from use of the

DATE: Thu May 28 03:09:00 2015 REV: 1.0
information included herein.

SHEET NUMBER: 13 OF 21 TITLE:

Caicos G5 VGA+DP+HDMI 25W ASIC, 5.7"

DOCUMENT NUMBER: 105-C982xx-00A

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

Power Management - Power Gating and Dynamic Voltage Control

+3.3V_BUS

1
+12V_BUS
R857 VDDC_EN
12,18
D 10K
1%
OUT D

3
2
R852 PSEQ_PU R839 1 2 5.1K PSEQ_PU_R 1
11.3K Q851

1
1% MMBT3904

6
C846 Place close

2
PSEQ_12V 2 Q850A 0.1uF to its CTLR
MMDT3904-7 10V
Node 3 DNI

2
1
+3.3V_BUS

3P3_RAMP
R853
1K
1%
1

+5V

2
R850
2.32K
1%

1
2

PSEQ_3V3 5 R622
Q850B 10K
MMDT3904-7 5%
1

2
R851
1K
1% VDDC_REF_IN 18
OUT
2

Rf22 Rf21 Rf20

18 VDDC_FB
IN

1
R671 R672 R650 RFB2
22.1K 34.8K 19.6K
1% 1% 1%

2
C C

MVDD_EN 19
OUT
+12V_BUS +3.3V_BUS

VDDC_FB_IN2

1
VDD_FB_IN1

6
R673
20K
1 DNI
R843
Q606B

2
5.1K
GPIO_15_PWRCNTL_0 2 2N7002DW
6 IN
+VDDC
2

1
+3.3V_BUS

1
SEQ_MVDD_EN# R846 1 2 5.1K MVDD_EN# 5 MR673
Q840B 20K
1

MMDT3904-7

1
R841

2
4.75K

3
1% R674
20K
2

Q606A

2
VDDC_PWR_GOOD R849 1 DNI 2 0R 1 UNNAMED_114_NPN_I571_B Q838 +1.8V_EN GPIO_20_PWRCNTL_1 5 2N7002DW
18 IN OUT 16 6 IN
MMBT3904

1
2

4
1

R847 1 2 5.1K 1V8_EN# 2 MR674

Q840A 20K
R845 MMDT3904-7
8.45K DNI
1%

2
DNI
2

+1.8V_LDO_POK R848 1 DNI 2 5.1K +1V_EN

16 IN OUT 15

B B

MEM VDDC MVDD

SUB BOM SUB BOM SUB BOM

SUBBOM(13B-00920) SUBBOM(13A-01522) SUBBOM(13A-01523)

256Mx16 1.5V 1GHz TOL: +/-3% TOL: +/-3%

HYNIX(13B-00827);SAMSUNG(13B-00828)
CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.

A AMD - PLATFORM HARDWARE ENG C 2014 Advanced Micro Devices

A
MVDD_FB_GS
OUT 19 #48, No.1387, ZHANGDONG ROAD This AMD Board schematic and design is the exclusive property of AMD, and

SHANGHAI, CHINA 201203

1

is provided only to entities under a non-disclosure agreement with AMD

FBR702 for evaluation purposes. Further distribution or disclosure is strictly

FBR8 11K prohibited. Use of this schematic and design for any purpose other than
1%
Vout=0.8(1+FBR7/FBR8) evaluation requires a Board Technology License Agreement with AMD.
2

AMD makes no representations or warranties of any kind regarding this

SHEET: PWR SEQ
schematic and design, including, not limited to, any implied warranty

of merchantability or fitness for a particular purpose, and disclaims

responsibility for any consequences resulting from use of the

MVDD=1.5V FBR8 = 11K DATE: Thu May 28 03:08:58 2015 REV: 1.0
information included herein.

SHEET NUMBER: 14 OF 21 TITLE:

Caicos G5 VGA+DP+HDMI 25W ASIC, 5.7"

DOCUMENT NUMBER: 105-C982xx-00A

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D Linear Regulators D
LDO #1: Vin = +1.5V +/-2% Vout = 1V +/- 2%; Iout = 3A MAX

PCB: 50 to 70mm sq. copper area for cooling

+MVDD +3.3V_BUS

1st: 2480154800G GS7166

1
2nd: 2482083600G EM5107GE

1
C800

10uF R800 R801

6.3V 10K 5.1K
DNI +1V
TOL: +/-3%

2
+5V U800 COMMON(2480154800G)

2
VOUT = 0.8 x (1 + FBR1/FBR2)
3 VIN VOUT 6

1
4 7 1V_FB C802 C804
VDD FB Place it under ASIC

1
10uF 0.1uF

1
1V_REFIN 6.3V 16V
14 +1V_EN 2 EN NC 5 NS800
IN

2
C805

THMPAD
NS_VIA
1uF 2 +1V_PG 1 POK GND 8
OUT

2
1
6.3V

2
C806
GS7133SO

9
0.1uF
6.3V
DNI

2
R805 1 DNI 2 0R 1V_FB_TRACE

1
1
C801
C R803 680pF C
FBR1 1.02K 50V
1%

2
2
1
FBR2=5.36K->Vout=0.95V
FBR800
FBR2 4.02K FBR2=4.02K->Vout=1.00V
1%

2
B B

CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.

AMD - PLATFORM HARDWARE ENG C 2014 Advanced Micro Devices

#48, No.1387, ZHANGDONG ROAD This AMD Board schematic and design is the exclusive property of AMD, and

A SHANGHAI, CHINA 201203 is provided only to entities under a non-disclosure agreement with AMD A
for evaluation purposes. Further distribution or disclosure is strictly

prohibited. Use of this schematic and design for any purpose other than

evaluation requires a Board Technology License Agreement with AMD.

AMD makes no representations or warranties of any kind regarding this

SHEET: 1V
schematic and design, including, not limited to, any implied warranty

of merchantability or fitness for a particular purpose, and disclaims

responsibility for any consequences resulting from use of the

DATE: Thu Jun 04 06:11:37 2015 REV: 1.0
information included herein.

SHEET NUMBER: 15 OF 21 TITLE:

Caicos G5 VGA+DP+HDMI 25W ASIC, 5.7"

DOCUMENT NUMBER: 105-C982xx-00A

NOTES: NOTE

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D D

Linear Regulators
LDO #2: Vin = 3.00V to 3.60V (3.3V +/- 9%) Vout = +1.8V +/- 2%; Iout = 1A MAX

PCB: 50 to 70mm sq. copper area for cooling

+3.3V_BUS +3.3V_BUS

1
C866
1st: 2480154800G GS7166
10uF R863 R862
5.49K 10K 2nd: 2482083600G EM5107GE
6.3V
1% COMMON(2480154800G) +1.8V

2
DNI U861
+5V VOUT = 0.8 x (1 + FBR3/FBR4)

2
3 VIN VOUT 6

1
1
4 7 1.8V_FB C865 C862 C864
VDD FB
R865 180pF 10uF 0.1uF
C 13K
C
1

+1.8V_EN 1.8V_REFIN FBR3 50V 6.3V 16V

14 2 EN NC 5 1%
IN

2
C868

THMPAD

2
1uF 14 +1.8V_LDO_POK 1 POK GND 8
OUT

1
6.3V
2

1
C870
GS7133SO

9
0.1uF FBR861
10V FBR4 10K
DNI 1%

2
R866 1 DNI 2 0R

2
B B

CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.

A AMD - PLATFORM HARDWARE ENG C 2014 Advanced Micro Devices

A
#48, No.1387, ZHANGDONG ROAD This AMD Board schematic and design is the exclusive property of AMD, and

SHANGHAI, CHINA 201203 is provided only to entities under a non-disclosure agreement with AMD

for evaluation purposes. Further distribution or disclosure is strictly

prohibited. Use of this schematic and design for any purpose other than

evaluation requires a Board Technology License Agreement with AMD.

AMD makes no representations or warranties of any kind regarding this

SHEET: 1.8V
schematic and design, including, not limited to, any implied warranty

of merchantability or fitness for a particular purpose, and disclaims

responsibility for any consequences resulting from use of the

DATE: Thu May 28 03:08:59 2015 REV: 1.0
information included herein.

SHEET NUMBER: 16 OF 21 TITLE:

Caicos G5 VGA+DP+HDMI 25W ASIC, 5.7"

DOCUMENT NUMBER: 105-C982xx-00A

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D D

+5V Power
C C

1st source:2480154002G
+12V_BUS 2nd source:2480154001G +5V
REG800 3rd source:2480154000G To Power
3 IN OUT 2

1
APL111750VC
C812 C811 +5V_VESA

GND

TAB
1uF 1uF
16V 6.3V F800
1 2 To VGA/DVI/HDMI

2
200mA 24V

B B

CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.

AMD - PLATFORM HARDWARE ENG C 2014 Advanced Micro Devices

#48, No.1387, ZHANGDONG ROAD This AMD Board schematic and design is the exclusive property of AMD, and

A SHANGHAI, CHINA 201203 is provided only to entities under a non-disclosure agreement with AMD A
for evaluation purposes. Further distribution or disclosure is strictly

prohibited. Use of this schematic and design for any purpose other than

evaluation requires a Board Technology License Agreement with AMD.

AMD makes no representations or warranties of any kind regarding this

SHEET: 5V
schematic and design, including, not limited to, any implied warranty

of merchantability or fitness for a particular purpose, and disclaims

responsibility for any consequences resulting from use of the

DATE: Thu Jun 04 06:11:37 2015 REV: 1.0
information included herein.

SHEET NUMBER: 17 OF 21 TITLE:

Caicos G5 VGA+DP+HDMI 25W ASIC, 5.7"

DOCUMENT NUMBER: 105-C982xx-00A

NOTES: NOTE

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

VDDC and MVDD source

+12V_BUS

1
1

1
Overlap
D R608 R616
L611
D
0R 0R
DNI DNI 0.47uH

2
Overlap +VDDC_Source

1
C633 C615 C616 C617 C619 + C631
0.15uF 10uF 10uF 10uF 10uF 270uF
16V 16V 16V 16V 16V 16V
603 1206 1206 1206 1206 VDDC

2
VDDC DNI DNI VDDC VDDC

Mirrored on PCB Mirrored on PCB 6.3x7 TH

9
8
7
6
5
Input Bulk CAP
Input MLCC

Q601
MDU1514U C614 1 VDDC 2820pF 50V VDDC_FB
VDDC 18 14

Connect to C626 +VDDC

4
3
2
1
R613 1 VDDC 2 47K 1% C612 1 VDDC 20.1uF
UNNAMED_104_CAP_I72_A 16V
VDDC_UGATE_CTR R601 1 VDDC 2 0R VDDC_UGATE1 +VDDC
18
603
L601 0.47uH
VDDC_PHASE 1 2
18
VDDC

1
R619
2.2R
VDDC C623 C624 C629 C630 + C625 + C626
C 9 C
8
7
6
5
805
0.1uF 0.015uF 10uF 10uF 820uF 820uF

2
10V 10V 6.3V 6.3V 2.5V 2.5V

UNNAMED_104_CAP_I24_A
402 402 6.3 x 9 mm, TH 6.3 x 9 mm, TH

2
1
DNI DNI DNI DNI VDDC VDDC
Q603
MDU1511RH C608

VDDC 1800pF
50V
VDDC

2
603

Output MLCC
4
3
2
1

Output Bulk CAPs

9
8
7
6
5
Place across
LS MOSFET

Q604
MDU1511RH RC snubber values shown
VDDC
are for reference only, +3.3V_BUS

tuning is required

603

1
VDDC_LGATE_CTR R603 1 VDDC 2 0R VDDC_LGATE_1
18
4
3
2
1
R604 1VDDC_LGATE_CTR
DNI 2 0R VDDC_LGATE_2 R699
5.49K
603 1%
VDDC

2
VDDC_EN 12,14
IN

1
C699
+12V_BUS 0.0012uF R696
8.45K

1
50V
VDDC 1%

2
R666 VDDC

2
0R
DNI <PositionInPackage>

1
2
R612

UNNAMED_104_GS7210A_I97_NC
412K
1%
VDDC

2
C611 1 VDDC 20.0068uF
UNNAMED_104_CAP_I54_A 25V
R618 1 VDDC 2 0R VDDC_BOOT
1

0603
UNNAMED_104_CAP_I18_A

R609,MR609 share pad

C605 +VDDC Sense +VDDC from ASIC side
0.1uF R609 1 DNI 2 0R VDDC_FB
18 14

13

14

15

16

18
17
B 25V
VDDC
B
2

MR609 1 VDDC 2 0R VDDC_FB_TRACE

18

1
VOUT
NC

EN

TON

GND
GND
BOOT
VDDC_UGATE_CTR 12 NS600
18 UGATE
U601 1 NS_VIA Sense Point
VOUT
R605 1 VDDC 2 20K 1% 18 VDDC_PHASE 11
VDDC_PHASE PHASE

2
VDDC VDDA 2 UNNAMED_104_CAP_I113_A R607 1 VDDC 2 2.2R
+5V
+5V 10 UNNAMED_104_GS7210A_I97_OCSET RFB
OCSET
GS7210A-ATQ VDDC_FB_TRACE
FB 3 UNNAMED_104_GS7210A_I97_FB R690 1 VDDC 2 0R R611 1 VDDC 2 10K 1% 18

1
R614 1 VDDC 2 UNNAMED_104_CAP_I112_A
2.2R 9 VDDP PGOOD 4 C613 1 VDDC 256pF 50V
1

1
C606
C603 1uF MR690 VDDC_FB
0R OUT 14,18
10V
1uF VDDC DNI

2
LGATE

VSSP

GND

REFIN
10V
VDDC
2

2
VDDC_LGATE_CTR
18

VDDC_PWR_GOOD 14
OUT
1

C622

0.1uF
10V
VDDC_REF_IN

DNI
2
IN

CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.

14

A AMD - PLATFORM HARDWARE ENG C 2014 Advanced Micro Devices

A
#48, No.1387, ZHANGDONG ROAD This AMD Board schematic and design is the exclusive property of AMD, and

SHANGHAI, CHINA 201203 is provided only to entities under a non-disclosure agreement with AMD

for evaluation purposes. Further distribution or disclosure is strictly

prohibited. Use of this schematic and design for any purpose other than

evaluation requires a Board Technology License Agreement with AMD.

AMD makes no representations or warranties of any kind regarding this

SHEET: VDDC
schematic and design, including, not limited to, any implied warranty

of merchantability or fitness for a particular purpose, and disclaims

responsibility for any consequences resulting from use of the

DATE: Thu May 28 03:08:57 2015 REV: 1.0
information included herein.

SHEET NUMBER: 18 OF 21 TITLE:

Caicos G5 VGA+DP+HDMI 25W ASIC, 5.7"

DOCUMENT NUMBER: 105-C982xx-00A

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

Regulator for MVDD

D D

1
UNNAMED_121_CAP_I123_A
C705 C706

1uF 0.1uF

1
6.3V 10V
MVDD MVDD
C C

2
R714 R713
10K 10K
DNI DNI

2
C703
1 2MVDD
UNNAMED_121_CAP_I128_B
UNNAMED_121_CAP_I128_A
+MVDD

L701 2.2uH
+3.3V_BUS 0.1uF 25V
1 2

1
MVDD
UNNAMED_121_CAP_I125_A
1

C729 C723 C724 + C726

1

C711 U700 22uF 22uF 22uF 820uF +MVDD

23
22
21
20
19
18
R730 10V 10V 10V 2.5V
0.01uF MVDD R712 1 MVDD 2 UNNAMED_121_CAP_I116_A
39.2K 1% C712 1 MVDD 20.0068uF 25V DNI DNI DNI MVDD

2
5.49K 10V

PGND
VCC
VIN
SS

BOOT

LX
1%
2

MVDD

1
MVDD
1 UNNAMED_121_GS9238_I175_PGOOD
2

POK

NS900
2 17 C725 C727 C728
14 MVDD_EN
IN EN LX
1

1
3 UNNAMED_121_GS9238_I175_PFM 16 0.1uF 0.015uF 390pF
PFM LX
1

C730 C713 10V 10V 50V

4 AGND 15 MVDD MVDD MVDD

2
R731 PGND
0.1uF 5 FB 14 0.1uF
8.45K PGND
1

10V 6.3V
DNI 1% 6 UNNAMED_121_GS9238_I175_TON
TON 13 MVDD
2

2
DNI
R715
PGND
12
2

10K PGND
MVDD AIN
VIN
VIN

LX
LX
2

GS9238-ATQ-R
7
8
9

10
11
FBR7
1

R710 1 MVDD 2 10K 1% MVDD_VOL_FB

Use +VDDC_Source to share L601 to eliminate PCIe 12V current slew rate over spec issue(0.1A/us)
+VDDC_Source R705 C710 1 MVDD 21000pF 50V
100K
1%
MVDD MVDD_FB_GS
IN 14
2

R734 1 MVDD 2 UNNAMED_121_CAP_I156_A

2.2R
1

C715 C716 C717 C718 C734

B 10uF 10uF 4.7uF 0.15uF 1uF B
16V 16V 16V 16V 16V
MVDD MVDD DNI MVDD MVDD
2

CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.

A AMD - PLATFORM HARDWARE ENG C 2014 Advanced Micro Devices

A
#48, No.1387, ZHANGDONG ROAD This AMD Board schematic and design is the exclusive property of AMD, and

SHANGHAI, CHINA 201203 is provided only to entities under a non-disclosure agreement with AMD

for evaluation purposes. Further distribution or disclosure is strictly

prohibited. Use of this schematic and design for any purpose other than

evaluation requires a Board Technology License Agreement with AMD.

AMD makes no representations or warranties of any kind regarding this

SHEET: MVDD
schematic and design, including, not limited to, any implied warranty

of merchantability or fitness for a particular purpose, and disclaims

responsibility for any consequences resulting from use of the

DATE: Thu May 28 03:08:58 2015 REV: 1.0
information included herein.

SHEET NUMBER: 19 19 OF 21 21 TITLE:16ci203

TITLE:

Caicos G5 VGA+DP+HDMI 25W ASIC, 5.7"

DOCUMENT NUMBER: 105-C982xx-00A

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

MEMORY CHANNEL A

Debug
GDDR5 2pcs 128Mx32 (1GB)

D D

CH A

JTAG/I2C
GPIO

POWER REGULATORS

From +12V
DAC1
+VDDC RGB Filters

+MVDD HVGA

FAN

From +12V LINEAR:

ROM
Straps
+5V_VESA, +5V_VESA2

From +12V_BUS SL TMDS HDMI

C C
TMDP-F AC Coupling Caps Connector
+5V BIOS

From +MVDD converter(+0.95V):

5V_VESA
Thermal

PCIE_VDDC, DPLL_VDDC, DDC AUXDDC3

Speed control
DPx_VDD10, SPV10, MEM_VREF

GPIO17
& temperature
INTERRUPT HPD1
From +3.3V Direct:
sense D+/D-

VDDR3, AVDD
FAN Temp. Sensing

TS_FDO
Built-in PWM

From 3.3V Linear (1.8V)

PCIE_PVDD, PCIE_VDDR, VDDR4,

Dynamic Power Management

DPLL_PVDD, SPV18, MPV18, DL TMDS

VDD1DI, VDD2DI, AVDD, AVDDQ, AC Coupling Caps DP

TMDPB

DPx_PVDD, DPx_VDD18, VDD_CT,

POWER DELIVERY
TSVDD

Connector

Oland LE AUX5

B HPD2 B
100MHz

XO_IN2
27MHz

XO_IN Clock

Temperature Critical
CTF XTALIN

PCI-Express 27MHz Xtal

Power Sequencing
Circuit

Caicos G5 1GB
+3.3V_BUS VGA+DP+HDMI
+12V_BUS

PCI-Express Bus

CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC.

A AMD - PLATFORM HARDWARE ENG C 2014 Advanced Micro Devices

A
#48, No.1387, ZHANGDONG ROAD This AMD Board schematic and design is the exclusive property of AMD, and

SHANGHAI, CHINA 201203 is provided only to entities under a non-disclosure agreement with AMD

for evaluation purposes. Further distribution or disclosure is strictly

prohibited. Use of this schematic and design for any purpose other than

evaluation requires a Board Technology License Agreement with AMD.

AMD makes no representations or warranties of any kind regarding this

SHEET: Diagram
schematic and design, including, not limited to, any implied warranty

of merchantability or fitness for a particular purpose, and disclaims

responsibility for any consequences resulting from use of the

DATE: Thu May 21 06:47:46 2015 REV: 1.0
information included herein.

SHEET NUMBER: 20 OF 21 TITLE:16ci203

TITLE:

Caicos G5 VGA+DP+HDMI 25W ASIC, 5.7"

DOCUMENT NUMBER: 105-C982xx-00A

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

AMD
TITLE:

Caicos G5 VGA+DP+HDMI 25W ASIC, 5.7" DOCUMENT NUMBER: 105-C982xx-00A DATE: Thu May 28 02:44:26 2015 SHEET NUMBER: 21 OF 21 REV: 1.0

CONFIDENTIAL AND PROPRIETARY TO ADVANCED MICRO DEVICES INC. C 2014 Advanced Micro Devices
ENGINEER: NOTES:
This AMD Board schematic and design is the exclusive property of AMD, and is provided only to entities under a non-disclosure agreement with AMD
AMD - PLATFORM HARDWARE ENG
for evaluation purposes. Further distribution or disclosure is strictly prohibited. Use of this schematic and design for any purpose other than #48, No.1387, ZHANGDONG ROAD
REVISION HISTORY Tony Yang NOTE evaluation requires a Board Technology License Agreement with AMD. AMD makes no representations or warranties of any kind regarding this

schematic and design, including, not limited to, any implied warranty of merchantability or fitness for a particular purpose, and disclaims
SHANGHAI, CHINA 201203
responsibility for any consequences resulting from use of the information included herein.

SCH PCB Date REVISION DESCRIPTON

Rev Rev
1.00 00A 05/28/15 1. Initial release

D D

C C

B B

A A

8 7 6 5 4 3 2 1