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Unit3 microprocessor(full notes)

Bachelor's of computer Application (BCA) (University of Calicut)

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Unit 3:

Types of Programming techniques: Looping:

• The programming technique used to instruct the microprocessor to
repeat tasks is called looping.
• This task is accomplished by using jump instructions.
• Looping is a programming technique which implies that the task
has to be repeated.
• Looping is achieved by instructions that change the sequence of
instruction to perform the task again.
• Loops are of two types:
• Continuous loops: which perform the task continuously.
• Conditional loops: repeats a task until some specific data
conditions are satisfied.
• Continuous loops is one which runs continuously without ever
stopping until the system is reset.
• Continuous loop is implemented using unconditional JUMP
instruction (JMP).
• The flow control is as shown below:

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Conditional loops:

• Conditional loops are loops which run until a given condition is

fulfilled.
• When the aforementioned condition is fulfilled, the control is sent
to another location mentioned along with the condition.
• Conditional loops are implemented using conditional JUMP
instructions like JZ, JNZ, JP, JM etc.

Looping in the 8085 Microprocessor:

• 8085 Microprocessor does not have a dedicated instruction for

looping.
• Looping in 8085 is achieved through the use of JUMP instructions.
• The JMP instruction is the unconditional jump, whereas the other
instructions provide a condition, which if followed change the
sequence of execution of instructions.

Generation of Time delay in 8085 Microprocessor:

• The delay used in different places to stimulate clocks, or counters
or other areas.
• When delay subroutine is executed, microprocessor does not
execute other tasks.
• For delay we are using instruction execution times.
• Executing some instructions in a loop, delay is generated.
• There are some methods of generating delays:
1. By using single 8 bit register.
2. By using 16 bit register pair.
3. By using Nested loop.

1. By using 8 bit register:

Consider the following instructions:

MVI B, 0AH //Move value 10H to B.
REPEAT: DCR B //Decrement B until it becomes 0.

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JNZ REPEAT

For first instruction to execute it takes 7T states.

For second instruction it takes 4T states.
For third instruction it takes 10T states. When condition
becomes false it takes 7T.

Time delay Inside loop= (4T+10T)*10

= 14T*10 =140T states
=140T-3T =137T states.
Time delay outside loop=7T

Total Delay Generated= delay outside loop + delay

Inside loop = 137T+7T =144T states.

Suppose 8085 processor is connected to a crystal

oscillator of 2Mhz frequency , then the frequency inside
processor is = 2 Mhz.
So T=1/frequency inside = 0.5 Micro second.
So total Time delay generated = 144T = 144*0.5=72
Microsecond delay is generated.

For Maximum delay using Register:

MVI C, FFH //7T

LOOP: DCR C //4T
JNZ LOOP //10T/7T

Total delay generated= 7T + 254(4+10) + (4+7) = 3574T=3574*0.5=

1787 Microsecond.

2. Delay using 16 bit Register pair:

LXI B, 2348H //10T

LOOP: DCX B //6T

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MOV A,C //4T

ORA B //4T
JNZ LOOP // 10T/7T

• The hexadecimal value of 2348H can be written in decimal as

9092.
• Delay generated= 10T + 9091(6+4+4+10)T + (6+4+4+7)T
= 218215T= 218215*0.5 Microseconds=
109107.5 Microsecond, which is very high delay generated.

3. Loop inside loop delay:

MVI C, OAH //7T

LOOP: MVI B, FFH
REPEAT: DCR B //3574T
JNZ REPEAT
DCR C //4T
JNZ LOOP //10T/7T

Delay generated =(3574T+4T+10T)10 +7T -3T = 35884T

=35884*0.5= 17,942 microsecond.

Stack in 8085 Microprocessors:

The stack is a reserved area of the memory in RAM where we can store
temporary information. Interestingly, the stack is a shared resource as it
can be shared by the microprocessor and the programmer. The
programmer can use the stack to store data. And the microprocessor uses
the stack to execute subroutines. The 8085 has a 16-bit register known as
the 8Stack Pointer.9
This register9s function is to hold the memory address of the stack. This
control is given to the programmer. The programmer can decide the

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starting address of the stack by loading the address into the stack pointer
register at the beginning of a program.
The stack works on the principle of First In Last Out. The memory
location of the most recent data entry on the stack is known as the Stack
Top.
We use two main instructions to control the movement of data into a
stack and from a stack. These two instructions are PUSH and POP.

PUSH – This is the instruction we use to write information on the stack.

POP – This is the instruction we use to read information from the stack.

Explanation of the code

LXI SP, 8000H – The address of the stack pointer is set to 8000H by
loading the number into the stack pointer register.

LXI H, 1234H – Next, we add a number to the HL pair. The most

significant two bits will enter the H register. The least significant two
bits will enter the L register.

PUSH H – The PUSH command will push the contents of the H register
first to the stack. Then the contents of the L register will be sent to the
stack. So the new stack top will hold 34H.

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POP D – The POP command will remove the contents of the stack and
store them to the DE register pair. The top of the stack clears first and
enters the E register. The new top of the stack is 12H now. This one
clears last and enters the D register. The contents of the DE register pair
is now 1234H.

HLT – HLT indicates that the program execution needs to stop.

• Push - Stack grows – 2 Bytes (put data on stack)

• Pop – Stack shrinks – 2 Bytes (get data from stack)
• Push – Stack grows and address reduces.
Decrement and store.

Consider another example showing stack operation of Push and Pop..

• Push- stack grows and address decrements(put data on stack)

• Pop- stack shrinks and address increments(get data from stack)

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Subroutine in 8085 Microprocessors:

• It is a small program written and stored separately and it can be

called whenever required.
• Block of instructions which carries out a specific and well defined
task.
• It divides the main program into 2 parts.
• It provides value return to same point.
• Transfers control to subroutine.
• Execute the subroutine.
• Revert to main program.
• Above points happen only when subroutine occurs in the main
program.
• CALL instruction is used to call a subroutine.
• RET , return instruction will help return to the main program after
executing the subroutine.

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• PC or program counter is a 16 bit register which stores the address

of the next instruction to be executed.
• Now PC1432, But on reaching 1432 it moves to subroutine and
contents of PC needs to be stored in stack.

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• Now PC2392 , When execution reaches RET statement

PC2396 and then return statement returns the control back to
main program and again using POP operations, the contents will be
taken back from stack.
• PC1432 and again program starts execution.

CALL statement in 8085 Microprocessors:

• CALL instruction is a subroutine instruction.

• They are of two types: unconditional and conditional CALL.
• Unconditional Call instruction –
CALL address is the format for unconditional call instruction. After
execution of this instruction program control is transferred to a sub-
routine whose starting address is specified in the instruction. Value
of PC (Program Counter) is transferred to the memory stack and
value of SP (Stack Pointer) is decremented by 2.

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• Conditional Call instruction –

In these instructions program control is transferred to subroutine
and value of PC is pushed into stack only if condition is satisfied.

RET(RETURN) statement in 8085 Microprocessors:

• RET instruction is a subroutine instruction.
• They are of two types: unconditional and conditional RET.

Unconditional Return instruction –

RET is the instruction used to mark the end of sub-routine. It has no
parameter. After execution of this instruction program control is
transferred back to main program from where it had stopped. Value of PC
(Program Counter) is retrieved from the memory stack and value of SP
(Stack Pointer) is incremented by 2.
Conditional Return instruction –
By these instructions program control is transferred back to main program

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and value of PC is popped from stack only if condition is satisfied. There

is no parameter for return instruction.

Advantages of Subroutine –
1. Decomposing a complex programming task into simpler steps.
2. Reducing duplicate code within a program.
3. Enabling reuse of code across multiple programs.
4. Improving tractability or makes debugging of a program easy.

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Interrupts in 8085 microprocessor:

When microprocessor receives any interrupt signal from peripheral(s)

which are requesting its services, it stops its current execution and
program control is transferred to a sub-routine by
generating CALL signal and after executing sub-routine by
generating RET signal again program control is transferred to main
program from where it had stopped.
When microprocessor receives interrupt signals, it sends an
acknowledgement (INTA) to the peripheral which is requesting for its
service.
Interrupts can be classified into various categories based on different
parameters:
1. Hardware and Software Interrupts –
When microprocessors receive interrupt signals through pins
(hardware) of microprocessor, they are known as Hardware
Interrupts. There are 5 Hardware Interrupts in 8085
microprocessor. They are – INTR, RST 7.5, RST 6.5, RST 5.5,
TRAP
Software Interrupts are those which are inserted in between the
program which means these are mnemonics of microprocessor.
There are 8 software interrupts in 8085 microprocessor. They
are – RST 0, RST 1, RST 2, RST 3, RST 4, RST 5, RST 6, RST 7.

2. Vectored and Non-Vectored Interrupts –

Vectored Interrupts are those which have fixed vector address
(starting address of sub-routine) and after executing these,
program control is transferred to that address.

1. Maskable and Non-Maskable Interrupts –

Maskable Interrupts are those which can be disabled or ignored
by the microprocessor. These interrupts are either edge-
triggered or level-triggered, so they can be disabled. INTR, RST

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7.5, RST 6.5, RST 5.5 are maskable interrupts in 8085

microprocessor.
Non-Maskable Interrupts are those which cannot be disabled or
ignored by microprocessor. TRAP is a non-maskable interrupt.
It consists of both level as well as edge triggering and is used
in critical power failure conditions.
Priority of Interrupts –
When microprocessor receives multiple interrupt requests
simultaneously, it will execute the interrupt service request (ISR)
according to the priority of the interrupts.

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8255A Programmable Peripheral devices:

The 8255A is a general purpose programmable I/O device designed to

transfer the data from I/O to interrupt I/O under certain conditions as
required. It can be used with almost any microprocessor.
It consists of three 8-bit bidirectional I/O ports (24I/O lines) which can
be configured as per the requirement.

Ports of 8255A

8255A has three ports, i.e., PORT A, PORT B, and PORT C.

• Port A contains one 8-bit output latch/buffer and one 8-bit input
buffer.
• Port B is similar to PORT A.
• Port C can be split into two parts, i.e. PORT C lower (PC0-PC3)
and PORT C upper (PC7-PC4) by the control word.
These three ports are further divided into two groups, i.e. Group A
includes PORT A and upper PORT C. Group B includes PORT B and
lower PORT C. These two groups can be programmed in three different
modes, i.e. the first mode is named as mode 0, the second mode is named
as Mode 1 and the third mode is named as Mode 2.

Operating Modes

8255A has three different operating modes −

• Mode 0 − In this mode, Port A and B is used as two 8-bit ports and
Port C as two 4-bit ports. Each port can be programmed in either
input mode or output mode where outputs are latched and inputs
are not latched. Ports do not have interrupt capability.
• Mode 1 − In this mode, Port A and B is used as 8-bit I/O ports. They
can be configured as either input or output ports. Each port uses

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three lines from port C as handshake signals. Inputs and outputs are
latched.
• Mode 2 − In this mode, Port A can be configured as the
bidirectional port and Port B either in Mode 0 or Mode 1. Port A
uses five signals from Port C as handshake signals for data transfer.
The remaining three signals from Port C can be used either as
simple I/O or as handshake for port B.

Features of 8255A

The prominent features of 8255A are as follows −

• It consists of 3 8-bit IO ports i.e. PA, PB, and PC.
• Address/data bus must be externally demux'd.
• It is TTL compatible.
• It has improved DC driving capability.

8255 Architecture

The following figure shows the architecture of 8255A −

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8255A Signal description(Pin diagram):

Data Bus Buffer

It is a tri-state 8-bit buffer, which is used to interface the microprocessor

to the system data bus. Data is transmitted or received by the buffer as
per the instructions by the CPU. Control words and status information is
also transferred using this bus.

Read/Write Control Logic

This block is responsible for controlling the internal/external transfer of

data/control/status word. It accepts the input from the CPU address and
control buses, and in turn issues command to both the control groups.

CS

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It stands for Chip Select. A LOW on this input selects the chip and
enables the communication between the 8255A and the CPU. It is
connected to the decoded address, and A0 & A1 are connected to the
microprocessor address lines.

WR

It stands for write. This control signal enables the write operation. When
this signal goes low, the microprocessor writes into a selected I/O port or
control register.

RESET

This is an active high signal. It clears the control register and sets all ports
in the input mode.

RD

It stands for Read. This control signal enables the Read operation. When
the signal is low, the microprocessor reads the data from the selected I/O
port of the 8255.

A0 and A1

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These input signals work with RD, WR, and one of the control signal.
Following is the table showing their various signals with their result.

Microprocessor 8254 Programmable Interval Timer:

8254 is a device designed to solve the timing control problems in a

microprocessor. It has 3 independent counters, each capable of
handling clock inputs up to 10 MHz and size of each counter is 16 bit.
It operates in +5V regulated power supply and has 24 pin signals. All
modes are software programmable. The 8254 is an advanced version of
8253 which did not offered the feature of read back command.
The basic block diagram of 8254 is:

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It has 3 counters each with two inputs (Clock and Gate) and one output.
Gate is used to enable or disable counting. When any value of count is
loaded and value of gate is set(1), after every step value of count is
decremented by 1 until it becomes zero.
Depending upon the value of CS, A1 and A0 we can determine
addresses of selected counter.

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Applications –
1. To generate accurate time delay
2. As an event counter
3. Square wave generator
4. Rate generator
5. Digital one shot

8237 DMA Controller:

Direct Memory Access:

• DMA or direct memory access is the technology that allows direct
transfer of data between memory and I/O devices when the
microprocessor is busy.
• DMA is the capability provided by some bus architectures that
allows data to be sent directly from an attached device(disk drive
or any peripheral device) to the memory on computers
motherboard, the microprocessor is freed and hence speed of
system increases.

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• It is the data transfer without the involvement of microprocessor or

when microprocessor is busy performing other operations.

Introduction of 8237

• Direct Memory Access (DMA) is a method of allowing data to be

moved from one location to another in a computer without
intervention from the central processor (CPU).
• It is also a fast way of transferring data within (and sometimes
between) computer.
• The DMA I/O technique provides direct access to the memory
while the microprocessor is temporarily disabled.

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• The DMA controller temporarily borrows the address bus, data bus
and control bus from the microprocessor and transfers the data
directly from the external devices to a series of memory locations
(and vice versa).

Basic DMA Operation:

• Two control signals are used to request and acknowledge a direct

memory access (DMA) transfer in the microprocessor-based
system.
1. The HOLD signal as an input(to the processor) is used to
request a DMA action.
2. The HLDA signal as an output that acknowledges the DMA
action.
• When the processor recognizes the hold, it stops its execution and
enters hold cycles.
• HOLD input has higher priority than INTR or NMI.
• The only microprocessor pin that has a higher priority than a
HOLD is the RESET pin.
• HLDA becomes active to indicate that the processor has placed its
buses at high-impedance state.

Basic DMA Definitions

• Direct memory accesses normally occur between an I/O device and

memory without the use of the microprocessor.
1. A DMA read transfers data from the memory
to the I/O device.
2. A DMA write transfers data from an I/O device
to memory.
• The system contains separate memory and I/O control signals.
• Hence the Memory & the I/O are controlled simultaneously

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• The DMA controller provides memory with its address, and the
controller signal selects the I/O device during the transfer.
• Data transfer speed is determined by speed of the memory device
or a DMA controller.
• In many cases, the DMA controller slows the speed of the system
when transfers occur.
• The serial PCI (Peripheral Component Interface) Express bus
transfers data at rates exceeding DMA transfers.
• This in modern systems has made DMA is less important.

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The 8237 DMA Controller

• The 8237 supplies memory & I/O with control signals and memory
address information during the DMA transfer.
• It is actually a special-purpose microprocessor whose job is high-
speed data transfer between memory and I/O

8237 is not a discrete component in modern microprocessor-based

systems.
It appears within many system controller chip sets
8237 is a four-channel device compatible with 8086/8088, adequate
for small systems.
Expandable to any number of DMA channel inputs
8237 is capable of DMA transfers at rates up to 1.6MB per second.
Each channel is capable of addressing a full
64K-byte section of memory.

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8237 Internal Registers

CAR

• The current address register holds a 16-bit memory address used

for the DMA transfer.
• each channel has its own current address
register for this purpose.
• When a byte of data is transferred during a DMA operation, CAR
is either incremented
or decremented. depending on how it is programmed

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CWCR

• The current word count register programs a channel for the number
of bytes to transferred during a DMA action.

CR

• The command register programs the operation of the 8237 DMA

controller.
• The register uses bit position 0 to select the memory-to-memory
DMA transfer mode.
1. Memory-to-memory DMA transfers use DMA channel
2. DMA channel 0 to hold the source address
3. DMA channel 1 holds the destination address

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BA and BWC

• The base address (BA) and base word count (BWC) registers are
used when auto-initialization is selected for a channel.
• In auto-initialization mode, these registers are used to reload the
CAR and CWCR after the DMA action is completed.

MR

• The mode register programs the mode of operation for a channel.

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• Each channel has its own mode register as selected by bit positions
1 and 0.
1. Remaining bits of the mode register select operation, auto-
initialization, increment/decrement, and mode for the channel

BR

• The bus request register is used to request

a DMA transfer via software.
1. very useful in memory-to-memory transfers, where an
external signal is not available to begin the DMA transfer

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MRSR

• The mask register set/reset sets or clears the channel mask.

1. if the mask is set, the channel is disabled
2. the RESET signal sets all channel masks
to disable them

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MSR

• The mask register clears or sets all of

the masks with one command instead of individual channels, as
with the MRSR.

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SR

• The status register shows status of each DMA channel. The TC bits
indicate if the channel has reached its terminal count (transferred
all its bytes).
• When the terminal count is reached, the DMA transfer is
terminated for most modes
of operation.
• The request bits indicate whether the DREQ input for a given
channel is active.

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VCC

POWER: a5V supply.

VSS

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GROUND: Ground.

CLK Input

CLOCK INPUT:Clock Input controls the internal operations of the

8237A and its rate of data transfers.

CS Input

CHIP SELECT:Chip Select is an active low input used to select the

8237A as an I/O device during the Idle cycle. This allows CPU
communication on the data bus.

RESET Input

RESET: Reset is an active high input which clears the Command, Status,
Request and Temporary registers. It also clears the first/ last flip/flop
and sets the Mask register. Following a Reset the device is in the Idle
cycle.

READY Input

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READY: Ready is an input used to extend the memory read and write
pulses from the 8237A to accommodate slow memories or I/O
peripheral devices. Ready must not make transitions during its specified
setup/hold time.

HLDA Input

HOLD ACKNOWLEDGE: The active high Hold Acknowledge from

the CPU indicates that it has relinquished control of the system busses.

DREQ0 ±DREQ3 Input

DMA REQUEST: The DMA Request lines are individual asynchronous

channel request inputs used by peripheral circuits to obtain DMA
service. In fixed Priority, DREQ0 has the highest priority and DREQ3
has the lowest priority. A request is generated by activating the DREQ
line of a channel. DACK will acknowledge the recognition of DREQ
signal.

DB0 ±DB7

DATA BUS: The Data Bus lines are bidirectional three-state signals
connected to the system data bus. The outputs are enabled in the
Program condition during the I/O Read to output the contents of an
Address register, a Status register, the Temporary register or a Word
Count register to the CPU. The outputs are disabled and the inputs are

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read during an I/O Write cycle when the CPU is programming the
8237A control registers. During DMA cycles the most significant 8 bits
of the address are output onto the data bus to be strobed into an external
latch by ADSTB. In memory-to-memory operations, data from the
memory comes into the 8237A on the data bus during the read-from-
memory transfer. In the write-to-memory transfer, the data bus outputs
place the data into the new memory location.

IOR Input/Output

I/O READ: I/O Read is a bidirectional active low three-state line. In the
Idle cycle, it is an input control signal used by the CPU to read the
control registers. In the Active cycle, it is an output control signal used
by the 8237A to access data from a peripheral during a DMA Write
transfer.

IOW Input/Output

I/O WRITE: I/O Write is a bidirectional active low three-state line. In

the Idle cycle, it is an input control signal used by the CPU to load
information into the 8237A. In the Active cycle, it is an output control
signal used by the 8237A to load data to the peripheral during a DMA
Read transfer.

EOP Input/Output

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END OF PROCESS: End of Process is an active low bidirectional

signal. Information concerning the completion of DMA services is
available at the bidirectional EOP pin.

A0 ±A3 Input/Output

ADDRESS: The four least significant address lines are bidirectional

three-state signals. In the Idle cycle they are inputs and are used by the
CPU to address the register to be loaded or read. In the Active cycle they
are outputs and provide the lower 4 bits of the output address.

A4 ±A7 Output

ADDRESS: The four most significant address lines are three-state

outputs and provide 4 bits of address. These lines are enabled only
during the DMA service.

HRQ Output

HOLD REQUEST: This is the Hold Request to the CPU and is used to
request control of the system bus. If the corresponding mask bit is clear,
the presence of any valid DREQ causes 8237A to issue the HRQ.

DACK0 ±DACK3 Output

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DMA ACKNOWLEDGE: DMA Acknowledge is used to notify the

individual peripherals when one has been granted a DMA cycle. The
sense of these lines is programmable. Reset initializes them to active
low.

AEN Output

ADDRESS ENABLE:Address Enable enables the 8-bit latch containing

the upper 8 address bits onto the system address bus. AEN can also be
used to disable other system bus drivers during DMA transfers. AEN is
active HIGH.

ADSTB Output

ADDRESS STROBE: The active high, Address Strobe is used to strobe

the upper address byte into an external latch.

MEMR Output

MEMORY READ: The Memory Read signal is an active low three-state

output used to access data from the selected memory location during a
DMA Read or a memory-to-memory transfer.

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MEMW Output

MEMORY WRITE: The Memory Write is an active low three-state

output used to write data to the selected memory location during a DMA
Write or a memory-to-memory transfer.

PIN5 Input

PIN5: This pin should always be at a logic HIGH level.

Interrupt-driven data transfer in 8085

• Here data transfer takes place with an interrupt signal.
• When device is ready to transfer data , corresponding I/O port
sends an interrupt to the processor.
• With the interrupt entire set of instructions are executed.

Downloaded by Dr Senthil VVIT ([email protected])

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Downloaded by Dr Senthil VVIT ([email protected])