CA Classes-51-55

Computer Architecture Unit 2
References:
 David Salomon, (2008), Computer Organisation, NCC Blackwell.
 John L. Hennessy and David A. Patterson, Computer Architecture:
A Quantitative Approach, (4th Ed.), Morgan Kaufmann Publishers
 Joseph D. Dumas II; Computer Architecture; CRC Press
 Nicholas P. Carter; Schaum’s outline of computer Architecture;
Mc. Graw-Hill Professional
E-references:
 http://publib.boulder.ibm.com/infocenter/zos/basics/topic/com.ibm.zos.z
concepts/zconcepts_75.html/ Retrieved on 30-03-2012
 http://www.ibm.com/search/csass/search?sn=mh&q=multiprocessing
%20system&lang=en&cc=us&/ Retrieved on 31-03-2012
Manipal University Jaipur B1648 Page No. 51

Unit 3 Instruction Set Principles

Structure:
3.1 Introduction
Objectives
3.2 Classifying instruction set architecture
Zero-address instructions
One-address instructions
Two-address instructions
Three-address instructions
3.3 Memory Addressing
3.4 Address Modes for Signal Processing
3.5 Operations in the instruction sets
Fetch & decode
Execution cycle (instruction execution)
3.6 Instructions for Control Flow
3.7 MIPS Architecture
3.8 Summary
3.9 Glossary
3.10 Terminal Questions
3.11 Answers
3.1 Introduction
In the previous unit, you have studied about fundamentals of computer
architecture and design. Now we will study in detail about the instruction set
and its principles.
The instruction set or the instruction set architecture (ISA) is the set of basic
instructions that a processor understands. In other words, an instruction set,
or instruction set architecture (ISA), is the part of the computer architecture
related to programming, including the native data types, instructions,
registers, addressing modes, memory architecture, interrupt and exception
handling, and external I/O. There are a number of instructions in a program
that have to be accessed in a particular sequence. This encourages us to
describe the issue of instruction and its sequence which we will study in this
unit. In this unit, you will study the fundamentals involved in instruction set
architecture and design. Firstly, the operations in the instruction sets,

instruction set architecture, memory locations and addresses, memory

addressing, abstract model of the main memory, and instructions for control
flow need to be categorised. Also, we will discuss about MIPS
(Microprocessor without Interlocked Pipeline Stages) architecture.
Objectives:
After studying this unit, you should be able to:
 classify instruction set architecture
 identify memory addressing
 explain address modes for signal processing
 list the various operations in the instruction sets
 recognise instructions for control flow
 describe MIPS architecture along with its characteristics
3.2 Classifying Instruction Set Architecture

The reference manuals provided with a computer system contain a
description of its physical and logical structure. This gave a description of
the internal construction of the CPU, as well as the processor registers
available and their logical competences. The manuals explain all the
hardware-executed instructions, their binary code format, and an accurate
definition of each instruction very well. The control unit of the CPU deduces
each code instruction and present the essential control functions required to
process the instruction.
The instruction format is generally represented in a rectangular box
denoting the bits of the instruction as they appear in memory words or in a
control register. The bits of the instruction are separated into groups called
fields.
The most common fields found in instruction formats are:
1. An operation code field that specifies the operation to be performed.
2. An address field that designates a memory address or a processor
register.
3. A mode field that specifies the way the operand or the effective address
is determined.
Apart from these fields some other special fields can also be employed, for
example a field that gives the number of shifts in a shift-type instruction.
Instruction’s operation code field is known as a collection of bits that
describes a variety of processor operations, such as add, subtract,

complement, and shift. A variety of alternatives for choosing the operands
from the given address is specified by the bits that define the mode field of
the instruction code. Execution of operations is done by some data stored in
memory or processor registers through specification received by computer
instructions. Operands are identified by a memory address that resides in
memory while the ones residing in processor registers are given by a
register address.
A register address is a binary number of k bits that defines one of
2k registers in the CPU. Thus, a CPU with 16 processor registers
R0 through R15 will have a register address field of four bits. The binary
number 0101, for example, will designate register R5. Instructions in
computers can be of different lengths containing varying number of
addresses. The following are the different types of instruction formats:
3.2.1 Zero-address instructions
In zero-address machines, both operands are assumed to be stored at a
default location. The stack is used as the source of the input operands
machines and the result goes back into the stack. Stack is a LIFO (last-in-
first-out) data structure which is supported by all the processors, whether or
not they are zero-address machines. LIFO implies that the last item placed
on the stack is the first item to be taken out of the stack.
All operations on this type of machine assume that the required input
operands are the top two values on the stack. The result of the operation is
placed on top of the stack. Table 3.1 gives some sample instructions for the
stack machines. Notice that the first two instructions are not zero-address
instructions. These two are special instructions that use a single address
and are used to move data between memory and stack.

Table 3.1: Sample Stack Machine Instructions
The zero-address format is used by all other instructions. Now, we will see
how the stack machine converts the arithmetic expression we studied the
earlier subsections. In these machines, the statement:
A=B+C*D-E+F+A
is translated to the following code:
push E ; <E>
push C ; <C, E>
push D ; <D, C, E>
mult ;<C*D, E>
push B ; <B, C*D, E>
add ;<B+C*D, E>
sub ;<B+C*D-E>
push F ; <F, B+D*C-E>
add ;<F+B+D*C-E>
push A ; <A, F+B+D*C-E>
add ;<A+F+B+D*C-E>
pop A ; <>
On the right, we show the state of the stack after executing each instruction.
The top element of the stack is shown on the left. Notice that we pushed E
early because we need to subtract it from (B+C*D).

CA Classes-51-55

Uploaded by

Copyright:

Available Formats

CA Classes-51-55

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

CA Classes-51-55

Uploaded by

Copyright:

Available Formats

Computer Architecture Unit 2

Manipal University Jaipur B1648 Page No. 51

Unit 3 Instruction Set Principles

Manipal University Jaipur B1648 Page No. 52

instruction set architecture, memory locations and addresses, memory

3.2 Classifying Instruction Set Architecture

describes a variety of processor operations, such as add, subtract,

Manipal University Jaipur B1648 Page No. 54

Table 3.1: Sample Stack Machine Instructions

Manipal University Jaipur B1648 Page No. 55

You might also like