Intel ProcessPXA255 Developers Manual
Intel ProcessPXA255 Developers Manual
Intel ProcessPXA255 Developers Manual
Developer’s Manual
March, 2003
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Contents
1 Introduction...................................................................................................................................1-1
1.1 Intel® XScale™ Microarchitecture Features......................................................................1-1
1.2 System Integration Features..............................................................................................1-1
1.2.1 Memory Controller ................................................................................................1-2
1.2.2 Clocks and Power Controllers...............................................................................1-2
1.2.3 Universal Serial Bus (USB) Client.........................................................................1-2
1.2.4 DMA Controller (DMAC) .......................................................................................1-3
1.2.5 LCD Controller ......................................................................................................1-3
1.2.6 AC97 Controller ....................................................................................................1-3
1.2.7 Inter-IC Sound (I2S) Controller .............................................................................1-3
1.2.8 Multimedia Card (MMC) Controller .......................................................................1-3
1.2.9 Fast Infrared (FIR) Communication Port...............................................................1-3
1.2.10 Synchronous Serial Protocol Controller (SSPC)...................................................1-4
1.2.11 Inter-Integrated Circuit (I2C) Bus Interface Unit....................................................1-4
1.2.12 GPIO.....................................................................................................................1-4
1.2.13 UARTs ..................................................................................................................1-4
1.2.14 Real-Time Clock (RTC).........................................................................................1-5
1.2.15 OS Timers.............................................................................................................1-5
1.2.16 Pulse-Width Modulator (PWM) .............................................................................1-5
1.2.17 Interrupt Control ....................................................................................................1-5
1.2.18 Network Synchronous Serial Protocol Port...........................................................1-5
2 System Architecture .....................................................................................................................2-1
2.1 Overview............................................................................................................................2-1
2.2 Intel® XScale™ Microarchitecture Implementation Options..............................................2-2
2.2.1 Coprocessor 7 Register 4 - PSFS Bit ...................................................................2-2
2.2.2 Coprocessor 14 Registers 0-3 - Performance Monitoring.....................................2-3
2.2.3 Coprocessor 14 Register 6 and 7- Clock and Power Management......................2-3
2.2.4 Coprocessor 15 Register 0 - ID Register Definition ..............................................2-3
2.2.5 Coprocessor 15 Register 1 - P-Bit ........................................................................2-4
2.3 I/O Ordering .......................................................................................................................2-5
2.4 Semaphores ......................................................................................................................2-5
2.5 Interrupts............................................................................................................................2-5
2.6 Reset .................................................................................................................................2-6
2.7 Internal Registers...............................................................................................................2-7
2.8 Selecting Peripherals vs. General Purpose I/O .................................................................2-7
2.9 Power on Reset and Boot Operation .................................................................................2-8
2.10 Power Management...........................................................................................................2-8
2.11 Pin List ...............................................................................................................................2-8
2.12 Memory Map....................................................................................................................2-18
2.13 System Architecture Register Summary ..........................................................................2-21
3 Clocks and Power Manager .........................................................................................................3-1
3.1 Clock Manager Introduction...............................................................................................3-1
3.2 Power Manager Introduction..............................................................................................3-2
3.3 Clock Manager...................................................................................................................3-2
Figures
2-1 Block Diagram ...........................................................................................................................2-2
2-2 Memory Map (Part One) — From 0x8000_0000 to 0xFFFF FFFF..........................................2-19
2-3 Memory Map (Part Two) — From 0x0000_0000 to 0x7FFF FFFF ..........................................2-20
3-1 Clocks Manager Block Diagram ................................................................................................3-3
4-1 General-Purpose I/O Block Diagram .........................................................................................4-2
4-2 Interrupt Controller Block Diagram ..........................................................................................4-21
4-3 PWMn Block Diagram..............................................................................................................4-39
4-4 Basic Pulse Width Waveform ..................................................................................................4-43
5-1 DMAC Block Diagram................................................................................................................5-1
5-2 DREQ timing requirements........................................................................................................5-3
5-3 No-Descriptor Fetch Mode Channel State.................................................................................5-6
5-4 Descriptor Fetch Mode Channel State.......................................................................................5-8
5-5 Little Endian Transfers.............................................................................................................5-10
6-1 General Memory Interface Configuration...................................................................................6-2
6-2 SDRAM Memory System Example............................................................................................6-5
6-3 Static Memory System Example................................................................................................6-6
6-4 External to Internal Address Mapping Options ........................................................................6-19
6-5 Basic SDRAM Timing Parameters...........................................................................................6-29
6-6 SDRAM_Read_diffbank_diffrow ..............................................................................................6-29
6-7 SDRAM_read_samebank_diffrow ...........................................................................................6-30
6-8 SDRAM_read_samebank_samerow .......................................................................................6-30
6-9 SDRAM_write ..........................................................................................................................6-31
6-10 SDRAM 4-Beat Read/ 4-Beat Write To Different Partitions.....................................................6-31
6-11 SDRAM 4-Beat Write / 4-Write Same Bank, Same Row .........................................................6-32
6-12 SMROM Read Timing Diagram Half-Memory Clock Frequency .............................................6-39
6-13 Burst-of-Eight Synchronous Flash Timing Diagram (non-divide-by-2 mode) ..........................6-41
16-6 Motorola SPI* Frame Protocols for SPO and SPH Programming (single
transfers) .................................................................................................................................16-9
16-7 National Semiconductor Microwire* Frame Protocol (multiple transfers) ..............................16-10
16-8 National Semiconductor Microwire* Frame Protocol (single transfers) .................................16-10
16-9 Programmable Serial Protocol (multiple transfers)................................................................16-11
16-10 Programmable Serial Protocol (single transfers)...................................................................16-12
16-11 TI SSP with SSCR[TTE]=1 and SSCR[TTELP]=0.................................................................16-13
16-12 TI SSP with SSCR[TTE]=1 and SSCR[TTELP]=1.................................................................16-14
16-13 Motorola SPI with SSCR[TTE]=1...........................................................................................16-14
16-14 National Semiconductor Microwire with SSCR1[TTE]=1.......................................................16-15
16-15 PSP mode with SSCR1[TTE]=1 and SSCR1[TTELP]=0 (slave to frame) .............................16-15
16-16 PSP mode with SSCR1[TTE]=1 and SSCR1[TTELP]=0 (master to frame) ..........................16-16
16-17 PSP mode with SSCR1[TTE]=1 and SSCR1[TTELP]=1 (must be slave to
frame) ....................................................................................................................................16-16
17-1 Example UART Data Frame....................................................................................................17-3
17-2 Example NRZ Bit Encoding – (0b0100 1011...........................................................................17-4
17-3 IR Transmit and Receive Example ..........................................................................................17-9
17-4 XMODE Example. ...................................................................................................................17-9
Tables
2-1 CPU Core Fault Register Bit Definitions....................................................................................2-3
2-2 ID Bit Definitions ........................................................................................................................2-4
2-3 PXA255 Processor ID Values....................................................................................................2-4
2-4 Effect of Each Type of Reset on Internal Register State ...........................................................2-6
2-5 Processor Pin Types .................................................................................................................2-8
2-6 Pin & Signal Descriptions for the PXA255 Processor................................................................2-9
2-7 Pin Description Notes ..............................................................................................................2-17
2-8 System Architecture Register Address Summary ...................................................................2-21
3-1 Core PLL Output Frequencies for 3.6864 MHz Crystal .............................................................3-5
3-2 95.85 MHz Peripheral PLL Output Frequencies for 3.6864 MHz Crystal ..................................3-5
3-3 147.46 MHz Peripheral PLL Output Frequencies for 3.6864 MHz Crystal ................................ 3-6
3-4 Power Mode Entry Sequence Table .......................................................................................3-20
3-5 Power Mode Exit Sequence Table .........................................................................................3-20
3-6 Power and Clock Supply Sources and States During Power Modes .....................................3-22
3-7 PMCR Bit Definitions ...............................................................................................................3-23
3-8 PCFR Bit Definitions................................................................................................................3-24
3-9 PWER Bit Definitions ...............................................................................................................3-25
3-10 PRER Bit Definitions................................................................................................................3-26
3-11 PFER Bit Definitions ................................................................................................................3-27
3-12 PEDR Bit Definitions................................................................................................................3-28
3-13 PSSR Bit Definitions................................................................................................................3-29
3-14 PSPR Bit Definitions................................................................................................................3-30
3-15 PMFW Register Bitmap and Bit Definitions .............................................................................3-31
3-16 PGSR0 Bit Definitions .............................................................................................................3-32
3-17 PGSR1 Bit Definitions .............................................................................................................3-32
3-18 PGSR2 Bit Definitions .............................................................................................................3-33
3-19 RCSR Bit Definitions ...............................................................................................................3-34
3-20 CCCR Bit Definitions ...............................................................................................................3-35
Revision History
Date Revision Description
The PXA255 processor is a 17x17mm 256-pin PBGA package configuration for high performance.
The 17x17mm package has a 32-bit memory data bus and the full assortment of peripherals.
Refer to the Intel® XScale™ Microarchitecture for the Intel® PXA255 Processor User’s Manual
for more details.
• DMA Controller
• LCD Controller
• AC97
• I2S
• MultiMediaCard
• FIR Communication
• Synchronous Serial Protocol Port
• I2C
• General Purpose I/O pins
• UARTs
• Real-Time Clock
• OS Timers
• Pulse Width Modulation
• Interrupt Control
The 3.6864-MHz crystal drives a core Phase Locked Loop (PLL) and a Peripheral PLL. The PLLs
produce selected clock frequencies to run particular functional blocks.
The 32.768-kHz crystal provides an optional clock source that must be selected after a hard reset.
This clock drives the Real Time Clock (RTC), Power Management Controller, and Interrupt
Controller. The 32.768-kHz crystal is on a separate power island to provide an active clock while
the processor is in sleep mode.
Power management controls the transition between the turbo/run, idle, and sleep operating modes.
Two dedicated DMA channels allow the LCD Controller to support single- and dual-panel
displays. Passive monochrome mode supports up to 256 gray-scale levels and passive color mode
supports up to 64K colors. Active color mode supports up to 64K colors.
1.2.12 GPIO
Each GPIO pin can be individually programmed as an output or an input. Inputs can cause
interrupts on rising or falling edges. Primary GPIO pins are not shared with peripherals while
secondary GPIO pins have alternate functions which can be mapped to the peripherals.
1.2.13 UARTs
The processor provides three Universal Asynchronous Receiver/Transmitters. Each UART can be
used as a slow infrared (SIR) transmitter/receiver based on the Infrared Data Association Serial
Infrared (SIR) Physical Layer Link Specification.
The STUART’s transmit and receive pins are multiplexed with the Fast Infrared Communication
Port.
The HWUART’s pins are multiplexed with the PCMCIA control pins. Because of this, these
HWUART pins operate at the same voltage as the memory bus. Also, since the PCMCIA pin
nPWE is used for variable-latency input/output (VLIO), while using these pins for the HWUART,
VLIO is unavailable. The HWUART pins are also available over the BTUART pins. When
operating over the BTUART pins, the HWUART pins operate at the I/O voltage.
1.2.15 OS Timers
The OS Timers can be used to provide a 3.68-MHz reference counter with four match registers.
These registers can be configured to cause interrupts when equal to the reference counter. One
match register can be used to cause a watchdog reset.
2.1 Overview
The PXA255 processor is an integrated system-on-a-chip microprocessor for high performance,
low power portable handheld and handset devices. It incorporates the Intel® XScale™
microarchitecture with on-the-fly frequency scaling and sophisticated power management to
provide industry leading MIPs/mW performance. The PXA255 processor is ARM* Architecture
Version 5TE instruction set compliant (excluding floating point instructions) and follows the
ARM* programmer’s model.
The processor’s memory interface supports a variety of memory types to allow design flexibility.
Support for the connection of two companion chips permits a glueless interface to external devices.
An integrated LCD display controller provides support for displays up to 640x480 pixels, and
permits 1-, 2-, 4-, and 8-bit grayscale and 8- or 16-bit color pixels. A 256 entry/512 byte palette
RAM provides flexibility in color mapping.
A set of serial devices and general system resources provide computational and connectivity
capability for a variety of applications. Refer to Figure 2-1 for an overview of the microprocessor
system architecture.
RTC
Color or
Grayscale Memory
OS Timer LCD Controller
Controller
PWM(2)
Int.
Controller
Clocks & Variable
DMA Controller
Power Man.
Peripheral Bus
Latency I/O ASIC
and Bridge
I2S System Bus Control
General Purpose I/O
Most of these options are specified within the coprocessor register space. The processor does not
implement any coprocessor registers beyond those defined in the Intel® XScale™
microarchitecture. The coprocessor registers which are ASSP specific, as stated in the Intel®
XScale™ Microarchitecture for the Intel® PXA255 Processor User’s Manual, order number
278793, are defined in the following sections.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
PSFS
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved.
[31:6] —
Read undefined.
Power Source Fault Status
0 = nVDD_FAULT or nBATT_FAULT pin has not been asserted since it was
last cleared by a reset or the CPU.
5 PSFS 1 = nVDD_FAULT or nBATT_FAULT pin was asserted and PMCR[IDAE] =
1.
Read only, write ignored.
Cleared by Hardware, Watchdog, and GPIO Resets.
Reserved.
[4:0] —
Read undefined.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Implementation 8 7 6 5 4 3 2 1 0
Architecture
Trademark
generation
Revision
Revision
Number
Product
Product
Version
Core
Core
Reset 0 1 1 0 1 0 0 1 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0
A0 0x6905_2D06 0x6926_4013
Loads and stores to internal addresses are generally completed more quickly than those issued to
external addresses. The difference in completion time allows one operation to be received before
another operation, but completed after the second operation.
In the following sequence, the store to the address in r4 is completed before the store to the address
in r2 because the first store waits for memory in the queue while the second is not delayed.
If the two stores are control operations that must be completed in order, the recommended sequence
is to insert a load to an unbuffered, uncached memory page followed by an operation that depends
on data from the load:
ldr r5, [r6] ; load from external unbuffered, uncached address ([r2] if possible)
2.4 Semaphores
The Swap (SWP) and Swap Byte (SWPB) instructions, as described in the ARM* Architecture
reference, may be used for semaphore manipulation. No on-chip master or process can access a
memory location between the load and store portion of a SWP or SWPB to the same location.
Note: Semaphore coherency may be interrupted because an external companion chip that uses the
MBREQ/MBGNT handshake can take ownership of the bus during a locked sequence. To allow
semaphore manipulation by external companion chips, the software must manage coherency.
2.5 Interrupts
The interrupt controller is described in detail in Section 4.2, “Interrupt Controller”. All on-chip
interrupts are enabled, masked, and routed to the core FIQ or IRQ. Each interrupt is enabled or
disabled at the source through an interrupt mask bit. Generally, all interrupt bits in a unit are ORed
together and present a single value to the interrupt controller.
Each interrupt goes through the Interrupt Controller Mask Register and then the Interrupt
Controller Level Register directs the interrupt into either the IRQ or FIQ. If an interrupt is taken,
the software may read the Interrupt Controller Pending Register to identify the source. After it
identifies the interrupt source, software is responsible for servicing the interrupt and clearing it in
the source unit before exiting the service routine.
Note: Clearing interrupts may take a delay. To allow the status bit to clear before returning from an
interrupt service routine (ISR), clear the interrupt early in the routine.
2.6 Reset
The processor can be reset in any of three ways: Hardware, Watchdog, and GPIO resets. Each is
described in more detail in Section 3.4, “Resets and Power Modes” on page 3-6.
• Hardware reset results from asserting the nRESET pin and forces all units into reset state.
• Watchdog reset results from a time-out in the OS Timer and may be used to recover from
runaway code. Watchdog reset is disabled by default and must be enabled by software.
• GPIO reset is a “soft reset” that is less destructive than Hardware and Watchdog resets.
Each type of reset affects the state of the processor pins. Table 2-4 shows each pin’s state after each
type of reset.
Leaving Sleep Mode causes a Sleep Mode reset. Unlike other resets, Sleep Mode resets do not
change the state of the pins.
The Reset Controller Status Register (RCSR) contains information on the type of reset, including
Sleep Mode resets.
Table 2-4. Effect of Each Type of Reset on Internal Register State (Sheet 1 of 2)
Unit Sleep Mode GPIO Reset Watchdog Reset Hard Reset
Table 2-4. Effect of Each Type of Reset on Internal Register State (Sheet 2 of 2)
Unit Sleep Mode GPIO Reset Watchdog Reset Hard Reset
Byte and halfword accesses to internal registers are not permitted and yield unpredictable results.
Register space where a register is not specifically mapped is defined as reserved space. Reading or
writing reserved space causes unpredictable results.
The processor does not use all register bit locations. The unused bit locations are marked reserved
and are allocated for future use. Write reserved bit locations as zeros. Ignore the values of these bits
during reads because they are unpredictable.
To allocate a peripheral to a pin, disable the GPIO function for that pin, then map the peripheral
function onto the pin by selecting the proper alternate function for the pin. Some GPIOs have
multiple alternate functions. After a function is selected for a pin, all other functions are excluded.
For this reason some peripherals are mapped to multiple GPIOs, as shown in Section 4.1.2, “GPIO
Alternate Functions” on page 4-2. Multiple mapping does not mean multiple instances of a
peripheral - only that the peripheral is connected to the pins in several ways.
When the system deasserts nRESET and nTRST, the processor deasserts nRESET_OUT a
specified time later and the device attempts to boot from physical address location 0x0000_0000.
The BOOT_SEL[2:0] pins are sampled when reset is deasserted and let the user specify the type
and width of memory device from which the processor attempts to boot. The software can read the
pins as described in Section 6.10.2, “Boot Time Defaults” on page 6-72.
Note: In low power modes, ensure that input pins are not floating and output pins are not driven by an
external device that opposes how the processor is driving that pin. In either case, the system will
draw excess current. Current draw that varies in sleep mode or varies greatly between parts is
typically a sign of floating pins.
Section 3.4, “Resets and Power Modes” describes the modes in detail.
IC CMOS input
OC CMOS output
OCZ CMOS output, Hi-Z
ICOCZ CMOS bidirectional, Hi-Z
IA Analog Input
OA Analog output
IAOA Analog bidirectional
SUP Supply pin (either VCC or VSS)
Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 1 of 9)
Pin Name Type Signal Descriptions Reset State Sleep State
Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 2 of 9)
Pin Name Type Signal Descriptions Reset State Sleep State
SDCLK[1] OCZ SDRAM Clocks (output) Connect SDCLK[1] and Driven Low Driven Low
SDCLK[2] to the clock pins of SDRAM in bank pairs 0/1
and 2/3, respectively. They are driven by either the
internal memory controller clock, or the internal memory
controller clock divided by 2. At reset, all clock pins are
free running at the divide by 2 clock speed and may be
SDCLK[2] OC turned off via free running control register bits in the Driven Low Driven Low
memory controller. The memory controller also provides
control register bits for clock division and deassertion of
each SDCLK pin. SDCLK[2:1] control register assertion
bits are always deasserted upon reset.
nCS[5]/
ICOCZ
GPIO[33]
nCS[4]/
ICOCZ
GPIO[80]
Static chip selects. (output) Chip selects to static
nCS[3]/ memory devices such as ROM and Flash. Individually
ICOCZ Hi-Z - Note [1] Note [4]
GPIO[79] programmable in the memory configuration registers.
nCS[5:0] can be used with variable latency I/O devices.
nCS[2]/
ICOCZ
GPIO[78]
nCS[1]/
ICOCZ
GPIO[15]
Static chip select 0. (output) Chip select for the boot
nCS[0] ICOCZ Driven High Note [4]
memory. nCS[0] is a dedicated pin.
Read/Write for static interface. (output) Signals that the
RD/nWR OCZ Driven Low Holds last state
current transaction is a read or write.
Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 3 of 9)
Pin Name Type Signal Descriptions Reset State Sleep State
Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 4 of 9)
Pin Name Type Signal Descriptions Reset State Sleep State
L LCLK/ LCD line clock. (output) Indicates the start of a new line.
ICOCZ Hi-Z - Note [1] Note [3]
GPIO[75] Also referred to as Hsync.
L PCLK/ LCD pixel clock. (output) Clocks valid pixel data into the
ICOCZ Hi-Z - Note [1] Note [3]
GPIO[76] LCD’s line shift buffer.
Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 5 of 9)
Pin Name Type Signal Descriptions Reset State Sleep State
BTCTS/
ICOCZ Bluetooth UART Clear-to-Send. (input) Hi-Z - Note [1] Note [3]
GPIO[44]
BTRTS/
ICOCZ Bluetooth UART Data-Terminal-Ready. (output) Hi-Z - Note [1] Note [3]
GPIO[45]
Standard UART and ICP Pins
IrDA receive signal. (input) Receive pin for the FIR
IRRXD/
ICOCZ function. Hi-Z - Note [1] Note [3]
GPIO[46]
Standard UART receive. (input)
IrDA transmit signal. (output) Transmit pin for the
IRTXD/
ICOCZ Standard UART, SIR and FIR functions. Hi-Z - Note [1] Note [3]
GPIO[47]
Standard UART transmit. (output)
HWUART Pins
Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 6 of 9)
Pin Name Type Signal Descriptions Reset State Sleep State
Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 7 of 9)
Pin Name Type Signal Descriptions Reset State Sleep State
Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 8 of 9)
Pin Name Type Signal Descriptions Reset State Sleep State
Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 9 of 9)
Pin Name Type Signal Descriptions Reset State Sleep State
GPIO Reset Operation: Configured as GPIO inputs by default after any reset. The input buffers for these pins
are disabled to prevent current drain and the pins are pulled high with 10K to 60K internal resistors. The input
[1] paths must be enabled and the pullups turned off by clearing the Read Disable Hold (RDH) bit described in
Section 3.5.7, “Power Manager Sleep Status Register (PSSR)” on page 3-29. Even though sleep mode sets the
RDH bit, the pull-up resistors are not re-enabled by sleep mode.
Crystal oscillator pins: These pins are used to connect the external crystals to the on-chip oscillators. Refer to
[2] Section 3.3.1, “32.768 kHz Oscillator” on page 3-4 and Section 3.3.2, “3.6864 MHz Oscillator” on page 3-4 for
details on Sleep Mode operation.
GPIO Sleep operation: During the transition into sleep mode, the state of these pins is determined by the
corresponding PGSRn. See Section 3.5.10, “Power Manager GPIO Sleep State Registers (PGSR0, PGSR1,
PGSR2)” and Section 4.1.3.2, “GPIO Pin Direction Registers (GPDR0, GPDR1, GPDR2)” on page 4-8. If
[3] selected as an input, this pin does not drive during sleep. If selected as an output, the value contained in the
Sleep State Register is driven out onto the pin and held there while the PXA255 processor is in Sleep Mode.
GPIOs configured as inputs after exiting sleep mode cannot be used until PSSR[RDH] is cleared.
Static Memory Control Pins: During Sleep Mode, these pins can be programmed to either drive the value in the
Sleep State Register or to be placed in Hi-Z. To select the Hi-Z state, software must set the FS bit in the Power
[4] Manager General Configuration Register. If PCFR[FS] is not set, then during the transition to sleep these pins
function as described in [3], above. For nWE, nOE, and nCS[0], if PCFR[FS] is not set, they are driven high by
the Memory Controller before entering sleep. If PCFR[FS] is set, these pins are placed in Hi-Z.
PCMCIA Control Pins: During Sleep Mode: Can be programmed either to drive the value in the Sleep State
[5] Register or to be placed in Hi-Z. To select the Hi-Z state, software must set PCFR[FP]. If it is not set, then during
the transition to sleep these pins function as described in [3], above.
[6] During sleep, this supply may be driven low. This supply must never be high impedance.
Note: Accessing reserved portions of the memory map will give unpredictable results.
The PCMCIA interface is divided into Socket 0 and Socket 1 space. These two sockets are each
subdivided into I/O, memory and attribute space. Each socket is allocated 256 MB of memory
space.
Figure 2-2. Memory Map (Part One) — From 0x8000_0000 to 0xFFFF FFFF
0xFFFF_FFFF
Reserved (64 MB)
0xFC00_0000
0xF800_0000 Reserved (64 MB)
Figure 2-3. Memory Map (Part Two) — From 0x0000_0000 to 0x7FFF FFFF
0x7FFF FFFF
Reserved (64 MB)
0x7C00_0000
0x7800_0000 Reserved (64 MB)
0x3C00_0000
0x3800_0000 PCMCIA/CF- Slot 1 (256 MB)
0x3400_0000
0x3000_0000
0x2C00_0000
0x2800_0000
PCMCIA/CF - Slot 0 (256MB)
0x2400_0000
0x2000_0000
Reserved (64 MB)
0x1C00_0000
Reserved (64 MB)
0x1800_0000
Static Chip Select 5 (64 MB)
0x1400_0000
Static Chip Select 4 (64 MB)
0x1000_0000
Static Chip Select 3 (64 MB)
0x0C00_0000
Static Chip Select 2 (64 MB)
0x0800_0000
Static Chip Select 1 (64 MB)
0x0400_0000
0x0000_0000 Static Chip Select 0 (64 MB)
DMA
0x4000_0000
Controller
0x4000_0000 DCSR0 DMA Control / Status Register for Channel 0
0x4000_0004 DCSR1 DMA Control / Status Register for Channel 1
0x4000_0008 DCSR2 DMA Control / Status Register for Channel 2
0x4000_000C DCSR3 DMA Control / Status Register for Channel 3
0x4000_0010 DCSR4 DMA Control / Status Register for Channel 4
0x4000_0014 DCSR5 DMA Control / Status Register for Channel 5
0x4000_0018 DCSR6 DMA Control / Status Register for Channel 6
0x4000_001C DCSR7 DMA Control / Status Register for Channel 7
0x4000_0020 DCSR8 DMA Control / Status Register for Channel 8
0x4000_0024 DCSR9 DMA Control / Status Register for Channel 9
0x4000_0028 DCSR10 DMA Control / Status Register for Channel 10
0x4000_002C DCSR11 DMA Control / Status Register for Channel 11
0x4000_0030 DCSR12 DMA Control / Status Register for Channel 12
0x4000_0034 DCSR13 DMA Control / Status Register for Channel 13
0x4000_0038 DCSR14 DMA Control / Status Register for Channel 14
0x4000_003C DCSR15 DMA Control / Status Register for Channel 15
0x4000_00f0 DINT DMA Interrupt Register
0x4000_0100 DRCMR0 Request to Channel Map Register for DREQ 0
0x4000_0104 DRCMR1 Request to Channel Map Register for DREQ 1
0x4000_0108 DRCMR2 Request to Channel Map Register for I2S receive Request
0x4000_010C DRCMR3 Request to Channel Map Register for I2S transmit Request
0x4000_0110 DRCMR4 Request to Channel Map Register for BTUART receive Request
0x4000_0114 DRCMR5 Request to Channel Map Register for BTUART transmit Request.
0x4000_0118 DRCMR6 Request to Channel Map Register for FFUART receive Request
0x4000_011C DRCMR7 Request to Channel Map Register for FFUART transmit Request
0x4000_0120 DRCMR8 Request to Channel Map Register for AC97 microphone Request
0x4000_0124 DRCMR9 Request to Channel Map Register for AC97 modem receive Request
0x4000_0128 DRCMR10 Request to Channel Map Register for AC97 modem transmit Request
0x4000_012C DRCMR11 Request to Channel Map Register for AC97 audio receive Request
0x4000_0130 DRCMR12 Request to Channel Map Register for AC97 audio transmit Request
0x4000_0134 DRCMR13 Request to Channel Map Register for SSP receive Request
0x4000_0138 DRCMR14 Request to Channel Map Register for SSP transmit Request
0x4000_013C DRCMR15 Request to Channel Map Register for NSSP receive Request
0x4000_0140 DRCMR16 Request to Channel Map Register for NSSP transmit Request
0x4000_0144 DRCMR17 Request to Channel Map Register for ICP receive Request
0x4000_0148 DRCMR18 Request to Channel Map Register for ICP transmit Request
0x4000_014C DRCMR19 Request to Channel Map Register for STUART receive Request
0x4000_0150 DRCMR20 Request to Channel Map Register for STUART transmit Request
0x4000_0154 DRCMR21 Request to Channel Map Register for MMC receive Request
0x4000_0158 DRCMR22 Request to Channel Map Register for MMC transmit Request
0x4000_015C DRCMR23 Reserved
0x4000_0160 DRCMR24 Reserved
0x4000_0164 DRCMR25 Request to Channel Map Register for USB endpoint 1 Request
0x4000_0168 DRCMR26 Request to Channel Map Register for USB endpoint 2 Request
0x4000_016C DRCMR27 Request to Channel Map Register for USB endpoint 3 Request
0x4000_0170 DRCMR28 Request to Channel Map Register for USB endpoint 4 Request
0x4000_0174 DRCMR29 Request to Channel Map Register for HWUART receive Request
0x4000_0178 DRCMR30 Request to Channel Map Register for USB endpoint 6 Request
0x4000_017C DRCMR31 Request to Channel Map Register for USB endpoint 7 Request
0x4000_0180 DRCMR32 Request to Channel Map Register for USB endpoint 8 Request
0x4000_0184 DRCMR33 Request to Channel Map Register for USB endpoint 9 Request
0x4000_0188 DRCMR34 Request to Channel Map Register for HWUART transmit Request
0x4000_018C DRCMR35 Request to Channel Map Register for USB endpoint 11 Request
0x4000_0190 DRCMR36 Request to Channel Map Register for USB endpoint 12 Request
0x4000_0194 DRCMR37 Request to Channel Map Register for USB endpoint 13 Request
0x4000_0198 DRCMR38 Request to Channel Map Register for USB endpoint 14 Request
0x4000_019C DRCMR39 Reserved
0x4000_0200 DDADR0 DMA Descriptor Address Register Channel 0
0x4000_0204 DSADR0 DMA Source Address Register Channel 0
0x4000_0208 DTADR0 DMA Target Address Register Channel 0
0x4000_020C DCMD0 DMA Command Address Register Channel 0
0x4000_0210 DDADR1 DMA Descriptor Address Register Channel 1
0x4000_0214 DSADR1 DMA Source Address Register Channel 1
0x4000_0218 DTADR1 DMA Target Address Register Channel 1
0x4000_021C DCMD1 DMA Command Address Register Channel 1
0x4000_0220 DDADR2 DMA Descriptor Address Register Channel 2
0x4000_0224 DSADR2 DMA Source Address Register Channel 2
0x4000_0228 DTADR2 DMA Target Address Register Channel 2
0x4000_022C DCMD2 DMA Command Address Register Channel 2
0x4000_0230 DDADR3 DMA Descriptor Address Register Channel 3
0x4000_0234 DSADR3 DMA Source Address Register Channel 3
0x4000_0238 DTADR3 DMA Target Address Register Channel 3
0x4000_023C DCMD3 DMA Command Address Register Channel 3
0x4000_0240 DDADR4 DMA Descriptor Address Register Channel 4
0x4000_0244 DSADR4 DMA Source Address Register Channel 4
0x4000_0248 DTADR4 DMA Target Address Register Channel 4
I2S 0x4040_0000
0x4040_0000 SACR0 Global Control Register
0x4040_0004 SACR1 Serial Audio I2S/MSB-Justified Control Register
0x4040_0008 — Reserved
0x4040_000C SASR0 Serial Audio I2S/MSB-Justified Interface and FIFO Status Register
0x4040_0010 — Reserved
0x4040_0014 SAIMR Serial Audio Interrupt Mask Register
0x4040_0018 SAICR Serial Audio Interrupt Clear Register
0x4040_001C
through — Reserved
0x4040_005C
0x4040_0060 SADIV Audio Clock Divider Register.
0x4040_0064
through — Reserved
0x4040_007C
0x4040_0080 SADR Serial Audio Data Register (TX and RX FIFO access Register).
AC97 0x4050_0000
0x4050_0000 POCR PCM Out Control Register
0x4050_0004 PICR PCM In Control Register
0x4050_0008 MCCR Mic In Control Register
0x4050_000C GCR Global Control Register
0x4050_0010 POSR PCM Out Status Register
0x4050_0014 PISR PCM In Status Register
0x4050_0018 MCSR Mic In Status Register
0x4050_001C GSR Global Status Register
0x4050_0020 CAR CODEC Access Register
0x4050_0024
through — Reserved
0x4050_003C
0x4050_0040 PCDR PCM FIFO Data Register
0x4050_0044
through — Reserved
0x4050_005C
0x4050_0060 MCDR Mic-in FIFO Data Register
0x4050_0064
through — Reserved
0x4050_00FC
0x4050_0100 MOCR Modem Out Control Register
0x4050_0104 — Reserved
0x4050_0108 MICR Modem In Control Register
0x4050_010C — Reserved
0x4050_0110 MOSR Modem Out Status Register
0x4050_0114 — Reserved
0x4050_0118 MISR Modem In Status Register
0x4050_011C
through — Reserved
0x4050_013C
0x4050_0140 MODR Modem FIFO Data Register
0x4050_0144
through — Reserved
0x4050_01FC
0x4050_0200
through — Primary Audio CODEC registers
0x4050_02FC
0x4050_0300
through — Secondary Audio CODEC registers
0x4050_03FC
0x4050_0400
through — Primary Modem CODEC registers
0x4050_04FC
0x4050_0500
through — Secondary Modem CODEC registers
0x4050_05FC
UDC 0x4060_0000
0x4060_0000 UDCCR UDC Control Register
0x4060_0010 UDCCS0 UDC Endpoint 0 Control/Status Register
0x4060_0014 UDCCS1 UDC Endpoint 1 (IN) Control/Status Register
0x4060_0018 UDCCS2 UDC Endpoint 2 (OUT) Control/Status Register
0x4060_001C UDCCS3 UDC Endpoint 3 (IN) Control/Status Register
0x4060_0020 UDCCS4 UDC Endpoint 4 (OUT) Control/Status Register
0x4060_0024 UDCCS5 UDC Endpoint 5 (Interrupt) Control/Status Register
0x4060_0028 UDCCS6 UDC Endpoint 6 (IN) Control/Status Register
0x4060_002C UDCCS7 UDC Endpoint 7 (OUT) Control/Status Register
0x4060_0030 UDCCS8 UDC Endpoint 8 (IN) Control/Status Register
0x4060_0034 UDCCS9 UDC Endpoint 9 (OUT) Control/Status Register
0x4060_0038 UDCCS10 UDC Endpoint 10 (Interrupt) Control/Status Register
0x4060_003C UDCCS11 UDC Endpoint 11 (IN) Control/Status Register
0x4060_0040 UDCCS12 UDC Endpoint 12 (OUT) Control/Status Register
0x4060_0044 UDCCS13 UDC Endpoint 13 (IN) Control/Status Register
0x4060_0048 UDCCS14 UDC Endpoint 14 (OUT) Control/Status Register
0x4060_004C UDCCS15 UDC Endpoint 15 (Interrupt) Control/Status Register
0x4060_0060 UFNRH UDC Frame Number Register High
0x4060_0064 UFNRL UDC Frame Number Register Low
0x4060_0068 UBCR2 UDC Byte Count Register 2
ICP 0x4080_0000
0x4080_0000 ICCR0 ICP Control Register 0
0x4080_0004 ICCR1 ICP Control Register 1
0x4080_0008 ICCR2 ICP Control Register 2
0x4080_000C ICDR ICP Data Register
0x4080_0010 — Reserved
0x4080_0014 ICSR0 ICP Status Register 0
0x4080_0018 ICSR1 ICP Status Register 1
RTC 0x4090_0000
0x4090_0000 RCNR RTC Count Register
0x4090_0004 RTAR RTC Alarm Register
0x4090_0008 RTSR RTC Status Register
0x4090_000C RTTR RTC Timer Trim Register
OS Timer 0x40A0_0000
0x40A0_0000 OSMR<0>
0x40A0_0004 OSMR<1>
OS Timer Match registers<3:0>
0x40A0_0008 OSMR<2>
0x40A0_000C OSMR<3>
0x40A0_0010 OSCR OS Timer Counter Register
0x40A0_0014 OSSR OS Timer Status Register
0x40A0_0018 OWER OS Timer Watchdog Enable Register
0x40A0_001C OIER OS Timer Interrupt Enable Register
PWM 0 0x40B0_0000
0x40B0_0000 PWM_CTRL0 PWM 0 Control Register
0x40B0_0004 PWM_PWDUTY0 PWM 0 Duty Cycle Register
0x40B0_0008 PWM_PERVAL0 PWM 0 Period Control Register
PWM 1 0x40C0_0000
0x40C0_0000 PWM_CTRL1 PWM 1Control Register
0x40C0_0004 PWM_PWDUTY1 PWM 1 Duty Cycle Register
0x40C0_0008 PWM_PERVAL1 PWM 1 Period Control Register
Interrupt
0x40D0_0000
Control
0x40D0_0000 ICIP Interrupt Controller IRQ Pending Register
0x40D0_0004 ICMR Interrupt Controller Mask Register
0x40D0_0008 ICLR Interrupt Controller Level Register
0x40D0_000C ICFP Interrupt Controller FIQ Pending Register
0x40D0_0010 ICPR Interrupt Controller Pending Register
0x40D0_0014 ICCR Interrupt Controller Control Register
GPIO 0x40E0_0000
0x40E0_0000 GPLR0 GPIO Pin-Level Register GPIO<31:0>
0x40E0_0004 GPLR1 GPIO Pin-Level Register GPIO<63:32>
0x40F0_002C — Reserved
0x40F0_0030 RCSR Reset Controller Status Register
SSP 0x4100_0000
0x4100_0000 SSCR0 SSP Control Register 0
0x4100_0004 SSCR1 SSP Control Register 1
0x4100_0008 SSSR SSP Status Register
0x4100_000C SSITR SSP Interrupt Test Register
0x4100_0010 SSDR (Write / Read) SSP Data Write Register/SSP Data Read Register
MMC
0x4110_0000
Controller
0x4110_0000 MMC_STRPCL Control to start and stop MMC clock
0x4110_0004 MMC_STAT MMC Status Register (read only)
0x4110_0008 MMC_CLKRT MMC clock rate
0x4110_000C MMC_SPI SPI mode control bits
0x4110_0010 MMC_CMDAT Command/response/data sequence control
0x4110_0014 MMC_RESTO Expected response time out
0x4110_0018 MMC_RDTO Expected data read time out
0x4110_001C MMC_BLKLEN Block length of data transaction
0x4110_0020 MMC_NOB Number of blocks, for block mode
0x4110_0024 MMC_PRTBUF Partial MMC TXFIFO FIFO written
0x4110_0028 MMC_I_MASK Interrupt Mask
0x4110_002C MMC_I_REG Interrupt Register (read only)
0x4110_0030 MMC_CMD Index of current command
0x4110_0034 MMC_ARGH MSW part of the current command argument
0x4110_0038 MMC_ARGL LSW part of the current command argument
0x4110_003C MMC_RES Response FIFO (read only)
0x4110_0040 MMC_RXFIFO Receive FIFO (read only)
0x4110_0044 MMC_TXFIFO Transmit FIFO (write only)
Clocks
0x4130_0000
Manager
0x4130_0000 CCCR Core Clock Configuration Register
0x4130_0004 CKEN Clock Enable Register
0x4130_0008 OSCC Oscillator Configuration Register
Network SSP 0x4140_0000
0x4140_0000 NSSCR0 NSSP Control Register 0
0x4140_0004 NSSCR1 NSSP Control Register 1
0x4140_0008 NSSSR NSSP Status Register
0x4140_000C NSSITR NSSP Interrupt Test Register
0x4140_0010 NSSDR NSSP Data Read/Write Register
0x4140_0028 NSSTO NSSP Time Out Register
Note: Not all frequency combinations are valid. See Section 3.3.3, “Core Phase Locked Loop” for valid
combinations.
The Clocks and Power Manager also controls the entry into and exit from any of the low power or
special clocking modes on processor. These modes are:
• Turbo Mode: the Core runs at its peak frequency. In this mode, make very few external
memory accesses because the Core must wait on the external memory.
• Run Mode: the Core runs at its normal frequency. In this mode, the Core is assumed to be
doing frequent external memory accesses, so running slower is optimum for the best power/
performance trade-off.
• Idle Mode: the Core is not being clocked, but the rest of the system is fully operational. This
mode is used during brief lulls in activity, when the external system must continue operation
but the Core is idle.
• Sleep Mode: places the processor in its lowest power state but maintains I/O state, RTC, and
the Clocks and Power Manager. Wake-up from Sleep Mode requires re-booting the system,
since most internal state was lost. The core power must be grounded in sleep to prevent current
leakage.
The Clocks and Power Manager also controls the processor’s actions during the Frequency Change
Sequence. The Frequency Change Sequence is a sequence that changes the Core Frequency (Run
and Turbo) and Memory Frequency from the previously stored values to the new values in the Core
Clock Configuration register. This sequence takes time to complete due to PLL relock time, but it
allows dynamic frequency changes without compromising external memory integrity. Any
peripherals that rely on the Core or Memory Controller must be configured to withstand a data flow
interruption.
The clocks manager also contains clock gating for power reduction.
Figure 3-1 shows a functional representation of the clocking network. “L” is in the core PLL.
The PXbus is the internal bus between the Core, the DMA/Bridge, the LCD Controller, and the
Memory Controller as shown in Figure 3-1. This bus is clocked at 1/2 the run mode frequency. For
optimal performance, the PXbus should be clocked as fast as possible. For example, if a target core
frequency of 200 MHz is desired use 200 MHz run mode instead of 200 MHz turbo mode with run
at 100 MHz. Increasing the PXbus frequency may help reduce the latency involved in accessing
non-cacheable memory.
Figure 3-1. Clocks Manager Block Diagram
CPU
CORE
100-400
MHz
PLL* /N
/1 /112
32.768 147.46
kHz MEM
MHz Controller
OSC PLL
3.6864 95.846 /M
MHz MHz /4 /2
OSC PLL
DMA
/ LCD
RETAINS POWER IN SLEEP Controller
Bridge
PXbus
32.768 kHz oscillator use is optional and provides the lowest power consumption during Sleep
Mode. In less power-sensitive applications, disable the 32.768 kHz oscillator in the Oscillator
Configuration Register (OSCC) and leave the external pins floating (no external crystal required)
for cost savings. If the 32.768 kHz oscillator is not in the system, the frequency of the RTC and
Power Manager will be 3.6864 MHz divided by 112 (32.914 kHz). In Sleep, the 3.6864 MHz
oscillator consumes hundreds of microamps of extra power when it stays enabled. See
Section 3.5.2, “Power Manager General Configuration Register (PCFR)” on page 3-24 for
information on The Oscillator Power Down Enable (OPDE) bit, which determines if the
3.6864 MHz oscillator is enabled in Sleep Mode. No external capacitors are required.
Do not choose a combination that generates a frequency that is not supported in the voltage range
and package in which the processor is operating.
SDCLK must not be greater than 100 MHz. If MEMCLK is greater than 100 MHz, the SDCLK to
MEMCLK ratio must be set to 1:2 in the Memory Controller.
Table 3-1. Core PLL Output Frequencies for 3.6864 MHz Crystal
Turbo Mode Frequency (MHz) for Values
“N” and Core Clock
SDRAM
Configuration Register (CCCR[15:0]) PXbus MEM, LCD
programming for Values of “N” max
L M Frequency Frequency
Frequency
(MHz) (MHz)
(MHz)
1.00
1.50 2.00 3.00
(Run)
Table 3-2. 95.85 MHz Peripheral PLL Output Frequencies for 3.6864 MHz Crystal
Unit Name Nominal Frequency Actual Frequency
Table 3-3. 147.46 MHz Peripheral PLL Output Frequencies for 3.6864 MHz Crystal
Unit Name Nominal Frequency Actual Frequency
When a module’s clock is disabled, the registers in that module are still readable and writable. The
AC97 is an exception and is completely inaccessible if the clock is disabled.
Reset, nRESET must be held low for tDHW_NRESET to allow the system to stabilize and the reset
state to propagate. Refer to the Intel® PXA255 Processor Electrical, Mechanical, and Thermal
Specification for details.
Refer to Table 2-6, “Pin & Signal Descriptions for the PXA255 Processor” for the pin states during
Watchdog and other Resets.
The previous mode of operation does not affect a GPIO Reset. When performing a GPIO Reset,
nRESET_OUT is asserted. If GP[1] is asserted for less than four 3.6864-MHz clock cycles, the
processor may remain in its previous mode or enter into a GPIO reset.
GPIO Reset does not function in Sleep Mode because all GPIO pins’ Alternate Function Inputs are
disabled. External wake-up sources must be routed through one of the enabled GPIO wake-up
sources (see Section 3.5.3 for details) during Sleep Mode. GP[1] may be enabled as a wake-up
source.
GPIO Reset does not reset the Memory Controller Configuration registers. This creates the
possibility that the contents of external memories may be preserved if the external memories are
properly configured before GPIO Reset is entered. To preserve SDRAM contents during a GPIO
Reset, software must correctly configure the Memory Control and the time spent in GPIO Reset
must be shorter than the SDRAM refresh interval. The amount of time spent in GPIO Reset
depends on the CPU’s mode before GPIO Reset. See Section 6, “Memory Controller” for details.
Refer to Table 2-6, “Pin & Signal Descriptions for the PXA255 Processor” for the states of all the
PXA255 processor pins during GPIO reset and other resets.
Software can set or clear other bits in the CCLKCFG in the same write that sets the TURBO bit.
The other bits in the register take precedence over Turbo Mode, so, if another bit is set, that mode’s
sequence is followed before the CPU enters Turbo Mode. When the CPU exits the other mode, it
enters either Run or Turbo Mode, based on the state of the CCLKCFG [TURBO] bit.
Do not confuse the CCLKCFG Register, which is in Coprocessor 14, with the CCCR (See
Section 3.6.1), which is in the processor’s Clocks and Power Manager.
Other bits in the CCLKCFG may be set or cleared in the write that clears CCLKCFG [TURBO].
All other bits in the register take precedence over Turbo Mode, so the new mode’s proper sequence
is followed.
Idle, Sleep, Frequency Change Sequence, and Reset have precedence over Turbo Mode and cause
the processor to exit Turbo Mode. When the CPU exits of one of these modes, it enters either Run
or Turbo Mode, based on the state of CCLKCFG [TURBO].
When ICCR[DIM] is cleared, any enabled interrupt wakes up the processor. When ICCR[DIM] is
set, only unmasked interrupts cause wake-up.
Enabled interrupts are interrupts that are allowed at the unit level. Masked interrupts are interrupts
that are prevented from interrupting the core based on the Interrupt Controller Mask Register.
Any enabled interrupt causes Idle Mode to exit. When ICCR[DIM] is cleared, the Interrupt
Controller Mask register (ICMR) is ignored during Idle Mode. This means that an interrupt does
not have to be unmasked to cause Idle Mode to exit. Idle Mode exits in the following sequence:
1. A valid, enabled Interrupt asserts.
2. The CPU clocks restart and the CPU resumes operation at the state indicated by CCLKCFG
[TURBO].
Idle Mode also exits when the nBATT_FAULT or nVDD_FAULT pin is asserted. When either pin
is asserted, Idle Mode exits in the following sequence:
1. The nBATT_FAULT or nVDD_FAULT pin is asserted.
2. If the Imprecise Data Abort Enable (IDAE) bit in the Power Manager Control Register
(PMCR) is clear (not recommended), the processor enters Sleep Mode immediately.
3. If the IDAE bit is set, the nBATT_FAULT or nVDD_FAULT assertion is treated as a valid
interrupt to the clocks module and Idle Mode exits using its normal, interrupt-driven sequence.
Software must then shut down the system and enter Sleep Mode. See Section 3.4.9.3,
“Entering Sleep Mode” for more details.
1. Configure the Memory Controller to ensure SDRAM contents are maintained during the
Frequency Change Sequence. The Memory Controller’s refresh timer must be programmed to
match the maximum refresh time associated with the slower of two frequencies (current and
desired). The SDRAM divide by two must be set to a value that prevents the SDRAM
frequency from exceeding the specified frequency. For example, to change from 100/100 to
133/66, the SDRAM bus must be set to divide by two before the frequency change. To change
from 133/66 to 100/100, the SDRAM must be set to one-to-one after the frequency change
sequence is completed. See Section 6, “Memory Controller” for more details.
2. Disable the LCD Controller or configure it to avoid the effects of an interruption in the LCD
clocks and data from the processor.
3. Configure peripheral units to handle a lack of DMA service for up to 500 µs. If a peripheral
unit can not function for 500 µs without DMA service, it must be disabled.
4. Disable peripheral units that can not accommodate a 500 µs interrupt latency. The interrupts
generated during the Frequency Change Sequence are serviced when the sequence exits.
5. Program the CCCR (Section 3.6.1, “Core Clock Configuration Register (CCCR)”) to reflect
the desired frequency.
Note: Program the Memory Controller to ensure the correct self-refresh time for SDRAM, given the
slower of the current and desired clock frequencies.
The Imprecise Data Abort is also not recognized and if nVDD_FAULT or nBATT_FAULT is
asserted, the assertion is ignored until the Frequency Change Sequence exits. This means that the
processor does not enter Sleep Mode until the Frequency Change Sequence is complete.
If the Watchdog Timer is enabled during the Frequency Change Sequence, set the Watchdog Match
Register to ensure that the Frequency Change Sequence completes before the Watchdog Reset is
asserted.
If Hardware or Watchdog Reset is asserted during the Frequency Change Sequence, the DRAM
contents are lost because all states, including Memory Controller configuration and information
about the previous Frequency Change Sequence, are reset. If GPIO Reset is asserted during the
Frequency Change Sequence, the SDRAM contents will be lost during the GPIO Reset exit
sequence if the SDRAM is not in self-refresh mode and the exit sequence exceeds the refresh
interval.
Note: This sequence occurs even if the before and after frequencies are the same.
2. The internal PLL clock generator for the processor clock waits for stabilization. Refer to the
Intel® PXA250 and PXA210 Application Processors Electrical, Mechanical, and Thermal
Specification for details.
3. The CPU clocks restart and the CPU resumes operation at the state indicated by the TURBO
bit (either Run or Turbo Mode). Interrupts to the CPU are no longer gated.
4. The FCS bit is not automatically cleared. To prevent an accidental return to the Frequency
Change Sequence, software must not immediately clear the FCS bit. The bit must be cleared
on the next required write to the register.
5. Values may be written to the CCCR, but they are ignored until the Frequency Change
Sequence is re-entered.
6. The SDRAM must transition out of self-refresh mode and into its idle state. See Section 6,
“Memory Controller” for details on configuring the SDRAM interface.
• SDRAM is placed in self refresh before entering 33-MHz idle mode, because SDRAM cannot
be refreshed correctly in 33-MHz idle mode. Carefully consider the processor interrupt
behavior when the SDRAM in self refresh. To allow the interrupts to occur while SDRAM is
in self refresh, set the I and F bits in the CPSR. This allows interrupts to wake the processor
from idle mode without jumping to the interrupt handler. When the system’s SDRAM is no
longer in self refresh, the I and F bits can be cleared and the interrupt is handled.
• Because nBATT_FAULT and nVDD_FAULT can cause a data abort interrupt, the function of
these pins in 33-MHz idle mode also needs special consideration. Either the Imprecise Data
Abort Enable (IDAE) bit in the Power Manager Control Register (PMCR) must be clear,
(causing the processor to immediately enter sleep mode if either nBATT_FAULT or
nVDD_FAULT are asserted) or take software precautions to avoid starting execution in or
trying to use SDRAM while it is in self refresh.
During 33-Mhz idle mode these system unit modules are functional:
• Real-time clock
• Operating system timer
• Interrupt controller
• General purpose I/O
• Clocks and power manager
• Flash ROM/SRAM
Unlike normal idle mode, in 33-MHz idle mode all other peripheral units cannot be used, including
SDRAM, LCD and DMA controllers.
When ICCR[DIM] is cleared, any enabled interrupt wakes up the processor. When ICCR[DIM] is
set, only unmasked interrupts cause wake-up.
Enabled interrupts are interrupts that are allowed at the unit level. Masked interrupts are interrupts
that are prevented from interrupting the core based on the Interrupt Controller Mask Register
(ICMR).
Because all activity on the processor except the RTC stops when Sleep Mode starts, peripherals
must be disabled to allow an orderly shutdown. When Sleep Mode exits, the processor’s state resets
and processing resumes in a boot-up mode.
Note: The PCFR[OPDE] bit must be cleared to enable the 3.6864 MHz oscillator during sleep when fast
sleep wakeup is selected by setting the PMFW[FWAKE] bit.
If the external voltage regulator is failing or the main battery is low or missing, some systems must
enter sleep mode quickly. When nBATT_FAULT or nVDD_FAULT is asserted, the system is
required to shut down immediately.
To allow the assertion of nVDD_FAULT or nBATT_FAULT to cause an imprecise data abort, set
the Imprecise Data Abort Enable (IDAE) bit in the PMCR. Setting the IDAE bit in the PMCR will
result in software executing the data abort handler routine as part of entering sleep mode. If the
IDAE bit is clear, the processor enters sleep mode immediately without executing the abort handler
routine.
Note: Using an exception handler to invoke sleep in response to a power fault event is advantageous
because software can clear the PMFW[FWAKE] bit and configure the power management IC to
use PWR_EN to disable the core power supply during sleep to minimize power consumption from
a critically low battery.
PSSR[VFS] and PSSR[BFS] can not be used prior to entering Sleep Mode to determine which type
of fault occurred, VDD fault or battery fault, respectively. If either nVDD_FAULT or
nBATT_FAULT signals are asserted or if both are asserted at the same time (and the IDAE bit of
the PMCR is set), the software data abort handler will be called. Since there is only one common
data abort handler, software must first determine if one of the two nVDD_FAULT or
nBATT_FAULT assertion events resulted in an imprecise data abort by reading Coprocessor 7,
Register 4, Bit 5 (PSFS). If the PSFS bit is cleared, neither a nVDD_FAULT or nBATT_FAULT
assertion occurred and the data abort handler was called for some other reason. If the PSFS bit is
set, this indicates either a nVDD_FAULT or nBATT_FAULT assertion occurred, but it is not
possible to determine which of the two faults was asserted. For either case, nVDD_FAULT or
nBATT_FAULT assertion, software should shut the system down as quickly as possible by
performing the steps outlined below to enter Sleep Mode.
Note: All addresses (data and instruction) used in the abort handler routines should be resident and
accessible in the memory page tables, i.e. system software developers should ensure no further
aborts occur while executing an abort handler. The processor does not support recursive (nested)
aborts. The system must not assert nBATT_FAULT or nVDD_FAULT signals more than once
before nRESET_OUT is asserted. System software can not return to normal execution following a
nBATT_FAULT or nVDD_FAULT. If a battery or VDD fault occurs while executing in the abort
mode, the abort handler is reentered. This condition of a recursive abort occurrence can be detected
in software by reading the Saved Program Status Register (SPSR) to see if the previous context
was executing in abort mode.
7. The CPU clock stops and power is removed from the Core.
8. PWR_EN is deasserted.
When the Power Manger get the indication from the Memory Controller that it has finished its
outstanding transactions and has put the SDRAM into self-refresh, there are eight core clock cycles
before the GPIOs latch the PGSR values and four core clock cycles after that, nRESET_OUT
asserts low.
In some systems the Imprecise Data Abort latency lasts longer than the residual charge in the failed
power supply can sustain operation. This normally only occurs when the processor is in a Power
Mode or Sequence that requires that the processor exit before Sleep Mode starts. Frequency
Change Sequence is an example of such a Power Sequence. In these Power Modes and Sequences,
the IDAE bit must not be set. This allows the processor to enters Sleep Mode immediately but any
critical states in the processor are lost.
If the IDAE bit is not set and the nVDD_FAULT or nBATT_FAULT pin is asserted, the Sleep
Sequence begins at Step 4.
If the nBATT_FAULT signal is asserted while in Sleep Mode, GPIO[1:0] are set as the only valid
wake-up signals.
The Power Manager watches for wake up events programmed by the CPU before Sleep Mode
starts or set by the Power Manager it detects a fault condition. In order to detect a rising-edge or
falling-edge on a GPIO pin, the rising- or falling-edge must be held for more than one full
32.768 kHz clock cycle. The Power Manager takes three 32.768 kHz clock cycles to acknowledge
the GPIO edge and begin the wake up sequence.
Refer to Table 2-6, “Pin & Signal Descriptions for the PXA255 Processor” on page 2-9 for the
PXA255 processor pin states during sleep mode reset and other resets.
Note: If Hardware Reset is asserted during Sleep Mode, the DRAM contents are lost because all states,
including Memory Controller configuration and information about the previous Sleep Mode, are
reset.
Normally, Sleep Mode exits in the following sequence. Any time the nBATT_FAULT pin is
asserted, the processor returns to Sleep Mode. The nVDD_FAULT pin is ignored until the external
power supply stabilization timer expires.
1. A pre-programmed wake up event from an enabled GPIO or RTC source occurs. If the
nBATT_FAULT pin is asserted, the wake up source is ignored.
2. The PWR_EN signal is asserted and the Power Manager waits for the external power supply to
stabilize. If nVDD_FAULT is asserted after the external power supply timer expires, the
processor returns to Sleep Mode.
3. If PCFR[OPDE] and OSCC[OON] were set when Sleep Mode started, the 3.6864 MHz
oscillator is enabled and stabilizes. Otherwise, the 3.6864 MHz oscillator is already stable and
this step is bypassed.
4. The processor’s PLL clock generator is reprogrammed with the values in the CCCR and
stabilizes.
5. The Sleep Mode configuration in PWRMODE[M] is cleared.
6. The processor’s internal reset is deasserted and the CPU begins a normal boot sequence. When
the normal boot sequence begins, all of the processor’s units, except the RTC and portions of
the Clocks and Power Manager and the Memory Controller, return to their predefined reset
settings.
7. The nRESET_OUT pin is deasserted. This indicates that the processor is about to perform a
fetch from the Reset vector.
8. Clear PSSR[PH] before accessing GPIOs, including chip selects that are muxed with GPIOs.
9. Clear PCFR[FS] and PCFR[FP] if either was set before Sleep Mode was triggered.
10. The SDRAM must transition out of self-refresh mode and into its idle state. See Section 6,
“Memory Controller” for details on configuring the SDRAM interface.
11. Software must examine the RCSR, to determine what caused the reboot, and the Power
Manager Sleep Status register (PSSR), to determine what triggered Sleep Mode.
12. If the PSPR was used to preserve any critical states during Sleep Mode, software can now
recover the information.
If the nVDD_FAULT or nBATT_FAULT pin is asserted during the Sleep Mode exit sequence, the
system re-enters Sleep Mode in the following sequence:
1. Regardless of the state of the IDAE bit:
— All GPIO edge detects and the RTC alarm interrupt are cleared.
— The Power Manager wake-up source registers (PWER, PRER, and PFER) are loaded with
0x0000 0003, their wake-up fault state. This limits the potential wake-up sources to a
rising or falling edge on GPIO[0] or GPIO[1]. The wake-up fault state prevents spurious
events from causing an unwanted wake-up while the battery is low or the power supply is
at risk. The fault state is also the default state after a Hardware Reset.
2. The PLL clock generators are disabled.
3. If the OPDE bit in the PCFR is set and the OON bit in the OSCC is set, the 3.6864 MHz
oscillator is disabled. If the oscillator is disabled, Sleep Mode consumes less power. If it is
enabled, Sleep Mode exits more quickly.
4. An internal reset is generated to the core and most peripheral modules. This reset asserts the
nRESET_OUT pin.
5. The PWR_EN pin is deasserted. If PMFW[FWAKE] is cleared, the system must respond by
grounding the VCC and PLL_VCC power supplies to minimize power consumption.
Freq Change
Fault1 Sleep
Turbo
Sleep
Step
Idle
Description of Action
Freq Change
Fault1 Sleep
Turbo
Sleep
Step
Idle
Description of Action
Freq Change
Fault1 Sleep
Turbo
Sleep
Step
Idle
Description of Action
11 Deassert nRESET_OUT x x
12 Restart CPU clocks, enable interrupts x x x x x x
1: Fault Sleep Mode starts if IDAE is clear and nBATT_FAULT or nVDD_FAULT is asserted.
Table 3-6. Power and Clock Supply Sources and States During Power Modes
Power Mode
Supply Source
Freq
Module Turbo Run Idle Sleep
Change
Pw Ck Pw Ck Pw Ck Pw Ck Pw Ck Pw Ck
CPU, Run/
Caches, Turbo T R Off
Buffers (R/T)
changing
Memory
Controller
LCD
Mem
Controller
VCC On On On On Off Off
DMA
Controller On On On
General
PLL
Periphs.
On
OS timer 3.686
Interrupts MHz Osc
Real Time
Clock VCC/
32.768
Reg V On V On V On V On I On
Power kHz Osc
(V/R)
Manager
GP[3:0], PM HV/ Dynamic/
pads, Osc Batt Static
pads (H/B) (D/S) H D H D H D H D H S
General IO H
KEY:
T: Turbo clock
R: Run clock
V: Module powered off VCC.
I: Module powered off internal regulator
H: Module powered off VCCQ or VCCN
D: Module is dynamic or actively clocked
S: Module is static or clocks are gated.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
IDAE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved.
[31:1] —
Read undefined and must always be written with zeroes.
Imprecise Data Abort Enable.
0 – Allow immediate entry to sleep mode when nVDD_FAULT or nBATT_FAULT is
asserted.
0 IDAE
1 – Force imprecise data abort signal to CPU to allow software to enter sleep mode
when nVDD_FAULT or nBATT_FAULT is asserted. Recommended mode.
Cleared on hardware, watchdog, and GPIO reset, or when sleep mode exits.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
OPDE
FS
FP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved.
[31:3] —
Read undefined and must always be written with zeroes.
Float Static Chip Selects during Sleep Mode.
0 = Static Chip Select pins are not floated in Sleep Mode. nCS[5:1] are driven to the
state of the appropriate PGSR register bits. nCS[1], nWE, and nOE are driven high.
2 FS
1 = Static Chip Select pins are floated in Sleep Mode. The pins nCS[5:0], nWE, and
nOE are affected.
Cleared on Hardware, Watchdog, and GPIO Resets.
Float PCMCIA controls during Sleep Mode.
0 = PCMCIA pins are not floated in Sleep Mode. They are driven to the state of the
appropriate PGSR register bits.
1 FP 1 = The PCMCIA signals: nPOE, nPWE, nPIOW, nPIOR, and nPCE[2:1] are floated in
Sleep Mode. nPSKTSEL and nPREG are derived from address signals and assume
the state of the address bus during Sleep Mode.
Cleared on Hardware, Watchdog, and GPIO Resets.
3.6864 MHz oscillator power-down enable.
If the 32.7686 kHz crystal is disabled because the OON bit in the Oscillator
Configuration Register is 0, OPDE is ignored and the 3.6864 MHz oscillator is not
0 OPDE disabled.
0 = Do not stop the oscillator during Sleep Mode.
1 = Stop the 3.6864 MHz oscillator during Sleep Mode.
Cleared on Hardware, Watchdog, and GPIO Resets.
Software should enable wakeups only for those GPIO pins that are configured as inputs during
sleep. Any GPIO pins that are configured as outputs during sleep, should have their associated
wake enable bits set to logic zero in all three PMU wake enable registers (PWER, PRER, and
PFER).
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
WERTC
WE15
WE14
WE13
WE12
WE10
WE11
WE9
WE8
WE7
WE6
WE5
WE4
WE3
WE2
WE1
WE0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Software should enable wakeups only for those GPIO pins that are configured as inputs during
sleep. Any GPIO pins that are configured as outputs during sleep, should have their associated
wake enable bits set to logic zero in all three PMU wake enable registers (PWER, PRER, and
PFER).
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
RE15
RE14
RE13
RE12
RE10
RE11
RE9
RE8
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Reserved.
[31:16] —
Read undefined and must always be written with zeroes.
Sleep mode Rising-edge Wake up Enable
0 – Wake up due to GPx rising-edge detect disabled.
[15:0] REx
1 – Wake up due to GPx rising-edge detect enabled.
Set to 0x 0003 on hardware, watchdog, and GPIO resets.
Software should enable wakeups only for those GPIO pins that are configured as inputs during
sleep. Any GPIO pins that are configured as outputs during sleep, should have their associated
wake enable bits set to logic zero in all three PMU wake enable registers (PWER, PRER, and
PFER).
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
FE15
FE14
FE13
FE12
FE10
FE11
FE9
FE8
FE7
FE6
FE5
FE4
FE3
FE2
FE1
FE0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Reserved.
[31:16] —
Read undefined and must always be written with zeroes.
Sleep mode Falling-edge Wake-up Enable
0 – Wake up due to GPx falling-edge detect disabled.
[15:0] FEx
1 – Wake up due to GPx falling-edge detect enabled.
Set to 0x0003 on hardware, watchdog, and GPIO resets.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
ED15
ED14
ED13
ED12
ED10
ED11
ED9
ED8
ED7
ED6
ED5
ED4
ED3
ED2
ED1
ED0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved.
[31:16] —
Read undefined and must always be written with zeroes.
Sleep mode Edge Detect Status
0 – Wake up on GPx not detected.
[15:0] EDx
1 – Wake up due to edge on GPx detected.
Cleared by hardware, watchdog, and GPIO resets. Cleared by writing a 1.
To clear a status flag write a 1 to it. Writing a 0 to a status bit has no effect. Hardware, watchdog,
and GPIO resets clear or set the PSSR bits.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
RDH
BFS
SSS
VFS
PH
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
[31:6] — reserved
Read Disable Hold.
0 – GPIO pins are configured according to their GPIO configuration
1 – Receivers of all GPIO pins that can act as inputs are disabled and following a
5 RDH hardware, GPIO, or watchdog reset, internal GPIO pull-ups are active. Must be
cleared by the processor after the peripheral and GPIO interfaces are configured
but before they are used.
Set by hardware, watchdog, and GPIO resets and sleep mode. Cleared by writing a 1.
Peripheral Control Hold.
0 – GPIO pins are configured according to their GPIO configuration
1 – GPIO pins are being held in their sleep mode state. Set when sleep mode starts.
4 PH
Must be cleared by the processor after the peripheral interfaces have been
configured but before they are actually used by the processor.
Cleared by hardware, watchdog, and GPIO resets. Cleared by writing a 1.
3 — reserved
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
RDH
BFS
SSS
VFS
PH
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 3-14. PSPR Bit Definitions
0x40F0_0008 PSPR Clocks and Power Manager
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reserved 8 7 6 5 4 3 2 1 0
Reserved
FWAKE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
[31:3] —
Read undefined and must always be written with zeroes.
FAST WAKEUP ENABLE
0 – Selects the standard sleep wakeup sequence with a 10 ms power supply
stabilization delay when power is disabled during sleep.
[1] FWAKE
1 – Selects the fast sleep wakeup sequence without a power supply stabilization delay
when power is maintained during sleep.
Cleared by hardware reset.
Reserved
[0] —
Read undefined and must always be written with zeroes.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS31
SS30
SS29
SS28
SS27
SS26
SS25
SS24
SS23
SS22
SS21
SS20
SS19
SS18
SS17
SS16
SS15
SS14
SS13
SS12
SS10
SS11
SS9
SS8
SS7
SS6
SS5
SS4
SS3
SS2
SS1
SS0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS63
SS62
SS61
SS60
SS59
SS58
SS57
SS56
SS55
SS54
SS53
SS52
SS51
SS50
SS49
SS48
SS47
SS46
SS45
SS44
SS43
SS42
SS41
SS40
SS39
SS38
SS37
SS36
SS35
SS34
SS33
SS32
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS84
SS83
SS82
SS81
SS80
SS79
SS78
SS77
SS76
SS75
SS74
SS73
SS72
SS71
SS70
SS69
SS68
SS67
SS66
SS65
SS64
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:17] — reserved
If programmed as an output, Sleep state of GPx
0 – Pin is driven to a zero during sleep mode
[16:0] SSx
1 – Pin is driven to a one during sleep mode
Cleared by hardware, watchdog, and GPIO resets.
Refer to Table 2-4, “Effect of Each Type of Reset on Internal Register State” on page 2-6 for details
of the behavior of different modules during each type of reset.
Each RCSR status bit is set by a different reset source and can be cleared by writing a 1 back to the
bit. The RCSR status bits for watchdog reset, sleep mode, and GPIO resets have a hardware reset
state of zero.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDR
HWR
SMR
GPR
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
[31:4] — reserved
GPIO Reset.
0 – GPIO reset has not occurred since the last time the CPU or hardware reset cleared
this bit.
3 GPR
1 – GPIO reset has occurred since the last time the CPU or hardware reset cleared this
bit.
Cleared by hardware reset and by setting to a 1.
Sleep Mode.
0 – Sleep mode has not occurred since the last time the CPU or hardware reset cleared
this bit.
2 SMR
1 – Sleep mode has occurred since the last time the CPU or hardware reset cleared
this bit.
Cleared by hardware reset and by setting to a 1.
Watchdog Reset.
0 – Watchdog reset has not occurred since the last time the CPU or hardware reset
cleared this bit.
1 WDR
1 – Watchdog reset has occurred since the last time the CPU or hardware reset cleared
this bit.
Cleared by hardware reset and by setting to a 1.
Hardware Reset.
0 – Hardware reset has not occurred since the last time the CPU cleared this bit.
0 HWR
1 – Hardware reset has occurred since the last time the CPU cleared this bit.
Set by hardware reset. Cleared by setting to a 1.
Memory frequency = 3.6864 MHz crystal freq. * crystal frequency to memory frequency multiplier
(L)
Run mode frequency = Memory frequency * memory frequency to run mode frequency multiplier
(M)
Turbo mode frequency = run mode frequency * run mode frequency to turbo mode frequency
multiplier (N)
The value for L is chosen based on external memory or LCD requirements and can be constant
while M and N change to allow run and turbo mode frequency changes without disrupting memory
settings. The value for M is chosen based on bus bandwidth requirements and minimum core
performance requirements. The value for N is chosen based on peak core performance
requirements.
Table 3-20. CCCR Bit Definitions
Core Clock Configuration Register
0x4130_0000 Clocks Manager
(CCCR)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved N M L
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
reserved
reserved
reserved
CKEN16
CKEN14
CKEN13
CKEN12
CKEN11
CKEN8
CKEN7
CKEN6
CKEN5
CKEN3
CKEN2
CKEN1
CKEN0
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1
[31:17] — reserved
LCD Unit Clock Enable
0 – Clock to the unit is disabled
16 CKEN16
1 – Clock to the unit is enabled.
Set by hardware and watchdog resets
15 — reserved
I2C Unit Clock Enable
0 – Clock to the unit is disabled
14 CKEN14
1 – Clock to the unit is enabled.
Set by hardware and watchdog resets
FICP Unit Clock Enable
0 – Clock to the unit is disabled
13 CKEN13
1 – Clock to the unit is enabled.
These bits are set by hardware reset or watchdog reset
MMC Unit Clock Enable
0 – Clock to the unit is disabled
12 CKEN12
1 – Clock to the unit is enabled.
These bits are set by hardware reset or watchdog reset
USB Unit Clock Enable
0 – Clock to the unit is disabled
11 CKEN11 1 – Clock to the unit is enabled.
Set by hardware and watchdog resets
This bit must be set to allow the 48Mhz clock output on GP7 Alternate Function 1.
10 — reserved
NSSP Unit Clock Enable
0 – Clock to the unit is disabled
9 CKEN9
1 – Clock to the unit is enabled.
Set by hardware and watchdog resets
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
reserved
reserved
reserved
CKEN16
CKEN14
CKEN13
CKEN12
CKEN11
CKEN8
CKEN7
CKEN6
CKEN5
CKEN3
CKEN2
CKEN1
CKEN0
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1
When OSCC[OOK] is set, the RTC and PM are clocked from the 32.768 KHz oscillator.
Otherwise, the 3.6864 MHz oscillator is used. The OPDE bit, which allows the 3.6864 MHz
oscillator to be disabled in sleep mode, is ignored (treated as if it were clear) if OSCC[OOK] is
clear. OSCC[OOK] can only be reset by a hardware reset.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OON
OOK
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:2] — reserved
32.768 KHz OON (write-once only bit)
0 – 32.768 KHz oscillator is disabled. The 3.6864 MHz oscillator (divided by 112) clocks
the RTC and PM.
1 OON
1 – 32.768 KHz oscillator is enabled. OON can not be cleared once written except by
hardware reset.
Cleared by hardware reset.
32.768 kHz OOK (read-only bit)
0 – 32.768 KHz oscillator is disabled or not stable. The 3.6864 MHz oscillator (divided
by 112) clocks the RTC and PM.
0 OOK
1 – 32.768 KHz oscillator has been enabled (OON=1) and stabilized. It will clock the
RTC and PM.
Cleared by hardware reset.
To ensure that CCLKCFG[TURBO] does not change when entering the frequency change
sequence, software must do a read-modify-write.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TURBO
FCS
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:2] — reserved
Frequency Change Sequence
0 – Do not enter frequency change sequence
1 FCS
1 – Enter frequency change sequence
Cleared on hardware, watchdog, and GPIO reset and when sleep mode exits.
Turbo Mode
0 – Do not enter turbo mode/Exit turbo mode
0 TURBO
1 – Enter turbo mode
Cleared on hardware, watchdog, and GPIO reset and when sleep mode exits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved M
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:2] — reserved
Low Power Mode
00 – Run/turbo mode
01 – Idle mode
[1:0] M
10 – reserved
11 – Sleep mode
Set to 00 on reset.
To ensure that the internal ESD protection devices do not activate during power up, a minimum rise
time must be observed. Refer to the Intel® PXA255 Processor Electrical, Mechanical, and
Thermal Specification for details.
A 3.6864 MHz crystal must be connected between the PXTAL and PEXTAL pins. A 32.768 kHz
crystal is normally connected between the TXTAL and TEXTAL pins. This configuration gives the
lowest overall power consumption because the crystal’s resonant nature provides better power
efficiency than an external source that drives the crystal pins. Some applications have other clock
sources of the same frequency and can reduce overall cost by driving the crystal pins externally.
Refer to the Oscillator Electrical Specifications in the Intel® PXA255 Processor Design Guide for
more information.
Use the GPIO Pin Direction Register (GPDR) to set whether the GPIO pins are outputs or inputs.
When programmed as an output, the pin can be set high by writing to the GPIO Pin Output Set
Register (GPSR) and cleared low by writing to the GPIO Pin Output Clear Register (GPCR). The
set and clear registers can be written to regardless of whether the pin is configured as an input or an
output. If a pin is configured as an input, the programmed output state occurs when the pin is
reconfigured to be an output.
Validate each GPIO pin’s state by reading the GPIO Pin Level Register (GPLR). You can read this
register any time to confirm the state of a pin. In addition, use the GPIO Rising Edge Detect Enable
Register (GRER) and GPIO Falling Edge Detect Enable Register (GFER) to detect either a rising
edge or falling edge on each GPIO pin. Use the GPIO Edge Detect Status register (GEDR) to read
edge detect state. These edge detects can be programmed to generate interrupts (see Section 4.2).
Also use GPIO[15:0] to generate wake-up events that bring the PXA255 processor out of sleep
mode (refer to Section 3.4.9.5, “Exiting Sleep Mode” on page 3-18).
When the processor enters sleep mode, the contents of the Power Manager Sleep State registers
(PGSR0, PGSR1 and PGSR2) are loaded into the output data registers. If the particular pin is
programmed as an output, then the value in the PGSR is driven onto the pin before entering sleep
mode. When the processor exits sleep mode, these values remain driven until the GPIO pins are
reprogrammed by writing to the GPDR, GPSR or GPCR, and setting the GPIO bit in the Power
Manager Sleep Status register (PSSR) to indicate that the GPIO registers have been re-initialized
after sleep mode. This is necessary since the GPIO logic loses power during sleep mode
Most GPIO pins can also serve an alternate function within the processor. Certain modes within the
serial controllers and LCD controller require extra pins. These functions are hardwired into specific
GPIO pins and their use is described in the following paragraphs. Even though a GPIO pin is used
for an alternate function, you must still program the proper direction of that pin through the GPDR.
Details on alternate functions are provided in Section 4.1.2. Figure 4-1 shows a block diagram of a
single GPIO pin.
Figure 4-1. General-Purpose I/O Block Diagram
Pin Direction
Register
2
Alternate Function
Registers
3
2 Alternate Functions
1 (Inputs)
0
Edge Edge Detect
Detect Status Register
For more information on alternate functions, refer to the Source Unit column in Table 4-1 for the
appropriate section of this document.
Multimedia Card
GP54 MMCCLK ALT_FN_1_OUT 01 MMC Clock
(MMC) Controller
GP54 nPSKTSEL ALT_FN_2_OUT 10 Memory Controller Socket Select for Card Space
GP55 nPREG ALT_FN_2_OUT 10 Card Address bit 26
Memory Controller
GP56 nPWAIT ALT_FN_1_IN 01 Wait signal for Card Space
GP57 nIOIS16 ALT_FN_1_IN 01 Memory Controller Bus Width select for I/O Card Space
GP58 LDD[0] ALT_FN_2_OUT 10 LCD data pin 0
GP59 LDD[1] ALT_FN_2_OUT 10 LCD data pin 1
GP60 LDD[2] ALT_FN_2_OUT 10 LCD data pin 2
GP61 LDD[3] ALT_FN_2_OUT 10 LCD data pin 3
LCD Controller
GP62 LDD[4] ALT_FN_2_OUT 10 LCD data pin 4
GP63 LDD[5] ALT_FN_2_OUT 10 LCD data pin 5
GP64 LDD[6] ALT_FN_2_OUT 10 LCD data pin 6
GP65 LDD[7] ALT_FN_2_OUT 10 LCD data pin 7
LDD[8] ALT_FN_2_OUT 10 LCD Controller LCD data pin 8
GP66 memory controller alternate bus
MBREQ ALT_FN_1_IN 01 Memory Controller
master req
LDD[9] ALT_FN_2_OUT 10 LCD Controller LCD data pin 9
GP67 Multimedia Card
MMCCS0 ALT_FN_1_OUT 01 MMC Chip Select 0
(MMC) Controller
Multimedia Card
MMCCS1 ALT_FN_1_OUT 01 MMC Chip Select 1
GP68 (MMC) Controller
LDD[10] ALT_FN_2_OUT 10 LCD Controller LCD data pin 10
Multimedia Card
MMCCLK ALT_FN_1_OUT 01 MMC_CLK
GP69 (MMC) Controller
LDD[11] ALT_FN_2_OUT 10 LCD Controller LCD data pin 11
System Integation
RTCCLK ALT_FN_1_OUT 01 Real Time clock (1 Hz)
GP70 Unit
LDD[12] ALT_FN_2_OUT 10 LCD Controller LCD data pin 12
Clocks & Power
3.6 MHz ALT_FN_1_OUT 01 3.6 MHz Oscillator clock
GP71 Manager Unit
LDD[13] ALT_FN_2_OUT 10 LCD Controller LCD data pin 13
Clocks & Power
32 kHz ALT_FN_1_OUT 01 32 kHz clock
GP72 Manager Unit
LDD[14] ALT_FN_2_OUT 10 LCD Controller LCD data pin 14
LDD[15] ALT_FN_2_OUT 10 LCD Controller LCD data pin 15
GP73
MBGNT ALT_FN_1_OUT 01 Memory Controller Memory controller grant
Note: All GPIO registers are initialized to 0x0 at reset, which results in all GPIO pins being initialized as
inputs.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PL31
PL30
PL29
PL28
PL27
PL26
PL25
PL24
PL23
PL22
PL21
PL20
PL19
PL18
PL17
PL16
PL15
PL14
PL13
PL12
PL10
PL11
PL9
PL8
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This is read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PL63
PL62
PL61
PL60
PL59
PL58
PL57
PL56
PL55
PL54
PL53
PL52
PL51
PL50
PL49
PL48
PL47
PL46
PL45
PL44
PL43
PL42
PL41
PL40
PL39
PL38
PL37
PL36
PL35
PL34
PL33
PL32
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This is read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PL84
PL83
PL82
PL81
PL80
PL79
PL78
PL77
PL76
PL75
PL74
PL73
PL72
PL71
PL70
PL69
PL68
PL67
PL66
PL65
PL64
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
<31:21> — reserved
GPIO Pin Level ‘x’ (where x = 64 to 80).
This read-only field indicates the current value of each GPIO.
<20:0> PL[x]
0 – Pin state is low
1 – Pin state is high
Note: A reset clears all bits in the GPDR0-2 registers and configures all GPIO pins as inputs.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD31
PD30
PD29
PD28
PD27
PD26
PD25
PD24
PD23
PD22
PD21
PD20
PD19
PD18
PD17
PD16
PD15
PD14
PD13
PD12
PD10
PD11
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD63
PD62
PD61
PD60
PD59
PD58
PD57
PD56
PD55
PD54
PD53
PD52
PD51
PD50
PD49
PD48
PD47
PD46
PD45
PD44
PD43
PD42
PD41
PD40
PD39
PD38
PD37
PD36
PD35
PD34
PD33
PD32
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD84
PD83
PD82
PD81
PD80
PD79
PD78
PD77
PD76
PD75
PD74
PD73
PD72
PD71
PD70
PD69
PD68
PD67
PD66
PD65
PD64
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
<31:21> — reserved
GPIO Pin ‘x’ Direction (where x = 64 to 80).
<20:0> PD[x] 0 – Pin configured as an input.
1 – Pin configured as an output
4.1.3.3 GPIO Pin Output Set Registers (GPSR0, GPSR1, and GPSR2) and Pin
Output Clear Registers (GPCR0, GPCR1, GPCR2)
When a GPIO is configured as an output, the state of the pin can be controlled by writing to either
the GPSR or GPCR. An output pin is set high by writing a one to its corresponding bit within the
GPSR. To clear an output pin, a one is written to the corresponding bit within the GPCR. GPSR
and GPCR are write-only registers. Reads return unpredictable values.
Writing a zero to any of the GPSR or GPCR bits has no effect on the state of the pin. Writing a one
to a GPSR or GPCR bit corresponding to a pin that is configured as an input is effective only after
the pin is configured as an output. Reserved bits (GPSR2[31:17] and GPCR2[31:17]), must be
written with zeros and reads must be ignored.
Table 4-9, Table 4-10, and Table 4-11 show the bit definitions of GPSR0, GPSR1, and GPSR2.
Table 4-12, Table 4-13, and Table 4-14 show the bit definitions of GPCR0, GPCR1, and GPCR2.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PS31
PS30
PS29
PS28
PS27
PS26
PS25
PS24
PS23
PS22
PS21
PS20
PS19
PS18
PS17
PS16
PS15
PS14
PS13
PS12
PS10
PS11
PS9
PS8
PS7
PS6
PS5
PS4
PS3
PS2
PS1
PS0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PS63
PS62
PS61
PS60
PS59
PS58
PS57
PS56
PS55
PS54
PS53
PS52
PS51
PS50
PS49
PS48
PS47
PS46
PS45
PS44
PS43
PS42
PS41
PS40
PS39
PS38
PS37
PS36
PS35
PS34
PS33
PS32
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PS84
PS83
PS82
PS81
PS80
PS79
PS78
PS77
PS76
PS75
PS74
PS73
PS72
PS71
PS70
PS69
PS68
PS67
PS66
PS65
PS64
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
<31:21> — reserved
GPIO Pin ‘x’ Output Pin Set (where x= 64 through 80).
<20:0> PS[x] 0 – Pin level unaffected.
1 – If pin configured as an output, set pin level high (one).
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PC31
PC30
PC29
PC28
PC27
PC26
PC25
PC24
PC23
PC22
PC21
PC20
PC19
PC18
PC17
PC16
PC15
PC14
PC13
PC12
PC10
PC11
PC9
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PC63
PC62
PC61
PC60
PC59
PC58
PC57
PC56
PC55
PC54
PC53
PC52
PC51
PC50
PC49
PC48
PC47
PC46
PC45
PC44
PC43
PC42
PC41
PC40
PC39
PC38
PC37
PC36
PC35
PC34
PC33
PC32
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PC84
PC83
PC82
PC81
PC80
PC79
PC78
PC77
PC76
PC75
PC74
PC73
PC72
PC71
PC70
PC69
PC68
PC67
PC66
PC65
PC64
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
<31:21> — reserved
GPIO Pin ‘x’ Output Pin Clear (where x= 64 through 80).
<20:0> PC[x] 0 – Pin level unaffected.
1 – If pin configured as an output, clear pin level low (zero).
4.1.3.4 GPIO Rising Edge Detect Enable Registers (GRER0, GRER1, GRER2)
and Falling Edge Detect Enable Registers (GFER0, GFER1, GFER2)
Each GPIO can also be programmed to detect a rising-edge, falling-edge, or either transition on a
pin. When an edge is detected that matches the type of edge programmed for the pin, a status bit is
set. The interrupt controller can be programmed so that an interrupt is signalled to the core when
any of these status bits are set. Additionally, the interrupt controller can be programmed so that a
subset of the status bits causes the processor to wake from Sleep mode when they are set. Refer to
Section 3.4.9, “Sleep Mode” on page 3-15 and Section 3.5.6, “Power Manager GPIO Edge Detect
Status Register (PEDR)” on page 3-28 for more information on which status bits can cause a wake
up from Sleep mode.
Use the GRER and the GFER to select the type of transition on a GPIO pin that causes a bit within
the GPIO Edge Detect Enable Status register (GEDR) to be set. For a given GPIO pin, its
corresponding GRER bit is set causing a GEDR status bit to be set when the pin transitions from
logic level zero to logic level one. Likewise, the GFER is used to set the corresponding GEDR
status bit when a transition from logic level one to logic level zero occurs. When the corresponding
bits are set in both registers, either a falling- or a rising-edge transition causes the corresponding
GEDR status bit to be set.
Note: The minimum pulse width duration to guarantee edge detection is 1µS.
Table 4-15 through Table 4-17 show the bitmaps of the GRER0, GRER1, and GRER2. Table 4-18
through Table 4-20 show the bitmaps of the GFER, GFER1, and GFER2.
Note: For reserved bits in GRER2 and GFER2, writes must be zeros and reads must be ignored.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RE31
RE30
RE29
RE28
RE27
RE26
RE25
RE24
RE23
RE22
RE21
RE20
RE19
RE18
RE17
RE16
RE15
RE14
RE13
RE12
RE10
RE11
RE9
RE8
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIO Pin ‘x’ Rising Edge Detect Enable (where x = 0 through 31).
<31:0> RE[x] 0 – Disable rising-edge detect enable.
1 – Set corresponding GEDR status bit when a rising edge is detected on the GPIO pin
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RE63
RE62
RE61
RE60
RE59
RE58
RE57
RE56
RE55
RE54
RE53
RE52
RE51
RE50
RE49
RE48
RE47
RE46
RE45
RE44
RE43
RE42
RE41
RE40
RE39
RE38
RE37
RE36
RE35
RE34
RE33
RE32
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIO Pin ‘x’ Rising Edge Detect Enable (where x = 32 through 63).
<31:0> RE[x] 0 – Disable rising-edge detect enable.
1 – Set corresponding GEDR status bit when a rising edge is detected on the GPIO pin
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RE84
RE83
RE82
RE81
RE80
RE79
RE78
RE77
RE76
RE75
RE74
RE73
RE72
RE71
RE70
RE69
RE68
RE67
RE66
RE65
RE64
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
<31:21> — reserved
GPIO Pin ‘x’ Rising Edge Detect Enable (where x = 64 through 80).
<20:0> RE[x] 0 – Disable rising-edge detect enable.
1 – Set corresponding GEDR status bit when a rising edge is detected on the GPIO pin
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FE31
FE30
FE29
FE28
FE27
FE26
FE25
FE24
FE23
FE22
FE21
FE20
FE19
FE18
FE17
FE16
FE15
FE14
FE13
FE12
FE10
FE11
FE9
FE8
FE7
FE6
FE5
FE4
FE3
FE2
FE1
FE0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIO Pin ‘x’ Falling Edge Detect Enable (where x = 0 through 31).
<31:0> FE[x] 0 – Disable falling-edge detect enable.
1 – Set corresponding GEDR status bit when a falling edge is detected on the GPIO pin
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FE63
FE62
FE61
FE60
FE59
FE58
FE57
FE56
FE55
FE54
FE53
FE52
FE51
FE50
FE49
FE48
FE47
FE46
FE45
FE44
FE43
FE42
FE41
FE40
FE39
FE38
FE37
FE36
FE35
FE34
FE33
FE32
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIO Pin ‘x’ Falling Edge Detect Enable (where x = 32 through 63).
<31:0> FE[x] 0 – Disable falling-edge detect enable.
1 – Set corresponding GEDR status bit when a falling edge is detected on the GPIO pin
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FE84
FE83
FE82
FE81
FE80
FE79
FE78
FE77
FE76
FE75
FE74
FE73
FE72
FE71
FE70
FE69
FE68
FE67
FE66
FE65
FE64
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
<31:21> — reserved
GPIO Pin ‘x’ Falling Edge Detect Enable (where x = 64 through 80).
<20:0> FE[x] 0 – Disable falling-edge detect enable.
1 – Set corresponding GEDR status bit when a falling edge is detected on the GPIO pin
Each edge detect that sets the corresponding GEDR status bit for GPIO[80:0] can trigger an
interrupt request. GPIO[80:2] together form a group that can cause one interrupt request to be
triggered when any one of GEDR[80:2] are set. GPIO[0] and GPIO[1] cause independent first-
level interrupts. Refer to Section 4.2, for a description of the programming of GPIO interrupts.
Table 4-21 through Table 4-23 show the bitmaps of the GEDR0, GEDR1, and GEDR2.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ED31
ED30
ED29
ED28
ED27
ED26
ED25
ED24
ED23
ED22
ED21
ED20
ED19
ED18
ED17
ED16
ED15
ED14
ED13
ED12
ED10
ED11
ED9
ED8
ED7
ED6
ED5
ED4
ED3
ED2
ED1
ED0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ED63
ED62
ED61
ED60
ED59
ED58
ED57
ED56
ED55
ED54
ED53
ED52
ED51
ED50
ED49
ED48
ED47
ED46
ED45
ED44
ED43
ED42
ED41
ED40
ED39
ED38
ED37
ED36
ED35
ED34
ED33
ED32
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ED84
ED83
ED82
ED81
ED80
ED79
ED78
ED77
ED76
ED75
ED74
ED73
ED72
ED71
ED70
ED69
ED68
ED67
ED66
ED65
ED64
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
<31:21> — reserved
GPIO Pin ‘x’ Edge Detect Status (where x=64 through 80).
READ
0 – No edge detect has occurred on pin as specified in GRER and/or GFER.
<20:0> ED[x] 1 – Edge detect has occurred on pin as specified in GRER and/or GFER.
WRITE
0 – No effect.
1 – Clear edge detect status field.
Caution: Configuring a GPIO to map to an alternate function that is not available causes indeterminate
results.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AF15 AF14 AF13 AF12 AF11 AF10 AF9 AF8 AF7 AF6 AF5 AF4 AF3 AF2 AF1 AF0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIO Pin ‘x’ Alternate Function Select Bits (where x=0 through 15).
A bit-pair in this register determines the corresponding GPIO pin’s functionality as one of
the alternate functions that is mapped to it or as a generic GPIO pin.
<31:0> AF[x] 00 – The corresponding GPIO pin (GPIO[x]) is used as a general purpose I/O.
01 – The corresponding GPIO pin (GPIO[x]) is used for its alternate function 1.
10 – The corresponding GPIO pin (GPIO[x]) is used for its alternate function 2.
11 – The corresponding GPIO pin (GPIO[x]) is used for its alternate function 3.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AF31 AF30 AF29 AF28 AF27 AF26 AF25 AF24 AF23 AF22 AF21 AF20 AF19 AF18 AF17 AF16
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIO Pin ‘x’ Alternate Function Select Bits (where x=16 through 31).
A bit-pair in this register determines the corresponding GPIO pin’s functionality as one of
the alternate functions that is mapped to it or as a generic GPIO pin.
<31:0> AF[x] 00 – The corresponding GPIO pin (GPIO[x]) is used as a general purpose I/O.
01 – The corresponding GPIO pin (GPIO[x]) is used for its alternate function 1.
10 – The corresponding GPIO pin (GPIO[x]) is used for its alternate function 2.
11 – The corresponding GPIO pin (GPIO[x]) is used for its alternate function 3.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AF47 AF46 AF45 AF44 AF43 AF42 AF41 AF40 AF39 AF38 AF37 AF36 AF35 AF34 AF33 AF32
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIO Pin ‘x’ Alternate Function Select Bits (where x=32 through 47).
A bit-pair in this register determines the corresponding GPIO pin’s functionality as one of
the alternate functions that is mapped to it or as a generic GPIO pin.
<31:0> AF[x] 00 – The corresponding GPIO pin (GPIO[x]) is used as a general purpose I/O.
01 – The corresponding GPIO pin (GPIO[x]) is used for its alternate function 1.
10 – The corresponding GPIO pin (GPIO[x]) is used for its alternate function 2.
11 – The corresponding GPIO pin (GPIO[x]) is used for its alternate function 3.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AF63 AF62 AF61 AF60 AF59 AF58 AF57 AF56 AF55 FA54 AF53 AF52 AF51 AF50 AF49 AF48
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIO Pin ‘x’ Alternate Function Select Bits (where x=48 through 63).
A bit-pair in this register determines the corresponding GPIO pin’s functionality as one of
the alternate functions that is mapped to it or as a generic GPIO pin.
<31:0> AF[x] 00 – The corresponding GPIO pin (GPIO[x]) is used as a general purpose I/O.
01 – The corresponding GPIO pin (GPIO[x]) is used for its alternate function 1.
10 – The corresponding GPIO pin (GPIO[x]) is used for its alternate function 2.
11 – The corresponding GPIO pin (GPIO[x]) is used for its alternate function 3.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AF79 AF78 AF77 AF76 AF75 AF74 AF73 AF72 AF71 AF70 AF69 AF68 AF67 AF66 AF65 AF64
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPIO Pin ‘x’ Alternate Function Select Bits (where x=64 through 79).
A bit-pair in this register determines the corresponding GPIO pin’s functionality as one of
the alternate functions that is mapped to it or as a generic GPIO pin.
<31:0> AF[x] 00 – The corresponding GPIO pin (GPIO[x]) is used as a general purpose I/O.
01 – The corresponding GPIO pin (GPIO[x]) is used for its alternate function 1.
10 – The corresponding GPIO pin (GPIO[x]) is used for its alternate function 2.
11 – The corresponding GPIO pin (GPIO[x]) is used for its alternate function 3.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
<31:10> — reserved
GPIO Pin ‘x’ Alternate Function Select Bits (where x=80 through 84).
A bit-pair in this register determines the corresponding GPIO pin’s functionality as one of
the alternate functions that is mapped to it or as a generic GPIO pin.
<9:0> AF[x] 00 – The corresponding GPIO pin (GPIO[x]) is used as a general purpose I/O.
01 – The corresponding GPIO pin (GPIO[x]) is used for its alternate function 1.
10 – The corresponding GPIO pin (GPIO[x]) is used for its alternate function 2.
11 – The corresponding GPIO pin (GPIO[x]) is used for its alternate function 3.
In this example,
• GPIO[0] is configured as a normal GPIO input
This programming sequence is required for programming the GPIO alternate functions out of reset:
1. WRITE GPSR0 0x0000_8000 – this sets GPIO15 (active low chip select) when it is configured
as an output.
2. WRITE GPDR0 0x0000_BFC0 – GPIO[12:6], GPIO[13] and GPIO[15] as outputs. This drives
GPIO[15] high until the alternate function information is programmed. This is required for active
low outputs.
For GPIOs that need to be configured as outputs, you must first program the GPSR and GPCR
signals so the pin direction is changed. Change pin direction by setting the bit in the GPDR
register—a ‘0’ is driven for active high signals and ‘1’ for active low signals.
Note: For more information on alternate functions, refer to the Source Unit column in Table 4-1 for the
appropriate section of this document.
Table 4-24 through Table 4-29 show the bitmaps of the GPIO Alternate Function registers.
— Interrupt Controller FIQ Pending Register (ICFP) – contains the interrupts from all
sources that can generate an FIQ interrupt. The Interrupt Controller Level register (ICLR)
is programmed to send interrupts to the ICFP to generate an FIQ.
• The second level uses registers contained in the source device (the device generating the first-
level interrupt bit). The second-level interrupt status gives additional information about the
interrupt and is used inside the interrupt service routine. In general, multiple second-level
interrupts are OR’ed to produce a first-level interrupt bit.
In most cases, the root cause of an interrupt can be determined by reading two register locations:
the ICIP for an IRQ interrupt or the ICFP for an FIQ interrupt to determine the interrupting device.
You then read the status register within that device to find the exact function requesting service.
When the ICCR[DIM] bit is zero, the Interrupt Mask Register is ignored during Idle mode, and all
enabled interrupts cause the processor to exit from idle mode. Otherwise, only unmasked interrupts
cause the processor to exit from idle mode. The reset state of ICCR[DIM] is zero.
IRQ
Interrupt Pending Interrupt
Register (ICPR) to
Processor
IRQ Interrupt
Pending Register
(ICIP)
FIQ Interrupt
Pending Register
(ICFP)
After a reset, the FIQ and IRQ interrupts are disabled within the CPU, and the states of all of the
interrupt controller registers are set to 0x0. The interrupt controller registers must be initialized by
software before interrupts are again enabled within the CPU.
Mask bits allow periodic software polling of interruptible sources while preventing them from
actually causing an interrupt. The ICMR is initialized to zero at reset, indicating that all interrupts
are masked and the ICMR has to be configured by the user to select the desired interrupts.
Table 4-36 describes the available first-level interrupts and their location in the ICPR.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
reserved
IM31
IM30
IM29
IM28
IM27
IM26
IM25
IM24
IM23
IM22
IM21
IM20
IM19
IM18
IM17
IM14
IM13
IM12
IM10
IM11
IM9
IM8
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ?
Table 4-36 describes the available first-level interrupts and their location in the ICPR.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
reserved
IL31
IL30
IL29
IL28
IL27
IL26
IL25
IL24
IL23
IL22
IL21
IL20
IL19
IL18
IL17
IL14
IL13
IL12
IL10
IL11
IL9
IL8
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ?
Table 4-36 describes the available first-level interrupts and their location in the ICPR.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIM
reserved
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0
<31:1> — reserved
Disable Idle mask.
0 – All enabled interrupts bring the processor out of idle mode.
<0> DIM 1 – Only enabled and unmasked (as defined in the ICMR) bring the processor out of idle
mode.
This bit is cleared during all resets.
4.2.2.4 Interrupt Controller IRQ Pending Register (ICIP) and FIQ Pending
Register (ICFP)
The ICIP and the ICFP, shown in Table 4-33 and Table 4-34, contain one bit per interrupt (22 total.)
These bits indicate an interrupt request has been made by a unit. Inside the interrupt service
routine, read the ICIP and ICFP to determine the interrupt source. In general, software then reads
status registers within the interrupting device to determine how to service the interrupt. Bits within
the ICPR (see Section 4.2.2.5) are read only, and represent the logical OR of the status bits in the
ICIP and ICFP for a given interrupt. Once an interrupt has been serviced, the handler writes a one
to the required status bit, clearing the pending interrupt at the source.
Clearing the interrupt status bit at the source, automatically clears the corresponding ICIP or ICFP
flag, provided there are no other interrupt status bits set within the source unit.
Table 4-36 describes the available first-level interrupts and their location in the ICPR.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
reserved
IP31
IP30
IP29
IP28
IP27
IP26
IP25
IP24
IP23
IP22
IP21
IP20
IP19
IP18
IP17
IP14
IP13
IP12
IP10
IP11
IP9
IP8
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ?
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
reserved
FP31
FP30
FP29
FP28
FP27
FP26
FP25
FP24
FP23
FP22
FP21
FP20
FP19
FP18
FP17
FP14
FP13
FP12
FP10
FP11
FP9
FP8
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ?
Table 4-36 shows the pending interrupt source assigned to each bit position in the ICPR. Also
included in the table are the source units for the interrupts and the number of second-level
interrupts associated with each. For more information on the second-level interrupts, see the
section that corresponds to its name in the Source Unit column.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
reserved
IS31
IS30
IS29
IS28
IS27
IS26
IS25
IS24
IS23
IS22
IS21
IS20
IS19
IS18
IS17
IS14
IS13
IS12
IS10
IS11
IS9
IS8
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
reserved
IS31
IS30
IS29
IS28
IS27
IS26
IS25
IS24
IS23
IS22
IS21
IS20
IS19
IS18
IS17
IS14
IS13
IS12
IS10
IS11
IS9
IS8
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
reserved
IS31
IS30
IS29
IS28
IS27
IS26
IS25
IS24
IS23
IS22
IS21
IS20
IS19
IS18
IS17
IS14
IS13
IS12
IS10
IS11
IS9
IS8
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Several units have more than one source per interrupt signal. When an interrupt is signalled from
one of these units, the interrupt handler routine identifies which interrupt was signalled using the
interrupt controller’s pending register. This identifies the unit that made the request, but not the
exact source. The handler then reads the interrupting unit’s status register to identify which source
within the unit signalled the interrupt. For all interrupts that have one corresponding source, the
interrupt handler routine needs to use only the interrupt controller’s registers to identify the exact
cause of the interrupt. ICPR[16:15] and ICPR[7:0] are reserved bits and must be written as zeros.
Reads to these bits must be ignored.
In addition to the RCNR, the RTC incorporates a 32-bit, RTC Alarm register (RTAR). The RTAR
may be programmed with a value that is compared against the RCNR. One 32-kHz cycle after each
rising edge of the HZ clock, the counter is incremented and then compared to the RTAR. If the
values match, and the enable bit is set, then the RTC Status register (RTSR) alarm match bit
(RTSR[AL]) is set. This status bit is also routed to the interrupt controller and may be unmasked in
the interrupt controller to generate a processor interrupt. Another available interruptible status bit
that can be set whenever the HZ clock transitions is the RTSR. By writing a one to the AL or HZ
bit in the RTSR, the status bit is cleared.
The HZ clock is generated by dividing one of two selectable clock sources, both approximately
32.768 kHz in frequency. The first source is the output of the 3.6864 MHz crystal oscillator further
divided by 112 to approximately 32.914 kHz. The other source is the optional 32.768 kHz crystal
oscillator output itself. Your system may be built with both the 32.768 kHz crystal oscillator and
the 3.6864 MHz crystal oscillator. ALternately, your system may only use the 3.6864 MHz crystal
oscillator, if the additional power consumption during sleep mode is acceptable.
The divider logic for generating the HZ clock is programmable. This lets you trim the counter to
adjust for inherent inaccuracies in the crystal’s frequency and the inaccuracy caused by the division
of the 3.6864 MHz oscillator which yields only an approximate 32 kHz frequency. The trimming
mechanism lets you adjust the RTC to an accuracy of +/- 5 seconds per month. The trimming
procedure is described in a later paragraph.
All registers in the RTC, with the exception RTTR, are reset by hardware reset and the watchdog
reset. The trim register, RTTR is reset only by hardware reset.
All reserved bits must be written to zeros and reads to these bits must be ignored. You can only
reset the RTTR with a hardware reset. To safeguard the validity of the data written into the trim
register, bit 31 is used as a Lock Bit. The data in RTTR may be changed only if RTTR[LCK] is
cleared. Once, RTTR[LCK] is set to be a one, only a hardware reset can clear the RTTR.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK
Reset 0 ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Because of the asynchronous nature of the HZ clock relative to the processor clock, writes to this
register are controlled by a hardware mechanism that delays the actual write to the register by two
32 kHz clock cycles after the processor store is performed.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTMV
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Because of the asynchronous nature of the HZ clock relative to the processor clock, writes to this
counter are controlled by a hardware mechanism that delays the actual write to the counter after the
processor store is performed by approximately two 32 kHz clock cycles. In case of multiple writes
to RCNR in quick succession, the final update to the RCNR counter may be delayed by up to two
32 kHz clock cycles.
The RCNR may be read at any time. Reads reflect the value in the counter after it increments or has
been written and does not have the two 32 kHz clock cycle delay.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCV
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
In Sleep mode, only AL events set the status bit in the RTSR register. The HZ bit is not set in Sleep
mode since it is a recurring event.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HZE
ALE
HZ
AL
reserved
Reset ? ? ? ? ? ? ? ? ? ? ? ? / ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0
<31:4> — reserved
HZ interrupt enable.
<3> HZE 0 – The HZ interrupt is not enabled.
1 – The HZ interrupt is enabled.
RTC alarm interrupt enable.
<2> ALE 0 – The RTC alarm interrupt is not enabled.
1 – The RTC alarm interrupt is enabled.
HZ rising-edge detected.
<1> HZ 0 – No rising edge has been detected.
1 – A rising edge has been detected and HZE bit is set.
RTC alarm detected.
<0> AL 0 – No RTC alarm has been detected.
1 – An RTC alarm has been detected (RTNR matches RCAR).and ALE bit is set
The RTTR is reset to its default value of 0x0000_7FFF each time the nRESET signal is asserted.
This yields approximately a 1 Hz clock.
When the clock divisor count (RTTR[15:0]) is set to 0x0, the HZ clock feeding the RTC maintains
a high level signal - essentially disabling the RTC. For all non-zero values programmed into the
clock divisor count, the HZ clock frequency will be the 32 kHz clock source divided by the clock
divisor count plus 1.
The fractional part of the adjustment is done by periodically deleting clocks from the clock stream
driving the integer counter. The trim interval period is hardwired to be 210-1 periods of the HZ
clock. If the HZ clock is programed to be 1 Hz the trim interval would be approximately 17
minutes. The number of clocks deleted (the trim delete value) is a 10-bit programmable counter
allowing from 0 to 210-1 32 kHz clocks to be deleted from the input clock stream once per trim
interval. RTTR[25:16] represents the number of 32 kHz clocks deleted per trim operation.
In summary, every 210-1 HZ clock periods, the integer counter stops clocking for a period equal to
the fractional error that has accumulated. If this fractional error is programmed to be zero, then no
trim operations occur and the RTC is clocked with the raw 32 kHz clock. The relationship between
the HZ clock frequency and the nominal 32 kHz clock (f1 and f32K, respectively) is shown in the
following equation.
f1 = HZ clock frequency
f32k = RTC internal clock - either the 32.678 kHz crystal output or the 3.68 MHz crystal
output divided down to 32.914 kHz
RTTR[DEL] = RTTR(25:16)
RTTR[CK_DIV] = RTTR(15:0)
This example is more common in that the measured frequency of the oscillator has a fractional
component. Again, the desired HZ clock output frequency is 1 Hz. If the oscillator output is
measured as 32768.92 cycles/s (Hz), an integer trim is necessary so that the average number of
cycles counted before generating one 1 Hz clock is 32768.92. Similar to the previous example, the
integer field RTTR[15:0] is loaded with the hexadecimal equivalent of 32768-1 or 0x0000_7FFF
(reset value).
Because the actual clock frequency is 0.92 cycles per second faster than the integer value, the HZ
clock generated by just the integer trimming is slightly faster than needed and must be slowed
down. Accordingly, program the fractional trim to delete 0.92 cycles per second on average to
bring the HZ output frequency down to the proper value. Since the trimming procedure is
performed every 1023 (210 -1) seconds, the trim must be set to delete 941.16 clocks every 1023
seconds (.92 x 1023 = 941.16). Load the counter with the hexadecimal equivalent of 941, or
0x3AD. The fractional component of this value cannot be trimmed out and constitutes the error in
trimming, described below.
This trim setting leaves an error of. 16 cycles per 1023 seconds. The error calculation yields (in
parts-per-million or ppm):
As seen from trim example #2, the maximum possible error approaches 1 clock per 210-1 seconds.
Calculating the ppm error for this scenario yields:
To maintain an accuracy of +/- 5 seconds per month, the required accuracy is calculated to be:
5 sec- X -----------------------------
Error = -------------- 1 month - = 1.9 ppm
month 2592000 sec
This calculation indicates that the HZ clock output can be made very accurate through the use of
the trim procedure. Likewise, use the trim procedure to compensate for a range of factors that can
affect crystal oscillators. Such factors can include, but are not limited to:
• Manufacturing and supplier variance in the crystals
• Crystal aging effects
• System voltage differences
• System manufacturing variance
The trim procedure can counteract these factors by providing a highly accurate mechanism to
remove the variance and shifts from the manufacturing and static environment variables on an
individual system level. However, since this is a calibration solution, it is not a practical solution
for dynamic changes in the system and environment and can most likely only be done in a factory
setting due to the equipment required.
also routed to the interrupt controller where they can be programmed to cause an interrupt. OSMR3
also serves as a watchdog match register that resets the processor when a match occurs provided
the OS Timer Watchdog Match Enable Register (OWER) is set. You must initialize the OSCR and
OSMR registers and clear any set status bits before the FIQ and IRQ interrupts are enabled within
the CPU.
The following procedure is suggested when using OSMR3 as a watchdog – each time the operating
system services the register:
1. The current value of the counter is read.
2. An offset is then added to the read value. This offset corresponds to the amount of time before
the next time-out (care must be taken to account for counter wraparound).
3. The updated value is written back to OSMR3.
The OS code must repeat this procedure periodically before each match occurs. If a match occurs,
the OS timer asserts a reset to the processor.
Table 4-41 shows the bitmap of the OS Timer Match register. All four registers are identical, except
for location. A single, generic OS Timer match register is described, but all information is common
to all four OS Timer Match Registers.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSMV
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
E3
E2
E1
E0
reserved
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0
<31:4> — reserved
Interrupt enable channel 3.
<3> E3 0 – A match between OSMR3 and the OS Timer will NOT assert OSSR[M3].
1 – A match between OSMR3 and the OS Timer asserts OSSR[M3].
Interrupt enable channel 2.
<2> E2 0 – A match between OSMR2 and the OS Timer will NOT assert OSSR[M2].
1 – A match between OSMR2 and the OS Timer asserts OSSR[M2].
Interrupt enable channel 1.
<1> E1 0 – A match between OSMR1 and the OS Timer will NOT assert OSSR[M1].
1 – A match between OSMR1 and the OS Timer asserts OSSR[M1].
Interrupt enable channel 0.
<0> E0 0 – A match between OSMR0 and the OS Timer will NOT assert OSSR[M0].
1 – A match between OSMR0 and the OS Timer asserts OSSR[M0].
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WME
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
<31:1> — reserved
Watchdog Match Enable
<0> WME 0 – OSMR3 match will NOT cause a reset of the processor
1 – OSMR3 match causes a reset of the processor.
After the OSCR is written, there is a delay before the register is actually updated. Software must
make sure the register has changed to the new value before relying on the contents of the register.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSCV
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M3
M2
M1
M0
reserved
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0
<31:4> — reserved
Match status channel 3.
If OIER[3] is set then:
<3> M3
0 – OSMR[3] has NOT matched the OS timer counter since last being cleared.
1 – OSMR[3] has matched the OS timer counter.
Match status channel 2.
If OIER[2] is set then:
<2> M2
0 – OSMR[2] has NOT matched the OS timer counter since last being cleared.
1 – OSMR[2] has matched the OS timer counter.
Match status channel 1.
If OIER[1] is set then:
<1> M1
0 – OSMR[1] has NOT matched the OS timer counter since last being cleared.
1 – OSMR[1] has matched the OS timer counter.
Match status channel 0.
If OIER[0] is set then:
<0> M0
0 – OSMR[0] has NOT matched the OS timer counter since last being cleared.
1 – OSMR[0] has matched the OS timer counter.
Clock Gate
Value of
PWM_CTRLn[PRESCALE]
Value of
PWM_PERVALn[PV]
Comparator RESET
Bus
Interfac
PWM_OUTn
10-bit up counter
PSCLK_PWMn FLIP-FLOP
Comparator SET
Value of
PWM_DUTYn[DCYCLE]
4.5.1.1 Interdependencies
The PWM unit is clocked off the 3.6864 MHz oscillator output.
Each register contains one or more fields which determine an attribute of the PWM_OUTn
waveform. PWM_CTRLn[PRESCALE] specifies the divisor for the PWM module clock. Note
that the actual PWM module clock divisor used is 1 greater than the value programmed into
PWM_CTRLn[PRESCALE]. This divided PWM module clock drives a 10 bit up-counter. This up-
counter feeds 2 separate comparators. The first comparator contains the value of
PWM_DUTYn[DCYCLE]. When the values match, the PWM_OUT signal is set high. The other
comparator contains PWM_PERVALn[PV] and clears the PWM_OUT signal low when
PWM_PERVALn[PV] + 1 and the 10-bit up counter are equal. Both PWM_PERVALn[PV] and
PWM_DUTYn[DCYCLE] are 10 bit fields.
Note: Take care to ensure that the value of the PWM_PERVALn register remains larger than
PWM_DUTYn register. In the case where PWM_PERVALn is less than PWM_DUTYn the output
maintains a high state.
Note: The value of the divisor is one greater than the value programmed into the PRESCALE field.
• PWM_SD – PWMn can shut down in one of two ways, gracefully or abruptly, depending on
the setting of PWM_CTRLn[PWM_SD]. If gracefully is chosen, then the duty cycle counter
completes its count before PWMn is shut down. If abruptly is chosen, then the prescale
counter and the duty cycle counter are reset to the reload values in their associated registers
and PWMn is immediately shut down.
Note: During abrupt shut down the PWM_OUTn signal may be delayed by up to one PSCLK_PWMn
clock period.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWM_SD
reserved PRESCALE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
<31:7> — reserved
PWMn Shutdown Method:
<6> PWM_SD 0 – Graceful shutdown of PWMn when the clock enable bit in the CKEN register is
cleared.
1 – Abrupt shutdown of PWMn when the clock enable bit in the CKEN register is cleared.
PWMn Prescale Divisor.
<5:0> PRESCALE Determines the frequency of the PWM module clock (in terms of the 3.86 MHz clock)
PSCLK_PWMn = 3.6864 MHz / (PWM_CTRL[PRESCALE] + 1)
If FDCYCLE=0x0 and DCYCLE=0x0, PWM_OUTn is set low and does not toggle.
Note: If FDCYCLE is 0b1, PWM_OUTn is high for the entire period and is not influenced by the value
programmed in the DCYCLE bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDCYCLE
reserved DCYCLE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
<31:11> — reserved
PWMn Full Duty Cycle
<10> FDCYCLE 0 – PWM clock (PWM_OUTn) duty cycle is determined by DCYCLE field.
1 – PWM_OUTn is set high and does not toggle.
PWMn Duty Cycle
<9:0> DCYCLE Duty cycle of PWMn clock, i.e. the number of PSCLK_PWM cycles PWMn is asserted
within one cycle of PWMn.
The PWM_PERVALn, shown in Table 4-48, contains a 10 bit field called PV. This field determines
the period of the PWM_OUTn waveform in terms of the PSCLK_PWMn clock. If this field is
cleared to zero PWMn is effectively turned off and PWM_OUTn remains in a high state. For any
non-zero value written to the PV field, the output frequency of PWMn is the frequency of the
PSCLK_OUTn divided by the value of (PV + 1). The range of the clock gate extends from a pass-
through of the PSCLK_PWMn to a clock delay of 26 or 64 input clocks per output pulse.
When the value of the 10 bit up-counter equals the value of (PV +1), the up-counter and the flip-
flop are reset and the values of PWM_CTRLn, PWM_PERVALn and PWM_DUTYn are loaded
into the internal versions of these registers. Resetting this flip-flop causes PWM_OUTn to go low
and the PWM cycle to start again.
Writing all zeroes to this register results in the output maintaining a high state unless
FDCYCLE=0x0 and DCYCLE=0x0. If FDCYCLE=0x0 and DCYCLE=0x0, the output maintains
a low state regardless of the value in the PV bit field.
Note: Due to internal timing requirements, all changes to any of the PWM registers must be complete a
minimum of 4 core clock cycles before the start of end of a PWM clock cycle in order to guarantee
that the following PWM cycle implements the new values.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PV
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
<31:10> — reserved
PWMn Period Control:
The number of PSCLK_PWMn cycles that comprise one PWM_OUTn cycle
<9:0> PV NOTE: If PV = 0x0, the PWMn clock (PWM_OUTn) is set high and does not toggle unless
FDCYCLE=0x0 and DCYCLE=0x0. In this case PWM_OUTn is set low and does
not toggle regardless of the value in PV.
3.6864 MHz
PSCLK_PWMn
PWM_DUTYn = 6
PWM_OUTn
PWM_PERVALn = 10 (+1)
PWM_PERVAL[PV] = 0xA
PWM_DUTY[FDCYCLE] = 0x0
PWM_DUTY[DCYCLE] = 0x6
PWM_CTRL[PRESCALE] = 0x0
The output waveform in Figure 4-4 is created by writing PWM_PERVALn[PV] with a decimal
value of 10 (11 clocks) and PWM_DUTYn[DCYCLE] with 6. Figure 4-4 also shows that
PWM_CTRLn[PRESCALE] is configured with a value of 0x0 loaded, which results in the
PSCLK_PWMn having the same frequency as the 3.6864 MHz input clock.
Flow-through data passes through the DMAC before the data is latched by the destination in its
buffers/memory. This DMAC can perform memory-to-memory moves with flow-through transfers.
Figure 5-1 provides an overview of the DMAC. Table 5-1 provides a list of the DMAC signals and
descriptions.
Figure 5-1. DMAC Block Diagram
Memory Controller
DMA Controller
Control Registers
16 DMA Channels
Channel 15
DREQ[1:0]
DCSR0
(external) Channel 0
DDADR0
DSADR0 DMA_IRQ
DRCMR0 (internal)
DTADR0
PREQ[37:0] DCMD0
(internal) DINT
Peripheral Bus
(internal)
Channel information must be maintained on a per-channel basis and is contained in the DMAC
registers see in Table 5-13. The DMAC supports two methods of loading the DMAC register, No-
Descriptor and Descriptor Fetch Modes. The fetch modes are discussed in further detail in
Section 5.1.4.
Software must ensure cache coherency when it configures the DMA channels. The DMAC does
not check the cache so target and source addresses must be configured as non-cacheable in the
Memory Management Unit.
Each demand for data that a peripheral generates results in a read or write to memory data. A
peripheral must not request a DMA transfer unless it is prepared to read or write the full data block
(8, 16, or 32 bytes) and it is equipped to handle reads and writes less than a full data block. Reads
and writes less than a full data block can occur at the end of a DMA transfer.
must remain deasserted for at least four MEMCLKs. The DMAC registers the transition from 0 to
1 to identify a new request. The external companion chip must not assert another DREQ until the
previous DMA data transfer starts.
Figure 5-2. DREQ timing requirements
dreq_assert_min dreq_deassert_min
mem_clk
DREQ
The PREQ[37:0] bits are the active high internal signals from the on-chip peripherals. Unlike
DREQ[1:0], they are level sensitive. The DMAC does not sample the PREQ[37:0] signals until it
completely finishes the current data transfer. For a write request to the on-chip peripheral, the
DMAC begins to sample the PREQ[37:0] signals after it sends the last byte of the write request.
For a read request, the DMAC begins to sample the PREQ[37:0] signals after it sends the last byte
that pertains to the read on the internal bus.
The DCSR[REQPEND] bit indicates the status of the pending request for the channel.
If a DREQx assertion sets the DCSR[REQPEND] bit and software resets the DCSR[RUN] bit to
stop the channel, the DCSR[REQPEND] bit and the internal registers that hold the DREQx
assertion information may remain set even though the channel has stopped. To reset the
DCSR[REQPEND] bit, software must send a dummy descriptor that transfers some data.
When DMA interrupt occurs, it is visible in Pending Interrupt Register Bit 25 (see Section 4.2.2.5,
“Interrupt Controller Pending Register (ICPR)” on page 4-25). When a pending interrupt becomes
active, it is sent to the CPU if its corresponding ICMR mask Bit 25 (see Section 4.2.2.1, “Interrupt
Controller Mask Register (ICMR)” on page 4-22) is set to a one.
If two or more channels are active and request a DMA, the priority scheme in Table 5-2 applies.
Request priority does not affect requests that have already started. The DMAC priority scheme is
considered when the smaller dimension of the DCMDx[SIZE] or DCMDx[LENGTH] is complete.
If all channels request data transfers, the Sets are prioritized in following order:
• Set zero
• Set one
• Set zero
• Set two
• Set zero
• Set one
• Set zero
• Set three
The pattern repeats for the next eight channel services. In each set, the channels are given round-
robin priority.
Table 5-2. Channel Priority (if all channels are running concurrently)
Set Channels Priority Number of times served
The state machine used to determine the priority of the DMA channels is shown in Table 5-3. Use
this table to determine the exact sequence the DMA controller gives to each channel when not all
channels are running concurrently.
The channels get a round-robin priority in each set. Out of reset, the state machine state is zero. If a
channel in set zero has a pending request, that channel is serviced. If a channel in set one has a
pending request, that channel is serviced and so on. Once a request is serviced, the state machine
state is incremented, wrapping around from state machine state seven back to state machine state
zero. If there is no pending request, the state machine stays in the current state machine state until
there is a pending request. See Table 5-4 for priority scheme examples.
The Descriptor Fetch and No-Descriptor modes can be used simultaneously on different channels.
This means that some DMA channels can be active in one mode while other channels are active in
the other mode.
A channel must be stopped before it can be switched from one mode to the other.
If an error occurs in a channel, it returns to its stopped state and remains there until software clears
the error condition and writes a 1 to the DCSR[RUN] register.
Ensure that the software does not program the channel’s DDADx No-Descriptor Fetch Mode.
7. The channel waits for the next request or continues with the data transfer until the
DCMD[LENGTH] reaches zero.
8. The DDADR[STOP] is set to a 1 and the channel stops.
DCSR[RUN]=0, RUN=0
DCSR[NODESCFETCH]=1,
DSADR,DTADR,
DCMD programmed Valid
Uninitialized descriptor Channel
not running Error
RUN=1
No
descriptor
DDADR[STOP] = 0
DCMD[FLOWSRC] xor fetch
DCMD[FLOWTRG] = 1 (running) RUN=0
DCMD[FLOWSRC] &
DCMD[FLOWTRG] = 0
DCMD[FLOWSRC] xor
Wait DCMD[FLOWTRG] = 1
for Transferring
request Data
Request Asserted
DCMD[LENGTH]≠ 0
DDADR[STOP] = 1 DDADR[STOP] = 1 & DCMD[FLOWSRC] = 0
& DCMD[FLOWTRG] = 0
Stopped
a. Word [0] -> DDADRx register and a single flag bit. Points to the next four-word
descriptor.
b. Word [1] -> DSADRx register for the current transfer.
c. Word [2] -> DTADRx register for the current transfer.
d. Word [3] -> DCMDx register for the current transfer.
6. The channel waits for the request or starts the data transfer, as determined by the
DCMD[FLOW] source and target bits.
7. The channel transmits a number of bytes equal to the smaller of DCMD[SIZE] and
DCMD[LENGTH].
8. The channel waits for the next request or continues with the data transfer until the
DCMD[LENGTH] reaches zero.
9. The channel stops or continues with a new descriptor fetch from the memory, as determined by
the DDADR[STOP] bit.
Bit [0] (STOP) of Word [0] in a DMA descriptor (the low bit of the DDADRx field) marks the
descriptor at the end of a descriptor list. The value of the STOP bit does not affect the manner in
which the channel’s registers load the descriptor’s fields. If a descriptor with its STOP bit set is
loaded into a channel's registers, the channel stops after it completely transfers the data that
pertains to that descriptor. Figure 5-4 summarizes this operation.
Software must set the DCSR[RUN] bit to 1 after it loads the DDADR. The channel descriptor fetch
does not take place unless the DDADR register is loaded and the DCSR[RUN] bit is set to a 1.
The DMAC priority scheme does not affect DMA descriptor fetches. The next descriptor is fetched
immediately after the previous descriptor is serviced.
RUN=1
Descriptor DDADR[STOP] = 0
DCMD[FLOWSRC] xor fetch
(running)
DCMD[FLOWTRG] = 1
DCMD[FLOWSRC] &
DCMD[FLOWTRG] = 0
DCMD[FLOWSRC] xor
Wait DCMD[FLOWTRG] = 1
for Transferring
request Data
Request Asserted
DCMD[LENGTH]≠ 0
DDADR[STOP] = 1 DDADR[STOP] = 1 & DCMD[FLOWSRC] = 0
& DCMD[FLOWTRG] = 0
Stopped
• Wait for Request: Channel is waiting for a request before it starts to transfer the data.
• Transfer Data: Channel is transferring data.
• Channel Error: Channel has an error. It remains in the stopped state until software clears the
error condition, re-initializes the channel, and writes a 1 to the DCSR[RUN] bit. See
Section 5.3.1 and Section 5.3.2 for details.
• Stopped: Channel is stopped.
Figure 5-3 and Figure 5-4 show the progression from state to state.
The DMAC ensures that all memory references made by a single DMA data stream are presented
to main memory in the order in which they were made. The descriptor fetches occurs between the
data blocks. This allows self-modifying DMA descriptor chains to function correctly (see Example
4 on page 5-27). It also allows schemes in which a DMA stream writes data blocks followed by
status blocks and schemes in which another DMA stream (probably from the processor) polls the
same field in the status block.
The DMAC ensures that data is not retained in per-channel buffers between descriptors. When a
descriptor is completely processed, any read data that is buffered in the channel is discarded and
any write data that is buffered in the channel is sent to memory (although it may not be there yet).
The DMA interrupt is not posted until the descriptor is completely processed.
Figure 5-5 shows the order which data is transferred as determined by the DCMD[ENDIAN] and
DCMD[SIZE] bits.
If data is being transferred from an internal device to memory, DCMD[ENDIAN] is set to a 0, and
DCMD[SIZE] is set to a 1, the memory receives the data in the following order:
1. Byte[0]
2. Byte[1]
3. Byte[2]
4. Byte[3]
DMAC
3 0
2 1
1 0 3 2
3 2 1 0 1 2
3 2 1 0
0 3
• Internal Peripheral to Memory Transfers: Most peripherals do not send a request for trailing
bytes for on-chip peripheral to memory transfers. Refer to the appropriate section in this
document for details of a peripheral’s operation. If the peripheral sends out a request, the DMA
transfers the number of bytes equal to the smaller of DCMD[LENGTH] or DCMD[SIZE]. If
software must us programmed I/O to handle the trailing bytes, it must follow this sequence of
operation:
1. Writing a 0 to the DCSR[RUN] bit to stop the DMA channel.
2. Wait until the channel to stops.
3. Make reads to the channel’s registers to check the channel’s status.
4. Perform the programmed I/O transfers to the peripheral.
5. Set the DCSR[RUN] bit to a 1 and reset the DMA channel for future data transfers.
Main memory includes any memory that the processor supports, except writes to flash. Writes to
flash are not supported and cause a bus error.
In flow-through transfer mode, data passes through the DMAC before it is latched by the
destination in its buffers/memory. The DMAC can also perform memory-to-memory moves in
flow-through transfer mode.
If the internal peripheral address is in the DSADR, the DCMDx[FLOWSRC] bit must be set to a 1.
This allows the processor to wait for the request before it initiates the transfer. If the internal
peripheral address is in the DTADR, the DCMDx[FLOWTRG] bit must be set to a 1.
If DCMDx[IRQEN] is set to a 1, a DMA interrupt is requested at the end of the last cycle
associated with the byte that caused DCMDx[LENGTH] to decrement to 0.
For a flow-through DMA read to an internal peripheral, use the following settings for the DMAC
register bits:
• DSADR[SRCADDR] = external memory address
• DTADR[TRGADDR] = internal peripheral’s address
• DCMD[INCSRCADDR] = 1
• DCMD[FLOWSRC] = 0
• DCMD[FLOWTRG] = 1
For a flow-through DMA write to an internal peripheral, use the following settings for the DMAC
register bits:
• DSADR[SRCADDR] = internal peripheral address
• DTADR[TRGADDR] = external memory address
• DCMD[INCTRGADDR] = 1
• DCMD[FLOWSRC] = 1
• DCMD[FLOWTRG] = 0
endpoint 1
0x4060_0100 1 01 32 Target 0x4000_0164
transmit
endpoint 2
0x4060_0180 1 01 32 Source 0x4000_0168
receive
endpoint 3
0x4060_0200 1 01 32 Target 0x4000_016C
transmit
endpoint 4
0x4060_0400 1 01 32 Source 0x4000_0170
receive
endpoint 6
0x4060_0600 1 01 32 Target 0x4000_0178
transmit
endpoint 7
0x4060_0680 1 01 32 Source 0x4000_017C
receive
USB
endpoint 8
0x4060_0700 1 01 32 Target 0x4000_0180
transmit
endpoint 9
0x4060_0900 1 01 32 Source 0x4000_0184
receive
endpoint 11
0x4060_0B00 1 01 32 Target 0x4000_018C
transmit
endpoint 12
0x4060_0B80 1 01 32 Source 0x4000_0190
receive
endpoint 13
0x4060_0C00 1 01 32 Target 0x4000_0194
transmit
endpoint 14
0x4060_0E00 1 01 32 Source 0x4000_0198
receive
If DCMDx[IRQEN] is set to a 1, a DMA interrupt can be requested at the end of the last cycle
associated with the byte that caused DCMDx[LENGTH] to decrease from a 1 to a 0.
Note: The process shown for a flow-through DMA read to an external peripheral indicates that the
external address increases. Some external peripherals, such as FIFOs, do not require an increment
in the external address.
For a flow-through DMA read to an external peripheral, use the following settings for the DMAC
register bits:
• DSADR[SRCADDR] = external memory address
• DTADR[TRGADDR] = companion chip’s address
• DCMD[INCSRCADDR] = 1
• DCMD[INCTRGADDR] = 0
• DCMD[FLOWSRC] = 0
• DCMD[FLOWTRG] = 1
Note: The process shown for a flow-through DMA write to an external peripheral indicates that the
external address increases. Some external peripherals, such as FIFOs, do not require an increment
in the external address.
For a flow-through DMA write to an external peripheral, use the following settings for the DMAC
register bits:
• DSADR[SRCADDR] = companion chip address
• DTADR[TRGADDR] = external memory address.
• DCMD[INCSRCADDR] = 0
• DCMD[INCTRGADDR] = 1
• DCMD[FLOWSRC] = 1
• DCMD[FLOWTRG] = 0
If DCMD[IRQEN] is set to a 1, a DMA interrupt is requested at the end of the last cycle associated
with the byte that caused DCMDx[LENGTH] to decrease from 1 to 0.
Note: The process shown for a memory-to-memory transfer indicates that the external address increases.
Some external peripherals, such as FIFOs, do not require an increment in the external address.
For a memory-to-memory read or write, use these settings for the DMAC registers:
• DSADR[SRCADDR] = external memory address
• DTADR[TRGADDR] = external memory address
• DCMD[INCSRCADDR] = 1
• DCMD[INCTRGADDR] = 1
• DCMD[FLOWSRC] = 0
• DCMD[FLOWTRG] = 0
• DCSR[RUN] =1
Software must set the corresponding DCSR register error bit to reset the interrupt.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ChlIntr15
ChlIntr14
ChlIntr13
ChlIntr12
ChlIntr10
ChlIntr11
ChlIntr9
ChlIntr8
ChlIntr7
ChlIntr6
ChlIntr5
ChlIntr4
ChlIntr3
ChlIntr2
ChlIntr1
ChlIntr0
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31:16 — reserved
Channel ‘x’ Interrupt (read-only).
15:0 CHLINTRx 0 – No interrupt
1 – Interrupt
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NODESCFETCH
BUSERRINTR
STOPIRQEN
STOPSTATE
STARTINTR
REQPEND
ENDINTR
RUN
reserved reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NODESCFETCH
BUSERRINTR
STOPIRQEN
STOPSTATE
STARTINTR
REQPEND
ENDINTR
RUN
reserved reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAPVLD
reserved
reserved CHLNUM
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31:8 — reserved
Map Valid (read / write).
0 – Request is unmapped
1 – Request is mapped to a channel indicated by DRCMRx[3:0]
7 MAPVLD
Determines whether the request is mapped to a channel or not. If the bit is set to a 1, the
request is mapped to a channel indicated in DRCMRx[3:0]. If the bit is 0, the request is
unmapped. This bit can also be used to mask the request.
6:4 — reserved
Channel Number (read / write).
Indicates the channel number if DRCMR[MAPVLD] is set to a 1.
3:0 CHLNUM
Do not map two active requests to the same channel. It produces unpredictable results.
Refer to Section 5.1.3 to review the channel priority scheme.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STOP
DESCRIPTOR ADDRESS reserved
Reset Uninitialized 0
DESCRIPTOR
31:4 Address of next descriptor (read / write).
ADDRESS
3:1 — reserved
Stop (read / write).
0 – Run channel.
1 – Stop channel after completely processing this descriptor and before fetching the next
0 STOP descriptor, i.e., DCMD[LENGTH]= 0.
If this bit is set, the channel to stops after it completely processes the descriptor and before
it fetches the next descriptor. If the DDADRx[STOP] bit is 0, a new descriptor fetch based
on the DDADR starts when the current descriptor is completely processed.
DSADRx contains the Source Address for the current descriptor of a specific channel. The Source
Address is the address of the internal peripheral or a memory location. On power up, the bits in this
register are undefined. If the Source Address is the address of a companion chip or external
peripheral, the source address must be aligned to an 8-byte boundary. This allows bits [2:0] of the
address to be reserved. If the source address is the address for an internal peripheral, the address
must be 32-bit aligned, so bits [1:0] are reserved. DSADR cannot contain the address of any other
internal DMA, LCD, or MEMC registers.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
SOURCE ADDRESS
Reset Uninitialized
These registers contain the target address for the current descriptor in a channel. The target address
is the address of an internal peripheral or a memory location. On power up, the bits in this register
are undefined. If the target address is the address of a companion chip or external peripheral, the
target address must be aligned to an 8-byte boundary. This allows bits [2:0] of the address to be
reserved. If the target address is the address for an internal peripheral, the address must be 32-bit
aligned so that bits [1:0] are reserved. DTADRx must not contain the address of any other internal
DMA, LCD, or MEMC register.
The DTADRx must not contain a flash address because writes to flash from the DMAC are not
supported.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
TARGET ADDRESS
Reset Uninitialized
These registers contain the channel’s control bits and the length of the current transfer in that
channel. On power up, the bits in this register are set to 0.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INCSRCADDR
INCTRGADDR
STARTIRQEN
ENDIRQEN
FLOWSRC
FLOWTRG
reserved
reserved
ENDIAN
WIDTH
SIZE
reserved LENGTH
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INCSRCADDR
INCTRGADDR
STARTIRQEN
ENDIRQEN
FLOWSRC
FLOWTRG
reserved
reserved
ENDIAN
WIDTH
SIZE
reserved LENGTH
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
5.4 Examples
This section contains examples that show how to:
• Set up and start a channel
• Initialize a descriptor list for a channel that is running
• Add a descriptor to the end of a descriptor list for a channel that is running
• Initialize a channel that is going to be used by a direct DMA master
The following example shows how to set up a channel to transfer LENGTH words from the address
DSADR to the I/O address DTADR. The example also shows how to start the transfer. The
example sets the stop bit in the DDADR, so the DMA channel stops after it completely transfers
LENGTH bytes of data.
The channel starts, loads the descriptor in its registers, and stops because the transfer length is 0
and the STOP bit is set. No data is transferred in this example. The channel can be restarted by
writing to its DDADR and writing a 1 to the DCSR[RUN] bit.
Example 3. How to add a descriptor to the end of a descriptor list for a channel that is
running:
The example in this section assumes that the Descriptor Fetch Mode is active.
DMA descriptor lists are used as queues of full buffers for network transmitters and as queues of
empty buffers for network receivers. Because the buffers in a queue are often small (in particular,
as small as an ATM cell), on-the-fly DMA descriptor lists manipulation must be efficient.
1. Write a 0 to DCSR[RUN].
2. Wait until the channel stops. The channel stop state is reflected in the DCSR:STOPSTATE bit.
3. In memory, create the descriptor to be added and set its stop bit to a 1.
4. In the memory, manipulate the DDADR of the current chain’s last descriptor such that its
DDADR points to the descriptor created in Step 3.
5. In the memory, create a new descriptor that has the same DDADR, DSADR, DTADR, and
CMD as those of the stopped DMA channel. The new descriptor is the next descriptor for the
list.
6. Examine the DMA channel registers and determine if the channel stopped in the chain’s last
descriptor of the chain. If it did, manipulate the DDADR of the last descriptor in the memory
so that its DDADR points to the descriptor created in Step 3. Otherwise, continue to Step 7.
7. Program the channel’s DDADR with the descriptor created in Step 5.
8. Set the DCSR[RUN] to a 1.
Example 4. How to initialize a channel that is going to be used by a direct DMA master:
The most efficient way to move data between an I/O device and main memory is the processor’s
descriptor-based DMA system. Each application has different requirements, so a descriptor-based
DMA may be best for some applications while a non-descriptor-based DMA is best for others. For
applications that can not tolerate the time needed to fetch a descriptor before each DMA transfer,
choose the non descriptor-based DMA method. For applications that can tolerate it, a descriptor-
based DMA method can reduce the amount of core intervention.
Self–Modifying Descriptors: The descriptor-based DMA system can be used to provide true direct
memory access to devices that require it.
An external device with these requirements can use a constant descriptor in memory.
struct {longddadr;
longdsadr;
longdtadr;
shortlength;
shortdcmd;
} desc[2];
desc[0].ddadr = &desc[1]
desc[0].dsadr = I_ADR + I_DESC_OFFS
desc[0].dtadr = &desc[1].dsadr
desc[0].length = 8;
desc[0].dcmd = CMD_IncTrgAdr | CMD_FlowThru;
desc[1].ddadr = &desc[0]
desc[1].dtadr = I_ADR + I_DATA_OFFS
desc[1].dsadr = 0
desc[1].length = 0
desc[1].dcmd = 0
When the external device has data to transfer, it makes a DMA request in the standard way. The
DMAC wakes up and reads four words from the device’s I_DESC_OFFS address (the DMAC only
transfers four words because the first descriptor has an 8-byte count.). The four words from the
external device are written in the DSADR, DTADR, and DCMD fields of the next descriptor. The
DMAC then steps into the next (dynamically modified) descriptor and, using the I_DATA_OFFS
address on the external device, starts the transfer that the external device requested. When the
transfer is finished, the DMAC steps back into the first descriptor and the process is repeated.
This example lends itself to any number of variations. For example, a DMA channel that is
programmed in this way can be used to transfer messages from a network device directly into client
buffers. Each block of data would be preceded by its final destination address and a count.
6.1 Overview
The processor external memory bus interface supports Synchronous Dynamic Memory (SDRAM),
synchronous and asynchronous burst modes, Page-mode flash, Synchronous Mask ROM
(SMROM), Page Mode ROM, SRAM, SRAM-like Variable Latency I/O (VLIO), 16-bit PC Card
expansion memory, and Compact Flash. Memory types can be programmed through the Memory
Interface Configuration registers. Figure 6-1 is a block diagram of the maximum configuration of
the memory controller.
nSDCS<0>
SDRAM Partition 0
nSDCS<1>
SDCLK<1>, SDCKE<1> SDRAM Partition 1
SDRAM Memory Interface
nSDCS<2> Up to 4 partitions of SDRAM
memory (16- or 32-bit wide)
SDRAM Partition 2
nSDCS<3>
SDCLK<2>, SDCKE<1> SDRAM Partition 3
DQM[3:0] MA[24:10]
nSDRAS, nSDCAS
MD[31:0] MD[15:0]
Buffers and 16-bit PC Card Memory Interface
Transceivers Up to 2-socket support.
MA[25:0] Requires some
Memory external buffering
Controller
Interface Card Control
nCS<0>
Static Memory or
Static Bank 0 Variable Latency I/O Interface
Up to 6 banks of ROM, Flash,
nCS<1> SRAM, Variable Latency I/O,
Static Bank 1 (16 or 32-bit wide)
NOTE:
nCS<2> Static Bank 0 must be populated by
SDCLK<0>, SDCKE<0> Static Bank 2 “bootable” memory
SDRAM has four partitions, Static Memory has six, and Card space has two. When memory access
attempts to burst across the boundary between adjacent partitions, ensure that the configurations
for the partitions are identical. The configurations must be identical in every aspect, including
external bus width and burst length.
partition pairs: the 0/1 pair and the 2/3 pair. The partitions in a pair must be identical in size and
configuration. The two pairs may be different (for example, the 0/1 pair can be 100 MHz SDRAM
on a 32-bit data bus, while the 2/3 pair can be 50 MHz SDRAM on a 16-bit data bus).
The processor performs auto-refresh (CBR) during normal operation, and supports self-refreshing
SDRAM during Sleep mode. An SDRAM auto-power-down mode bit can be set so that the clock
and clock enable to SDRAM are automatically de-asserted whenever none of the corresponding
partitions is being accessed.
Upon enabling an SDRAM partition, a mode register set command (MRS), see Section 6.5.6, is
sent to the SDRAM devices by writing to the MDMRS register. The PXA255 processor adds
support for low-power SDRAM by giving software access to the Extended Mode Register via the
MDMRSLP register.
MRS commands always configure SDRAM internal mode registers for sequential burst type and a
burst length of four.
The Variable Latency I/O interface differs from SRAM in that it allows the data-ready input signal,
RDY, to insert a variable number of wait states. For all static memory types, each chip select can be
individually configured to a 16-bit or 32-bit-wide data bus. nOE is asserted on all reads, nPWE is
asserted on writes to Variable Latency I/O devices, and nWE is asserted on writes to all other static
devices, both synchronous and asynchronous. For SRAM and variable latency I/O, DQM[3:0] are
byte selects for both reads and writes.
When the processor comes out of reset, it starts fetches and executes instructions at address 0x00,
which corresponds to memory selected by nCS<0>. The boot ROM must be located at this address.
The BOOT_SEL pins determine the type of boot memory (refer to Section 6.10.1).
The processor 16-bit PC Card / Compact Flash Controller provides the following signals.
• nPREG is muxed with MA[26] and selects register space (I/O or attribute) versus memory
space
• nPOE and nPWE allow memory and attribute reads and writes
• nPIOR, nPIOW, and nIOIS16 control I/O reads and writes
• nPWAIT allows extended access times
• nPCE2 and nPCE1 are byte select high and low for a 16-bit data bus
• PSKTSEL selects between two card sockets
nSDCS(2:0)
nSDRAS, nSDCAS, nWE, CKE(1)
SDCLK(2:1)
MA(23:10)
MD(31:0)
DQM(3:0)
Figure 6-3 shows an alternate memory configuration. This system uses 2M x 16 SMROM devices
in static banks 0 and 1, and RAM devices in static bank 2.
Figure 6-3. Static Memory System Example
nCS(2:0)
MD(31:0)
nOE
DQM[3:0]
2 2 2
DQML DQML DQML
3 3 3
DQMH DQMH DQMH
31:16 31:16 31:16
DQ(15:0) DQ(15:0) DQ(15:0)
Table 6-1 lists all the transactions that the processor can generate. No burst can cross an aligned 32-
byte boundary. On a 16-bit data bus, each full word access becomes a two half-word burst, with
address bit 1 set to a 0. Each write access to Flash memory space must take place in one non-burst
operation, regardless of the bus size.
For writes to SDRAM, SRAM, or Variable Latency I/O memory spaces, the DQM[3:0] lines
enable the corresponding byte of the data bus. Flash memory space stores must be exactly the
width of the Flash data bus, either 16- or 32-bits. See Section 6.7.6 for more information.
For reads to all memory types, the DQM[3:0] lines are deasserted (set low so data is not masked).
Hardware does not detect reads and writes from or to enabled and nonexistent memory. If memory
in an enabled partition is not present, a read returns indeterminate data.
If memory does not occupy all 64 MB of the partition, reads and writes from or to the unoccupied
portion are processed as if the memory occupies the entire 64 MB of the memory partition.
A single word (or half-word if the data bus width is defined as 16-bits) access to a disabled
SDRAM partition (MDCNFG:DEx=0) causes a CBR refresh cycle to all four partitions. This
technique is used in the hardware initialization procedure. Read return data is indeterminate and
writes are not executed on the external memory bus.
A burst read access to a disabled SDRAM partition results in a target-abort exception. Target aborts
are also generated for burst writes to Flash/ROM space and bursts to configuration space.
Attempted single beat writes to ROM are not aborted. Bursts to configuration space also result in
target aborts. Target aborts can be either Data or Prefetch abort depending on the source of the
attempted burst transaction.
The signals used to control the SDRAM memory are listed in Section 6.2.1.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSA1111_2
DSA1111_0
DLATCH2
DLATCH0
DADDR2
DADDR0
DRAC2
DCAC2
DRAC0
DCAC0
DWID2
DWID0
DNB2
DNB0
DE3
DE2
DE1
DE0
reserved DTC2 reserved DTC0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSA1111_2
DSA1111_0
DLATCH2
DLATCH0
DADDR2
DADDR0
DRAC2
DCAC2
DRAC0
DCAC0
DWID2
DWID0
DNB2
DNB0
DE3
DE2
DE1
DE0
reserved DTC2 reserved DTC0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSA1111_2
DSA1111_0
DLATCH2
DLATCH0
DADDR2
DADDR0
DRAC2
DCAC2
DRAC0
DCAC0
DWID2
DWID0
DNB2
DNB0
DE3
DE2
DE1
DE0
reserved DTC2 reserved DTC0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
All values in the MDCNFG register must be programmed correctly to ensure proper operation of
the device.
The MDMRS[MDBLx] bits configure the SDRAM to a burst length of four. This value is fixed and
cannot be changed. For transfer cycles that require more data than the set burst length of four, the
controller can preform as many bursts as necessary to transfer the required amount of data. For
example, during a cache line fill the controller can perform a four-beat burst followed immediately
by another four-beat burst. This approach requires the controller to generate the first address for the
second burst. During transfer cycles less than four beats, the controller ignores the data it does not
need. For instance, if the SDRAM is configured as non-cacheable, single beat reads are seen on the
bus as a four-beat read with only one beat that is used by the processor. This also applies to a
single-beat write.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDADD2
MDADD0
reserved
reserved
MDBL2
Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0
31 — reserved
SDRAM partition pair 2 CAS Latency - derived from MDCNFG:DTC2. Writes are ignored.
22:20 MDCL2
Ready-only.
SDRAM partition pair 2 Burst Type. Fix to sequential addressing. Writes are ignored.
19 MDADD2
Always reads 0.
SDRAM partition pair 2 burst length. Fixed to a burst length of four. Writes are ignored.
18:16 MDBL2
Always reads 010.
15 — reserved
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDADD2
MDADD0
reserved
reserved
MDBL2
MDMRS2 MDCL2 MDMRS0 MDCL0 MDBL0
Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0
SDRAM partition pair 0 CAS Latency - derived from MDCNFG:DTC0. Writes are ignored.
6:4 MDCL0
This field is ready-only.
SDRAM partition pair 0 Burst Type. Fix to sequential addressing. Writes are ignored.
3 MDADD0
Always reads 0.
SDRAM partition pair 0 burst length. Fixed to a burst length of four. Writes are ignored.
2:0 MDBL0
Always reads 010.
This register is not used with in the processor except to write the value during the MRS command.
All values in the MDCNFG register must be programmed correctly to ensure proper operation of
the SDRAM. The register is used by a low-power SDRAM to control the Partial Array Self-
Refresh (PASR) and Temperature Compensated Self-Refresh (TCSR) settings.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDMRSLP2
MDMRSLP0
MDLPEN2
MDLPEN0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ENABLE BIT FOR LOW POWER MRS VALUE FOR PARTITION PAIR 2/3:
31 MDLPEN2 0 – Disable low power MRS for Partition Pair 2/3
1 – Enable low power MRS for Partition Pair 2/3
LOW POWER MRS VALUE TO BE WRITTEN TO SDRAM FOR
30:16 MDMRSLP2
PARTITION PAIR 2/3
Enable bit for low power MRS value for Partition Pair 0/1.
15 MDLPEN0 0 – Disable low power MRS for Partition Pair 0/1
1 – Enable low power MRS for Partition Pair 0/1
LOW POWER MRS VALUE TO BE WRITTEN TO SDRAM FOR
14:0 MDMRSLP0
PARTITION PAIR 0/1
The clock-run bits (K0RUN, K1RUN, and K2RUN) and clock-enable bits (E0PIN and E1PIN)
provide software control of SDRAM and Synchronous Static Memory low-power modes. When
the clock-run bits and clock-enable bits are cleared, the corresponding memory is inaccessible.
Automatic power-down, enabled by the APD bit, is an mechanism for minimizing power
consumption in the processor SDCLK pin drivers and/or the SDRAM/Synchronous Static Memory
devices. A latency penalty of one memory cycle is incurred when SDCLK and SDCKE are
restarted between non-consecutive SDRAM/Synchronous Static Memory transfers.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
SLFRSH
K2FREE
K1FREE
K0FREE
K2RUN
K1RUN
K0RUN
K2DB2
K1DB2
K0DB2
E1PIN
E0PIN
APD
reserved DRI
Reset 0 0 0 0 0 0 1 1 1 1 0 0 1 0 1 0 0 1 * * 1 1 1 1 1 1 1 1 1 1 1 1
31:26 — reserved
SDRAM Free-Running Control
0 – SDCLK2 is not free-running
25 K2FREE 1 – SDCLK2 is free-running (ignores MDREFR[APD] or MDREFR[K2RUN] bits)
Provides synchronous memory with SDCLK2 following a reset in order to reset internal
circuitry.
SDRAM Free-Running Control
0 – SDCLK1 is not free-running
24 K1FREE
1 – SDCLK1 is free-running (ignores MDREFR[APD] or MDREFR[K1RUN] bits)
Provides synchronous memory with SDCLK1 following a reset to reset internal circuitry.
SDRAM Free-Running Control
0 – SDCLK0 is not free-running
23 K0FREE
1 – SDCLK0 is free-running (ignores MDREFR[APD] or MDREFR[K0RUN] bits)
Provides synchronous memory with SDCLK0 following a reset to reset internal circuitry.
SDRAM Self-Refresh Control/Status
Control/status bit for entering and exiting SDRAM self-refresh and is automatically set on a
hardware or sleep reset.
0 – Self refresh disabled
1 – Self refresh enabled
22 SLFRSH SLFRSH can be set by software to force a self-refresh command. E1PIN does not have to
be cleared. The appropriate clock run bits (K1RUN and/or K2RUN) must remain set until
SDRAM has entered self-refresh and must be set prior to exiting self-refresh (clearing
SLFRSH). This capability must be used with extreme caution because the resulting state
prohibits automatic transitions for any commands.
Clearing SLFRSH is a part of the hardware or sleep reset procedure for SDRAM.
21 — reserved
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
SLFRSH
K2FREE
K1FREE
K0FREE
K2RUN
K1RUN
K0RUN
K2DB2
K1DB2
K0DB2
E1PIN
E0PIN
APD
reserved DRI
Reset 0 0 0 0 0 0 1 1 1 1 0 0 1 0 1 0 0 1 * * 1 1 1 1 1 1 1 1 1 1 1 1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
SLFRSH
K2FREE
K1FREE
K0FREE
K2RUN
K1RUN
K0RUN
K2DB2
K1DB2
K0DB2
E1PIN
E0PIN
APD
reserved DRI
Reset 0 0 0 0 0 0 1 1 1 1 0 0 1 0 1 0 0 1 * * 1 1 1 1 1 1 1 1 1 1 1 1
Figure 6-4 shows the bank/row/column address multiplexing using a 2x13x9 32-bit SDRAM as an
example for the normal bank-addressing scheme. All unused address bits during RAS and CAS
time - including MA[9:0] bits not shown here - are not guaranteed, and will be either driven to zero
or one.
Refer to Table 6-7 through Table 6-9 for a listing of address mapping options.
Table 6-4 shows how the SDRAM row and column addresses are mapped to the internal SDRAM
address. The SDRAM row and column addresses are muxed. The SDRAM row is sent during an
Active command and is followed by the column address during the read or write command.
MA<20> is driven with 0 during column addressing. BA[1:0] is used to tell the SDRAM which
bank is being read from and remains stable during column addressing. During SDRAM
configuration, all the address pins are used to transfer the MRS command.
Figure 6-4. External to Internal Address Mapping Options
Table 6-7. External to Internal Address Mapping for Normal Bank Addressing (Sheet 1 of 3)
# Bits External Address pins at SDRAM RAS Time External Address pins at SDRAM CAS Time
MA<24:10> MA<24:10>
Bank x
Row x
Col x 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Data
1x11x8x32 21 20 19 18 17 16 15 14 13 12 11 10 21 ‘0’ 9 8 7 6 5 4 3 2
1x11x8x16 20 19 18 17 16 15 14 13 12 11 10 9 20 ‘0’ 8 7 6 5 4 3 2 1
1x11x9x32 22 21 20 19 18 17 16 15 14 13 12 11 22 ‘0’ 10 9 8 7 6 5 4 3 2
1x11x9x16 21 20 19 18 17 16 15 14 13 12 11 10 21 ‘0’ 9 8 7 6 5 4 3 2 1
1x11x10x32 23 22 21 20 19 18 17 16 15 14 13 12 23 ‘0’ 11 10 9 8 7 6 5 4 3 2
1x11x10x16 22 21 20 19 18 17 16 15 14 13 12 11 22 ‘0’ 10 9 8 7 6 5 4 3 2 1
1x11x11x32 NOT VALID (illegal addressing combination) NOT VALID (illegal addressing combination)
1x11x11x16 NOT VALID (illegal addressing combination) NOT VALID (illegal addressing combination)
1x12x8x32 22 21 20 19 18 17 16 15 14 13 12 11 10 22 ‘0’ 9 8 7 6 5 4 3 2
1x12x8x16 21 20 19 18 17 16 15 14 13 12 11 10 9 21 ‘0’ 8 7 6 5 4 3 2 1
1x12x9x32 23 22 21 20 19 18 17 16 15 14 13 12 11 23 ‘0’ 10 9 8 7 6 5 4 3 2
1x12x9x16 22 21 20 19 18 17 16 15 14 13 12 11 10 22 ‘0’ 9 8 7 6 5 4 3 2 1
1x12x10x32 24 23 22 21 20 19 18 17 16 15 14 13 12 24 ‘0’ 11 10 9 8 7 6 5 4 3 2
Table 6-7. External to Internal Address Mapping for Normal Bank Addressing (Sheet 2 of 3)
# Bits External Address pins at SDRAM RAS Time External Address pins at SDRAM CAS Time
MA<24:10> MA<24:10>
Bank x
Row x
Col x 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Data
1x12x10x16 23 22 21 20 19 18 17 16 15 14 13 12 11 23 ‘0’ 10 9 8 7 6 5 4 3 2 1
1x12x11x32 25 24 23 22 21 20 19 18 17 16 15 14 13 25 12 ‘0’ 11 10 9 8 7 6 5 4 3 2
1x12x11x16 24 23 22 21 20 19 18 17 16 15 14 13 12 24 11 ‘0’ 10 9 8 7 6 5 4 3 2 1
1x13x8x32 23 22 21 20 19 18 17 16 15 14 13 12 11 10 23 ‘0’ 9 8 7 6 5 4 3 2
1x13x8x16 22 21 20 19 18 17 16 15 14 13 12 11 10 9 22 ‘0’ 8 7 6 5 4 3 2 1
1x13x9x32 24 23 22 21 20 19 18 17 16 15 14 13 12 11 24 ‘0’ 10 9 8 7 6 5 4 3 2
1x13x9x16 23 22 21 20 19 18 17 16 15 14 13 12 11 10 23 ‘0’ 9 8 7 6 5 4 3 2 1
1x13x10x32 25 24 23 22 21 20 19 18 17 16 15 14 13 12 25 ‘0’ 11 10 9 8 7 6 5 4 3 2
1x13x10x16 24 23 22 21 20 19 18 17 16 15 14 13 12 11 24 ‘0’ 10 9 8 7 6 5 4 3 2 1
1x13x11x32 13 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 ‘0’ 11 10 9 8 7 6 5 4 3 2
1x13x11x16 25 24 23 22 21 20 19 18 17 16 15 14 13 12 25 11 ‘0’ 10 9 8 7 6 5 4 3 2 1
2x11x8x32 22 21 20 19 18 17 16 15 14 13 12 11 10 22 21 ‘0’ 9 8 7 6 5 4 3 2
2x11x8x16 21 20 19 18 17 16 15 14 13 12 11 10 9 21 20 ‘0’ 8 7 6 5 4 3 2 1
2x11x9x32 23 22 21 20 19 18 17 16 15 14 13 12 11 23 22 ‘0’ 10 9 8 7 6 5 4 3 2
2x11x9x16 22 21 20 19 18 17 16 15 14 13 12 11 10 22 21 ‘0’ 9 8 7 6 5 4 3 2 1
2x11x10x32 24 23 22 21 20 19 18 17 16 15 14 13 12 24 23 ‘0’ 11 10 9 8 7 6 5 4 3 2
2x11x10x16 23 22 21 20 19 18 17 16 15 14 13 12 11 23 22 ‘0’ 10 9 8 7 6 5 4 3 2 1
2x11x11x32 NOT VALID (illegal addressing combination) NOT VALID (illegal addressing combination)
2x11x11x16 NOT VALID (illegal addressing combination) NOT VALID (illegal addressing combination)
2x12x8x32 23 22 21 20 19 18 17 16 15 14 13 12 11 10 23 22 ‘0’ 9 8 7 6 5 4 3 2
2x12x8x16 22 21 20 19 18 17 16 15 14 13 12 11 10 9 22 21 ‘0’ 8 7 6 5 4 3 2 1
2x12x9x32 24 23 22 21 20 19 18 17 16 15 14 13 12 11 24 23 ‘0’ 10 9 8 7 6 5 4 3 2
2x12x9x16 23 22 21 20 19 18 17 16 15 14 13 12 11 10 23 22 ‘0’ 9 8 7 6 5 4 3 2 1
2x12x10x32 25 24 23 22 21 20 19 18 17 16 15 14 13 12 25 24 ‘0’ 11 10 9 8 7 6 5 4 3 2
2x12x10x16 24 23 22 21 20 19 18 17 16 15 14 13 12 11 24 23 ‘0’ 10 9 8 7 6 5 4 3 2 1
2x12x11x32 26 25 24 23 22 21 20 19 18 17 16 15 14 13 26 25 12 ‘0’ 11 10 9 8 7 6 5 4 3 2
2x12x11x16 25 24 23 22 21 20 19 18 17 16 15 14 13 12 25 24 11 ‘0’ 10 9 8 7 6 5 4 3 2 1
Table 6-7. External to Internal Address Mapping for Normal Bank Addressing (Sheet 3 of 3)
# Bits External Address pins at SDRAM RAS Time External Address pins at SDRAM CAS Time
MA<24:10> MA<24:10>
Bank x
Row x
Col x 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Data
2x13x8x32 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 24 23 ‘0’ 9 8 7 6 5 4 3 2
2x13x8x16 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 23 22 ‘0’ 8 7 6 5 4 3 2 1
2x13x9x32 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 25 24 ‘0’ 10 9 8 7 6 5 4 3 2
2x13x9x16 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 24 23 ‘0’ 9 8 7 6 5 4 3 2 1
2x13x10x16 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 25 24 ‘0’ 10 9 8 7 6 5 4 3 2 1
Table 6-8. External to Internal Address Mapping for SA-1111 Addressing (Sheet 1 of 3)
# Bits External Address pins at SDRAM RAS Time External Address pins at SDRAM CAS Time
MA<24:10> MA<24:10>
Bank x
Row x
Col x 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Data
1x11x8x32 21 20 19 18 17 16 15 14 13 12 11 10 21 ‘0’ 9 8 7 6 5 4 3 2
1x11x8x16 NOT VALID (illegal addressing combination) NOT VALID (illegal addressing combination)
1x11x9x32 21 20 19 18 17 16 15 14 13 12 11 10 21 ‘0’ 22 9 8 7 6 5 4 3 2
1x11x9x16 21 20 19 18 17 16 15 14 13 12 11 10 21 ‘0’ 9 8 7 6 5 4 3 2 1
1x11x10x32 21 20 19 18 17 16 15 14 13 12 11 10 21 ‘0’ 23 22 9 8 7 6 5 4 3 2
1x11x10x16 21 20 19 18 17 16 15 14 13 12 11 10 21 ‘0’ 22 9 8 7 6 5 4 3 2 1
1x11x11x32 NOT VALID (illegal addressing combination) NOT VALID (illegal addressing combination)
1x11x11x16 NOT VALID (illegal addressing combination) NOT VALID (illegal addressing combination)
1x12x8x32 22 21 20 19 18 17 16 15 14 13 12 11 10 21 ‘0’ 9 8 7 6 5 4 3 2
1x12x8x16 NOT VALID (illegal addressing combination) NOT VALID (illegal addressing combination)
1x12x9x32 22 21 20 19 18 17 16 15 14 13 12 11 10 21 ‘0’ 23 9 8 7 6 5 4 3 2
1x12x9x16 22 21 20 19 18 17 16 15 14 13 12 11 10 21 ‘0’ 9 8 7 6 5 4 3 2 1
1x12x10x32 22 21 20 19 18 17 16 15 14 13 12 11 10 21 ‘0’ 24 23 9 8 7 6 5 4 3 2
Table 6-8. External to Internal Address Mapping for SA-1111 Addressing (Sheet 2 of 3)
# Bits External Address pins at SDRAM RAS Time External Address pins at SDRAM CAS Time
MA<24:10> MA<24:10>
Bank x
Row x
Col x 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Data
1x12x10x16 22 21 20 19 18 17 16 15 14 13 12 11 10 21 ‘0’ 23 9 8 7 6 5 4 3 2 1
1x12x11x32 NOT VALID (illegal addressing combination) NOT VALID (illegal addressing combination)
1x12x11x16 NOT VALID (illegal addressing combination) NOT VALID (illegal addressing combination)
1x13x8x32 23 22 21 20 19 18 17 16 15 14 13 12 11 10 21 ‘0’ 9 8 7 6 5 4 3 2
1x13x8x16 NOT VALID (illegal addressing combination) NOT VALID (illegal addressing combination)
1x13x9x32 23 22 21 20 19 18 17 16 15 14 13 12 11 10 21 ‘0’ 24 9 8 7 6 5 4 3 2
1x13x9x16 23 22 21 20 19 18 17 16 15 14 13 12 11 10 21 ‘0’ 9 8 7 6 5 4 3 2 1
1x13x10x32 23 22 21 20 19 18 17 16 15 14 13 12 11 10 21 ‘0’ 25 24 9 8 7 6 5 4 3 2
1x13x10x16 23 22 21 20 19 18 17 16 15 14 13 12 11 10 21 ‘0’ 24 9 8 7 6 5 4 3 2 1
1x13x11x32 NOT VALID (illegal addressing combination) NOT VALID (illegal addressing combination)
1x13x11x16 NOT VALID (illegal addressing combination) NOT VALID (illegal addressing combination)
2x11x8x32 22 21 20 19 18 17 16 15 14 13 12 11 10 22 21 ‘0’ 9 8 7 6 5 4 3 2
2x11x8x16 NOT VALID (illegal addressing combination) NOT VALID (illegal addressing combination)
2x11x9x32 22 21 20 19 18 17 16 15 14 13 12 11 10 22 21 ‘0’ 23 9 8 7 6 5 4 3 2
2x11x9x16 22 21 20 19 18 17 16 15 14 13 12 11 10 22 21 ‘0’ 9 8 7 6 5 4 3 2 1
2x11x10x32 22 21 20 19 18 17 16 15 14 13 12 11 10 22 21 ‘0’ 24 23 9 8 7 6 5 4 3 2
2x11x10x16 22 21 20 19 18 17 16 15 14 13 12 11 10 22 21 ‘0’ 23 9 8 7 6 5 4 3 2 1
2x11x11x32 NOT VALID (illegal addressing combination) NOT VALID (illegal addressing combination)
2x11x11x16 NOT VALID (illegal addressing combination) NOT VALID (illegal addressing combination)
2x12x8x32 23 22 21 20 19 18 17 16 15 14 13 12 11 10 23 22 ‘0’ 9 8 7 6 5 4 3 2
2x12x8x16 NOT VALID (illegal addressing combination) NOT VALID (illegal addressing combination)
2x12x9x32 23 22 21 20 19 18 17 16 15 14 13 12 11 10 23 22 ‘0’ 24 9 8 7 6 5 4 3 2
2x12x9x16 23 22 21 20 19 18 17 16 15 14 13 12 11 10 23 22 ‘0’ 9 8 7 6 5 4 3 2 1
2x12x10x32 23 22 21 20 19 18 17 16 15 14 13 12 11 10 23 22 ‘0’ 25 24 9 8 7 6 5 4 3 2
2x12x10x16 23 22 21 20 19 18 17 16 15 14 13 12 11 10 23 22 ‘0’ 24 9 8 7 6 5 4 3 2 1
2x12x11x32 NOT VALID (illegal addressing combination) NOT VALID (illegal addressing combination)
2x12x11x16 NOT VALID (illegal addressing combination) NOT VALID (illegal addressing combination)
Table 6-8. External to Internal Address Mapping for SA-1111 Addressing (Sheet 3 of 3)
# Bits External Address pins at SDRAM RAS Time External Address pins at SDRAM CAS Time
MA<24:10> MA<24:10>
Bank x
Row x
Col x 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Data
2x13x8x32 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 23 22 ‘0’ 9 8 7 6 5 4 3 2
2x13x8x16 NOT VALID (illegal addressing combination) NOT VALID (illegal addressing combination)
2x13x9x32 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 23 22 ‘0’ 25 9 8 7 6 5 4 3 2
2x13x9x16 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 23 22 ‘0’ 9 8 7 6 5 4 3 2 1
2x13x10x16 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 23 22 ‘0’ 25 9 8 7 6 5 4 3 2 1
Use the information below to connect the processor to the SDRAM devices. Some of the
addressing combinations may not apply in SA1111 addressing mode. See Table 6-10 for a complete
listing of supported addressing combinations and how to connect the PXA255 processor to the
SA1111.
Table 6-9. Pin Mapping to SDRAM Devices with Normal Bank Addressing (Sheet 1 of 3)
# Bits Pin mapping to SDRAM devices for Normal Addressing.
MA[24:10] represent the address signals driven from the processor.
Bank x
Row x
Col x MA24 MA23 MA22 MA21 MA20 MA19 MA18 MA17 MA16 MA15 MA14 MA13 MA12 MA11 MA10
Data
Table 6-9. Pin Mapping to SDRAM Devices with Normal Bank Addressing (Sheet 2 of 3)
# Bits Pin mapping to SDRAM devices for Normal Addressing.
MA[24:10] represent the address signals driven from the processor.
Bank x
Row x
Col x MA24 MA23 MA22 MA21 MA20 MA19 MA18 MA17 MA16 MA15 MA14 MA13 MA12 MA11 MA10
Data
Table 6-9. Pin Mapping to SDRAM Devices with Normal Bank Addressing (Sheet 3 of 3)
# Bits Pin mapping to SDRAM devices for Normal Addressing.
MA[24:10] represent the address signals driven from the processor.
Bank x
Row x
Col x MA24 MA23 MA22 MA21 MA20 MA19 MA18 MA17 MA16 MA15 MA14 MA13 MA12 MA11 MA10
Data
Table 6-10. Pin Mapping to SDRAM Devices with SA1111 Addressing (Sheet 1 of 3)
# Bits Pin mapping to SDRAM devices for SA1111 Addressing Options.
MA[24:10] represent the address signals driven from the PXA255 processor.
Bank x
Row x
Col x MA24 MA23 MA22 MA21 MA20 MA19 MA18 MA17 MA16 MA15 MA14 MA13 MA12 MA11 MA10
Data
Table 6-10. Pin Mapping to SDRAM Devices with SA1111 Addressing (Sheet 2 of 3)
# Bits Pin mapping to SDRAM devices for SA1111 Addressing Options.
MA[24:10] represent the address signals driven from the PXA255 processor.
Bank x
Row x
Col x MA24 MA23 MA22 MA21 MA20 MA19 MA18 MA17 MA16 MA15 MA14 MA13 MA12 MA11 MA10
Data
Table 6-10. Pin Mapping to SDRAM Devices with SA1111 Addressing (Sheet 3 of 3)
# Bits Pin mapping to SDRAM devices for SA1111 Addressing Options.
MA[24:10] represent the address signals driven from the PXA255 processor.
Bank x
Row x
Col x MA24 MA23 MA22 MA21 MA20 MA19 MA18 MA17 MA16 MA15 MA14 MA13 MA12 MA11 MA10
Data
Table 6-11 shows the SDRAM interface commands. The table assumes the bank bits for the
SDRAM are sent out on external address lines MA<24:23>.
PWRDN 1 0 1 1 1 1 1 x
PWRDNX 0 1 1 1 1 1 1 x
SLFRSH 1 0 0 0 0 1 0 x
CBR 1 1 0 0 0 1 x x
MRS 1 x 0 0 0 0 0 OP code
All x 1
PALL
1 x 0 0 1 0 x x x
PRE
Bank bank 0
1 x x x
NOP 1 x x x
0 1 1 1
The programmable opcode for address bits MA<24:17> used during the mode-register set
command (MRS) is exactly what is programmed in the MDMRS register.
tRP tRCD CL
SDCLK
nSDCS
nSDRAS
nSDCAS
nWE
DATA 0 1 2 3
DQM[3:0] 0000
tRP = 2 clks
tRAS = 2 clks
tRCD = 2 clks
CL = 2 clks
tRP = 2 clks
tRAS = 7 clks
tRCD = 2 clks
CL = 2 clks
tRP
tRCD CL tRCD CL
SDCLK
nSDCS
nSDRAS
nSDCAS
nWE
DATA 0 1 2 3 1 2 3 4
DQM[3:0] 0000
tRP = 2 clks
tRAS = 7 clks
tRCD = 2 clks
CL = 2 clks
tRAS
nSDCS
nSDRAS
nSDCAS
nWE
DATA 0 1 2 3 4 5 6 7
tRP = 2 clks
tRAS = 5 clks
tRCD = 2 clks
CL = 2 clks
tRP tRCD CL CL
SDCLK
nSDCS
nSDRAS
nSDCAS
nWE
DATA 0 1 2 3 4 5 6 7
DQM[3:0] 0000
tRP = 2 clks
tRCD = 2 clks
tRAS = 2 clks
CL = 2 clks
tRCD CL
SDCLK
nSDCS
nSDRAS
nSDCAS
nWE
DATA 0 1 2 3
SDCLK[1]
SDCKE[1]
nSDCS 0 1 1
nSDRAS
nSDCAS
nWE
Figure 6-11. SDRAM 4-Beat Write / 4-Write Same Bank, Same Row
tRP = 2 clks
tRCD = 2 clks
tRAS = 2 clks
CL = 2 clks
tRCD CL
SDCLK
nSDCS
nSDRAS
nSDCAS
nWE
DATA 0 1 2 3 4 5 6 7
If any of the nCS[3:0] banks are configured for Synchronous Static Memory via
SXCNFG[SXENx], the corresponding half-words of MSC0 (see Section 6.7.2) and MSC1, except
the data width in MSCx[RBWx], are ignored.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SXLATCH2
SXLATCH0
reserved
reserved
SXCA2
SXRA2
SXCA0
SXRA0
SXEN2
SXEN0
SXTP2
SXTP0
SXRL2 SXCL2 SXRL0 SXCL0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * * * * * * * * * * * * * 0 *
31 — reserved
SXMEM latching scheme for pair 2/3
0 – Latch return data with fixed delay on MEMCLK
30 SXLATCH2 1 – Latch return data with return clock
Must be set to a 1 to enable the return clock SDCLK for latching data. For more details on
this return data latching, see Section 6.5.4.
SX Memory type for partition pair 2/3
00 – Synchronous Mask ROM (SMROM)
29:28 SXTP2 01 – reserved
10 – non-SDRAM-like Synchronous Flash
11 – reserved
SX Memory column address bit count for partition pair 2/3
00 – 7 column address bits
27:26 SXCA2 01 – 8 column address bits
10 – 9 column address bits
11 – 10 column address bits
SX Memory row address bit count for partition pair 2/3
00 – 12 row address bits
25:24 SXRA2 01 – 13 row address bits
10 – reserved
11 – reserved
RAS Latency for SX Memory partition pair 2/3.
Number of external SDCLK cycles between receiving the ACT command and the READ
command. The unit size for SXRL2 is the external SDCLK cycle.
IF SXTP2 = “00” (SMROM):
000 – 1 clock
001 – 2 clocks
010 – 3 clocks
23:21 SXRL2
011 – 4 clocks
100 – 5 clocks
101 – 6 clocks
110 – 7 clocks
111 – 8 clocks
IF SXTP2 = 10 (non-SDRAM timing Fast Flash), this field is not used and must be
programmed to 111.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SXLATCH2
SXLATCH0
reserved
reserved
SXCA2
SXRA2
SXCA0
SXRA0
SXEN2
SXEN0
SXTP2
SXTP0
SXRL2 SXCL2 SXRL0 SXCL0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * * * * * * * * * * * * * 0 *
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SXLATCH2
SXLATCH0
reserved
reserved
SXCA2
SXRA2
SXCA0
SXRA0
SXEN2
SXEN0
SXTP2
SXTP0
SXRL2 SXCL2 SXRL0 SXCL0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * * * * * * * * * * * * * 0 *
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SXLATCH2
SXLATCH0
reserved
reserved
SXCA2
SXRA2
SXCA0
SXRA0
SXEN2
SXEN0
SXTP2
SXTP0
SXRL2 SXCL2 SXRL0 SXCL0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * * * * * * * * * * * * * 0 *
Table 6-15. Synchronous Static Memory External to Internal Address Mapping Options
# Bits External Address pins at SXMEM RAS Time External Address pins at SXMEM CAS Time
MA<24:10> MA<24:10>
Bank x
Row x
Col x 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Data
2x12x7x32 22 21 20 19 18 17 16 15 14 13 12 11 10 9 22 21 0 8 7 6 5 4 3 2
2x12x7x16 21 20 19 18 17 16 15 14 13 12 11 10 9 8 21 20 0 7 6 5 4 3 2 1
2x12x8x32 23 22 21 20 19 18 17 16 15 14 13 12 11 10 23 22 0 9 8 7 6 5 4 3 2
2x12x8x16 22 21 20 19 18 17 16 15 14 13 12 11 10 9 22 21 0 8 7 6 5 4 3 2 1
2x12x9x32 24 23 22 21 20 19 18 17 16 15 14 13 12 11 24 23 0 10 9 8 7 6 5 4 3 2
2x12x9x16 23 22 21 20 19 18 17 16 15 14 13 12 11 10 23 22 0 9 8 7 6 5 4 3 2 1
2x12x10x32 25 24 23 22 21 20 19 18 17 16 15 14 13 12 25 24 0 11 10 9 8 7 6 5 4 3 2
2x12x10x16 24 23 22 21 20 19 18 17 16 15 14 13 12 11 24 23 0 10 9 8 7 6 5 4 3 2 1
2x13x7x32 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 23 22 0 8 7 6 5 4 3 2
2x13x7x16 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 22 21 0 7 6 5 4 3 2 1
2x13x8x32 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 24 23 0 9 8 7 6 5 4 3 2
2x13x8x16 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 23 22 0 8 7 6 5 4 3 2 1
2x13x9x32 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 25 24 0 10 9 8 7 6 5 4 3 2
2x13x9x16 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 24 23 0 9 8 7 6 5 4 3 2 1
2x13x10x16 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 25 24 0 10 9 8 7 6 5 4 3 2 1
To write a new MRS value to a synchronous static memory, first enable and configure the memory
via the SXCNFG register, then write the SXMRS register. This register is only used for the value
written during the MRS command. All values in the SXCNFG register must be programmed
correctly to ensure proper device operation (refer to the external memory chip product
documentation for proper MRS encoding). Information programmed in the SXCNFG[CL] and
SXCNFG[RL] fields must match any CAS latencies and RAS latencies programmed in this
SXMRS register. Software must ensure that fields match the latencies. In some cases, duplicate
information must be programmed.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
reserved
SXMRS2 SXMRS0
Reset 0 0 0 0 0 0 1 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 1 0
31 — reserved
MRS value to be written to Synchronous Static memory requiring an MRS command for
30:16 SXMRS2
Bank Pair 2
15 — reserved
MRS value to be written to Synchronous Static Memory requiring an MRS command for
14:0 SXMRS0
Bank Pair 0
RL = 2 CL = 5
SDCLK
SDCKE
nCS[0]
nSDRAS
nSDCAS
nWE
nOE
MD d0 d1 d2
DQM[3:0] 0000
RDnWR
Consult the documentation for the memory being used. Table 6-17 is provided only as a reference.
The frequency configuration must be determined based on the CLK-to-output delay, the CLK
period, and the nADV-to-output delay timing parameters of the Flash device.
The values for this part number are shown as an example. For Intel part number 28F800F3,
programming values for this register to ensure proper operation with the processors are shown in
Table 6-17.
Software must ensure that the CLK-to-output delay is less than 1 SDCLK period for non-SDRAM
Timing Synchronous Flash.
010
2:0 BURST LENGTH
8 Word Burst
5:3 reserved 000
1
6 CLOCK CONFIGURATION
Use rising edge of clock
1
7 BURST SEQUENCE Linear burst Order
(INTEL BURST ORDER IS NOT SUPPORTED)
N/A
8 WAIT CONFIGURATION nWAIT from the Flash device is ignored by the
processor.
0
9 DATA OUTPUT CONFIGURATION
Hold data for one clock
10 reserved 0
010 -> CAS Latency 3
011 -> CAS Latency 4
100 -> CAS Latency 5
13:11 FREQUENCY CONFIGURATION 101 -> CAS Latency 6
110 -> CAS Latency 7
Chosen based on the AC Characteristics - Read only
Operation section of the Flash device data sheet
14 reserved 0
0 - Synchronous Operation
15 READ MODE
1 - Asynchronous Operation
Table 6-18 shows sample frequency configurations for programming non-SDRAM Timing Fast
Flash. When in doubt, the higher frequency configuration and corresponding CAS latency must be
used.
Table 6-18. Frequency Code Configuration Values Based on Clock Speed (Sheet 1 of 2)
Valid
MEMCLK SDCLK0 MDREFR: Corresponding
Frequency
Frequency Frequency K0DB2 CAS Latencies
Configurations
20 20 0 2/3/4/5/6 3/4/5/6/7
33 33 0 3/4/5/6 4/5/6/7
50 0 4/5/6 5/6/7
50
25 1 2/3/4/5/6 3/4/5/6/7
66 0 5/6 6/7
66
33 1 3/4/5/6 4/5/6/7
100 50 1 4/5/6 5/6/7
118 59 1 5/6 6/7
Table 6-18. Frequency Code Configuration Values Based on Clock Speed (Sheet 2 of 2)
Valid
MEMCLK SDCLK0 MDREFR: Corresponding
Frequency
Frequency Frequency K0DB2 CAS Latencies
Configurations
SDCLK[0]
nCS[0]
nADV(nSDCAS)
nOE
nWE
SXCNFG[CL]
MD[31:0]
DQM[3:0] 0000
This diagram is for SXCNFG:CL = "100" (CAS Latency = 5) (Frequency Code Configuration = 4)
K3 Flash
GPIO[1] nS Q
#RST
nRESET_OUT
nR ESET
GPIO_a nR
If Watchdog reset is not necessary, a secondary GPIO can control nRESET_OUT using the
equation #RST = nRESET & (nRESET_OUT | GPIO_a). This allows sleep mode entry to reset the
flash memory while keeping it in synchronous mode during a GPIO reset. Figure 6-15 shows the
required logic. GPIO_a is an unused GPIO that is kept high during normal operation and driven
low before sleep mode entry.
Figure 6-15. Flash Memory Reset Logic if Watchdog Reset is Not Necessary
K3 Flash
GPIO_a
#RST
nRESET_OUT
nRESET
The Variable Latency I/O interface differs from SRAM in that it allows the use of the data-ready
input signal, RDY, to insert a variable number of memory-cycle wait states. The data bus width for
each chip-select region can be programmed as 16- or 32-bit. nCS[3:0] can also be configured for
Synchronous Static Memory (refer to Section 6.6). During Variable Latency I/O writes, nPWE is
used instead of nWE so SDRAM refreshes can be executed while performing the VLIO transfers.
The use of the signals nOE, nWE, and nPWE is summarized below:
• nOE is asserted for all reads
• nWE is asserted for Flash and SRAM writes
• nPWE is asserted for Variable Latency I/O writes
For SRAM and Variable Latency I/O implementations, DQM[3:0] signals are used for the write
byte enables, where DQM[3] corresponds to the MSB. The processor supplies 26-bits of byte
address for access of up to 64 Mbytes per chip select. This byte address is sent out on the 26
external address pins. Do not connect MA[1:0] for 32-bit systems. Do not connect MA[0] for 16-
bit systems (the PXA255 processor operating in 16-bit mode). For all reads on a 32 bit system
DQM[3:0] and MA[1:0] are 0. For all reads on a 16 bit system DQM[1:0] and MA[0] are 0. In the
timing diagrams, these byte addresses are shown and referred to as “addr”.
8-bit 00 1110
8-bit 01 1101
8-bit 10 1011
8-bit 11 0111
16-bit 00 1100
16-bit 10 0011
32-bit 00 0000
8-bits 0 10
8-bits 1 01
16-bits 0 00
The RBW fields specify the bus width for the memory space selected by nCS[5:0]. For a 16-bit bus
width transactions occur on MD[15:0]. The BOOT_SEL pins and/or SXCNFG register must be
used to configure nCS[3:0] for SMROM or some other type of Synchronous Static Memory.
When programming a different memory type in an MSC register, ensure that the new value has
been accepted and programmed before issuing a command to that memory. To do this, the MSC
register must be read after it is written and before an access to the memory is attempted. This is
especially important when changing from ROM/Flash to an unconstrained writable memory type
(such as SRAM).
If any of the nCS[3:0] banks is configured for Synchronous Static Memory via SXCNFG[SXENx],
the corresponding half-words of MSC0 and/or MSC1 are ignored, except MSCx:RBWx, the data
width. Another exception is non-SDRAM timing Synchronous Flash, which writes asynchronously
and requires these programmed values.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RBUFF1/3/5
RBUFF0/2/4
RBW1/3/5
RBW0/2/4
RRR0/2/4
RRR1/3/5 RDN1/3/5 RDF1/3/5 RT1/3/5 RDN0/2/4 RDF0/2/4 RT0/2/4
Reset 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 * 0 0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RBUFF1/3/5
RBUFF0/2/4
RBW1/3/5
RBW0/2/4
RRR0/2/4
RRR1/3/5 RDN1/3/5 RDF1/3/5 RT1/3/5 RDN0/2/4 RDF0/2/4 RT0/2/4
Reset 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 * 0 0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RBUFF1/3/5
RBUFF0/2/4
RBW1/3/5
RBW0/2/4
RRR0/2/4
RRR1/3/5 RDN1/3/5 RDF1/3/5 RT1/3/5 RDN0/2/4 RDF0/2/4 RT0/2/4
Reset 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 * 0 0 0
ROM type
000 - Nonburst ROM or Flash Memory
001 - SRAM
010 - Burst-of-four ROM or Flash (with non-burst writes)
011 - Burst-of-eight ROM or Flash (with non-burst writes)
100 - Variable Latency I/O (VLIO)
101 - reserved
110 - reserved
2:0 R/W RTx<2:0>
111 - reserved
Burst refers to the device’s timing. When the subsequent reads from the
device take less time than the first read from a device, it is referred to as
burst timing. The address bits must also be taken into account for burst
timing devices. For example, in a burst-of-four device, only the lower two
non-byte address bits can change for burst timing. For 32-bit devices, this is
MA[3:2]. The address order can go 00, 01, 10, 11 where the reads from 01,
10, and 11, take less time to come out of the device. For burst-of-eight
devices, the lower three non-byte address bits can change. Writes to these
devices are non-burst.
Table 6-22. Asynchronous Static Memory and Variable Latency I/O Capabilities
Timing (Memory Clocks)
Non-burst
000 ROM or RDF+1 RDF+1 0 N/A RDF+1 N/A
Flash
001 SRAM RDF+1 RDF+1 0 RDN+2 RDN+1 1
Burst-of-4 RDF+1 RDF+1
ROM or (0,4) (0,4)
010 0 N/A RDF+1 N/A
Flash (non- RDN+1 RDN+1
burst writes) (1:3,5:7) (1:3,5:7)
Burst-of-8
RDF+1 RDF+1
ROM or
(0) (0)
011 Flash 0 N/A RDF+1 N/A
RDN+1 RDN+1
(non-burst
(1:7) (1:7)
writes)
Variable RDF+ RDF+1+ RDF+ RDF+1+
100 RDN+2 RDN+2
Latency I/O RDN+2+waits waits RDN+2+waits waits
RRR must be programmed with the maximum tOFF value, as specified by the ROM manufacturer.
For hardware reset initialization values, refer to Section 6.8. MSC0[15:0] is selected when the
address space corresponding to nCS0 is accessed. The processor supports a ROM burst size of 1, 4,
or 8 by configuring the MSCx[RTx] register bits to 0, 2 or 3 respectfully.
CLK_MEM
nCS[0]
tAS
MA[25:5]
RDF+2 RDN+1
MA[4:2] 0 1 2 3 4 5 6 7
MA[1:0] "00"
RDF+1 RRR*2+1
nADV(nSDCAS)
tCES tCEH
nOE
nWE
RDnWR
tDOH
tDSOH
MD[31:0]
DQM[3:0] "0000"
nCS[1]
* MSC0:RDF0 = 4, RDN0 = 1, RRR0 = 1 tAS = Address Setup to nCS asserted = 1 clk_mem
tCES = nCS setup to nOE asserted = 0 ns
tCEH = nCS hold from nOE deasserted = 0 ns
tDSOH = MD setup to Address changing = 1.5 clk_mems plus
board routing delays
tDOH = MD hold from Address changing = 0 ns
Figure 6-18. Eight-Beat Burst Read from 16-Bit Burst-of-Four ROM or Flash (MSC0[RDF] = 4,
MSC0[RDN] = 1, MSC0[RRR] = 0)
CLK_MEM
nCS[0]
tAS
MA[25:5]
RDF+2 RDN+1
MA[4:2] 0 1 2 3 4 5 6 7
MA[1:0] "00"
RDF+1 RRR*2+1
nADV(nSDCAS)
tCES tCEH
nOE
nWE
RDnWR
tDOH
tDSOH
MD[31:0]
DQM[3:0] "0000"
nCS[1]
* MSC0:RDF0 = 4, RDN0 = 1, RRR0 = 1 tAS = Address Setup to nCS asserted = 1 clk_mem
tCES = nCS setup to nOE asserted = 0 ns
tCEH = nCS hold from nOE deasserted = 0 ns
tDSOH = MD setup to Address changing = 1.5 clk_mems plus
board routing delays
tDOH = MD hold from Address changing = 0 ns
Figure 6-19. 32-Bit Non-burst ROM, SRAM, or Flash Read Timing Diagram - Four Data Beats
(MSC0[RDF] = 4, MSC0[RRR] = 1)
MEMCLK
nCS[0]
RDF+2 RDF+1
RDF+1
MA[25:2] 0 1 2 3
MA[1:0] 00
RDF+1 RRR*2+1
RDF+1
nADV(nSDCAS)
nOE
nWE
RDnWR
MD[31:0]
DQM[3:0] 0000
nCS[1]
The timing for a read access is identical to that for a non-burst ROM (see Section 6.7.3.1). The
RDF fields in the MSCx registers select the latency for a read access. The MSCx[RDN] field
controls the nWE low time during a write cycle. MSCx[RRR] is the time from nCS deassertion
after a memory access to the start of another memory access. MSCx[RTx] must be configured to
0b001 to select SRAM.
For writes to SRAM, if all byte enables are turned off (masking out the data, DQM = 1111), then
the write enable are 1 (nWE = 1) for this write beat. This can result in a period when nCS is
asserted, but neither nOE nor nWE is asserted. This happens with a write of 1 beat to SRAM, but
all byte enables are turned off.
MEMCLK
nCS[0]
tAS
MA[25:2] 0 1 2 3
tASW
tCES tAH tCEH
RRR*2+1
RDN+1
RDN RDN+1 RDN+1 RDN+1
nWE
nOE
RDnWR
tDH
tDSWH mask data bytes
MD[31:0] D0 D1 D2 D3
nCS[1]
nADV(nSDCAS)
Both reads and writes for VLIO differ from SRAM in that the processor samples the data-ready
input, RDY. The RDY signal is level sensitive and goes through a two-stage synchronizer on input.
When the internal RDY signal is high, the I/O device is ready for data transfer. This means that for
a transaction to complete at the minimum assertion time for either nOE or nPWE (RDF+1), the
RDY signal must be high two clocks prior to the minimum assertion time for either nOE or nPWE
(RDF-1). Data will be latched on the rising edge of MEMCLK once the internal RDY signal is high
and the minimum assertion time of RDF+1 has been reached. Once the data has been latched, the
address may change on the next rising edge of MEMCLK or any cycles thereafter. The nOE or
nPWE signal will de-assert one MEMCLK after data is latched. Before a subsequent data beat,
nOE or nPWE remains deasserted for RDN+2 memory cycles. The chip select and byte selects,
DQM[3:0], remain asserted for one memory cycle after the burst’s final nOE or nPWE deassertion.
For both reads and writes from/to VLIO, a DMA mode exists that does not increment the address to
the VLIO, which will allow port-type VLIO chips to interface to the processor. See
DCMDx[INCSRCADDR] and DCMDx[INCTRGADDR] in Table 5-12, “DCMDx Bit
Definitions” on page 5-24.
For writes to VLIO, if all byte enables are turned off, masking out the data, DQM = 1111, the write
enable is suppressed (nPWE = 1) for this write beat to VLIO. This can result in a period when nCS
is asserted, but neither nOE nor nPWE is asserted (this happens when there is a write of 1 beat to
VLIO, but all byte enables are turned off).
CLK_MEM
nCS[0]
tAS
MA[25:2] addr addr + 1 addr + 2 addr + 3
MA[1:0] "00"
RDN
RDN+2 RDN+2
RDN+ RDN+2
RDN+
0 Waits 1 Wait 2 Waits 3 Waits
nPWE
RDnWR
RDY
RDY_sync
MD[31:0]
DQM[3:0] "0000"
*MSC0: RDF0 = 3, RDN0 = 2, RRR0 = 1 tAS = Address Setup to nCS asserted = 1 clk_mem
tAH = Address Hold from nOE deasserted = 1 clk_mem
tASRW0 = Address Setup to nOE asserted (1st access) = 3 clk_mems
tASRWn = Address Setup to nOE asserted (next access(s)) = RDN clk_mems
tCES = nCS setup to nOE asserted = 2 clk_mems
tCEH = nCS hold from nOE deasserted = 1 clk_mem
tDSOH = MD setup to Address changing = 1.5 clk_mems plus
board routing delays
tDOH = MD hold from Address changing = 0 ns
tRDYH = RDY Hold from nOE deasserted = 0 ns
Figure 6-22. 32-Bit Variable Latency I/O Write Timing (Burst-of-Four, Variable Wait Cycles Per
Beat)
MEMCLK
nCS[0]
tAS
MA[25:2] 0 1 2 3
tASRW0 tASWN
tAH
RDF+1+Waits tCEH
tCES
RDN+2
RDN+ RRR*2+1
nPWE
nOE
RDnWR
RDY
tDH
tDSWH
MD[31:0] D0 D1 D2 D3
nCS[1]
In Figure 6-21 and Figure 6-22, some of the parameters are defined as follows:
• tAS = Address setup to nCS = 1 MEMCLK
• tCES = nCS setup to nOE or nPWE = 2 MEMCLKs
• tASRW0 = Address setup to nOE or nPWE low (asserted) = 3 MEMCLKs
• tASRWn = Address setup to nOE or nPWE low (asserted) = RDN MEMCLKs
• tDSWH,min = Minimum write data, DQM setup to nPWE high (deasserted) = (RDF+2)
MEMCLKs
• tDHW = Data, DQM hold after nPWE high (deasserted) = 1 MEMCLK
• tDHR = Data hold required after nOE deasserted = 0 ns
• tCEH = nCS held asserted after nOE or nPWE deasserted = 1 MEMCLK
• tAH = Address hold after nOE or nPWE deasserted = 1 MEMCLK
• nOE or nPWE high time between burst beats = (RDN+2) MEMCLKs
CLK_MEM
RRR*2+1
nCS[0]
tAS tAS
MA[25:2] command address data address
RDF+1 RDF+1
nWE
nOE
RDnWR
tDH tDH
tDSWH tDSWH
MD[31:0] CMD DATA
nADV(nSDCAS)
* A command and data write to Flash tAS = Address Setup to nCS asserted = 1 clk_mem
MSC0:RDF0 = 2, RRR0 = 2 tAH = Address Hold from nWE deasserted = 2 clk_mem
tASW = Address Setup to nWE asserted = 3 clk_mem
tCES = nCS setup to nWE asserted = 2 clk_mems
tCEH = nCS hold from nWE deasserted = 1 clk_mem
tDSWH = MD/DQM setup to nWE deasserted = RDF+2 clk_mems
tDH = MD/DQM hold from nWE deasserted = 1 clk_mem
The programming of each of the four fields in each of the six registers lets software to individually
select the duration of accesses to I/O, common memory, and attribute space for each of two 16-bit
PC Card/Compact Flash card slots.
Refer to Table 6-23 through Table 6-25 for bitmaps of the MCMEMx registers. Also refer to
Table 6-26. Refer to Figure 6-29 and Figure 6-30 for a 16-bit PC Card/Compact Flash timing
diagram.
These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31:20 — reserved
MCMEMx_H Minimum Number of memory clocks to set up address before command assertion for
19:14
OLD MCMEM for socket x is equal to MCMEMx_HOLD + 2.
13:12 — reserved
MCMEMx_A Code for the command assertion time. See Table 6-26 for a description of this code and its
11:7
SST affects on the command assertion.
MCMEMx_S Minimum Number of memory clocks to set up address before command assertion for
6:0
ET MCMEM for socket x is equal to MCMEMx_SET + 2.
These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
ATTx_SET
reserved ATTx_HOLD ATTx_ASST
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31:20 — reserved
MCATTx_HO Minimum Number of memory clocks to set up address before command assertion for
19:14
LD MCATT for socket x is equal to MCATTx_HOLD + 2.
13:12 — reserved
MCATTx_AS Code for the command assertion time. See Table 6-26 for a description of this code and its
11:7
ST affects on the command assertion.
MCATTx_SE Minimum Number of memory clocks to set up address before command assertion for
6:0
T MCATT for socket x is equal to MCATTx_SET + 2.
These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31:20 — reserved
MCIOx_HOL Minimum Number of memory clocks to set up address before command assertion for MCIO
19:14
D for socket x is equal to MCIOx_HOLD + 2.
13:12 — reserved
MCIOx_ASS Code for the command assertion time. See Table 6-26 for a description of this code and its
11:7
T affects on the command assertion.
Minimum Number of memory clocks to set up address before command assertion for MCIO
6:0 MCIOx_SET
for socket x is equal to MCIOx_SET + 2.
# MEMCLKs # MEMCLKs
# MEMCLKs
(minimum) (minimum) # MEMCLKs # MEMCLKs
Code (minimum)
Programmed to assert to assert (minimum) (minimum)
decimal to wait before
Bit Value command command command command
value checking for
(nPIOW) after (nPIOR) after assertion time assertion time
nPWAIT=’1’
nPWAIT=’1’ nPWAIT=’1’
00000 0 2 3 4 5 6
00001 1 3 5 6 8 9
00010 2 4 7 8 11 12
00011 3 5 9 10 14 15
00100 4 6 11 12 17 18
00101 5 7 13 14 20 21
00110 6 8 15 16 23 24
00111 7 9 17 18 26 27
01000 8 10 19 20 29 30
01001 9 11 21 22 32 33
01010 10 12 23 24 35 36
01011 11 13 25 26 38 39
01100 12 14 27 28 41 42
01101 13 15 29 30 44 45
01110 14 16 31 32 47 48
01111 15 17 33 34 50 51
10000 16 18 35 36 53 54
10001 17 19 37 38 56 57
10010 18 20 39 40 59 60
10011 19 21 41 42 62 63
10100 20 22 43 44 65 66
10101 21 23 45 46 68 69
10110 22 24 47 48 71 72
10111 23 25 49 50 74 75
11000 24 26 51 52 77 78
11001 25 27 53 54 80 81
11010 26 28 55 56 83 84
11011 27 29 57 58 86 87
11100 28 30 59 60 89 90
# MEMCLKs # MEMCLKs
# MEMCLKs
(minimum) (minimum) # MEMCLKs # MEMCLKs
Code (minimum)
Programmed to assert to assert (minimum) (minimum)
decimal to wait before
Bit Value command command command command
value checking for
(nPIOW) after (nPIOR) after assertion time assertion time
nPWAIT=’1’
nPWAIT=’1’ nPWAIT=’1’
11101 29 31 61 62 92 93
11110 30 32 63 64 95 96
11111 31 33 65 66 98 99
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NOS
CIT
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31:2 — reserved
Card-Is-There
0 – No card inserted
1 CIT 1 – Card inserted
Must be set by software when at least one card is present and must be cleared when all
cards are removed.
Number-of-Sockets
0 NOS 0 – 1 Socket
1 – 2 Sockets
reserved
0x3400_0000
reserved
0x2400_0000
The 16-bit PC Card Memory Map space is divided into eight partitions, four for each card slot. The
four partitions for each card slot are: common memory, I/O, attribute memory, and a reserved
space. Each partition starts on a 64-Mbyte boundary.
During an access, pins MA[25:0], nPREG, and PSKTSEL are driven at the same time. nPCE1 and
nPCE2 are driven concurrently with the address signals for common memory and attribute-
memory accesses. For I/O accesses, their value depends on the value of nIOIS16 and is valid a
fixed amount of time after nIOIS16 is valid.
Common memory and attribute memory accesses assert the nPOE or nPWE control signals. I/O
accesses assert the nIOR or nIOW control signals and use the nIOIS16 input signal to determine
the bus width of the transfer (8 or 16 bits). The PXA255 processor uses nPCE2 to indicate to the
expansion device that the upper half of the data bus (MD[15:8]) are used for the transfer, and
nPCE1 to indicate that the lower half of the data bus (MD[7:0]) are used. nPCE1 and nPCE2 are
asserted for 16-bit accesses.
Refer to Table 6-28 through Table 6-35 for signal combinations during common memory, I/O, and
attribute accesses.
When writes goes to a card sockets and a byte has been masked via an internal byte enable, the
write does not occur on the external bus. For reads, one half-word is always read from the socket,
even if only 1 byte is requested. In some cases, based on internal address alignment, one word is
read, even if only 1 byte is requested.
All DMA modes are supported in the Card interface increment the address.
Figure 6-27 and Figure 6-28 show general solutions for a one- and two-socket configuration. The
pull-ups shown are included as specified in the PC Card Standard - Volume 2 - Electrical
Specification. Low-power systems must remove power from the pull-ups during sleep to avoid
unnecessary power consumption.
GPIO or memory-mapped external registers can be used to control the reset of the 16-bit PC Card
interface, power selection (VCC and VPP), and drive enables. The INPACK# signal is not used.
Figure 6-27 and Figure 6-28 provide the logical connections necessary to support hot insertion
capability. For dual-voltage support, level shifting buffers are required for all PXA255 processor
input signals. Hot insertion capability requires that each socket be electrically isolated from the
other and from the remainder of the memory system. If one or both of these features is not required,
then some of the logic shown in the following diagrams can be eliminated.
Software is responsible for setting the MECR[NOS] and MECR[CIT] bits. NOS indicates the
number of sockets that the system support while CIT is written when the Card is in place. Input
pins nPWAIT and nIOIS16 are three stated until card detect (CD) signal is asserted. To achieve
this, software programs the MECR[CIT] bit when a card is detected. If the MECR[CIT] is 0, the
nPWAIT and nIOIS16 inputs are ignored.
Figure 6-27 shows the minimal glue logic needed for a 1-socket system, including: data
transceivers, address buffers, and level shifting buffers. The transceivers are enabled by the
PSKTSEL signal. The DIR pin of the transceiver is driven by the RD/nWR pin. A GPIO is used for
the three-state signal of the address and nPWE lines. These signals must be three-stated because
they are used for memories other than the card interface. The Card Detect[1:0] signals are driven
by the signal device.
MD<15:0> D<15:0>
DIR nOE
RD/nWR
GPIO<w> nPCD0
nCD<1>
GPIO<x> nPCD1 nCD<2>
PSKTSEL
MA[25:0] A[25:0]
nWE
nPWE
nPREG nREG
nPCE<2:1> nCE<2:1>
nPOE nOE
nPIOR nIOR
nPIOW nIOW
5V to 3.3V or 2.5V
nPWAIT nWAIT
5V to 3.3V or 2.5V
nIOIS16 nIOIS16
Figure 6-28 shows the glue logic need for a 2-socket system. RDY/nBSY signals are routed
through a buffer to two separate GPIO pins. In the data bus transceiver control logic, nPCE1
controls the enable for the low byte lane and nPCE2 controls the enable for the high byte lane.\
PXA255
Processor Socket 0
D(15:0) D(15:0)
DIR OE#
nPCEx
Socket 1
D(15:0)
DIR OE#
nPOE
nPIOR
nPCEx
CD1#
GPIO(w)
CD2#
CD1#
GPIO(x)
CD2#
GPIO(y) RDY/BSY#
GPIO(z) RDY/BSY#
PSKTSEL
MA(25:0) A(25:0)
nPREG REG#
A(25:0)
nPCE(1:2) CE(1:2)# REG#
nPOE, OE#
6 6
nPWE WE#
nPIOW, IOR# CE(1:2)#
nPIOR IOW# OE#
6
WE#
IOR#
IOW#
WAIT#
nPWAIT
WAIT#
IOIS1616#
nPIOIS16
IOIS1616#
MEMCLK
MA,nPREG,PSKTSEL
nPCE2,nPCE1
x_SET x_HOLD
nPWE,nPOE,nPIOW,nPIOR
RDnWR
nIOIS16
x_ASST_HOLD
nPWAIT
read_data
write_data
MEMCLK
MA[25:1],nPREG,PSKTSEL
MA[0]
nPCE2
nPCE1
IOx_SET IOx_SET
IOx_HOLD IOx_HOLD
nPIOW,nPIOR
RDnWR
nIOIS16
IOx_ASST_HOLD IOx_ASST_HOLD
nPWAIT
read_data
The interface waits the smallest possible amount of time (x_ASST_WAIT) before it checks the
value of the nPWAIT signal. If the nPWAIT signal is asserted (active low), the interface continues
to wait (for a variable number of wait states) until nPWAIT is deasserted. When the nPWAIT signal
is deasserted, the command continues to be asserted for a fixed amount of time (x_ASST_HOLD).
EXTERNAL SYSTEM
Processor
SDCKE<1>
SDCLK<1>
nSDCS(0)
nSDRAS
External
Memory nSDCAS SDRAM
Controlle Bank 0
nWE
MA[25:0]
DQM[3:0]
MD[31:0]
MBREQ
MBGNT
Companion
Chip
GPIO
Block
GPIO<13> (MBGNT)
GPIO<14> (MBREQ)
EXTERNAL SYSTEM
Processor
nCS(0,1,2,3,4,5)
nOE
nPWE
Memory MA[25:0] Companion
Controller Chip
DQM[3:0]
MD[31:0]
RDY
During the three-state period, both MBREQ and MBGNT remain high and an external device can
take control of the three-stated pins. The external device must drive all the three-stated pins.
Floating inputs can cause excessive crossover current and erroneous SDRAM commands. During
the three-state period, the processor can not perform SDRAM refresh cycles.
The alternate master must assume the responsibility for SDRAM integrity during the three-state
period. The system must be designed to ensure that the period of alternate mastership is limited to
less than the refresh period or that the alternate master implements a refresh counter to perform
refreshes at the proper intervals.
To surrender the bus, the alternate master deasserts MBREQ. The processor deasserts SDCKE<1>
and MBGNT. The alternate master stops driving the SDRAM pins. The processor drives all
SDRAM pins and then re-asserts SDCKE<1>.
7. The Memory Controller performs an SDRAM refresh if SDRAM clocks and clock enable are
turned on.
8. The Memory Controller sends an MRS command to the SDRAMs if the MDCNFG:SA1111x
bit is enabled. This changes the SDRAM burst length back to four.
If the refresh counter for the processor requested a refresh cycle during the alternate master’s
tenure, a refresh cycle runs first, followed by any other bus transactions that stalled during that
period.
To enable alternate bus master, the set up the signals by writing the following registers:
• Write the GPIO Pin Direction register GPDR0 to set bit 13 (make GPIO[13] an output) and
clear bit 14 (make GPIO[14] an input)
• Write the GPIO Alternate Function register GAFR0_L to set bits 27 and 26 to 0b11 (enable the
MBGNT alternate function 3) and set bits 29 and 28 to 0b01 (enable the MBREQ alternate
function 1).
If a transaction is in progress when GPIO reset is asserted, the alternate master loses ownership of
the bus. The alternate master must immediately give up the bus when MBGNT is deasserted.
Because the memory controller is not reset, an SDRAM refresh can occur immediately after the
GPIO reset assertion.
The memory controller prevents the processor from entering sleep until all outstanding transactions
have completed. This includes waiting for the MBREQ signal from the alternate master to deassert.
For best sleep performance, the alternate master must immediately give up the bus when MBGNT
is deasserted. If necessary, the alternate master can hold the bus until its transaction is completed.
After the memory controller has completed all outstanding transactions, it places SDRAM into
self-refresh and allows the processor to complete the sleep entry sequence.
Note: The alternate bus master must de-assert MBREQ when nVDD_FAULT or nBATT_FAULT is
asserted.
The memory controller prevents the processor from entering sleep until all outstanding transactions
have completed. This includes waiting for the MBREQ signal from the alternate master to deassert.
For best sleep performance, the alternate master must immediately give up the bus when MBGNT
is deasserted or, as part of the sleep entry routine, the alternate master can be disabled. If necessary,
the alternate master can hold the bus until its transaction is completed. After the memory controller
has completed all outstanding transactions, it places SDRAM into self-refresh and allows the
processor to complete the sleep entry sequence.
Note: The alternate bus master must de-assert MBREQ when nVDD_FAULT or nBATT_FAULT is
asserted.
0 1 0 reserved
0 1 1 reserved
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOT_SEL
PKG_TYPE
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * * * *
31:4 — reserved
000
001
100
(PXA255 processor)
101
110
111
BOOT_SEL[2:0] = 000
MSC0 0x7FF0_7FF0
32 Asynchronous RBW0 = 0
32-bit
ROM SXCNFG 0x0004_0004
MDREFR 0x03CA_4FFF
E0PIN = 0, K0RUN = 0
BOOT_SEL[2:0] = 001
MSC0 0x7FF0_7FF8
16 Asynchronous RBW0 = 1
16-bit
ROM SXCNFG 0x0004_0004
MDREFR 0x03CA_4FFF
E0PIN = 0, K0RUN = 0
BOOT_SEL[2:0] = 100
32 SMROM
32-bit MSC0 7FF0 7FF0
(64 Mbit) RBW0 = 0
(nWORD = 1)
SXCNFG 0004 4531
or
SXEN0 = 1h, SXCL0 = 4h (CL = 5),
SXRL0 = 1h (RL = 2), SXRA0 = 1h (13-bits),
SMROM
SXCA0 = 1h (8-bits), SXTP0 = 0h, SXLATCH=1h
16 16-bit
(32 Mbit)
MDREFR 03CA 7FFF
32 (nWORD = 0)
E0PIN = 1, K0RUN = 1
16 SMROM
16-bit
(32 Mbit) BOOT_SEL[2:0] = 100 SXMRS 0232 0232
(nWORD = 0) BOOT_SEL[2:0] = 101 SXMRS 0232 0232
BOOT_SEL[2:0] = 101
MSC0 7FF0 7FF8
16 SMROM RBW0 = 1
16-bit
(64 Mbit) SXCNFG 0004 4931
(nWORD = ‘0’)
SXEN0 = 1h, SXCL0 = 4h (CL = 5),
SXRL0 = 1h (RL = 2), SXRA0 = 1h (13-bits),
SXCA0 = 2h (9-bits), SXTP0 = 0h, SXLATCH=1h
BOOT_SEL[2:0] = 110
BOOT_SEL[2:0] = 111
In sleep mode, the memory pins and controller are in the same state as they are after a hardware
reset, except that the GPIO signals are driven high. If SDRAMs are in self-refresh, they are held
there by setting SDCKE<1> to a 0.
being configured, the SDRAM banks must be disabled and MDREFR:APD must be
deasserted (auto-power-down disabled).
a. Write SXCNFG (with enable bits asserted).
b. Write to SXMRS to trigger an MRS command to all enabled banks of synchronous static
memory.
c. SXLCR must only be written when it is required by the SDRAM-like synchronous flash
device for command encoding.
3. In systems that contain SDRAM, transition the SDRAM controller through the following state
sequence:
a. self-refresh and clock-stop
b. self-refresh
c. power-down
d. PWRDNX
e. NOP
4. The SDRAM clock run and enable bits (MDREFR:K1RUN, K2RUN, and E1PIN), described
in Section 6.5.3. MDREFR:SLFRSH must not be asserted.
a. Write MDREFR:K1RUN, K2RUN (self-refresh and clock-stop -> self-refresh).
Configure MDREFR:K1DB2,K2DB2.
b. Write MDREFR:SLFRSH (self-refresh -> power-down).
c. Write MDREFR:E1PIN (power-down -> PWRDNX).
d. a write is not required for this state transition (PWRDNX -> NOP).
e. Configure, but do not enable, each SDRAM partition pair.
f. Write MDCNFG (with enable bits deasserted), MDCNFG:DE3:2,1:0 set to ‘0’.
5. For systems that contain SDRAM, wait a specified NOP power-up waiting period required by
the SDRAMs to ensure the SDRAMs receive a stable clock with a NOP condition
6. Ensure the Data Cache bit (DCACHE) is disabled. If this bit is enabled, the refreshes triggered
by the next step may not pass through to the Memory Controller properly.
7. On a hardware reset in systems that contain SDRAM, trigger the specified number (typically
eight) of refresh cycles by attempting non-burst read or write accesses to any disabled
SDRAM bank. Each such access causes a simultaneous CBR refresh cycles for all four banks,
which causes a pass through the CBR state and back to NOP. On the first pass, the PALL state
occurs before the CBR state.
8. Re-enable the DCACHE bit if it is disabled.
9. In systems that contain SDRAM, enable SDRAM partitions by setting
MDCNFG:DE3:2,DE1:0.
10. In systems containing SDRAM, write the MDMRS register to trigger an MRS command to all
enabled banks of SDRAM. For each SDRAM partition pair that has one or both partitions
enabled, this forces a pass through the MRS state and back to NOP. The CAS latency must be
the only variable option and is derived from the value programmed in the
MDCNFG:MDTC0,2 fields. The burst type is programmed to sequential and the length is set
to four.
11. Optionally, in systems that contain SDRAM or Synchronous Static memory, enable auto-
power-down by setting MDREFR[APD].
After all the SDRAM rows have been refreshed, enable GPIO reset
7.1 Overview
The processor LCD controller supports single- or dual-panel displays. Encoded pixel data created
by the core is stored in external memory in a frame buffer in 1, 2, 4, 8, or 16-bit increments. The
data is fetched from external memory and loaded into a first-in first-out (FIFO) buffer on a demand
basis, using the LCD controller’s dedicated dual-channel DMA controller (DMAC). One channel is
used for single-panel displays and two are used for dual-panel displays.
Frame buffer data contains encoded pixel values that are used by the LCD controller as pointers to
index a 256-entry x 16-bit-wide palette. For 16 bit per pixel frame buffer entries, the palette RAM
is bypassed. Monochrome palette entries are eight bits wide, and color palette entries are 16 bits
wide. The encoded pixel data determines the number of possible colors within the palette as
follows:
• 1-bit-wide pixels address the top 2 locations of the palette
• 2-bit-wide pixels address the top 4 locations of the palette
• 4-bit-wide pixels address the top 16 locations of the palette
• 8-bit-wide pixels address any of the 256 entries within the palette
• 16-bit-wide pixels bypass the palette
When passive color 16-bit pixel mode is enabled, the color pixel values bypass the palette and are
fed directly to the LCD controller’s Frame Rate Control logic. When active color 16-bit pixel mode
is enabled, the pixel value bypasses the palette and the Frame Rate Control logic and is sent
directly to the LCD controller’s data pins. Optionally, the palette RAM is loaded for each frame by
the LCD controller’s DMAC.
Once the encoded pixel value is used to select a palette entry, the value programmed within the
entry is transferred to the Frame Rate Control logic, which uses the Temporal Modulated Energy
Distribution (TMED) algorithm to produce the pixel data that is sent to the screen. Frame Rate
Control is a technique used to create additional color shades by rapidly turning on and off a pixel
on the LCD screen. This is also known as temporal dithering. The data output from the dither logic
is grouped into the selected format (e.g., 8-bit color, dual panel, 16-bit color., etc.) and placed in a
FIFO buffer before being sent out on the LCD controller’s pins and driven to the display using the
pixel clock.
Depending on the type of panel used, the LCD controller is programmed to use either 4-, 8-, or 16-
pixel data output pins. Single-panel monochrome displays use either four or eight data pins to send
4 or 8 pixels for each pixel clock. Single-panel color displays use eight pins to send 2-2/3 pixels
each pixel clock (8 pins / 3 colors/pixel = 2 2/3 pixels per clock). The LCD controller also supports
dual-panel mode, in which the LCD controller’s data lines are split into two groups, one to drive
the top half and one to drive the bottom half of the screen. For dual-panel displays, the number of
pixel data output pins is doubled, allowing twice as many pixels to be sent each pixel clock to the
two halves of the screen.
In active color display mode, the LCD controller can drive TFT displays. When using 1-, 2-, 4-, or
8-bit modes, the LCD’s dither logic is bypassed, and the pixel value is sent from the palette buffer
directly to the LCD’s data output pins. 16-bit pixel mode bypasses both the palette and the dither
logic.
7.1.1 Features
The processor LCD controller supports the following features:
• Display modes:
— single- or dual-panel displays
— up to 256 gray-scale levels (8 bits) in Passive Monochrome Mode
— a total of 65536 possible colors in Passive Color Mode (using the 16-bit TMED dithering
algorithm)
— up to 65536 colors in Active Color Mode (16 bits, bypasses palette)
— passive 8-bit color single-panel displays
— passive 8-bit (per panel) color dual-panel displays
• Display sizes up to 1024x1024 pixels, recommended maximum of 640x480
• Internal color palette RAM 256 entry by 16 bits (can be loaded automatically at the beginning
of each frame)
• Encoded pixel data of 1, 2, 4, 8, or 16 bits
• Programmable toggle of AC bias pin output (toggled by line count)
• Programmable pixel clock from 195 kHz to 83 MHz (100 MHz/512 to 166 MHz/2)
• Integrated 2-channel DMA (one channel for palette and single panel, the other channel for
second panel in dual-panel mode).
• Programmable wait-state insertion at the beginning and end of each line
• Programmable polarity for output enable, frame clock, and line clock
• Programmable interrupts for input and output FIFO underrun
• Programmable frame and line clock polarity, pulse width, and wait counts
Figure 7-1 illustrates a simplified, top-level block diagram for the processor LCD Controller.
Figure 7-1. LCD Controller Block Diagram
System Bus
From Clock
Module LCDClk LCD DMA Controller
Encoded
pixel data
Raw pixel
data
Palette RAM
Raw
pixel data
TMED
Dithering
Engine
Dithered
pixels
Serializer
Output FIFOs
To Pins
L_DD[15:0]
Table 7-1 describes the LCD controller’s pins. For more detailed information, see Section 7.3.5.
All of the LCD pins are outputs only.
These data lines transmit either four or eight data values at a time to the LCD display. For
monochrome displays, each pin value represents a single pixel. For passive color, groupings of
three pin values represent one pixel (red, green, and blue subpixel data values). In single-panel
L_DD[7:0]
monochrome mode, L_DD<3:0> pins are used. For double-pixel data, single-panel
monochrome, dual-panel monochrome, single-panel color, and active color modes, L_DD[7:0]
are used.
When dual-panel color or TFT (active color mode) operation is programmed, these data outputs
L_DD[15:8]
are also required to send pixel data to the screen.
The Pixel Clock is used by the LCD display to clock the pixel data into the line shift register. In
passive mode, the pixel clock toggles only when valid data is available on the data pins. In
L_PCLK
active mode, the pixel clock toggles continuously, and L_BIAS serves as an output to signal
when data is valid on the LCD’s data pins.
The Line Clock is used by the LCD display to signal the end of a line of pixels. The display
L_LCLK transfers the line data from the shift register to the screen and increments the line pointer. In
active mode, it is the horizontal synchronization signal.
The Frame Clock is used by the LCD display to signal the start of a new frame of pixels. The
L_FCLK display resets the line pointer to the top of the screen. In active mode, it is the vertical
synchronization signal.
AC Bias is used to signal the LCD display to switch the polarity of the power supplies to the row
L_BIAS and column drivers of the screen to counteract DC offset. In active mode, it serves as the output
enable to signal when data is latched from the data pins using the Pixel Clock.
If the LCD controller is being re-enabled, there has not been a reset since the last programming,
and the GPIO pins are still configured for LCD Controller functionality, only the registers
FDADRx and LCCR0 need to be reprogrammed. The LCD Controller Status Register (LCSR)
must also be written to clear any old status flags before re-enabling the LCD controller. See
Section 7.6.7 for details.
Regular disabling, the recommended method for stopping the LCD controller, is accomplished by
setting the disable bit, LCCR0[DIS]. The other bits in LCCR0 must not be changed — read the
register, set the DIS bit, and rewrite the register. This method causes the LCD controller to stop
cleanly at the end of the frame currently being fetched from memory. If the LCD DMAC is
fetching palette data when DIS is set, the palette RAM load is completed, and the next frame is
displayed before the LCD is disabled. The LCD Disable Done bit, LCSR[LDD], is set when the
LCD controller finishes displaying the last frame fetched, and the enable bit, LCCR0[ENB], is
cleared automatically by hardware.
Quick disabling is accomplished by clearing the enable bit, LCCR0[ENB]. The LCD controller
will finish any current DMA transfer, stop driving the panel, and shut down immediately, setting
the quick-disable bit, LCSR[QD]. This method is intended for situations such as a battery fault,
where system bus traffic has to be minimized immediately so the processor can have enough time
to store critical data to memory before the loss of power. The LCD controller must not be re-
enabled until the QD bit is set, indicating that the quick shutdown is complete.
Once disabled, the LCD Controller automatically disables its clocks to conserve power.
The FIFO signals a service request to the DMAC whenever four FIFO entries are empty. In turn,
the DMAC automatically fills the FIFO with a 32-byte burst. Pixel data from the frame buffer
remains packed within individual 8-byte entries when it is loaded into the FIFO. If the pixel size is
1, 2, 4, or 8-bits, the FIFO entries are unpacked and used to index the palette RAM to read the color
value. In 16-bit passive mode, the entries bypass the palette and go directly to the TMED dither
logic. In 16-bit active mode, the pixels are sent directly to the pins.
Understanding how the TMED dithering algorithm works is not necessary to use the processor
LCD controller. However, certain characteristics of the algorithm can be controlled through the use
of the TMEDRGB Seed Register (Table 7-14) and the TMED Control Register (TCR, Table 7-15).
If these registers are to be modified from their default values, refer to this section. Figure 7-2
illustrates the TMED concept.
Figure 7-2. Temporal Dithering Concept - Single Color
Time X
Y
(frame #) position position
This dithering concept is applied separately to each color displayed. Each color has zeros added to
make the data for each color 8 bits. If a monochrome display is used, only a single matrix (blue) is
used.
The processor LCD Controller implements the following algorithm, which is used by TMED to
determine an upper and lower boundary:
LowerBoundary = [(PixelValue * FrameNumber) mod 256] + Offset
UpperBoundary = [(PixelValue + LowerBoundary) mod 256]
A 16x16 matrix uses the row (line), column (pixel number), and frame number (which wraps back
to 0 from 255) to select a matrix value. When the matrix value is between the lower and upper
boundaries from the algorithm, the LCD controller sends a “1” to the LCD panel. The boundaries
created by the algorithm are circular, wrapping from 255 back to 0, as shown in Figure 7-3.
Compare
Range
192 64
128
Either of two matrices may be used for each color, chosen by bits 0, 1, and 14 of the TMED
Control Register (TCR, Section 7.6.10). Offsets may be selected for the shading of each color to
avoid gray color problems. Although these offset values are panel dependent, the recommended
values are listed in Section 7.6.9, with the blue data path being used for monochrome modes.
Offsets may also be chosen in the TMED Control Register for shifting the row (horizontal) value,
line (vertical) value, and frame number.
Figure 7-4 shows the block diagram for TMED. Pixel data (up to 8 bits) enters the module and is
sent through the Color Value (CV) generator. Depending on the value of the TCR[TSCS] field, the
CV generator rounds off between 0 and 3 of the least-significant bits, creating a new CV. If the
original pixel value is 254 or 255, the final data output is set to one. Otherwise, the following
occurs:
1. The new CV is sent through the Color Offset Adjuster, where it is used as a lookup into the
matrix selected by TCR[COAM].
2. Either the 8-bit output of the chosen matrix or 00h, as selected by TCR[COAE], is added to the
appropriate color’s seed register value in register TRGBR to form an offset.
3. This offset is added to the result of the multiplication of the Frame Number and the CV to form
the algorithm’s lower boundary (only the lower 8 bits are used).
4. The CV is added to the lower boundary to obtain the upper boundary.
5. Row (line) and column (pixel) counters are combined with beat suppression (offset) values in
the Pixel Number Adjuster and Address Generator to form yet another address for a matrix
lookup.
6. The output of the chosen matrix is compared to the lower and upper boundaries in the Data
Generator.
7. If the matrix output is between these boundaries or the original pixel value is 254 or 255, then
the data output to the panel is one. In all other cases, it is zero.
TSR<7:0>
TCR<2> Color Lower Boundary
TCR<0> Offset Generator LB
Adjuster LB =FN x CV + Offset
TCR<13:12> Color Value
LB
Generator
pixel CV Upper Boundary
data
Generator UB Data Outpu
Generator Data
UB =LB + CV
force to 1 LB > ME > UB Bit
or Pixel > 253
Single Color Component Path (RED)
Outpu
Data
Single Color Component Path (GREEN) Bit
Outpu
Data
Single Color Component Path (BLUE) Bit
TCR<7:4>
pixel clk
Address ME
line clk Line Counter Pixel Number
Generator Matrix
Pixel Counter Adjustor
TCR<11:8>
TCR<14>
See Section 7.5 for pin timing diagrams. When the LCD controller is disabled, all of its pins can be
used for GPIO. See Chapter 4, “System Integration Unit” for further details. See also Table 7-1.
If an output FIFO underrun occurs (i.e., the LCD controller runs out of data), L_PCLK stalls until
valid data is available. This results in a slower pixel clock, but data sent to the display is always
valid.
To prevent a D.C. charge from building within a passive display, its power and ground supplies
must be switched periodically. Many modern panels do this automatically. If not, the LCD
controller can toggle the AC bias pin (L_BIAS) to signal the display to switch the polarity. The
frequency of the L_BIAS toggle is controlled by programming the number of line clock transitions
between each toggle (LCCR3[ACB]).
If an output FIFO underrun occurs, the data on the L_DD pins is repeated, L_BIAS stays asserted,
and L_PCLK keeps running. As valid data enters the output FIFO, it is sent to the display.
Additional pixel clocks are inserted at the end of the line to drain the remaining valid pixels from
the output FIFO before HSYNC is asserted. This mechanism allows an underrun to corrupt only a
single line rather than an entire frame.
7.3.6 DMA
Values for palette RAM entries and encoded pixel data are stored in off-chip memory and are
transferred to the LCD controller’s input FIFO buffers, on a demand basis, using the LCD
controller’s dedicated DMA controller (DMAC). The LCD’s descriptor-based DMAC contains two
channels that transfer data from external memory to the input FIFOs. One channel is used for
single-panel displays and two are used for dual-panel displays.
The LCD controller issues a service request to the DMAC after it has been initialized and enabled.
The DMAC automatically performs eight word transfers, filling four entries of the input FIFO.
Values are fetched from the bottom of the FIFO, one entry at a time, and each 64-bit value is
unpacked into individual pixel encodings of 1, 2, 4, 8, or 16 bits each. After the value is removed
from the bottom of the FIFO, the entry is invalidated, and all data in the FIFO is shifted down one
entry. When four of the entries are empty, a service request is issued to the DMAC. If the DMAC is
not able to keep the FIFO filled with enough pixel data (due to insufficient external memory access
speed) and the FIFO is emptied, the appropriate FIFO underrun status bit is set (bit IUL or IUU in
register LCSR), and an interrupt request is issued (unless it is masked).
After enabling the LCD controller, the user must first load the palette RAM before processing any
frame data. After the initial load, the palette can be reloaded optionally on a frame-by-frame basis.
This would be done when the color selection changes frame to frame. The palette RAM is always
loaded with DMA channel 0.
Figure 7-5 shows the format of the palette entries in little endian. “Endian” does not imply
endianness with respect to bytes and half-words within memory. It refers strictly to the ordering of
the palette entries; i.e., whether palette entry 0 is at the MSB or the LSB of a word boundary. The
ordering of RGB values within the 16-bit entry is fixed for little endian. In Figure 7-5, “Base” is the
palette buffer base programmed in register FSADR.
In the following figures, “Base” refers to the initial address programmed in the FSADR register,
“Palette Buffer Index” refers to the data that specifies the location in the palette buffer, and “Raw
Pixel Data” refers to the actual 16-bit RGB data when the palette RAM is bypassed.
Bit 0
Bit 31 30 29 28 ... 3 2 1 0
Base +
Pixel 31 Pixel 30 Pixel 29 Pixel 28 ... Pixel 3 Pixel 2 Pixel 1 Pixel 0
0x0
Base +
Pixel 63 Pixel 62 Pixel 61 Pixel 60 ... Pixel 35 Pixel 34 Pixel 33 Pixel 32
0x4
Bit 1 0
Bit 31 30 29 28 27 26 ... 7 6 5 4 3 2 1 0
Base
Pixel 15 Pixel 14 Pixel 13 ... Pixel 3 Pixel 2 Pixel 1 Pixel 0
+ 0x0
Base
Pixel 31 Pixel 30 Pixel 29 ... Pixel 19 Pixel18 Pixel 17 Pixel 16
+ 0x4
Bit 3 2 1 0
Bit 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
Base
Pixel 7 Pixel 6 Pixel 5 Pixel 4 Pixel 3 Pixel 2 Pixel 1 Pixel 0
+ 0x0
Base
Pixel 15 Pixel 14 Pixel 13 Pixel 12 Pixel 11 Pixel 10 Pixel 9 Pixel 8
+ 0x4
Bit 7 6 5 4 3 2 1 0
8 bits/pixel Palette Buffer Index<7:0>
Bit 31 24 23 16 15 8 7 0
Base
Pixel 3 Pixel 2 Pixel 1 Pixel 0
+ 0x0
Base
Pixel 7 Pixel 6 Pixel 5 Pixel 4
+ 0x4
Figure 7-10. 16 Bits Per Pixel Data Memory Organization - Passive Mode
)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Raw Pixel Data<15:0>
16 bits/pixel
Red Data<4:0> Green Data<5:0> Blue Data<4:0>
Bit 31 16 15 0
Base +
Pixel 1 Pixel 0
0x0
Base +
Pixel 3 Pixel 2
0x4
Note: For passive 16 bits per pixel operation, the Raw Pixel Data must be organized as shown above.
Figure 7-11. 16 Bits Per Pixel Data Memory Organization - Active Mode
)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
16 bits/pixel Raw Pixel Data<15:0>
Bit 31 16 15 0
Base +
Pixel 1 Pixel 0
0x0
Base +
Pixel 3 Pixel 2
0x4
Note: For active 16 bits per pixel operation, the Raw Pixel Data is sent directly to the LCD panel pins and
must be in the same format as required by the LCD panel.
In dual-panel mode, pixels are presented to two halves of the screen at the same time (upper and
lower). A second DMA channel, input FIFO, and output FIFO exist to support dual-panel
operation. The palette buffer is implemented in DMA channel 0, but not channel 1. The frame
source address for the lower half always points to the top of the encoded pixel values for channel 1.
The frame source address of both DMA channels must be configured such that the least significant
three address bits are all zero (address bits 2 through 0 must be zero). This requires that the source
address of the frame buffer start at 8-byte boundaries.
Each line in the frame buffer must start at a word boundary. For the various pixel sizes, this
requires each line of the display to have pixels in multiples of: 32 pixels for 1-bit pixels, 16 pixels
for 2-bit pixels, 8 pixels for 4-bit pixels, 4 pixels for 8-bit pixels, and 2 pixels for 16-bit pixels. If
the LCD screen does not naturally have the correct multiple of pixels per line, the user must adjust
the start address for each line by adding dummy pixel values to the end of the previous line.
Note: There are two special conditions: 8 bits/pixel monochrome screens with double-pixel-data mode
and 8 or 16 bits/pixel passive color screens require a multiple of 8 pixels for each line.
For example, if the screen being driven is 107 pixels wide, and 4 bits/pixel mode is used, each line
is 107 pixels or nibbles in length (53.5 bytes). The next nearest 8-pixel boundary (for 4-bit pixels)
occurs at 112 pixels or nibbles (56 bytes). Each new line in the frame buffer must start at multiples
of 56 bytes by adding an extra 5 dummy pixels per line (2.5 bytes) to LCCR1[PPL].
If dummy pixels are to be inserted, the panel must ignore the extra pixel clocks at the end of each
line that correspond to the dummy pixels.
Use the following equation to calculate the total size of the frame buffer (in bytes). This calculation
is used to encode the length of the frame buffer in the DMA descriptors (Section 7.6.5.4). The first
term is the size required for the encoded pixel values. “Lines” is the number of lines for the display.
“Pixels” is the number of pixels per line. Use the actual line/pixel count, not minus 1 as in the
LCCR registers. “n” = the number of extra dummy pixels required per line, as described above. For
dual-panel mode, the frame buffer size is equally distributed between the two DMA channels.
Therefore, “Lines” in this equation are divided in half for dual-panel mode.
• Lines • ( Pixels + n )
FrameBufferSize = BitsPerPixel
-------------------------------------------------------------------------
-
8
The bandwidth required for the LCD Controller can be calculated using the following equations.
FrameBufferSize is the result of the previous equation. Bandwidth is always an important part of
any system analysis. Systems with large panels and high bits per pixel must ensure that the panel is
not starved for data.
Sample calculations for an 640x480 panel, 16 bits per pixel, 60 Hz refresh rate:
ENB set to 1
L_FCLK VSP = 0
VSW = 1 HSW = 1
L_LCLK
HSP = 0
BLW = 0 ELW = 0
L_PCLK
PCP = 1
PPL = 319
LDD[3:0] Line 0 Data Line 1 Data Line 2 Data
L_FCLK VSP = 0
VSW = 2
HSW = 1
L_LCLK
HSP = 0
ELW = 0 BLW = 0
L_PCLK
PCP = 1
PPL = 319
LDD[3:0] Line 239 Data Line 0 Data
LPP = 239
For PCP = 0 the L_PCLK waveform is inverted, but the timing is identical.
Figure 7-14. Passive Mode Pixel Clock and Data Pin Timing
L_FCLK
L_LCLK
PCP = 0
L_PCLK
ENB set to 1
VSW = 0
L_FCLK VSP = 0
(VSYNC)
HSW = 1 BFW = 1
L_LCLK
HSP = 0
(HSYNC)
L_BIAS
(OE)
BLW = 0 ELW = 0
L_PCLK
PCP = 0
PPL = 7
LDD[15:0] Line 0 Data Line 1 Data Line 2 Data
For PCP = 1 the L_PCLK waveform is inverted, but the timing is identical.
Figure 7-16. Active Mode Pixel Clock and Data Pin Timing
L_FCLK
(VSYNC)
L_LCLK
(HSYNC)
L_BIAS
(OE)
PCP = 0
L_PCLK
An additional control field exists to tune the DMAC’s performance based on the type of memory
system with which the processor is used. This field controls the placement of a minimum delay
between each LCD DMA request during palette loads to insure enough bus bandwidth is given to
other bus masters for accesses.
The DMA descriptor addresses are initially programmed by software. After that, the other DMA
registers are programmed by the hardware. Section 7.6.5 provides a complete description of how
the DMA is programmed.
Each of these hardware-detected events can signal an interrupt request to the interrupt controller.
LCD Output Fifo Underrun Mask (OUM) — used to mask interrupt requests that are asserted
whenever an output FIFO underrun error occurs. When OUM=0, underrun interrupts are enabled,
and whenever an output FIFO underrun (OU) status bit within the LCD status register (LCSR) is
set (one), an interrupt request is made to the interrupt controller. When OUM=1, underrun
interrupts are masked and the state of the underrun status bit (OU) is ignored by the interrupt
controller. Setting OUM does not affect the current state of the status bit or the LCD controller’s
ability to set and clear it, it only blocks the generation of the interrupt request. Output FIFO
underruns are more critical than Input FIFO underruns, since Output FIFO underruns will affect the
display.
Branch Mask (BM) — used to mask interrupt requests that are asserted after the LCD Controller
has branched to a new set of frame descriptors. See Section 7.6.6 for details.
Palette DMA Request Delay (PDD) — used to select the minimum number of internal bus clock
cycles to wait between the servicing of each DMA request issued while the on-chip palette is
loaded. When the palette is optionally loaded at the beginning of a frame, up to 512 bytes of data
may be accessed by the LCD’s DMAC. Using PDD allows other bus masters to gain access to
shared memory in between palette DMA loads. PDD must be used carefully, as it can severely
degrade LCD controller performance if not used properly. It is recommended to leave PDD zero
and add delay only when necessary. PDD does not apply to the normal input FIFO DMA requests
for frame buffer information, since these DMA requests do not occur back-to-back. The input FIFO
DMA request rate is a function of the rate at which pixels are displayed on the screen.
After a word of palette data is written to the input FIFO, the value contained within PDD is loaded
to a down counter that disables the palette from issuing another DMA request until the counter
decrements to zero. This counter ensures that the LCD’s DMAC does not tie up the full bandwidth
of the processor system bus. Once the counter reaches zero, any pending or future DMA requests
by the palette cause the DMAC to arbitrate for the bus. Once the DMA burst cycle has completed,
the process starts over, and the value in PDD is loaded to the counter to create another wait state
period, which disables the palette from issuing a DMA request. PDD can be programmed with a
value that causes the FIFO to wait from 0 to 255 clock cycles after the completion of one DMA
request to the start of the next request. When PDD=0x00, the FIFO DMA request delay function is
disabled.
LCD Quick Disable Interrupt Mask (QDM) — used to mask interrupt requests that are asserted
after the LCD Enable bit (ENB) is cleared and the DMAC finishes the current burst transfer. The
LCD controller immediately stops requesting new data and the current frame is not completed.
This shutdown is for Sleep shutdown. When QDM=0, the quick disable interrupt is enabled, and
whenever the LCD quick disable (QD) status bit in the LCD Status Register (LCSR) is set, an
interrupt request is made to the interrupt controller. When QDM=1, the quick disable interrupt is
masked and the state of the QD status bit is ignored by the interrupt controller. Setting QDM does
not affect the current state of QD or the LCD controller’s ability to set and clear QD, it only blocks
the generation of the interrupt request.
LCD Disable (DIS) — During LCD Controller operation, setting DIS=1 causes the LCD
Controller to finish fetching the current frame from memory and then shut down cleanly. If the
LCD DMAC is loading the palette RAM when DIS is set, the load will complete followed by the
next frame, and then the LCD controller is disabled. Completion of the current frame is signalled
by the LCD when it sets the LCD disable done flag (LDD) in register LCSR. Use a read-modify-
write procedure to set this bit, since the other bit fields within LCCR0 continue to be used until the
current frame is completed. The LCD Enable bit (ENB) is cleared when the disable is completed.
Section 7.2.2 for more information.
Double-Pixel Data (DPD) Pin Mode — selects whether four or eight data pins are used for pixel
data output to the LCD screen in single-panel monochrome mode. When DPD=0, L_DD[3:0] pins
are used to send 4 pixel values each pixel clock transition. When DPD=1, L_DD[7:0] pins are used
to send 8 pixel values each pixel clock. See Table 7-3 for a comparison of how the LCD’s data pins
are used in each of its display modes.
Note: DPD does not affect dual-panel monochrome mode, any of the color modes, or active mode. Clear
DPD in these modes.
Passive/Active Display Select (PAS) — selects whether the LCD controller operates in passive
(STN) or active (TFT) display control mode. When PAS=0, passive mode is selected. All LCD data
flow operates normally (including the LCD’s dither logic), and all LCD controller pin timing
operates as described in Table 7.5.
When PAS=1, active mode is selected. 1- and 2-bit pixel modes are not supported in active mode.
For 4- and 8-bit pixel modes, pixel data is transferred via DMA from off-chip memory to the input
FIFO, unpacked, and used to select an entry from the palette, just as in passive mode. However, the
value read from the palette bypasses the LCD controller’s dither logic and is sent directly to the
output FIFO to be driven onto the LCD’s data pins. This 16-bit output to the pins represents 5 bits
of red, 6 bits of green, and 5 bits of blue data. For 16-bit pixel encoding mode, two 16-bit values
are packed into each word in the frame buffer. Each 16-bit value is transferred via DMA from off-
chip memory to the input FIFO. Unlike 4 and 8 bit per pixel modes, the 16-bit value bypasses both
the palette and the dither logic and is placed directly in the output FIFO to be sent to the LCD’s
data pins. Using the 16-bit pixel encoding mode allows a total of 64K colors to be generated.
The 16-bit output from either the palette or frame buffer to the pins can be organized in any fashion
necessary to correctly interface with the LCD panel. Typically, the output is configured into one of
three user-specified RGB color formats: 6 bits of red, 5 bits of green, and 5 bits of blue data; 5 bits
of red, 6 bits of green, and 5 bits of blue data; and 5 bits of red, 5 bits of green, and 6 bits of blue
data. The RGB format 5:6:5 is normally used, since the human eye can distinguish more shades of
green than of red or blue.
The LCD pin timing changes when active mode is selected. Timing of each pin is described in
subsequent bit-field sections for both passive and active mode.
The LCD controller can be configured in active color display mode and used with an external DAC
and optionally an external palette to drive a video monitor. Only monitors that implement the RGB
data format can be used. The LCD controller does not support the NTSC standard. However, the
2X pixel clock mode allows the LCD controller to easily interface with an NTSC encoder, such as
the Analog Devices 7171 encoder.
Figure 7-17 shows which bits are sent to the individual LCD data pins for both a frame buffer entry
(for 16-bit/pixel mode) and a selected palette entry (for 1, 2, 4 and 8 bit/pixel mode). The pixel bits
corresponding to L_DD pins when using an RGB format of 5:6:5 are also shown. In active mode,
L_DD pins [15:8] are also used. The user must configure the proper GPIO pins for LCD operation
to enable LCD Controller operation. See Chapter 4, “System Integration Unit” for GPIO
configuration information.
The processor LCD controller may be used with active panels having more than 16 data pins, but
the panel will be limited to a total of 64K colors. There are three options:
1. To maintain the panel’s full range of colors and increase the granularity of the spectrum,
connect the LCD controller’s 16 data pins to the panel’s most significant R, G, and B pixel data
input pins and tie the panel’s least significant R, G, and B data pins either high or low.
2. To maintain the granularity of the spectrum and limit the overall range of colors possible,
connect the LCD controller’s 16 data pins to the panel’s least significant R, G, and B pixel data
input pins and tie the panel’s most significant data pins either high or low.
3. Sometimes, better results can be obtained by replicating the upper bits on the lower bits.
Figure 7-17. Frame Buffer/Palette Output to LCD Data Pins in Active Mode
4/8/16 Bits/Pixel Mode, Frame Buffer or Palette Entry
PIxel R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
L_DD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Pin
End of Frame Mask (EFM) — used to mask interrupt requests that are asserted at the end of each
frame (when the DMA length of transfer counter decrements to zero). When EFM=0, the interrupt
is enabled, and whenever the EOF status bit in the LCD status register (LCSR) is set to one, an
interrupt request is made to the interrupt controller. When EFM=1, the interrupt is masked, and the
state of the EOF status bit is ignored by the interrupt controller. Setting EFM does not affect the
current state of EOF or the LCD controller’s ability to set and clear EOF, it only blocks the
generation of the interrupt request.
Input Fifo Underrun Mask (IUM) — used to mask interrupt requests that are asserted whenever
an input FIFO underrun error occurs. When IUM=0, underrun interrupts are enabled, and whenever
an input FIFO underrun (IUL, IUU) status bit in the LCD status register (LCSR) is set to one, an
interrupt request is made to the interrupt controller. When IUM=1, underrun interrupts are masked
and the state of the underrun status bits (IUL, IUU) is ignored by the interrupt controller. Setting
IUM does not affect the current state of these status bits or the LCD controller’s ability to set and
clear them, it only blocks the generation of the interrupt requests.
Start Of Frame Mask (SFM) — used to mask interrupt requests that are asserted at the beginning
of each frame when the LCD’s frame descriptor has been loaded into the internal DMA registers.
When SFM=0, the interrupt is enabled, and whenever the start of frame (SOF) status bit in the LCD
status register (LCSR) is set, an interrupt request is made to the interrupt controller. When SFM=1,
the interrupt is masked and the state of the SOF status bit is ignored by the interrupt controller.
Setting SFM does not affect the current state of SOF or the LCD controller’s ability to set and clear
SOF, it only blocks the generation of the interrupt request.
LCD Disable Done Interrupt Mask (LDM) — used to mask interrupt requests that are asserted
after the LCD is disabled and the frame currently being sent to the output pins has completed.
When LDM=0, the interrupt is not masked, and whenever the LCD disable done (LDD) status bit
in the LCD status register (LCSR) is set to one, an interrupt request is made to the interrupt
controller. When LDM=1, the interrupt is masked, and the state of the LDD status bit is ignored by
the interrupt controller. Setting LDM does not affect the current state of LDD or the LCD
controller’s ability to set and clear LDD, it only blocks the generation of the interrupt request. This
interrupt is used when the LCD must be disabled after the current frame being sent to the output
pins has completed. Clearing LCD Enable (ENB) is a quick disable, and LDD is not set.
Note: This mask bit applies only to regular shutdowns using the LCD Disable (DIS) bit.
Single-/Dual-Panel Select (SDS) — In passive mode (PAS=0), SDS is used to select the type of
display control implemented by the LCD screen. When SDS=0, single-panel operation is selected
(pixels presented to screen a line at a time). When SDS=1, dual-panel operation is selected (pixels
presented to screen two lines at a time). Single-panel LCD drivers have one line/row shifter and
driver for pixels and one line pointer. Dual-panel LCD controller drivers have two line/row shifters
(one for the top half of the screen, one for the bottom) and two line pointers (one for the top half of
the screen, one for the bottom).
When dual-panel mode is programmed, both of the LCD controller’s DMA channels are used.
DMA channel 0 is used to load the palette RAM from the frame buffer and to drive the upper half
of the display, and DMA channel 1 drives the lower half. The two channels alternate when fetching
data for both halves of the screen, placing encoded pixel values in the two separate input FIFOs.
When dual-panel operation is enabled, the LCD controller doubles its pin usage. For monochrome
screens, eight pins are used and for color screens, 16 pins are used.
Table 7-3 shows the LCD data pins and GPIO pins used for each mode of operation and the
ordering of pixels delivered to a screen for each mode of operation.
Note: In passive color mode, the data pin ordering switches. Figure 7-18 shows the LCD data pin pixel
ordering.
.
Top L_DD[7:0]
Color Dual Passive
Bottom L_DD[15:8]
Color Single Active Whole L_DD[15:0]
Row n/2 LDD<4> LDD<5> LDD<6> LDD<7> LDD<4> LDD<5> LDD<6> LDD<7> LDD<4>
Row n/2+1 LDD<4> LDD<5> LDD<6> LDD<7> LDD<4> LDD<5> LDD<6> LDD<7> LDD<4>
Color/Monochrome Select (CMS) — selects whether the LCD controller operates in color or
monochrome mode. When CMS=0, color mode is selected. Palette entries are 16 bits wide (5-bits
red, 6-bits green, 5-bits blue), 8 data pins are enabled for single-panel mode, 16 data pins are
enabled for dual-panel mode, and all three dither blocks are used, one each for the red, green, and
blue pixel components. When CMS=1, monochrome mode is selected, palette entries are 8 bits
wide, 4 or 8 data pins are enabled for single-panel mode, 8 data pins are enabled for dual-panel
mode, and the blue dither block is used.
LCD Enable (ENB) — used to enable and quickly disable all LCD controller operation. When
ENB=0, the LCD controller is either disabled or in the process of quickly disabling, and all of the
LCD pins can be used for GPIO. When ENB=1, the LCD controller is enabled.
All other control registers must be initialized before setting ENB. LCCR0 can be programmed last,
and all bit fields can be configured at the same time with a word write to the register. If ENB is
cleared while the LCD controller is enabled, the LCD controller will immediately stop requesting
data from the LCD DMAC, and the current frame will not complete. The LCD controller must not
be re-enabled until the QD status flag is set in register LCSR, indicating the quick disable is
complete. Quick disable is for sleep shutdown. Regular shutdown of the LCD controller at the end
of the frame can be done via the LCD Disable bit, LCCR0[DIS]. There are separate maskable
interrupts for quick disable and regular disable. See Section 7.2.1 for more information.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
OUM
QDM
CMS
LDM
DPD
ENB
EFM
SFM
SDS
PAS
IUM
DIS
BM
reserved PDD
Reset X X X X X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31:22 — reserved
Output FIFO Underrun mask:
21 OUM 0 = FIFO underrun errors generate an interrupt.
1 = FIFO underrun errors do not generate an interrupt.
Branch Mask:
20 BM 0 = Generates an interrupt after branching to a new frame.
1 = Branch Start (BS) condition does not generate an interrupt.
Palette DMA Request Delay:
19:12 PDD Value (0–255) specifies the number of internal bus clocks to wait before requesting another
burst of palette data. The counter starts decrementing when the first word is written to the
input FIFO buffer. PDD = 0x00 disables this function.
LCD Quick Disable Mask:
11 QDM 0 = Generate an interrupt after quick disable.
1 = Quick Disable (QD) status does not generate an interrupt.
LCD Disable:
10 DIS 0 = LCD Controller has not been disabled.
1 = LCD Controller has been disabled, or is in the process of disabling.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
OUM
QDM
CMS
LDM
EFM
SFM
DPD
ENB
SDS
PAS
IUM
DIS
BM
reserved PDD
Reset X X X X X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Beginning-of-Line Pixel Clock Wait Count (BLW) — used to specify the number of dummy
pixel clocks to insert at the beginning of each line or row of pixels. After the line clock for the
previous line has been negated, the value in BLW is used to count the number of pixel clocks to
wait before starting to output the first set of pixels in the next line. BLW generates a wait period
ranging from 1 to 256 pixel clock cycles. BLW must be programmed with the desired number of
pixel clocks minus one. L_PCLK does not toggle during these “dummy” pixel clock cycles in
passive display mode. It does toggle continuously in active display mode.
End-of-Line Pixel Clock Wait Count (ELW) — used to specify the number of “dummy” pixel
clocks to insert at the end of each line or row of pixels before pulsing the line clock pin. Once a
complete line of pixels is transmitted to the LCD driver, the value in ELW is used to count the
number of pixel clocks to wait before pulsing the line clock. ELW generates a wait period ranging
from 1 to 256 pixel clock cycles. ELW must be programmed with the desired number of pixel
clocks minus one. L_PCLK does not toggle during these dummy pixel clock cycles in passive
display mode. It does toggle continuously in active display mode.
Horizontal Sync Pulse Width (HSW) — specifies the pulse width (minus 1) of the line clock in
passive mode or the horizontal synchronization pulse in active mode. L_LCLK is asserted each
time a line is sent to the display and a programmable number of pixel clock wait states have
elapsed. When L_LCLK is asserted, the value in HSW is transferred to a 6-bit down counter, which
decrements at the programmed pixel clock frequency. When the counter reaches zero, L_LCLK is
negated. HSW can be programmed to generate a line clock pulse width ranging from 1 to 64 pixel
clock periods.
The pixel clock does not toggle during the line clock pulse in passive display mode but does toggle
in active display mode. The polarity (active and inactive state) of the line clock pin is programmed
using the horizontal sync polarity (HSP) bit in LCCR3.
HSW must be programmed with the desired number of pixel clocks minus one.
Note: The term “pulse width” refers to the time which L_LCLK is asserted, rather than the time for a
cycle of the line clock to occur.
Pixels Per Line (PPL) — used to specify the number of pixels in each line or row on the screen
(minus one). PPL is a 10-bit value that represents between 1 and 1024 pixels per line. It is
recommended not to exceed 640 pixels. It is used to count the number of pixel clocks that must
occur before the line clock can be asserted. As discussed in Section 7.4.2, pixels per line must be
multiples of: 32 pixels for 1-bit pixels, 16 pixels for 2-bit pixels, 8 pixels for 4-bit pixels, 4 pixels
for 8-bit pixels, and 2 pixels for 16-bit pixels. The two special conditions are: 8-bits/pixel
monochrome screens with double-pixel-data mode and 8 or 16 bits/pixel passive color screens
require a multiple of 8 pixels for each line.
If the display used is not naturally a multiple of the above, “dummy” pixels must be added to each
line to keep the frame buffer aligned in memory. For example, if the display being controlled is 250
pixels wide and the pixel-size is 8-bits, the nearest greater multiple of 8 is 256. Pixels per line must
be set to 255. 6 extra “dummy” pixel values must be added to the end of each line in the frame
buffer. The display being controlled must ignore the dummy pixel clocks at the end of each line.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Beginning-of-Frame Line Clock Wait Count (BFW) — used in active mode (LCCR0[PAS] = 1)
to specify the number of line clocks to insert at the beginning of each frame. The BFW count starts
when the VSYNC signal for the previous frame is negated. The value in BFW is used to count the
number of line clock periods to insert before starting pixel output in the next frame. BFW generates
a wait period ranging from 0 to 255 extra L_LCLK cycles (BFW=0x00 disables the wait count).
L_LCLK does toggle during the generation of the BFW line clock wait periods.
In passive mode, BFW must be set to zero so that no beginning-of-frame wait states are generated.
Use VSW exclusively in passive mode to insert line clock wait states, which allow the LCD
controller’s DMAC to fill the palette and insert additional pixels before the start of the next frame.
End-of-Frame Line Clock Wait Count (EFW) — used in active mode (LCCR0[PAS] = 1) to
specify the number of line clocks to insert at the end of each frame. Once a complete frame of
pixels is transmitted to the LCD display, the value in EFW is used to count the number of line clock
periods to wait. After the count has elapsed, the VSYNC (L_FCLK) signal is pulsed. EFW
generates a wait period ranging from 0 to 255 line clock cycles (EFW = 0x00 disables the EOF
wait count). L_LCLK does not toggle during the generation of the EFW line clock periods.
In passive mode, EFW must be set to zero so that no EOF wait states are generated. Use VSW
exclusively in passive mode to insert line clock wait states, which allow the LCD controller’s
DMAC to fill the palette and insert additional pixels before the start of the next frame.
Vertical Sync Pulse Width (VSW) — used to specify the pulse width of the vertical
synchronization pulse in active mode or to add extra “dummy” line clock wait states between the
end and beginning of frame in passive mode.
In active mode (LCCR0[PAS]=1), L_FCLK is used to generate the vertical sync signal and is
asserted each time the last line or row of pixels for a frame is sent to the display and a
programmable number of line clock wait states as specified by LCCR1[BLW] have elapsed. When
L_FCLK is asserted, the value in VSW is transferred to a 6-bit down counter, which uses the line
clock frequency to decrement. When the counter reaches zero, L_FCLK is negated. VSW can be
programmed to generate a vertical sync pulse width ranging from 1 to 64 line clock periods. VSW
must be programmed with the desired number of line clocks minus one. The polarity (active and
inactive state) of the L_FCLK pin is programmed using the vertical sync polarity (VSP) bit in
LCCR3.
In passive mode (LCCR0[PAS]=0), VSW does not affect the timing of the L_FCLK pin, but rather
can be used to add extra line clock wait states between the end of each frame and the beginning of
the next frame. When the last line clock of a frame is negated, the value in VSW is transferred to a
6-bit down counter that uses the line clock frequency to decrement. When the counter reaches zero,
the next frame begins. VSW can be programmed to generate from 1 to 64 dummy line clock
periods between each frame in passive mode. VSW must be programmed to allow:
• enough wait states to occur between frames such that the LCD’s DMAC is able to fully load
the on-chip palette (if applicable)
• a sufficient number of encoded pixel values to be fetched from the frame buffer, to be
processed by the dither logic and placed in the output FIFO, ready to be sent to the LCD data
pins.
The number of wait states required is system dependent, depending on such factors as:
• palette buffer size (none; 8, 32 or 512 bytes)
• memory system speed (number of wait states, burst speed, number of beats)
• Palette DMA request delay, LCCR0[PDD].
The line clock pin does toggle during the insertion of the line clock wait state periods.
VSW does not affect generation of the frame clock signal in passive mode. Passive LCD displays
require that the frame clock be active on the rising edge of the first line clock pulse of each frame,
with adequate setup and hold time. To meet this requirement, the LCD controller’s frame clock pin
is asserted on the rising edge of the first pixel clock for each frame. The frame clock remains
asserted for the remainder of the first line as pixels are sent to the display. It is then negated on the
rising edge of the first pixel clock of the second line of each frame.
Lines Per Panel (LPP) — specifies the number of lines or rows present on the LCD panel being
controlled. In single-panel mode, it represents the total number of lines for the entire LCD display.
LPP is used to count the correct number of line clocks that must occur before the frame clock can
be pulsed. In dual-panel mode, it represents half the number of lines of the entire LCD display,
which is split into two panels. LPP is a 10-bit value that represents between 1 and 1024 lines per
screen. It must be programmed with the actual height of the display minus one. It is recommended
not to exceed 480 pixels. For portrait mode panels, more than 480 pixels can be used as long as
total pixels do not exceed 480,000. For example, a 480x640 portrait mode panel can be used.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Double Pixel Clock (DPC) — doubles the rate of the pixel clock on the L_PCLK pin. This allows
direct connection to an NTSC encoder (e.g., the Analog Devices 7171). All of the LCD controller
settings are still specified in terms of the “original” pixel clock and this mode affects only the
L_PCLK output pin. If DPC is set to 1, the pixel clock divisor (PCD) must be greater than or equal
to 1.
Bits Per Pixel (BPP) — BPP specifies the size of encoded pixel values in memory. Pixel sizes of
1, 2, 4, and 8 bits require that the internal palette RAM be loaded before pixels can be displayed on
the screen. See Section 7.6.5 for details on programming the DMAC to load the palette RAM. BPP
is programmed as follows:
0b000 = 1-bit pixels
0b001 = 2-bit pixels
0b010 = 4-bit pixels
Output Enable Polarity (OEP) — In active display mode (LCCR0[PAS] = 1), the OEP bit
selects the active and inactive states of the output enable signal (L_BIAS). In this mode, the AC
bias pin serves as an enable that signals the off-chip device when data is actively being driven
using the pixel clock, which continuously toggles in active mode. When OEP = 0, L_BIAS is
active high and inactive low. When OEP = 1, L_BIAS is active low and inactive high. When
L_BIAS is in its active state, data is driven onto the LCD data pins on the programmed edge of the
pixel clock.
Pixel Clock Polarity (PCP) — selects the edge of the pixel clock (L_PCLK) on which data is
sampled at the LCD pins. When PCP = 0, sampling occurs on the rising edge of L_PCLK. When
PCP = 1, sampling occurs on the falling edge. PCP does not affect the timing of data being driven,
it simply inverts L_PCLK.
Horizontal Sync Polarity (HSP) — selects the active and inactive states of the L_LCLK pin.
When HSP = 0, L_LCLK is active high and inactive low. When HSP = 1, it is active low and
inactive high. In active display mode, L_LCLK serves as the horizontal sync signal and in passive
display mode, it is the line clock.
In both active and passive display modes, the L_FCLK pin is forced to its inactive state whenever
pixels are transmitted. After the end of each line and a programmable number of pixel clocks occur
(controlled by LCCR1[ELW]), the L_FCLK pin is forced to its active state for a programmable
number of line clocks (controlled by LCCR1[HSW]), and is then again forced to its inactive state.
Vertical Sync Polarity (VSP) — selects the active and inactive states of the L_FCLK pin. When
VSP = 0, L_FCLK is active high and inactive low. When VSP = 1, L_FCLK is active low and
inactive high.
In active display mode (LCCR0[PAS] = 1), L_FCLK serves as the vertical sync signal. It is forced
to its inactive state while pixels are transmitted during the frame. After the end of the frame and a
programmable number of line clocks occur (controlled by LCCR2[EFW]), it is forced to its active
state for a programmable number of line clocks (controlled by LCCR2[VSW]), and is then again
forced to its inactive state.
In passive display mode, L_FCLK serves as the frame clock. It is forced to its active state on the
rising edge of the first pixel clock of each frame. It remains active during the transmission of the
entire first line of pixels in the frame and is then forced back to its inactive state on the rising edge
of the first pixel clock of the second line of the frame. It remains at this state through the end of the
frame.
AC Bias Pin Transitions Per Interrupt (API) — specifies the number of AC bias pin (L_BIAS)
transitions to count before setting the AC bias count status (ACS) bit in the LCD Controller Status
Register (LCSR), which signals an interrupt request. After the LCD controller is enabled, the value
in API is loaded to a 4-bit down counter, and the counter decrements each time L_BIAS is inverted.
When the counter reaches zero, it stops, and the AC bias count bit, LCSR[ABC], is set. Once ABC
is set, the 4-bit down counter is reloaded with the value in API and is disabled until ABC is cleared.
When ABC is cleared by the CPU, the down counter is enabled and again decrements each time the
AC bias pin is inverted. The number of AC bias pin transitions between each interrupt request
ranges from 1 to 15. Setting API to 0x0 disables the API function.
In active display mode (LCCR0[PAS] = 1), L_BIAS is the output enable signal. However,
signalling of the API interrupt may still occur. The ACB bit field can be used to count line clock
pulses in active mode. When the programmed number of line clock pulses occurs, an internal
signal is toggled that is used to decrement the 4-bit counter used by the API interrupt logic. Once
this internal signal toggles the programmed number of times, as specified by API, an interrupt is
generated. The user must program API to zero if the API interrupt function is not required in active
mode.
AC Bias Pin Frequency (ACB) — In passive display mode (LCCR0[PAS] = 1), the 8-bit ACB
field specifies the number of line clocks to count between each toggle of the AC bias pin
(L_BIAS). After the LCD controller is enabled, the value in ACB is loaded to an 8-bit down
counter, which begins to decrement using the line clock (L_LCLK). When the counter reaches
zero, it stops, L_BIAS is toggled, and the whole procedure starts again. The number of line clocks
between each bias pin transition ranges from 1 to 256, corresponding to ACB values from 0 to 255.
Thus, the value to program into ACB is the desired number of line clocks minus 1.
AC bias is used by a passive LCD display to periodically reverse the polarity of the power supplied
to the screen in order to eliminate D.C. offset. If the LCD display being controlled has its own
internal means of switching its power supply, set ACB to its maximum value (0xFF) to reduce
power consumption. ACB must be programmed conservatively in a system with bandwidth
problems that result in output FIFO underruns in the LCD Controller. In these cases, the pixel clock
is stalled for passive displays, which can result in more time between line clocks than expected.
See Section 7.3.5 for more information on how output FIFO underruns are handled.
In active display mode, the ACB bit field has no effect on the L_BIAS pin. Because the pixel
clock toggles continuously in active mode, the AC bias pin is used as an output enable signal. It is
asserted automatically by the LCD controller in active mode whenever pixel data is driven out to
the data pins to signal the display when it may latch pixels using the pixel clock. ACB can be used
in active mode to count line clocks and generate API interrupts.
Pixel Clock Divider (PCD) — selects the frequency of the pixel clock (L_CLK). PCD can be any
value from 0 to 255. It generates a range of pixel clock frequencies from LCLK/2 to LCLK/512,
where LCLK is the programmed frequency of the LCD/Memory Controller clock. LCLK can vary
from 100MHz to 166 MHz.
The pixel clock frequency must be adjusted to meet the required screen refresh rate, which depends
on:
• number of pixels for the target display
• number of panels (single or dual)
• display type (monochrome or color)
• number of pixel clock wait states programmed at the beginning and end of each line
• number of line clocks inserted at the beginning and end of each frame
• width of the VSYNC signal in active mode or VSW line clocks inserted in passive mode
• width of the frame clock or HSYNC signal.
All of these factors alter the time duration from one frame transmission to the next. Different
display manufacturers require different frame refresh rates, depending on the physical
characteristics of the display. PCD is used to alter the pixel clock frequency in order to meet these
requirements. The frequency of the pixel clock for a set PCD value or the required PCD value to
yield a target pixel clock frequency can be calculated using the two following equations. If double
pixel clock mode (DPC) is enabled, PCD must be set greater than or equal to 1.
LCLK
PixelClock = ------------------------------
2 ( PCD + 1 )
LCLK
PCD = ------------------------------------- – 1
2 ( PixelClock )
where
LCLK = LCD/Memory Clock
PCD = LCCR3[7:0]
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPC
OEP
PCP
HSP
VSP
Reset X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31:28 - reserved
Double Pixel Clock mode:
27 DPC 0 = The L_PCLK pin is driven at the frequency specified by PCD.
1 = The L_PCLK pin is driven at double the frequency specified by PCD.
Bits Per Pixel:
000 – 1-bits/pixel [4 entry, 8 byte palette buffer (only first 2 entries are used)]
001 – 2-bits/pixel [4 entry, 8 byte palette buffer]
26:24 BPP 010 – 4-bits/pixel [16 entry, 32 byte palette buffer]
011 – 8-bits/pixel [256 entry, 512 byte palette buffer]
100 – 16-bits/pixel [no palette buffer]
101, 110, 111 – reserved
Output Enable Polarity:
0 = L_BIAS pin is active high and inactive low in active display mode.
23 OEP 1 = L_BIAS pin is active low and inactive high in active display mode.
In active display mode, data is driven out to the LCD’s data pins on the programmed pixel
clock edge when the L_BIAS pin is active. OEP is ignored in passive display mode.
Pixel Clock Polarity:
22 PCP 0 = Data is sampled on the LCD data pins on the rising edge of L_PCLK.
1 = Data is sampled on the LCD data pins on the falling edge of L_PCLK.
Horizontal Sync Polarity:
21 HSP 0 = L_LCLK pin is active high and inactive low.
1 = L_LCLK pin is active low and inactive high.
Vertical Sync Polarity:
20 VSP 0 = L_FCLK pin is active high and inactive low.
1 = L_FCLK pin is active low and inactive high.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OEP
DPC
PCP
HSP
VSP
reserved BPP API ACB PCD
Reset X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The address in FDADRx is not used when the BRA bit in the Frame Branch Register (FBRx) is set.
In this case, the Frame Branch Address is used to fetch the descriptor for the next frame. Branches
can be used to load a new palette or to process a regular frame, as detailed in Section 7.6.6.
Note: If only one frame buffer is used in external memory, the FDADRx field (word[0] of the frame
descriptor) must point back to itself.
These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Descriptor Address
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
These read-only registers are loaded indirectly via the frame descriptors, as described in
Section 7.6.5.1.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
These read-only registers are loaded indirectly via the frame descriptors, as described in
Section 7.6.5.1.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Frame ID reserved
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? X X X
These read-only registers are loaded indirectly via the frame descriptors, as described in
Section 7.6.5.1.
Load Palette (PAL) — indicates that data being fetched will be loaded into the palette RAM. If
PAL is set to one, the palette RAM is loaded with the first 8, 32, or 512-bytes of data as follows:
8 bytes for 1 and 2-bit pixels
32 bytes for 4-bit pixels
512 bytes for 8-bit pixels.
Software must load the palette at least once after enabling the LCD. Otherwise, the palette entries
will not be initialized, and the frame data will not have a valid frame palette to reference.
The palette must not be loaded if the LCD is operating in 16-bit pixel mode.
Note: The PAL bit must never be set in LDCMD1, since the palette is always loaded with Channel 0.
Start Of Frame Interrupt (SOFINT) — when set, the DMAC sets the start of frame bit
(LCSR[SOF]) when starting a new frame. The SOF bit is set after a new descriptor is loaded from
memory and before the palette/frame data is fetched.
In dual-panel mode, LCSR[SOF] is set only when both channels reach the start of frame and both
frame descriptors have SOFINT set. SOFINT must not be set for palette descriptors in dual-panel
mode, since only one channel is ever used to load the palette RAM.
End Of Frame Interrupt (EOFINT) — when set, the DMAC sets the end of frame bit
(LCSR[EOF]) after fetching the last word in the frame buffer.
In dual-panel mode, LCSR[EOF] is set only when both channels reach the end of frame and both
frame descriptors have EOFINT set. EOFINT must not be set for palette descriptors in dual-panel
mode, since only one channel is ever used to load the palette RAM.
Transfer Length (LEN) — determines the number of bytes fetched by the DMAC. LEN = 0 is not
valid. If PAL is set to one, LEN must be programmed with the size of the palette RAM. This
corresponds to:
8 bytes for 1 and 2-bit pixels (only the top 2 entries are actually used for 1-bit pixels)
32 bytes for 4-bit pixels
512 bytes for 8-bit pixels.
The value of LEN for frame data is a function of the screen size and the pixel size and it must be
consistent with the values used for LCCR1[PPL], LCCR2[LPP], and LCCR3[BPP]. See
Section 7.4.2 for instructions on calculating length. The LCD DMAC decrements LEN as it fetches
data, allowing the user to read the number of bytes remaining for the current descriptor.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOFINT
EOFINT
PAL
Reset X X X X X 0 X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31:27 — reserved
Load Palette:
0 = DMA in progress is not the palette buffer.
26 PAL
1 = DMA in progress is the palette buffer.
PAL must not be set in LDCMD1.
25:23 — reserved
Start of Frame Interrupt:
22 SOFINT 0 = Do not set the SOF interrupt bit in the LCD status register when starting a new frame.
1 = Set the start of frame (SOF) interrupt bit in the LCD status register when starting a new
frame (after loading the frame descriptor).
End of Frame Interrupt:
0 = Do not set the EOF interrupt bit in the LCD status register when finished fetching the
21 EOFINT last word of this frame.
1 = Set the end of frame (EOF) interrupt bit in the LCD status register when finished
fetching the last word of this frame.
Length of transfer in bytes:
The two lowest bits [1:0] are part of the length calculation but must always be zero for
20:0 LEN
proper memory alignment.
LEN = 0 is illegal.
When BRA is set, the Frame Descriptor Address Register is ignored. The next descriptor is fetched
from the address in FBRx[31:4], regardless of whether frame data or palette RAM data is being
processed. Setting BINT to one forces the DMAC to set the Branch Status interrupt bit (BS) in the
LCD Controller Status Register after fetching the branched-to descriptor. BRA is automatically
cleared by hardware when the branch is taken.
Note: In dual-panel mode, both FBR0 and FBR1 must be written in order to branch properly.
These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
BINT
BRA
Frame Branch Address
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X 0 0
3:2 — reserved
Branch Interrupt:
1 BINT 0 = Do not set the BS interrupt bit in register LCSR after the branched-to descriptor is
loaded.
1 = Set the BS interrupt bit in register LCSR after the branched-to descriptor is loaded.
Branch:
0 BRA 0 = Do not branch after finishing the current frame.
1 = Branch after finishing the current frame. The next descriptor will be fetched from the
Frame Branch Address. BRA is automatically cleared after loading the new descriptor.
Unless masked, each of these hardware-detected events signals an interrupt request to the interrupt
controller. Two bits, BER and ABC, generate nonmaskable interrupts.
Each of the LCD’s status bits continues to signal an interrupt request for as long as the bit is set.
Once the bit is cleared, the interrupt is cleared. Status bits are referred to as sticky (once set by
hardware, they must be cleared by software). Writing one to a sticky status bit clears it. Writing
zero has no effect. All LCD interrupts can be masked by programming the Interrupt Controller
Mask Register (ICMR). See Section 4.2, “Interrupt Controller” on page 4-20 for more details.
Subsequent Interrupt Status (SINT) — set when an unmasked interrupt occurs and there is
already a pending interrupt. The frame ID of the first interrupt is saved in the LCD controller
interrupt ID register (LIIDR). SINT is set only for bus error, start of frame, end of frame, and
branch status interrupts.
Note: If a branched-to descriptor has SOF set, both the SOF and branch interrupts are signalled at the
same time, and SINT is not set.
Branch Status (BS) — set after the DMA controller has branched and loaded the descriptor from
the frame branch address in the frame branch register, and the branch interrupt (BINT) bit in the
frame branch register is set. When BS is set, an interrupt request is made to the interrupt controller
if it is unmasked (LCCR0[BM] = 0).
In dual-panel mode (LCCR0[SDS = 1]), both DMA channels are enabled, and BS is set only after
both channels’ frames have been fetched. BS remains set until cleared by software.
End Of Frame Status (EOF) — set after the DMA controller has finished fetching a frame from
memory and that frame’s descriptor has the end-of-frame interrupt bit set (LDCMDx[EOFINT] =
1). When EOF is set, an interrupt request is made to the interrupt controller if it is unmasked
(LCCR0[EFM] = 0).
When dual-panel mode is enabled (LCCR0[SDS] = 1), both DMA channels are enabled, and SOF
is set only after both channels’ frames have been fetched. EOF remains set until cleared by
software.
LCD Quick Disable Status (QD) — set when LCD Enable (LCCR0[ENB]) is cleared and the
DMA controller finishes any current data burst. When QD is set, an interrupt request is made to the
interrupt controller if it is unmasked (LCCR0[QDM] = 0). This forces the LCD controller to stop
immediately and quit driving the LCD pins. Quick disable is intended for use with Sleep shutdown.
Output FIFO Underrun Status (OU) — set when an output FIFO is completely empty and the
LCD’s data pin driver logic attempts to fetch data from the FIFO. It is cleared by writing one to the
bit. OU is used for single- and dual-panel displays. In dual-panel mode (LCCR0[SDS] = 1), both
FIFOs are filled and emptied at the same time, so that underrun occurs at the same time for both
panels. When OU is set, an interrupt request is made to the interrupt controller if it is unmasked
(LCCR0[OUM] = 0). Output FIFO underruns are more important that Input FIFO underruns,
because they affect the panel.
Input FIFO Underrun Upper Panel Status (IUU) — set when the upper panel’s input FIFO is
completely empty and the LCD controller’s pixel unpacking logic attempts to fetch data from the
FIFO. It is cleared by writing one to the bit. IUU is used in both single-panel (LCCR0[SDS] = 0)
and dual-panel (SDS = 1) modes. When IUU is set, an interrupt request is made to the interrupt
controller if it is unmasked (LCCR0[IUM] = 0).
Input FIFO Underrun Lower Panel Status (IUL) — used only in dual-panel mode
(LCCR0[SDS] = 1) and is set when the lower panel’s input FIFO is completely empty and the LCD
controller’s pixel unpacking logic attempts to fetch data from the FIFO. It is cleared by writing one
to the bit. When IUL is set, an interrupt request is made to the interrupt controller if it is unmasked
(LCCR0[IUM]=0).
AC Bias Count Status (ABC) — set each time the AC bias pin (L_BIAS) toggles the number of
times specified in the AC bias pin transitions per interrupt (API) field in LCCR3. If API is
programmed with a non-zero value, a counter is loaded with the value in API and is decremented
each time L_BIAS toggles. When the counter reaches zero, ABC is set, which signals an interrupt
request to the interrupt controller. The counter reloads using the value in API but does not start to
decrement again until ABC is cleared by software.
Bus Error Status (BER) — set when a DMA transfer causes a system bus error. The error is
signalled when the DMA controller attempts to access a reserved or nonexistent memory space.
When this occurs, the DMA controller stops and remains halted until software installs a valid
memory address into the FDADRx register. In dual-channel mode, both channels are stopped.
FDADR0 and FDADR1 must be rewritten to continue LCD operation. BER remains set until
cleared by software.
Start Of Frame Status (SOF) — set after the DMA controller has loaded a new descriptor and
that descriptor has the start of frame interrupt bit set (LDCMDx[SOFINT] = 1). When SOF is set,
an interrupt request is made to the interrupt controller if it is unmasked (LCCR0[SFM] = 0). In
dual-panel mode (LCCR0[SDS] = 1), both DMA channels are enabled, and SOF is set only after
both channels’ descriptors have been loaded. SOF remains set until cleared by software.
LCD Disable Done Status (LDD) — set by hardware after the LCD has been disabled and the
frame that is active has been sent to the LCD data pins. When the LCD controller is disabled by
setting the LCD disable bit in LCCR0, the current frame is completed before the controller is
disabled. After the last set of pixels is clocked out onto the LCD data pins by the pixel clock, the
LCD controller is disabled, LDD is set, and an interrupt request is made to the interrupt controller
if it is unmasked (LCCR0[LDM] = 0). LDD remains set until cleared by software.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SINT
ABC
BER
EOF
SOF
LDD
IUU
IUL
QD
OU
BS
reserved
Reset X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0
31:11 — reserved
Subsequent Interrupt status, maskable interrupt:
0 = A second unmasked branch, start of frame, end of frame, or bus error interrupt has
10 SINT NOT occurred before a previous interrupt has completed.
1 = A second unmasked branch, start of frame, end of frame, or bus error interrupt has
occurred before the previous interrupt has been cleared. The value in the Interrupt
Frame ID Register is not replaced with the value from the second interrupt.
Branch Status, maskable interrupt:
0 = The DMA has not loaded a branched-to descriptor, or the DMA has loaded a
9 BS branched-to descriptor, but the branch interrupt (BINT) bit is not set in the Frame
Branch Register.
1 = The DMA has loaded a branched-to descriptor, and the BINT bit is set.
End Of Frame status, maskable interrupt:
8 EOF 0 = A new frame with the EOFINT bit set in its descriptor has not been processed.
1 = The DMA has finished fetching a frame with the EOFINT bit set in its descriptor.
LCD Quick Disable status, maskable interrupt:
7 QD 0 = LCD has not been quickly disabled by clearing LCCCR0[ENB].
1 = LCD has been quickly disabled.
Output FIFO Underrun status, maskable interrupt:
6 OU 0 = Output FIFOs have not underrun.
1 = LCD dither logic is not supplying data to output FIFOs for the panel at a sufficient rate.
The output FIFOs have completely emptied.
Input FIFO Underrun Upper panel status, maskable interrupt:
0 = The input FIFO for the upper (dual-panel mode) or whole panel (single-panel mode)
5 IUU display has not underrun.
1 = DMA is not supplying data to the input FIFO for the upper or whole panel at a sufficient
rate. The FIFO has completely emptied, and the pixel unpacking logic has attempted
to take data from the FIFO.
Input FIFO Underrun Lower panel status, dual-panel mode only, maskable interrupt:
0 = The input FIFO for the lower panel display has not underrun.
4 IUL 1 = DMA is not supplying data to the input FIFO for the lower panel at a sufficient rate. The
FIFO has completely emptied, and the pixel unpacking logic has attempted to take
data from the FIFO.
AC Bias Count status, nonmaskable interrupt:
0 = The AC bias transition counter has not decremented to zero.
3 ABC 1 = The AC bias transition counter has decremented to zero, indicating that the L_BIAS
pin has toggled the number of times specified by the LCCR3[API] control-bit field. The
counter is reloaded with the value in API but is disabled until the user clears ABC.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SINT
ABC
BER
EOF
SOF
LDD
IUU
IUL
QD
OU
BS
reserved
Reset X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IFRAMEID reserved
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? X X X
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
For more details on the effects of the individual fields within this register, please refer to
Section 7.3.3.
TMED Energy Distribution Select (TED) — selects which matrix is used in the final step of
TMED algorithm. TMED = 1 selects the (preferred) TMED2 matrix. TMED = 0 selects the older
TMED matrix. After the pixel value has gone through the algorithm to determine a lower and upper
boundary, the row and column counters are combined and run through one of the matrices to obtain
a number that will be compared to the 2 boundaries. If that number is between the 2 boundaries,
then the data out for this pixel in this frame is a 1, otherwise it is a 0.
TMED Horizontal Beat Suppression (THBS) — is the column shift value used as an offset that
is combined with the row (line) counter and the pixel counter to create an address to lookup in the
matrix. The matrix output is compared to the upper and lower boundaries defined in Section 7.3.3.
TMED Vertical Beat Suppression (TVBS) — is the block shift value used as an offset that is
combined with the pixel counter.
TMED Frame Number Adjuster Enable (FNAME) — allows the frame number adjuster to add
an offset to the current frame number before the value is sent through the algorithm. Setting this bit
enables the addition of the current frame number to a value composed from the row and column
counters. This value comes from one of the two look up matrices which is selected by
TMED[FNAM].
TMED Color Offset Adjuster Enable (COAE) — enables the color offset adjuster for each color.
The color offset adjuster creates the offset in the lower boundary in the TMED algorithm (refer to
Section 7.3.3). The Offset is created by adding either the output of the lookup matrix (input was the
Color Value) or‘00’ to the Seed value in the TSR for that color. The color offset adjuster for each
color can be disabled by clearing this bit. When cleared, this bit allows only the Seed Register
value to go through the algorithm.
TMED Frame Number Adjuster Matrix (FNAM) — selects which matrix is used when using
the frame number adjuster. A 1 will select the (recommended) TMED2 matrix, and a 0 will select
the older TMED matrix.
TMED Color Offset Adjuster Matrix (COAM) — selects which matrix is used when using the
color offset adjuster. A 1 will select the (recommended) TMED2 matrix, and a 0 will select the
older TMED matrix.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
FNAME
COAM
COAE
FNAM
TED
reserved THBS TVBS
Reset X X X X X X X X X X X X X X X X X 1 1 1 0 1 0 1 0 1 0 0 1 1 1 1
31:15 — reserved
TMED Energy Distribution Matrix Select
14 TED 0 = Selects Matrix 1
1 = Selects Matrix 2
13:12 — reserved
TMED Horizontal Beat Suppression
11:8 THBS
Specifies the column shift value.
TMED Vertical Beat Suppression
7:4 TVBS
Specifies the block shift value.
TMED Frame Number Adjuster Enable
3 FNAME 0 = Disable frame number adjuster.
1 = Enable frame number adjuster.
TMED Color Offset Adjuster Enable
2 COAE 0 = Disable color offset adjuster.
1 = Enable color offset adjuster.
TMED Frame Number Adjuster Matrix
1 FNAM 0 = Selects Matrix 1 for frame number adjuster.
1 = Selects Matrix 2 for frame number adjuster.
TMED Color Offset Adjuster Matrix
0 COAM 0 = Selects Matrix 1 for color offset adjuster.
1 = Selects Matrix 2 for color offset adjuster.
8.1 Overview
The SSPC is a full-duplex synchronous serial interface and can connect to a variety of external
analog-to-digital (A/D) converters, audio and telecom codecs, and other devices that use serial
protocols for transferring data. The SSPC supports National’s Microwire* , Texas Instruments’
Synchronous Serial Protocol* (SSP), and Motorola’s Serial Peripheral Interface* (SPI) protocol.
The SSPC operates in master mode (the attached peripheral functions as a slave) and supports
serial bit rates from 7.2 KHz to 1.84 MHz. Serial data formats may range from 4 to 16 bits in
length. The SSPC provides 16 entries deep x 16 bits wide transmit and receive data FIFOs.
The FIFOs may be loaded or emptied by the Central Processor Unit (CPU) using programmed I/O,
or DMA burst transfers of 4 or 8 half-words per transfer while receiving or transmitting.
SSPSCLK is the bit-rate clock driven from the SSPC to the peripheral. SSPSCLK is toggled only
when data is actively being transmitted and received.
SSPSFRM is the framing signal, indicating the beginning and the end of a serialized data word.
SSPTXD and SSPRXD are the Transmit and Receive serial data lines.
SSPEXTCLK is an external clock (input through GPIO27) that replaces the standard 3.6864 MHz
clock used to generate the serial bit-rate clock (SSPSCLK). The external clock is internally divided
by 2 and then further divided by the value in SSCR0[SCR].
If SSP operation is disabled, the five SSP pins are available for GPIO use. See Chapter 4, “System
Integration Unit” for details on configuring pin direction and interrupt capabilities.
Programmed I/O transmits and receives data directly between the CPU and the transmit/receive
FIFO’s. The DMA controller transfers data during transmit and receive operations between
memory and the FIFO’s. DMA programming guidelines are found in Chapter 5, “DMA
Controller”.
As the received data fills the receive FIFO, a programmable threshold triggers an interrupt to the
Interrupt Controller. If enabled, an interrupt service routine responds by identifying the source of
the interrupt and then performs one or several read operations from the inbound (receive) FIFO
buffer.
The SSPC supports three formats: Motorola SPI, Texas Instruments SSP, and National Microwire.
The three formats have significant differences, as described below.
While SSP and SPI are full-duplex protocols, Microwire uses a half-duplex master-slave
messaging protocol. At the start of a frame, a 1 or 2-byte control message is transmitted from the
controller to the peripheral. The peripheral does not send any data. The peripheral interprets the
message and, if it is a READ request, responds with requested data, one clock after the last bit of
the requesting message. Return data (part of the same frame) can be from 4 to 16 bits in length.
Total frame length is 13 to 33 bits.
The serial clock (SSPSCLK) only toggles during an active frame. At other times it is held in an
inactive or idle state, as defined by its specified protocol.
SSPSFRM
...
Bit<N-
SSPTXD Bit<N> ... Bit<1> Bit<0>
1>
Bit<N-
SSPRXD Bit<N> ... Bit<1> Bit<0>
1>
SSPSCLK
... ...
SSPSFRM
... ...
Bit<N- Bit<N-
SSPTX /RX Bit<0> Bit<N> ... Bit<1> Bit<0> Bit<N> ... Bit<1> Bit<0>
1> 1>
Continuous Transfers
In idle mode or when the SSP is disabled, SSPSCLK and SSPTXD are low and SSPSFRM is high.
When transmit (outgoing) data is ready, SSPSFRM goes low and stays low for the remainder of the
frame. The most significant serial data bit is driven onto SSPTXD a half-cycle later, and halfway
into the first bit period SSPSCLK asserts high and continues toggling for the remaining data bits.
Data transitions on the configured SSPSCLK edge. From 4 to 16 bits may be transferred per frame.
When SSPSFRM is asserted, receive data is simultaneously driven from the peripheral on
SSPRXD, most significant bit first. Data transitions on the configured SSPSCLK edge and is
sampled by the controller on opposite edge. At the end of the frame, SSPSFRM is deasserted high
one clock period after the last bit is latched at its destination and the completed incoming word is
shifted into the incoming FIFO. The peripheral can tristate SSPRXD after sending the last bit of the
frame. SSPTXD retains the last value transmitted when the controller goes into idle mode, unless
the SSP port is disabled or reset (which forces SSPTXD to zero).
For back-to-back transfers, start and completion are similar to those of a single transfer but
SSPSFRM does not deassert between words. Both transmitter and receiver know the word length
and internally keep track of the start and end of words (frames). There are no dead bits. One
frame’s least significant bit is followed immediately by the next frame’s most significant bit.
Figure 8-2 shows one of the four configurations for the Motorola SPI frame format for single and
back-to-back frame transmissions.
SSPSFRM
...
Bit<N-
SSPTXD Bit<N> ... Bit<1> Bit<0>
1>
Bit<N-
SSPRXD Bit<N> ... Bit<1> Bit<0>
1>
SSPSCLK
... ...
SSPSFRM
... ...
Bit<N- Bit<N-
SSPTX /RX Bit<0> Bit<N> ... Bit<1> Bit<0> Bit<N> ... Bit<1> Bit<0>
1> 1>
Continuous Transfers
Note: SSPSCLK’s phase and polarity can be configured for four modes. This example shows one of those modes.
Each Microwire transmission begins with SSPSFRM assertion (low), followed by an 8 or 16-bit
command word sent from controller to peripheral on SSPTXD. The command word data size is
selected by the Microwire Transmit Data Size (MWDS) bit in SSP Control Register 1. SSPRXD is
controlled by the peripheral and remains tristated. SSPSCLK goes high midway through the
command’s most significant bit and continues to toggle at the bit rate.
One bit-period after the last command bit, the peripheral must return the serial data requested, most
significant bit first, on SSPRXD. Data transitions on SSPSCLK’s falling edge and is sampled on
the rising edge. SSPSCLK’s last falling edge coincides with the end of the last data bit on SSPRXD
and it remains low if it is the only or last word of the transfer. SSPSFRM deasserts high one-half
clock period later.
The start and end of a series of back-to-back transfers are similar to those of a single transfer.
However, SSPSFRM remains asserted (low) throughout the transfer. The end of a data word on
SSPRXD is immediately followed by the start of the next command byte on SSPTXD.
Figure 8-3 shows the National Microwire frame format with 8-bit command words for single and
back-to-back frame transmissions.
SSPSFRM
... ...
4 to 16 Bits
Single Transfer
SSPSCLK
... ... ...
SSPSFRM
... ... ...
1 Clk 1 Clk
Continuous Transfers
The processor can fill or empty FIFOs in response to an interrupt from the FIFO logic. Each FIFO
has a programmable interrupt threshold. When the threshold value is exceeded and an interrupt is
enabled, an interrupt that signals the CPU to empty the receive FIFO or refill the transmit FIFO is
generated.
The user can also poll the SSP Status Register (see Section 8.7.4) to determine how many samples
are in a FIFO or whether the FIFO is full or empty.
Note: If the transmit/receive byte count is not a multiple of the transfer burst size, the user must check the
SSP Status Register (see Section 8.7.4) to determine if any data remains in the Receive FIFO.
When the registers are programmed, reserved bits must be written as zeros and are read as
undefined.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECS
SSE
FRF
reserved SCR DSS
Reset X 0x00 0 0 0 0
transmit FIFO. The transmit logic in the SSPC left-justifies the data sample according to the DSS
bits before the sample is transmitted. Data sizes of 1, 2, and 3 bits are reserved and produce
unpredictable results in the SSPC.
In National Microwire frame format, this bit field selects the size of the received data. The size of
the transmitted command data is either 8-bit or 16-bit as selected by the MWDS bit in SSCR1.
FRF=11 is reserved and the SSPC produces unpredictable results if this value is used.
If the off-chip clock is used, the user must set the appropriate bits in the GPIO alternate function
and pin direction registers that correspond to the pin. See Chapter 4, “System Integration Unit” for
more details on configuring GPIO pins for alternate functions.
Note: Disable the SSPC by setting the SSPC Enable (SSE) to a 0 before setting the ECS bit to a 1. The
ECS bit may be set to one either before the SSE is set to one or at the same time.
When the SSCR0[SSE] bit is cleared during active operation, the SSP is immediately disabled and
the frame being transmitted is terminated. Clearing SSCR0[SSE] resets the SSP’s FIFOs and the
SSP status bits. The SSP’s control registers are not reset when SSCR0[SSE] is cleared.
Note: After reset or after the SSCR0[SSE] is cleared, ensure that the SSCR1 and SSSR registers are
properly reconfigured or reset before re-enabling the SSP with the SSCR0[SSE]. Other control bits
in SSCR0 may be written at the same time as the SSCR0[SSE].
When the SSPC is disabled, its five pins may be used as GPIOs. They are configured as inputs or
outputs with the control registers described in Chapter 4, “System Integration Unit”. In Sleep
mode, the pins’ states are controlled by the GPIO sleep register. SSPC register settings have no
effect on the pins in Sleep mode.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MWDS
LBM
SPO
SPH
RIE
TIE
reserved RFT TFT
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MWDS
LBM
SPO
SPH
RIE
TIE
reserved RFT TFT
TFT
Sets threshold level at which Transmit FIFO generates an interrupt or DMA request. This
9:6 (Transmit FIFO level must be set to the desired threshold value minus 1.
Threshold)
RFT
Sets threshold level at which Receive FIFO generates an interrupt or DMA request. This
13:10 (Receive FIFO level must be set to the desired threshold value minus 1.
Threshold)
31:14 — reserved
The RIE bit’s state does not affect the receive FIFO DMA request generation that is asserted when
the RFS bit is set to a 1.
The TIE bit’s state does not affect the transmit FIFO DMA request generation that is asserted when
the TFS bit is set to a 1.
Note: Loop back mode cannot be used with Microwire frame format.
Note: The SPO bit is ignored for all data frame formats except for the Motorola SPI format (FRF=00).
The combination of the SPO and SPH settings determines when SSPSCLK is active during the
assertion of SSPSFRM and which SSPSCLK edge is used to transmit and receive data on the
SSPTXD and SSPRXD pins. When SPO and SPH are programmed to the same value, transmit data
is driven on SSPSCLK’s falling edge and receive data is latched on SSPSCLK’s rising edge. When
SPO and SPH are programmed to opposite values (one 0 and the other 1), transmit data is driven on
SSPSCLK’s rising edge and receive data is latched on SSPSCLK’s falling edge.
The SPH is ignored for all data frame formats except the Motorola SPI format (FRF=00).
Figure 8-4 shows the pin timing for the four SPO and SPH programming combinations. SPO
inverts the SSPSCLK signal’s polarity and SPH determines the phase relationship between
SSPSCLK and SSPSFRM, shifting the SSPSCLK signal one-half phase to the left or right during
the SSPSFRM assertion.
Figure 8-4. Motorola SPI* Frame Formats for SPO and SPH Programming
SSPSCLK SPO=0
...
SSPSCLK SPO=1
...
SSPSFRM
...
Figure 8-4. Motorola SPI* Frame Formats for SPO and SPH Programming
Bit<N-
SSPRXD Bit<N> ... Bit<1> Bit<0>
1>
SSPSCLK SPO=0
...
SSPSCLK SPO=1
...
SSPSFRM
...
Bit<N-
SSPTXD Bit<N> ... Bit<1> Bit<0>
1>
Bit<N-
SSPRXD Bit<N> ... Bit<1> Bit<0>
1>
Be careful not to set the RFT value too high for your system or the FIFO could overrun because of
the bus latencies caused by other internal and external peripherals. This is especially the case for
interrupt and polled modes that require a longer time to service.
8 Bytes 0 11 3 15
16 Bytes 0 7 7 15
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
As the system accesses the register, FIFO control logic transfers data automatically between
register and FIFO as fast as the system moves data. The SSP Status Register has bits that indicate
whether either FIFO is full, above/below a programmable threshold, or empty.
For transmit operations from SSPC to SSP peripheral, the CPU (using programmed I/O) may write
to the SSDR when the transmit FIFO is below its threshold level.
When a data size less than 16-bits is selected, do not left-justify data before it is written to the
SSDR. Transmit logic left-justifies the data and ignores any unused bits. Received data less than
16-bits is automatically right-justified in the receive FIFO.
When the SSPC is programmed for National Microwire frame format and the size for transmit data
is 8-bits, as selected by the MWDS bit in the SSCR1, the most significant byte is ignored.
SSCR0[DSS] controls receive data size.
Note: Both FIFOs are cleared when the SSPC is reset or a zero is written to the SSCR0[SSE] bit.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset X 0x0000
15:0 Data
Data word to be written to/read from Transmit/Receive FIFO
(Low Word)
31:16 — reserved
Bits that cause an interrupt will signal the request as long as the bit is set. When the bit is cleared,
the interrupt is cleared. Read/write bits are called status bits, read-only bits are called flags. Status
bits are referred to as sticky (once set by hardware, they must be cleared by software). Writing a 1
to a sticky status bit clears it. Writing a 0 has no effect. Read-only flags are set and cleared by
hardware. Writes have no effect. Some bits that cause interrupts have corresponding mask bits in
the control registers.
All bits are read-only except ROR, which is read/write. ROR’s reset state is zero. Writes to TNF,
RNE, BSY, TFS, and RFS have no effect. Writes to reserved bits are ignored and reads from these
bits are undetermined.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
ROR
RNE
BSY
RFS
TNF
TFS
reserved RFL TFL
1:0 — reserved
Transmit FIFO Not Full (read only)
2 TNF 0 = Transmit FIFO is full
1 = Transmit FIFO is not full
Receive FIFO Not Empty (read only)
3 RNE 0 = Receive FIFO is empty
1 = Receive FIFO is not empty
SSP Busy (read only)
4 BSY 0 = SSP is idle or disabled
1 = SSP currently transmitting or receiving a frame
Transmit FIFO Service Request (read only)
5 TFS 0 = Transmit FIFO level exceeds TFT threshold, or SSP disabled
1 = Transmit FIFO level is at or below TFT threshold, generate interrupt or DMA request
Receive FIFO Service Request (read only)
6 RFS 0 = Receive FIFO level exceeds RFT threshold, or SSP disabled
1 = Receive FIFO level is at or above RFT threshold, generate interrupt or DMA request
Receive FIFO Overrun (read/write)
7 ROR 0 = Receive FIFO has not experienced an overrun
1 = Attempted data write to full Receive FIFO, request interrupt
Transmit FIFO Level (read only)
11:8 TFL Number of entries in Transmit FIFO. Note: When the value 0x0 is read, the FIFO is either
empty or full and the software must refer to the TNF bit.
Receive FIFO Level (read only)
15:12 RFL Number of entries minus one in Receive FIFO. Note: When the value 0xF is read, the FIFO
is either empty or full and the software must refer to the RNE bit.
31:16 — reserved
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
9.1 Overview
The I2C bus was created by the Phillips Corporation and is a serial bus with a two-pin interface.
The SDA data pin is used for input and output functions and the SCL clock pin is used to control
and reference the I2C bus. The I2C unit allows the processor to serve as a master and slave device
that resides on the I2C bus.
The I2C unit enables the processor to communicate with I 2C peripherals and microcontrollers for
system management functions. The I2C bus requires a minimum amount of hardware to relay status
and reliability information concerning the processor subsystem to an external device.
The I2C unit is a peripheral device that resides on the processor internal bus. Data is transmitted to
and received from the I2C bus via a buffered interface. Control and status information is relayed
through a set of memory-mapped registers. Refer to The I2C-Bus Specification for complete details
on I2C bus operation.
Note: The I2C unit does not support the hardware general call, 10-bit addressing, or CBUS compatibility.
For example, when the processor I2C unit acts as a master on the bus, it addresses an EEPROM as
a slave to receive data (see Figure 9-1). When the I2C unit is addressing the EEPROM, it is a
master-transmitter and the EEPROM is a slave-receiver. When the I2C reads data, it is a master-
receiver and the EEPROM is a slave-transmitter. Whether it is a transmitter or receiver, the master
generates the clock, initiates the transaction, and terminates the transaction.
Figure 9-1. I2C Bus Configuration Example
EEPROM
Processor
SCL
SDA
Gate Micro -
Array Controller
The I2C bus allows for a multi-master system, which means more than one device can initiate data
transfers at the same time. To support this feature, the I2C bus arbitration relies on the wired-AND
connection of all I2C interfaces to the I2C bus. Two masters can drive the bus simultaneously,
provided they drive identical data. If a master tries to drive SDA high while another master drives
SDA low, it loses the arbitration. The SCL line is a synchronized combination of clocks generated
by the masters using the wired-AND connection to the SCL line.
The I2C bus serial operation uses an open-drain wired-AND bus structure, which allows multiple
devices to drive the bus lines and to communicate status about events such as arbitration, wait
states, error conditions, etc. For example, when a master drives the clock (SCL) line during a data
transfer, it transfers a bit on every instance that the clock is high. When the slave is unable to accept
or drive data at the rate that the master is requesting, the slave can hold the clock line low between
the high states to insert a wait interval. The master’s clock can only be altered by another master
during arbitration or a slow slave peripheral that keeps the clock line low.
I2C transactions are either initiated by the processor as a master or received by the processor as a
slave. Both conditions may result in reads, writes, or both to the I2C bus.
The I2C unit initiates an interrupt to the processor when a buffer is full, a buffer is empty, the I2C
unit slave address is detected, arbitration is lost, or a bus error condition occurs. All interrupt
conditions must be cleared explicitly by software. See Section 9.9.4 for details.
The 8-bit I2C Data Buffer Register (IDBR) is loaded with a byte of data from the shift register
interface to the I2C bus when receiving data and from the processor internal bus when writing data.
The serial shift register is not user accessible.
The I2C Control Register (ICR) and the I2C Status Register (ISR) are located in the I2C memory-
mapped address space. The registers and their functions are defined in Section 9.9.
The I2C unit supports a fast mode operation of 400 Kbits/sec and a standard mode of 100 Kbits/sec.
Refer to The I2C-Bus Specification for details.
While the I2C unit is idle, it defaults to slave-receive mode. This allows the interface to monitor the
bus and receive any slave addresses intended for the processor.
When the I2C unit receives an address that matches the 7-bit address found in the I2C Slave
Address Register (ISAR) or the general call address (see Section 9.4.7), the interface either
remains in slave-receive mode or transitions to slave-transmit mode. The Read/Write bit (R/nW)
determines which mode the interface enters. The R/nW bit is the least significant bit of the byte
containing the slave address. If the R/nW bit is low, the master that initiated the transaction intends
write data and the I2C unit remains in slave-receive mode. If the R/nW is high, the master that
initiated the transaction intends to read data and the I2C unit transitions to slave-transmit mode.
Section 9.4.6 further defines slave operation.
When the I2C unit initiates a read or write on the I2C bus, it transitions from the default slave-
receive mode to the master-transmit mode. If the transaction is a write, the I2C unit remains in
master-transmit mode after the address transfer is completed. If the transaction is a read, the I2C
unit transmits the start address, then transitions to master-receive mode. Section 9.4.5 further
defines master operation.
The I2C unit uses the ICR[START] and ICR[STOP] bits to:
• Initiate an additional byte transfer
• Initiate a START condition on the I2C bus
• Enable Data Chaining (repeated START)
• Initiate a STOP condition on the I2C bus
Table 9-4 defines the START and STOP bits in the ICR.
Figure 9-2 shows the relationship between the SDA and SCL lines for START and STOP
conditions.
Figure 9-2. Start and Stop Conditions
~
SDA
~
~
SCL
The START condition is not cleared by the I2C unit. If the I 2C loses arbitration while initiating a
START, it may re-attempt the START when the bus is freed. See Section 9.4.4 for details on how
the I2C unit functions in those circumstances.
After each byte transfer, including the ICR[ACKNAK] bit, the I2C unit holds the SCL line low to
insert wait states until the ICR[TB] bit is set. This action notifies the I2C unit to release the SCL
line and allow the next information transfer to proceed.
START Condition
ACK/
START Target Slave Address R/nW NAK
STOP Condition
ACK/
Data Byte STOP
NAK
Read/Write Transaction
(0) Write
(1) Read
7-Bit I2C Slave Address
7 0
MSB LSB
The first byte transmission must be followed by an ACK pulse from the addressed slave. When the
transaction is a write, the I2C unit remains in master-transmit mode and the addressed slave device
stays in slave-receive mode. When the transaction is a read, the I2C unit transitions to master-
receive mode immediately following the ACK and the addressed slave device transitions to slave-
transmit mode. When a NAK is returned, the I2C unit aborts the transaction by automatically
sending a STOP and setting the ISR[BED] bit.
When the I2C unit is enabled and idle, it remains in slave-receive mode and monitors the I2C bus
for a START signal. When it detects a START pulse, the I2C unit reads the first seven bits and
compares them to those in the ISAR and the general call address (0x00). When the bits match those
in the ISAR register, the I2C unit reads the eighth bit (R/nW bit) and transmits an ACK pulse. The
I2C unit either remains in slave-receive mode (R/nW = 0) or transitions to slave-transmit mode (R/
nW = 1). See Section 9.4.7 for actions when a general call address is detected.
SDA released
∼
Data Output
by Transmitter
∼
(SDA)
SDA pulled low
by Receiver (ACK)
∼
Data Output
by Receiver
(SDA)
∼
SCL from
1 2-7 8 9
Master
Clock Pulse
Start Condition for Acknowledge
In master-transmit mode, if the target slave-receiver device cannot generate the acknowledge pulse,
the SDA line remains high. The lack of an acknowledge NAK causes the I2C unit to set the
ISR[BED] bit and generate the associated interrupt when enabled. The I2C unit automatically
generates a STOP condition and aborts the transaction.
In master-receive mode, the I2C unit sends a negative acknowledge (NAK) to signal the slave-
transmitter to stop sending data. The ICR[ACKNAK] bit controls the ACK/NAK bit value that the
I2C bus drives. As required by the I2C bus protocol, the ISR[BED] bit is not set for a master-
receive mode NAK. The I2C unit automatically transmits the ACK pulse after it receives each byte
from the serial bus. Before the unit receives the last byte, software must set the ICR[ACKNAK] bit
to 1 (NAK). The NAK pulse is sent after the last byte to indicate that the last byte has been sent.
In slave mode, the I2C unit automatically acknowledges its own slave address, independent of the
value in the ICR[ACKNAK] bit. In slave-receive mode, an ACK response automatically follows a
data byte, independent of the value in the ICR[ACKNAK] bit. The I2C unit sends the ACK value
after it receives the eighth data bit in a byte.
In slave-transmit mode, the I2C unit receives a NAK from the master to indicate the last byte has
been transferred. The master then sends a STOP or repeated START. The ISR[UB] bit remains set
until a STOP or repeated START is received.
9.4.4 Arbitration
The I2C bus’ multi-master capabilities require I2C bus arbitration. Arbitration takes place when
two or more masters generate a START condition in the minimum hold time.
Arbitration can take a long time. If the address bit and the R/nW are the same, the arbitration
scheme considers the data. Because the I2C bus has a wired-AND nature, a transfer does not lose
data if multiple masters signal the same bus states. If the address and the R/nW bit or the data they
contain are different, the master signals a high state loses arbitration and shuts off its data drivers. If
the I2C unit loses arbitration, it shuts off the SDA or SCL drivers for the rest of the byte transfer,
sets the ISR[ALD] bit, and returns to slave-receive mode.
Clock synchronization is through the wired-AND connection of the I2C interfaces to the SCL line.
When a master’s clock changes from high to low, the master holds down the SCL line for its
associated period (see Figure 9-6). A clock cannot switch from low to high if another master has
not completed its period. The master with the longest low period holds down the SCL line. Masters
with shorter periods are held in a high wait-state until the master with the longest period completes.
After the master with the longest period completes, the SCL line changes to the high state and
masters with the shorter periods continue the data cycle.
Figure 9-6. Clock Synchronization During the Arbitration Procedure
CLK1
CLK2
SCL
Data 1
Data 2
SDA
SCL
If the I 2C unit loses arbitration as the address bits are transferred and it is not addressed by the
address bits, the I2C unit resends the address when the I2C bus becomes free. A resend is possible
because the IDBR and ICR registers are not overwritten when arbitration is lost.
If the I2C unit loses arbitration because another bus master addresses the processor as a slave
device, the I2C unit switches to slave-receive mode and overwrites the original data in the I2C data
buffer register. Software can clear the start and re-initiate the master transaction.
Note: Software must prevent the I2C unit from starting a transaction to its own slave address because
such a transaction puts the I2C unit in an indeterminate state.
Note: Software ensures that arbitration is resolved quickly. For example, software can ensure that masters
send unique data by requiring that each master transmit its I2C address as the first data byte of any
transaction. When arbitration is resolved, the winning master sends a restart and begins a valid data
transfer. The slave discards the master’s address and use the other data.
Write target • CPU writes to IDBR bits 7-1 before a START condition enabled.
Master-transmit
slave address • First seven bits sent on bus after START.
to IDBR Master-receive
• See Section 9.3.3.
• CPU writes to least significant IDBR bit with target slave address.
Write R/nW Bit Master-transmit • If low, master remains a master-transmitter. If high, master
to IDBR Master-receive transitions to a master-receiver.
• See Section 9.4.2.
• See “Generate clock output” above.
• Performed after target slave address and R/nW bit are in IDBR.
Signal START Master-transmit
• Software sets ICR[START] bit.
Condition Master-receive
• Software sets ICR[TB] bit to initiate start condition.
• See Section 9.3.3.
• CPU writes byte to IDBR
Initiate first Master-transmit • I2C unit transmits byte when ICR[TB] bit is set.
data byte
transfer Master-receive • I2C unit clears ICR[TB] bit and sets ISR[ITE] bit when transfer is
complete.
• If two or more masters signal a start within the same clock period,
arbitration must occur.
• I2C unit arbitrates for as long as needed. Arbitration takes place
during slave address and R/nW bit or data transmission and
continues until all but one master loses the bus. No data lost.
Arbitrate for Master-transmit
• If I2C unit loses arbitration, it sets ISR[ALD] bit after byte transfer is
I2C Bus Master-receive completed and transitions to slave-receive mode.
• If I2C unit loses arbitration as it attempts to send target address byte,
I2C unit attempts to resend it when the bus becomes free.
• System designer must ensure boundary conditions described in
Section 9.4 do not occur.
Wait for • As a master-transmitter, the I2C unit generates the clock for the
Acknowledge Master-transmit acknowledge pulse. The I2C unit releases the SDA line to allow
from slave- only slave-receiver ACK transmission.
receiver • See Section 9.4.3.
• I2C master operation data receive mode.
• Eight bits are read from the serial bus, collected in the shift register
then transferred to the IDBR after the ICR[ACKNAK] bit is read.
• The CPU reads the IDBR when the ISR[IRF] bit is set and the
ICR[TB] bit is clear. If IDBR Receive Full Interrupt is enabled, it is
signalled to the CPU.
• When the IDBR is read, if the ISR[ACKNAK] is clear (indicating
Read one byte ACK), the processor writes the ICR[ACKNAK] bit and set the
Master-receive ICR[TB] bit to initiate the next byte read.
of I2C Data
only
from the IDBR • If the ISR[ACKNAK] bit is set (indicating NAK), ICR[TB] bit is clear,
ICR[STOP] bit is set, and ISR[UB] bit is set, then the last data byte
has been read into the IDBR and the I2C unit is sending the STOP.
• If the ISR[ACKNAK] bit is set (indicating NAK), ICR[TB] bit is clear,
but the ICR[STOP] bit is clear, then the CPU has two options: 1. set
the ICR[START] bit, write a new target address to the IDBR, and set
the ICR[TB] bit which will send a repeated start condition or 2. set
the ICR[MA] bit and leave the ICR[TB] bit clear which will send a
STOP only.
• As a master-receiver, the I2C unit will generate the clock for the
Transmit acknowledge pulse. The I2C unit is also responsible for driving the
Acknowledge Master-receive SDA line during the ACK cycle.
to slave- only • If the next data byte is to be the last transaction, the CPU will set the
transmitter ICR[ACKNAK] bit for NAK generation.
• See Section 9.4.3.
• If data chaining is desired, a repeated START condition is used
instead of a STOP condition.
Generate a
Repeated • This occurs after the last data byte of a transaction has been written
Master-transmit
START to to the bus.
chain I2C Master-receive
• The CPU will write the next target slave address and the R/nW bit to
transactions the IDBR, set the ICR[START] bit, and set the ICR[TB] bit.
• See Section 9.3.3.
• Generated after the CPU writes the last data byte on the bus.
Generate a Master-transmit
• CPU generates a STOP condition by setting the ICR[STOP] bit.
STOP Master-receive
• See Section 9.3.3.
When the CPU needs to read data, the I2C unit transitions from slave-receive mode to master-
transmit mode to transmit the start address, R/nW bit, and the ACK pulse. After it sends the ACK
pulse, the I2C unit transitions to master-receive mode and waits to receive the read data from the
slave device (see Figure 9-8).Multiple transactions can take place during an I2C operation. For
example, transitioning from master-receive to master-transmit through a repeated start.
Read Write
SDA
∼
∼
∼
∼
∼
∼
Transmit • As a slave-receiver, the I2C unit pulls the SDA line low to generate
Acknowledge to Slave-receive the ACK pulse during the high SCL period.
master- only • ICR[ACKNAK] bit controls the ACK data the I2C unit drives. See
transmitter Section 9.4.3.
• Data transmit mode of I2C slave operation.
Write one byte of • Occurs when ISR[ITE] bit is set and ICR[TB] bit is clear. If enabled,
Slave-transmit
I2C data to the the IDBR Transmit Empty Interrupt is signalled to the processor.
only
IDBR • The processor writes a data byte to IDBR and sets ICR[TB] bit to start
the transfer.
Wait for • As a slave-transmitter, the I2C unit releases the SDA line to allow the
Acknowledge Slave-transmit master-receiver to pull the line low for the ACK.
from master- only
receiver • See Section 9.4.3.
Figure 9-11 through Figure 9-13 are examples of I2C transactions and show the relationships
between master and slave devices.
The I2C unit supports sending and receiving general call address transfers on the I2C bus. When
software sends a general call message from the I2C unit, it must set the ICR[GCD] bit to prevent
the I2C unit from responding as a slave. If the ICR[GCD] is not set, the I2C bus enters an
indeterminate state.
If the I2C unit acts as a slave and receives a general call address while the ICR[GCD] bit is clear, it:
• Sets the ISR[GCAD] bit
• Sets the ISR[SAD] bit
• Interrupts the processor (if the interrupt is enabled)
If the I2C unit receives a general call address and the ICR[GCD] bit is set, it ignores the general
call address.
Figure 9-14. General Call Address
Data Data
START 00000000 ACK Second Byte 0 ACK Byte ACK Byte ACK STOP
2-byte transaction in which the second byte tells the slave to reset and store this
0 0x06
value in the programmable part of its address.
2-byte transaction in which the second byte tells the slave to store this value in
0 0x04
the programmable part of its address. No reset.
0 0x00 Not allowed as a second byte
NOTE: Other values are not fixed and must be ignored.
Software must ensure that the I2C unit is not busy before it asserts a reset. Software must also
ensure that the I2C bus is idle when the unit is enabled after reset. When directed to reset, the I2C
unit, except for ISAR, returns to the default reset condition. ISAR is not affected by a reset.
When B=1, the sequence is a hardware general call and is not supported by the I2C unit. Refer to
the The I2C-Bus Specification for information on hardware general calls.
Note: If a NAK is not sent in Step 11, the next transaction must involve another data byte read.
When the ICR[UR] bit is set, the I2C unit resets but the associated I2C MMRs remain intact. When
resetting the I2C unit with the ICR’s unit reset, use the following guidelines:
1. Set the reset bit in the ICR register and clear the remainder of the register.
2. Clear the ISR register.
3. Clear reset in the ICR.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 9-8. IBMR Bit Definitions
Physical Address
I2C Bus Monitor Register I2C Bus Interface Unit
4030_1680
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDAS
SCLS
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
31:2 — reserved
1 SCLS SCL Status: This bit continuously reflects the value of the SCL pin.
0 SDAS SDA Status: This bit continuously reflects the value of the SDA pin.
When the I2C unit is in transmit mode (master or slave), the processor writes data to the IDBR over
the internal bus. The processor writes data to the IDBR when a master transaction is initiated or
when the IDBR Transmit Empty Interrupt is signalled. Data moves from the IDBR to the shift
register when the Transfer Byte bit is set. The IDBR Transmit Empty Interrupt is signalled (if
enabled) when a byte is transferred on the I2C bus and the acknowledge cycle is complete. If the
IDBR is not written by the processor and a STOP condition is not in place before the I2C bus is
ready to transfer the next byte packet, the I2C unit inserts wait states until the processor writes the
IDBR and sets the Transfer Byte bit.
When the I2C unit is in receive mode (master or slave), the processor reads IDBR data over the
internal bus. The processor reads data from the IDBR when the IDBR Receive Full Interrupt is
signalled. The data moves from the shift register to the IDBR when the ACK cycle is complete.
The I2C unit inserts wait states until the IDBR is read. Refer to Section 9.4.3 for more information
on the acknowledge pulse in receiver mode. After the processor reads the IDBR, the ACK/NAK
Control bit is written and the Transfer Byte bit is written, allowing the next byte transfer to proceed
to the I2C bus. The IDBR register is 0x00 after reset.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 9-9. IDBR Bit Definitions
Physical Address
I2C Data Buffer Register I2C Bus Interface Unit
4030_1688
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved IDB
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31:8 — reserved
7:0 IDB I2C Data Buffer: Buffer for I2C bus send/receive data.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 9-10. ICR Bit Definitions (Sheet 1 of 3)
Physical Address
I2C Control Register I2C Bus Interface Unit
4030_1690
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACKNAK
START
SADIE
ALDIE
SSDIE
STOP
SCLE
IRFIE
ITEIE
BEIE
GCD
IUE
MA
FM
UR
TB
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31:16 — reserved
Fast Mode:
15 FM 0 = 100 KBit/sec. operation
1 = 400 KBit/sec. operation
Unit Reset:
14 UR 0 = No reset.
1 = Reset the I 2C unit only.
Slave Address Detected Interrupt Enable:
13 SADIE 0 = Disable interrupt.
1 = Enables the I 2C unit to interrupt the processor when it detects a slave address match or
general call address.
Arbitration Loss Detected Interrupt Enable:
12 ALDIE 0 = Disable interrupt.
1 = Enables the I2C unit to interrupt the processor when it loses arbitration in master mode.
Slave STOP Detected Interrupt Enable:
11 SSDIE 0 = Disable interrupt.
1 = Enables the I 2C unit to interrupt the processor when it detects a STOP condition in
slave mode.
ACKNAK
START
SADIE
ALDIE
SSDIE
STOP
SCLE
IRFIE
ITEIE
BEIE
GCD
IUE
MA
FM
UR
TB
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bus Error Interrupt Enable:
0 = Disable interrupt.
1 = Enables the I2C unit to interrupt the processor for the following I2C bus errors:
10 BEIE • As a master transmitter, no ACK was detected after a byte was sent.
• As a slave receiver, the I2C unit generated a NAK pulse.
NOTE: Software is responsible for guaranteeing that misplaced START and STOP
conditions do not occur. See Section 9.7.
IDBR Receive Full Interrupt Enable:
9 IRFIE 0 = Disable interrupt.
1 = Enables the I2C unit to interrupt the processor when the IDBR receives a data byte
from the I2C bus.
IDBR Transmit Empty Interrupt Enable:
8 ITEIE 0 = Disable interrupt.
1 = Enables the I2C unit to interrupt the processor after transmitting a byte onto the I2C
bus.
General Call Disable:
0 = Enables the I2C unit to respond to general call messages.
7 GCD
1 = Disables I2C unit response to general call messages as a slave.
Must be set when the I2C unit sends a master mode general call message.
I2C Unit Enable:
0 = Disables the unit and does not master any transactions or respond to any slave
6 IUE transactions.
1 = Enables the I2C unit (defaults to slave-receive mode).
Software must ensure that the I2C bus is idle before it sets this bit.
SCL Enable:
5 SCLE 0 = Disables the I2C unit from driving the SCL line.
1 = Enables the I2C clock output for master mode operation.
Master Abort: generates a STOP without transmitting another data byte when the I2C unit
is in master mode.
0 = The I2C unit transmits STOP using the STOP ICR bit only.
1 = The I2C unit sends STOP without data transmission.
4 MA In master-transmit mode, after a data byte is sent, the ICR’s Transfer Byte bit is cleared and
IDBR Transmit Empty bit is set. When no more data bytes need to be sent, setting master
abort bit sends the STOP. The Transfer Byte bit (03) must remain clear.
In master-receive mode, when a NAK is sent without a STOP (STOP ICR bit was not set)
and the processor does not send a repeated START, setting this bit sends the STOP. Once
again, the Transfer Byte bit (03) must remain clear.
Transfer Byte: used to send/receive a byte on the I2C bus.
0 = Cleared by I2C unit when the byte is sent/received.
1 = Send/receive a byte.
3 TB
The processor can monitor this bit to determine when the byte transfer is completed. In
master or slave mode, after each byte transfer, including ACK/NAK bit, the I2C unit holds
the SCL line low (inserting wait states) until the Transfer Byte bit is set.
ACKNAK
START
SADIE
ALDIE
SSDIE
STOP
SCLE
IRFIE
ITEIE
BEIE
GCD
IUE
MA
FM
UR
TB
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2
ACK/NAK Control: defines the type of ACK pulse sent by the I C unit when in master-
receive mode.
0 = The I 2C unit sends an ACK pulse after it receives a data byte.
2 ACKNAK
1 = The I 2C unit sends a negative ACK (NAK) after it receives a data byte.
The I2C unit automatically sends an ACK pulse when it responds to its slave address or
when it responds in slave-receive mode, independent of the ACK/NAK control bit setting.
STOP: initiates a STOP condition after the next data byte on the I2C bus is transferred in
master mode. In master-receive mode, the ACK/NAK control bit must be set along with this
1 STOP bit. See Section 9.3.3.3 for more details on the STOP state.
0 = Do not send a STOP.
1 = Send a STOP.
START: initiates a START condition to the I2C unit when in master mode. See
Section 9.3.3.1 for more details on the START state.
0 START
0 = Do not send a START.
1 = Send a START.
The ISR also clears the following interrupts signalled from the I2C unit:
• IDBR Receive Full
• IDBR Transmit Empty
• Slave Address Detected
• Bus Error Detected
• STOP Condition Detect
• Arbitration Lost
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACKNAK
GCAD
RWM
BED
SAD
ALD
SSD
IBB
IRF
ITE
UB
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31:11 — reserved
Bus Error Detected:
0 = No error detected.
1 = The I2C unit sets this bit when it detects one of the following error conditions:
• As a master transmitter, no ACK is detected on the interface after a byte is sent.
10 BED
• As a slave receiver, the I2C unit generates a NAK pulse.
NOTE:When an error occurs, I2C bus transactions continue. Software must ensure that
misplaced START and STOP conditions do not occur. See Section 9.4.4.
To clear this bit, write a 1 to it.
Slave Address Detected:
0 = No slave address detected.
9 SAD 1 = I2C unit detected a 7-bit address that matches the general call address or ISAR. An
interrupt is signalled when the SADIE interrupt is set to a 1.
To clear this bit, write a 1 to it.
General Call Address Detected:
8 GCAD 0 = No general call address received.
1 = I2C unit received a general call address.
IDBR Receive Full:
0 = The IDBR has not received a new data byte or the I2C unit is idle.
7 IRF 1 = The IDBR register received a new data byte from the I2C bus. An interrupt is signalled
when the IRFIE is set to a 1.
To clear this bit, write a 1 to it.
IDBR Transmit Empty:
0 = The data byte is still being transmitted.
6 ITE 1 = The I2C unit has finished transmitting a data byte on the I2C bus. An interrupt is
signalled when the ITEIE interrupt is set to 1.
To clear this bit, write a 1 to it.
Arbitration Loss Detected: used during multi-master operation.
0 = Cleared when arbitration is won or never took place.
5 ALD
1 = Set when the I2C unit loses arbitration.
To clear this bit, write a 1 to it.
Slave STOP Detected:
0 = No STOP detected.
4 SSD
1 = Set when the I2C unit detects a STOP while in slave-receive or slave-transmit mode.
To clear this bit, write a 1 to it.
I2C Bus Busy:
3 IBB 0 = I2C bus is idle or the I 2C unit is using the bus (i.e., unit busy).
1 = Set when the I2C bus is busy but the I2C unit is not involved in the transaction.
Unit Busy:
2 UB 0 = I2C unit not busy.
1 = Set when the I2C unit is busy. Defined as the time between the first START and STOP.
ACKNAK
GCAD
RWM
BED
SAD
ALD
SSD
IBB
IRF
ITE
UB
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ACK/NAK Status:
0 = I2C unit received or sent an ACK on the bus.
1 ACKNAK 1 = I2C unit received or sent a NAK.
Used in slave-transmit mode to determine when the transferred byte is the last one.
Updated after each byte and ACK/NAK information is received.
Read/Write Mode:
0 = I2C unit is in master-transmit or slave-receive mode.
0 RWM
1 = I2C unit is in master-receive or slave-transmit mode.
R/nW bit of the slave address. Automatically cleared by hardware after a stop state.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 9-12. ISAR Bit Definitions
Physical Address
I2C Slave Address Register I2C Bus Interface Unit
4030_16A0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved ISA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31:7 — reserved
I2C Slave Address: 7-bit address that the I2C unit responds to when in slave-receive
6:0 ISA
mode.
10.2 Overview
Each serial port contains a UART and a slow infrared transmit encoder and receive decoder that
conforms to the IRDA Serial Infrared (SIR) Physical Layer Link Specification.
Each UART performs serial-to-parallel conversion on data characters received from a peripheral
device or a modem and parallel-to-serial conversion on data characters received from the
processor. The processor can read a UART’s complete status during functional operation. Status
information includes the type and condition of transfer operations and error conditions (parity,
overrun, framing, or break interrupt) associated with the UART.
Each serial port operates in FIFO or non-FIFO mode. In FIFO mode, a 64-byte Transmit FIFO
holds data from the processor until it is transmitted on the serial link and a 64-byte Receive FIFO
buffers data from the serial link until it is read by the processor. In non-FIFO mode, the transmit
and Receive FIFOs are bypassed.
Each UART includes a programmable baud rate generator that can divide the input clock by 1 to
(216–1). This produces a 16X clock that can be used to drive the internal transmitter and receiver
logic. Software can program interrupts to meet its requirements. This minimizes the number of
computations required to handle the communications link. Each UART operates in an environment
that is controlled by software and can be polled or is interrupt driven.
SERIAL INPUT: Serial data input to the receive shift register. In infrared
RXD Input mode, it is connected to the infrared receiver input. This signal is present on
all three UARTs.
SERIAL OUTPUT: Serial data output to the communications link-
peripheral, modem, or data set. The TXD signal is set to the logic 1 state
TXD Output
upon a Reset operation. It is connected to the output of the infrared
transmitter in infrared mode. This signal is present all three UARTs.
CLEAR TO SEND: When low, indicates that the modem or data set is ready
to exchange data. The nCTS signal is a modem status input and its
condition can be tested by reading bit 4 (CTS) of the Modem Status
Register. Bit 4 is the complement of the nCTS signal. Bit 0 (DCTS) of the
Modem Status Register (MSR) indicates whether the nCTS input has
nCTS Input changed state since the last time the Modem Status Register was read.
nCTS has no effect on the transmitter. This signal is present on the
FFUART and BTUART.
When the CTS bit of the MSR changes state and the Modem Status
interrupt is enabled, an interrupt is generated.
DATA SET READY: When low, indicates that the modem or data set is
ready to establish a communications link with a UART. The nDSR signal is
a Modem Status input and its condition can be tested by reading Bit 5
(DSR) of the MSR. Bit 5 is the complement of the nDSR signal. Bit 1
nDSR Input (DDSR) of the MSR indicates whether the nDSR input has changed state
since the MSR was last read. This signal is only present on the FFUART.
When the DSR bit of the MSR changes state, an interrupt is generated if the
Modem Status interrupt is enabled.
DATA CARRIER DETECT: When low, indicates that the data carrier has
been detected by the modem or data set. The nDCD signal is a modem
status input and its condition can be tested by reading Bit 7 (DCD) of the
MSR. Bit 7 is the complement of the nDCD signal. Bit 3 (DDCD) of the MSR
nDCD Input indicates whether the nDCD input has changed state since the previous
reading of the Modem Status Register. nDCD has no effect on the receiver.
This signal is only present on the FFUART.
When the DCD bit changes state and the Modem Status interrupt is
enabled, an interrupt is generated.
RING INDICATOR: When low, indicates that the modem or data set has
received a telephone ringing signal. The nRI signal is a Modem Status input
whose condition can be tested by reading Bit 6 (RI) of the MSR. Bit 6 is the
complement of the nRI signal. Bit 2, the trailing edge of ring indicator
nRI Input (TERI), of the MSR indicates whether the nRI input signal has changed
from low to high since the MSR was last read. This signal is only present on
the FFUART.
When the RI bit of the MSR changes from a high to low state and the
Modem Status interrupt is enabled, an interrupt is generated.
DATA TERMINAL READY: When low, signals the modem or the data set
that the UART is ready to establish a communications link. The nDTR
output signal can be set to an active low by programming Bit 0 (DTR) of the
nDTR Output
MSR to a 1. A Reset operation sets this signal to its inactive state. LOOP
mode operation holds this signal in its inactive state. This signal is only
present on the FFUART.
REQUEST TO SEND: When low, signals the modem or the data set that
the UART is ready to exchange data. The nRTS output signal can be set to
an active low by programming Bit 1 (RTS) of the Modem Control Register to
nRTS Output
a 1. A Reset operation sets this signal to its inactive (high) state. LOOP
mode operation holds this signal in its inactive state. This signal is used by
the FFUART and BTUART.
Parit
Start Data Data Data Data Data Data Data Data Stop Stop
y
Bit <0> <1> <2> <3> <4> <5> <6> <7> Bit 1 Bit 2
Bit
TXD or RXD pin
LSB MSB
Receive data sample counter frequency is 16 times the value of the bit frequency. The 16X clock is
created by the baud rate generator. Each bit is sampled three times in the middle. Shaded bits in
Figure 10-1 are optional and can be programmed by software.
Each data frame is between seven and 12 bits long, depending on the size of the data programmed,
whether parity is enabled, and the number of stop bits. A data frame begins by transmitting a start
bit that is represented by a high to low transition. The start bit is followed by from five to eight bits
of data that begin with the least significant bit (LSB). The data bits are followed by an optional
parity bit. The parity bit is set if even parity is enabled and the data byte has an odd number of ones
or if odd parity is enabled and the data byte has an even number of ones. The data frame ends with
one, one and a half or two stop bits, as programmed by software. The stop bits are represented by
one, one and a half, or two successive bit periods of a logic one.
Each UART has two FIFOs: one transmit and one receive. The transmit FIFO is 64 bytes deep and
eight bits wide. The receive FIFO is 64 bytes deep and 11 bits wide. Three bits are used for tracking
errors.
The UART can use NRZ coding to represent individual bit values. NRZ coding is enabled when the
Interrupt Enable Register’s (IER) bit 5, IER[5] is set to high. A one is represented by a line
transition and a zero is represented by no line transition. Figure 10-2 shows the data byte 0b 0100
1011 in NRZ coding. The byte’s LSB is transmitted first.
Figure 10-2. Example NRZ Bit Encoding – (0b0100 1011
LSB MSB
Bit 1 1 0 1 0 0 1 0
Value
Digital
Data
NRZ
Data
)E
10.4.1 Reset
The UARTs are disabled on reset. To enable a UART, Software must program the GPIO registers
(see Section 4.1, “General-Purpose I/O” on page 4-1) then set IER[UUE]. When the UART is
enabled, the receiver waits for a frame start bit and the transmitter sends data if it is available in the
Transmit Holding Register. Transmit data can be written to the Transmit Holding Register before
the UART unit is enabled. In FIFO mode, data is transmitted from the FIFO to the Transmit
Holding Register before it goes to the pin.
When the UART unit is disabled, the transmitter or receiver finishes the current byte and stops
transmitting or receiving more data. Data in the FIFO is not cleared and transmission resumes
when the UART is enabled.
In FIFO mode, the RBR latches the value of the data byte at the front of the FIFO.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RBR7
RBR6
RBR5
RBR4
RBR3
RBR2
RBR1
RBR0
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31:8 — reserved
7:0 RBR[7:0] Data byte received least significant bit first.
In FIFO mode, a write to the THR puts data into the top of the FIFO. The data at the front of the
FIFO is loaded to the TSR when that register is empty.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
THR7
THR6
THR5
THR4
THR3
THR2
THR1
THR0
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31:8 — reserved
7:0 THR[7:0] Data byte transmitted least significant bit first.
The baud rate of the data shifted in to or out of a UART is given by the formula:
14.7456 MHz
BaudRate = ----------------------------------
( 16xDivisor )
For example: if the divisor is 24, the baud rate is 38400 bps.
The divisor’s reset value is 0x0002. For the FFUART and the STUART, the divisor must be set to
at least 0x0004 before the UART unit is enabled.
These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLL7
DLL6
DLL5
DLL4
DLL3
DLL2
DLL1
DLL0
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31:8 — reserved
7:0 DLL[7:0] Low byte compare value to generate baud rate.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLH15
DLH14
DLH13
DLH12
DLH10
DLH11
DLH9
DLH8
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31:8 — reserved
7:0 DLH[7:0] High byte compare value to generate baud rate.
The Character Timeout Indication interrupt is separated from the Received Data Available interrupt
to ensure that the processor and the DMA controller do not service the receive FIFO at the same
time. When a Character Timeout Indication interrupt occurs, the processor must handle the data in
the Receive FIFO through programmed I/O.
An error interrupt is used when DMA requests are enabled. The interrupt is generated when LSR
bit 7 is set to a 1, because a receive DMA request is not generated when the receive FIFO has an
error. The error interrupt tells the processor to handle the data in the receive FIFO through
programmed I/O. The error interrupt is enabled when DMA requests are enabled and it can not be
masked. Receiver Line Status interrupts occur when the error is at the front of the FIFO.
Note: When DMA requests are enabled and an interrupt occurs, software must first read the LSR to see if
an error interrupt exists, then check the IIR for the source of the interrupt. When the last error byte
is read from the FIFO, DMA requests are automatically enabled. Software is not required to check
for the error interrupt if DMA requests are disabled because an error interrupt only occurs when
DMA requests are enabled.
Bit 7 of the IER is used to enable DMA requests. The IER also contains the unit enable and NRZ
coding enable control bits. Bits 7 through 4 are used differently from the standard 16550 register
definition.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTOIE
RAVIE
DMAE
NRZE
RLSE
UUE
MIE
TIE
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31:8 — reserved
DMA Requests Enable.
7 DMAE 0 – DMA requests are disabled
1 – DMA requests are enabled
UART Unit Enable.
6 UUE 0 – The unit is disabled
1 – The unit is enabled
NRZ coding Enable. NRZ encoding/decoding is only used in UART mode, not in infrared
mode. If the slow infrared receiver or transmitter is enabled, NRZ coding is disabled.
5 NRZE
0 – NRZ coding disabled
1 – NRZ coding enabled
Character Timeout Indication Interrupt Enable.
4 RTOIE 0 – Character Timeout Indication interrupt disabled
1 – Character Timeout Indication interrupt enabled
Modem Interrupt Enable.
3 MIE 0 – Modem Status interrupt disabled
1 – Modem Status interrupt enabled
Receiver Line Status Interrupt Enable.
2 RLSE 0 – Receiver Line Status interrupt disabled
1 – Receiver Line Status interrupt enabled
Transmit Data request Interrupt Enable.
1 TIE 0 – Transmit FIFO Data Request interrupt disabled
1 – Transmit FIFO Data Request interrupt enabled
Receiver Data Available Interrupt Enable.
0 RAVIE 0 – Receiver Data Available (Trigger level reached) interrupt disabled
1 – Receiver Data Available (Trigger level reached) interrupt enabled
Note: To ensure that the DMA controller and programmed I/O do not access the same FIFO, software
must not set the DMAE while the TIE or RAVIE bits are set to a 1.
In FIFO mode, the “Received Data is available” interrupt (Priority Level 2) takes priority over the
“Character Timeout Indication” interrupt (Priority Level 2). For example, if the UART is in FIFO
mode and FIFO Control Register[ITL] = 0b00, this will cause the UART to generate an interrupt
when there is one byte in the FIFO. In this scenario, if there is one byte in the FIFO, an interrupt is
generated, and IIR[3:0] = 0b0100, which indicates that Received Data is available. If data remains
in the FIFO and if a Character Timeout occurs (no data has been sent for 4 character times), then
the interrupt status does not change to IIR[3:0] = 0b1100 (Character Timeout Indication).
The error interrupt is reported separately in the LSR. In DMA mode, software must check for the
error interrupt before it checks the IIR.
If additional data is received before a Character Timeout Indication interrupt is serviced, the
interrupt is deasserted.
1 (highest) Receiver Line Status: one or more error bits were set.
Received Data is available. In FIFO mode, trigger level was reached. In
2
non-FIFO mode, RBR has data.
Character Timeout Indication occurred. Occurs only in FIFO mode, when
2
data is in the receive FIFO but no data has been sent for a set time period.
Transmitter requests data. In FIFO mode, the transmit FIFO is at least half
3
empty. In non-FIFO mode, the THR has been transmitted.
4 (lowest) Modem Status: one or more modem input signal has changed state.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOES1
FIFOES0
reserved
reserved
IID3
IID2
IID1
reserved
IP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
31:8 — reserved
FIFO Mode Enable Status:
00 – Non-FIFO mode is selected
7:6 FIFOES[1:0] 01 – reserved
10 – reserved
11 – FIFO mode is selected (FCR[TRFIFOE] = 1)
5:4 — reserved
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOES1
FIFOES0
reserved
reserved
IID3
IID2
IID1
reserved
IP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESETRF
RESETTF
TRFIFOE
reserved
reserved
reserved
ITL
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31:8 — reserved
Interrupt Trigger Level: When the number of bytes in the receiver FIFO equals the interrupt
trigger level programmed into this field and the Received Data Available Interrupt is
enabled via the IER, an interrupt is generated and appropriate bits are set in the IIR. The
receive DMA request is also generated when the trigger level is reached.
7:6 ITL 0b00 – 1 byte or more in FIFO causes interrupt (Not valid in DMA mode)
0b01 – 8 bytes or more in FIFO causes interrupt and DMA request
0b10 – 16 bytes or more in FIFO causes interrupt and DMA request
0b11 – 32 bytes or more in FIFO causes interrupt and DMA request
5:3 — reserved
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESETRF
RESETTF
TRFIFOE
reserved
reserved
reserved
ITL
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reset transmitter FIFO: When RESETTF is set to 1, all the bytes in the transmitter FIFO
are cleared. The TDRQ bit in the LSR is set and the IIR shows a transmitter requests data
interrupt, if the TIE bit in the IER register is set. The transmitter shift register is not cleared
2 RESETTF and it completes the current transmission.
0 – Writing 0 has no effect
1 – The transmitter FIFO is cleared
Reset Receiver FIFO: When RESETRF is set to 1, all the bytes in the receiver FIFO are
cleared. The DR bit in the LSR is reset to 0. All the error bits in the FIFO and the FIFOE bit
in the LSR are cleared. Any error bits, OE, PE, FE or BI, that had been set in LSR are still
1 RESETRF set. The receiver shift register is not cleared. If the IIR had been set to Received Data
Available, it is cleared.
0 – Writing 0 has no effect
1 – The receiver FIFO is cleared
Transmit and Receive FIFO Enable: TRFIFOE enables/disables the transmitter and
receiver FIFOs. When TRFIFOE = 1, both FIFOs are enabled (FIFO Mode). When
TRFIFOE = 0, the FIFOs are both disabled (non-FIFO Mode). Writing a 0 to this bit clears
all bytes in both FIFOs. When changing from FIFO mode to non-FIFO mode and vice
0 TRFIFOE versa, data is automatically cleared from the FIFOs. This bit must be 1 when other bits in
this register are written or the other bits are not programmed.
0 – FIFOs are disabled
1 – FIFOs are enabled
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STKYP
WLS1
WLS0
DLAB
PEN
STB
EPS
SB
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31:8 — reserved
Divisor Latch Access Bit: Must be set high (logic 1) to access the Divisor Latches of the
Baud Rate Generator during a READ or WRITE operation. Must be set low (logic 0) to
7 DLAB access the Receiver Buffer, the Transmit Holding Register, or the IER.
0 – access Transmit Holding register (THR), Receive Buffer register (RBR) and IER.
1 – access Divisor Latch registers (DLL and DLH)
Set Break: Causes a break condition to be transmitted to the receiving UART. Acts only on
the TXD pin and has no effect on the transmitter logic. In FIFO mode, wait until the
6 SB transmitter is idle, LSR[TEMT]=1, to set and clear SB.
0 – no effect on TXD output
1 – forces TXD output to 0 (space)
Sticky Parity: Forces the bit value at the parity bit location to be the opposite of the EPS bit,
rather than the parity value. This stops parity generation. If PEN = 0, STKYP is ignored.
5 STKYP
0 – no effect on parity bit
1 – forces parity bit to be opposite of EPS bit value
Even Parity Select: Even parity select bit. If PEN = 0, EPS is ignored.
4 EPS 0 – sends or checks for odd parity
1 – sends or checks for even parity
Parity Enable: Enables a parity bit to be generated on transmission or checked on
reception.
3 PEN
0 – no parity
1 – parity
Stop Bits: Specifies the number of stop bits transmitted and received in each character.
When receiving, the receiver only checks the first stop bit.
2 STB
0 – 1 stop bit
1 – 2 stop bits, except for 5-bit character then 1-1/2 bits
Word Length Select: Specifies the number of data bits in each transmitted or received
character.
00 – 5-bit character
1:0 WLS[1:0]
01 – 6-bit character
10 – 7-bit character
11 – 8-bit character
In non-FIFO mode, LSR[4:2]: parity error, framing error, and break interrupt, show the error status
of the character that has just been received.
In FIFO mode, LSR[4:2] show the status bits of the character that is currently at the front of the
FIFO.
LSR[4:1] produce a receiver line status interrupt when the corresponding conditions are detected
and the interrupt is enabled. In FIFO mode, the receiver line status interrupt only occurs when the
erroneous character reaches the front of the FIFO. If the erroneous character is not at the front of
the FIFO, a line status interrupt is generated after the other characters are read and the erroneous
character becomes the character at the front of the FIFO.
The LSR must be read before the erroneous character is read. LSR[4:1] bits are set until software
reads the LSR.
See Section 10.4.5 for details on using the DMA to receive data.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOE
TDRQ
TEMT
DR
OE
PE
FE
reserved
BI
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0
31:8 — reserved
FIFO Error Status: In non-FIFO mode, this bit is 0. In FIFO Mode, FIFOE is set to 1 when
there is at least one parity error, framing error, or break indication for any of the characters
in the FIFO. A processor read to the LSR does not reset this bit. FIFOE is reset when all
erroneous characters have been read from the FIFO. If DMA requests are enabled (IER bit
7 is set to 1) and FIFOE is set to 1, the error interrupt is generated and no receive DMA
7 FIFOE request is generated even when the receive FIFO reaches the trigger level. Once the errors
have been cleared by reading the FIFO, DMA requests are re-enabled automatically. If
DMA requests are not enabled (IER bit7 is set to 0), FIFOE set to 1 does not generate an
error interrupt.
0 – No FIFO or no errors in receiver FIFO
1 – At least one character in receiver FIFO has errors
Transmitter Empty: Set when the Transmit Holding Register and the Transmitter Shift
Register are both empty. It is cleared when either the Transmit Holding Register or the
Transmitter Shift Register contains a data character. In FIFO mode, TEMT is set when the
6 TEMT transmitter FIFO and the Transmit Shift Register are both empty.
0 – There is data in the Transmit Shift Register, the Transmit Holding Register, or the FIFO
1 – All the data in the transmitter has been shifted out
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOE
TDRQ
TEMT
OE
DR
PE
FE
reserved
BI
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0
Transmit Data Request: Indicates that the UART is ready to accept a new character for
transmission. In addition, this bit causes the UART to issue an interrupt to the processor
when the transmit data request interrupt enable is set high and generates the DMA request
to the DMA controller if DMA requests and FIFO mode are enabled. The TDRQ bit is set
when a character is transferred from the Transmit Holding register into the Transmit Shift
register. The bit is cleared with the loading of the Transmit Holding Register. In FIFO mode,
5 TDRQ TDRQ is set to 1 when half of the characters in the FIFO have been loaded into the Shift
register or the RESETTF bit in FCR has been set. It is cleared when the FIFO has more
than half data. If more than 64 characters are loaded into the FIFO, the excess characters
are lost.
0 – There is data in Holding register or FIFO waiting to be shifted out
1 – Transmit FIFO has half or less than half data
Break Interrupt: BI is set when the received data input is held low for longer than a full word
transmission time (that is, the total time of Start bit + data bits + parity bit + stop bits). The
Break indicator is reset when the processor reads the LSR. In FIFO mode, only one
character equal to 0x00, is loaded into the FIFO regardless of the length of the break
4 BI condition. BI shows the break condition for the character at the front of the FIFO, not the
most recently received character.
0 – No break signal has been received
1 – Break signal received
Framing Error: FE indicates that the received character did not have a valid stop bit. FE is
set when the bit following the last data bit or parity bit is detected to be 0. If the LCR had
been set for two stop bit mode, the receiver does not check for a valid second stop bit. The
FE indicator is reset when the processor reads the LSR. The UART will resynchronize after
a framing error. To do this it assumes that the framing error was due to the next start bit, so
3 FE it samples this “start” bit twice and then reads in the “data”. In FIFO mode, FE shows a
framing error for the character at the front of the FIFO, not for the most recently received
character.
0 – No Framing error
1 – Invalid stop bit has been detected
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOE
TDRQ
TEMT
OE
DR
PE
FE
reserved
BI
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0
Parity Error: Indicates that the received data character does not have the correct even or
odd parity, as selected by the even parity select bit. PE is set upon detection of a parity
error and is cleared when the processor reads the LSR. In FIFO mode, PE shows a parity
2 PE error for the character at the front of the FIFO, not the most recently received character.
0 – No Parity error
1 – Parity error has occurred
Overrun Error: In non-FIFO mode, indicates that data in the Receive Buffer Register was
not read by the processor before the next character was received. The new character is
lost. In FIFO mode, OE indicates that all 64 bytes of the FIFO are full and the most recently
1 OE received byte has been discarded. The OE indicator is set upon detection of an overrun
condition and cleared when the processor reads the LSR.
0 – No data has been lost
1 – Received data has been lost
Data Ready: Set when a complete incoming character has been received and transferred
into the Receive Buffer Register or the FIFO. In non-FIFO mode, DR is cleared when the
receive buffer is read. In FIFO mode, DR is cleared if the FIFO is empty (last character has
0 DR been read from RBR) or the FIFO is reset with FCR[RESETRF].
0 – No data has been received
1 – Data is available in RBR or the FIFO
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOOP
OUT2
OUT1
DTR
RTS
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Read/Write
31:5 — reserved
Loopback Mode: This bit provides a local loopback feature for diagnostic testing of the
UART. When LOOP is set to a logic 1, the following will occur: The transmitter serial output
is set to a logic 1 state. The receiver serial input is disconnected from the pin. The output of
the Transmitter Shift register is “looped back” into the receiver shift register input. The four
modem control inputs (nCTS, nDSR, nDCD, and nRI) are disconnected from the pins and
the modem control output pins (nRTS and nDTR) are forced to their inactive state.
Coming out of the loopback mode may result in unpredictable activation of the delta bits
(bits 3:0) in the Modem Status Register. It is recommended that MSR is read once to clear
the delta bits in the MSR.
Loopback mode must be configured before the UART is enabled.
The lower four bits of the MCR are connected to the upper four Modem Status Register
bits:
4 LOOP
• DTR = 1 forces DSR to a 1
• RTS = 1 forces CTS to a 1
• OUT1 = 1 forces RI to a 1
• OUT2= 1 forces DCD to a 1
In loopback mode, data that is transmitted is immediately received. This feature allows the
processor to verify the transmit and receive data paths of the UART. The transmit, receive
and modem control interrupts are operational, except the modem control interrupts are
activated by MCR bits, not the modem control pins. A break signal can also be transferred
from the transmitter section to the receiver section in loopback mode.
0 – normal UART operation
1 – loopback mode UART operation
OUT2 signal control: OUT2 connects the UART’s interrupt output to the Interrupt Controller
unit. When LOOP=0:
0 – UART interrupt is disabled.
3 OUT2 1 – UART interrupt is enabled.
When LOOP=1, interrupts always go to the processor:
0 – MSR[DCD] forced to a 0
1 – MSR[DCD] forced to a 1
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOOP
OUT2
OUT1
DTR
RTS
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Read/Write
Test bit. This bit is used only in Loopback mode. It is ignored otherwise.
2 OUT1 0 – Force MSR[RI] to 0
1 – Force MSR[RI] to 1
Request to Send.
1 RTS 0 – nRTS pin is 1
1 – nRTS pin is 0
Data Terminal Ready.
0 DTR 0 – nDTR pin is 1
1 – nDTR pin is 0
The status of the modem control lines do not affect the FIFOs. To use these lines for flow control,
IER[MIE] must be set. When an interrupt on one of the flow control pins occurs, the interrupt
service routine must disable the UART. The UART will continue transmission/reception of the
current character and then stop. The contents of the FIFOs will be preserved. If the UART is re-
enabled, transmission will continue where it stopped. Interrupts from the flow control pins will not
come through the UART unit if the unit is disabled. When disabling the unit because of flow
control, interrupts must be enabled in the processor Interrupt Controller for the flow control pins.
The Interrupt Controller will still trigger interrupts if the pins are in Alternate Function Mode.
Note: When bit 0, 1, 2, or 3 is set, a Modem Status interrupt is generated if IER[MIE] is set.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DDCD
DDSR
DCTS
TERI
DCD
DSR
CTS
RI
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31:8 — reserved
Data Carrier Detect: Complement of the Data Carrier Detect (nDCD) input. Equivalent to
MCR[OUT2] if MCR[LOOP] is set.
7 DCD
0 – nDCD pin is 1
1 – nDCD pin is 0
Ring Indicator: Complement of the Ring Indicator (nRI) input. Equivalent to MCR[OUT1] if
MCR[LOOP] is set.
6 RI
0 – nRI pin is 1
1 – nRI pin is 0
Data Set Ready: Complement of the Data Set Ready (nDSR) input. Equivalent to
MCR[DTR] if MCR[LOOP] is set.
5 DSR
0 – nDSR pin is 1
1 – nDSR pin is 0
Clear To Send: Complement of the Clear to Send (nCTS) input. Equivalent to MCR[RTS] if
MCR[LOOP] is set.
4 CTS
0 – nCTS pin is 1
1 – nCTS pin is 0
Delta Data Carrier Detect:
3 DDCD 0 – No change in nDCD pin since last read of MSR
1 – nDCD pin has changed state
Trailing Edge Ring Indicator:
2 TERI 0 – nRI pin has not changed from 0 to 1 since last read of MSR
1 – nRI pin has changed from 0 to 1
Delta Data Set Ready:
1 DDSR 0 – No change in nDSR pin since last read of MSR
1 – nDSR pin has changed state
Delta Clear To Send:
0 DCTS 0 – No change in nCTS pin since last read of MSR
1 – nCTS pin has changed state
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SP
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31:8 — reserved
Scratch Pad
7:0 SP
No effect on UART functionality
The receiver line status interrupt (IIR = 0xC6) has the highest priority and the received data
available interrupt (IIR = 0xC4) is lower. The line status interrupt occurs only when the character at
the front of the FIFO has errors.
The data ready bit (DR in the LSR) is set when a character is transferred from the shift register to
the Receive FIFO. The DR bit is cleared when the FIFO is empty.
After the processor reads one character from the receive FIFO or a new start bit is received, the
character timeout indication interrupt is cleared and the timeout is reset. If a character timeout
indication interrupt has not occurred, the timeout is reset when a new character is received or the
processor reads the receive FIFO.
The transmit DMA request is generated when the transmit FIFO is at least half empty and
IER[DMAE] is set. After the transmit DMA request is generated, the DMA Controller (DMAC)
writes data to the FIFO. For each DMA request, the DMAC sends 8, 16, or 32 bytes of data to the
FIFO. The number of bytes to be transmitted is programmed in the DMA channel.
The receive DMA request is generated when the receive FIFO reaches its trigger level with no
errors in its entries and the IER[DMAE] is set. A receive DMA request is not generated if the
trigger level is set to 1.
The DMAC then reads data from the FIFO. For each DMA request, the DMA controller can read 8,
16 or 32 bytes of data from the FIFO. The number of bytes to be read is programmed in the DMA
channel.
Note: Do not program the channel to read more data than the FIFO trigger level.
If DMA requests are enabled and an erroneous character is received, the receive DMA requests are
automatically disabled and an error interrupt is generated. The erroneous character is placed in the
receive FIFO. If the UART was requesting a receive DMA transaction, the request is immediately
cancelled. This prevents the DMAC from attempting to access the FIFOs while software clears the
error.
When all the errors in the receive FIFO are cleared, receive DMA requests are automatically
enabled and can be generated when the trigger level is reached.
Note: Ensure that the DMAC has finished previous receive DMA requests before the error interrupt
handler begins to clear the errors from the FIFO.
The SIR interface does not contain the actual IR LED driver or the receiver amplifier. The I/O pins
attached to the SIR only have digital CMOS level signals. The SIR supports two-way
communication, but full duplex communication is not possible because reflections from the
transmit LED enter the receiver. The SIR interface supports frequencies up to 115.2 kbps. Because
the input clock is 14.7456 MHz, the baud divisor must be eight or more.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCVEIR
XMODE
XMITIR
RXPL
TXPL
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31:5 — reserved
Receive Data Polarity:
4 RXPL 0 – SIR decoder interprets positive pulses as zeroes
1 – SIR decoder interprets negative pulses as zeroes
Transmit Data Polarity:
3 TXPL 0 – SIR encoder generates a positive pulse for a data bit of zero
1 – SIR encoder generates a negative pulse for a data bit of zero
Transmit Pulse Width Select: When XMODE is cleared, the UART 16X clock is used to
clock the IRDA transmit and receive logic. When XMODE is set, the transmit encoder
generates 1.6 µs pulses (that are 3/16 of a bit time at 115.2 kbps) instead of pulses 3/16 of
2 XMODE a bit time wide, and the receive decoder expects pulses will be 1.6µs wide also.
0 – Transmit pulse width is 3/16 of a bit time wide
1 – Transmit pulse width is 1.6 µs
Receiver SIR Enable: When RCVEIR is set, the signal from the RXD pin is processed by
the IRDA decoder before it is fed to the UART. If RCVEIR is cleared, then all clocking to the
1 RCVEIR IRDA decoder is blocked and the RXD pin is fed directly to the UART.
0 – Receiver is in UART mode
1 – Receiver is in infrared mode
Transmitter SIR Enable: When XMITIR is set to a 1, the normal TXD output from the UART
is processed by the IRDA encoder before it is fed to the device pin. If XMITIR is cleared, all
clocking to the IRDA encoder is blocked and the UART’s TXD signal is connected directly
to the device pin.
0 XMITIR When Transmitter SIR Enable is set, the TXD output pin, which is in a normally high default
state, will switch to a normally low default state. This can cause a false start bit unless the
infrared LED is disabled before XMITIR is set.
0 – Transmitter is in UART mode
1 – Transmitter is in infrared mode
10.4.6.2 Operation
The SIR modulation technique works with 5-, 6-, 7-, or 8-bit characters with an optional parity bit.
The data is preceded by a zero value start bit and ends with one or more stop bits. The encoding
scheme is to set a pulse 3/16 of a bit wide in the middle of every zero bit and send no pulses for bits
that are ones. The pulse for each zero bit must occur, even for consecutive bits with no edge
between them.
START
UART TRANSMIT
BIT 1 0 0 0 1 0 1 0 STOP
SHIFT VALUE
BIT
IR ENCODER OUTPUT
(TXD PIN VALUE)
IR DECODER OUTPUT
START
UART RECEIVE 1 0 0 0 1 1 0 STOP
BIT 0
SHIFT VALUE BIT
The top line in Figure 10-3 shows an asynchronous transmission as it is sent from the UART. The
second line shows the pulses generated by the IR encoder at the TXD pin. A pulse is generated in
the middle of the START bit and any data bit that is a zero. The third line shows the values received
at the RXD input pin. The fourth line shows the receive decoder’s output. The receive decoder
drives the receiver data line low when it detects a pulse. The bottom line shows how the UART’s
receiver interprets the decoder’s action. This last line is the same as the first, but it is shifted half a
bit period.
When XMODE is cleared, each zero bit has a pulse width of 3/16 of a bit time. When XMODE is
set, a pulse of 1.6 µs is generated in the middle of each zero bit. The shorter infrared pulse
generated when XMODE is set reduces the LEDs’ power consumption. At 2400 bps, the LED is
normally on for 78 µs for each zero bit that is transmitted. When XMODE is set, the LED is on
only 1.6 µs. XMode changes the behavior of the receiver. The receiver expects pulses of the correct
pulse width. If the transceiver crops the incoming pulse, then Xmode must be set.
Note:
Figure 10-4. XMODE Example
1 7 11 16
16X Baud Clock
(14.7456 MHz)
Note: Note: The SIR TXD output pin is automatically held deasserted when the RCVEIR bit is set.
Before setting the RCVEIR bit, check that the TEMT bit is 1. While receiving, any data placed in
the Transmit FIFO will not be held. Only add data to the Transmit FIFO while not receiving. To
start transmission, the RCVEIR bit must be cleared.
To disable SIR, disable the IrDA LED first, if possible. Second, set the TXD GPIO pin to the
infrared LED's default state using the GPCR/GPSR registers. Next, change the TXD pin from
alternate function to GPIO mode. Now the SIR can be disabled without causing spurious transmit
pulses.
The FICP shares GPIO pins for transmit and receive data with the Standard UART. Only one of the
ports can be used at a time. To support a variety of IrDA transceivers, both the transmit and receive
data pins can be individually configured to communicate using normal or active low data.
The transmit/receive data is modulated according to the 4PPM IrDA standard and converted to
serial or parallel data. The modulation technique and the frame format are discussed in the sections
that follow.
Timeslots
1 2 3 4
Data = 0b00
Data = 0b01
Data = 0b10
Data = 0b11
Reordered 0 1 0 0 1 1 1 0
Nibbles
Nibble 0 Nibble 1 Nibble 2 Nibble 3
Chips 1 2 3 4
Timeslots
1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4
125 ns
4PPM
Data
48 MHz
Receive data sample counter frequency = 6/pulse width. Each timeslot is sampled on the third clock.
Address Control
Preamble Start Flag Data CRC-32 Stop Flag
(optional) (optional)
Preamble - | 1000 | 0000 | 1010 | 1000 |... repeated at least 16 times
Start flag - | 0000 | 1100 | 0000 | 1100 | 0110 | 0000 | 0110 | 0000 |
Stop Flag - | 0000 |1100 | 0000 | 1100 | 0000 | 0110 | 0000 | 0110 |
The preamble, start, and stop flags are a mixture of chips that contain 0, 1, or 2 pulses in their
timeslots. Chips with 0 and 2 pulses are used to construct flags because the chips represent invalid
data bit pairings. The preamble contains 16 repeated transmissions of the chips: 1000 0000 1010
1000. The start flag contains one transmission of eight chips: 0000 1100 0000 1100 0110 0000
0110 0000. The stop flag contains one transmission of eight chips: 0000 1100 0000 1100 0000
0110 0000 0110. The address, control, data, and CRC-32 use the standard 4PPM chip encoding to
represent two bits per chip.
For reception, FICP control register 1 (ICCR1) is used to program a unique receive address. The
AME bit in the FICP control register 0 (ICCR0) determines the address match function. The
received frames’ addresses are stored in the receive FIFO with normal data.
If the calculated value does not match the expected value, the CRC error bit that corresponds to the
last data byte received is set. When this byte reaches the trigger level range, an interrupt is
generated.
Note: Unlike the address, control, and data fields, the 32-bit inverted CRC value is transmitted and
received most significant nibble first.
CRC ( x ) = ( x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 )
After the FICP is enabled, the receiver logic begins and selects an arbitrary chip boundary, uses a
serial shifter to receive four incoming 4PPM chips from the receive data pin, and latches and
decodes the chips one at a time. If the chips do not have the correct preamble, the timeslot
counter’s clock skips one 8-MHz period and effectively delays the timeslot count by one. This
process is called hunt mode and is repeated until the chips have the correct preamble, which
indicates that the timeslot counter is synchronized. The preamble can be repeated as few as 16
times or can be continuously repeated to indicate an idle transmit line.
After 16 preambles are transmitted, the start flag is received. The start flag is eight chips long. If
any portion of the start flag does not match the encoding, the receive logic signals a framing error
and the receive logic returns to hunt mode.
When the correct start flag is recognized, each following group of four chips is decoded into a data
byte and placed in a 5-byte temporary FIFO that is used to prevent the CRC from being placed in
the receive FIFO. When the temporary FIFO is full, data values are transferred to the receive FIFO
one at a time. A frame’s first data byte is the address. If receiver address matching is enabled, the
received address is compared to the address in the address match value field in ICCR1. If the
values match or the incoming address contains all ones, all following data bytes, including the
address byte, are stored in the receive FIFO. If the values do not match, the receiver logic does not
store any data in the receive FIFO, ignores the remainder of the frame, and searches for the next
preamble. If receiver address matching is not enabled, the frame’s first data byte is stored in the
FIFO as normal data. The frame’s second data byte can contain an optional control field and must
be decoded in software.
The IrDA standard limits frames to any amount of data up to a 2047 bytes (including the address
and control bytes). The FICP does not limit frame size. Software must ensure that each incoming
frame does not exceed 2047 bytes.
When the receive FIFO reaches its trigger level, an interrupt (if enabled) and DMA transfer request
(if no errors are detected in the data) are signalled. If the data is not removed quickly enough to
prevent the FIFO from completely filling, the receive logic attempts to place additional data into
the full FIFO and an overrun error is signalled. When the FIFO is full, all subsequent data bytes
received are lost and all FIFO contents remain intact.
If the data field contains any invalid chips (such as 0011, 1010, 1110) the frame aborts and the
oldest byte in the temporary FIFO is moved to the receive FIFO, the remaining temporary FIFO
entries are discarded, the end-of-frame (EOF) tag is set in the FIFO entry that holds the last valid
byte of data, and the receiver logic searches for the preamble.
The receive logic continuously searches for the 8-chip stop flag. When the stop flag is recognized,
the last byte that was placed within the receive FIFO is flagged as the frame’s last byte and the data
in the temporary FIFO is removed and used as the CRC value for the frame. The receive logic
compares the frame’s CRC value to the CRC-32 value, which is continuously calculated from the
incoming data stream. If CRC and CRC-32 values do not match, the last byte that was placed in the
receive FIFO is also tagged with a CRC error. The frame’s CRC value is not placed in the receive
FIFO. If the stop flag is not properly detected, an abort is signalled.
If software disables the FICP’s receiver while it is operating, the data byte being received stops
immediately, the serial shifter and receive FIFO are cleared, the System Integration Unit (SIU)
takes control of the receive data pin, and the clocks used by the receive logic are shut off to
conserve power. The receive data input polarity must be reprogrammed if the receive data pin is
used as a GPIO input.
A minimum of 16 preambles are transmitted for each frame. If data is not available after the
sixteenth preamble, additional preambles are transmitted until a byte of valid data resides in the
bottom of the transmit FIFO. The preambles are followed by the start flag and the data from the
transmit FIFO. Groups of four chips (eight bits) are encoded and loaded in a serial shift register.
The contents of the serial shift register are sent out on the transmit data pin, which is clocked by the
8-MHz baud clock. The preamble, start and stop flags, and CRC value are transmitted
automatically.
When the transmit FIFO has 32 or more empty entries, an interrupt (if enabled) and DMA service
request are sent. If new data does not arrive quickly enough to prevent the FIFO from becoming
empty, the transmit logic attempts to transfer additional data from the empty FIFO. Software
determines whether to interpret the data underrun (a lack of data) as a signal of normal frame
completion or as an unexpected frame termination.
When software selects normal frame completion and an underrun occurs, the transmit logic
transmits the CRC value that was calculated during data transmission, including the address and
control bytes, followed by the stop flag that marks the end of the frame. The transmitter then
continuously transmits preambles until data is available in the FIFO. When data is available, the
transmitter starts to transmit the next frame.
When software selects unexpected frame termination and an underrun occurs, the transmit logic
transmits an abort and interrupts the CPU. The transmitter continues to send the abort until data is
available in the transmit FIFO. When data is available, the FICP transmits 16 preambles and a start
flag and starts the new frame. The off-chip receiver can choose to ignore the abort and continue to
receive data or signal the FICP to attempt to transmit the aborted frame again.
At the end of each transmitted frame, the FICP sends a pulse called the serial infrared interaction
pulse (SIP). A SIP must be sent at least every 500 ms to ensure that low-speed devices (115.2 Kbps
and slower) do not interfere with devices that transmit at higher speeds. The SIP simulates a start
bit that causes low-speed devices to stay off the air for at least another 500 ms. The SIP pulse
forces the transmit data pin high for 1.625 µs and low for 7.375 µs (the total SIP period is 9.0 µs).
After the SIP period, the preamble is transmitted continuously to indicate to the off-chip receiver
that the FICP’s transmitter is in the idle state. The preamble is transmitted until new data is
available in the transmit FIFO or the FICP’s transmitter is disabled. At least one frame must be
completed every 500 ms to ensure that an SIP pulse can keep low-speed devices from interrupting
the transmission. Because most IrDA compatible devices produce an SIP after each frame
transmitted, software only needs to ensure that a frame is either transmitted or received by the FICP
every 500 ms. Frame length does not represent a significant portion of the 500 ms timeframe in
which an SIP must be produced. At 4.0 Mbps, the longest frame allowed is 16,568 bits, which
takes just over 4 ms to transmit. The FICP also issues an SIP when the transmitter is first enabled.
This ensures that low-speed devices do not interfere as the FICP transmits its data.
If software disables the FICP’s transmitter during operation, data transmission stops immediately,
the serial shifter and transmit FIFO are cleared, and the SIU takes control of the transmit data pin.
The transmit data output’s polarity must be properly reprogrammed if the pin is used as a GPIO
output.
When the transmit FIFO has 32 or more empty bytes, the transmit DMA request and an interrupt (if
enabled) are generated and tell the processor to send more data to the FIFO. When the transmit
FIFO is full, any more data from the processor is lost. When the receive FIFO reaches its trigger
level (programmed in ICCR2), the receive DMA request (if no errors are found within the entries)
and an interrupt (if enabled) are generated and tell the processor to remove the data from the FIFO.
If an error is found in the FIFO’s trigger level range, DMA requests are disabled and an interrupt is
generated to ensure that the DMAC does not read the error bytes.
The number of bytes being transferred for each DMA request is programmed in the DMAC and
can be 8, 16, or 32 bytes. The receive FIFO’s trigger level must be set so the FIFO has enough data
for the DMAC to read. The transmit FIFO does not have programmable trigger levels. Its DMA
request is generated when the FIFO has 32 or more empty bytes, regardless of the DMA transfer
size.
The DMA controller must not service the receive FIFO when the processor tries to respond to a
receive error interrupt. The error interrupt may be set high before the DMA controller finishes the
previous request. The processor can not remove the error bytes until the DMAC has completed its
transaction.
The core must also read bytes from the FIFO until ICSR0[EIF] is cleared if there are errors in FIFO
entries below the DMA trigger level. When the entries below the DMA trigger level no longer
contain status flags, DMA requests are enabled.
The control registers determine: IrDA transmission rate, address match value, how transmit FIFO
underruns are handled, normal or active low transmit and receive data, whether transmit and
receive operations are enabled, the FIFO interrupt service requests, receive address matching, and
loopback mode.
The data register addresses the top of the transmit FIFO and the bottom of the receive FIFO. Reads
to the data register access the receive FIFO. Writes to the data register access the transmit FIFO.
The status registers contain: CRC, overrun, underrun, framing, and receiver abort errors; the
transmit FIFO service request; the receive FIFO service request; and end-of-frame conditions.
Each of these hardware-detected events signals an interrupt request to the interrupt controller. The
status registers also contain flags for transmitter busy, receiver synchronized, receive FIFO not
empty, and transmit FIFO not full (no interrupt generated).
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AME
LBM
RXE
TUS
TXE
RIE
ITR
TIE
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:8] — reserved
Address match enable.
Receive logic will compare the address of the incoming frames to the Address Match Value
field in ICCR1.
7 AME
0 = Disable receiver address match function. Store data in receive FIFO.
1 = Enable receiver address match function. Do not put data in the receive FIFO unless
address is recognized or address is the broadcast address.
Transmit FIFO interrupt enable.
0 = Transmit FIFO service request, ICSR0[TFS], does not generate an interrupt.
6 TIE 1 = Transmit FIFO service request generates an interrupt.
Setting TIE does not clear TFS or prevent TFS from being set or cleared by the transmit
FIFO. TIE does not affect transmit FIFO DMA requests.
Receive FIFO interrupt enable.
0 = Receive FIFO service request, ICSR0[RFS], does not generate an interrupt.
5 RIE 1 = Receive FIFO service request generates an interrupt
Setting RIE does not clear RFS or prevent RFS from being set or cleared by the receive
FIFO. RIE does not affect receive FIFO DMA requests.
Receive enable.
0 = FICP receive logic disabled.
1 = FICP receive logic enabled if ICCR0[ITR] is set.
All other control bits must be configured before setting RXE. If RXE is cleared while
receiving data then reception is stopped immediately, all data within the receive FIFO and
4 RXE
serial input shifter is cleared, and control of the receive data pin is given to the SIU.
While communication is normally half-duplex, it is possible to transmit and receive data at
the same time. This is used for testing in Loopback Mode.
If RXE is used to clear the receive FIFO, check ICSR1[RNE] to ensure the receive FIFO is
clear before re-enabling the receiver.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AME
LBM
RXE
TUS
TXE
RIE
ITR
TIE
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Transmit enable.
0 = FICP transmit logic disabled.
1 = FICP transmit logic enabled if ICCR0[ITR] is set.
All other control bits must be configured before TXE is set. An SIP is transmitted
immediately after the transmitter is enabled. If the transmit FIFO is empty, preambles are
sent until data is placed in the FIFO.
3 TXE If TXE is cleared while it transmits data, transmission stops immediately, all data in the
transmit FIFO and serial output shifter is cleared, and the SIU takes control of the transmit
data pin.
While communication is normally half-duplex, it is possible to transmit and receive data at
the same time. Duplex communication is used for testing in Loopback Mode.
If TXE is used to clear the transmitter, check ICSR1[TBY] to ensure the transmitter is not
busy before the transmitter is re-enabled.
Transmit FIFO underrun select.
A transmit FIFO underrun can either end the current frame normally, or transmit an abort.
0 = Transmit FIFO underrun causes CRC, stop flag, and SIP to be transmitted, and masks
2 TUS transmit underrun interrupt generation.
1 = Transmit FIFO underrun causes abort to be transmitted, and generates an interrupt.
Clearing ICCR0[TUS] does not affect the current state of ICSR0[TUR] or prevent TUR from
being set or cleared by the transmit FIFO. After an abort, a SIP is transmitted followed by
16 preambles. Preambles continue until data is in the FIFO.
Loopback mode.
Used for testing FICP.
1 LBM
0 = Normal FICP operation enabled.
1 = Output of transmit serial shifter is connected to input of receive serial shifter.
IrDA transmission.
0 ITR 0 = ICP unit is not enabled.
1 = ICP unit is enabled.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved AMV
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:8] — reserved
Address match value.
The 8-bit value used by receiver logic to compare to address of incoming frames. If AME=1
and AMV matches the address of the incoming frame, store the frame address, control,
[7:0] AMV
and data in receive FIFO. If the address does not match, ignore the frame and search for
the next preamble.
The broadcast address 0xFF in the incoming frame always generates a match.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIG
RXP
TXP
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0
[31:4] — reserved
Receive pin polarity select.
0 = Data from the receive data pin is inverted before being used by the FICP unit.
3 RXP
1 = Data from the receive data pin to the FICP unit is not inverted.
Set on reset.
Transmit pin polarity select.
0 = Data from the FICP is inverted before being sent to the transmit data pin.
2 TXP
1 = Data from the FICP is not inverted before being sent to the transmit data pin.
Set on reset.
Receive FIFO trigger level
The receive FIFO generates service requests when the FIFO has reached the trigger level
and has no errors in its data. The DMA controller data transfer size must be set to the same
size as the Receive FIFO trigger level. To change the trigger level, the Receive FIFO must
be disabled.
[1:0] TRIG
0b00- receive FIFO service request is generated when the FIFO has 8 bytes or more
0b01- receive FIFO service request is generated when the FIFO has 16 bytes or more
0b10- receive FIFO service request is generated when the FIFO has 32 bytes or more
0b11- reserved
Reads to ICDR access the lower 8 bits of the receive FIFO’s bottom entry. As data enters the top of
the receive FIFO, bits 8 – 10 are used as tags to indicate conditions that occur as each piece of data
is received. The tag bits are transferred down the FIFO with the data byte that encountered the
condition. When data reaches the bottom of the FIFO, bit 8 of the FIFO entry is transferred to the
end-of-frame (EOF) flag, bit 9 to the CRC error (CRE) flag, and bit 10 to the receiver overrun
(ROR) flag. All these flags are in FICP status register 1. These flags can be read to determine
whether the value at the bottom of the FIFO represents the frame’s last byte or an error that was
encountered during reception. After the flags are checked, the FIFO value can be read. This causes
the data in the next location of the receive FIFO to be transferred to the bottom entry and its EOF,
CRE, and ROR bits to be transferred to the status register.
The end/error in FIFO (EIF) flag is set in status register 0 when a tag bit is set in any of the receive
FIFO’s bottom eight, 16, or 32 entries, as determined by the trigger level. The EIF flag is cleared
when no error bits are set in the FIFO’s bottom entries. When EIF is set, an interrupt is generated
and the receive FIFO DMA request is disabled. Software must empty the FIFO and check for the
EOF, CRE, and ROR error flags in ICSR1 before it removes each data value from the FIFO. After
each entry is removed, the EIF bit must be checked to determine if any set end or error tag remains
and the procedure is repeated until all set tags are flushed from the FIFO’s bottom entries. When
EIF is cleared, DMA service for the receive FIFO is re-enabled.
Both FIFOs are cleared when the processor is reset. The transmit FIFO is cleared when TXE is 0.
The receive FIFO is cleared when RXE is 0.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DATA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:8] — reserved
Top/bottom of transmit/receive FIFO.
[7:0] DATA Read - Read data from front of receive FIFO
Write - Place data at end of transmit FIFO
If a bit signals an interrupt request, it signals the interrupt request as long as the bit is set. When the
bit is cleared, the interrupt is cleared. Read/write bits are called status bits. Read-only bits are
called flags. Status bits that must be cleared by software after they are set by hardware are called
sticky status bits. Writing a 1 to a sticky status bit clears it. Writing a 0 to a sticky status bit has no
effect. Read-only flags are set and cleared by hardware. Writes to read-only flags have no effect.
Some bits that cause interrupts have corresponding mask bits in the control registers.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TUR
RAB
FRE
RFS
TFS
EIF
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:6] — reserved
Framing error.
5 FRE 0 = No framing errors encountered in the receipt of this data.
1 = Framing error occurred. A preamble was followed by something other than another
preamble or start flag, request interrupt.
Receive FIFO service request (read-only).
4 RFS 0 = Receive FIFO has not reached it trigger level or receiver disabled.
1 = Receive FIFO has reached its trigger level and receiver is enabled. DMA service
request signalled. Interrupt request signalled if not masked by ICCR0[RIE].
Transmit FIFO service request (read-only).
3 TFS 0 = Transmit FIFO has more than 96 entries of data or transmitter disabled.
1 = Transmit FIFO has 96 or less entries of data and transmitter is enabled. DMA service
request signalled. Interrupt request signalled if not masked by ICCR0[TIE].
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RAB
TUR
FRE
RFS
TFS
EIF
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Receiver abort.
0 = No abort has been detected for the incoming frame.
2 RAB 1 = Abort detected during receipt of incoming frame. Two or more chips containing no
pulses or any invalid chips were detected on the receive pin. EOF bit set on last piece
of “good” data received before the abort, interrupt requested.
Transmit FIFO underrun.
0 – Transmit FIFO has not experienced an underrun.
1 TUR 1 – Transmit logic attempted to fetch data from transmit FIFO while it was empty. Interrupt
request signalled if not masked by ICCR0[TUS].
Underruns are not generated when the FICP transmitter is first enabled and is idle.
End/error in FIFO (read-only).
0 – Bits 8–10 are not set within any of the entries at or below the trigger level of the receive
FIFO. Receive FIFO DMA service requests are enabled.
0 EIF 1 – One or more tag bits (8 – 10) are set within the entries at or below the trigger level of
the receive FIFO. Request interrupt, disable receive FIFO DMA service requests.
This interrupt is not maskable in the FICP. Once the bad bytes have been removed from
the FIFO and EIF is cleared, DMA requests are automatically enabled.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ROR
CRE
RNE
EOF
RSY
TBY
TNF
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
[31:7] — reserved
Receive FIFO overrun (read-only).
0 = Receive FIFO has not experienced an overrun.
1 = Receive logic attempted to place data into receive FIFO while it was full. Data received
6 ROR
after the FIFO is full are lost.
Each time an 11-bit value reaches the bottom of the receive FIFO, bit 10 from the last FIFO
entry is transferred to the ROR bit.
CRC error (read-only).
0 = CRC not encountered yet or no CRC check errors encountered in the receipt of data.
1 = CRC calculated on the incoming data. Does not match CRC value contained within
5 CRE
the received frame.
Each time an 11-bit value reaches the bottom of the receive FIFO, bit 9 from the last FIFO
entry is transferred to the CRE bit.
End of frame (read-only).
0 = Current frame has not completed.
1 = The value at the bottom of the receive FIFO is the last byte of data within the frame,
4 EOF
including aborted frames.
Each time an 11-bit value reaches the bottom of the receive FIFO, bit 8 from the last FIFO
entry is transferred to the EOF bit.
Transmit FIFO not full (read-only).
3 TNF 0 = Transmit FIFO is full.
1 = Transmit FIFO is not full (no interrupt generated).
Receive FIFO not empty (read-only).
2 RNE 0 = Receive FIFO is empty.
1 = Receive FIFO is not empty (no interrupt generated).
Transmitter busy flag (read-only).
1 TBY 0 = Transmitter is idle (continuous preambles) or disabled.
1 = Transmit logic is currently transmitting a frame (address, control, data, CRC, or start/
stop flag). No interrupt generated.
Receiver synchronized flag (read-only).
0 RSY 0 = Receiver is in hunt mode or is disabled.
1 = Receiver logic is synchronized with the incoming data (no interrupt generated).
The UDC transmits serial information that contains layers of communication protocols. Fields are
the most basic protocol. UDC fields include: sync, packet identifier (PID), address, endpoint, frame
number, data, and Cyclic Redundancy Check (CRC). Fields are combined to produce packets. A
packet’s function determines the combination and number of fields that make up the packet. Packet
types include: token, start of frame, data, and handshake. Packets are assembled into groups to
produce transactions. Transactions fall into four groups: bulk, control, interrupt, and isochronous.
Endpoint 0 is used only to communicate the control transactions that configure the UDC. Endpoint
0’s responsibilities include: connection, address assignment, endpoint configuration, bus
enumeration, and disconnection.
The UDC uses a dual-port memory to support FIFO operations. Each Bulk and Isochronous
Endpoint FIFO structure is double buffered to enable the endpoint to process one packet as it
assembles another. The DMA and the Megacell can fill and empty the FIFOs. An interrupt or DMA
service request is generated when a packet has been received. The DMA engine services the UDC
FIFOs in 32-byte increments. Interrupts are also generated when the FIFO encounters a short
packet or zero-length packet. Endpoint 0 has a 16-entry long, 8-bit wide FIFO that can only be read
or written by the processor.
For endpoints 1-15, the UDC uses its dual-ported memory to hold data for a Bulk OUT transaction
while the transaction is checked for errors. If the Bulk OUT transaction data is invalid, the UDC
sends a NAK handshake to request the host to resend the data. The software is not notified that the
OUT data is invalid until the Bulk OUT data is received and verified. If the host sends a NAK
handshake in response to a Bulk IN data transmission, the UDC resends the data. Because the FIFO
maintains a copy of the data, the software does not have to reload the data.
The external pins dedicated to the UDC interface are UDC+ and UDC-. The USB protocol uses
differential signalling between the two pins for half-duplex data transmission. A 1.5 kΩ pull-up
resistor must be connected to the USB cable’s D+ signal to pull the UDC+ pin high when it is not
driven. Pulling the UDC+ pin high when it is not driven allows the UDC to be a high-speed,
12-Mbps device and provides the correct polarity for data transmission. The serial bus uses
differential signalling to transmit multiple states simultaneously. These states are combined to
produce transmit data and various bus conditions, including: Idle, Resume, Start of Packet, End of
Packet, Disconnect, Connect, and Reset.
0 Control IN/OUT 16
1 Bulk IN 64x2
2 Bulk OUT 64x2
3 Isochronous IN 256x2
4 Isochronous OUT 256x2
5 Interrupt IN 8
6 Bulk IN 64x2
7 Bulk OUT 64x2
8 Isochronous IN 256x2
9 Isochronous OUT 256x2
10 Interrupt IN 8
11 Bulk IN 64x2
12 Bulk OUT 64x2
13 Isochronous IN 256x2
14 Isochronous OUT 256x2
15 Interrupt IN 8
Data flow is relative to the USB host. IN packets represent data flow from the UDC to the host.
OUT packets represent data flow from the host to the UDC.
The FIFOs for the Bulk and Isochronous endpoints are double-buffered so one packet can be
processed as the next is assembled. While the UDC transmits an IN packet from a particular
endpoint, the Megacell can load the same endpoint for the next frame transmission. While the
Megacell unloads an OUT endpoint, the UDC can continue to process the next incoming packet to
that endpoint.
By decoding the polarity of the UDC+ and UDC- pins and using differential data, four distinct
states are represented. Two of the four states are used to represent data. A 1 indicates that UDC+ is
high and UDC- is low. A 0 indicates that UDC+ is low and UDC- is high. The two remaining states
and pairings of the four encodings are further decoded to represent the current state of the USB.
Table 12-2 shows how differential signalling represents eight different bus states.
Hosts and hubs have pull-down resistors on both the D+ and D- lines. When a device is not
attached to the cable, the pull-down resistors cause D+ and D- to be pulled down below the single-
ended low threshold of the host or hub. This creates a state called single-ended zero (SE0). The
host detects a disconnect when an SE0 persists for more than 2.5 µs (30 bit times). When the UDC
is connected to the USB cable, the pull-up resistor on the UDC+ pin causes D+ to be pulled above
the single-ended high threshold level. After 2.5 µs, the host detects a connect.
After the host detects a Connect, the bus is in the Idle state because UDC+ is high and UDC- is low.
The bus transitions from the Idle state to the Resume state (a 1 to 0 transition) to signal the Start of
Packet (SOP). Each USB packet begins with a Sync field that starts with the 1-to-0 transition (see
Section 12.3.1). After the packet data is transferred, the bus signals the End of Packet (EOP) state
by pulling both UDC+ and UDC- low for 2 bit times followed by an Idle state for 1 bit time. If the
idle persists for more than 3 ms, the UDC enters Suspend state and is placed in low-power mode.
The host can awaken the UDC from the Suspend state by signalling a reset or by switching the bus
to the resume state via normal bus activity. Under normal operating conditions, the host
periodically signals an Start of Frame (SOF) to ensure that devices do not enter the suspend state.
incoming data, which produces the clock. To ensure the receiver is periodically synchronized, six
consecutive ones in the serial bit stream trigger the transmitter to insert a zero. This procedure is
known as bit stuffing. The receiver logic detects stuffed bits and removes them from incoming
data. Bit stuffing causes a transition on the incoming signal at least once every 7 bit times to ensure
the baud clock is locked. Bit stuffing is enabled for an entire packet from the time the SOP is
detected until the EOP is detected (enabled during the Sync field through the CRC field).
Figure 12-1 shows the NRZI encoding of the data byte 0b1101 0010.
Figure 12-1. NRZI Bit Encoding Example
A Sync is preceded by the Idle state and is the first field of every packet. The first bit of a Sync
field signals the SOP to the UDC or host. A Sync is 8 bits wide and consists of seven zeros
followed by a one (0x80). Bits are transmitted to the bus least significant bit first in every field,
except the CRC field.
The PID is 1 byte wide and always follows the sync field. The first four bits contain an encoded
value that represents packet type (Token, Data, Handshake, and Special), packet format, and type
of error detection. The last four bits contain a check field that ensures the PID is transmitted
without errors. The check field is generated by performing a ones complement of the PID. The
UDC XORs the PID and CRC fields and takes the action prescribed in the USB standard if the
result does not contain all ones, which indicates an error has occurred in transmission.
The Address and Endpoint fields are used to access the UDC’s 16 endpoints. The Address field
contains seven bits and permits 127 unique devices to be placed on the USB. After the USB host
signals a reset, the UDC and all other devices are assigned the default address, zero. The host is
then responsible for assigning a unique address to each device on the bus. Addresses are assigned
in the enumeration process, one device at a time. After the host assigns the an address to the UDC,
the UDC only responds to transactions directed to that address. The Address field follows the PID
in every packet transmitted.
When the UDC detects a packet that is addressed to it, it uses the Endpoint field to determine which
of the UDC’s endpoints is being addressed. The Endpoint field contains four bits. Encodings for
endpoints 0 (0000b) through 15 (1111b) are allowed. The Endpoint field follows the Address field.
The Frame Number is an 11-bit field incremented by the host each time a frame is transmitted.
When it reaches its maximum value, 2047 (0x7FF), its value rolls over. Frame Number is
transmitted in the SOF packet, which the host outputs in 1 ms intervals. Device controllers use the
Frame Number field to control isochronous transfers. Data fields are used to transmit the packet
data between the host and the UDC. A data field consists of 0 to 1023 bytes. Each byte is
transmitted least significant bit first. The UDC generates an interrupt to indicate that a Start of
Frame event has occurred.
CRC fields are used to detect errors introduced during token and data packet transmission, and are
applied to all the fields in the packet except the PID field. The PID contains its own 4-bit ones
complement check field for error detection. Token packets use a 5-bit CRC (x5+x2+1) called CRC5
and Data packets use a 16-bit CRC (x16+x15+x2+1) called CRC16. For both CRCs, the checker
resets to all ones at the start of each packet.
Sync PID
To assemble control transfers, the host sends a control transaction to tell the UDC what type of
control transfer is taking place (control read or control write), followed by one or more data
transactions. The setup is the first stage of the control transfer. The device must respond with an
ACK or no handshake (if the data is corrupted). The control transaction, by default, uses a DATA0
transfer and each subsequent data transaction toggles between DATA1 and DATA0 transfers. A
control write to an endpoint uses OUT transactions. Control reads use IN transactions. The transfer
direction is the opposite of the last data transaction. The transfer direction is used to report status
and functions as a handshake. For a control write, the last transaction is an IN from the UDC to the
host. For a control read, the last transaction is an OUT from the host to the UDC. The last data
transaction always uses a DATA1 transfer, even if the previous transaction used DATA1.
Table 12-11 shows a summary of all device requests. Refer to the Universal Serial Bus
Specification Revision 1.1 for a full description of host device requests.
SET_FEATURE Enables a specific feature such as device remote wake-up or endpoint stalls.
CLEAR_FEATURE Clears or disables a specific feature.
Configures the UDC for operation. Used after a reset of the Megacell or after
SET_CONFIGURATION
a reset has been signalled via the USB.
GET_CONFIGURATION Returns the current UDC configuration to the host.
Sets existing descriptors or add new descriptors. Existing descriptors include:
SET_DESCRIPTOR
device, configuration, string, interface, and endpoint.
GET_DESCRIPTOR Returns the specified descriptor, if it exists.
SET_INTERFACE Selects an alternate setting for the UDC’s interface.
GET_INTERFACE Returns the selected alternate setting for the specified interface.
Returns the UDC’s status including: remote wake-up, self-powered, data
GET_STATUS
direction, endpoint number, and stall status.
SET_ADDRESS Sets the UDC’s 7-bit address value for all future device accesses.
SYNCH_FRAME Sets then reports an endpoint’s synchronization frame.
The UDC decodes most standard device commands with no intervention required by the user. The
following commands are not passed to the user are: Set Address, Set Feature, Clear Feature, Get
Configuration, Get Status, Get Interface, and Sync Frame. The Set Configuration and Set Interface
commands are passed to the user to indicate that the host set the specified configuration or interface
and the software must take any necessary actions. Alternate interfaces settings are not supported;
the host must set the alternate settings field in SET_INTERFACE requests to zero. If the UDC
receives a SET_INTERFACE request with the alternate settings field non-zero, the UDC responds
with a STALL. The Get Descriptor and Set Descriptor commands are passed to the user to be
decoded.
Because the Set Feature and Clear Feature commands are not passed on, the user is not able decode
the device remote wakeup feature commands. To solve this problem, the status bit
UDCCS0:DRWF indicates whether or not the device remote wakeup feature is enabled. UDCCS0:
DRWF is a read-only bit. When the bit is set to 1, the device remote wakeup feature is enabled.
When the bit is set to 0, the feature is not enabled.
12.3.7 Configuration
In response to the GET_DESCRIPTOR command, the user device sends back a description of the
UDC configuration. The UDC can physically support more data channel bandwidth than the USB
specification allows. When the device responds to the host, it must specify a legal USB
configuration. For example, if the device specifies a configuration of six isochronous endpoints of
256 bytes each, the host is not be able to schedule the proper bandwidth and does not take the UDC
out of Configuration 0. The user device determines which endpoints to report to the host. If an
endpoint is not reported, it is not used. Another option, attractive for use with isochronous
endpoints, is to describe a configuration of a packet with a maximum size less than 256 bytes to the
host. For example, if software responds to the GET_DESCRIPTOR command that Endpoint 3 only
supports 64 bytes maximum packet Isochronous IN data, the user device must set the
UDCCS3[TSP] bit after it loads 64 bytes for transmission. Similarly, if Endpoint 4 is described as
supporting 128 bytes maximum packet Isochronous OUT data, the UDC recognizes the end of the
packet, sets UDCCS4[RPC], and an interrupt is generated.
The direction of the endpoints is fixed. Physically, the UDC only supports interrupt endpoints with
a maximum packet size of 8 bytes or less, bulk endpoints with a maximum packet size of 64 bytes
or less, and isochronous endpoints with a maximum packet size of 256 bytes or less.
To make the processor more adaptable, the UDC supports a total of four configurations. Each of
these configurations are identical in the UDC, software can make three distinct configurations,
each with two interfaces. Configuration 0 is a default configuration of Endpoint 0 only and cannot
be defined as any other arrangement.
The “5 V to 3.3 V” device is required because the input pins of the processor can only tolerate 3.3
V. The device can be implemented in a number of ways. The most robust and expensive solution is
a Power-On-Reset device such as a MAX6348. This solution produces a clean signal edge and
minimizes signal bounce. A more inexpensive solution is a 3.3 V line buffer with inputs that can
tolerate 5 V. This solution does not reduce signal bounce, so software must compensate by reading
the GPIO repeatedly until it proves to be stable. A third solution is a signal bounce minimization
circuit that can tolerate 5 V but produces a 3.3 V signal to the GPIO pin.
If software must put a peripheral in sleep mode, it configures the GPIOx pin as an input. This
causes the UDC+ line to float, which appears to be a disconnect to the host PC. The peripheral is
put in sleep mode. When the peripheral comes out of sleep mode, software must drive a 1 to the
GPIOx pin to indicate to the host PC that a high-speed USB peripheral is connected.
When GPIOn and GPIOx are the same pin, do not put a peripheral in sleep mode if the USB cable
is connected to the device. During sleep, the USB controller is in reset and does not respond to the
host PC. When it returns from sleep mode, the peripheral does not respond to its host-assigned
address.
14. When the host executes the STATUS OUT stage (zero-length OUT), the UDC sets the
UDDCS0[OPR] bit, which causes an interrupt.
15. Software enters the ISR routine and determines that the UDCCS0[OPR] bit is set, the
UDCCS0[SA] bit is clear, and its internal state machine is EP0_END_XFER. Software clears
the UDCCS0[OPR] bit and transfers its internal state machine to EP0_IDLE.
16. Software clears the UDC interrupt bit and returns from the interrupt service routine.
If the host sends another SETUP command during these steps, the software must terminate the first
SETUP command and start the new command.
16. Software clears the UDC interrupt bit and returns from the interrupt service routine.
If the host sends another SETUP command during these steps, the software must terminate the first
SETUP command and start the new command.
the wrong amount of data was sent, software cleans up any buffer pointers and disregards the
received data.
20. Software changes its internal state machine to EP0_IDLE.
21. Software clears the UDC interrupt bit and returns from the interrupt service routine.
If the host sends another SETUP command during these steps, the software must terminate the first
SETUP command and start the new command.
If the host sends another SETUP command during these steps, the software must terminate the first
SETUP command and start the new command.
In Case 5, the Transmit Short Packet is only set if a packet size of less than 64 bytes is sent. If the
packet size is 64 bytes, the system arms when the 64th byte is loaded. Loading the 64th byte and
setting the UDCCS1[TSP] bit produces one 64-byte packet and one zero-length packet.
When software receives a SETUP VENDOR command to set up an EP1 BULK IN transaction, it
may take one of two courses of action, as appropriate for the chosen operating model:
• Configure the DMA engine and disable the EP1 interrupt to allow the DMA engine to handle
the transaction.
• Enable the EP1 interrupt to allow the Megacell to directly handle the transaction.
1. During the SETUP VENDOR command, software enables the DMA engine and masks the
EP1 interrupt. The DMA start address must be aligned on a 16-byte boundary.
a. If the packet size is 64 bytes, software transfers the all the data in one DMA descriptor
and sets the UDCCS1[TSP] bit in the second DMA descriptor.
b. If the packet size is less than 64 bytes, software sets up a string of descriptors in which the
odd numbered descriptors point to the data and the even numbered descriptors are writes
to the UDCCS1[TSP] bit.
2. The host PC sends a BULK-IN and the UDC sends a data packet back to the host PC.
3. The UDC generates an interrupt that is masked from the Megacell.
4. The DMA engine fills the EP1 data FIFO (UDDR1) with data and sets the UDCCS1[TSP] bit
if the data packet is a short packet.
5. Steps 2 through 4 repeat until all the bulk data is sent to the host PC.
When software receives a SETUP VENDOR command to set up an EP2 BULK OUT transaction,
it may take one of two courses of action, as appropriate for the chosen operating model:
• Enable the DMA engine to handle the transaction.
• Allow the Megacell to directly handle the transaction.
In Case 7, the Transmit Short Packet is only set if a packet size of less than 256 bytes is sent. If the
packet size is 256 bytes, the system arms when the 256th byte is loaded. Loading the 256th byte
and setting the UDCCS3[TSP] bit produces one 256-byte packet and one zero-length packet.
1. During the SETUP VENDOR command, software enables the DMA engine and masks the
EP3 interrupt. The DMA start address must be aligned on a 16-byte boundary.
a. If the packet size is 256 bytes, software transfers the all the data in one DMA descriptor.
b. If the packet size is less than 256 bytes, software sets up a string of descriptors in which
the odd numbered descriptors point to the data and the even numbered descriptors are
writes to the UDCCS1[TSP] bit.
2. The host PC sends an ISOC-IN and the UDC sends a data packet back to the host PC.
3. The UDC generates an interrupt that is masked from the Megacell.
4. The DMA engine fills the EP3 data FIFO (UDDR3) with data and sets the UDCCS3[TSP] bit
if the data packet is a short packet.
5. Steps 2 through 4 repeat until all the data has been sent to the host.
When software receives a SETUP VENDOR command to set up an EP4 ISOCHRONOUS OUT
transaction, it may take one of three courses of action, as appropriate for the chosen operating
model:
• Configure the DMA engine and disable the EP4 interrupt to allow the DMA engine to handle
the transaction.
• Enable the EP4 interrupt to allow the Megacell to directly handle the transaction.
• Enable the SOF interrupt to handle the transaction on a frame count basis.
In Case 9, the Transmit Short Packet is only set if a packet size of less than 8 bytes is sent. If the
packet size is 8 bytes, the system arms when the 8th byte is loaded. Loading the 8th byte and
setting the UDCCS5[TSP] bit produces one 8-byte packet and one zero-length packet.
b. If UDCCR[UDA] is a 1, there is currently no USB reset on the bus and software enables
future reset interrupts by clearing the UDCCR[REM] bit.
3. Return from interrupt.
4. The host either asserts a USB reset or negates a USB reset.
5. The UDC generates a Reset Interrupt.
6. Software determines that the UDCCR[RSTIR] bit is set and clears the interrupt by writing a 1
to the UDCCR[RSTIR] bit. Software then examines the UDCCR[UDA] bit to determine the
type of reset that took place:
a. If UDCCR[UDA] is a 0, a Reset Assertion took place. Software returns from the interrupt
and waits for the Reset Negation interrupt.
b. If UDDCR[UDA] is a 1, a Reset Negation took place. Software sets any initialization that
is necessary.
7. Return from interrupt.
address for the 16 x 8 data FIFO that can be used to transmit and receive data. Endpoint 0 also has
a write count register that is used to determine the number of bytes the USB host controller has sent
to Endpoint 0.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSIR
RESIR
RSTIR
REM
SRM
RSM
UDA
UDE
reserved
x x x x x x x x x x x x x x x x x x x x x x x x 1 0 1 0 0 0 0 0
31:8 — reserved
If UDE is set to a 0 the entire UDC design is reset. If the reset occurs while the UDC is actively
transmitting or receiving data, it stops immediately and the remaining bits in the transmit or receive
serial shifter are reset. All entries in the transmit and receive FIFO are also reset.
The UDE bit is cleared to zero, which disables the UDC following a Megacell reset. Writes to
reserved bits are ignored and reads return zeros.
These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31:8 7 6 5 4 3 2 1 0
Reset X 1 1 0 1 1 1 1 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DRWF
OPR
RNE
SST
FST
FTF
IPR
SA
reserved
x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0
When software enables the status stage for Vendor/Class commands and control data commands
such as GET_DESCRIPTOR, GET_CONFIGURATION, GET_INTERFACE, GET_STATUS, and
SET_DECSCRIPTOR, software must also set IPR. The data in the Transmit FIFO must be
transmitted and the interrupt must be processed before the IPR is set for the status stage.
The status stage for all other USB Standard Commands that do not have a data stage, such as
SET_ADDRESS, SET_CONFIGURATION, SET_INTERFACE, SET_FEATURE, and
CLEAR_FEATURE, is handled by the UDC and the software must not set IPR.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
TUR
TPC
TSP
SST
TFS
FST
FTF
reserved
X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 1
31:8 — reserved
Transmit short packet
7 TSP
1 = Short packet ready for transmission.
6 — reserved
Force STALL
5 FST
1 = Issue STALL handshakes to IN tokens.
Sent STALL
4 SST
1 = STALL handshake was sent.
Transmit FIFO underrun
3 TUR
1 = Transmit FIFO experienced an underrun.
Flush Tx FIFO
2 FTF
1 = Flush Contents of TX FIFO
Transmit packet complete
1 TPC 0 = Error/status bits invalid.
1 = Transmit packet has been sent and error/status bits are valid.
Transmit FIFO service
0 TFS 0 = Transmit FIFO has no room for new data
1 = Transmit FIFO has room for at least 1 complete data packet
Setting this bit does not prevent the UDC from transmitting the next buffer. The UDC issues NAK
handshakes to all IN tokens if this bit is set and neither buffer has been triggered by writing
64-bytes or setting UDCCSx[TSP].
When DMA loads the transmit buffers, the interrupt generated by UDCCSx[TPC] can be masked
to allow data to be transmitted without core intervention.
These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
DME
RPC
RNE
RSP
RFS
SST
FST
reserved
x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0
31:8 — reserved
Receive short packet (read-only).
7 RSP
1 = Short packet received and ready for reading.
Receive FIFO not empty (read-only).
6 RNE 0 = Receive FIFO empty.
1 = Receive FIFO not empty.
Force stall (read/write).
5 FST
1 = Issue STALL handshakes to OUT tokens.
Sent stall (read/write 1 to clear).
4 SST
1 = STALL handshake was sent.
DMA Enable(read/write)
3 DME 0 = Send data received interrupt after EOP received
1 = Send data received interrupt after EOP received and Receive FIFO has < 32 bytes of
data
2 — reserved
Receive packet complete (read/write 1 to clear).
1 RPC 0 = Error/status bits invalid.
1 = Receive packet has been received and error/status bits are valid.
Receive FIFO service (read-only).
0 RFS 0 = Receive FIFO has less than 1 data packet.
1 = Receive FIFO has 1 or more data packets.
exception is RNE which will get set with RPC but will clear itself once the active FIFO is empty.
After clearing RPC, the next buffer will become active and the status bits will be updated
accordingly, including RPC. The UDCCSx[RPC] bit is cleared by writing a 1 to it. The UDC issues
NAK handshakes to all OUT tokens while this bit is set and both buffers have unread data.
These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TUR
TPC
TSP
TFS
FTF
reserved reserved
Reset X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 1
31:8 — reserved
Transmit short packet (read/write 1 to set).
7 TSP
1 = Short packet ready for transmission.
6:4 — reserved
Transmit FIFO underrun (read/write 1 to clear)
3 TUR
1 = Transmit FIFO experienced an underrun.
Flush Tx FIFO (always read 0/ write a 1 to set)
2 FTF
1 = 1 – Flush Contents of TX FIFO
Transmit packet complete (read/write 1 to clear).
1 TPC 0 = Error/status bits invalid.
1 = Transmit packet has been sent and error/status bits are valid.
Transmit FIFO service (read-only).
0 TFS 0 = Transmit FIFO has no room for new data
1 = Transmit FIFO has room for at least 1 complete data packet
Setting this bit does not prevent the UDC from transmitting the next buffer. The UDC issues NAK
handshakes to all IN tokens if this bit is set and neither buffer has been triggered by writing
64 bytes or setting UDCCSx[TSP].
When DMA is used to load the transmit buffers, the interrupt generated by UDCCSx[TPC] can be
masked to allow data to be transmitted without core intervention.
These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
DME
RPC
RNE
ROF
RSP
RFS
reserved
Reset x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0
31:8 — reserved
Receive short packet (read-only)
7 RSP
0 = Short packet received and ready for reading.
Receive FIFO not empty (read-only).
6 RNE 0 = Receive FIFO empty.
1 = Receive FIFO not empty.
5:4 — reserved
DMA Enable(read/write)
3 DME 0 = Send receive interrupt after EOP receive
1 = Send data received interrupt after EOP received and Receive FIFO has < 32 bytes of
data
Receive overflow (read/write 1 to clear)
2 ROF
1 = Isochronous data packets are being dropped from the host because the receiver is full.
Receive packet complete (read/write 1 to clear).
1 RPC 0 = Error/status bits invalid.
1 = Receive packet has been received and error/status bits are valid.
Receive FIFO service (read-only).
0 RFS 0 = Receive FIFO has less than 1 data packet.
1 = Receive FIFO has 1 or more data packets.
These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
TUR
TPC
TSP
SST
TFS
FST
FTF
reserved
Reset x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 1
31:8 — reserved
Transmit short packet (read/write 1 to set).
7 TSP
1 = Short packet ready for transmission.
6 — reserved
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
TUR
TPC
TSP
SST
TFS
FST
FTF
reserved
Reset x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 1
The UDC issues NAK handshakes to all IN tokens if this bit is set and the buffer is not triggered by
writing 8 bytes or setting UDCCSx[TSP].
These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IM7
IM6
IM5
IM4
IM3
IM2
IM1
IM0
reserved
Reset x x x x x x x x x x x x x x x x x x x x x x x x 1 1 1 1 1 1 1 1
31:8 — reserved
Interrupt Mask for Endpoint 7
7 IM7 0 = Receive interrupt enabled
1 = Receive interrupt disabled
Interrupt Mask for Endpoint 6
6 IM6 0 = Transmit interrupt enabled
1 = Transmit interrupt disabled
Interrupt mask for Endpoint 5
5 IM5 0 = Transmit interrupt enabled
1 = Transmit interrupt disabled
Interrupt mask for Endpoint 4
4 IM4 0 = Receive Interrupt enabled
1 = Receive Interrupt disabled
Interrupt mask for Endpoint 3
3 IM3 0 = Transmit interrupt enabled
1 = Transmit interrupt disabled
Interrupt Mask for Endpoint 2
2 IM2 0 = Receive interrupt enabled
1 = Receive interrupt disabled
Interrupt Mask for Endpoint 1
1 IM1 0 = Transmit interrupt enabled
1 = Transmit interrupt disabled
Interrupt mask for endpoint 0
0 IM0 0 = Endpoint zero interrupt enabled
1 = Endpoint zero interrupt disabled
These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IM15
IM14
IM13
IM12
IM10
IM11
IM9
IM8
reserved
Reset X X X X X X X X X X X X X X X X X X X X X X X X 1 1 1 1 1 1 1 1
31:8 — reserved
Interrupt mask for Endpoint 15
7 IM15 0 = Transmit interrupt enabled
1 = Transmit interrupt disabled
Interrupt mask for Endpoint 14
6 IM14 0 = Receive interrupt enabled
1 = Receive interrupt disabled
Interrupt mask for Endpoint 13
5 IM13 0 = Transmit interrupt enabled
1 = Transmit interrupt disabled.
Interrupt mask for Endpoint 12
4 IM12 0 = Receive interrupt enabled
1 = Receive interrupt disabled
Interrupt mask for Endpoint 11
3 IM11 0 = Transmit interrupt enabled
1 = Transmit interrupt disabled
Interrupt mask for Endpoint 10
2 IM10 0 = Receive interrupt enabled
1 = Receive interrupt disabled
Interrupt mask for Endpoint 9
1 IM9 0 = Receive interrupt enabled
1 = Receive interrupt disabled
Interrupt Mask for Endpoint 8
0 IM8 0 = Transmit interrupt enabled
1 = Transmit interrupt disabled
These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits.
The bits in USIR0 and USIR1 are controlled by a mask bit in the UDC Interrupt Control Register
(UICR0/1). The mask bits, when set, prevent a status bit in the USIRx from being set. If the mask
bit for a particular status bit is cleared and an interruptible condition occurs, the status bit is set. To
clear status bits, the core must write a 1 to the position to be cleared. The interrupt request for the
UDC remains active as long as the value of the USIRx is non-zero.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IR7
IR6
IR5
IR4
IR3
IR2
IR1
IR1
reserved
Reset x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0
31:8 — reserved
Interrupt Request Endpoint 7 (read/write 1 to clear)
7 IR7
1 = Endpoint 7 needs service.
Interrupt Request Endpoint 6 (read/write 1 to clear)
6 IR6
1 = Endpoint 6 needs service.
Interrupt Request Endpoint 5 (read/write 1 to clear)
5 IR5
1 = Endpoint 5 needs service.
Interrupt Request Endpoint 4 (read/write 1 to clear)
4 IR4
1 = Endpoint 4 needs service.
Interrupt Request Endpoint 3 (read/write 1 to clear)
3 IR3
1 = Endpoint 3 needs service.
Interrupt Request Endpoint 2 (read/write 1 to clear)
2 IR2
1 = Endpoint 2 needs service.
Interrupt Request Endpoint 1 (read/write 1 to clear)
1 IR1
1 = Endpoint 1 needs service.
Interrupt Request Endpoint 0 (read/write 1 to clear)
0 IR0
1 = Endpoint 0 needs service.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IR15
IR14
IR13
IR12
IR10
IR11
IR9
IR8
reserved
x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0
31:8 — reserved
Interrupt Request Endpoint 15 (read/write 1 to clear)
7 IR15
1 = Endpoint 15 needs service.
Interrupt Request Endpoint 14 (read/write 1 to clear)
6 IR14
1 = Endpoint 14 needs service.
Interrupt Request Endpoint 13 (read/write 1 to clear)
5 IR13
1 = Endpoint 13 needs service.
Interrupt Request Endpoint 12 (read/write 1 to clear)
4 IR12
1 = Endpoint 12 needs service.
Interrupt Request Endpoint 11 (read/write 1 to clear)
3 IR11
1 = Endpoint 11 needs service.
Interrupt Request Endpoint 10 (read/write 1 to clear)
2 IR10
1 = Endpoint 10 needs service.
Interrupt Request Endpoint 9 (read/write 1 to clear)
1 IR9
1 = Endpoint 9needs service.
Interrupt Request Endpoint 8 (read/write 1 to clear)
0 IR8
1 = Endpoint 8 needs service.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
3-Bit
IPE14
Frame
IPE9
IPE4
SIM
SIR
reserved
Number
MSB
Reset x x x x x x x x x x x x x x x x x x x x x x x x 0 1 0 0 0 0 0 0
31:8 — reserved
SOF Interrupt Request (read/write 1 to clear)
7 SIR
1 = SOF has been received.
SOF interrupt mask
6 SIM 0 = SOF interrupt enabled.
1 = SOF interrupt disabled.
Isochronous Packet Error Endpoint 14 (read/write 1 to clear)
5 IPE14
1 = Status indicator that data in the endpoint FIFO is corrupted
Isochronous Packet Error Endpoint 9 (read/write 1 to clear)
4 IPE9
1 = Status indicator that data in the endpoint FIFO is corrupted
Isochronous Packet Error Endpoint 4 (read/write 1 to clear)
3 IPE4
1 = Status indicator that data in the endpoint FIFO is corrupted
Frame Number MSB.
2:0 FNMSB
Most significant 3-bits of 11-bit frame number associated with last receive SOF.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 0
31:8 — reserved
Frame number LSB
7:0 FNLSB
Least significant 8-bits of frame number associated with last received SOF.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved BC
Reset x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0
31:8 — reserved
7:0 BC Byte Count (read-only). Number of bytes in the FIFO is Byte Count plus 1 (BC+1).
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0
31:8 — reserved
Top/bottom of endpoint 0 FIFO data.
7:0 DATA Read – Bottom of endpoint 0 FIFO data.
Write – Top of endpoint 0 FIFO data.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset x x x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0
31:8 — reserved
7:0 DATA Top of endpoint data currently being loaded
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0
31:8 — reserved
7:0 DATA Top of endpoint data currently being read
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0
31:8 — reserved
7:0 DATA Top of endpoint data currently being loaded
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0
31:8 — reserved
7:0 DATA Top of endpoint data currently being loaded
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0
31:8 — reserved
7:0 DATA Top of endpoint data currently being loaded
13.1 Overview
The AC’97 Controller Unit (ACUNIT) of the PXA255 processor supports the AC’97 revision 2.0
features listed in Section 13.2. The ACUNIT also supports audio controller link (AC-link). AC-
link is a serial interface for transferring digital audio, modem, mic-in, CODEC register control, and
status information.
The AC’97 CODEC sends the digitized audio samples that the ACUNIT stores in memory. For
playback or synthesized audio production, the processor retrieves stored audio samples and sends
them to the CODEC through the AC-link. The external digital-to-analog converter (DAC) in the
CODEC then converts the audio samples to an analog audio waveform.
This chapter describes the programming model for the ACUNIT. The information in this chapter
requires an understanding of the AC’97 revision 2.0 specification.
Note: The ACUNIT and the I2S Controller cannot be used at the same time.
The processor ACUNIT does not support these optional AC’97 features:
• Double-rate sampling (n+1 sample for PCM L, R & C)
• 18- and 20-bit sample lengths
Note: Refer to Section 4.1.3, “GPIO Register Definitions” on page 4-6 for details on programing the
GPDR and GAFR for use with the ACUNIT.
SDATA_IN_0
SDATA_IN_1
PCM Playback Two output slots Two-channel composite PCM output stream
PCM Record data Two input slots Two-channel composite PCM input stream
CODEC control Two output slots Control register write port
CODEC status Two input slots Control register read port
Modem Line
One output slot Modem line CODEC DAC input stream
CODEC Output
Modem Line
One input slot Modem line CODEC ADC output stream
CODEC Input
The ACUNIT provides synchronization for all data transaction on the AC-link. A data transaction
is made up of 256 bits of information broken up into groups of 13 time slots and is called a frame.
Time slot 0 is called the Tag Phase and is 16 bits long. The other 12 time slots are called the Data
Phase. The Tag Phase contains one bit that identifies a valid frame and 12 bits that identify the time
slots in the Data Phase that contain valid data. Each time slot in the Data Phase is 20 bits long.
A frame begins when SYNC goes high. The amount of time that SYNC is high corresponds to the
Tag Phase. AC’97 frames occur at fixed 48 kHz intervals and are synchronous to the 12.288 MHz
bit rate clock, BITCLK.
The ACUNIT and the CODEC use the SYNC and BITCLK to determine when to send transmit
data and when to sample receive data. A transmitter transitions the serial data stream on each rising
edge of BITCLK and a receiver samples the serial data stream on each falling edge of BITCLK.
The transmitter must tag the valid slots in its serial data stream. The valid slots are tagged in slot 0.
Serial data on the AC-link is ordered most significant bit (MSB) to least significant bit (LSB). The
Tag Phase’s first bit is bit 15 and the first bit of each slot in Data Phase is bit 19. The last bit in any
slot is bit 0.
Figure 13-2 shows Tag and Data Phase organization for the ACUNIT and the CODEC. The figure
also lists the slot definitions that the ACUNIT supports.
Figure 13-2. AC’97 Standard Bidirectional Audio Frame
Slot # 0 1 2 3 4 5 6 7 8 9 10 11 12
SYNC
BIT_CLK
Valid
SDATA_OUT Frame
slot(1) slot(2) slot(12) "0" codec ID codec ID 19 0 19 0 19 0 19 0
End of previous
Time Slot "Valid" Slot 1 Slot 2 Slot 3 Slot 12
Audio Frame
Bits
("1" = time slot contains valid PCM data)
A new audio output frame begins with a low-to-high SYNC transition synchronous to BITCLK’s
rising edge. BITCLK’s falling edge immediately follows and AC’97 samples SYNC’s assertion.
BITCLK’s falling edge marks the instance that AC-link’s sides are each aware that a new audio
frame has started. On BITCLK’s next rising edge, the ACUNIT transitions SDATA_OUT into the
slot 0’s first bit position (valid frame bit). Each new bit position is presented to AC-link on a
BITCLK rising edge and then sampled by AC’97 on the following BITCLK falling edge. This
sequence ensures that data transitions and subsequent sample points for both incoming and
outgoing data streams are time aligned.
Figure 13-4. Start of Audio Output Frame
BIT_CLK
Valid
SDATA_OUT Frame
slot(1) slot(2)
End of previous
Audio Frame
The SDATA_OUT composite stream is MSB-justified (MSB first). The ACUNIT fills all non-valid
slot bit positions with zeroes. If fewer than 20 valid bits exist in an assigned valid time slot, the
ACUNIT stuffs all trailing non-valid bit positions of the 20-bit slot with zeroes.
For example, if a 16-bit sample stream is being played to an AC’97 DAC, the first 16 bit positions
are presented to the DAC MSB-justified. They are followed by the next four bit positions that the
ACUNIT stuffs with zeroes. This process ensures that the least significant bits do not introduce any
DC biasing, regardless of the implemented DAC’s resolution (16-, 18-, or 20-bit).
Note: When the ACUNIT transmits mono audio sample streams, software must ensure that the left and
right sample stream time slots are filled with identical data.
Audio output frame slot 1 communicates control register address and write/read command
information to the ACUNIT.
Two CODECs are connected to the single SDATA_OUT. To address the primary and secondary
CODECs individually, follow these steps:
Only one I/O cycle can be pending across the AC-link at any time. The ACUNIT uses write and
read posting on I/O accesses across the link. For example, read data from a CODEC register is not
sent over the AC-link (Slot 2 of incoming stream) within the same frame that the read request is
sent.
For CODEC reads, the ACUNIT gives the CODEC a maximum of four subsequent frames to
respond -- if no response is received, the ACUNIT returns a dummy read completion
(0xFFFF_FFFF) to the CPU and sets the Read Completion Status (RDCS) bit of the Global Status
Register (GSR).
The CAIP bit of the CODEC Access Register (CAR) is used to assure that only one I/O cycle
occurs across the AC-link at any time. Software must read the CAIP bit before initiating an I/O
cycle. If the CAIP bit reads as a one, another driver is performing an I/O cycle; if the CAIP bit
reads as a zero, a new I/O cycle can be initiated.
The exception to posted accesses is reads to the CODEC GPIO Pin Status register (address 0x54).
CODEC GPIO Pin Status read data is sent by the CODEC over the AC-link in the same frame that
the read request was sent to the CODEC. The CODEC GPIO Pin Status read data is sent in Slot 12
of the incoming stream. A CODEC with a GPIO Pin Status register must constantly send the status
of the register in slot 12.
Bit(19:4) Control register write data Stuffed with 0s if current operation is a read
Bit(3:0) reserved Stuffed with 0s
If the current command port operation is a read, the ACUNIT fills Slot 2 with zeroes.
Multiple input data streams are received and multiplexed on slot boundaries as dictated by the slot
valid bits in each stream. Each AC-link audio input frame consists of twelve 20-bit time slots. Slot
0 is reserved and contains 16 bits that are used for AC-link protocol infrastructure.
Software must poll the first bit in the audio input frame (SDATA_IN slot 0, bit 15) for an indication
that the CODEC is in the CODEC ready state before it places the ACUNIT into data transfer
operation. When the “CODEC is ready” state is sampled, the next 12 sampled bits indicate which
of the 12 time slots are assigned to input data streams and whether they contain valid data.
Figure 13-5, “AC’97 Input Frame” illustrates the time slot-based AC-link protocol.
BIT_CLK
Codec
SDATA_IN slot(1) slot(2) slot(12) "0" "0" "0" 19 0 19 0 19 0 19 0
Ready
A new audio input frame begins when SYNC transitions from low to high. The low to high
transition is synchronous to BITCLK’s rising edge. On BITCLK’s next falling edge, AC’97
samples SYNC’s assertion. This falling edge marks the moment that AC-link’s sides are each
aware that a new audio frame has started. The next time BITCLK rises, the ACUNIT transitions
SDATA_IN to the first bit position in slot 0 (CODEC ready bit). Each new bit position is presented
to AC-link on a BITCLK’s rising edge and then sampled by ACUNIT on the following BITCLK’s
falling edge. This sequence ensures that data transitions and subsequent sample points are time
aligned for both incoming and outgoing data streams.
Figure 13-6. Start of an Audio Input Frame
BIT_CLK
Codec
SDATA_IN Ready
slot(1) slot(2)
End of previous
Audio Frame
The SDATA_IN composite stream is MSB justified (MSB first) and the AC’97 CODEC fills non-
valid bit positions with zeroes. SDATA_IN data is sampled on BITCLK’s falling edge.
CODEC Ready, sent by the CODEC on its data out stream in bit 15 of Slot 0, is not expected to
change during normal operation. The AC’97 Specification revision 2.0 requires that a CODEC
only change its CODEC Ready status in response to a power down (PR) state change issued by the
ACUNIT. The ACUNIT’s hardware by itself does not monitor the CODEC Ready for the purpose
of sending or receiving data. The ACUNIT stores CODEC Ready in the PCR bit of the GSR for a
primary CODEC and SCR bit of the GSR for a secondary CODEC. Software should monitor PCR
or SCR to trigger a DMA or a programmed I/O operation. The ACUNIT only samples CODEC
Ready valid once and then ignores it for subsequent frames. CODEC Ready is only resampled after
a PR state change.
Slot 1 echoes the control register index for the data to be returned in Slot 2, if the ACUNIT tags
Slot 1 and Slot 2 as valid during Slot 0.
The ACUNIT only accepts status data (Slot 2 of incoming stream) if the accompanying control
register index (Slot 1 of incoming stream) matches the last valid control register index that was sent
in Slot 1 of the outgoing stream of the most recent previous frame.
For multiple sample rate output, the CODEC examines its sample-rate control registers, its FIFOs’
states, and the incoming SDATA_OUT tag bits at the beginning of each audio output frame to
determine which SLOTREQ bits to set active (low). SLOTREQ bits asserted during the current
audio input frame indicate which output slots require data from the ACUNIT in the next audio
output frame. For fixed 48 kHz operation, the SLOTREQ bits are set active (low), and a sample is
transferred during each frame.
For multiple sample-rate input, the tag bit for each input slot indicates whether valid data is
present.
Again, Slot 1 delivers a CODEC control register index and multiple “sample-rate slot request
flags” for all output slots. AC’97 defines the ten least significant bits of Slot 1 as CODEC on-
demand data request flags for outgoing stream Slots 3-12. For two-channel audio, only data-
request flags corresponding to slots 3 and 4 are meaningful.
Note: Slot requests for Slot 3 and Slot 4 are always set or cleared in tandem (both are set or both are
cleared).
Note: If Slot 2 is tagged invalid, the CODEC fills the entire slot with zeroes.
The CODEC transmits its ADC output data (MSB first) and fills any trailing non-valid bit positions
with zeroes.
The CODEC transmits its ADC output data (MSB first), and fills any trailing non-valid bit
positions with zeroes.
The ACUNIT only supports a 16-bit ADC output resolution from the optional line modem.
The data returned on the latest frame is also accessible to software through the CODEC register at
address 0x54 in the modem CODEC I/O space. Data received in Slot 12 is stored internally in the
ACUNIT. So when software initiates a read of the CODEC register at address 0x54 in the modem
CODEC I/O space, the read data is already inside the ACUNIT.
SYNC
BITCLK
slot 12
SDATA_IN prev. frame TAG
The ACUNIT transmits the write to the Powerdown Register (0x26) over the AC-link. Set up the
ACUNIT so that it does not transmit data in Slots 3-12 when it writes 0x1000 to the PR4 bit of the
Powerdown Register. AC’97 revision 2.0 does not require the CODEC to process other data when
it receives a power down request. When the CODEC receives the power down request, it
immediately transitions BITCLK and SDATA_IN to a logic low level.
Figure 13-8 shows the AC-link timing for a wake up triggered by a CODEC. Because the processor
may need to be awakened, the Power Management unit detects the AC’97 wake-up event
(SDATA_IN high for more than one microsecond). When the ACUNIT is ready, it responds to the
wake-up event by asserting a warm or cold reset (see Figure 13-8). A Modem CODEC may require
the capacity to wake up the AC-link to report events such as Caller-ID and wake-up-on-ring.
Figure 13-8. SDATA_IN Wake Up Signaling
SYNC Note 1
BITCLK
Notes:
After SDATA_IN goes high, SYNC must be held for a minimum of 1 µSec.
The minimum SDATA_IN wake up pulse width is 1 µSec.
BITCLK not to scale.
B1027-01
NOTES:
1. After SDATA_IN goes high, SYNC must be held for a minimum of 1 µSec.
2. The minimum SDATA_IN wake up pulse width is 1 µSec.
3. BITCLK not to scale
After a power down, the AC-link must wait for a minimum of four audio frame times after the
frame in which the power down occurred before it can be reactivated by reasserting the SYNC
signal. When AC-link powers up, it indicates readiness through the CODEC ready bit (input slot 0,
bit 15).
Receive FIFO entries are read through the PCDR, the MODR, or the Mic-in Data Register
(MCDR).
Note: After it is enabled, the ACUNIT requests the DMA to fill the transmit FIFO.
Note: The ACUNIT registers do not store the status of DMA requests or information regarding the
number of data samples in each FIFO. As a result, programmed I/O must not be used in place of
DMA requests for data transfers.
Only the DMA can access the FIFOs. The DMA controller accesses FIFO data in 8-, 16-, or 32-
byte blocks. The DMA request thresholds are not programmable.The ACUNIT makes a transmit
DMA request when the transmit FIFO has less than 32 bytes. The ACUNIT makes a receive DMA
request when the receive FIFO has 32 bytes or more. Regardless of burst size, the DMA descriptor
length must be a multiple of 32 bytes to prevent audio artifacts from being introduced onto the AC-
link.
13.6.1 Initialization
The AC’97 CODEC and ACUNIT are reset on power up. After power up, the nACRESET signal
remains asserted until the audio or modem driver sets the COLD_RST bit of the GCR to one.
During operation, clearing the COLD_RST bit to zero resets the ACUNIT and CODEC. To
initialize the ACUNIT follow theses steps:
1. Program the GPIO Direction register and GPIO Alternate Function Select register to assign
proper pin directions for the ACUNIT ports. Refer to Section 13.3 for details.
2. Set the COLD_RST bit of the GCR to one to deassert nACRESET. Until this is done, all other
registers remain in a reset state. Deasserting nACRESET has the following effects:
a. Frames filled with zeroes are transmitted because the transmit FIFO is still empty. This
situation does not cause an error condition.
b. The ACUNIT records zeroes until the CODEC sends valid data.
c. DMA requests are enabled.
3. Enable the Primary Ready Interrupt Enable and/or the Secondary Ready Interrupt Enable by
setting the PRIRDY_IEN bit and/or the SECRDY_IEN bit of the GCR to one.
4. Software enables DMA operation in response to primary and secondary ready interrupts.
5. The ACUNIT triggers transmit DMA requests. The DMA fills the transmit FIFO in response.
6. The ACUNIT continues to transmit zeroes until the transmit FIFO is half full. When it is half
full, valid transmit FIFO data is sent across the AC-link.
Note: When nACRESET is deasserted, a read to the CODEC Mixer register returns the type of hardware
that resides in the CODEC. If the CODEC is not present or if the AC’97 is not supported, the
ACUNIT does not set the CODEC-ready bit, GCR[PCRDY] for the Primary CODEC or
GCR[SCRDY] for the Secondary CODEC.
If the transmit buffers do not have 32-byte resolution, the trailing bytes in the Transmit FIFO are
not transmitted. A transmit buffer must be padded with zeroes if it is smaller than a multiple of 32
bytes. Regardless of burst size, the DMA descriptor length must be a multiple of 32 bytes to
prevent audio artifacts from being introduced onto the AC-link.
If the CODEC transmitted data has a total buffer size smaller than a multiple of 32 bytes, zeroes are
recorded. A receive DMA request is made when the receive FIFO is half-full.
Software must read the CODEC Access Register (CAR) to lock the AC-link. The AC-link is free if
the CAIP bit of the CAR is zero. For details about the CAR, refer to Table 13-13.
A read access to the CAR sets the CAIP bit. The ACUNIT clears the CAIP bit when the CODEC-
write or CODEC-read operation completes. Software can also clear the CAIP bit by writing a zero
to it.
After it locks the AC-link, software can write or read a CODEC register using the appropriate
processor physical address.
The ACUNIT sets the CDONE bit of the GSR to one after the completion of a CODEC write
operation. For details, refer to Table 13-8. Software clears this bit by writing a 1 to it.
All data transfers across the AC-link are synchronized to SYNC’s rising edge. The ACUNIT
divides the BITCLK by 256 to generate the SYNC signal. This calculation yields a 48 kHz SYNC
signal, and its period defines a frame. Data is transitioned on AC-link on every BITCLK rising
edge and subsequently sampled on AC-link’s receiving side on each following BITCLK falling
edge. For a timing diagram see Figure 13-3.
The ACUNIT synchronizes data between two different clock domains: the BITCLK and an internal
system clock. This internal system clock is always half the run mode frequency. The run mode
frequency is equal to or greater than eight times the BITCLK frequency.
13.8.1 FIFOs
The ACUNIT has five FIFOs:
• PCM Transmit FIFO, with sixteen 32-bit entries.
• PCM Receive FIFO, with sixteen 32-bit entries.
• Modem Transmit FIFO, with sixteen 32-bit entries (upper 16 bits must always be zero).
• Modem Receive FIFO, with sixteen 32-bit entries (upper 16 bits are always zero).
• Mic-in Receive FIFO, with sixteen 32-bit entries (upper 16 bits are always zero).
A receive FIFO triggers a DMA request when the FIFO has eight or more entries. A transmit FIFO
triggers a DMA request when it holds less than eight entries. A transmit FIFO must be half full
(filled with eight entries) before any data is transmitted across the AC-link.
13.8.2 Interrupts
The following status bits interrupt the processor when the interrupts are enabled:
• Mic-in FIFO error: Mic-in Receive FIFO’s over-run or under-run error.
• Modem-in FIFO error: Modem Receive FIFO’s over-run or under-run error.
• PCM-in FIFO error: Audio Receive FIFO’s over-run or under-run error.
• Modem-out FIFO error: Modem Transmit FIFO’s over-run or under-run error.
• PCM-out FIFO error: Audio Transmit FIFO’s over-run or under-run error.
• Modem CODEC GPI status change interrupt: Interrupts the CPU if bit 0 of Slot 12 is set. This
indicates a change in one of the bits in the modem CODEC’s GPIO register.
• Primary CODEC resume interrupt: Sets a status register bit when the Primary CODEC
resumes from a lower power mode. Software writes a one to this bit to clear it.
• Secondary CODEC resume interrupt: Sets a status register bit when the Secondary CODEC
resumes from a lower power mode. Software writes a one to this bit to clear it.
• CODEC command done interrupt: Interrupts the CPU when a CODEC register’s command is
completed. Software writes a one to this bit to clear it.
• CODEC status done interrupt: Interrupts the CPU when a CODEC register’s status address
and data reception are completed. Software writes a one to this bit to clear it.
• Primary CODEC ready interrupt: Sets a status register bit when the Primary CODEC is ready.
The CODEC sets bit 0 of Slot 0 on the input frame to signal that it is ready. Software clears the
PRIRDY_IEN bit of the GCR to clear this interrupt.
• Secondary CODEC ready interrupt: Sets a status register bit when the Secondary CODEC is
ready. The CODEC sets bit 0 of Slot 0 on the input frame to signal that it is ready. Software
clears the SECRDY_IEN bit of the GCR to clear this interrupt.
13.8.3 Registers
The ACUNIT and CODEC registers are mapped in addresses ranging from 0x4050_0000 through
0x405F_FFFF. All ACUNIT registers are 32-bit addressable. Even though a CODEC has up to
sixty-four 16-bit registers that are 16-bit addressable, they are accessed via a 32-bit address map
and translated to 16-bits for the CODEC.
Programmed I/O and DMA bursts can access the following registers:
• Global registers: The ACUNIT has three global registers: Status, Control, and CODEC access
registers that are common to the audio and modem domains.
• Channel-specific audio ACUNIT registers refer to PCM-out, PCM-in, and mic-in channels.
• Channel-specific Modem ACUNIT registers refer to modem-out and modem-in channels.
• Audio CODEC registers
• Modem CODEC registers
Channel specific data registers are for FIFO accesses and the PCM, Modem, and Mic-in FIFOs
each have a register. A write access to one of these registers updates the written data in the
corresponding Transmit FIFO. A read access to one of these registers flushes out an entry from the
corresponding Receive FIFO.
Note: Register tables show organization and individual bit definitions. All reserved bits are read as
unknown values and must be written with a 0. A question mark indicates the value is unknown at
reset.
Note: Some register bits receive status from CODECs. The CODEC status sets the bit and software clears
the bit (write a one to clear). The status can come in at any time, even when the bit is set or during
a software clear. If software clears the bit as the CODEC status updates the bit, the CODEC status
event takes higher priority. The term “interruptible” denotes bits that can be affected by this
condition.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECRDY_IEN
SECRES_IEN
ACLINK_OFF
PRIRDY_IEN
PRIRES_IEN
WARM_RST
COLD_RST
CDONE_IE
SDONE_IE
reserved
GIE
reserved reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SECRDY_IEN
SECRES_IEN
ACLINK_OFF
PRIRDY_IEN
PRIRES_IEN
WARM_RST
COLD_RST
CDONE_IE
SDONE_IE
reserved
GIE
reserved reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
Secondary Resume Interrupt Enable:
5 SECRES_IEN 0 = Interrupt is disabled
1 = Enables an interrupt to occur when the Secondary CODEC causes a resume event on
the AC-link
Primary Resume Interrupt Enable:
4 PRIRES_IEN 0 = Interrupt is disabled
1 = Enables an interrupt to occur when the Primary CODEC causes a resume event on the
AC-link
AC-link Shut Off:
0 = If the AC-link was off, turns it back on, otherwise this bit has no effect.
1 = Causes the ACUNIT to drive SDATA_OUT and SYNC outputs low and turn off input
3 ACLINK_OFF buffer enables. The reset output is however maintained high. The AC-link will not be
allowed to access any of the FIFOs.
Setting this bit does not ensure a clean shut down. Software must make sure that all
transactions are complete before setting this bit.
AC’97 Warm Reset
0 = A warm reset is not generated.
1 = Causes a warm reset to occur on the AC-link. The warm reset will awaken a
2 WARM_RST suspended CODEC without clearing it’s internal registers.
If software attempts to perform a warm reset while BITCLK is running, the write will be
ignored and the bit will not change. This bit is self clearing i.e., it remains set until the reset
completes and BITCLK is seen on the AC-link after which it clears itself.
AC'97 Cold Reset
0 = Causes a cold reset to occur throughout the AC'97 circuitry. All data in the ACUNIT
and the CODEC will be lost.
1 COLD_RST 1 = A cold reset is not generated.
Defaults to 0. After reset, the driver must to set this bit to a 1.The value of this bit is retained
after suspends, hence, if this bit was set to a 1 before a suspend, a cold reset is not
generated on a resume.
CODEC GPI Interrupt Enable (GIE)
This bit controls whether the change in status of any Modem CODEC GPI causes an
interrupt.
0 GIE 0 = If this bit is not set, bit 0 of the Global Status Register is set, but an interrupt is not
generated.
1 = If this bit is set, the change in value of a GPI (as indicated by bit 0 of slot 12) causes an
interrupt and sets bit 0 of the Global Status Register
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIT3SLT12
BIT2SLT12
BIT1SLT12
reserved
reserved
SECRES
PRIRES
CDONE
SDONE
MOINT
POINT
RDCS
MIINT
PIINT
MINT
GSCI
SCR
PCR
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT3SLT12
BIT2SLT12
BIT1SLT12
reserved
reserved
SECRES
PRIRES
CDONE
SDONE
MOINT
POINT
RDCS
MIINT
PIINT
MINT
GSCI
SCR
PCR
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
reserved
FEIE
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
FEIE
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
FIFOE
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
FIFOE
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAIP
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCM_RDATA PCM_LDATA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Writing a 32-bit sample to this register updates the data into the PCM Transmit FIFO. Reading this
register gets a 32-bit sample from the PCM Receive FIFO.
PCDR Register
PCM Transmit FIFO PCM Receive FIFO
31 0
TxEntry3 TxFIFO RxFIFO RxEntry3
Written Read
TxEntry2 RxEntry2
TxEntry1 RxEntry1
TxEntry0 RxEntry0
Right Left Right Left
31 16 15 0 31 16 15 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
FEIE
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
FIFOE
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MIC_IN_DAT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Receive
Processor/DMA
Data
Read
RxEntry15
RxFIFO RxEntry3
Read
RxEntry2
RxEntry1
RxEntry0
15 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
FEIE
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
FEIE
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
FIFOE
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
FIFOE
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MODEM_DAT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A 32-bit sample write to this register updates the data into the Modem Transmit FIFO. A read to
this register gets a 32-bit sample from the Modem Receive FIFO.
Transmit Receive
data Processor/DMA Processor DMA Data
Write Read
TxEntry15 RxEntry15
TxEntry2 RxEntry2
TxEntry1 RxEntry1
TxEntry0 RxEntry0
15 0 15 0
In the equations, Shift_Left_Once() shifts the 7-bit CODEC address left by one bit and shifts a 0 to
the LSB. The address translations are shown in Table 13-23.
14.1 Overview
The I2SC consists of buffers, status and control registers, serializers, and counters for transferring
digitized audio between the processor system memory and an external I2S CODEC.
For playback of digitized audio or production of synthesized audio, the I2SC retrieves digitized
audio samples from processor system memory and sends them to a CODEC through the I2SLINK.
The external digital-to-analog converter in the CODEC then converts the audio samples into an
analog audio waveform.
For recording of digitized audio, the I2SC receives digitized audio samples from a CODEC
(through the I2SLINK) and stores them in processor system memory.
The I2S controller supports the normal-I2S and the MSB-Justified-I2S formats. Four, or optionally
five, pins connect the controller to an external CODEC:
• A bit-rate clock, which can use either an internal or an external source.
• A formatting or “Left/Right” control signal.
• Two serial audio pins, one input and one output.
• The bit-rate clock, an optional system clock also sent to the CODEC by the I2SC.
The I2S data can be stored to and retrieved from system memory either by the DMA controller or
by programmed I/O.
For I2S systems, additional pins are required to control the external CODEC. Some CODECs use
an L3 control bus, which requires 3 signals — L3_CLK, L3_DATA, and L3_MODE — for writing
bytes into the L3-bus register. The I2SC supports the L3 bus protocol via software control of the
general-purpose I/O (GPIO) pins. The I2SC does not provide hardware control for the L3 bus
protocol.
Two similar protocols exist for transmitting digitized stereo audio over a serial path: Normal-I2S
and MSB-Justified-I2S. Both work with a variety of clock rates, which can be obtained by dividing
the PLL clock by a programmable divider, or from an external clock source. For further details
regarding clock rates, see Table 14-2.
BITCLK supplies the serial audio bit rate, which is the basis for the external CODEC bit-sampling
logic. BITCLK is one-quarter the frequency of SYSCLK and is 64 times the audio sampling
frequency. One bit of the serial audio data sample is transmitted or received each BITCLK period.
A single serial audio sample comprises a “left” and “right” signal, each containing either 8, 16 or
32 bits.
SYNC is BITCLK divided by 64, resulting in an 8 kHz to 48 kHz signal. The state of SYNC is
used to denote whether the current serial data samples are “Left” or “Right” channel data.
The SDATA_IN and SDATA_OUT data pins are used to send/receive the serial audio data to/from
the CODEC.
Table 14-1 lists the signals between the I2S and an external CODEC device.
BITCLK can be configured either as an input or as an output. To program the direction, follow
these steps:
1. Program SYSUNIT’s GPIO Direction Register (GPDR). See Section 4.1.3.2, “GPIO Pin
Direction Registers (GPDR0, GPDR1, GPDR2)” on page 4-8 for details regarding the GPDR.
2. Program SYSUNIT’s GPIO Alternate Function Select Register (GAFR). See Section 4.1.3.6,
“GPIO Alternate Function Register (GAFR0_L, GAFR0_U, GAFR1_L, GAFR1_U,
GAFR2_L, GAFR2_U)” on page 4-16 for details regarding the GAFR.
3. Program the BCKD bit in the I2SC’s Serial Audio Control Register. See Section 14.6.1,
“Serial Audio Controller Global Control Register (SACR0)” for more details.
Note: Modifying the status of the SACR0[BCKD] bit during normal operation can cause jitter on the
BITCLK and can affect serial activity.
2. Program SYSUNIT’s GPIO Alternate Function Select Register (GAFR). See Section 4.1.3.6,
“GPIO Alternate Function Register (GAFR0_L, GAFR0_U, GAFR1_L, GAFR1_U,
GAFR2_L, GAFR2_U)” on page 4-16 for details regarding the GAFR.
The processor uses programmed I/O instructions to access the I2SC and can access the following
types of data:
• I2SC registers data — All registers are 32 bits wide and are aligned to word boundaries. See
Section 14.6 for further details.
• I2SC FIFO data — An entry is placed into the Transmit FIFO by writing to the I2SC’s Serial
Audio Data register (SADR). Writing to SADR updates a Transmit FIFO entry. Reading
SADR flushes out a Receive FIFO entry.
• I2S CODEC data — The CODEC registers can be accessed through the L3 bus. The L3 bus
operation is emulated by software controlling 3 GPIO pins.
The DMA controller can only access the FIFOs. Accesses are made through the SADR, as
explained in the previous paragraph. The DMA controller accesses FIFO data in blocks of 8, 16, or
32 bytes. The DMA controller responds to the following DMA requests made by the I2SC:
• The Transmit FIFO request is based on the transmit threshold (TFTH) setting and is asserted if
the Transmit FIFO has less than TFTH+1 entries. See Table 14-3 for further details regarding
TFTH.
• The Receive FIFO request is based on the receive threshold (RFTH) setting and is asserted if
the Receive FIFO has RFTH+1 or more entries. See Table 14-3 for further details regarding
RFTH.
14.3.1 Initialization
1. Set the BITCLK direction by programming the SYSUNIT’s GPIO Direction register, the
SYSUNIT’s GPIO Alternate Function Select register, and bit 2 of the I2SC’s Serial Audio
Controller Global Control Register (SACR0).
2. Choose between Normal I2S or MSB-Justified modes of operation. This can be done by
programming bit 0 of Serial Audio Controller I2S/MSB-Justified Control Register (SACR1).
For further details, see Section 14.6.2.
3. Optional: Programmed I/O may be used for priming the Transmit FIFO with a few samples
(ranging from 1 to 16). If the I2SLINK is enabled with an empty Transmit FIFO, a Transmit
Under-run error bit will be set in the Status register. For further details, see Section 14.6.3.
This is hence an optional step, which prevents such an error. If Step 3 is not executed, then
Programmed I/O must clear the Transmit Under-run status bit by setting bit 5 of the Interrupt
Clear Register. For further details, see Section 14.6.5.
4. The following control bits can be simultaneously programmed in the I2SC’s Serial Audio
Controller Global Control register (SACR0):
a. Enable I2SLINK by setting the ENB bit (bit-0) of SACR0.
b. Maintain BITCLK direction as programmed in Step1. Modifying BITCLK direction will
glitch the clock and affect I2SLINK activity.
c. Program transmit and receive threshold levels by programming the TFTH and RFTH bits
of SACR0[11:8] and SACR0(15:12), respectively. See Section 14.6.1.2, regarding
permitted threshold levels.
Once the I2SLINK is enabled, frames filled with 0s will be transmitted if the Transmit FIFO is
still empty. This will set a Transmit Under-run status bit in SASR0. Step 3 can be executed to
avoid this error condition. Valid data is sent across the I2SLINK after filling the Transmit
FIFO with at least one sample. One sample consists of a 32-bit value with 16 bits each
dedicated to a left and a right value.
Enabling the I2SLINK will also cause zeros to be recorded by the I2SC until the CODEC
sends in valid data.
Enabling the I2SLINK also enables transmit and receive DMA Requests.
During the second condition, the last valid sample is continuously sent across the I2SLINK until
the I2SC is turned off by disabling the SACR0[ENB] bit.
If the total buffer size of the received data is less than a factor of the receive threshold, zeross will
be recorded. A receive DMA request is made when the programmed threshold is reached.
BITCLK can be supplied either by the CODEC or by an internal PLL. If supplied internally,
BITCLK and SYSCLK are configured as output pins, and both are supplied to the CODEC. If
BITCLK is supplied by the CODEC, then it is configured as an input pin. In this case, the
SYSCLK’s GPIO pin can be used for an alternate function.
The BITCLK, as shown in Table 14-2, is different for different sampling frequencies. If the
BITCLK is chosen as an output, the Audio Clock Divider Register divides the 147.46MHz PLL
clock to generate the SYSCLK. The SYSCLK is further divided by four to generate the BITCLK.
The sampling frequency is the frequency of the SYNC signal, which is generated by dividing the
BITCLK by 64. See Section 14.6.4, for further details about the register.
A sampling rate of 48kHz supports MPEG2 and MPEG4. A rate of 44.1kHz supports MP3.
0x0000_000C 12.288 MHz 3.072 MHz 48.000 kHz (closest std = 48 kHz)
0x0000_000D 11.343 MHz 2.836 MHz 44.308 kHz (closest std = 44.1 kHz)
0x0000_001A 5.671 MHz 1.418 MHz 22.154 kHz (closest std = 22.05 kHz)
0x0000_0024 4.096 MHz 1.024 MHz 16.000 kHz (closest std = 16.00 kHz)
0x0000_0034 2.836 MHz 708.92 kHz 11.077 kHz (closest std = 11.025 kHz)
0x0000_0048 2.048 MHz 512.00 kHz 8.000 kHz (closest std = 8.00 kHz)
Audio data is stored with two samples (Left + Right) per 32-bit word, even if samples are smaller
than 16 bits. The Left channel data occupies bits [15:0], while the Right channel data uses bits
[31:16] of the 32-bit word. Within each 16-bit field, the audio sample is left-justified, with unused
bits packed as zeroes on the right-hand (LSB) side.
In memory, the mapping of stereo samples is the same as in the FIFO buffers. However, single-
channel audio occupies a full 32-bit word per sample, using either the upper or lower half of the
word, depending on whether it’s considered a Left or Right sample.
The BITCLK supplies the serial audio bit rate, the basis for the external CODEC bit-sampling
logic. Its frequency is 64 times the audio sampling frequency. Divided by 64, the resulting 8 kHz to
48 kHz signal signifies timing for Left and Right serial data samples passing on the serial data
paths. This Left/Right signal is sent to the CODEC on the SYNC pin. Each phase of the Left/Right
signal is accompanied by one serial audio data sample on the data pins SDATA_IN and
SDATA_OUT.
Figure 14-1 and Figure 14-2 provide timing diagrams that show formats for I2S and MSB-justified
modes of operations.
Data is transmitted and received in frames of 64 BITCLK cycles. Each frame consists of a Left
sample and a Right sample. Each frame holds 16-bits of valid sample data (shown in the figures)
and 16-bits of padded zeros (not shown in the figures). The transmit and receive FIFOs only hold
valid sample data (not padded zero data).
In the Normal I2S mode, the SYNC is low for the Left sample and high for the Right sample. Also,
the MSB of each data sample lags behind the SYNC edges by one BITCLK cycle.
In the MSB-Justified mode, the SYNC is high for the Left sample and low for the Right sample.
Also, the MSB of each data sample is aligned with the SYNC edges.
Figure 14-1. I2S Data Formats (16 bits)
cycle0
0 1 2 3 13 14 15 16 29 30 31 32 33 34 35 45 46 47 48 62 63 0
BITCLK
15 14 13 3 2 1 0 15 14 13 12 3 2 1 0
SData_Out
cycle0
0 1 2 3 13 14 15 16 29 30 31 32 33 34 35 45 46 47 48 62 63 0
BITCLK
15 14 13 3 2 1 0 15 14 13 12 3 2 1 0
SData_Out
14.6 Registers
The I2S Controller registers are all 32-bit addressable, ranging from 0x4040_0000 through
0x404F_FFFF.
Note: If ENB is toggled in the middle of a normal operation, the RST bit must also be set and cleared to
reset all I2SC registers.
Note: The SACR0[ENB] control signal crosses clock domains. It is registered in an internal clock
domain that is much faster than the BITCLK domain. It takes four BITCLK cycles and four
internal clock cycles before SACR0[ENB] is conveyed to the slower BITCLK domain. If the
control setting is modified at a rate faster than (4 BITCLK + 4 internal clock) cycles, the last
updated value in this time frame is stored in a temporary register and is transferred to the BITCLK
domain.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
reserved
EFWR
BCKD
STRF
ENB
RST
reserved RFTH TFTH
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0
31:16 — reserved
Receive FIFO interrupt or DMA threshold. Set to value 0 – 15. This value must be set to the
15:12 RFTH threshold value minus 1.
Receive DMA Request asserted whenever the Receive FIFO has >= (RFTH+1) entries.
Transmit FIFO interrupt or DMA threshold. Set to value 0 – 15. This value must be set to
11:8 TFTH the threshold value minus 1.
Transmit DMA Request asserted whenever the Transmit FIFO has < (TFTH+1) entries.
7:6 — reserved
Select Transmit or Receive FIFO for EFWR based special purpose function:
0 = Transmit FIFO is selected
5 STRF
1 = Receive FIFO is selected
See Table 14-4 for details.
This bit enables a special purpose FIFO Write/Read function:
0 = Special purpose FIFO Write/Read Function is disabled
4 EFWR
1 = Special purpose FIFO Write/Read Function is enabled
See Table 14-4 for details.
Resets FIFOs logic and all registers, except this register (SACR0):
3 RST 0 = Not reset
1 = Reset is active to other registers
This bit specifies input/output direction of BITCLK:
2 BCKD 0 = Input. BITCLK driven by an external source.
1 = Output. BITCLK generated internally and driven out to the CODEC.
1 — reserved
Enable I2S function:
0 ENB 0 = I2SLINK is disabled
1 = I2SLINK is enabled
8 Bytes 2 0 14 1 15
16 Bytes 4 0 12 3 15
32 Bytes 8 0 8 7 15
SACR1 bits DRPL, DREC, and AMSL cross clock domains. They are registered in an internal
clock domain that is much faster than the BITCLK domain. It takes 4 BITCLK cycles and 4
internal clock cycles before these controls are conveyed to the slower BITCLK domain. If the
above control settings are modified at a rate faster than (4 BITCLK + 4 internal clock) cycles, the
last updated value in this time frame is stored in a temporary register and is transferred to the
BITCLK domain.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
ENLBF
DREC
AMSL
DRPL
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31:6 — reserved
Enable I2S/MSB Interface Loop Back Function:
5 ENLBF 0 = I2S/MSB Interface Loop Back Function is disabled
1 = I2S/MSB Interface Loop Back Function is enabled
Disable Replaying Function of I2S or MSB-Justified Interface:
4 DRPL 0 = Replaying Function is enabled
1 = Replaying Function is disabled
Disable Recording Function of I2S or MSB-Justified Interface:
3 DREC 0 = Recording Function is enabled
1 = Recording Function is disabled
2:1 — reserved
Specify Alternate Mode (I2S or MSB-Justified) Operation:
0 AMSL 0 = Select I2S Operation Mode
1 = Select MSB-Justified Operation Mode
Only 4 bits are assigned for TFL and RFL. Actual fill levels are interpreted as follows:
Actual_RFL(4:0) calculation:
if (RFL(3:0) == 4’b0)
Actual_RFL(4:0) = {RNE, RFL(3:0)}
else
Actual_RFL(4:0) = {1’b0, RFL(3:0)}
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
ROR
RNE
TUR
RFS
BSY
TNF
TFS
reserved RFL TFL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
31:16 — reserved
15:12 RFL Receive FIFO Level: number of entries in Receive FIFO
11:8 TFL Transmit FIFO Level: number of entries in Transmit FIFO
7 — reserved
Receive FIFO Overrun:
0 = Receive FIFO has not experienced an overrun
6 ROR 1 = I2S attempted data write to full Receive FIFO (Interruptible)
Can interrupt processor if bit6 of Serial Audio Interrupt Mask Register is set.
Cleared by setting bit 6 of Serial Audio Interrupt Clear Register.
Transmit FIFO Under-run:
0 = Transmit FIFO has not experienced an under-run
5 TUR 1 = I2S attempted data read from an empty Transmit FIFO
Can interrupt processor if bit 5 of Serial Audio Interrupt Mask Register is set.
Cleared by setting bit 5 of Serial Audio Interrupt Clear Register.
Receive FIFO Service Request:
0 = Receive FIFO level below RFL threshold, or I2S disabled
4 RFS 1 = Receive FIFO level is at or above RFL threshold.
Can interrupt processor if bit 4 of Serial Audio Interrupt Mask Register is set.
Cleared automatically when # of Receive FIFO entries < (RFTH + 1).
Transmit FIFO Service Request:
0 = Transmit FIFO level exceeds TFL threshold, or I2S disabled
3 TFS 1 = Transmit FIFO level is at or below TFL threshold
Can interrupt processor if bit 3 of Serial Audio Interrupt Mask Register is set.
Cleared automatically when # of Transmit FIFO entries >= (TFTH + 1).
I2S Busy:
2 BSY 0 = I2S is idle or disabled
1 = I2S currently transmitting or receiving a frame
Receive FIFO not empty:
1 RNE 0 = Receive FIFO is empty
1 = Receive FIFO is not empty
Transmit FIFO not full:
0 TNF 0 = Transmit FIFO is full
1 = Transmit FIFO is not full
Note: Setting this register to values other than those shown in Section 14.2 is not allowed and will cause
unpredictable activity.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SADIV
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0
31:7 — reserved
Audio clock divider. Valid SADIV(6:0) are:
000 1100 – BITCLK of 3.072MHz
000 1101 – BITCLK of 2.836 MHz
6:0 SADIV 001 1010 – BITCLK of 1.418MHz
010 0100 – BITCLK of 1.024MHz
011 0100 – BITCLK of 708.92 KHz
100 1000 – BITCLK of 512.00 KHz
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ROR
TUR
reserved reserved
Reset r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r
31:7 — reserved
6 ROR Clear Receive FIFO overrun Interrupt and ROR status bit in SASR0.
5 TUR Clear Transmit FIFO under-run Interrupt and TUR status bit in SASR0.
4:0 — reserved
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ROR
TUR
RFS
TFS
reserved reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 14-3 illustrates data flow through the FIFOs and SADR.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTH DTL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 14-3. Transmit and Receive FIFO Accesses Through the SADR
SADR Register
PCM Transmit FIFO PCM Receive FIFO
31 0
TxEntry3 TxFIFO RxFIFO RxEntry3
Written Read
TxEntry2 RxEntry2
TxEntry1 RxEntry1
TxEntry0 RxEntry0
Right Left Right Left
31 16 15 0 31 16 15 0
14.7 Interrupts
The following SASR0 status bits, if enabled, interrupt the processor:
• Receive FIFO Service DMA Request (RFS)
• Transmit FIFO Service DMA Request (TFS)
• Transmit Under-run (TUR)
• Receive Over-run (ROR).
15.1 Overview
The PXA255 processor MultiMediaCard (MMC) controller acts as a link between the software
used to access the processor and the MMC stack (a set of memory cards). The MMC controller is
designed to support the MMC system, a low-cost data storage and communications system. A
detailed description of the MMC system is available through the MMC Association’s web site at
www.mmca.org. The processor’s MMC controller is based on the standards outlined in The
MultiMediaCard System Specification Version 2.1 with the exception that one- and three-byte data
transfers are not supported and the maximum block length is 1023.
The MMC controller supports the translation protocol from a standard MMC or Serial Peripheral
Interface (SPI) bus to the MMC stack. The software used to access the processor must indicate
whether to use MMC or SPI mode as the protocol to communicate with the MMC controller.
The MMC controller contains all card-specific functions, serves as the bus master for the MMC
system, and implements the standard interface to the card stack. The controller handles card
initialization; CRC generation and validation; and command, response, and data transactions.
The MMC controller is a slave to the software and consists of command and control registers, a
response FIFO, and data FIFOs. The software has access to these registers and FIFOs and
generates commands, interprets responses, and controls subsequent actions.
Figure 15-1 shows a block diagram of the interaction of a typical MMC stack, the MMC controller,
and a software.
Figure 15-1. MMC System Interaction
MMCLK
MMCMD
Software Processor’s MMC
MMDAT
MMC Stack
Interface Controller MMCCS0
MMCCS1
The MMC bus connects the card stack to the controller. The software and controller can turn the
MMC clock on and off. The card stack and the controller communicate serially through the
command and data lines and implement a message-based protocol. The messages consist of the
following tokens:
• Command: a 6-byte command token starts an operation. The command set includes card
initialization, card register reads and writes, data transfers, etc. The MMC controller sends the
command token serially on the MMCMD signal. The format for a command token is shown in
Table 15-1.
47 1 0 start bit
46 1 1 transmission bit
[45:40] 6 x command index
[39:8] 32 x argument
[7:1] 7 x CRC7
0 1 1 end bit
• Response: a response token is an answer to a command token. Each command has either a
specific response type or no response type. The format for a response token varies according to
the response expected and the card’s mode. Response token formats are detailed The
MultiMediaCard System Specification Version 2.1.
• Data: data is transferred serially between the controller and the card in 8-bit blocks at rates up
to 20 Mbps. The format for the data token depends on the card’s mode. Table 15-2 shows the
data token format for MMC mode and Table 15-3 shows the data token format for SPI mode.
1 0 start bit
x x data
no CRC x CRC7
1 1 end bit
In MMC mode, all operations contain command tokens and most commands have an associated
response token. Read and write commands also have a data token. Command and response tokens
are sent and received on the bidirectional MMCMD signal and data tokens are sent and received on
the bidirectional MMDAT signal. A typical MMC mode command timing diagram with and
without a response is shown in Figure 15-2 while Figure 15-3 shows a typical MMC mode timing
diagram for a sequential read or write
.
MMDAT
from from
stop command
host to data to/from stops data transfer
In SPI mode, not all commands are available. The available commands have both a command and
response token. The MMCMD and MMDAT signals are no longer bidirectional in SPI mode. The
MMCMD is an output and the MMDAT is an input with respect to the processor. The command
and data tokens to be written are sent on the MMCMD signal and the response and read data tokens
are received on the MMDAT signal. Figure 15-4 shows a typical SPI mode timing diagram without
a data token. Figure 15-5 and Figure 15-6 show SPI mode read and write timing diagrams,
respectively.
Note: One- and three-byte data transfers are not supported with this controller. Data transfers of 10 or
more bytes are supported for stream writes only.
Refer to The MultiMediaCard System Specification for detailed information on MMC and SPI
modes of operation.
The MMC controller is the interface between the software and the MMC bus. It is responsible for
the timing and protocol between the software and the MMC bus. It consists of control and status
registers, a 16-bit response FIFO that is eight entries deep, two 8-bit receive data FIFOs that are 32
entries deep, and two 8-bit transmit FIFOs that are 32 entries deep. The registers and FIFOs are
accessible by the software.
The MMC controller also enables minimal data latency by buffering data and generating and
checking CRCs.
The MMCLK, MMCCS0, and MMCCS1 signals are routed through alternate functions within the
GPIO. Refer to Section 4.1, “General-Purpose I/O” on page 4-1 for a description of the process
used to assign these signals to a specific GPIO. Even though there are several GPIO assigned to
each signal, each signal must be programmed to one of the possible GPIOs. Refer to Section 4.1.2,
“GPIO Alternate Functions” on page 4-2 for a complete description of the GPIO alternate
functions.
After the 80-clock initialization sequence, the software must continuously send CMD1 (see
Table 15-18 for command definitions) by loading the appropriate command index into the
MMC_CMD register until the card indicates that the power-up sequence is complete. The software
can then assign an address to the card or put it into SPI mode.
After an MMC card is powered on, it is assigned a default relative card address (RCA) of 0x0001.
The software assigns different addresses to each card during the initialization sequence described
in Section 15.2.3. A card is then addressed by its new relative address in the argument portion of
the command token that is protected with a 7-bit CRC (see Table 15-1). For a description of the
identification process when multiple cards are connected to a system, refer to the Card
Identification Process as described in The MultiMediaCard System Specification.
There are five formats for the response token, including a no response token. The response token
length is 48 or 136 bits and may be protected with a 7-bit CRC. Details of the response token can
be found in The MultiMediaCard System Specification.
In write data transfers, the data is suffixed with a 5-bit CRC status token from the card. After the
CRC status token, the card may indicate that it is busy by pulling the MMDAT line low.
The start address for a read operation can be any random byte address in the valid address space of
the card memory. For a write operation, the start address must be on a sector boundary and the data
length must be an integer multiple of the sector length. A sector is the number of blocks that will be
erased during the write operation and is fixed for each MMC card. A block is the number of bytes
to be transferred.
Note: When the card is in SPI mode, the only way to return to MMC mode is by toggling the power to the
card.
Card addressing is implemented with hardware chip selects, MMCCS1 and MMCCS0. All
command, response, and data tokens are 8-bits long and are transmitted immediately following the
assertion of the respective chip select.
The command token is protected with a 7-bit CRC. The card always sends a response to a
command token. The response token has four formats, including an 8-bit error response. The length
of the response tokens is one, two, or five bytes.
SPI mode offers a non protected mode. In this mode, CRC bits of the command, response, and data
tokens are still required in the tokens but these bits are ignored by the card and the controller.
In write data transfers, the data is suffixed with an 8-bit CRC status token from the card. As in
MMC mode, the card may indicate that it is busy by pulling the MMDAT line low after the status
token. In read data transfers, the card may respond with the data or a data error token one byte long.
15.2.6 Interrupts
The MMC controller generates interrupts to signal the status of a command sequence. The software
is responsible for masking the interrupts appropriately, verifying the interrupts, and performing the
appropriate action as necessary.
Interrupts and masking are described in Section 15.5.11 and Section 15.5.12. The
CMDAT[DMA_EN] bit will also mask the MMC_I_MASK[RXFIFO_RD_REQ] and
MMC_I_MASK[TXFIFO_WR_REQ] interrupt bits.
The MMC controller has an internal frequency generator that may start, stop, and divide the MMC
bus clock. The software may start and stop the clock by setting the appropriate bits in the
MMC_STRPCL register. The MMCLK frequency is controlled by the value written in the
MMC_CLKRT register.
To write any MMC controller register for the next command sequence, software must:
1. Stop the clock.
2. Write the registers.
3. Restart the clock.
Software must not stop the clock when it attempts to read the receive FIFOs or write the transmit
FIFOs. When the clock stops, it resets the pointers in the FIFOs and any data left in the FIFOs can
not be transmitted or accessed. When the receive FIFOs are empty and the
MMC_STAT[DATA_TRAN_DONE] is set, software may stop the clock.
The software can specify the clock divisor of the 20 Mhz clock by setting the MMC_CLKRT
register. The clock rate may be set as:
• 20 Mhz
• 1/2 of 20 Mhz, 10 Mhz
• 1/4 of 20 Mhz, 5 Mhz
• 1/8 of 20 Mhz, 2.5 Mhz
• 1/16 of 20 Mhz, 1.25 Mhz
• 1/32 of 20 Mhz, 625 khz
• 1/64 if 20 Mhz, 312.5 khz
The controller can also turn the clock off automatically. If both receive FIFOs become full during
data reads, or one receive FIFO is being read by the software and the other receive FIFO becomes
full, or both transmit FIFOs become empty during data writes, or one transmit FIFO is being
written by the software and the other transmit FIFO is empty, the controller will automatically turn
the clock off to prevent data overflows and under runs. For read data transfers, the controller turns
the clock back on after a receive FIFO has been emptied. For write data transfers, the controller
turns the clock back on after the transmit FIFO is no longer empty.
Warning: Stopping the clock while data is in the transmit or receive FIFOs will cause unpredictable results.
If the software stops the clock at any time, it must wait for the MMC_STAT[CLK_EN] status bit to
be cleared before proceeding.
The FIFO will hold all possible response lengths. Responses that are only one byte long are located
on the MSB of the 16-bit entry in the FIFO. The first half-word read from the response FIFO is the
most significant half-word of the received response.
The FIFO does not contain the response CRC. The status of the CRC check is in the status register,
MMC_STAT.
Both FIFOs and their controls are cleared to a starting state after a system reset and at the
beginning of all command sequences.
The FIFOs swap between the software and MMC bus. At any time, while the software has read
access to one of the FIFOs, the MMC bus has write access to the other FIFO.
For purposes of an example, the FIFOs are called RXFIFO1 and RXFIFO2. After a reset or at the
beginning of a command sequence, both FIFOs are empty and the software has read access to
RXFIFO1 and the MMC has write access to RXFIFO2. When RXFIFO2 becomes full and
RXFIFO1 is empty, the FIFOs swap and the software has read access to RXFIFO2 and the MMC
has write access to RXFIFO1. When RXFIFO1 becomes full and RXFIFO2 is empty, the FIFOs
swap and the software has read access to RXFIFO1 and the MMC has write access to RXFIFO2.
This swapping process continues through out the data transfer and is transparent to both the
software and the MMC controller.
If at any time both FIFOs become full and the data transmission is not complete, the controller
turns the MMCLK off to prevent any overflows. When the clock is off, data transmission from the
card stops until the clock is turned back on. After the software has emptied the FIFO that it is
connected to, the controller turns the clock on to continue data transmission.
The full status of the FIFO that the software is connected to is registered in the
MMC_STAT[RECV_FIFO_FULL] bit.
The receive FIFO is readable on byte boundaries and the FIFO read request is only asserted once
per FIFO access (once per 32 bytes available). Therefore, 32 bytes must be read for each request,
except for the last read which may be less than 32 bytes.
If the DMA is used, it must be programmed to do 1-byte reads of 32-byte bursts. The last read can
be less than a 32-byte burst. Some examples are:
• Receive 96 bytes of data:
Read 32 bytes three times.
For the DMA, use three descriptors of 32 bytes and 32-byte bursts.
• Receive 98 bytes of data:
Read 32 bytes three times, then read two more bytes.
For the DMA, use three descriptors of 32 bytes and 32-byte bursts and one descriptor of two
more bytes and 8-, 16-, or 32- byte bursts.
• Receive 105 bytes:
Read 32 bytes three times, then read nine more bytes.
For the DMA, use three descriptors of 32 bytes and 32-byte bursts and one descriptor of nine
or more bytes and 16- or 32-byte bursts.
Both FIFOs and their controls are cleared to a starting state after a system reset and at the
beginning of all command sequences.
The FIFOs swap between the software and MMC bus. At any time, while the software has write
access to one of the FIFOs, the MMC bus has read access to the other FIFO.
For purposes of an example, the FIFOs are called TXFIFO1 and TXFIFO2. After a reset or at the
beginning of a command sequence, both FIFOs are empty and the software has write access to
TXFIFO1 and the MMC has read access to TXFIFO2. When TXFIFO1 becomes full and
TXFIFO2 is empty, the FIFOs swap and the software has write access to TXFIFO2 and the MMC
has read access to TXFIFO1. When TXFIFO2 becomes full and TXFIFO1 is empty, the FIFOs
swap and the software has write access to TXFIFO1 and the MMC has read access to TXFIFO2.
This swapping process continues through out the data transfer and is transparent to both the
software and the MMC controller.
If at any time both FIFOs become empty and the data transmission is not complete, the controller
turns the MMCLK off to prevent any underruns. When the clock is off, data transmission to the
card stops until the clock is turned back on. When the transmit FIFO is no longer empty, the MMC
controller automatically restarts the clock.
If the software does not fill the FIFO to which it is connected, the
MMC_PRTBUF[BUF_PART_FULL] bit must be set to a 1. This enables the FIFOs to swap
without filling the FIFO.
The empty status of the FIFO that the software is connected to is registered in the
MMC_STAT[XMIT_FIFO_EMPTY] bit.
The transmit FIFO is writable on byte boundaries and the FIFO write request is only asserted once
per FIFO access (once per 32 entries available). Therefore, 32 bytes must be written for each
request, except for the last write which may be less than 32 bytes.
When the DMA is used, it must be programmed to do 1-byte writes of 32-byte bursts. The last
write can be less than a 32-byte burst.
If the last write is less than 32 bytes, then the MMC_PRTBUF[BUF_PART_FULL] bit must be set.
When the DMA is used, the last descriptor must be programmed to allow the DMA to set an
interrupt after the data is written to the FIFO. After the interrupt occurs, the software must set the
MMC_PRTBUF[BUF_PART_FULL] bit.
To access the FIFOs with the DMA, the software must program the DMA to read or write the
MMC FIFOs with single byte transfers, and 32-byte bursts. For example, to write 64 bytes of data
to the MMC_TXFIFO, the software must program the DMA to write 64 bytes with an 8-bit port
size to the MMC and for 32-byte bursts. The MMC issues a request to read the MMC_RXFIFO and
a request to write the MMC_TXFIFO.
The CMDAT[DMA_EN] bit must be set to a 1 to enable communication with the DMA and it must
be set to a 0 to enable program I/O.
Some cards may become busy as the result of a command. The software may wait for the card to
become not busy by writing the MMC_I_MASK register and waiting for the
MMC_I_REG[PRG_DONE] interrupt or the software can start communication to another card.
The software may not access the same card again until the card is no longer busy. Refer to The
MultiMediaCard System Specification for additional information.
The software must follow the steps as described in Section 15.3.1. In addition, before starting the
clock, the software must write these registers as necessary.
• MMC_RDTO
• MMC_BLKLEN
• MMC_NOB
After the software writes the registers and starts the clock, the software must read the MMC_RES
as described above and read or write the MMC_RXFIFO or MMC_TXFIFO FIFOs.
After completely reading or writing the data FIFOs, the software must wait for the appropriate
interrupts. The status register, MMC_STAT, must be read to ensure that the transaction is complete
and to check the status of the transaction.
When using DMA request signals, the controller indicates to the DMA when a FIFO is ready for
reading or writing. It is expected that all FIFO reads and writes will empty and fill the FIFO to
which it is connected. If at any time the MMC_TXFIFO is not filled (32 bytes) by the software, the
software must notify the controller by setting the MMC_PRTBUF[BUF_PART_FULL]. The
software can write more bytes of data than is needed into the MMC_TXFIFO, but the controller
will only transmit the number of bytes in the MMC_BLKLEN register.
At the end of any data transfer or busy signal on the MMC bus, the MMC controller waits eight
MMC clocks before asserting the MMC_I_REG[DATA_TRAN_DONE] interrupt to notify the
software that the data transfer is complete. This guarantees that the specified minimum of eight
MMC clocks occurs between a data transfer and the next command.
On write data transfers, a card may become busy while programming the data. The software may
wait for the card to become not busy by writing the MMC_I_MASK register and waiting for the
MMC_I_REG[PRG_DONE] interrupt or the software can start communication to another card.
Refer to The MultiMediaCard System Specification for additional information.
The MMC controller performs data transactions in all the basic modes: single block, multiple
blocks, and stream modes.
After turning the clock on to start the command sequence, the software must program the DMA to
fill the MMC_TXFIFO (write 32 bytes). The software must continue to fill the FIFO until all of the
data has been written to the FIFOs. The software must then wait for the transmission to complete
by waiting for the MMC_I_REG[DATA_TRAN_DONE] interrupt and
MMC_I_REG[PRG_DONE] interrupt. The software can then read the status register,
MMC_STAT, to verify the status of the transaction.
For multiple block writes, The MultiMediaCard System Specification specifies that the card will
continue to receive blocks of data until the stop transmission command is received. After the
controller has transmitted the number of bytes specified in the MMC_NOB register, the controller
will stop transmitting data. After the MMC_I_REG[DATA_TRAN_DONE] interrupt is detected,
the software must setup the controller to send the stop transmission command, CMD12. Consult
The MultiMediaCard System Specification for a description of the stop transmission command.
If both transmit FIFOs become empty during data transmission, the MMC controller turns the
clock off. After a FIFO has been written, the controller turns the clock back on.
After turning the clock on to start the command sequence, the software must program the DMA to
empty the MMC_RXFIFO (read 32 bytes). The software will continue the process of emptying the
FIFO until all of the data has been read from the FIFO. The software must then wait for the
transmission to complete by waiting for the MMC_I_REG[DATA_TRAN_DONE] interrupt. The
software can then read the status register, MMC_STAT, to verify the status of the transaction.
For multiple block reads, The MultiMediaCard System Specification specifies that the card will
continue to send blocks of data until the stop transmission command is received. After the
controller has received the number of bytes specified in the MMC_NOB register, the controller will
stop receiving data. After the MMC_I_REG[DATA_TRAN_DONE] interrupt is detected, the
software must set up the controller to send the stop transmission command, CMD12. Consult The
MultiMediaCard System Specification for a description of the stop transmission command.
If both receive FIFOs become full during the data transmission, the controller turns the clock off.
Once the software empties the FIFO to which it is connected, the controller turns the clock back on.
After turning the clock on to start the command sequence, the software must start the process of
filling the MMC_TXFIFO and starting the clock as describe in Section 15.3.2.1. The software must
then wait for the MMC_I_REG[STOP_CMD] interrupt. This interrupt indicates that the MMC
controller is ready for the stop transmission command. The software must then stop the clock, write
the registers for a stop transmission command, and then start the clock. At this point, the software
must wait for the MMC_I_REG[DATA_TRAN_DONE] and MMC_I_REG[PRG_DONE]
interrupts.
After turning the clock on to start the command sequence, the software must start the process of
reading the MMC_RXFIFO as described in Section 15.3.2.2.
When it uses the DMA, the software must also configure the DMA to send an interrupt after all
data has been read. After the DMA interrupt or the program has read all of the data, the software
must send the stop transmission command. The MCC_STAT[DATA_TRAN_DONE] bit is not set
until after software sends the stop transmission command.
While a busy signal is on the MMC bus, the software can send only one of two commands:
• Send status command (CMD13).
• Disconnect command (CMD7).
If the software disconnects a card while it is in a busy state, the busy signal will be turned off and
the software can connect a different card. The software may not start another command sequence
on the same card while the card is busy.
Note: The clock must be stopped before writing to any registers as described in Section 15.3.1.
In SPI mode, the software has the option of performing a CRC check. The default is no CRC
checking.
The command and data are sent on the MMC bus aligned to every 8 clocks as described in the SPI
section of The MultiMediaCard System Specification.
In a read sequence, the card may return data or a data error token. If a data error token is received,
the controller will stop the transmission and update the status register.
15.4.2 Initialize
Card initialization sequences must be prefixed with 80 clock cycles. To generate 80 clock cycles
before any command, the software must set the MMC_CMDAT[INIT] bit.
3. MMC_SPI[SPI_CS_ADDRESS] must be set to specify the card that the software wants to
address. A 1 enables CS0 and a 0 enables CS1.
Note: When the card is in SPI mode, the only way to return to MMC mode is by toggling power to the
card.
The software must not make changes in the set of registers until the end of the command and
response sequence, after the clock is turned on.
After the clock is turned on, the software must wait for the MMC_I_REG[END_CMD_RES]
interrupt, which indicates that the command and response sequence is finished and the response is
in the MMC_RES FIFO.
The software may then read the MMC_STAT register to verify the status of the transaction and then
read MMC_RES FIFO. If a response time-out occurred, the MMC_RES FIFO will not contain any
valid data.
15.4.5 Erase
An erase command is performed as described in Section 15.4.4 with the following additions: the
BUSY_BIT in the MMC_CMDAT register must be set to a 1 after it reads the MMC_RES FIFO.
Note: If a piece of data smaller than 32 bytes is written to the FIFO, the MMC_PRTBUF register must be
set.
3. Set MMC_I_MASK register to 0x1e and wait for MMC_I_REG[DATA_TRAN_DONE]
interrupt.
4. Set MMC_I_MASK to 0x1d.
5. Wait for MMC_I_REG[PRG_DONE] interrupt. This interrupt indicates that the card has
finished programming. Software may wait for MMC_I_REG[PRG_DONE] or start another
command sequence on a different card.
6. Read the MMC_STAT register to verify the status of the transaction (i.e. CRC error status).
To address a different card, the software sends a select command to that card by sending a basic no
data command and response transaction. To address the same card, the software must wait for
MMC_I_REG[PRG_DONE] interrupt. This ensures that the card is not in the busy state.
The multiple block write mode also requires a stop transmission command, CMD12, after the data
is transferred to the card. After the MMC_I_REG[DATA_TRAN_DONE] interrupt occurs, the
software must program the controller registers to send a stop data transmission command.
The multiple block read mode requires a stop transmission command, CMD12, after the data from
the card is received. After the MMC_I_REG[DATA_TRAN_DONE] interrupt has occurred, the
software must program the controller registers to send a stop data transmission command.
Note: When data less than 32 bytes is written to the FIFO, the MMC_PRTBUF[BUF_PART_FULL] bit
must be set.
3. Set MMC_I_MASK to 0x77 and wait for MMC_I_REG[STOP_CMD] interrupt.
4. Set the command registers for a stop transaction command (CMD12).
5. Wait for a response to the stop transaction command as described in Section 15.4.4.
6. Set MMC_I_MASK to 0x1e.
7. Wait for MMC_I_REG[DATA_TRAN_DONE] interrupt.
8. Set MMC_I_MASK to 0x1d.
9. Wait for MMC_I_REG[PRG_DONE] interrupt. This interrupt indicates that the card has
finished programming. Software may wait for MMC_I_REG[PRG_DONE] interrupt or start
another command sequence on a different card.
10. Read the MMC_STAT register to verify the status of the transaction (i.e. CRC error status).
To address a different card, the software must send a select command to that card by sending a
basic no data command and response transaction. To address the same card, the software must wait
for MMC_I_REG[PRG_DONE] interrupt. This ensures that the card is not in the busy state.
Table 15-5 through Table 15-23 describe the registers and FIFOs.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STRPCL
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 15-6. MMC_STAT Bit Definitions (Sheet 1 of 2)
Physical Address
MMC_STAT Register MultiMediaCard Controller
0x4110_0004
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI_READ_ERROR_TOKEN
TIME_OUT_RESPONSE
CRC_WRITE_ERROR
CRC_READ_ERROR
DATA_TRAN_DONE
XMIT_FIFO_EMPTY
RECV_FIFO_FULL
READ_TIME_OUT
END_CMD_RES
RES_CRC_ERR
PRG_DONE
reserved
CLK_EN
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
SPI_READ_ERROR_TOKEN
TIME_OUT_RESPONSE
CRC_WRITE_ERROR
CRC_READ_ERROR
DATA_TRAN_DONE
XMIT_FIFO_EMPTY
RECV_FIFO_FULL
READ_TIME_OUT
END_CMD_RES
RES_CRC_ERR
PRG_DONE
reserved
CLK_EN
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
The software can only write this register after the clock is turned off and the software has received
an interrupt that indicates the clock is turned off.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 15-7. MMC_CLK Bit Definitions
Physical Address
MMC_CLKRT Register MultiMediaCard Controller
0x4110_0008
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLK_RAT
reserved
E[2:0]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 15-8. MMC_SPI Bit Definitions (Sheet 1 of 2)
Physical Address
MMC_SPI Register MultiMediaCard Controller
0x4110_000c
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI_CS_ADDRESS
SPI_CS_EN
CRC_ON
SPI_EN
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPI_CS_ADDRESS
SPI_CS_EN
CRC_ON
SPI_EN
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 15-9. MMC_CMDAT Bit Definitions (Sheet 1 of 2)
Physical Address
MMC_CMDAT Register MultiMediaCard Controller
0x4110_0010
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESPONSE_FORMAT[1:0]
STREAM_BLOCK
MMC_DMA_EN
WRITE/READ
DATA_EN
BUSY
INIT
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
RESPONSE_FORMAT[1:0]
STREAM_BLOCK
MMC_DMA_EN
WRITE/READ
DATA_EN
BUSY
INIT
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 15-10. MMC_RESTO Bit Definitions
Physical Address
MMC_RESTO Register MultiMediaCard Controller
0x4110_0014
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RES_TO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 15-11. MMC_RDTO Register
Physical Address
MMC_RDTO Register MultiMediaCard Controller
0x4110_0018
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved READ_TO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 15-12. MMC_BLKLEN Bit Definitions
Physical Address
MMC_BLKLEN Register MultiMediaCard Controller
0x4110_001c
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved BLK_LEN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 15-13. MMC_NOB Bit Definitions
Physical Address
MMC_NOB Register MultiMediaCard Controller
0x4110_0020
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved MMC_NOB
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 15-14. MMC_PRTBUF Bit Definitions
Physical Address
MMC_PRTBUF Register MultiMediaCard Controller
0x4110_0024
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUF_PART_FULL
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 15-15. MMC_I_MASK Bit Definitions (Sheet 1 of 2)
Physical Address
MMC_I_MASK Register MultiMediaCard Controller
0x4110_0028
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA_TRAN_DONE
TXFIFO_WR_REQ
RXFIFO_RD_REQ
END_CMD_RES
CLK_IS_OFF
PRG_DONE
STOP_CMD
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
DATA_TRAN_DONE
TXFIFO_WR_REQ
RXFIFO_RD_REQ
END_CMD_RES
CLK_IS_OFF
PRG_DONE
STOP_CMD
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA_TRAN_DONE
TXFIFO_WR_REQ
RXFIFO_RD_REQ
END_CMD_RES
CLK_IS_OFF
PRG_DONE
STOP_CMD
reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 15-17. MMC_CMD Register
Physical Address
MMC_CMD Register MultiMediaCard Controller
0x4110_0030
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
reserved
reserved CMD_INDEX
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 15-19. MMC_ARGH Bit Definitions
Physical Address
MMC_ARGH Register MultiMediaCard Controller
0x4110_0034
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved ARG_H
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 15-20. MMC_ARGL Bit Definitions
Physical Address
MMC_ARGL Register MultiMediaCard Controller
0x4110_0038
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved ARG_L
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The first half-word read from the response FIFO is the most significant half-word of the received
response.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved RESPONSE_DATA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x x x x x x x x x
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved READ_DATA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x
Bits Name Description
31:8 — reserved
7:0 READ_DATA One byte of read data
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 15-23. MMC_TXFIFO, FIFO Entry
Physical Address
MMC_TXFIFO Entry MultiMediaCard Controller
0x4110_0044
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved WRITE_DATA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x
16.1 Overview
The NSSP is a synchronous serial interface that connects to a variety of external analog-to-digital
(A/D) converters, telecommunication CODECs, and many other devices that use serial protocols
for data transfer. The NSSP provides support for the following protocols:
• Texas Instruments (TI) Synchronous Serial Protocol*
• Motorola Serial Peripheral Interface* (SPI) protocol
• National Semiconductor Microwire*
• Programmable Serial Protocol (PSP)
The NSSP operates as full-duplex devices for the TI Synchronous Serial Protocol*, SPI*, and PSP
protocols and as half-duplex devices for the Microwire* protocol.
The FIFOs can be loaded or emptied by the CPU using programmed I/O or DMA burst transfers.
16.2 Features
• Supports the TI Synchronous Serial Protocol*, the Motorola SPI* protocol, National
Semiconductor Microwire*, and a Programmable Serial Protocol (PSP)
• Two independent transmit and receive FIFOs, each 16 samples deep by 32-bits wide
• Sample sizes from four to 32-bits
• Maximum bit rate of 13 Mbps in slave of clock mode, requires using DMA
• Master-mode and slave-mode operation
• Receive-without-transmit operation
NSSPSCLK is the serial bit clock used to control the timing of a transfer.
NSSPSCLK is generated internally (master mode) or is supplied
NSSPSCLK Input/Output
externally (slave mode) as indicated by SSCR1[SCLKDIR] as defined in
Table 16-4.
NSSPSFRM is the serial frame indicator that indicates the beginning and
the end of a serialized data word. SSPSFRM is generated internally
NSSPSFRM Input/Output
(master mode) or is supplied externally (slave mode) as indicated by
SSCR1[SFRMDIR] as defined in Table 16-4.
NSSPTXD is the transmit data (serial data out) serialized data line. It is
NSSPTXD Output available on two GPIO pins, GPIO[83] or GPIO[84]. See Section 4.1,
“General-Purpose I/O” for details.
NSSPRXD is the receive data (serial data in) serialized data line. It is
NSSPRXD Input available on two GPIO pins, GPIO[83] or GPIO[84]. See Section 4.1,
“General-Purpose I/O” for details.
The Network SSP can output either NSSPTXD and NSSPRXD on either GPIO[83] or GPIO[84].
This allows a system to dynamically change the direction of transfer for this port. The NSSP can
change direction if enabled, but it must be idle.
16.4 Operation
The SSP controller transfers serial data between the PXA255 processor and an external device
through FIFOs. The PXA255 processor CPU initiates the transfers using programmed I/O or DMA
bursts to and from memory. Separate transmit and receive FIFOs and serial data paths permit
simultaneous transfers in both directions to and from the external device, depending on the
protocols chosen.
Programmed I/O transfers data directly between the CPU and the SSP Data Register (SSDR).
DMA transfers data between memory and the SSP Data Register (SSDR). Data written to the SSP
Data Register (by either the CPU or DMA) is automatically transmitted by the transmit FIFO. Data
received by the receive FIFO is automatically sent to the SSP Data Register.
The FIFOs can also be accessed by DMA bursts (in multiples of one, two or four bytes) depending
upon the EDSS value. When SSCR0[EDSS] is set, DMA bursts must be in multiples of four bytes
(the DMA must have the SSP configured as a 32-bit peripheral).When SSCR0[EDSS] is cleared,
DMA bursts must be in multiples of one or two bytes (the DMA’s DCMD[WIDTH] register must
be at least the SSP data size programmed into the SSCR0[EDSS] and SSCR0[DSS]. If the DMA
DCMD[WIDTH] field is configured for 1 byte width, the DMA burst size must be 8 or 16.
For writes, the SSP takes the data from the transmit FIFO, serializes it, and sends it over the serial
wire (SSPTXD) to the external device. Receive data from the external device (on SSPRXD) is
converted to parallel words and stored in the receive FIFO.
When exceeded, a programmable trigger threshold generates an interrupt or DMA service request
that, if SSCR1[TIE] or SSCR1[TSRE] are enabled, signal the CPU or DMA, respectively, to refill
the transmit FIFO. Similarly, a programmable trigger threshold generates an interrupt or DMA
service request that, if SSCR1[RIE] or SSCR1[RSRE] are enabled, signal the CPU or DMA,
respectively, to empty the receive FIFO.
The receive and transmit FIFOs are differentiated by whether the access is a read or a write
transfer. Reads automatically target the receive FIFO, while writes write data to the transmit FIFO.
From a memory-map perspective, both reads and writes are at the same address. The FIFOs are 16
samples deep by one word wide.
16.4.2.1 Time-out
A time-out condition exists when the receive FIFO is idle for the period of time defined by the
Time-Out Register (SSTO). When a time-out occurs, the receiver time-out interrupt (SSSR[TINT])
is set. If the time-out interrupt is enabled (SSCR1[TINTE] set) a time-out interrupt occurs to signal
the processor that a time-out condition has occurred. The time-out timer is reset after receiving a
new sample or after the processor reads the receive FIFO. Once SSSR[TINT] is set it must be
cleared by writing a one to it. If the time-out interrupt is enabled, clearing SSCR1[TINTE] also
causes the time-out interrupt to be de-asserted.
• SSPSCLK–Defines the bit rate at which serial data is driven onto and sampled from the port.
• SSPSFRM–Defines the boundaries of a basic data unit, comprised of multiple serial bits.
• SSPTXD–The serial data path for transmitted data, from system to peripheral.
• SSPRXD–The serial data path for received data, from peripheral to system.
A data frame can contain from four to 32-bits, depending on the selected protocol. Serial data is
transmitted most significant bit first. Four protocols are supported: TI Synchronous Serial
Protocol*, SPI, Microwire*, and a PSP.
Microwire* uses a half-duplex, master-slave messaging protocol. At the start of a frame, the
controller transmits a one or two-byte control message to the peripheral; no data is sent by the
peripheral. The peripheral interprets the message and if the message is a read request, the
peripheral responds with the requested data, one clock after the last bit of the request message.
Return data—part of the same frame—can be from four to 16-bits in length. The total frame length
is 13 to 33 bits. The SSPSCLK is active during the entire frame.
Note: The serial clock (SSPSCLK), if driven by the SSP, toggles only while an active data transfer is
underway, unless receive-without-transmit mode is enabled by setting SSCR1[RWOT] and the
frame format is not Microwire*, in which case the SSPSCLK toggles regardless of whether
transmit data exist within the transmit FIFO. At other times, SSPSCLK holds in an inactive or idle
state as defined by the protocol.
Figure 16-1 shows the TI Synchronous Serial Protocol for when back-to-back frames are
transmitted. Figure 16-2 shows the TI Synchronous Serial Protocol for a single transmitted frame.
Once the transmit FIFO contains data, SSPSFRM is pulsed high for one SSPSCLK period and the
value to be transmitted is transferred from the transmit FIFO to the transmit logic serial shift
register. On the next rising edge of SSPSCLK, the most significant bit of the four to 32-bit data
frame is shifted to the SSPTXD pin. Likewise, the MSB of the received data is shifted onto the
SSPRXD pin by the off-chip serial slave device. Both the SSP and the off-chip serial slave device
then latch each data bit into the serial shifter on the falling edge of each SSPSCLK. The received
data is transferred from the serial shifter to the receive FIFO on the first rising edge of SSPSCLK
after the last bit has been latched.
For back-to-back transfers, the start of one frame is the completion of the previous frame. The
MSB of one transfer immediately follows the LSB of the preceding with no “dead” time between
them. When the SSP is a master to the frame sync (SSPSFRM) and a slave to the clock
(SSPSCLK), at least three extra clocks are needed at the beginning and end of each block of
transfers to synchronize internal control signals (a block of transfers is a group of back-to-back
continuous transfers).
Figure 16-1. Texas Instruments Synchronous Serial Frame* Protocol (multiple transfers)
SSPSCLK
SSPSFRM
SSPTX Bit[0] Bit[N] Bit[N-1] Bit[1] Bit[0] Bit[N] Bit[N-1] Bit[1] Bit[0]
SSPRX Bit[0] Bit[N] Bit[N-1] Bit[1] Bit[0] Bit[N] Bit[N-1] Bit[1] Bit[0]
A9650-01
Figure 16-2. Texas Instruments Synchronous Serial Frame* Protocol (single transfers)
SSPSCLK
SSPSFRM
A9518-02
When the SSP is disabled or in idle mode, SSPSCLK and SSPTXD are low and SSPSFRM is high.
When transmit data is available to send, SSPSFRM goes low (one clock period before the first
rising edge of SSPSCLK) and stays low for the remainder of the frame. The most significant bit of
the serial data is driven onto SSPTXD one half-cycle later. Halfway into the first bit period,
SSPSCLK asserts high and continues toggling for the remaining data bits. Data transitions on the
falling edge of SSPSCLK. Four to 32 bits can be transferred per frame.
With the assertion of SSPSFRM, receive data is simultaneously driven from the peripheral on
SSPRXD, MSB first. Data transitions on SSPSCLK falling edges and is sampled by the controller
on rising edges. At the end of the frame, SSPSFRM is de-asserted high one clock period (one half
clock cycle after the last falling edge of SSPSCLK) after the last bit latched at its destination and
the completed incoming word is shifted into the incoming FIFO. The peripheral can drive
SSPRXD to a high-impedance state after sending the last bit of the frame. SSPTXD retains the last
value transmitted when the controller goes into idle mode, unless the SSP is disabled or reset
(which forces SSPTXD low).
For back-to-back transfers, frames start and complete similar to single transfers, except SSPSFRM
does not de-assert between words. Both transmitter and receiver are configured for the word length
and internally track the start and end of frames. There are no dead bits; the least significant bit of
one frame is followed immediately by the most significant bit of the next.
When using the SPI protocol, the SSP can either be a master or a slave device. However, the clock
and frame direction must be the same. For example, the SSCR1[SCLKDIR] and
SSCR0[SFRMDIR] must both be set or both be cleared.
Figure 16-3 shows when back-to-back frames are transmitted for the Motorola SPI* frame
protocol. Figure 16-4 shows one of the four possible configurations for the Motorola SPI* frame
protocol for a single transmitted frame.
SSPSCLK
SSPSFRM
A9651-01
Note: When configured as either master or slave (to clock or frame) the SSP continues to drive SSPTXD
with the last bit of data sent (the LSB). If SSCR0[SSE] is cleared, SSPTXD goes low. The state of
SSPRXD is undefined before the MSB and after the LSB is transmitted. For minimum power
consumption, this pin must not float.
Note: The phase and polarity of SSPSCLK can be configured for four different modes. This example
shows just one of those modes (SSCR1[SPO] = 0, SSCR1[SPH] = 0).
Figure 16-4. Motorola SPI* Frame Protocol (single transfers)
SSPSCLK
SSPSFRM
A9519-02
Note: When configured as either master or slave (to clock or frame) the SSP continues to drive SSPTXD
with the last bit of data sent (the LSB). If SSCR0[SSE] is cleared, SSPTXD goes low. The state of
SSPRXD is undefined before the MSB and after the LSB is transmitted. For minimum power
consumption, this pin must not float.
When SPH is cleared, SSPSCLK remains in its inactive or idle state (as determined by
SSCR1[SPO]) for one full cycle after SSPSFRM is asserted low at the beginning of a frame.
SSPSCLK continues to transition for the rest of the frame. It is then held in its inactive state for
one-half of an SSPSCLK period before SSPSFRM is de-asserted high at the end of the frame.
When SPH is set, SSPSCLK remains in its inactive or idle state (as determined by SSCR1[SPO])
for one-half cycle after SSPSFRM is asserted low at the beginning of a frame. SSPSCLK continues
to transition for the remainder of the frame and is then held in its inactive state for one full
SSPSCLK period before SSPSFRM is de-asserted high at the end of the frame.
The combination of the SSCR1[SPO] and SSCR1[SPH] settings determine when SSPSCLK is
active during the assertion of SSPSFRM and which SSPSCLK edge transmits and receives data on
the SSPTXD and SSPRXD pins.
When programming SSCR1[SPO] and SSCR1[SPH] to the same value (both set or both cleared),
transmit data is driven on the falling edge of SSPSCLK and receive data is latched on the rising
edge of SSPSCLK. When programming SSCR1[SPO] and SSCR1[SPH] to opposite values (one
set and the other cleared), transmit data is driven on the rising edge of SSPSCLK and receive data
is latched on the falling edge of SSPSCLK.
Note: SSCR1[SPH] is ignored for all data frame formats except for the Motorola SPI* protocol.
Figure 16-6 shows the pin timing for all four programming combinations of SSCR1[SPO] and
SSCR1[SPH]. The SSCR1[SPO] inverts the polarity of the SSPSCLK signal and SSCR1[SPH]
determines the phase relationship between SSPSCLK and SSPSFRM, shifting the SSPSCLK
signal one-half phase to the left or right during the assertion of SSPSFRM.
Figure 16-5. Motorola SPI* Frame Protocols for SPO and SPH Programming (multiple
transfers)
SSPSCLK SPO=0
SSPSCLK
SPO=1
SSPSFRM
A9652-01
Note: When configured as either master or slave (to clock or frame) the SSP continues to drive SSPTXD
with the last bit of data sent (the LSB). If SSCR0[SSE] is cleared, SSPTXD goes low. The state of
SSPRXD is undefined before the MSB and after the LSB is transmitted. For minimum power
consumption, this pin must not float.
Figure 16-6. Motorola SPI* Frame Protocols for SPO and SPH Programming (single transfers)
SSPSCLK SPO=0
SSPSCLK
SPO=1
SSPSFRM
A9520-02
Note: When configured as either master or slave (to clock or frame) the SSP continues to drive SSPTXD
with the last bit of data sent (the LSB). If SSCR0[SSE] is cleared, SSPTXD goes low. The state of
SSPRXD is undefined before the MSB and after the LSB is transmitted. For minimum power
consumption, this pin must not float.
Each serial transmission begins with SSPSFRM asserting low, followed by an eight or 16-bit
command word sent from the controller to the peripheral on SSPTXD. The command word data
size is selected by the Microwire* transmit data size bit (SSCR1[MWDS]). SSPRXD is controlled
by the peripheral and remains in a high-impedance state. SSPSCLK asserts high midway into the
command’s most significant bit and continues toggling at the bit rate.
One bit-period after the last command bit, the peripheral returns the serial-data requested most
significant bit first on SSPRXD. Data transitions on the falling edge of SSPSCLK and is sampled
on the rising edge. The last falling edge of SSPSCLK coincides with the end of the last data bit on
SSPRXD and SSPSCLK remains low after that (if it is the only word or the last word of the
transfer). SSPSFRM de-asserts high one-half clock period later.
The start and end of a series of back-to-back transfers are like those of a single transfer; however,
SSPSFRM remains asserted (low) throughout the transfer. The end of a data word on SSPRXD is
followed immediately by the start of the next command byte on SSPTXD with no dead time.
When using the Microwire* protocol, the SSP can function only as a master (frame and clock are
outputs). Therefore, both SSCR1[SCLKDIR] and SSCR0[SFRMDIR] must both be cleared.
Figure 16-7 shows the National Semiconductor Microwire* frame protocol with eight-bit
command words when back-to-back frames are transmitted. Figure 16-8 shows the National
Semiconductor Microwire* frame protocol with eight-bit command words for a single transmitted
frame.
SSPSCLK
SSPSFRM
A9653-01
Note: When configured master the SSP continues to drive SSPTXD with the last bit of data sent (the
LSB) or it drives zero, depending on the status of SSPSP[ETDS]. If SSCR0[SSE] is cleared,
SSPTXD goes low. The state of SSPRXD is undefined before the MSB and after the LSB is
transmitted. For minimum power consumption, this pin must not float.
Figure 16-8. National Semiconductor Microwire* Frame Protocol (single transfers)
SSPSCLK
SSPSFRM
Bit[7] or
SSPTXD Bit[15] Bit[0] End of Transfer Data State
8 or 16-Bit Control
A9521-02
Note: When configured master the SSP continues to drive SSPTXD with the last bit of data sent (the
LSB) or it drives zero, depending on the status of SSPSP[ETDS]. If SSCR0[SSE] is cleared,
SSPTXD goes low. The state of SSPRXD is undefined before the MSB and after the LSB is
transmitted. For minimum power consumption, this pin must not float.
There are four possible serial clock sub-modes, depending on the SSPSCLK edges selected for
driving data and sampling received data and the selection of idle state of the clock.
For the PSP, the idle and disable modes of the SSPTXD, SSPSCLK, and SSPSFRM are
programmable via SSPSP[ETDS], SSPSP[SCMODE] and SSPSP[SFRMP]. When transmit data is
ready, the SSPSCLK remains in its idle state for the number of serial clock (SSPSCLK) clock
periods programmed within the start delay (SSPSP[STRTDLY]) field. SSPSCLK then starts
toggling, SSPTXD remains in the idle state for the number of cycles programmed within the
dummy start field (SSPSP[DMYSTRT]). The SSPSFRM signal asserts after the number of half-
clocks programmed in the field SSPSP[SFRMP]. The SSPSFRM remains asserted for the number
of half-clocks programmed within SSPSP[SFRMWDTH]. Four to 32-bits can be transferred per
frame. Once the LSB transfers, the SSPSCLK continues toggling based on the dummy stop field
(SSPSP[DMYSTOP]). SSPTXD either retains the last value transmitted or is forced to zero,
depending on the value programmed within the end of transfer data state field (SSPSP[ETDS]),
when the controller goes into idle mode, unless the SSP is disabled or reset (which forces SSPTXD
low). Refer to Table 16-2 for more information.
With the assertion of SSPSFRM, receive data is simultaneously driven from the peripheral on
SSPRXD, MSB first. Data transitions on SSPSCLK based on the serial clock mode selected and
are sampled by the controller on the opposite edge. When the SSP is a master to the frame sync
(SSPSFRM) and a slave to the clock (SSPSCLK), at least three extra clocks are needed at the
beginning and end of each block of transfers to synchronize internal control signals (a block of
transfers is a group of back-to-back continuous transfers).
Figure 16-9. Programmable Serial Protocol (multiple transfers)
SSPSCLK
(when SCMODE = 0)
SSPSCLK
(when SCMODE = 1)
SSPSCLK
(when SCMODE = 2)
SSPSCLK
(when SCMODE = 3) End of
Transfer
Data State
Undefined MSB LSB End of Transfer MSB LSB
SSPTXD Data State
T1 T2 T3 T4 T1 T2 T3
SSPSFRM
(when SFRMP = 1)
T5 T6 T5 T6
SSPSFRM
(when SFRMP = 0)
A9523-02
SSPSCLK
(when SCMODE = 0)
SSPSCLK
(when SCMODE = 1)
SSPSCLK
(when SCMODE = 2)
SSPSCLK
(when SCMODE = 3)
T1 T2 T3 T4
SSPSFRM
(when SFRMP = 1)
T5 T6
SSPSFRM
(when SFRMP = 0)
A9522-02
Note: The SSPSFRM delay must not extend beyond the end of T4. SSPSFRM Width must be asserted for
at least 1 SSPSCLK, and must be deasserted before the end of the T4 cycle (i.e. in terms of time,
not bit values, (T5 + T6) <= (T1 + T2 + T3 + T4), 1<= T6 < (T2 + T3 + T4), and (T5 + T6) >= (T1
+ 1) to ensure that SSPSFRM is asserted for at least 2 edges of the SSPSCLK). While the PSP can
be programmed to generate the assertion of SSPSFRM during the middle of the data transfer (after
the MSB was sent), the SSP is not able to receive data in frame slave mode (SSCR1[SFRMDIR] is
set) if the assertion of frame is not before the MSB is sent (For example, T5 <= T2 if
SSCR1[SFRMDIR] is set). Transmit Data transitions from the “End of Transfer Data State” to the
next MSB value upon the assertion of frame. The start delay field should be programmed to 0
whenever SSPSCLK or SSPSFRM is configured as an input.
SSCR1[TTE] enables Hi-Z on SSPTXD. SSCR1[TTELP] controls when SSPTXD is placed into
Hi-Z.
If SSCR1[TTE] is 1 and SSCR1[TTELP] is 0, SSPTXD is driven with the MSB at the first rising
edge of SSPSCLK after SSPSFRM is asserted. SSPTXD is Hi-Z after the falling edge of SSPSCLK
for the LSB (1 clock edge after the clock edge that starts the LSB). Figure 16-11shows the pin
timing for this mode.
Figure 16-11. TI SSP with SSCR[TTE]=1 and SSCR[TTELP]=0
SSPSCLK
SSPSFRM
A9974-01
If SSCR1[TTE] is 1 and SSCR1[TTELP] is 1, SSPTXD is driven with the MSB at the first rising
edge of SSPSCLK after SSPSFRM is asserted. SSPTXD is Hi-Z at the next rising edge of
SSPSCLK after the LSB (2 clock edges after the clock edge that starts the LSB). Figure 16-12
shows the pin timing for this mode.
SSPSCLK
SSPSFRM
A9975-01
Note: If SSPSCLK is an input, the device driving SSPSCLK must provide another clock edge to cause
the TXD line to go to Hi-Z.
SSPSCLK
SSPSFRM
A9976-01
If SSCR1[TTE] is 1, SSPTXD is driven at the same clock edge that the MSB is driven. SSPTXD is
Hi-Z after the next rising edge of SSPSCLK for the LSB (1 clock edge after the clock edge that
starts the LSB). Figure 16-14 shows the pin timing for this mode.
SSPSCLK
SSPSFRM
Bit[7] or
SSPTXD Bit[15] Bit[0]
8 or 16-Bit Control
A9977-01
If SSCR1[TTE] is 1 and SSCR1[TTELP] is 0, SSPTXD is driven at the same clock edge that the
MSB is driven. If the SSP is a slave to frame SSPTXD is Hi-Z on the clock edge after the edge that
starts the LSB. Figure 16-15 shows the pin timing for this mode.
Figure 16-15. PSP mode with SSCR1[TTE]=1 and SSCR1[TTELP]=0 (slave to frame)
SSPSCLK
(when SCMODE = 0)
SSPSCLK
(when SCMODE = 1)
SSPSCLK
(when SCMODE = 2)
SSPSCLK
(when SCMODE = 3)
T1 T2 T3 T4
SSPSFRM
(when SFRMP = 1)
T5 T6
SSPSFRM
(when SFRMP = 0)
A9978-01
If the SSP is a master to frame, SSPTXD is Hi-Z two clock edges after the clock edge that drives
the LSB. This occurs even if the SSP is a master of clock and this clock edge does not appear on
the SSPSCLK. Figure 16-16 shows the pin timing for this mode.
Figure 16-16. PSP mode with SSCR1[TTE]=1 and SSCR1[TTELP]=0 (master to frame)
SSPSCLK
(when SCMODE = 0)
SSPSCLK
(when SCMODE = 1)
SSPSCLK
(when SCMODE = 2)
SSPSCLK
(when SCMODE = 3)
T1 T2 T3 T4
SSPSFRM
(when SFRMP = 1)
T5 T6
SSPSFRM
(when SFRMP = 0)
A9979-01
SSCR1[TTELP] can only be set to 1 in PSP mode if the SSP is a slave to frame. If SSCR1[TTE] is
1 and SSCR1[TTELP] is 1 and the SSP is a slave to frame, SSPTXD is driven at the same clock
edge that the MSB is driven. SSPTXD is Hi-Z two clock edges after the clock edge that starts the
LSB. This occurs even if the SSP is a master of clock and this clock edge does not appear on the
SSPSCLK. If the SSP is a slave of clock, then the device driving SSPSCLK must provide another
clock edge. Figure 16-17 shows the pin timing for this mode.
Figure 16-17. PSP mode with SSCR1[TTE]=1 and SSCR1[TTELP]=1 (must be slave to frame)
SSPSCLK
(when SCMODE = 0)
SSPSCLK
(when SCMODE = 1)
SSPSCLK
(when SCMODE = 2)
SSPSCLK
(when SCMODE = 3)
T1 T2 T3 T4
SSPSFRM
(when SFRMP = 1)
T5 T6
SSPSFRM
(when SFRMP = 0)
A9980-01
Reading the SSP Status Register (see Section 16.5.3) shows whether the FIFO is full, empty or
how many samples it contains.
This generates baud rates up to a maximum of 3.68 Mbits per second. When driven by an external
clock, SSPSCLK can be driven up to 13 MHz, generating baud rates up to 13 Mbits per second. At
these fast baud rates, using polled/interrupt mode is insufficient to keep the FIFO filled. You must
use DMA mode.
Note: Write the SSP registers after a reset but before the SSP is enabled.
• The SSP Time-Out (SSTO) register programs the time-out value used to signal a specified
period of receive FIFO inactivity.
• While in PSP mode, the SSP Programmable Serial Protocol (SSPSP) register programs the
parameters used in defining the data transfer.
• The data register is mapped as one 32-bit location, which physically points to either of two 32-
bit registers: one register is for writes of data transfers to the transmit FIFO and the other
register is for reads that take data from the receive FIFO. A write cycle or burst write puts
successive words into the SSP write register and then into the transmit FIFO. A read cycle or
burst read takes data from the SSP read register and the receive FIFO reloads it with available
data bits it has stored.
Do not increment the address using read and write DMA bursts.
• Besides showing the state of the FIFO buffers, the status register shows whether the
programmable trigger threshold has been passed and whether a transmit or receive FIFO
service request is active. The status register also shows how full the FIFO is. Flag bits indicate
when the SSP is actively transmitting data, when the transmit FIFO is not full, and when the
receive FIFO is not empty. The SSSR[ROR] bit signals an overrun of the receive FIFO In this
case newly received data is discarded.
When programming registers, reserved bits must be written as zeroes and read as undefined.
These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
EDSS
SCR
DSS
SSE
FRF
reserved
? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? 0 0 0 0 0 0
NOTE: Software must not change SCR when the SSPSCLK is enabled because doing so
causes the SSPSCLK frequency to immediately change.
Serial bit rate = SSP Clock / (SCR + 1)
SYNCHRONOUS SERIAL PORT ENABLE/DISABLE:
Enables and disables all SSP operations. When the port is disabled, all of its clocks can be
stopped by programmers to minimize power consumption.
When cleared during active operation, the SSP is disabled immediately, terminating the current
frame being transmitted or received. Clearing SSE resets the port FIFOs and the status bits;
however, the SSP control registers are not reset.
7 SSE
NOTE: After reset or after clearing the SSE, software must ensure that the SSCR1, SSITR,
SSTO, and SSPSP control registers are properly re-configured and that the SSSR
register is reset before re-enabling the SSP by setting SSE. Also, SSE must be cleared
before re-configuring the SSCR0, SSCR1, or SSPSP registers; any or all control bits in
SSCR0 can be written at the same time as the SSE.
0 – SSP operation disabled
1 – SSP operation enabled
6 — reserved
FRAME FORMAT:
SELECTS which frame format to use.
0b00 – Serial Peripheral Interface*
5:4 FRF
0b01 – TI Synchronous Serial Protocol*
0b10 – Microwire*
0b11 – Programmable Serial Protocol
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
EDSS
SCR
DSS
SSE
FRF
reserved
? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? 0 0 0 0 0 0
These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits.
SFRMDIR
SCLKDIR
reserved
reserved
reserved
TTELP
MWDS
EBCEI
RWOT
EFWR
TINTE
RSRE
SCFR
TSRE
STRF
LBM
SPO
SPH
TTE
RIE
TIE
RFT TFT
Reset 0 0 0 0 ? ? 0 0 0 0 0 0 0 ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SFRMDIR
SCLKDIR
reserved
reserved
reserved
TTELP
MWDS
EBCEI
RWOT
EFWR
TINTE
RSRE
SCFR
TSRE
STRF
LBM
SPO
SPH
TTE
RIE
TIE
RFT TFT
Reset 0 0 0 0 ? ? 0 0 0 0 0 0 0 ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits.
DMYSTOP
DMYSTRT
STRTDLY
SCMODE
reserved
SFRMP
ETDS
reserved SFRMWDTH SFRMDLY
Reset ? ? ? ? ? ? ? 0 0 ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMYSTOP
DMYSTRT
STRTDLY
SCMODE
reserved
SFRMP
ETDS
reserved SFRMWDTH SFRMDLY
Reset ? ? ? ? ? ? ? 0 0 ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This is a read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 16-6. SSTO Bit Definitions
0X4140_0028 SSTO Network SSP Serial Port
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved TIMEOUT
Reset ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Setting bits in this register causes the SSP controller to generate interrupts and DMA requests if
enabled. This is useful in testing the port’s functionality.
Setting any of these bits also causes the corresponding status bit(s) to be set in the SSP Status
Register (SSSR). The interrupt or service request caused by the setting of one of these bits remains
active until the bit is cleared.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TROR
TRFS
TTFS
reserved reserved
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 ? ? ? ? ?
31:8 — — reserved
TEST RECEIVE FIFO OVERRUN:
0 – No receive FIFO overrun service request is generated.
7 R/W TROR
1 – Generates a non-maskable Interrupt to the CPU. No DMA request
is generated.
TEST RECEIVE FIFO SERVICE REQUEST:
0 – No receive FIFO service request is generated.
6 R/W TRFS
1 – Generates a non-maskable Interrupt to the CPU and a DMA
request for the receive FIFO.
TEST TRANSMIT FIFO SERVICE REQUEST:
0 – No transmit FIFO service request is generated.
5 R/W TTFS
1 – Generates a non-maskable Interrupt to the CPU and a DMA
request for the transmit FIFO.
4:0 — — reserved
Bits that cause an interrupt signal the request as long as the bit is set. The interrupt clears when the
bits clear. Read and write bits are called status bits (status bits are referred to as sticky and once set
by hardware, they must be cleared by software); Read-only bits are called flags. Writing a 1 to a
status bit clears it; writing a 0 has no effect. Read-only flags are set and cleared by hardware; writes
have no effect. The reset state of read-write bits is zero and all bits return to their reset state when
SSCR0[SSE] is cleared. Additionally, some bits that cause interrupts have corresponding mask bits
in the control registers and are indicated in the section headings that follow.
Set the desired values for this register before enabling the SSP (via SSCR0[SSE]).
These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 16-8. SSSR Bit Definitions (Sheet 1 of 3)
0x4140_0008 SSSR Network SSP Serial Port
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12
reserved 11 10 9 8 7 6 5 4 3 2 1 0
reserved
reserved
TINT
ROR
BCE
RNE
TUR
CSS
BSY
RFS
RFL
TNF
TFS
TFL
reserved
Reset ? ? ? ? ? ? ? ? 0 0 0 ? 0 ? ? ? 1 1 1 1 0 0 0 0 0 0 0 0 0 1 ? ?
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
reserved
reserved
ROR
TINT
BCE
RNE
CSS
BSY
TUR
RFS
RFL
TNF
TFS
TFL
reserved
Reset ? ? ? ? ? ? ? ? 0 0 0 ? 0 ? ? ? 1 1 1 1 0 0 0 0 0 0 0 0 0 1 ? ?
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
reserved
reserved
ROR
TINT
BCE
RNE
CSS
BSY
TUR
RFS
RFL
TNF
TFS
TFL
reserved
Reset ? ? ? ? ? ? ? ? 0 0 0 ? 0 ? ? ? 1 1 1 1 0 0 0 0 0 0 0 0 0 1 ? ?
As the system accesses the register, FIFO control logic transfers data automatically between the
registers and FIFOs as fast as the system moves it. Unless attempting a write to a full transmit
FIFO, data in the FIFO shifts up or down to accommodate the new word(s). Status bits show users
whether the FIFO is full, above the programmable trigger threshold, below the programmable
trigger threshold or empty.
For transmit data transfers, the register can be written by the system processor anytime it falls
below its trigger threshold when using programmed I/O.
When a data size of less than 32-bits is selected, do not left-justify data written to the transmit
FIFO. Transmit logic left-justifies the data and ignores any unused bits. Received data of less than
32-bits is automatically right-justified in the receive FIFO.
When the SSP is programmed for the Microwire* protocol and the size of the Transmit data is eight
bits (SSCR1[MWDS] cleared), the most significant bits are ignored. Similarly, if the size for the
Transmit data is 16 bits (SSCR1[MWDS] set), the most significant 16 bits are ignored.
SSCR0[DSS] controls the Receive data size.
Both FIFOs are cleared when the port is reset, or by clearing SSCR0[SSE].
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 16-9. SSDR Bit Definitions
0x4140_0010 SSDR Network SSP Serial Port
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
The HWUART interface pins are available via either the PCMCIA general purpose I/O (GPIO)
pins or the BTUART pins. Refer to Section 4.1.2, “GPIO Alternate Functions” for more
information. When using the HWUART through the PCMCIA pins, they are driven at the same
voltage level as the memory interface. Because the PCMCIA signal nPWE is used for variable-
latency input / output (VLIO), VLIO cannot be used while the HWUART interface is using the
PCMCIA pins.
The HWUART is configured differently than the other UARTs. The HWUART supports full
hardware flow control.
17.1 Overview
The HWUART contains a UART and a slow infrared transmit encoder and receive decoder that
conforms to the IrDA Serial Infrared (SIR) Physical Layer Link Specification.
The UART performs serial-to-parallel conversion on data characters received from a peripheral
device or a modem and parallel-to-serial conversion on data characters received from the
processor. The processor can read the UART’s complete status during functional operation. Status
information includes the type and condition of transfer operations and error conditions (parity,
overrun, framing, or break interrupt) associated with the UART.
The HWUART operates in FIFO or non-FIFO mode. In FIFO mode, a 64-byte transmit FIFO holds
data from the processor until it is transmitted on the serial link and a 64-byte receive FIFO buffers
data from the serial link until it is read by the processor. In non-FIFO mode, the transmit and
receive FIFOs are bypassed.
The HWUART can also use direct memory access (DMA) to transfer data to and from the
HWUART.
17.2 Features
Software can program interrupts to meet its requirements. This minimizes the number of
computations required to handle the communications link. The UART operates in an environment
that is controlled by software and can be polled or is interrupt driven. The HWUART has these
features:
• Functionally compatible with the 16550A and 16750 UART specifications. The UART
supports not only the 16550A and 16750 industry standards but these additional functions as
well:
— DMA requests for transmit and receive data services
— Slow infrared asynchronous interface
SERIAL INPUT – Serial data input to the receive shift register. In infrared mode, it is connected to the infrared
RXD Input
receiver input.
SERIAL OUTPUT – Serial data output to the communications link-peripheral, modem, or data set. The TXD
TXD Output signal is set to the logic 1 state upon a Reset operation. It is connected to the output of the infrared transmitter in
infrared mode.
CLEAR TO SEND – When low, indicates that the modem or data set is ready to exchange data.
Non-Autoflow Mode: When not in autoflow mode, bit 4 (CTS) of the Modem Status register (MSR) indicates the
state of nCTS. Bit 4 is the complement of the nCTS signal. Bit 0 (DCTS) of the Modem Status register indicates
whether the nCTS input has changed state since the previous reading of the Modem Status register. When the
CTS bit of the MSR changes state and the modem status interrupt is enabled, an interrupt is generated. nCTS
has no effect on the transmitter. The user can program the UART to interrupt the processor when DCTS changes
state. The programmer can then stall the outgoing data stream by starving the transmit FIFO or disabling the
nCTS Input UART with the Interrupt Enable register (IER).
NOTE: If UART transmission is stalled by disabling the UART, the user will not receive an MSR interrupt when
nCTS reasserts. This is because disabling the UART also disables interrupts. To get around this, either
use Auto CTS in Autoflow Mode, or program the nCTS GPIO pin to interrupt.
Autoflow Mode: In autoflow mode, the UART transmit circuity checks the state of nCTS before transmitting each
byte. If nCTS is high, no data is transmitted.
REQUEST TO SEND – When low, signals the modem or the data set that the UART is ready to exchange data.
Non-Autoflow Mode: The nRTS output signal can be asserted by setting bit 1 (RTS) of the Modem Control
register to 1. The RTS bit is the complement of the nRTS signal.
nRTS Output
Autoflow Mode: nRTS is automatically asserted by the autoflow circuitry when the receive buffer exceeds its
programmed trigger threshold. It is deasserted when enough bytes are removed from the buffer to lower the data
level back to the trigger threshold.
17.4 Operation
The format of a UART data frame is shown in Figure 17-1.
Figure 17-1. Example UART Data Frame
Start Data Data Data Data Data Data Data Data Parity Stop Stop
Bit <0> <1> <2> <3> <4> <5> <6> <7> Bit Bit 1 Bit 2
TXD or RXD pin
LSB MSB
Receive data sample counter frequency is 16 times the value of the bit frequency. The 16X clock is
created by the baud rate generator. Each bit is sampled three times in the middle. Shaded bits in
Figure 17-1 are optional and can be programmed by software.
Each data frame is between seven and 12 bits long, depending on the size of the data programmed,
whether parity is enabled, and the number of stop bits. A data frame begins by transmitting a start
bit that is represented by a high to low transition. The start bit is followed by data that is five to
eight bits wide and begins with the least significant bit (LSB). The data bits are followed by an
optional parity bit. The parity bit is set if even parity is enabled and the data byte has an odd
number of ones or if odd parity is enabled and the data byte has an even number of ones. The data
frame ends with one, one and a half, or two stop bits, as programmed by software. The stop bits are
represented by one, one and a half, or two successive bit periods of a logic one.
The UART has two FIFOs: one transmit and one receive. The transmit FIFO is 64 bytes deep and
eight bits wide. The receive FIFO is 64 bytes deep and 11 bits wide. Three bits are used for tracking
errors.
The UART can use NRZ coding to represent individual bit values. NRZ coding is enabled when
Interrupt Enable register (IER) bit 5 (IER[5]) is set to high. A one is represented by a line transition
and a zero is represented by no line transition. Figure 17-2 shows the data byte 0b 0100 1011 in
NRZ coding. The LSB is transmitted first.
Figure 17-2. Example NRZ Bit Encoding – (0b0100 1011
LSB MSB
Bit 1 1 0 1 0 0 1 0
Value
Digital
Data
NRZ
Data
17.4.1 Reset
The UART is disabled on reset. To enable the UART, use software to program the GPIO registers
then set IER[UUE]. When the UART is enabled, the receiver waits for a frame start bit and the
transmitter sends data if it is available in the Transmit Holding register. Transmit data can be
written to the Transmit Holding register before the UART is enabled. In FIFO mode, data is
transmitted from the FIFO to the Transmit Holding register before it goes to the pin.
When the UART unit is disabled, the transmitter or receiver finishes the current byte and stops
transmitting or receiving data. When the UART is enabled, data in the FIFO is not cleared and
transmission resumes.
For a receive interrupt to occur, the receive FIFO and receive interrupts must be enabled. The
Interrupt Identification register (IIR) bits 1 and 2 (IIR[IID]) change to show that receive data is
available when the FIFO reaches its trigger threshold. IIR[IID] changes to show the next waiting
interrupt when the FIFO drops below the trigger threshold. A change in IIR[IID] triggers an
interrupt to the core. Software reads IIR[IID] to determine the cause of the interrupt.
The receiver line status interrupt (IIR = 0xC6) has the highest priority and the received data
available interrupt (IIR = 0xC4) is lower. The line status interrupt occurs only when the character at
the front of the FIFO has errors.
The data ready bit (DR in the Line Status register) is set when a character is transferred from the
shift register to the receive FIFO. The DR bit is cleared when the FIFO is empty.
A character timeout interrupt occurs when the receive FIFO and receive timeout interrupt are
enabled and these conditions exist:
• At least one character is in the FIFO.
• The most recently received character was received more than four continuous character times
ago. If two stop bits are programmed, the second is included in this interval.
• The most recent FIFO read was performed more than four continuous character times ago.
After the processor reads one character from the receive FIFO or a new start bit is received, the
timeout interrupt is cleared and the timeout is reset. If a timeout interrupt has not occurred, the
timeout is reset when a new character is received or the processor reads the receive FIFO.
Transmit interrupts can only occur when the transmit FIFO and transmit interrupt are enabled. The
transmit data request interrupt occurs when the transmit FIFO is at least half empty. The interrupt is
cleared when the Transmit Holding register (THR) is written or the IIR is read.
The processor can also check the transmitter empty (LSR[TEMT]) bit, which is set when the
transmit FIFO and Transmit Holding register are empty.
Note: When DMA requests are enabled and an interrupt occurs, software must first read the LSR to
verify an error interrupt exists, then check the IIR for the source of the interrupt. If an interrupt
occurs and LSR[FIFOE] is clear, software must read the ISR to determine the error condition.
When the last error byte is read from the FIFO, DMA requests are automatically enabled. Software
is not required to check for the error interrupt if DMA requests are disabled. Error interrupts only
occur when DMA requests are enabled.
If an error occurs when the receive FIFO trigger threshold has been reached, such that a receive
DMA request is set, users need to wait for the DMA to finish the transfer before reading out the
error bytes through programmed I/O. If not, FIFO underflow could occur.
Note: Ensure that the DMA controller has completed the previous receive DMA requests before the error
interrupt handler begins to clear the errors from the FIFO. If not, FIFO underflow could occur.
Autoflow mode can be used in two ways: full autoflow, automating both nCTS and nRTS; and half
autoflow, automating only nCTS. Full autoflow is enabled by setting MCR[AFE] and MCR[RTS]
to 1. Auto-nCTS-only mode is enabled by setting MCR[AFE] and clearing MCR[RTS].
When in full autoflow mode, nRTS is asserted when the UART FIFO is ready to receive data from
the remote transmitter. This occurs when the amount of data in the receive FIFO is below the
programmable trigger threshold value. When the amount of data in the receive FIFO reaches the
programmable trigger threshold, nRTS is deasserted. It is asserted once again when enough bytes
are removed from the FIFO to lower the data level below the trigger threshold.
When in full or half-autoflow mode, nCTS is asserted by the remote receiver when the receiver is
ready to receive data from the UART. The UART checks nCTS before sending the next byte of data
and will not transmit the byte until nCTS is low. If nCTS goes high while the transfer of a byte is in
progress, the transmitter sends the byte.
Note: Autoflow mode can be used only in conjunction with FIFO mode.
If the UART is to program the Divisor Latch registers, you can choose one of two methods for
auto-baud calculation: table-based and formula-based. Set Auto-Baud Control register (ABR), bit 3
(ABR[ABT]) to select which method you want to use (refer to Section 17.5.8). When the formula
method is used, any baud rate defined by the parameters in Section 17.5.3 can be programmed by
the UART. The formula method works well for higher baud rates, but could possibly fail below
28.8 kbps if the remote transmitter’s actual baud rate differs by more than one percent of its target.
The table method is more immune to such errors as the table rejects uncommon baud rates and
rounds to the common ones. The table method allows any baud rate defined by the formula in
Section 17.5.3 above 28.8 kbps. Below 28.8 kbps the only baud rates which can be programmed by
the UART are 19200, 14400, 9600, 4800, 1200, and 300 baud.
When the baud rate is detected, the auto-baud circuitry disables itself by clearing ABR, bit 0
(ABR[ABE]). If users want to re-enable auto-baud detection, ABR[ABE] must be set.
Note: Auto-baud rate detection is not supported with IrDA (slow infrared) mode.
The SIR interface does not contain the actual IR LED driver or the receiver amplifier. The I/O pins
attached to the SIR only have digital CMOS level signals. The SIR supports two-way
communication, but full duplex communication is not possible because reflections from the
transmit LED enter the receiver. The SIR interface supports frequencies up to 115.2 Kbps. Because
the input clock is 14.7456 MHz, the baud divisor must be eight or more.
17.4.5.1 Operation
The SIR modulation technique works with 5-, 6-, 7-, or 8-bit characters with an optional parity bit.
The data is preceded by a zero value start bit and ends with one or more stop bits. The encoding
scheme is to set a pulse 3/16 of a bit wide in the middle of every zero bit and send no pulses for bits
that are ones. The pulse for each zero bit must occur, even for consecutive bits with no edge
between them.
START
UART TRANSMIT
BIT 1 0 0 0 1 0 1 0 STOP
SHIFT VALUE
BIT
IR ENCODER OUTPUT
(TXD PIN VALUE)
IR DECODER OUTPUT
START
UART RECEIVE 1 0 0 0 1 1 0 STOP
BIT 0
SHIFT VALUE BIT
The top line in Figure 17-3 shows an asynchronous transmission as it is sent from the UART. The
second line shows the pulses generated by the IR encoder at the TXD pin. A pulse is generated in
the middle of the START bit and any data bit that is a zero. The third line shows the values received
at the RXD input pin. The fourth line shows the receive decoder’s output. The receive decoder
drives the receiver data line low when it detects a pulse. The bottom line shows how the UART’s
receiver interprets the decoder’s action. This last line is the same as the first, but it is shifted half a
bit period.
When XMODE is cleared, each zero bit has a pulse width of 3/16 of a bit time. When XMODE is
set, a pulse of 1.6 µs is generated in the middle of each zero bit. The shorter infrared pulse
generated when XMODE is set reduces the LED’s power consumption. At 2400 bps, the LED is
normally on for 78 µs for each zero bit that is transmitted. When XMODE is set, the LED is on
only 1.6 µs (as show in Figure 17-4).
Figure 17-4. XMODE Example.
1 7 11 16
16X Baud Clock
To prevent transmitter LED reflection feed back to the receiver, disable the IR receiver decoder
when the IR transmit encoder transmits data and disables the IR transmit encoder when the IR
receiver decoder receives data. The RCVEIR and XMITIR bits in the Infrared Selection Register
(ISR) must not be set at the same time (refer to Section 17.5.15).
In FIFO mode, the RBR latches the value of the data byte at the front of the FIFO (see Table 17-2).
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved Byte 0
Bits Name Description
31:8 — reserved
7:0 Byte 0 Byte 0
In FIFO mode, a write to the THR puts data into the end of the FIFO. The data at the front of the
FIFO is loaded to the TSR when that register is empty.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved Byte 0
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0
Load these divisor latches during initialization to ensure that the baud rate generator operates
properly. If each divisor latch is loaded with a 0, the 16X clock stops. The divisor latches are
accessed with a word write.
The baud rate of the data shifted in to or out of a UART is given by the formula:
14.7456 MHz
BaudRate = ----------------------------------
( 16xDivisor )
For example, if the divisor is 24, the baud rate is 38400 bps.
Table 17-4 and Table 17-5 describe the DLL and DLH registers.
These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 17-4. DLL Bit Definitions
Physical Address
Divisor Latch Register Low (DLL) PXA255 Processor Hardware UART
0x4160_0000 (DLAB=1)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DLL
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 1 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved DLH
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0
The character timeout indication interrupt is separated from the received data available interrupt to
ensure that the processor and the DMA controller do not service the receive FIFO at the same time.
When a character timeout indication interrupt occurs, the processor must handle the data in the
receive FIFO through programmed I/O.
Enabling DMA requests also enables a separate error interrupt. For additional information see
Section 17.4.2.5.
Set bit 7 of the IER to enable DMA requests. The IER also contains the unit enable and NRZ
coding enable control bits. Bits 7 through 4 are used differently from the standard 16550A register
definition.
Note: MCR[OUT2] is a global interrupt enable, and must be set to enable UART interrupts.
Note: To ensure that the DMA controller and programmed I/O do not access the same FIFO, software
must not set DMAE (bit 7) while TIE (bit 1) or RAVIE (bit 0) are set to 1.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 17-6. IER Bit Definitions
Physical Address
Interrupt Enable Register (IER) PXA255 Processor Hardware UART
0x4160_0004
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTOIE
RAVIE
DMAE
NRZE
RLSE
UUE
MIE
TIE
reserved
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0
If additional data is received before a receiver time out interrupt is serviced, the interrupt is
deasserted.
Read IIR to determine the type and source of UART interrupts. To be 16550 compatible, the lower
4 bits of the IIR are priority encoded, shown in Table 17-9. If two or more interrupts represented by
these bits occur, only the interrupt with the highest priority is displayed. The autobaud lock
interrupt is not priority encoded. It asserts/deasserts independently of the lower 4 bits.
IIR[nIP] indicates the existence of an interrupt in the lower four bits of the IIR. A low signal on this
bit indicates an encoded interrupt is pending. If this bit is high, no encoded interrupt is pending,
regardless of the state of the other 3 bits. nIP has no effect or association with IIR[ABL], which
asserts/deasserts independently of nIP.
1 (highest) Receiver line status – One or more error bits were set.
Received data is available. In FIFO mode, trigger threshold was reached. In non-FIFO mode,
2
RBR has data.
Receiver timeout occurred. Occurs only in FIFO mode, when data is in the receive FIFO but no
2
data has been sent for a set time period.
Transmitter requests data. In FIFO mode, the transmit FIFO is at least half empty. In non-FIFO
3
mode, the THR has been transmitted.
4 (lowest) Modem status – One or more modem input signal has changed state.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
FIFOES
TOD
ABL
nIP
IID
reserved
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 ? 0 0 0 0 1
reserved
FIFOES
TOD
ABL
nIP
IID
reserved
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 ? 0 0 0 0 1
Table 17-9 shows the priority, type, and source of the Interrupt Identification register interrupts. It
also gives the reset condition used to deassert the interrupts. Bits (0-3) of the IIR register represent
priority encoded interrupts. Bits (4-7) do not.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESETRF
RESETTF
TRFIFOE
reserved
ITL
TIL
reserved
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 ? ? 0 0 0 0
RESETRF
RESETTF
TRFIFOE
reserved
ITL
TIL
reserved
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 ? ? 0 0 0 0
Bits Name Description
Reset Receiver FIFO – When RESETRF is set to 1, all the bytes in the receiver FIFO are
cleared. The DR bit in the LSR is reset to 0. All the error bits in the FIFO and the FIFOE bit
in the LSR are cleared. Any error bits, OE, PE, FE or BI, that had been set in LSR are still
1 RESETRF set. The receiver shift register is not cleared. If the IIR had been set to received data
available, it is cleared.
0 = Writing 0 has no effect
1 = The receiver FIFO is cleared
Transmit and Receive FIFO Enable – TRFIFOE enables/disables the transmitter and
receiver FIFOs. When TRFIFOE = 1, both FIFOs are enabled (FIFO Mode). When
TRFIFOE = 0, the FIFOs are both disabled (non-FIFO Mode). Writing a 0 to this bit clears
all bytes in both FIFOs. When changing from FIFO mode to non-FIFO mode and vice versa,
0 TRFIFOE data is automatically cleared from the FIFOs. This bit must be 1 when other bits in this
register are written or the other bits are not programmed.
0 = FIFOs are disabled
1 = FIFOs are enabled
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 17-11. FOR Bit Definitions
Physical Address
FIFO Occupancy Register (FOR) PXA255 Processor Hardware UART
0x4160_0024
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0
The auto-baud circuitry counts the number of clocks in the start bit and writes this count into the
Auto-Baud Count register (ACR – refer to Section 17.5.9). It then interrupts the processor if
ABR[ABLIE] is set. It also automatically programs the Divisor Latch registers (DLL and DLH –
refer to Section 17.5.3) if ABR[ABUP] bit is set.
Note: Auto-baud rate detection is not supported with slow infrared Mode.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 17-12. ABR Bit Definitions
Physical Address
Autobaud Control Register (ABR) PXA255 Processor Hardware UART
0x4160_0028
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABLIE
ABUP
ABE
ABT
reserved
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 17-14. LCR Bit Definitions (Sheet 1 of 2)
Physical Address
Line Control Register (LCR) PXA255 Processor Hardware UART
0x4160_000C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STKYP
DLAB
WLS
PEN
STB
EPS
SB
reserved
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0
STKYP
DLAB
WLS
PEN
STB
EPS
SB
reserved
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0
In non-FIFO mode, LSR[4:2] show the parity error, framing error, break interrupt, and show the
error status of the character that has just been received.
In FIFO mode, LSR[4:2] show the status bits of the character that is currently at the front of the
FIFO.
LSR[4:1] produce a receiver line status interrupt when the corresponding conditions are detected
and the interrupt is enabled. In FIFO mode, the receiver line status interrupt only occurs when the
erroneous character reaches the front of the FIFO. If the erroneous character is not at the front of
the FIFO, a line status interrupt is generated after the other characters are read and the erroneous
character becomes the character at the front of the FIFO.
The LSR must be read before the erroneous character is read. LSR[4:1] bits are set until software
reads the LSR.
See Section 17.4.2.3 for details on using the DMA to receive data.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOE
TDRQ
TEMT
DR
OE
PE
FE
reserved
BI
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 1 1 0 0 0 0 0
FIFOE
TDRQ
TEMT
DR
OE
PE
FE
reserved
BI
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 1 1 0 0 0 0 0
Bits Name Description
FRAMING ERROR
FE indicates that the received character did not have a valid stop bit. FE is set when the bit
following the last data bit or parity bit is detected as 0. If the LCR had been set for two stop
bit mode, the receiver does not check for a valid second stop bit. The FE indicator is reset
when the processor reads the LSR. The UART re-synchronizes after a framing error. To do
3 FE
this it assumes that the framing error was due to the next start bit, so it samples this “start”
bit twice and then reads in the “data”. In FIFO mode, FE shows a framing error for the
character at the front of the FIFO, not for the most recently received character.
0 = No framing error
1 = Invalid stop bit has been detected
PARITY ERROR
Indicates that the received data character does not have the correct even or odd parity, as
selected by the even parity select bit. PE is set when a parity error is detected and is
2 PE cleared when the processor reads the LSR. In FIFO mode, PE shows a parity error for the
character at the front of the FIFO, not the most recently received character.
0 = No parity error
1 = Parity error has occurred
OVERRUN ERROR
In non-FIFO mode, OE indicates that data in the Receive Buffer register was not read by the
processor before the next character was received. The new character is lost. In FIFO mode,
OE indicates that all 64 bytes of the FIFO are full and the most recently received byte has
1 OE
been discarded. The OE indicator is set when an overrun condition is detected and cleared
when the processor reads the LSR.
0 = No data has been lost
1 = Received data has been lost
DATA READY
DR is set when a complete incoming character has been received and transferred into the
Receive Buffer register or the FIFO. In non-FIFO mode, DR is cleared when the receive
0 DR buffer is read. In FIFO mode, DR is cleared if the FIFO is empty (last character has been
read from Receive Buffer register) or the FIFO is reset with FCR[RESETRF].
0 = No data has been received
1 = Data is available in RBR or the FIFO
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
reserved
LOOP
OUT2
AFE
RTS
reserved
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 ? 0 ?
reserved
reserved
LOOP
OUT2
AFE
RTS
reserved
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 ? 0 ?
The status of the modem control lines do not affect the FIFOs. To use these lines for flow control,
IER[MIE] must be set. When an interrupt on one of the flow control pins occurs, the interrupt
service routine must disable the UART. The UART continues transmission and reception of the
current character and then stops. The contents of the FIFOs is preserved. If the UART is re-
enabled, transmission continues where it stopped.
Note: When bit 0, 1, 2, or 3 is set, a modem status interrupt is generated if IER[MIE] is set.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved
DCTS
CTS
reserved
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 ? ? ? 0
Bits Name Description
31:5 — reserved
reserved
DCTS
CTS
reserved
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 ? ? ? 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved SCR
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0
This is a read/write register. Ignore reads to reserved bits. Write zeros to reserved bits.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCVEIR
XMODE
XMITIR
RXPL
TXPL
reserved
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0