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Microinstructions are stored in control memory in groups, with each group
specifying a routine. Each computer instruction has its own microprogram routine in
control memory to generate the microoperations that execute the instruction. The
hardware that controls the address sequencing of the control memory must be capable
of sequencing the microinstructions within a routine and be able to branch from one
routine to another.
An initial address is loaded into the control address register when power is turned
on in the computer. This address is usually the address of the first
microinstruction that activates the instruction fetch routine. At the end of the
fetch routine, the instruction is in the instruction register of the computer.
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The control memory next must go through the routine that determines the
effective address of the operand. A machine instruction may have bits that specify
various addressing modes, such as indirect address and index registers. The
effective address computation routine in control memory can be reached through a
branch microinstruction, which is conditioned on the status of the mode bits of the
instruction. When the effective address computation routine is completed, the
address of the operand is available in the memory address register.
The next step is to generate the microoperations that execute the instruction
fetched from memory. The microoperation steps to be generated in processor
registers depend on the operation code part of the instruction. Each instruction
has its own microprogram routine stored in a given location of control memory. The
transformation from the instruction code bits to an address in control memory where
the routine is located is referred to as a mapping process.
A mapping procedure is a rule that transforms the instruction code into a control
memory address. Once the required routine is reached, the microinstructions that
execute the instruction may be sequenced by incrementing the control address
register. Microprograms that employ subroutines will require an external register
for storing the return address.
When the execution of the instruction is completed, control must return to the
fetch routine. This is accomplished by executing an unconditional branch
microinstruction to the first address of the fetch routine. In summary, the address
sequencing capabilities required in a control memory are:
• Incrementing of the control address register.
• Unconditional branch or conditional branch, depending on status bit conditions.
• A mapping process from the bits of the instruction to an address for control
memory.
• A facility for subroutine call and return.
Following shows a block diagram of a control memory and the associated hardware
needed for selecting the next microinstruction address.
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The microinstruction in control memory contains a set of bits to initiate

microoperations in computer registers and other bits to specify the method by which
the next address is obtained. The diagram shows four different paths from which the
control address register (CAR) receives the address. The incrementer increments the
content of the control address register by one, to select the next microinstruction
in sequence. Branching is achieved by specifying the branch address in one of the
fields of the microinstruction. Conditional branching is obtained by using part of
the microinstruction to select a specific status bit in order to determine its
condition. An external address is transferred into control memory via a mapping
logic circuit. The return address for a subroutine is stored in a special register
whose value is then used when the microprogram wishes to return from the
subroutine.
Conditional Branching : The status conditions are special bits in the system that
provide parameter information such as the carry-out of an adder, the sign bit of a
number, the mode bits of an instruction, and input or output status conditions.
Information in these bits can be tested and actions initiated based on their
condition: whether their value is 1 or 0.
The branch logic hardware may be implemented in a variety of ways. The simplest way
is to test the specified condition and branch to the indicated address if the
condition is met; otherwise, the address register is incremented. This can be
implemented with a multiplexer.
An unconditional branch microinstruction can be implemented by loading the branch
address from control memory into the control address register. This can be
accomplished by fixing the value of one status bit at the input of the multiplexer,
so it is always equal to 1. A reference to this bit by the status bit select lines
from control memory causes the branch address to be loaded into the control address
register unconditionally. Mapping of Instruction : A special type of branch exists
when a microinstruction specifies a branch to the first word in control memory. The
status bits for this type of branch are the bits in the operation code part of the
instruction. For example, a computer with a simple instruction format as shown in
below diagram has an operation code of four bits which can specify up to 16
distinct instructions.
Assume further that the control memory has 128 words, requiring an address of seven
bits. For each operation code there exists a microprogram routine in control memory
that executes the instruction. One simple mapping process that converts the 4-bit
operation code to a 7-bit address for control memory is shown in above diagram.
This mapping consists of placing a 0 in the most significant bit of the address,
transferring the four operation code bits, and clearing the two least significant
bits of the control address register. If the routine needs more than four
microinstructions, it can use addresses 1000000 through 1111111.
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Microinstructions are stored in control memory in groups, with each group

The microinstruction in control memory contains a set of bits to initiate

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